diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h new file mode 100644 index 0000000..6863438 --- /dev/null +++ b/plat/rpi/common/include/rpi_shared.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RPI_SHARED_H +#define RPI_SHARED_H + +#include + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ + +/* Utility functions */ +void rpi3_console_init(void); +void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, + uintptr_t code_start, uintptr_t code_limit, + uintptr_t rodata_start, uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, uintptr_t coh_limit +#endif + ); + +/* Optional functions required in the Raspberry Pi 3 port */ +unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); + +/* BL2 utility functions */ +uint32_t rpi3_get_spsr_for_bl32_entry(void); +uint32_t rpi3_get_spsr_for_bl33_entry(void); + +/* IO storage utility functions */ +void plat_rpi3_io_setup(void); + +/* VideoCore firmware commands */ +int rpi3_vc_hardware_get_board_revision(uint32_t *revision); + +#endif /* RPI3_PRIVATE_H */ diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c new file mode 100644 index 0000000..ab63d98 --- /dev/null +++ b/plat/rpi/common/rpi3_common.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef SHARED_RAM_BASE +#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ + SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef RPI3_PRELOADED_DTB_BASE +#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ + MT_MEMORY | MT_RW | MT_NS) +#endif + +#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \ + PLAT_RPI3_FIP_MAX_SIZE, \ + MT_MEMORY | MT_RO | MT_NS) + +#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#ifdef SPD_opteed +#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ + RPI3_OPTEE_PAGEABLE_LOAD_BASE, \ + RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + +/* + * Table of regions for various BL stages to map using the MMU. + */ +#ifdef IMAGE_BL1 +static const mmap_region_t plat_rpi3_mmap[] = { +#ifdef MAP_SHARED_RAM + MAP_SHARED_RAM, +#endif + MAP_DEVICE0, + MAP_FIP, +#ifdef SPD_opteed + MAP_OPTEE_PAGEABLE, +#endif + {0} +}; +#endif + +#ifdef IMAGE_BL2 +static const mmap_region_t plat_rpi3_mmap[] = { +#ifdef MAP_SHARED_RAM + MAP_SHARED_RAM, +#endif + MAP_DEVICE0, + MAP_FIP, + MAP_NS_DRAM0, +#ifdef BL32_BASE + MAP_BL32_MEM, +#endif + {0} +}; +#endif + +#ifdef IMAGE_BL31 +static const mmap_region_t plat_rpi3_mmap[] = { +#ifdef MAP_SHARED_RAM + MAP_SHARED_RAM, +#endif + MAP_DEVICE0, +#ifdef RPI3_PRELOADED_DTB_BASE + MAP_NS_DTB, +#endif +#ifdef BL32_BASE + MAP_BL32_MEM, +#endif + {0} +}; +#endif + +/******************************************************************************* + * Function that sets up the console + ******************************************************************************/ +static console_16550_t rpi3_console; + +void rpi3_console_init(void) +{ + int console_scope = CONSOLE_FLAG_BOOT; +#if RPI3_RUNTIME_UART != -1 + console_scope |= CONSOLE_FLAG_RUNTIME; +#endif + int rc = console_16550_register(PLAT_RPI3_UART_BASE, + PLAT_RPI3_UART_CLK_IN_HZ, + PLAT_RPI3_UART_BAUDRATE, + &rpi3_console); + if (rc == 0) { + /* + * The crash console doesn't use the multi console API, it uses + * the core console functions directly. It is safe to call panic + * and let it print debug information. + */ + panic(); + } + + console_set_scope(&rpi3_console.console, console_scope); +} + +/******************************************************************************* + * Function that sets up the translation tables. + ******************************************************************************/ +void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, + uintptr_t code_start, uintptr_t code_limit, + uintptr_t rodata_start, uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, uintptr_t coh_limit +#endif + ) +{ + /* + * Map the Trusted SRAM with appropriate memory attributes. + * Subsequent mappings will adjust the attributes for specific regions. + */ + VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", + (void *) total_base, (void *) (total_base + total_size)); + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + + /* Re-map the code section */ + VERBOSE("Code region: %p - %p\n", + (void *) code_start, (void *) code_limit); + mmap_add_region(code_start, code_start, + code_limit - code_start, + MT_CODE | MT_SECURE); + + /* Re-map the read-only data section */ + VERBOSE("Read-only data region: %p - %p\n", + (void *) rodata_start, (void *) rodata_limit); + mmap_add_region(rodata_start, rodata_start, + rodata_limit - rodata_start, + MT_RO_DATA | MT_SECURE); + +#if USE_COHERENT_MEM + /* Re-map the coherent memory region */ + VERBOSE("Coherent region: %p - %p\n", + (void *) coh_start, (void *) coh_limit); + mmap_add_region(coh_start, coh_start, + coh_limit - coh_start, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + mmap_add(plat_rpi3_mmap); + + init_xlat_tables(); +} + +/******************************************************************************* + * Return entrypoint of BL33. + ******************************************************************************/ +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return PLAT_RPI3_NS_IMAGE_OFFSET; +#endif +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t rpi3_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +uint32_t rpi3_get_spsr_for_bl33_entry(void) +{ +#if RPI3_BL33_IN_AARCH32 + INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n"); + return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE, + DISABLE_ALL_EXCEPTIONS); +#else + return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#endif +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + ERROR("rpi3: Interrupt routed to EL3.\n"); + return INTR_TYPE_INVAL; +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) +{ + assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || + (type == INTR_TYPE_NS)); + + assert(sec_state_is_valid(security_state)); + + /* Non-secure interrupts are signalled on the IRQ line always. */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* Secure interrupts are signalled on the FIQ line always. */ + return __builtin_ctz(SCR_FIQ_BIT); +} diff --git a/plat/rpi/common/rpi3_image_load.c b/plat/rpi/common/rpi3_image_load.c new file mode 100644 index 0000000..5394c6f --- /dev/null +++ b/plat/rpi/common/rpi3_image_load.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include +#include + +/******************************************************************************* + * This function flushes the data structures so that they are visible + * in memory for the next BL image. + ******************************************************************************/ +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +/******************************************************************************* + * This function returns the list of loadable images. + ******************************************************************************/ +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +/******************************************************************************* + * This function returns the list of executable images. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/plat/rpi/common/rpi3_io_storage.c b/plat/rpi/common/rpi3_io_storage.c new file mode 100644 index 0000000..49c6a76 --- /dev/null +++ b/plat/rpi/common/rpi3_io_storage.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +/* Semihosting filenames */ +#define BL2_IMAGE_NAME "bl2.bin" +#define BL31_IMAGE_NAME "bl31.bin" +#define BL32_IMAGE_NAME "bl32.bin" +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" +#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" +#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" +#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" +#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" +#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" +#endif /* TRUSTED_BOARD_BOOT */ + +/* IO devices */ +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = PLAT_RPI3_FIP_BASE, + .length = PLAT_RPI3_FIP_MAX_SIZE +}; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl32_extra1_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, +}; + +static const io_uuid_spec_t bl32_extra2_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t tb_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_cert_uuid_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t tos_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +static int open_fip(const uintptr_t spec); +static int open_memmap(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +/* By default, load images from the FIP */ +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL32_EXTRA1_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra1_uuid_spec, + open_fip + }, + [BL32_EXTRA2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_extra2_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_rpi3_io_setup(void) +{ + int io_result; + + io_result = register_io_dev_fip(&fip_dev_con); + assert(io_result == 0); + + io_result = register_io_dev_memmap(&memmap_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(io_result == 0); + + io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(io_result == 0); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +/* + * Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy + */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == 0) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } + + return result; +} diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c new file mode 100644 index 0000000..8c2d070 --- /dev/null +++ b/plat/rpi/common/rpi3_pm.c @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#ifdef RPI_HAVE_GIC +#include +#endif + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#else + +#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) + +#endif /* PSCI_EXTENDED_STATE_ID */ + +#define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ + rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +static const unsigned int rpi3_pm_idle_states[] = { + /* State-id - 0x01 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, + MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; + +/******************************************************************************* + * Platform handler called to check the validity of the power state + * parameter. The power state parameter has to be a composite power state. + ******************************************************************************/ +static int rpi3_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state != 0); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; rpi3_pm_idle_states[i] != 0; i++) { + if (power_state == rpi3_pm_idle_states[i]) { + break; + } + } + + /* Return error if entry not found in the idle state array */ + if (!rpi3_pm_idle_states[i]) { + return PSCI_E_INVALID_PARAMS; + } + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + PLAT_LOCAL_PSTATE_MASK; + state_id >>= PLAT_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called when a CPU is about to enter standby. + ******************************************************************************/ +static void rpi3_cpu_standby(plat_local_state_t cpu_state) +{ + assert(cpu_state == PLAT_LOCAL_STATE_RET); + + /* + * Enter standby state. + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +static void rpi3_pwr_domain_off(const psci_power_state_t *target_state) +{ +#ifdef RPI_HAVE_GIC + gicv2_cpuif_disable(); +#endif +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int rpi3_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned int pos = plat_core_pos_by_mpidr(mpidr); + uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; + + assert(pos < PLATFORM_CORE_COUNT); + + hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO; + + /* Make sure that the write has completed */ + dsb(); + isb(); + + sev(); + + return rc; +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + +#ifdef RPI_HAVE_GIC + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +#endif +} + +/******************************************************************************* + * Platform handlers for system reset and system off. + ******************************************************************************/ + +/* 10 ticks (Watchdog timer = Timer clock / 16) */ +#define RESET_TIMEOUT U(10) + +static void __dead2 rpi3_watchdog_reset(void) +{ + uint32_t rstc; + + console_flush(); + + dsbsy(); + isb(); + + mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, + RPI3_PM_PASSWORD | RESET_TIMEOUT); + + rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); + rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; + rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); + + for (;;) { + wfi(); + } +} + +static void __dead2 rpi3_system_reset(void) +{ + INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); + + rpi3_watchdog_reset(); +} + +static void __dead2 rpi3_system_off(void) +{ + uint32_t rsts; + + INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); + + /* + * This function doesn't actually make the Raspberry Pi turn itself off, + * the hardware doesn't allow it. It simply reboots it and the RSTS + * value tells the bootcode.bin firmware not to continue the regular + * bootflow and to stay in a low power mode. + */ + + rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); + rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; + mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); + + rpi3_watchdog_reset(); +} + +/******************************************************************************* + * Platform handlers and setup function. + ******************************************************************************/ +static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { + .cpu_standby = rpi3_cpu_standby, + .pwr_domain_off = rpi3_pwr_domain_off, + .pwr_domain_on = rpi3_pwr_domain_on, + .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, + .system_off = rpi3_system_off, + .system_reset = rpi3_system_reset, + .validate_power_state = rpi3_validate_power_state, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT; + + *entrypoint = sec_entrypoint; + *psci_ops = &plat_rpi3_psci_pm_ops; + + return 0; +} diff --git a/plat/rpi/common/rpi3_rotpk.S b/plat/rpi/common/rpi3_rotpk.S new file mode 100644 index 0000000..1c17b21 --- /dev/null +++ b/plat/rpi/common/rpi3_rotpk.S @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .global rpi3_rotpk_hash + .global rpi3_rotpk_hash_end +rpi3_rotpk_hash: + /* DER header */ + .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 + .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 + /* SHA256 */ + .incbin ROTPK_HASH +rpi3_rotpk_hash_end: diff --git a/plat/rpi/common/rpi3_stack_protector.c b/plat/rpi/common/rpi3_stack_protector.c new file mode 100644 index 0000000..aae5fac --- /dev/null +++ b/plat/rpi/common/rpi3_stack_protector.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include +#include + +#include + +/* Get 128 bits of entropy and fuse the values together to form the canary. */ +#define TRNG_NBYTES 16U + +u_register_t plat_get_stack_protector_canary(void) +{ + size_t i; + u_register_t buf[TRNG_NBYTES / sizeof(u_register_t)]; + u_register_t ret = 0U; + + rpi3_rng_read(buf, sizeof(buf)); + + for (i = 0U; i < ARRAY_SIZE(buf); i++) + ret ^= buf[i]; + + return ret; +} diff --git a/plat/rpi/common/rpi3_topology.c b/plat/rpi/common/rpi3_topology.c new file mode 100644 index 0000000..3747287 --- /dev/null +++ b/plat/rpi/common/rpi3_topology.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +#include + +#include + +#include + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { + return -1; + } + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) { + return -1; + } + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { + return -1; + } + + return plat_rpi3_calc_core_pos(mpidr); +} diff --git a/plat/rpi/common/rpi3_trusted_boot.c b/plat/rpi/common/rpi3_trusted_boot.c new file mode 100644 index 0000000..f6c669f --- /dev/null +++ b/plat/rpi/common/rpi3_trusted_boot.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include + +extern char rpi3_rotpk_hash[], rpi3_rotpk_hash_end[]; + +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + *key_ptr = rpi3_rotpk_hash; + *key_len = rpi3_rotpk_hash_end - rpi3_rotpk_hash; + *flags = ROTPK_IS_HASH; + + return 0; +} + +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + *nv_ctr = 0; + + return 0; +} + +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} + +int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) +{ + return get_mbedtls_heap_helper(heap_addr, heap_size); +} diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S index 556d872..24278bd 100644 --- a/plat/rpi/rpi3/aarch64/plat_helpers.S +++ b/plat/rpi/rpi3/aarch64/plat_helpers.S @@ -18,7 +18,6 @@ .globl plat_get_my_entrypoint .globl plat_is_my_cpu_primary .globl plat_my_core_pos - .globl plat_reset_handler .globl plat_rpi3_calc_core_pos .globl plat_secondary_cold_boot_setup @@ -164,16 +163,3 @@ mov_imm x0, PLAT_RPI3_UART_BASE b console_16550_core_flush endfunc plat_crash_console_flush - - /* --------------------------------------------- - * void plat_reset_handler(void); - * --------------------------------------------- - */ -func plat_reset_handler - /* use the 19.2 MHz clock for the architected timer */ - mov x0, #RPI3_INTC_BASE_ADDRESS - mov w1, #0x80000000 - str wzr, [x0, #RPI3_INTC_CONTROL_OFFSET] - str w1, [x0, #RPI3_INTC_PRESCALER_OFFSET] - ret -endfunc plat_reset_handler diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h index 2a12fe7..e308f70 100644 --- a/plat/rpi/rpi3/include/platform_def.h +++ b/plat/rpi/rpi3/include/platform_def.h @@ -110,8 +110,8 @@ /* * I/O registers. */ -#define DEVICE0_BASE RPI3_IO_BASE -#define DEVICE0_SIZE RPI3_IO_SIZE +#define DEVICE0_BASE RPI_IO_BASE +#define DEVICE0_SIZE RPI_IO_SIZE /* * Arm TF lives in SRAM, partition it here diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h index 7a3ea57..01d5b4a 100644 --- a/plat/rpi/rpi3/include/rpi_hw.h +++ b/plat/rpi/rpi3/include/rpi_hw.h @@ -13,14 +13,14 @@ * Peripherals */ -#define RPI3_IO_BASE ULL(0x3F000000) -#define RPI3_IO_SIZE ULL(0x01000000) +#define RPI_IO_BASE ULL(0x3F000000) +#define RPI_IO_SIZE ULL(0x01000000) /* * ARM <-> VideoCore mailboxes */ #define RPI3_MBOX_OFFSET ULL(0x0000B880) -#define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) +#define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET) /* VideoCore -> ARM */ #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) @@ -41,7 +41,7 @@ * Power management, reset controller, watchdog. */ #define RPI3_IO_PM_OFFSET ULL(0x00100000) -#define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) +#define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET) /* Registers on top of RPI3_PM_BASE. */ #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) #define RPI3_PM_RSTS_OFFSET ULL(0x00000020) @@ -62,7 +62,7 @@ * Hardware random number generator. */ #define RPI3_IO_RNG_OFFSET ULL(0x00104000) -#define RPI3_RNG_BASE (RPI3_IO_BASE + RPI3_IO_RNG_OFFSET) +#define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET) #define RPI3_RNG_CTRL_OFFSET ULL(0x00000000) #define RPI3_RNG_STATUS_OFFSET ULL(0x00000004) #define RPI3_RNG_DATA_OFFSET ULL(0x00000008) @@ -80,20 +80,20 @@ * Serial port (called 'Mini UART' in the BCM docucmentation). */ #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) -#define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) +#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET) #define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) /* * GPIO controller */ #define RPI3_IO_GPIO_OFFSET ULL(0x00200000) -#define RPI3_GPIO_BASE (RPI3_IO_BASE + RPI3_IO_GPIO_OFFSET) +#define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET) /* * SDHost controller */ #define RPI3_IO_SDHOST_OFFSET ULL(0x00202000) -#define RPI3_SDHOST_BASE (RPI3_IO_BASE + RPI3_IO_SDHOST_OFFSET) +#define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET) /* * Local interrupt controller diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk index 21a880c..a21a770 100644 --- a/plat/rpi/rpi3/platform.mk +++ b/plat/rpi/rpi3/platform.mk @@ -7,10 +7,11 @@ include lib/libfdt/libfdt.mk include lib/xlat_tables_v2/xlat_tables.mk -PLAT_INCLUDES := -Iplat/rpi/rpi3/include +PLAT_INCLUDES := -Iplat/rpi/common/include \ + -Iplat/rpi/rpi3/include PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \ - plat/rpi/rpi3/rpi3_common.c \ + plat/rpi/common/rpi3_common.c \ ${XLAT_TABLES_LIB_SRCS} BL1_SOURCES += drivers/io/io_fip.c \ @@ -20,7 +21,7 @@ plat/common/aarch64/platform_mp_stack.S \ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/rpi3_bl1_setup.c \ - plat/rpi/rpi3/rpi3_io_storage.c \ + plat/rpi/common/rpi3_io_storage.c \ drivers/rpi3/mailbox/rpi3_mbox.c \ plat/rpi/rpi3/rpi_mbox_board.c @@ -39,15 +40,15 @@ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \ plat/rpi/rpi3/rpi3_bl2_setup.c \ - plat/rpi/rpi3/rpi3_image_load.c \ - plat/rpi/rpi3/rpi3_io_storage.c + plat/rpi/common/rpi3_image_load.c \ + plat/rpi/common/rpi3_io_storage.c BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_psci_common.c \ plat/rpi/rpi3/aarch64/plat_helpers.S \ plat/rpi/rpi3/rpi3_bl31_setup.c \ - plat/rpi/rpi3/rpi3_pm.c \ - plat/rpi/rpi3/rpi3_topology.c \ + plat/rpi/common/rpi3_pm.c \ + plat/rpi/common/rpi3_topology.c \ ${LIBFDT_SRCS} # Tune compiler for Cortex-A53 @@ -160,7 +161,7 @@ ifneq ($(ENABLE_STACK_PROTECTOR), 0) PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \ - plat/rpi/rpi3/rpi3_stack_protector.c + plat/rpi/common/rpi3_stack_protector.c endif ifeq (${SPD},opteed) @@ -190,13 +191,13 @@ BL1_SOURCES += ${AUTH_SOURCES} \ bl1/tbbr/tbbr_img_desc.c \ plat/common/tbbr/plat_tbbr.c \ - plat/rpi/rpi3/rpi3_trusted_boot.c \ - plat/rpi/rpi3/rpi3_rotpk.S + plat/rpi/common/rpi3_trusted_boot.c \ + plat/rpi/common/rpi3_rotpk.S BL2_SOURCES += ${AUTH_SOURCES} \ plat/common/tbbr/plat_tbbr.c \ - plat/rpi/rpi3/rpi3_trusted_boot.c \ - plat/rpi/rpi3/rpi3_rotpk.S + plat/rpi/common/rpi3_trusted_boot.c \ + plat/rpi/common/rpi3_rotpk.S ROT_KEY = $(BUILD_PLAT)/rot_key.pem ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c index b869e9d..3ac30e0 100644 --- a/plat/rpi/rpi3/rpi3_bl1_setup.c +++ b/plat/rpi/rpi3/rpi3_bl1_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,10 +10,11 @@ #include #include #include +#include #include #include -#include "rpi3_private.h" +#include /* Data structure which holds the extents of the trusted SRAM for BL1 */ static meminfo_t bl1_tzram_layout; @@ -28,6 +29,11 @@ ******************************************************************************/ void bl1_early_platform_setup(void) { + /* use the 19.2 MHz clock for the architected timer */ + mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_CONTROL_OFFSET, 0); + mmio_write_32(RPI3_INTC_BASE_ADDRESS + RPI3_INTC_PRESCALER_OFFSET, + 0x80000000); + /* Initialize the console to provide early debug support */ rpi3_console_init(); diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c index b5e5835..991c0fc 100644 --- a/plat/rpi/rpi3/rpi3_bl2_setup.c +++ b/plat/rpi/rpi3/rpi3_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,7 @@ #include #include -#include "rpi3_private.h" +#include /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c index 2f1bc64..a9efc52 100644 --- a/plat/rpi/rpi3/rpi3_bl31_setup.c +++ b/plat/rpi/rpi3/rpi3_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,7 +15,7 @@ #include #include -#include "rpi3_private.h" +#include /* * Placeholder variables for copying the arguments that have been passed to diff --git a/plat/rpi/rpi3/rpi3_common.c b/plat/rpi/rpi3/rpi3_common.c deleted file mode 100644 index 85a26c2..0000000 --- a/plat/rpi/rpi3/rpi3_common.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include "rpi3_private.h" - -#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ - DEVICE0_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ - SHARED_RAM_SIZE, \ - MT_DEVICE | MT_RW | MT_SECURE) - -#ifdef RPI3_PRELOADED_DTB_BASE -#define MAP_NS_DTB MAP_REGION_FLAT(RPI3_PRELOADED_DTB_BASE, 0x10000, \ - MT_MEMORY | MT_RW | MT_NS) -#endif - -#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ - MT_MEMORY | MT_RW | MT_NS) - -#define MAP_FIP MAP_REGION_FLAT(PLAT_RPI3_FIP_BASE, \ - PLAT_RPI3_FIP_MAX_SIZE, \ - MT_MEMORY | MT_RO | MT_NS) - -#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) - -#ifdef SPD_opteed -#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \ - RPI3_OPTEE_PAGEABLE_LOAD_BASE, \ - RPI3_OPTEE_PAGEABLE_LOAD_SIZE, \ - MT_MEMORY | MT_RW | MT_SECURE) -#endif - -/* - * Table of regions for various BL stages to map using the MMU. - */ -#ifdef IMAGE_BL1 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, - MAP_FIP, -#ifdef SPD_opteed - MAP_OPTEE_PAGEABLE, -#endif - {0} -}; -#endif - -#ifdef IMAGE_BL2 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, - MAP_FIP, - MAP_NS_DRAM0, -#ifdef BL32_BASE - MAP_BL32_MEM, -#endif - {0} -}; -#endif - -#ifdef IMAGE_BL31 -static const mmap_region_t plat_rpi3_mmap[] = { - MAP_SHARED_RAM, - MAP_DEVICE0, -#ifdef RPI3_PRELOADED_DTB_BASE - MAP_NS_DTB, -#endif -#ifdef BL32_BASE - MAP_BL32_MEM, -#endif - {0} -}; -#endif - -/******************************************************************************* - * Function that sets up the console - ******************************************************************************/ -static console_16550_t rpi3_console; - -void rpi3_console_init(void) -{ - int console_scope = CONSOLE_FLAG_BOOT; -#if RPI3_RUNTIME_UART != -1 - console_scope |= CONSOLE_FLAG_RUNTIME; -#endif - int rc = console_16550_register(PLAT_RPI3_UART_BASE, - PLAT_RPI3_UART_CLK_IN_HZ, - PLAT_RPI3_UART_BAUDRATE, - &rpi3_console); - if (rc == 0) { - /* - * The crash console doesn't use the multi console API, it uses - * the core console functions directly. It is safe to call panic - * and let it print debug information. - */ - panic(); - } - - console_set_scope(&rpi3_console.console, console_scope); -} - -/******************************************************************************* - * Function that sets up the translation tables. - ******************************************************************************/ -void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, - uintptr_t code_start, uintptr_t code_limit, - uintptr_t rodata_start, uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, uintptr_t coh_limit -#endif - ) -{ - /* - * Map the Trusted SRAM with appropriate memory attributes. - * Subsequent mappings will adjust the attributes for specific regions. - */ - VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", - (void *) total_base, (void *) (total_base + total_size)); - mmap_add_region(total_base, total_base, - total_size, - MT_MEMORY | MT_RW | MT_SECURE); - - /* Re-map the code section */ - VERBOSE("Code region: %p - %p\n", - (void *) code_start, (void *) code_limit); - mmap_add_region(code_start, code_start, - code_limit - code_start, - MT_CODE | MT_SECURE); - - /* Re-map the read-only data section */ - VERBOSE("Read-only data region: %p - %p\n", - (void *) rodata_start, (void *) rodata_limit); - mmap_add_region(rodata_start, rodata_start, - rodata_limit - rodata_start, - MT_RO_DATA | MT_SECURE); - -#if USE_COHERENT_MEM - /* Re-map the coherent memory region */ - VERBOSE("Coherent region: %p - %p\n", - (void *) coh_start, (void *) coh_limit); - mmap_add_region(coh_start, coh_start, - coh_limit - coh_start, - MT_DEVICE | MT_RW | MT_SECURE); -#endif - - mmap_add(plat_rpi3_mmap); - - init_xlat_tables(); -} - -/******************************************************************************* - * Return entrypoint of BL33. - ******************************************************************************/ -uintptr_t plat_get_ns_image_entrypoint(void) -{ -#ifdef PRELOADED_BL33_BASE - return PRELOADED_BL33_BASE; -#else - return PLAT_RPI3_NS_IMAGE_OFFSET; -#endif -} - -/******************************************************************************* - * Gets SPSR for BL32 entry - ******************************************************************************/ -uint32_t rpi3_get_spsr_for_bl32_entry(void) -{ - /* - * The Secure Payload Dispatcher service is responsible for - * setting the SPSR prior to entry into the BL32 image. - */ - return 0; -} - -/******************************************************************************* - * Gets SPSR for BL33 entry - ******************************************************************************/ -uint32_t rpi3_get_spsr_for_bl33_entry(void) -{ -#if RPI3_BL33_IN_AARCH32 - INFO("BL33 will boot in Non-secure AArch32 Hypervisor mode\n"); - return SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, SPSR_E_LITTLE, - DISABLE_ALL_EXCEPTIONS); -#else - return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); -#endif -} - -unsigned int plat_get_syscnt_freq2(void) -{ - return SYS_COUNTER_FREQ_IN_TICKS; -} - -uint32_t plat_ic_get_pending_interrupt_type(void) -{ - ERROR("rpi3: Interrupt routed to EL3.\n"); - return INTR_TYPE_INVAL; -} - -uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) -{ - assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || - (type == INTR_TYPE_NS)); - - assert(sec_state_is_valid(security_state)); - - /* Non-secure interrupts are signalled on the IRQ line always. */ - if (type == INTR_TYPE_NS) - return __builtin_ctz(SCR_IRQ_BIT); - - /* Secure interrupts are signalled on the FIQ line always. */ - return __builtin_ctz(SCR_FIQ_BIT); -} diff --git a/plat/rpi/rpi3/rpi3_image_load.c b/plat/rpi/rpi3/rpi3_image_load.c deleted file mode 100644 index 5394c6f..0000000 --- a/plat/rpi/rpi3/rpi3_image_load.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include -#include - -/******************************************************************************* - * This function flushes the data structures so that they are visible - * in memory for the next BL image. - ******************************************************************************/ -void plat_flush_next_bl_params(void) -{ - flush_bl_params_desc(); -} - -/******************************************************************************* - * This function returns the list of loadable images. - ******************************************************************************/ -bl_load_info_t *plat_get_bl_image_load_info(void) -{ - return get_bl_load_info_from_mem_params_desc(); -} - -/******************************************************************************* - * This function returns the list of executable images. - ******************************************************************************/ -bl_params_t *plat_get_next_bl_params(void) -{ - return get_next_bl_params_from_mem_params_desc(); -} diff --git a/plat/rpi/rpi3/rpi3_io_storage.c b/plat/rpi/rpi3/rpi3_io_storage.c deleted file mode 100644 index 49c6a76..0000000 --- a/plat/rpi/rpi3/rpi3_io_storage.c +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include - -/* Semihosting filenames */ -#define BL2_IMAGE_NAME "bl2.bin" -#define BL31_IMAGE_NAME "bl31.bin" -#define BL32_IMAGE_NAME "bl32.bin" -#define BL33_IMAGE_NAME "bl33.bin" - -#if TRUSTED_BOARD_BOOT -#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" -#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" -#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" -#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" -#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" -#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" -#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" -#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" -#endif /* TRUSTED_BOARD_BOOT */ - -/* IO devices */ -static const io_dev_connector_t *fip_dev_con; -static uintptr_t fip_dev_handle; -static const io_dev_connector_t *memmap_dev_con; -static uintptr_t memmap_dev_handle; - -static const io_block_spec_t fip_block_spec = { - .offset = PLAT_RPI3_FIP_BASE, - .length = PLAT_RPI3_FIP_MAX_SIZE -}; - -static const io_uuid_spec_t bl2_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, -}; - -static const io_uuid_spec_t bl31_uuid_spec = { - .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, -}; - -static const io_uuid_spec_t bl32_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32, -}; - -static const io_uuid_spec_t bl32_extra1_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1, -}; - -static const io_uuid_spec_t bl32_extra2_uuid_spec = { - .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2, -}; - -static const io_uuid_spec_t bl33_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, -}; - -#if TRUSTED_BOARD_BOOT -static const io_uuid_spec_t tb_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_BOOT_FW_CERT, -}; - -static const io_uuid_spec_t trusted_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { - .uuid = UUID_SOC_FW_KEY_CERT, -}; - -static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, -}; - -static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, -}; - -static const io_uuid_spec_t soc_fw_cert_uuid_spec = { - .uuid = UUID_SOC_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t tos_fw_cert_uuid_spec = { - .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, -}; - -static const io_uuid_spec_t nt_fw_cert_uuid_spec = { - .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, -}; -#endif /* TRUSTED_BOARD_BOOT */ - -static int open_fip(const uintptr_t spec); -static int open_memmap(const uintptr_t spec); - -struct plat_io_policy { - uintptr_t *dev_handle; - uintptr_t image_spec; - int (*check)(const uintptr_t spec); -}; - -/* By default, load images from the FIP */ -static const struct plat_io_policy policies[] = { - [FIP_IMAGE_ID] = { - &memmap_dev_handle, - (uintptr_t)&fip_block_spec, - open_memmap - }, - [BL2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl2_uuid_spec, - open_fip - }, - [BL31_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl31_uuid_spec, - open_fip - }, - [BL32_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_uuid_spec, - open_fip - }, - [BL32_EXTRA1_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra1_uuid_spec, - open_fip - }, - [BL32_EXTRA2_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl32_extra2_uuid_spec, - open_fip - }, - [BL33_IMAGE_ID] = { - &fip_dev_handle, - (uintptr_t)&bl33_uuid_spec, - open_fip - }, -#if TRUSTED_BOARD_BOOT - [TRUSTED_BOOT_FW_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tb_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&trusted_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_key_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_key_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_KEY_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_key_cert_uuid_spec, - open_fip - }, - [SOC_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&soc_fw_cert_uuid_spec, - open_fip - }, - [TRUSTED_OS_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&tos_fw_cert_uuid_spec, - open_fip - }, - [NON_TRUSTED_FW_CONTENT_CERT_ID] = { - &fip_dev_handle, - (uintptr_t)&nt_fw_cert_uuid_spec, - open_fip - }, -#endif /* TRUSTED_BOARD_BOOT */ -}; - -static int open_fip(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - /* See if a Firmware Image Package is available */ - result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); - if (result == 0) { - result = io_open(fip_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using FIP\n"); - io_close(local_image_handle); - } - } - return result; -} - -static int open_memmap(const uintptr_t spec) -{ - int result; - uintptr_t local_image_handle; - - result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); - if (result == 0) { - result = io_open(memmap_dev_handle, spec, &local_image_handle); - if (result == 0) { - VERBOSE("Using Memmap\n"); - io_close(local_image_handle); - } - } - return result; -} - -void plat_rpi3_io_setup(void) -{ - int io_result; - - io_result = register_io_dev_fip(&fip_dev_con); - assert(io_result == 0); - - io_result = register_io_dev_memmap(&memmap_dev_con); - assert(io_result == 0); - - /* Open connections to devices and cache the handles */ - io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, - &fip_dev_handle); - assert(io_result == 0); - - io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, - &memmap_dev_handle); - assert(io_result == 0); - - /* Ignore improbable errors in release builds */ - (void)io_result; -} - -/* - * Return an IO device handle and specification which can be used to access - * an image. Use this to enforce platform load policy - */ -int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, - uintptr_t *image_spec) -{ - int result; - const struct plat_io_policy *policy; - - assert(image_id < ARRAY_SIZE(policies)); - - policy = &policies[image_id]; - result = policy->check(policy->image_spec); - if (result == 0) { - *image_spec = policy->image_spec; - *dev_handle = *(policy->dev_handle); - } - - return result; -} diff --git a/plat/rpi/rpi3/rpi3_pm.c b/plat/rpi/rpi3/rpi3_pm.c deleted file mode 100644 index b79e273..0000000 --- a/plat/rpi/rpi3/rpi3_pm.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include -#include -#include -#include -#include -#include - -#include - -/* Make composite power state parameter till power level 0 */ -#if PSCI_EXTENDED_STATE_ID - -#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) - -#else - -#define rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ - (((lvl0_state) << PSTATE_ID_SHIFT) | \ - ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ - ((type) << PSTATE_TYPE_SHIFT)) - -#endif /* PSCI_EXTENDED_STATE_ID */ - -#define rpi3_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ - (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ - rpi3_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) - -/* - * The table storing the valid idle power states. Ensure that the - * array entries are populated in ascending order of state-id to - * enable us to use binary search during power state validation. - * The table must be terminated by a NULL entry. - */ -static const unsigned int rpi3_pm_idle_states[] = { - /* State-id - 0x01 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, - MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), - /* State-id - 0x02 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), - /* State-id - 0x22 */ - rpi3_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, - MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), - 0, -}; - -/******************************************************************************* - * Platform handler called to check the validity of the power state - * parameter. The power state parameter has to be a composite power state. - ******************************************************************************/ -static int rpi3_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - unsigned int state_id; - int i; - - assert(req_state != 0); - - /* - * Currently we are using a linear search for finding the matching - * entry in the idle power state array. This can be made a binary - * search if the number of entries justify the additional complexity. - */ - for (i = 0; rpi3_pm_idle_states[i] != 0; i++) { - if (power_state == rpi3_pm_idle_states[i]) { - break; - } - } - - /* Return error if entry not found in the idle state array */ - if (!rpi3_pm_idle_states[i]) { - return PSCI_E_INVALID_PARAMS; - } - - i = 0; - state_id = psci_get_pstate_id(power_state); - - /* Parse the State ID and populate the state info parameter */ - while (state_id) { - req_state->pwr_domain_state[i++] = state_id & - PLAT_LOCAL_PSTATE_MASK; - state_id >>= PLAT_LOCAL_PSTATE_WIDTH; - } - - return PSCI_E_SUCCESS; -} - -/******************************************************************************* - * Platform handler called when a CPU is about to enter standby. - ******************************************************************************/ -static void rpi3_cpu_standby(plat_local_state_t cpu_state) -{ - assert(cpu_state == PLAT_LOCAL_STATE_RET); - - /* - * Enter standby state. - * dsb is good practice before using wfi to enter low power states - */ - dsb(); - wfi(); -} - -/******************************************************************************* - * Platform handler called when a power domain is about to be turned on. The - * mpidr determines the CPU to be turned on. - ******************************************************************************/ -static int rpi3_pwr_domain_on(u_register_t mpidr) -{ - int rc = PSCI_E_SUCCESS; - unsigned int pos = plat_core_pos_by_mpidr(mpidr); - uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE; - - assert(pos < PLATFORM_CORE_COUNT); - - hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO; - - /* Make sure that the write has completed */ - dsb(); - isb(); - - sev(); - - return rc; -} - -/******************************************************************************* - * Platform handler called when a power domain has just been powered on after - * being turned off earlier. The target_state encodes the low power state that - * each level has woken up from. - ******************************************************************************/ -static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == - PLAT_LOCAL_STATE_OFF); -} - -/******************************************************************************* - * Platform handlers for system reset and system off. - ******************************************************************************/ - -/* 10 ticks (Watchdog timer = Timer clock / 16) */ -#define RESET_TIMEOUT U(10) - -static void __dead2 rpi3_watchdog_reset(void) -{ - uint32_t rstc; - - console_flush(); - - dsbsy(); - isb(); - - mmio_write_32(RPI3_PM_BASE + RPI3_PM_WDOG_OFFSET, - RPI3_PM_PASSWORD | RESET_TIMEOUT); - - rstc = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET); - rstc &= ~RPI3_PM_RSTC_WRCFG_MASK; - rstc |= RPI3_PM_PASSWORD | RPI3_PM_RSTC_WRCFG_FULL_RESET; - mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTC_OFFSET, rstc); - - for (;;) { - wfi(); - } -} - -static void __dead2 rpi3_system_reset(void) -{ - INFO("rpi3: PSCI_SYSTEM_RESET: Invoking watchdog reset\n"); - - rpi3_watchdog_reset(); -} - -static void __dead2 rpi3_system_off(void) -{ - uint32_t rsts; - - INFO("rpi3: PSCI_SYSTEM_OFF: Invoking watchdog reset\n"); - - /* - * This function doesn't actually make the Raspberry Pi turn itself off, - * the hardware doesn't allow it. It simply reboots it and the RSTS - * value tells the bootcode.bin firmware not to continue the regular - * bootflow and to stay in a low power mode. - */ - - rsts = mmio_read_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET); - rsts |= RPI3_PM_PASSWORD | RPI3_PM_RSTS_WRCFG_HALT; - mmio_write_32(RPI3_PM_BASE + RPI3_PM_RSTS_OFFSET, rsts); - - rpi3_watchdog_reset(); -} - -/******************************************************************************* - * Platform handlers and setup function. - ******************************************************************************/ -static const plat_psci_ops_t plat_rpi3_psci_pm_ops = { - .cpu_standby = rpi3_cpu_standby, - .pwr_domain_on = rpi3_pwr_domain_on, - .pwr_domain_on_finish = rpi3_pwr_domain_on_finish, - .system_off = rpi3_system_off, - .system_reset = rpi3_system_reset, - .validate_power_state = rpi3_validate_power_state, -}; - -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - uintptr_t *entrypoint = (void *) PLAT_RPI3_TM_ENTRYPOINT; - - *entrypoint = sec_entrypoint; - *psci_ops = &plat_rpi3_psci_pm_ops; - - return 0; -} diff --git a/plat/rpi/rpi3/rpi3_private.h b/plat/rpi/rpi3/rpi3_private.h deleted file mode 100644 index b01c40c..0000000 --- a/plat/rpi/rpi3/rpi3_private.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef RPI3_PRIVATE_H -#define RPI3_PRIVATE_H - -#include - -/******************************************************************************* - * Function and variable prototypes - ******************************************************************************/ - -/* Utility functions */ -void rpi3_console_init(void); -void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size, - uintptr_t code_start, uintptr_t code_limit, - uintptr_t rodata_start, uintptr_t rodata_limit -#if USE_COHERENT_MEM - , uintptr_t coh_start, uintptr_t coh_limit -#endif - ); - -/* Optional functions required in the Raspberry Pi 3 port */ -unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr); - -/* BL2 utility functions */ -uint32_t rpi3_get_spsr_for_bl32_entry(void); -uint32_t rpi3_get_spsr_for_bl33_entry(void); - -/* IO storage utility functions */ -void plat_rpi3_io_setup(void); - -/* VideoCore firmware commands */ -int rpi3_vc_hardware_get_board_revision(uint32_t *revision); - -#endif /* RPI3_PRIVATE_H */ diff --git a/plat/rpi/rpi3/rpi3_rotpk.S b/plat/rpi/rpi3/rpi3_rotpk.S deleted file mode 100644 index 1c17b21..0000000 --- a/plat/rpi/rpi3/rpi3_rotpk.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - .global rpi3_rotpk_hash - .global rpi3_rotpk_hash_end -rpi3_rotpk_hash: - /* DER header */ - .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48 - .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 - /* SHA256 */ - .incbin ROTPK_HASH -rpi3_rotpk_hash_end: diff --git a/plat/rpi/rpi3/rpi3_stack_protector.c b/plat/rpi/rpi3/rpi3_stack_protector.c deleted file mode 100644 index 6f49f61..0000000 --- a/plat/rpi/rpi3/rpi3_stack_protector.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include -#include - -#include "rpi3_private.h" - -/* Get 128 bits of entropy and fuse the values together to form the canary. */ -#define TRNG_NBYTES 16U - -u_register_t plat_get_stack_protector_canary(void) -{ - size_t i; - u_register_t buf[TRNG_NBYTES / sizeof(u_register_t)]; - u_register_t ret = 0U; - - rpi3_rng_read(buf, sizeof(buf)); - - for (i = 0U; i < ARRAY_SIZE(buf); i++) - ret ^= buf[i]; - - return ret; -} diff --git a/plat/rpi/rpi3/rpi3_topology.c b/plat/rpi/rpi3/rpi3_topology.c deleted file mode 100644 index 200d41d..0000000 --- a/plat/rpi/rpi3/rpi3_topology.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#include - -#include - -#include "rpi3_private.h" - -/* The power domain tree descriptor */ -static unsigned char power_domain_tree_desc[] = { - /* Number of root nodes */ - PLATFORM_CLUSTER_COUNT, - /* Number of children for the first node */ - PLATFORM_CLUSTER0_CORE_COUNT, -}; - -/******************************************************************************* - * This function returns the ARM default topology tree information. - ******************************************************************************/ -const unsigned char *plat_get_power_domain_tree_desc(void) -{ - return power_domain_tree_desc; -} - -/******************************************************************************* - * This function implements a part of the critical interface between the psci - * generic layer and the platform that allows the former to query the platform - * to convert an MPIDR to a unique linear index. An error code (-1) is returned - * in case the MPIDR is invalid. - ******************************************************************************/ -int plat_core_pos_by_mpidr(u_register_t mpidr) -{ - unsigned int cluster_id, cpu_id; - - mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { - return -1; - } - - cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; - cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; - - if (cluster_id >= PLATFORM_CLUSTER_COUNT) { - return -1; - } - - if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) { - return -1; - } - - return plat_rpi3_calc_core_pos(mpidr); -} diff --git a/plat/rpi/rpi3/rpi3_trusted_boot.c b/plat/rpi/rpi3/rpi3_trusted_boot.c deleted file mode 100644 index f6c669f..0000000 --- a/plat/rpi/rpi3/rpi3_trusted_boot.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -extern char rpi3_rotpk_hash[], rpi3_rotpk_hash_end[]; - -int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, - unsigned int *flags) -{ - *key_ptr = rpi3_rotpk_hash; - *key_len = rpi3_rotpk_hash_end - rpi3_rotpk_hash; - *flags = ROTPK_IS_HASH; - - return 0; -} - -int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) -{ - *nv_ctr = 0; - - return 0; -} - -int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) -{ - return 1; -} - -int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) -{ - return get_mbedtls_heap_helper(heap_addr, heap_size); -}