diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index e05a7ba..855e98b 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -91,7 +91,7 @@ _STGEN_SEL, _I2C46_SEL, _SPI6_SEL, - _USART1_SEL, + _UART1_SEL, _RNG1_SEL, _UART6_SEL, _UART24_SEL, @@ -101,8 +101,8 @@ _SDMMC3_SEL, _QSPI_SEL, _FMC_SEL, - _ASS_SEL, - _MSS_SEL, + _AXIS_SEL, + _MCUS_SEL, _USBPHY_SEL, _USBO_SEL, _PARENT_SEL_NB, @@ -254,13 +254,13 @@ .fixed = (f), \ } -#define _CLK_PARENT(idx, off, s, m, p) \ - [(idx)] = { \ - .offset = (off), \ - .src = (s), \ - .msk = (m), \ - .parent = (p), \ - .nb_parent = ARRAY_SIZE(p) \ +#define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ + [_ ## _label ## _SEL] = { \ + .offset = _rcc_selr, \ + .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ + .msk = _rcc_selr ## _ ## _label ## SRC_MASK, \ + .parent = (_parents), \ + .nb_parent = ARRAY_SIZE(_parents) \ } #define _CLK_PLL(idx, type, off1, off2, off3, \ @@ -330,7 +330,7 @@ _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), - _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _USART1_SEL), + _CLK_SC_SELEC(RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), _CLK_SC_FIXED(RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), @@ -438,25 +438,25 @@ }; static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { - _CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents), - _CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents), - _CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents), - _CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents), - _CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents), - _CLK_PARENT(_USART1_SEL, RCC_UART1CKSELR, 0, 0x7, usart1_parents), - _CLK_PARENT(_RNG1_SEL, RCC_RNG1CKSELR, 0, 0x3, rng1_parents), - _CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents), - _CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7, uart234578_parents), - _CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7, uart234578_parents), - _CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7, uart234578_parents), - _CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7, sdmmc12_parents), - _CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7, sdmmc3_parents), - _CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0xf, qspi_parents), - _CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0xf, fmc_parents), - _CLK_PARENT(_ASS_SEL, RCC_ASSCKSELR, 0, 0x3, ass_parents), - _CLK_PARENT(_MSS_SEL, RCC_MSSCKSELR, 0, 0x3, mss_parents), - _CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents), - _CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents), + _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), + _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), + _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), + _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), + _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), + _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), + _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), + _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), + _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), + _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), + _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), + _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), + _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), + _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), + _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), + _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, ass_parents), + _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mss_parents), + _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), + _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), }; /* Define characteristic of PLL according type */ @@ -656,7 +656,7 @@ } sel = clk_sel_ref(s); - p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & sel->msk; + p_sel = (mmio_read_32(rcc_base + sel->offset) & sel->msk) >> sel->src; if (p_sel < sel->nb_parent) { return (int)sel->parent[p_sel]; } diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h index eaa853d..4b4aac8 100644 --- a/include/drivers/st/stm32mp1_rcc.h +++ b/include/drivers/st/stm32mp1_rcc.h @@ -480,4 +480,82 @@ /* Values of RCC_PWRLPDLYCR register */ #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0) +/* RCC_ASSCKSELR register fields */ +#define RCC_ASSCKSELR_AXISSRC_MASK GENMASK(2, 0) +#define RCC_ASSCKSELR_AXISSRC_SHIFT 0 + +/* RCC_MSSCKSELR register fields */ +#define RCC_MSSCKSELR_MCUSSRC_MASK GENMASK(1, 0) +#define RCC_MSSCKSELR_MCUSSRC_SHIFT 0 + +/* RCC_I2C46CKSELR register fields */ +#define RCC_I2C46CKSELR_I2C46SRC_MASK GENMASK(2, 0) +#define RCC_I2C46CKSELR_I2C46SRC_SHIFT 0 + +/* RCC_SPI6CKSELR register fields */ +#define RCC_SPI6CKSELR_SPI6SRC_MASK GENMASK(2, 0) +#define RCC_SPI6CKSELR_SPI6SRC_SHIFT 0 + +/* RCC_UART1CKSELR register fields */ +#define RCC_UART1CKSELR_UART1SRC_MASK GENMASK(2, 0) +#define RCC_UART1CKSELR_UART1SRC_SHIFT 0 + +/* RCC_RNG1CKSELR register fields */ +#define RCC_RNG1CKSELR_RNG1SRC_MASK GENMASK(1, 0) +#define RCC_RNG1CKSELR_RNG1SRC_SHIFT 0 + +/* RCC_STGENCKSELR register fields */ +#define RCC_STGENCKSELR_STGENSRC_MASK GENMASK(1, 0) +#define RCC_STGENCKSELR_STGENSRC_SHIFT 0 + +/* RCC_I2C12CKSELR register fields */ +#define RCC_I2C12CKSELR_I2C12SRC_MASK GENMASK(2, 0) +#define RCC_I2C12CKSELR_I2C12SRC_SHIFT 0 + +/* RCC_I2C35CKSELR register fields */ +#define RCC_I2C35CKSELR_I2C35SRC_MASK GENMASK(2, 0) +#define RCC_I2C35CKSELR_I2C35SRC_SHIFT 0 + +/* RCC_UART6CKSELR register fields */ +#define RCC_UART6CKSELR_UART6SRC_MASK GENMASK(2, 0) +#define RCC_UART6CKSELR_UART6SRC_SHIFT 0 + +/* RCC_UART24CKSELR register fields */ +#define RCC_UART24CKSELR_UART24SRC_MASK GENMASK(2, 0) +#define RCC_UART24CKSELR_UART24SRC_SHIFT 0 + +/* RCC_UART35CKSELR register fields */ +#define RCC_UART35CKSELR_UART35SRC_MASK GENMASK(2, 0) +#define RCC_UART35CKSELR_UART35SRC_SHIFT 0 + +/* RCC_UART78CKSELR register fields */ +#define RCC_UART78CKSELR_UART78SRC_MASK GENMASK(2, 0) +#define RCC_UART78CKSELR_UART78SRC_SHIFT 0 + +/* RCC_SDMMC12CKSELR register fields */ +#define RCC_SDMMC12CKSELR_SDMMC12SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC12CKSELR_SDMMC12SRC_SHIFT 0 + +/* RCC_SDMMC3CKSELR register fields */ +#define RCC_SDMMC3CKSELR_SDMMC3SRC_MASK GENMASK(2, 0) +#define RCC_SDMMC3CKSELR_SDMMC3SRC_SHIFT 0 + +/* RCC_ETHCKSELR register fields */ +#define RCC_ETHCKSELR_ETHSRC_MASK GENMASK(1, 0) +#define RCC_ETHCKSELR_ETHSRC_SHIFT 0 + +/* RCC_QSPICKSELR register fields */ +#define RCC_QSPICKSELR_QSPISRC_MASK GENMASK(1, 0) +#define RCC_QSPICKSELR_QSPISRC_SHIFT 0 + +/* RCC_FMCCKSELR register fields */ +#define RCC_FMCCKSELR_FMCSRC_MASK GENMASK(1, 0) +#define RCC_FMCCKSELR_FMCSRC_SHIFT 0 + +/* RCC_USBCKSELR register fields */ +#define RCC_USBCKSELR_USBPHYSRC_MASK GENMASK(1, 0) +#define RCC_USBCKSELR_USBPHYSRC_SHIFT 0 +#define RCC_USBCKSELR_USBOSRC_MASK BIT(4) +#define RCC_USBCKSELR_USBOSRC_SHIFT 4 + #endif /* STM32MP1_RCC_H */