diff --git a/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
new file mode 100644
index 0000000..4176921
--- /dev/null
+++ b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+/ {
+	/* compatible string */
+	compatible = "arm,rd-e1edge";
+
+	/*
+	 * Place holder for system-id node with default values. The
+	 * value of platform-id and config-id will be set to the
+	 * correct values during the BL2 stage of boot.
+	 */
+	system-id {
+		platform-id = <0x0>;
+		config-id = <0x0>;
+	};
+
+};
diff --git a/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
new file mode 100644
index 0000000..766dc00
--- /dev/null
+++ b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+	/* Platform Config */
+	compatible = "arm,tb_fw";
+	nt_fw_config_addr = <0x0 0xFEF00000>;
+	nt_fw_config_max_size = <0x0100000>;
+	/*
+	 * The following two entries are placeholders for Mbed TLS
+	 * heap information. The default values don't matter since
+	 * they will be overwritten by BL1.
+	 * In case of having shared Mbed TLS heap between BL1 and BL2,
+	 * BL1 will populate these two properties with the respective
+	 * info about the shared heap. This info will be available for
+	 * BL2 in order to locate and re-use the heap.
+	 */
+	mbedtls_heap_addr = <0x0 0x0>;
+	mbedtls_heap_size = <0x0>;
+};
diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
new file mode 100644
index 0000000..954a1cd
--- /dev/null
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+
+#include <sgi_base_platform_def.h>
+
+#define PLAT_ARM_CLUSTER_COUNT		2
+#define CSS_SGI_MAX_CPUS_PER_CLUSTER	8
+#define CSS_SGI_MAX_PE_PER_CPU		2
+
+#define PLAT_CSS_MHU_BASE		UL(0x45400000)
+
+/* Base address of DMC-620 instances */
+#define RDE1EDGE_DMC620_BASE0		UL(0x4e000000)
+#define RDE1EDGE_DMC620_BASE1		UL(0x4e100000)
+
+#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL2
+
+#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL3
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
new file mode 100644
index 0000000..833bb82
--- /dev/null
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/css/sgi/sgi-common.mk
+
+RDE1EDGE_BASE		=	plat/arm/board/rde1edge
+
+PLAT_INCLUDES		+=	-I${RDE1EDGE_BASE}/include/
+
+SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_e1.S
+
+BL1_SOURCES		+=	${SGI_CPU_SOURCES}
+
+BL2_SOURCES		+=	${RDE1EDGE_BASE}/rde1edge_plat.c	\
+				${RDE1EDGE_BASE}/rde1edge_security.c	\
+				drivers/arm/tzc/tzc_dmc620.c		\
+				lib/utils/mem_region.c			\
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
+				${RDE1EDGE_BASE}/rde1edge_plat.c	\
+				drivers/cfi/v2m/v2m_flash.c		\
+				lib/utils/mem_region.c			\
+				plat/arm/common/arm_nor_psci_mem_protect.c
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES		+=	${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
+TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
+
+FDT_SOURCES		+=	${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
+NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
+
+# Add the NT_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
+
+override CTX_INCLUDE_AARCH32_REGS	:= 0
diff --git a/plat/arm/board/rde1edge/rde1edge_plat.c b/plat/arm/board/rde1edge/rde1edge_plat.c
new file mode 100644
index 0000000..a1b8d62
--- /dev/null
+++ b/plat/arm/board/rde1edge/rde1edge_plat.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2018, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+
+unsigned int plat_arm_sgi_get_platform_id(void)
+{
+	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
+				& SID_SYSTEM_ID_PART_NUM_MASK;
+}
+
+unsigned int plat_arm_sgi_get_config_id(void)
+{
+	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
+}
diff --git a/plat/arm/board/rde1edge/rde1edge_security.c b/plat/arm/board/rde1edge/rde1edge_security.c
new file mode 100644
index 0000000..2123e09
--- /dev/null
+++ b/plat/arm/board/rde1edge/rde1edge_security.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/arm/tzc_dmc620.h>
+
+uintptr_t rde1edge_dmc_base[] = {
+	RDE1EDGE_DMC620_BASE0,
+	RDE1EDGE_DMC620_BASE1
+};
+
+static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
+	.dmc_base = rde1edge_dmc_base,
+	.dmc_count = ARRAY_SIZE(rde1edge_dmc_base)
+};
+
+static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
+	{
+		.region_base = ARM_AP_TZC_DRAM1_BASE,
+		.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
+		.sec_attr = TZC_DMC620_REGION_S_RDWR
+	}
+};
+
+static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
+	.plat_drv_data = &rde1edge_plat_driver_data,
+	.plat_acc_addr_data = rde1edge_acc_addr_data,
+	.acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data)
+};
+
+/* Initialize the secure environment */
+void plat_arm_security_setup(void)
+{
+	arm_tzc_dmc620_setup(&rde1edge_plat_config_data);
+}
diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts b/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts
deleted file mode 100644
index 3dedf1d..0000000
--- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	/* compatible string */
-	compatible = "arm,sgi-clark";
-
-	/*
-	 * Place holder for system-id node with default values. The
-	 * value of platform-id and config-id will be set to the
-	 * correct values during the BL2 stage of boot.
-	 */
-	system-id {
-		platform-id = <0x0>;
-		config-id = <0x0>;
-	};
-
-};
diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts b/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts
deleted file mode 100644
index 766dc00..0000000
--- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
-	/* Platform Config */
-	compatible = "arm,tb_fw";
-	nt_fw_config_addr = <0x0 0xFEF00000>;
-	nt_fw_config_max_size = <0x0100000>;
-	/*
-	 * The following two entries are placeholders for Mbed TLS
-	 * heap information. The default values don't matter since
-	 * they will be overwritten by BL1.
-	 * In case of having shared Mbed TLS heap between BL1 and BL2,
-	 * BL1 will populate these two properties with the respective
-	 * info about the shared heap. This info will be available for
-	 * BL2 in order to locate and re-use the heap.
-	 */
-	mbedtls_heap_addr = <0x0 0x0>;
-	mbedtls_heap_size = <0x0>;
-};
diff --git a/plat/arm/board/sgiclarkh/include/platform_def.h b/plat/arm/board/sgiclarkh/include/platform_def.h
deleted file mode 100644
index fe8907b..0000000
--- a/plat/arm/board/sgiclarkh/include/platform_def.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-
-#include <sgi_base_platform_def.h>
-
-#define PLAT_ARM_CLUSTER_COUNT		2
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER	8
-#define CSS_SGI_MAX_PE_PER_CPU		2
-
-#define PLAT_CSS_MHU_BASE		UL(0x45400000)
-
-/* Base address of DMC-620 instances */
-#define SGICLARKH_DMC620_BASE0		UL(0x4e000000)
-#define SGICLARKH_DMC620_BASE1		UL(0x4e100000)
-
-#define PLAT_MAX_PWR_LVL		ARM_PWR_LVL2
-
-#define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL3
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/sgiclarkh/platform.mk b/plat/arm/board/sgiclarkh/platform.mk
deleted file mode 100644
index 1e93d93..0000000
--- a/plat/arm/board/sgiclarkh/platform.mk
+++ /dev/null
@@ -1,42 +0,0 @@
-#
-# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/css/sgi/sgi-common.mk
-
-SGICLARKH_BASE		=	plat/arm/board/sgiclarkh
-
-PLAT_INCLUDES		+=	-I${SGICLARKH_BASE}/include/
-
-SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_e1.S
-
-BL1_SOURCES		+=	${SGI_CPU_SOURCES}
-
-BL2_SOURCES		+=	${SGICLARKH_BASE}/sgiclarkh_plat.c	\
-				${SGICLARKH_BASE}/sgiclarkh_security.c	\
-				drivers/arm/tzc/tzc_dmc620.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
-				${SGICLARKH_BASE}/sgiclarkh_plat.c	\
-				drivers/cfi/v2m/v2m_flash.c		\
-				lib/utils/mem_region.c			\
-				plat/arm/common/arm_nor_psci_mem_protect.c
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${SGICLARKH_BASE}/fdts/${PLAT}_tb_fw_config.dts
-TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
-
-FDT_SOURCES		+=	${SGICLARKH_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
-
-override CTX_INCLUDE_AARCH32_REGS	:= 0
diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_plat.c b/plat/arm/board/sgiclarkh/sgiclarkh_plat.c
deleted file mode 100644
index a1b8d62..0000000
--- a/plat/arm/board/sgiclarkh/sgiclarkh_plat.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/common/platform.h>
-
-unsigned int plat_arm_sgi_get_platform_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
-				& SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_sgi_get_config_id(void)
-{
-	return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_security.c b/plat/arm/board/sgiclarkh/sgiclarkh_security.c
deleted file mode 100644
index aaf9691..0000000
--- a/plat/arm/board/sgiclarkh/sgiclarkh_security.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
-
-uintptr_t sgiclarkh_dmc_base[] = {
-	SGICLARKH_DMC620_BASE0,
-	SGICLARKH_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t sgiclarkh_plat_driver_data = {
-	.dmc_base = sgiclarkh_dmc_base,
-	.dmc_count = ARRAY_SIZE(sgiclarkh_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t sgiclarkh_acc_addr_data[] = {
-	{
-		.region_base = ARM_AP_TZC_DRAM1_BASE,
-		.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
-		.sec_attr = TZC_DMC620_REGION_S_RDWR
-	}
-};
-
-static const tzc_dmc620_config_data_t sgiclarkh_plat_config_data = {
-	.plat_drv_data = &sgiclarkh_plat_driver_data,
-	.plat_acc_addr_data = sgiclarkh_acc_addr_data,
-	.acc_addr_count = ARRAY_SIZE(sgiclarkh_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	arm_tzc_dmc620_setup(&sgiclarkh_plat_config_data);
-}
diff --git a/readme.rst b/readme.rst
index 2d7af75..ae9ca80 100644
--- a/readme.rst
+++ b/readme.rst
@@ -194,7 +194,7 @@
 
 -  Allwinner sun50i_64 and sun50i_h6
 -  Amlogic Meson S905 (GXBB)
--  Arm SGI-575, RDN1Edge, SGI Clark.H and SGM-775
+-  Arm SGI-575, RDN1Edge, RDE1Edge and SGM-775
 -  Arm Neoverse N1 System Development Platform
 -  HiKey, HiKey960 and Poplar boards
 -  Marvell Armada 3700 and 8K