/* This document is intended to provide the developer with information
 * how to integrate a new CPU (MACH) into this part of the barebox tree
 */

/** @page dev_mips_mach MIPS based CPU (MACH) into the tree

@section mach_mips_reset What's happens when the reset signal is gone

Barebox normally must be linked to RAM region, cached region KSEG0 is preferred.
This make possible to run fast (because cache used) and skip MMU support.

After reset MIPS CPU starting to fetch instructions from 0xBFC00000.

@note Code running immediately after reset runs at an address it is not linked
      to: "runtime address != link address". You should only use branches and
      do not refer to fixed data. This implies the use of assembler code only.
      After MIPS CPU reset cache and MMU are in random state. They are unusable.

barebox MIPS initialisation sequence:

 * set the CP0 STATUS register to some known and sensible state.
Now you can load and store reliably in uncached space.

 * call a function \<mach_init_lowlevel\> (if not disabled).
do some special things required only on specific CPU
 (e. g. init RAM controller, disable watchdog)

 * call a function \<board_init_lowlevel\> (if not disable).
do some special things required only on specific board
 (e. g. setup GPIO to required state).

   ** It is desirable to have some debug code to make some contact
 with the outside world from assembler code
(e.g. debug_ll-like functions to write to rs232 console).

 * check integrity of barebox RAM execute location;
 * copy barebox to RAM execute location;

 * configure cache;

 * setup stack;

   ** after this point you can call a standard C routine.

 * setup exception vectors in RAM;
 * setup CP0 STATUS to switch exception vector address to RAM;

 * call start_barebox()

Further reading:
 * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006
ISBN-13: 978-0120884216

@subsection mach_mips_malta_info Malta boards

@li @subpage dev_malta_mach

@subsection mach_bcm47xx_info BCM47xx-based boards

@li @subpage dev_bcm47xx_mach

@subsection mach_xburst_info XBurst-based boards

@li @subpage dev_xburst_mach
*/
