diff --git a/arch/arm/mach-imx/speed-imx31.c b/arch/arm/mach-imx/speed-imx31.c
index 630c648..70b1330 100644
--- a/arch/arm/mach-imx/speed-imx31.c
+++ b/arch/arm/mach-imx/speed-imx31.c
@@ -41,6 +41,18 @@
 	return imx_get_mpl_dpdgck_clk();
 }
 
+/**
+ * Calculate the current pixel clock speed (aka HSP or IPU)
+ * @return 0 on failure or current frequency in Hz
+ */
+ulong imx_get_lcdclk(void)
+{
+	ulong hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 11) & 0x03;
+	ulong base_clk = imx_get_mcu_main_clk();
+
+	return base_clk / (hsp_podf + 1);
+}
+
 ulong imx_get_perclk1(void)
 {
 	u32 freq = imx_get_mcu_main_clk();
diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
index 4c8420a..1721079 100644
--- a/arch/arm/mach-imx/speed-imx35.c
+++ b/arch/arm/mach-imx/speed-imx35.c
@@ -118,6 +118,37 @@
 	return imx_get_ipgclk();
 }
 
+/**
+ * Calculate the current pixel clock speed (aka HSP or IPU)
+ * @return 0 on failure or current frequency in Hz
+ */
+unsigned long imx_get_lcdclk(void)
+{
+	unsigned long hsp_podf = (readl(IMX_CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+	unsigned long base_clk = imx_get_armclk();
+
+	if (base_clk > 400 * 1000 * 1000) {
+		switch(hsp_podf) {
+		case 0:
+			return base_clk >> 2;
+		case 1:
+			return base_clk >> 3;
+		case 2:
+			return base_clk / 3;
+		}
+	} else {
+		switch(hsp_podf) {
+		case 0:
+		case 2:
+			return base_clk / 3;
+		case 1:
+			return base_clk / 6;
+		}
+	}
+
+	return 0;
+}
+
 unsigned long imx_get_uartclk(void)
 {
 	unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);