diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c index 9e667e3..2d42d3d 100644 --- a/arch/arm/mach-imx/gpio.c +++ b/arch/arm/mach-imx/gpio.c @@ -29,10 +29,14 @@ void imx_gpio_mode(int gpio_mode) { unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> 5; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> 10; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; + unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; + unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; unsigned int tmp; + printf("gpio_mode: 0x%08x ocr: 0x%08x port: %d pin: %2d aout: %d bout: %d\n", gpio_mode, ocr, port, pin, aout, bout); + /* Pullup enable */ if(gpio_mode & GPIO_PUEN) PUEN(port) |= (1 << pin); @@ -52,25 +56,22 @@ GPR(port) &= ~(1 << pin); /* use as gpio? */ - if( ocr == 3 ) + if(!(gpio_mode & (GPIO_PF | GPIO_AF))) GIUS(port) |= (1 << pin); else GIUS(port) &= ~(1 << pin); /* Output / input configuration */ - /* FIXME: I'm not very sure about OCR and ICONF, someone - * should have a look over it - */ if (pin < 16) { tmp = OCR1(port); tmp &= ~(3 << (pin * 2)); tmp |= (ocr << (pin * 2)); OCR1(port) = tmp; - if( gpio_mode & GPIO_AOUT ) - ICONFA1(port) &= ~(3 << (pin * 2)); - if( gpio_mode & GPIO_BOUT ) - ICONFB1(port) &= ~(3 << (pin * 2)); + ICONFA1(port) &= ~(3 << (pin * 2)); + ICONFA1(port) |= aout << (pin * 2); + ICONFB1(port) &= ~(3 << (pin * 2)); + ICONFB1(port) |= bout << (pin * 2); } else { pin -= 16; @@ -79,10 +80,10 @@ tmp |= (ocr << (pin * 2)); OCR2(port) = tmp; - if( gpio_mode & GPIO_AOUT ) - ICONFA2(port) &= ~(3 << (pin * 2)); - if( gpio_mode & GPIO_BOUT ) - ICONFB2(port) &= ~(3 << (pin * 2)); + ICONFA2(port) &= ~(3 << (pin * 2)); + ICONFA2(port) |= aout << (pin * 2); + ICONFB2(port) &= ~(3 << (pin * 2)); + ICONFB2(port) |= bout << (pin * 2); } } diff --git a/board/phycore_pcm038/lowlevel_init.S b/board/phycore_pcm038/lowlevel_init.S index 0c47c3a..fc65b90 100644 --- a/board/phycore_pcm038/lowlevel_init.S +++ b/board/phycore_pcm038/lowlevel_init.S @@ -50,6 +50,9 @@ writel(0x130410c3, PCDR0) writel(0x09030913, PCDR1) + /* skip sdram setup for debugging */ + mov pc,r10 + /* Skip SDRAM initialization if we run from RAM */ cmp pc, #0xa0000000 bls 1f @@ -69,9 +72,9 @@ writel(0x00005005, 0x10027838) writel(0x15555555, 0x1002783C) writel(0x00000004, 0xD8001010) - writel(0x00795729, 0xD8001004) + writel(0x006ac73a, 0xD8001004) writel(0x92100000, 0xD8001000) - writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) writel(0xA2100000, 0xD8001000) writel(0x00000000, 0xA0000F00) writel(0x00000000, 0xA0000F00) @@ -82,14 +85,14 @@ writel(0x00000000, 0xA0000F00) writel(0x00000000, 0xA0000F00) writel(0x00000000, 0xA0000F00) - writel(0xB2126080, 0xD8001000) + writel(0xb2100000, 0xD8001000) ldr r0, =0xA0000033 - mov r1, #0x0 + mov r1, #0xda strb r1, [r0] ldr r0, =0xA1000000 - mov r1, #0x0 + mov r1, #0xff strb r1, [r0] - writel(0x82126080, 0xD8001000) + writel(0x82226080, 0xD8001000) mov pc,r10 diff --git a/board/phycore_pcm038/pcm038.c b/board/phycore_pcm038/pcm038.c index 092abd1..9b1f0e3 100644 --- a/board/phycore_pcm038/pcm038.c +++ b/board/phycore_pcm038/pcm038.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -42,45 +43,51 @@ .id = "ram0", .map_base = 0xa0000000, - .size = 32 * 1024 * 1024, + .size = 128 * 1024 * 1024, .type = DEVICE_TYPE_DRAM, }; -static struct device_d fec_dev = { - .name = "fec_imx27", - .id = "eth0", +static struct mpc5xxx_fec_platform_data fec_info = { + .xcv_type = MII100, +}; +static struct device_d fec_dev = { + .name = "fec_mpc5xxx", + .id = "eth0", + .map_base = 0x1002b000, + .platform_data = &fec_info, .type = DEVICE_TYPE_ETHER, }; static int pcm038_devices_init(void) { int i; - unsigned short mode[] = { - PD12_AOUT_FEC_RXD0, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD4_AOUT_FEC_RX_ER, - PD13_AOUT_FEC_RX_DV, + unsigned int mode[] = { PD0_AIN_FEC_TXD0, PD1_AIN_FEC_TXD1, PD2_AIN_FEC_TXD2, PD3_AIN_FEC_TXD3, - PD11_AOUT_FEC_TX_CLK, - PF23_AIN_FEC_TX_EN, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, PD14_AOUT_FEC_CLR, PD15_AOUT_FEC_COL, PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, PE12_PF_UART1_TXD, PE13_PF_UART1_RXD, PE14_PF_UART1_CTS, PE15_PF_UART1_RTS }; - for (i = 0; i < sizeof(mode) / sizeof(short); i ++) + for (i = 0; i < sizeof(mode) / sizeof(int); i++) imx_gpio_mode(mode[i]); register_device(&cfi_dev); diff --git a/commands/mount.c b/commands/mount.c index 22794f0..dd04bde 100644 --- a/commands/mount.c +++ b/commands/mount.c @@ -83,7 +83,7 @@ * Usage: mount [ ] * * Mounts a filesystem of a given on a to a . - * can be one of /dev/* or some arbitrary string if no + * can be one of /dev/ * or some arbitrary string if no * device is needed for this driver (for example ramfs). * * is the filesystem driver to use. Try the 'devinfo' command diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6b169da..0c88ef0 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -49,7 +49,7 @@ config DRIVER_NET_MPC5200 bool "MPC5200 Ethernet driver" - depends on ARCH_MPC5200 + depends on ARCH_MPC5200 || ARCH_IMX27 select MIIPHY config DRIVER_NET_TAP diff --git a/drivers/net/fec_mpc5200.c b/drivers/net/fec_mpc5200.c index 41c191f..d42243e 100644 --- a/drivers/net/fec_mpc5200.c +++ b/drivers/net/fec_mpc5200.c @@ -6,18 +6,27 @@ * (C) Copyright Motorola, Inc., 2000 */ +#define DEBUG + #include -#include +//#include #include #include #include #include #include -#include -#include -#include +//#include +//#include +#include +//#include #include #include "fec_mpc5200.h" +#ifdef CONFIG_ARCH_IMX27 +#include +#include +#include +#include +#endif #define CONFIG_PHY_ADDR 1 /* FIXME */ @@ -39,12 +48,13 @@ uint32 reg; /* convenient holder for the PHY register */ uint32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; + uint64_t start; /* * reading from any PHY's register is done by properly * programming the FEC's MII data register. */ + fec->eth->ievent = FEC_IEVENT_MII; reg = regAddr << FEC_MII_DATA_RA_SHIFT; phy = phyAddr << FEC_MII_DATA_PA_SHIFT; @@ -53,11 +63,12 @@ /* * wait for the related interrupt */ - while ((timeout--) && (!(fec->eth->ievent & FEC_IEVENT_MII))) ; - - if (timeout == 0) { - debug("Read MDIO failed...\n"); - return -1; + start = get_time_ns(); + while (!(fec->eth->ievent & FEC_IEVENT_MII)) { + if (is_timeout(start, MSECOND)) { + printf("Read MDIO failed...\n"); + return -1; + } } /* @@ -81,7 +92,7 @@ uint32 reg; /* convenient holder for the PHY register */ uint32 phy; /* convenient holder for the PHY */ - int timeout = 0xffff; + uint64_t start; reg = regAddr << FEC_MII_DATA_RA_SHIFT; phy = phyAddr << FEC_MII_DATA_PA_SHIFT; @@ -92,11 +103,12 @@ /* * wait for the MII interrupt */ - while ((timeout--) && (!(fec->eth->ievent & FEC_IEVENT_MII))) ; - - if (timeout == 0) { - debug("Write MDIO failed...\n"); - return -1; + start = get_time_ns(); + while (!(fec->eth->ievent & FEC_IEVENT_MII)) { + if (is_timeout(start, MSECOND)) { + printf("Write MDIO failed...\n"); + return -1; + } } /* @@ -107,19 +119,72 @@ return 0; } +#ifdef CONFIG_MPC5200 +static int mpc5xxx_fec_rx_task_enable(mpc5xxx_fec_priv *fec) +{ + SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); + return 0; +} + +static int mpc5xxx_fec_rx_task_disable(mpc5xxx_fec_priv *fec) +{ + SDMA_TASK_DISABLE(FEC_RECV_TASK_NO); + return 0; +} + +static int mpc5xxx_fec_tx_task_enable(mpc5xxx_fec_priv *fec) +{ + SDMA_TASK_ENABLE(FEC_XMIT_TASK_NO); + return 0; +} + +static int mpc5xxx_fec_tx_task_disable(mpc5xxx_fec_priv *fec) +{ + SDMA_TASK_DISABLE(FEC_XMIT_TASK_NO); + return 0; +} +#endif + +#ifdef CONFIG_ARCH_IMX27 +static int mpc5xxx_fec_rx_task_enable(mpc5xxx_fec_priv *fec) +{ + fec->eth->r_des_active = 1 << 24; + return 0; +} + +static int mpc5xxx_fec_rx_task_disable(mpc5xxx_fec_priv *fec) +{ + return 0; +} + +static int mpc5xxx_fec_tx_task_enable(mpc5xxx_fec_priv *fec) +{ + fec->eth->x_des_active = 1 << 24; + return 0; +} + +static int mpc5xxx_fec_tx_task_disable(mpc5xxx_fec_priv *fec) +{ + return 0; +} +#endif + static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec) { int ix; char *data; static int once = 0; + printf("%s\n", __FUNCTION__); + for (ix = 0; ix < FEC_RBD_NUM; ix++) { if (!once) { - data = (char *)malloc(FEC_MAX_PKT_SIZE); - if (data == NULL) { - printf ("RBD INIT FAILED\n"); - return -1; - } +#if 0 + /* sha: Should work like this: */ + data = (char *)xzalloc(FEC_MAX_PKT_SIZE); +#endif + /* sha: But for some reason we need alignement: */ + data = (char *)((unsigned long)(xzalloc(FEC_MAX_PKT_SIZE + 0x10) + 0x10) & ~0xf); fec->rbdBase[ix].dataPointer = (uint32)data; } fec->rbdBase[ix].status = FEC_RBD_EMPTY; @@ -138,27 +203,13 @@ static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec) { - int ix; - - for (ix = 0; ix < FEC_TBD_NUM; ix++) { - fec->tbdBase[ix].status = 0; - } - - /* - * Have the last TBD to close the ring - */ - fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP; - - /* - * Initialize some indices - */ - fec->tbdIndex = 0; - fec->usedTbdIndex = 0; - fec->cleanTbdNum = FEC_TBD_NUM; + fec->tbdBase[0].status = FEC_TBD_WRAP; } static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd) { + pRbd->dataLength = 0; + /* * Reset buffer descriptor as empty */ @@ -167,12 +218,10 @@ else pRbd->status = FEC_RBD_EMPTY; - pRbd->dataLength = 0; - /* * Now, we have an empty RxBD, restart the SmartDMA receive task */ - SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); + mpc5xxx_fec_rx_task_enable(fec); /* * Increment BD count @@ -180,50 +229,21 @@ fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; } -static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec) -{ - volatile FEC_TBD *pUsedTbd; - - /* - * process all the consumed TBDs - */ - while (fec->cleanTbdNum < FEC_TBD_NUM) { - pUsedTbd = &fec->tbdBase[fec->usedTbdIndex]; - if (pUsedTbd->status & FEC_TBD_READY) { - debug("Cannot clean TBD %d, in use\n", fec->cleanTbdNum); - return; - } - - /* - * clean this buffer descriptor - */ - if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) - pUsedTbd->status = FEC_TBD_WRAP; - else - pUsedTbd->status = 0; - - /* - * update some indeces for a correct handling of the TBD ring - */ - fec->cleanTbdNum++; - fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; - } -} - -static int mpc5xxx_fec_get_ethaddr(struct eth_device *dev, unsigned char *mac) +static int mpc5xxx_fec_get_hwaddr(struct eth_device *dev, unsigned char *mac) { /* no eeprom */ return -1; } -static int mpc5xxx_fec_set_ethaddr(struct eth_device *dev, unsigned char *mac) +static int mpc5xxx_fec_set_hwaddr(struct eth_device *dev, unsigned char *mac) { mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; uint8 currByte; /* byte for which to compute the CRC */ int byte; /* loop - counter */ int bit; /* loop - counter */ uint32 crc = 0xffffffff; /* initial value */ - +//#define WTF_IS_THIS +#ifdef WTF_IS_THIS /* * The algorithm used is the following: * we loop on each of the six bytes of the provided address, @@ -264,7 +284,12 @@ fec->eth->iaddr1 = 0; fec->eth->iaddr2 = (1 << crc); } - +#else + fec->eth->iaddr1 = 0; + fec->eth->iaddr2 = 0; + fec->eth->gaddr1 = 0; + fec->eth->gaddr2 = 0; +#endif /* * Set physical address */ @@ -277,8 +302,9 @@ static int mpc5xxx_fec_init(struct eth_device *dev) { mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; +#ifdef CONFIG_MPC5200 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; - +#endif debug("mpc5xxx_fec_init... Begin\n"); /* @@ -304,27 +330,31 @@ /* * Frame length=1518; 7-wire mode */ - fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */ + fec->eth->r_cntrl = 0x05ee0020; /* FIXME 0x05ee0000 */ } else { /* * Frame length=1518; MII mode; */ - fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */ - } + fec->eth->r_cntrl = 0x05ee0024; /* FIXME 0x05ee0004 */ - if (fec->xcv_type != SEVENWIRE) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ +#ifdef CONFIG_MPC5200 fec->eth->mii_speed = (((get_ipb_clock() >> 20) / 5) << 1); /* No MII for 7-wire mode */ +#endif +#ifdef CONFIG_ARCH_IMX27 + fec->eth->mii_speed = (((imx_get_ahbclk() >> 20) / 5) << 1); /* No MII for 7-wire mode */ +#endif } /* * Set Opcode/Pause Duration Register */ - fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */ + fec->eth->op_pause = 0x00010020; /* FIXME 0xffff0020; */ +#ifdef CONFIG_MPC5200 /* * Set Rx FIFO alarm and granularity value */ @@ -349,6 +379,13 @@ * Set transmit fifo watermark register(X_WMRK), default = 64 */ fec->eth->tfifo_alarm = 0x00000080; + + /* + * Turn ON cheater FSM: ???? + */ + fec->eth->xmit_fsm = 0x03000000; +#endif + fec->eth->x_wmrk = 0x2; /* @@ -357,31 +394,32 @@ fec->eth->gaddr1 = 0x00000000; fec->eth->gaddr2 = 0x00000000; - /* - * Turn ON cheater FSM: ???? - */ - fec->eth->xmit_fsm = 0x03000000; - +#ifdef CONFIG_MPC5200 /* * Set priority of different initiators */ sdma->IPR0 = 7; /* always */ sdma->IPR3 = 6; /* Eth RX */ sdma->IPR4 = 5; /* Eth Tx */ +#endif +#ifdef CONFIG_ARCH_IMX27 + fec->eth->emrbr = 2048-16; +#endif /* * Clear SmartDMA task interrupt pending bits */ - SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO); +// SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO); /* * Initialize SmartDMA parameters stored in SRAM */ +#ifdef CONFIG_MPC5200 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase; *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase; *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase; *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase; - +#endif debug("mpc5xxx_fec_init... Done \n"); if (fec->xcv_type != SEVENWIRE) @@ -394,6 +432,8 @@ { mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv; + printf("%s\n", __FUNCTION__); + #if defined(CONFIG_MPC5200) struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; /* @@ -403,17 +443,27 @@ sdma->PtdCntrl |= 0x00000001; #endif +#if 0 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */ +#else + fec->eth->x_cntrl = 1 << 2; /* full-duplex, heartbeat disabled */ +#endif + + fec->rbdIndex = 0; /* * Enable FEC-Lite controller */ +#if defined(CONFIG_MPC5200) fec->eth->ecntrl |= 0x00000006; - +#endif +#if defined(CONFIG_ARCH_IMX27) + fec->eth->ecntrl |= 0x00000002; +#endif /* * Enable SmartDMA receive task */ - SDMA_TASK_ENABLE(FEC_RECV_TASK_NO); + mpc5xxx_fec_rx_task_enable(fec); if (fec->xcv_type != SEVENWIRE) { miiphy_wait_aneg(&fec->miiphy); @@ -444,10 +494,10 @@ /* * Disable SmartDMA tasks */ - SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO); - SDMA_TASK_DISABLE (FEC_RECV_TASK_NO); + mpc5xxx_fec_tx_task_disable(fec); + mpc5xxx_fec_rx_task_disable(fec); -#if defined(CONFIG_MPC5200) +#ifdef CONFIG_MPC5200 /* * Turn on COMM bus prefetch in the MGT5200 BestComm after we're * done. It doesn't work w/ the current receive task. @@ -458,13 +508,15 @@ /* * Disable the Ethernet Controller */ - fec->eth->ecntrl &= 0xfffffffd; + fec->eth->ecntrl = 0; +#ifdef CONFIG_MPC5200 /* * Clear FIFO status registers */ fec->eth->rfifo_status &= 0x00700000; fec->eth->tfifo_status &= 0x00700000; +#endif // fec->eth->reset_cntrl = 0x01000000; @@ -514,7 +566,7 @@ { } -static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec) +static void __maybe_unused rfifo_print(char *devname, mpc5xxx_fec_priv *fec) { } #endif /* DEBUG_FIFO */ @@ -529,16 +581,13 @@ mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv; volatile FEC_TBD *pTbd; +// printf("%s length=%d data=0x%08x\n", __FUNCTION__, data_length, eth_data); + #ifdef DEBUG_FIFO debug_fifo("tbd status: 0x%04x\n", fec->tbdBase[0].status); tfifo_print(dev->name, fec); #endif /* - * Clear Tx BD ring at first - */ - mpc5xxx_fec_tbd_scrub(fec); - - /* * Check for valid length of data. */ if ((data_length > 1500) || (data_length <= 0)) { @@ -546,41 +595,17 @@ } /* - * Check the number of vacant TxBDs. - */ - if (fec->cleanTbdNum < 1) { - printf("No available TxBDs ...\n"); - return -1; - } - - /* * Get the first TxBD to send the mac header */ - pTbd = &fec->tbdBase[fec->tbdIndex]; + pTbd = &fec->tbdBase[0]; pTbd->dataLength = data_length; pTbd->dataPointer = (uint32)eth_data; - pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; - fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; - - /* - * Kick the MII i/f - */ - if (fec->xcv_type != SEVENWIRE) { - uint16 phyStatus; - fec5xxx_miiphy_read(&fec->miiphy, 0, 0x1, &phyStatus); - } + pTbd->status = FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY | FEC_TBD_WRAP; /* * Enable SmartDMA transmit task */ - - tfifo_print(dev->name, fec); - - SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO); - - tfifo_print(dev->name, fec); - - fec->cleanTbdNum -= 1; + mpc5xxx_fec_tx_task_enable(fec); /* * wait until frame is sent . @@ -604,6 +629,7 @@ NBUF *frame; uchar buff[FEC_MAX_PKT_SIZE]; +// printf("%s\n", __FUNCTION__); /* * Check if any critical events have happened */ @@ -614,6 +640,7 @@ /* BABT, Rx/Tx FIFO errors */ mpc5xxx_fec_halt(dev); mpc5xxx_fec_init(dev); + printf("some error: 0x%08x\n", ievent); return 0; } if (ievent & FEC_IEVENT_HBERR) { @@ -632,29 +659,38 @@ if (!(pRbd->status & FEC_RBD_EMPTY)) { if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && ((pRbd->dataLength - 4) > 14)) { + printf("read from %d (0x%08x) rbd=0x%08x", fec->rbdIndex, pRbd->dataPointer, pRbd); /* * Get buffer address and size */ frame = (NBUF *)pRbd->dataPointer; frame_length = pRbd->dataLength - 4; - + printf(" len=%d\n", frame_length); +#define DEBUG_RX_HEADER #ifdef DEBUG_RX_HEADER { int i; - printf("recv data hdr:"); - for (i = 0; i < 14; i++) - printf("%02x ", *(frame->head + i)); - printf("\n"); + printf("recv data hdr:\n"); + memory_display(frame->data, 0, frame_length, 1); } #endif /* * Fill the buffer and pass it to upper layers */ +#ifdef CONFIG_MPC5200 memcpy(buff, frame->head, 14); memcpy(buff + 14, frame->data, frame_length); +#endif +#ifdef CONFIG_ARCH_IMX27 + memcpy(buff, frame->data, frame_length); +#endif NetReceive(buff, frame_length); len = frame_length; + } else { + if (pRbd->status & FEC_RBD_ERR) { + printf("error frame: 0x%08x 0x%08x\n", pRbd, pRbd->status); + } } /* * Reset buffer descriptor as empty @@ -662,7 +698,7 @@ mpc5xxx_fec_rbd_clean(fec, pRbd); } - SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); +// SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO); return len; } @@ -672,6 +708,11 @@ struct eth_device *edev; mpc5xxx_fec_priv *fec; + printf("%s\n", __FUNCTION__); + +#ifdef CONFIG_ARCH_IMX27 + PCCR0 |= PCCR0_FEC_EN; +#endif edev = (struct eth_device *)malloc(sizeof(struct eth_device)); dev->type_data = edev; fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec)); @@ -682,24 +723,46 @@ edev->send = mpc5xxx_fec_send, edev->recv = mpc5xxx_fec_recv, edev->halt = mpc5xxx_fec_halt, - edev->get_ethaddr = mpc5xxx_fec_ethaddr, - edev->set_ethaddr = mpc5xxx_fec_ethaddr, + edev->get_ethaddr = mpc5xxx_fec_get_hwaddr, + edev->set_ethaddr = mpc5xxx_fec_set_hwaddr, fec->eth = (ethernet_regs *)dev->map_base; + +#ifdef CONFIG_MPC5200 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); +#endif +#ifdef CONFIG_ARCH_IMX27 + /* Reset chip. FIXME: shouldn't it be done for mpc5200 aswell? */ + fec->eth->ecntrl = 1; + while(fec->eth->ecntrl & 1) { + udelay(10); + } + + { + unsigned long base; + + base = ((unsigned long)xzalloc(sizeof(FEC_TBD) + 32) + 32) & ~0x1f; + fec->tbdBase = (FEC_TBD *)base; + fec->eth->etdsr = fec->tbdBase; + base = ((unsigned long)xzalloc(FEC_RBD_NUM * sizeof(FEC_RBD) + 32) + 32) & ~0x1f; + fec->rbdBase = (FEC_RBD *)base; + fec->eth->erdsr = fec->rbdBase; + } +#endif fec->xcv_type = pdata->xcv_type; sprintf(dev->name, "FEC ETHERNET"); - +#ifdef CONFIG_MPC5200 loadtask(0, 2); - +#endif if (fec->xcv_type != SEVENWIRE) { fec->miiphy.read = fec5xxx_miiphy_read; fec->miiphy.write = fec5xxx_miiphy_write; fec->miiphy.address = CONFIG_PHY_ADDR; fec->miiphy.flags = pdata->xcv_type == MII10 ? MIIPHY_FORCE_10 : 0; + fec->miiphy.edev = edev; miiphy_register(&fec->miiphy); } diff --git a/drivers/net/fec_mpc5200.h b/drivers/net/fec_mpc5200.h index 62fb1cf..8eacdd7 100644 --- a/drivers/net/fec_mpc5200.h +++ b/drivers/net/fec_mpc5200.h @@ -100,8 +100,11 @@ volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */ volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */ +#define erdsr fm_cntrl volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */ +#define etdsr rfifo_data volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */ +#define emrbr rfifo_status volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */ volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */ volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */ @@ -241,14 +244,24 @@ /* Receive & Transmit Buffer Descriptor definitions */ typedef struct BufferDescriptor { +#ifdef CONFIG_MPC5200 uint16 status; +#endif uint16 dataLength; +#ifdef CONFIG_ARCH_IMX27 + uint16 status; +#endif uint32 dataPointer; } FEC_RBD; typedef struct { +#ifdef CONFIG_MPC5200 uint16 status; +#endif uint16 dataLength; +#ifdef CONFIG_ARCH_IMX27 + uint16 status; +#endif uint32 dataPointer; } FEC_TBD; @@ -260,9 +273,6 @@ FEC_RBD *rbdBase; /* RBD ring */ FEC_TBD *tbdBase; /* TBD ring */ uint16 rbdIndex; /* next receive BD to read */ - uint16 tbdIndex; /* next transmit BD to send */ - uint16 usedTbdIndex; /* next transmit BD to clean */ - uint16 cleanTbdNum; /* the number of available transmit BDs */ struct miiphy_device miiphy; } mpc5xxx_fec_priv; @@ -274,8 +284,7 @@ #define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c) /* BD Numer definitions */ -#define FEC_TBD_NUM 48 /* The user can adjust this value */ -#define FEC_RBD_NUM 32 /* The user can adjust this value */ +#define FEC_RBD_NUM 64 /* The user can adjust this value */ /* packet size limit */ #define FEC_MAX_PKT_SIZE 1536 diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index a8ef8b7..472f74c 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h @@ -56,48 +56,62 @@ * i.MX1 and i.MXL: 0 <= x <= 3 * i.MX27 : 0 <= x <= 5 */ -#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) -#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) -#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) -#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) -#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) -#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) -#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) -#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) -#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) -#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) -#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) -#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) -#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) -#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) -#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) -#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) -#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) +#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8) +#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8) +#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8) +#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8) +#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8) +#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8) +#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8) +#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8) +#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8) +#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8) +#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8) +#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8) +#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8) +#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8) +#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8) +#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8) +#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8) #define GPIO_PIN_MASK 0x1f -#define GPIO_PORT_MASK (0x7 << 5) -#define GPIO_PORTA (0 << 5) -#define GPIO_PORTB (1 << 5) -#define GPIO_PORTC (2 << 5) -#define GPIO_PORTD (3 << 5) -#define GPIO_PORTE (4 << 5) -#define GPIO_PORTF (5 << 5) +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) #define GPIO_OUT (1 << 8) #define GPIO_IN (0 << 8) #define GPIO_PUEN (1 << 9) -#define GPIO_PF (0 << 10) -#define GPIO_AF (1 << 10) +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) -#define GPIO_OCR_MASK (3 << 11) -#define GPIO_AIN (0 << 11) -#define GPIO_BIN (1 << 11) -#define GPIO_CIN (2 << 11) -#define GPIO_GPIO (3 << 11) +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) -#define GPIO_AOUT (1 << 13) -#define GPIO_BOUT (1 << 14) +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) #endif /* _IMX_REGS_H */ diff --git a/include/asm-sandbox/posix_types.h b/include/asm-sandbox/posix_types.h index 5529f32..5dcc842 100644 --- a/include/asm-sandbox/posix_types.h +++ b/include/asm-sandbox/posix_types.h @@ -16,8 +16,8 @@ typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t;