diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3349e69..3afd885 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -56,6 +56,7 @@ select GPIOLIB select COMMON_CLK select CLKDEV_LOOKUP + select WATCHDOG_IMX_RESET_SOURCE config ARCH_MXS bool "Freescale i.MX23/28 (mxs) based" diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c index 0b450d6..a8d172c 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51.c +++ b/arch/arm/boards/ccxmx51/ccxmx51.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include @@ -45,6 +45,7 @@ #include #include #include +#include #include "ccxmx51.h" diff --git a/arch/arm/boards/ccxmx51/ccxmx51js.c b/arch/arm/boards/ccxmx51/ccxmx51js.c index f04615d..c947a1e 100644 --- a/arch/arm/boards/ccxmx51/ccxmx51js.c +++ b/arch/arm/boards/ccxmx51/ccxmx51js.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c index bf3cbc3..92e8df2 100644 --- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -250,18 +250,3 @@ imx_nand_load_image(_text, barebox_image_size); } #endif - -static int eukrea_cpuimx25_core_init(void) { - /* enable UART1, FEC, SDHC, USB & I2C clock */ - writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR0) | (1 << 6) | (1 << 23) - | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28), - MX25_CCM_BASE_ADDR + CCM_CGCR0); - writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR1) | (1 << 23) | (1 << 15) - | (1 << 13), MX25_CCM_BASE_ADDR + CCM_CGCR1); - writel(readl(MX25_CCM_BASE_ADDR + CCM_CGCR2) | (1 << 14), - MX25_CCM_BASE_ADDR + CCM_CGCR2); - - return 0; -} - -core_initcall(eukrea_cpuimx25_core_init); diff --git a/arch/arm/boards/eukrea_cpuimx25/flash_header.c b/arch/arm/boards/eukrea_cpuimx25/flash_header.c index 344c7ff..9102c2a 100644 --- a/arch/arm/boards/eukrea_cpuimx25/flash_header.c +++ b/arch/arm/boards/eukrea_cpuimx25/flash_header.c @@ -23,7 +23,7 @@ */ #include #include -#include +#include #include void __naked __flash_header_start go(void) diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c index 8d6cd1f..36ce98b 100644 --- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c @@ -19,7 +19,7 @@ */ #include #include -#include +#include #include #include #include @@ -56,15 +56,15 @@ common_reset(); /* restart the MPLL and wait until it's stable */ - writel(readl(MX25_CCM_BASE_ADDR + CCM_CCTL) | (1 << 27), - MX25_CCM_BASE_ADDR + CCM_CCTL); - while (readl(MX25_CCM_BASE_ADDR + CCM_CCTL) & (1 << 27)) {}; + writel(readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) | (1 << 27), + MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); + while (readl(MX25_CCM_BASE_ADDR + MX25_CCM_CCTL) & (1 << 27)) {}; /* Configure dividers and ARM clock source * ARM @ 400 MHz * AHB @ 133 MHz */ - writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL); + writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); /* Enable UART1 / FEC / */ /* writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0); @@ -117,10 +117,10 @@ writel(0x1, 0xb8003000); /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX25_CCM_BASE_ADDR + CCM_PCDR2); + r = readl(MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); r &= ~0xf; r |= 0x1; - writel(r, MX25_CCM_BASE_ADDR + CCM_PCDR2); + writel(r, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -128,22 +128,22 @@ board_init_lowlevel_return(); /* Init Mobile DDR */ - writel(0x0000000E, ESDMISC); - writel(0x00000004, ESDMISC); + writel(0x0000000E, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x00000004, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); __asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0" (loops)); - writel(0x0029572B, ESDCFG0); - writel(0x92210000, ESDCTL0); + writel(0x0029572B, MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x92210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x400); - writel(0xA2210000, ESDCTL0); + writel(0xA2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR); writeb(0xda, MX25_CSD0_BASE_ADDR); - writel(0xB2210000, ESDCTL0); + writel(0xB2210000, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x33); writeb(0xda, MX25_CSD0_BASE_ADDR + 0x1000000); - writel(0x82216080, ESDCTL0); + writel(0x82216080, MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c index cff4f77..c89ce8a 100644 --- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include @@ -194,7 +194,6 @@ #endif imx27_add_nand(&nand_info); - PCCR0 |= PCCR0_I2C1_EN; i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); imx27_add_i2c0(NULL); @@ -223,11 +222,16 @@ static int eukrea_cpuimx27_console_init(void) { + uint32_t val; + #ifdef CONFIG_DRIVER_SERIAL_IMX imx27_add_uart0(); #endif /* configure 8 bit UART on cs3 */ - FMCR &= ~0x2; + val = readl(MX27_SYSCTRL_BASE_ADDR + MX27_FMCR); + val &= ~0x2; + writel(val, MX27_SYSCTRL_BASE_ADDR + MX27_FMCR); + imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000); #ifdef CONFIG_DRIVER_SERIAL_NS16550 add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf, diff --git a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S index 1983d48..4ee6efb 100644 --- a/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S +++ b/arch/arm/boards/eukrea_cpuimx27/lowlevel_init.S @@ -1,6 +1,7 @@ #include #include -#include +#include +#include #include #define writel(val, reg) \ @@ -9,10 +10,10 @@ str r1, [r0]; #if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB -#define ROWS0 ESDCTL_ROW14 +#define ROWS0 ESDCTL0_ROW14 #define CFG0 0x0029572D #elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB -#define ROWS0 ESDCTL_ROW13 +#define ROWS0 ESDCTL0_ROW13 #define CFG0 0x00095728 #endif @@ -22,20 +23,26 @@ /* * DDR on CSD0 */ - writel(0x0000000C, ESDMISC) /* Enable DDR SDRAM operation */ + /* Enable DDR SDRAM operation */ + writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) - writel(0x55555555, DSCR(3)) /* Set the driving strength */ - writel(0x55555555, DSCR(5)) - writel(0x55555555, DSCR(6)) - writel(0x00005005, DSCR(7)) - writel(0x15555555, DSCR(8)) + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)) + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)) + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)) - writel(0x00000004, ESDMISC) /* Initial reset */ - writel(CFG0, ESDCFG0) - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) + writel(CFG0, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0) + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xa0000f00 mov r1, #0 @@ -45,7 +52,8 @@ subs r2, #1 bne 1b - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xA0000033 mov r1, #0xda strb r1, [r0] @@ -56,7 +64,9 @@ #endif mov r1, #0xff strb r1, [r0] - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) .endm .section ".text_bare_init","ax" @@ -67,23 +77,26 @@ common_reset r0 /* ahb lite ip interface */ - writel(0x20040304, AIPI1_PSR0) - writel(0xDFFBFCFB, AIPI1_PSR1) - writel(0x00000000, AIPI2_PSR0) - writel(0xFFFFFFFF, AIPI2_PSR1) + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) /* disable mpll/spll */ - ldr r0, =CSCR + ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR ldr r1, [r0] bic r1, r1, #0x03 str r1, [r0] - + /* * pll clock initialization - see section 3.4.3 of the i.MX27 manual */ - writel(0x00331C23, MPCTL0) /* MPLL = 399 MHz */ - writel(0x040C2403, SPCTL0) /* SPLL = 240 MHz */ - writel(0x33F38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + /* MPLL = 399 MHz */ + writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 240 MHz */ + writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) + writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) /* add some delay here */ mov r1, #0x1000 @@ -91,12 +104,14 @@ bne 1b /* clock gating enable */ - writel(0x00050f08, GPCR) + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) /* peripheral clock divider */ - writel(0x130400c3, PCDR0) /* FIXME */ - writel(0x09030208, PCDR1) /* PERDIV1=08 @133 MHz */ - /* PERDIV1=04 @266 MHz */ + /* FIXME */ + writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0) + /* PERDIV1=08 @133 MHz */ + writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1) + /* PERDIV1=04 @266 MHz */ /* skip sdram initialization if we run from ram */ cmp pc, #0xa0000000 diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 53cc428..fdbc26a 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -41,7 +41,7 @@ #include #include -#include +#include #include #include #include @@ -246,14 +246,14 @@ u32 reg; /* enable clock for I2C1, SDHC1, USB and FEC */ - reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); - reg |= 0x3 << CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT; - reg |= 0x3 << CCM_CGR1_I2C1_SHIFT, - reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1); - reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR2); - reg |= 0x3 << CCM_CGR2_USB_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR2); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + reg |= 0x3 << MX35_CCM_CGR1_SDHC1_SHIFT; + reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT, + reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR2); + reg |= 0x3 << MX35_CCM_CGR2_USB_SHIFT; + reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR2); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* @@ -345,10 +345,10 @@ switch (freq) { case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c index 26752d1..6fa9c8b 100644 --- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c +++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c @@ -1,6 +1,6 @@ #include #include -#include +#include #include void __naked __flash_header_start go(void) diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c index 8689f9e..0523335 100644 --- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c @@ -18,7 +18,7 @@ */ #include #include -#include +#include #include #include #include @@ -41,10 +41,10 @@ uint32_t r; /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + CCM_PDR4); + r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); r &= ~(0xf << 28); r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + CCM_PDR4); + writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); /* setup a stack to be able to call imx_nand_load_image() */ arm_setup_stack(STACK_BASE + STACK_SIZE - 12); @@ -105,27 +105,27 @@ * End of ARM1136 init */ - writel(0x003F4208, ccm_base + CCM_CCMR); + writel(0x003F4208, ccm_base + MX35_CCM_CCMR); /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); - writel(0x00001000, ccm_base + CCM_PDR0); + writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); + writel(0x00001000, ccm_base + MX35_CCM_PDR0); - r = readl(ccm_base + CCM_CGR0); + r = readl(ccm_base + MX35_CCM_CGR0); r |= 0x00300000; - writel(r, ccm_base + CCM_CGR0); + writel(r, ccm_base + MX35_CCM_CGR0); - r = readl(ccm_base + CCM_CGR1); + r = readl(ccm_base + MX35_CCM_CGR1); r |= 0x00030C00; r |= 0x00000003; - writel(r, ccm_base + CCM_CGR1); + writel(r, ccm_base + MX35_CCM_CGR1); /* enable watchdog asap */ - r = readl(ccm_base + CCM_CGR2); + r = readl(ccm_base + MX35_CCM_CGR2); r |= 0x03000000; - writel(r, ccm_base + CCM_CGR2); + writel(r, ccm_base + MX35_CCM_CGR2); r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; @@ -137,22 +137,22 @@ board_init_lowlevel_return(); /* Init Mobile DDR */ - writel(0x0000000E, ESDMISC); - writel(0x00000004, ESDMISC); + writel(0x0000000E, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x00000004, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); __asm__ volatile ("1:\n" "subs %0, %1, #1\n" "bne 1b":"=r" (loops):"0" (loops)); - writel(0x0009572B, ESDCFG0); - writel(0x92220000, ESDCTL0); + writel(0x0009572B, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x92220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x400); - writel(0xA2220000, ESDCTL0); + writel(0xA2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR); writeb(0xda, MX35_CSD0_BASE_ADDR); - writel(0xB2220000, ESDCTL0); + writel(0xB2220000, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x33); writeb(0xda, MX35_CSD0_BASE_ADDR + 0x2000000); - writel(0x82228080, ESDCTL0); + writel(0x82228080, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c index 1279f89..ab0ff81 100644 --- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c index a0ae938..5ce2f8e 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include @@ -167,8 +167,8 @@ * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 */ - writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */ - writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */ + writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */ + writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */ #define FEC_ENABLE_GPIO 35 #define FEC_RESET_B_GPIO 104 @@ -215,7 +215,7 @@ imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); - if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14)) + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); @@ -298,7 +298,7 @@ static int imx25_core_setup(void) { - writel(0x01010103, MX25_CCM_BASE_ADDR + CCM_PCDR2); + writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); return 0; } diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S index f911f9d..fb98099 100644 --- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S @@ -18,7 +18,7 @@ */ #include -#include +#include #include #include #include @@ -66,9 +66,9 @@ str r1, [r0, #MX25_CCM_MCR] /* enable all the clocks */ - writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR0) - writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + CCM_CGCR1) - writel(0x000FDFFF, MX25_CCM_BASE_ADDR + CCM_CGCR2) + writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0) + writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1) + writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2) writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR) /* Skip SDRAM initialization if we run from RAM */ diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c index 7cd61f9..5bcb24c 100644 --- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c @@ -236,7 +236,7 @@ imx_enable_enetclk(); mx28_evk_fec_reset(); - add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0x4000, + add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000, IORESOURCE_MEM, &fec_info); return 0; diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c index 9a01424..7da031a 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c +++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c @@ -41,12 +41,13 @@ #include #include #include -#include +#include #include #include #include #include #include +#include #include #include @@ -143,7 +144,7 @@ /* CS0: Nor Flash */ imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); - reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -281,10 +282,10 @@ imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00); /* enable clock for I2C1 and FEC */ - reg = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); - reg |= 0x3 << CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << CCM_CGR1_I2C1_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; + reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* diff --git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c index 66763db..076b816 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c +++ b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c @@ -1,6 +1,6 @@ #include #include -#include +#include #include void __naked __flash_header_start go(void) diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S index e5d0feb..dada5f3 100644 --- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S +++ b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S @@ -17,7 +17,7 @@ * */ -#include +#include #include #include #include @@ -98,27 +98,27 @@ ldr r0, CCM_BASE_ADDR_W ldr r2, CCM_CCMR_W - str r2, [r0, #CCM_CCMR] + str r2, [r0, #MX35_CCM_CCMR] ldr r3, MPCTL_PARAM_532_W /* consumer path*/ /* Set MPLL, arm clock and ahb clock */ - str r3, [r0, #CCM_MPCTL] + str r3, [r0, #MX35_CCM_MPCTL] ldr r1, PPCTL_PARAM_W - str r1, [r0, #CCM_PPCTL] + str r1, [r0, #MX35_CCM_PPCTL] ldr r1, CCM_PDR0_W - str r1, [r0, #CCM_PDR0] + str r1, [r0, #MX35_CCM_PDR0] - ldr r1, [r0, #CCM_CGR0] + ldr r1, [r0, #MX35_CCM_CGR0] orr r1, r1, #0x00300000 - str r1, [r0, #CCM_CGR0] + str r1, [r0, #MX35_CCM_CGR0] - ldr r1, [r0, #CCM_CGR1] + ldr r1, [r0, #MX35_CCM_CGR1] orr r1, r1, #0x00000C00 orr r1, r1, #0x00000003 - str r1, [r0, #CCM_CGR1] + str r1, [r0, #MX35_CCM_CGR1] /* Skip SDRAM initialization if we run from RAM */ cmp pc, #CSD0_BASE_ADDR @@ -140,13 +140,13 @@ /* setup bank 0 */ mov r5, #0x00 mov r2, #0x00 - mov r1, #CSD0_BASE_ADDR + mov r1, #MX35_CSD0_BASE_ADDR bl setup_sdram_bank /* setup bank 1 */ mov r5, #0x00 mov r2, #0x00 - mov r1, #CSD1_BASE_ADDR + mov r1, #MX35_CSD1_BASE_ADDR bl setup_sdram_bank mov lr, fp diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c index 3a8e5ea..9db0ed9 100644 --- a/arch/arm/boards/freescale-mx51-pdk/board.c +++ b/arch/arm/boards/freescale-mx51-pdk/board.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -37,7 +38,9 @@ #include #include #include +#include #include +#include static struct fec_platform_data fec_info = { .xcv_type = MII100, @@ -234,6 +237,10 @@ mdelay(50); } +#define DCD_NAME static struct imx_dcd_entry dcd_entry + +#include "dcd-data.h" + static int f3s_devices_init(void) { spi_register_board_info(mx51_babbage_spi_board_info, @@ -254,6 +261,9 @@ armlinux_set_bootparams((void *)0x90000100); armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); + imx51_bbu_internal_mmc_register_handler("mmc", "/dev/disk0", + BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry)); + return 0; } diff --git a/arch/arm/boards/freescale-mx51-pdk/dcd-data.h b/arch/arm/boards/freescale-mx51-pdk/dcd-data.h new file mode 100644 index 0000000..4dd6c0d --- /dev/null +++ b/arch/arm/boards/freescale-mx51-pdk/dcd-data.h @@ -0,0 +1,60 @@ + +DCD_NAME[] = { + { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, }, + { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, + { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, }, + { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, }, + { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, + { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, + { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, + { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, }, + { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, }, + { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, }, + { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, }, + { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, }, + { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, }, + { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, + { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, + { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, + { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, + { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, +}; + diff --git a/arch/arm/boards/freescale-mx51-pdk/flash_header.c b/arch/arm/boards/freescale-mx51-pdk/flash_header.c index c148eea..f3f1e4b 100644 --- a/arch/arm/boards/freescale-mx51-pdk/flash_header.c +++ b/arch/arm/boards/freescale-mx51-pdk/flash_header.c @@ -7,64 +7,9 @@ barebox_arm_head(); } -struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { - { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, }, - { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, - { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, - { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, }, - { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, }, - { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, - { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, - { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, - { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, }, - { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, }, - { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, }, - { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, }, - { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, - { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, - { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, }, - { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, }, - { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, - { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, - { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, - { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, - { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, - { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, -}; +#define DCD_NAME struct imx_dcd_entry __dcd_entry_section dcd_entry + +#include "dcd-data.h" #define APP_DEST 0x90000000 diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c index f7d6e05..216d26a 100644 --- a/arch/arm/boards/freescale-mx53-loco/board.c +++ b/arch/arm/boards/freescale-mx53-loco/board.c @@ -27,7 +27,7 @@ #include -#include +#include #include #include #include @@ -35,6 +35,9 @@ #include #include #include +#include +#include +#include #include #include @@ -176,6 +179,10 @@ add_generic_usb_ehci_device(1, MX53_OTG_BASE_ADDR + 0x200, NULL); } +#define DCD_NAME static struct imx_dcd_v2_entry dcd_entry + +#include "dcd-data.h" + static int loco_devices_init(void) { @@ -195,6 +202,9 @@ armlinux_set_bootparams((void *)0x70000100); armlinux_set_architecture(MACH_TYPE_MX53_LOCO); + imx53_bbu_internal_mmc_register_handler("mmc", "/dev/disk0", + BBU_HANDLER_FLAG_DEFAULT, dcd_entry, sizeof(dcd_entry)); + return 0; } diff --git a/arch/arm/boards/freescale-mx53-loco/dcd-data.h b/arch/arm/boards/freescale-mx53-loco/dcd-data.h new file mode 100644 index 0000000..9f95fb4 --- /dev/null +++ b/arch/arm/boards/freescale-mx53-loco/dcd-data.h @@ -0,0 +1,54 @@ + +DCD_NAME[] = { + { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), }, + { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), }, + { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), }, + { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), }, + { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), }, + { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), }, + { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), }, + { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), }, + { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), }, + { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), }, + { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), }, + { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), }, + { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, + { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), }, + { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), }, + { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), }, + { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, + { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, + { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, +}; diff --git a/arch/arm/boards/freescale-mx53-loco/flash_header.c b/arch/arm/boards/freescale-mx53-loco/flash_header.c index c2ab255..dc1162b 100644 --- a/arch/arm/boards/freescale-mx53-loco/flash_header.c +++ b/arch/arm/boards/freescale-mx53-loco/flash_header.c @@ -23,59 +23,9 @@ barebox_arm_head(); } -struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = { - { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), }, - { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), }, - { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), }, - { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), }, - { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), }, - { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), }, - { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), }, - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), }, - { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), }, - { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), }, - { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), }, - { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, - { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), }, - { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), }, - { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x052080b0), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x05208138), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), }, - { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, - { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, - { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, -}; +#define DCD_NAME struct imx_dcd_v2_entry __dcd_entry_section dcd_entry + +#include "dcd-data.h" #define APP_DEST 0x70000000 diff --git a/arch/arm/boards/freescale-mx53-smd/board.c b/arch/arm/boards/freescale-mx53-smd/board.c index 0483103..a5ad009 100644 --- a/arch/arm/boards/freescale-mx53-smd/board.c +++ b/arch/arm/boards/freescale-mx53-smd/board.c @@ -27,7 +27,7 @@ #include -#include +#include #include #include #include diff --git a/arch/arm/boards/freescale-mx6-arm2/board.c b/arch/arm/boards/freescale-mx6-arm2/board.c index ccc7318..ce9874d 100644 --- a/arch/arm/boards/freescale-mx6-arm2/board.c +++ b/arch/arm/boards/freescale-mx6-arm2/board.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/freescale-mx6-sabrelite/board.c b/arch/arm/boards/freescale-mx6-sabrelite/board.c index 25402d7..da37e17 100644 --- a/arch/arm/boards/freescale-mx6-sabrelite/board.c +++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -200,7 +200,7 @@ return 0; } -static int sabrelite_spi_cs[] = {GPIO_PORTC + 19}; +static int sabrelite_spi_cs[] = {IMX_GPIO_NR(3, 19)}; static struct spi_imx_master sabrelite_spi_0_data = { .chipselect = sabrelite_spi_cs, diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c index 933a9cd..5b17326 100644 --- a/arch/arm/boards/guf-cupid/board.c +++ b/arch/arm/boards/guf-cupid/board.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include @@ -117,7 +117,7 @@ gpio_direction_output(GPIO_LCD_ENABLE, 0); gpio_direction_output(GPIO_LCD_BACKLIGHT, 0); - reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -339,10 +339,10 @@ switch (freq) { case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c index a1b58cc..f2e44af 100644 --- a/arch/arm/boards/guf-cupid/lowlevel.c +++ b/arch/arm/boards/guf-cupid/lowlevel.c @@ -18,7 +18,7 @@ */ #include #include -#include +#include #include #include #include @@ -70,15 +70,15 @@ u32 r1, r0; /* disable second SDRAM region to save power */ - r1 = readl(ESDCTL1); + r1 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1); r1 &= ~ESDCTL0_SDE; - writel(r1, ESDCTL1); + writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL1); mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST; - writel(mode, ESDMISC); + writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST); - writel(mode, ESDMISC); + writel(mode, MX35_ESDCTL_BASE_ADDR + IMX_ESDMISC); /* wait for esdctl reset */ for (loop = 0; loop < 0x20000; loop++); @@ -89,16 +89,18 @@ ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ESDCFGx_tRCD_3 | ESDCFGx_tRC_20; - writel(r1, ESDCFG0); + writel(r1, MX35_ESDCTL_BASE_ADDR + IMX_ESDCFG0); /* enable SDRAM controller */ - writel(memsize | ESDCTL0_SMODE_NORMAL, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_NORMAL, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); /* Micron Datasheet Initialization Step 3: Wait 200us before first command */ for (loop = 0; loop < 1000; loop++); /* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */ - writel(memsize | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_PRECHARGE, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(r11, sdram_addr); /* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns) @@ -108,7 +110,8 @@ /* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP * (at least 140ns) */ - writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(r11, r9); /* AUTO REFRESH #1 */ for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ @@ -118,7 +121,8 @@ for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ /* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */ - writel(memsize | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + writel(memsize | ESDCTL0_SMODE_LOAD_MODE, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3)); /* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP @@ -133,7 +137,8 @@ */ /* Now configure SDRAM-Controller and check that it works */ - writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, ESDCTL0); + writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, + MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); /* Freescale asks for first access to be a write to properly * initialize DQS pin-state and keepers @@ -155,10 +160,10 @@ /* if both value are identical, we don't have 14 rows. assume 13 instead */ if (readl(r9) == readl(r9 + (1 << 25))) { - r0 = readl(ESDCTL0); + r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); r0 &= ~ESDCTL0_ROW_MASK; r0 |= ESDCTL0_ROW13; - writel(r0, ESDCTL0); + writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } /* So far we asssumed that we have 10 columns, verify this */ @@ -167,10 +172,10 @@ /* if both value are identical, we don't have 10 cols. assume 9 instead */ if (readl(r9) == readl(r9 + (1 << 11))) { - r0 = readl(ESDCTL0); + r0 = readl(MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); r0 &= ~ESDCTL0_COL_MASK; r0 |= ESDCTL0_COL9; - writel(r0, ESDCTL0); + writel(r0, MX35_ESDCTL_BASE_ADDR + IMX_ESDCTL0); } } @@ -181,7 +186,7 @@ void __bare_init __naked reset(void) { u32 r0, r1; - void *iomuxc_base = (void *)IMX_IOMUXC_BASE; + void *iomuxc_base = (void *)MX35_IOMUXC_BASE_ADDR; int i; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; @@ -297,27 +302,27 @@ /* Configure clocks */ /* setup cpu/bus clocks */ - writel(0x003f4208, MX35_CCM_BASE_ADDR + CCM_CCMR); + writel(0x003f4208, MX35_CCM_BASE_ADDR + MX35_CCM_CCMR); /* configure MPLL */ - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); /* configure PPLL */ - writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + CCM_PPCTL); + writel(PPCTL_PARAM_300, MX35_CCM_BASE_ADDR + MX35_CCM_PPCTL); /* configure core dividers */ - r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2); + r0 = MX35_PDR0_CCM_PER_AHB(1) | MX35_PDR0_HSP_PODF(2); - writel(r0, MX35_CCM_BASE_ADDR + CCM_PDR0); + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_PDR0); /* configure clock-gates */ - r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR0); + r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); r0 |= 0x00300000; - writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR0); + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR0); - r0 = readl(MX35_CCM_BASE_ADDR + CCM_CGR1); + r0 = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); r0 |= 0x00000c03; - writel(r0, MX35_CCM_BASE_ADDR + CCM_CGR1); + writel(r0, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); /* Configure SDRAM */ /* Try 32-Bit 256 MB DDR memory */ diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c index 7adee92..200a2ef 100644 --- a/arch/arm/boards/guf-neso/board.c +++ b/arch/arm/boards/guf-neso/board.c @@ -35,7 +35,7 @@ #include #include -#include +#include #include #include #include @@ -320,10 +320,10 @@ pllfunc(); /* clock gating enable */ - GPCR = 0x00050f08; + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); - PCDR0 = 0x130410c3; - PCDR1 = 0x09030911; + writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); + writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); diff --git a/arch/arm/boards/guf-neso/lowlevel.c b/arch/arm/boards/guf-neso/lowlevel.c index d45a5b4..ad414d9 100644 --- a/arch/arm/boards/guf-neso/lowlevel.c +++ b/arch/arm/boards/guf-neso/lowlevel.c @@ -18,7 +18,7 @@ */ #include #include -#include +#include #include #include #include @@ -33,8 +33,6 @@ #ifdef CONFIG_NAND_IMX_BOOT static void __bare_init __naked insdram(void) { - PCCR1 |= PCCR1_NFC_BAUDEN; - /* setup a stack to be able to call imx_nand_load_image() */ arm_setup_stack(STACK_BASE + STACK_SIZE - 12); @@ -57,10 +55,10 @@ common_reset(); /* ahb lite ip interface */ - AIPI1_PSR0 = 0x20040304; - AIPI1_PSR1 = 0xDFFBFCFB; - AIPI2_PSR0 = 0x00000000; - AIPI2_PSR1 = 0xFFFFFFFF; + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -70,30 +68,38 @@ /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - DSCR(3) = 0x55555555; /* Set the driving strength */ - DSCR(5) = 0x55555555; - DSCR(6) = 0x55555555; - DSCR(7) = 0x00005005; - DSCR(8) = 0x15555555; + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); - writel(0x00000004, ESDMISC); /* Initial reset */ - writel(0x006ac73a, ESDCFG0); + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */ + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); for (i = 0; i < 8; i++) writel(0, 0xa0000f00); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, 0xa0000033); writeb(0xff, 0xa1000000); writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0); + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/guf-neso/pll_init.S b/arch/arm/boards/guf-neso/pll_init.S index 87e5312..4c6cb67 100644 --- a/arch/arm/boards/guf-neso/pll_init.S +++ b/arch/arm/boards/guf-neso/pll_init.S @@ -1,5 +1,5 @@ #include -#include +#include #include #include @@ -8,34 +8,37 @@ ldr r1, =val; \ str r1, [r0]; -#define CSCR_VAL CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_MCU_SEL | \ - CSCR_ARM_SRC_MPLL | \ - CSCR_SP_SEL | \ - CSCR_ARM_DIV(0) | \ - CSCR_FPM_EN | \ - CSCR_SPEN | \ - CSCR_MPEN | \ - CSCR_AHB_DIV(1) +#define CSCR_VAL MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_MCU_SEL | \ + MX27_CSCR_ARM_SRC_MPLL | \ + MX27_CSCR_SP_SEL | \ + MX27_CSCR_ARM_DIV(0) | \ + MX27_CSCR_FPM_EN | \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN | \ + MX27_CSCR_AHB_DIV(1) ENTRY(neso_pll_init) + /* 399 MHz */ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0) - writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + writel(CSCR_VAL | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) ldr r2, =16000 1: diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c index 22406be..ca566c8 100644 --- a/arch/arm/boards/imx21ads/imx21ads.c +++ b/arch/arm/boards/imx21ads/imx21ads.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include @@ -95,10 +95,10 @@ imx21_setup_eimcs(4, 0x0, 0x0); imx21_setup_eimcs(5, 0x0, 0x0); - temp = PCDR0; + temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0); temp &= ~0xF000; temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */ - PCDR0 = temp; + writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0); return 0; } @@ -193,7 +193,6 @@ #ifdef CONFIG_NAND_IMX_BOOT void __bare_init nand_boot(void) { - PCCR0 |= PCCR0_NFC_EN; imx_nand_load_image(_text, barebox_image_size); board_init_lowlevel_return(); } diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S index 0cb8aaf..e52cac1 100644 --- a/arch/arm/boards/imx21ads/lowlevel_init.S +++ b/arch/arm/boards/imx21ads/lowlevel_init.S @@ -15,7 +15,7 @@ #include #include -#include +#include #include .section ".text_bare_init","ax" @@ -30,17 +30,17 @@ * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21 * reference manual. */ - ldr r0, =AIPI1_PSR0 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0 ldr r1, =0x00040304 str r1, [r0] - ldr r0, =AIPI1_PSR1 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1 ldr r1, =0xfffbfcfb str r1, [r0] - ldr r0, =AIPI2_PSR0 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0 ldr r1, =0x3ffc0000 str r1, [r0] - ldr r0, =AIPI2_PSR1 + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1 ldr r1, =0xffffffff str r1, [r0] @@ -48,11 +48,11 @@ * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable * the clock to peripherals. */ - ldr r0, =CSCR + ldr r0, =MX21_CCM_BASE_ADDR + MX21_CSCR ldr r1, =0x17180607 str r1, [r0] - ldr r0, =PCCR1 + ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1 ldr r1, =0x0e000000 str r1, [r0] @@ -65,7 +65,7 @@ * CSD1 not required, because the MX21ADS board only contains 64Mbyte. * CS3 can therefore be made available. */ - ldr r0, =FMCR + ldr r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR ldr r1, =0xffffffc9 str r1, [r0] @@ -79,7 +79,7 @@ 1: /* Precharge */ - ldr r0, =SDCTL0 + ldr r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0 ldr r1, =0x92120300 str r1, [r0] ldr r2, =0xc0200000 @@ -113,7 +113,7 @@ str r1, [r0] /* Set NFC_CLK to 24MHz */ - ldr r0, =PCDR0 + ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0 ldr r1, =0x6419a007 str r1, [r0] diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c index 22c6e40..f41b155 100644 --- a/arch/arm/boards/imx27ads/imx27ads.c +++ b/arch/arm/boards/imx27ads/imx27ads.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S index 1bebb1d..2dc34b5 100644 --- a/arch/arm/boards/imx27ads/lowlevel_init.S +++ b/arch/arm/boards/imx27ads/lowlevel_init.S @@ -5,7 +5,7 @@ */ #include -#include +#include #include #define writel(val, reg) \ @@ -118,13 +118,13 @@ common_reset r0 /* ahb lite ip interface */ - writel(0x20040304, AIPI1_PSR0) - writel(0xDFFBFCFB, AIPI1_PSR1) - writel(0x00000000, AIPI2_PSR0) - writel(0xFFFFFFFF, AIPI2_PSR1) + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) /* disable mpll/spll */ - ldr r0, =CSCR + ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR ldr r1, [r0] bic r1, r1, #0x03 str r1, [r0] @@ -136,15 +136,16 @@ * with 1.2 V core voltage! Find out if this is * documented somewhere. */ - writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */ - writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */ + writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */ + writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */ /* * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz * System clock (HCLK) = 133 MHz */ - writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) + writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) /* add some delay here */ mov r1, #0x1000 @@ -152,13 +153,14 @@ bne 1b /* clock gating enable */ - writel(0x00050f08, GPCR) + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) /* peripheral clock divider */ - writel(0x23C8F403, PCDR0) /* FIXME */ - writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */ - /* PERDIV1=04 @266 MHz * - * / + /* FIXME */ + writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0) + /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz */ + writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1) /* skip sdram initialization if we run from ram */ cmp pc, #0xa0000000 bls 1f diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c index 5413ea8..1ffd890 100644 --- a/arch/arm/boards/karo-tx25/board.c +++ b/arch/arm/boards/karo-tx25/board.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include @@ -75,8 +75,8 @@ MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, }; -#define TX25_FEC_PWR_GPIO (GPIO_PORTD | 9) -#define TX25_FEC_RST_GPIO (GPIO_PORTD | 7) +#define TX25_FEC_PWR_GPIO IMX_GPIO_NR(4, 9) +#define TX25_FEC_RST_GPIO IMX_GPIO_NR(4, 7) static void noinline gpio_fec_active(void) { @@ -108,7 +108,7 @@ imx25_iim_register_fec_ethaddr(); imx25_add_fec(&fec_info); - if (readl(MX25_CCM_BASE_ADDR + CCM_RCSR) & (1 << 14)) + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) nand_info.width = 2; imx25_add_nand(&nand_info); @@ -217,9 +217,9 @@ .pcr = PCR_TFT | PCR_COLOR | PCR_FLMPOL | PCR_LPPOL | PCR_SCLK_SEL, }; -#define STK5_LCD_BACKLIGHT_GPIO (GPIO_PORTA | 26) -#define STK5_LCD_RESET_GPIO (GPIO_PORTB | 4) -#define STK5_LCD_POWER_GPIO (GPIO_PORTB | 5) +#define STK5_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 26) +#define STK5_LCD_RESET_GPIO IMX_GPIO_NR(2, 4) +#define STK5_LCD_POWER_GPIO IMX_GPIO_NR(2, 5) static void tx25_fb_enable(int enable) { diff --git a/arch/arm/boards/karo-tx25/lowlevel.c b/arch/arm/boards/karo-tx25/lowlevel.c index 2d09fd7..9c5cc5c 100644 --- a/arch/arm/boards/karo-tx25/lowlevel.c +++ b/arch/arm/boards/karo-tx25/lowlevel.c @@ -18,7 +18,7 @@ */ #include #include -#include +#include #include #include #include @@ -45,8 +45,8 @@ static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl, uint32_t esdcfg) { - uint32_t esdctlreg = ESDCTL0; - uint32_t esdcfgreg = ESDCFG0; + uint32_t esdctlreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCTL0; + uint32_t esdcfgreg = MX25_ESDCTL_BASE_ADDR + IMX_ESDCFG0; if (base == 0x90000000) { esdctlreg += 8; @@ -121,12 +121,12 @@ writel(0x1, 0xb8003000); /* configure ARM clk */ - writel(0x20034000, MX25_CCM_BASE_ADDR + CCM_CCTL); + writel(0x20034000, MX25_CCM_BASE_ADDR + MX25_CCM_CCTL); /* enable all the clocks */ - writel(0x1fffffff, MX25_CCM_BASE_ADDR + CCM_CGCR0); - writel(0xffffffff, MX25_CCM_BASE_ADDR + CCM_CGCR1); - writel(0x000fdfff, MX25_CCM_BASE_ADDR + CCM_CGCR2); + writel(0x1fffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0); + writel(0xffffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1); + writel(0x000fdfff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -136,9 +136,9 @@ /* set to 3.3v SDRAM */ writel(0x800, MX25_IOMUXC_BASE_ADDR + 0x454); - writel(ESDMISC_RST, ESDMISC); + writel(ESDMISC_RST, MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC); - while (!(readl(ESDMISC) & (1 << 31))); + while (!(readl(MX25_ESDCTL_BASE_ADDR + IMX_ESDMISC) & (1 << 31))); #define ESDCTLVAL (ESDCTL0_ROW13 | ESDCTL0_COL9 | ESDCTL0_DSIZ_15_0 | \ ESDCTL0_REF4 | ESDCTL0_PWDT_PRECHARGE_PWDN | ESDCTL0_BL) diff --git a/arch/arm/boards/karo-tx28/tx28-stk5.c b/arch/arm/boards/karo-tx28/tx28-stk5.c index 9617876..766e77b 100644 --- a/arch/arm/boards/karo-tx28/tx28-stk5.c +++ b/arch/arm/boards/karo-tx28/tx28-stk5.c @@ -393,7 +393,7 @@ tx28_get_ethaddr(); imx_enable_enetclk(); - add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0x4000, + add_generic_device("imx28-fec", 0, NULL, IMX_FEC0_BASE, 0x4000, IORESOURCE_MEM, &fec_info); ret = register_persistent_environment(); diff --git a/arch/arm/boards/karo-tx51/tx51.c b/arch/arm/boards/karo-tx51/tx51.c index 3ee0ebd..dd377c1 100644 --- a/arch/arm/boards/karo-tx51/tx51.c +++ b/arch/arm/boards/karo-tx51/tx51.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/arm/boards/karo-tx53/Makefile b/arch/arm/boards/karo-tx53/Makefile index b56ce7f..2f45976 100644 --- a/arch/arm/boards/karo-tx53/Makefile +++ b/arch/arm/boards/karo-tx53/Makefile @@ -1,2 +1,5 @@ obj-y += board.o obj-y += flash_header.o +pbl-y += flash_header.o +obj-y += lowlevel.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/karo-tx53/board.c b/arch/arm/boards/karo-tx53/board.c index c8509be..8f87c9c 100644 --- a/arch/arm/boards/karo-tx53/board.c +++ b/arch/arm/boards/karo-tx53/board.c @@ -25,7 +25,7 @@ #include -#include +#include #include #include #include @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include @@ -99,7 +101,10 @@ static int tx53_mem_init(void) { - arm_add_mem_device("ram0", 0x70000000, SZ_1G); + if (IS_ENABLED(CONFIG_TX53_REV_1011)) + arm_add_mem_device("ram0", 0x70000000, SZ_1G); + else + arm_add_mem_device("ram0", 0x70000000, SZ_512M); return 0; } @@ -203,6 +208,14 @@ ARRAY_SIZE(tx53_fec_pads)); } +#define DCD_NAME_1011 static struct imx_dcd_v2_entry dcd_entry_1011 + +#include "dcd-data-1011.h" + +#define DCD_NAME_XX30 static u32 dcd_entry_xx30 + +#include "dcd-data-xx30.h" + static int tx53_devices_init(void) { imx53_iim_register_fec_ethaddr(); @@ -214,6 +227,14 @@ armlinux_set_bootparams((void *)0x70000100); armlinux_set_architecture(MACH_TYPE_TX53); + /* rev xx30 can boot from nand or USB */ + imx53_bbu_internal_nand_register_handler("nand-xx30", + BBU_HANDLER_FLAG_DEFAULT, (void *)dcd_entry_xx30, sizeof(dcd_entry_xx30), SZ_512K); + + /* rev 1011 can boot from MMC/SD, other bootsource currently unknown */ + imx53_bbu_internal_mmc_register_handler("mmc-1011", "/dev/disk0", + 0, (void *)dcd_entry_1011, sizeof(dcd_entry_1011)); + return 0; } @@ -221,8 +242,25 @@ static int tx53_part_init(void) { - devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); + const char *envdev; + + switch (imx_bootsource()) { + case bootsource_mmc: + devfs_add_partition("disk0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("disk0", SZ_512K, SZ_1M, DEVFS_PARTITION_FIXED, "env0"); + envdev = "MMC"; + break; + case bootsource_nand: + default: + devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x80000, 0x100000, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + envdev = "NAND"; + break; + } + + printf("Using environment in %s\n", envdev); return 0; } @@ -232,7 +270,8 @@ { mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); - imx53_init_lowlevel(1000); + if (!IS_ENABLED(CONFIG_TX53_REV_XX30)) + imx53_init_lowlevel(1000); imx53_add_uart0(); return 0; diff --git a/arch/arm/boards/karo-tx53/dcd-data-1011.h b/arch/arm/boards/karo-tx53/dcd-data-1011.h new file mode 100644 index 0000000..7034ff8 --- /dev/null +++ b/arch/arm/boards/karo-tx53/dcd-data-1011.h @@ -0,0 +1,94 @@ +DCD_NAME_1011[] = { + { .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), }, + { .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), }, + { .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), }, + { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), }, + { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), }, + { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), }, + { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), }, + { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), }, + { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), }, + { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), }, + { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), }, + { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), }, + { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), }, + { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), }, + { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), }, + { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), }, + { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), }, + { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, + { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), }, + { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), }, + { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, + { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, + { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), }, + { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, + { .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), }, + { .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), }, + { .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), }, + { .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), }, + { .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), }, +}; diff --git a/arch/arm/boards/karo-tx53/dcd-data-xx30.h b/arch/arm/boards/karo-tx53/dcd-data-xx30.h new file mode 100644 index 0000000..cb982dc --- /dev/null +++ b/arch/arm/boards/karo-tx53/dcd-data-xx30.h @@ -0,0 +1,144 @@ + +#define DCD_ITEM(adr, val) cpu_to_be32(adr), cpu_to_be32(val) +#define DCD_WR_CMD(len) cpu_to_be32(0xcc << 24 | (len) << 8 | 0x04) +#define DCD_CHECK_CMD(a, b, c) cpu_to_be32(a), cpu_to_be32(b), cpu_to_be32(c) + +/* + * This board uses advanced features of the DCD which do not corporate + * well with our flash header defines. The DCD consists of commands which + * have the length econded into them. Normally the DCDs only have a single + * command (DCD_COMMAND_WRITE_TAG) which is already part of struct + * imx_flash_header_v2. Now this board uses multiple commands, so we cannot + * calculate the command length using sizeof(dcd_entry). + */ + +DCD_NAME_XX30[] = { + DCD_ITEM(0x53fd4068, 0xffcc0fff), + DCD_ITEM(0x53fd406c, 0x000fffc3), + DCD_ITEM(0x53fd4070, 0x033c0000), + DCD_ITEM(0x53fd4074, 0x00000000), + DCD_ITEM(0x53fd4078, 0x00000000), + DCD_ITEM(0x53fd407c, 0x00fff033), + DCD_ITEM(0x53fd4080, 0x0f00030f), + DCD_ITEM(0x53fd4084, 0xfff00000), + DCD_ITEM(0x53fd4088, 0x00000000), + DCD_ITEM(0x53fa8174, 0x00000011), + DCD_ITEM(0x53fa8318, 0x00000011), + DCD_ITEM(0x63fd800c, 0x00000000), + DCD_ITEM(0x53fd4014, 0x00888944), + DCD_ITEM(0x53fd4018, 0x00016154), + DCD_ITEM(0x53fa8724, 0x04000000), + DCD_ITEM(0x53fa86f4, 0x00000000), + DCD_ITEM(0x53fa8714, 0x00000000), + DCD_ITEM(0x53fa86fc, 0x00000080), + DCD_ITEM(0x53fa8710, 0x00000000), + DCD_ITEM(0x53fa8708, 0x00000040), + DCD_ITEM(0x53fa8584, 0x00280000), + DCD_ITEM(0x53fa8594, 0x00280000), + DCD_ITEM(0x53fa8560, 0x00280000), + DCD_ITEM(0x53fa8554, 0x00280000), + DCD_ITEM(0x53fa857c, 0x00a80040), + DCD_ITEM(0x53fa8590, 0x00a80040), + DCD_ITEM(0x53fa8568, 0x00a80040), + DCD_ITEM(0x53fa8558, 0x00a80040), + DCD_ITEM(0x53fa8580, 0x00280040), + DCD_ITEM(0x53fa8578, 0x00280000), + DCD_ITEM(0x53fa8564, 0x00280040), + DCD_ITEM(0x53fa8570, 0x00280000), + DCD_ITEM(0x53fa858c, 0x000000c0), + DCD_ITEM(0x53fa855c, 0x000000c0), + DCD_ITEM(0x53fa8574, 0x00280000), + DCD_ITEM(0x53fa8588, 0x00280000), + DCD_ITEM(0x53fa86f0, 0x00280000), + DCD_ITEM(0x53fa8720, 0x00280000), + DCD_ITEM(0x53fa8718, 0x00280000), + DCD_ITEM(0x53fa871c, 0x00280000), + DCD_ITEM(0x53fa8728, 0x00280000), + DCD_ITEM(0x53fa872c, 0x00280000), + DCD_ITEM(0x63fd904c, 0x001f001f), + DCD_ITEM(0x63fd9050, 0x001f001f), + DCD_ITEM(0x63fd907c, 0x011e011e), + DCD_ITEM(0x63fd9080, 0x011f0120), + DCD_ITEM(0x63fd9088, 0x3a393d3b), + DCD_ITEM(0x63fd9090, 0x3f3f3f3f), + DCD_ITEM(0x63fd9018, 0x00011740), + DCD_ITEM(0x63fd9000, 0x83190000), + DCD_ITEM(0x63fd900c, 0x3f435316), + DCD_ITEM(0x63fd9010, 0xb66e0a63), + DCD_ITEM(0x63fd9014, 0x01ff00db), + DCD_ITEM(0x63fd902c, 0x000026d2), + DCD_ITEM(0x63fd9030, 0x00430f24), + DCD_ITEM(0x63fd9008, 0x1b221010), + DCD_ITEM(0x63fd9004, 0x00030012), + DCD_ITEM(0x63fd901c, 0x00008032), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x00408031), + DCD_ITEM(0x63fd901c, 0x055080b0), + DCD_ITEM(0x63fd9020, 0x00005800), + DCD_ITEM(0x63fd9058, 0x00011112), + DCD_ITEM(0x63fd90d0, 0x00000003), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00008040), + DCD_ITEM(0x63fd9040, 0x0539002b), + DCD_CHECK_CMD(0xcf000c04, 0x63fd9040, 0x00010000), + DCD_WR_CMD(0x24), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd901c, 0x00848231), + DCD_ITEM(0x63fd901c, 0x00000000), + DCD_ITEM(0x63fd9048, 0x00000001), + DCD_CHECK_CMD(0xcf000c04, 0x63fd9048, 0x00000001), + DCD_WR_CMD(0x2c), + DCD_ITEM(0x63fd901c, 0x00048031), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd907c, 0x90000000), + DCD_CHECK_CMD(0xcf000c04, 0x63fd907c, 0x90000000), + DCD_WR_CMD(0x2c), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x00000000), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd90a4, 0x00000010), + DCD_CHECK_CMD(0xcf000c04, 0x63fd90a4, 0x00000010), + DCD_WR_CMD(0x24), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x04008010), + DCD_ITEM(0x63fd901c, 0x00048033), + DCD_ITEM(0x63fd90a0, 0x00000010), + DCD_CHECK_CMD(0xcf000c04, 0x63fd90a0, 0x00000010), + DCD_WR_CMD(0x010c), + DCD_ITEM(0x63fd901c, 0x00008033), + DCD_ITEM(0x63fd901c, 0x00000000), + DCD_ITEM(0x53fa8004, 0x00194005), + DCD_ITEM(0x53fa819c, 0x00000000), + DCD_ITEM(0x53fa81a0, 0x00000000), + DCD_ITEM(0x53fa81a4, 0x00000000), + DCD_ITEM(0x53fa81a8, 0x00000000), + DCD_ITEM(0x53fa81ac, 0x00000000), + DCD_ITEM(0x53fa81b0, 0x00000000), + DCD_ITEM(0x53fa81b4, 0x00000000), + DCD_ITEM(0x53fa81b8, 0x00000000), + DCD_ITEM(0x53fa81dc, 0x00000000), + DCD_ITEM(0x53fa81e0, 0x00000000), + DCD_ITEM(0x53fa8228, 0x00000000), + DCD_ITEM(0x53fa822c, 0x00000000), + DCD_ITEM(0x53fa8230, 0x00000000), + DCD_ITEM(0x53fa8234, 0x00000000), + DCD_ITEM(0x53fa8238, 0x00000000), + DCD_ITEM(0x53fa84ec, 0x000000e4), + DCD_ITEM(0x53fa84f0, 0x000000e4), + DCD_ITEM(0x53fa84f4, 0x000000e4), + DCD_ITEM(0x53fa84f8, 0x000000e4), + DCD_ITEM(0x53fa84fc, 0x000000e4), + DCD_ITEM(0x53fa8500, 0x000000e4), + DCD_ITEM(0x53fa8504, 0x000000e4), + DCD_ITEM(0x53fa8508, 0x000000e4), + DCD_ITEM(0x53fa852c, 0x00000004), + DCD_ITEM(0x53fa8530, 0x00000004), + DCD_ITEM(0x53fa85a0, 0x00000004), + DCD_ITEM(0x53fa85a4, 0x00000004), + DCD_ITEM(0x53fa85a8, 0x000000e4), + DCD_ITEM(0x53fa85ac, 0x000000e4), + DCD_ITEM(0x53fa85b0, 0x00000004), +}; diff --git a/arch/arm/boards/karo-tx53/flash_header.c b/arch/arm/boards/karo-tx53/flash_header.c index 9b97fab..5c6aa53 100644 --- a/arch/arm/boards/karo-tx53/flash_header.c +++ b/arch/arm/boards/karo-tx53/flash_header.c @@ -20,109 +20,31 @@ void __naked __flash_header_start go(void) { - barebox_arm_head(); + barebox_arm_imx_fcb_head(); } /* * FIXME: These are the dcd values for a Ka-Ro TX53 1011 which * is not in production. It has 1GB DDR2 memory. */ -struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = { - { .addr = cpu_to_be32(0x53fd406c), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4070), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4074), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4078), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd407c), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4080), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fd4088), .val = cpu_to_be32(0xffffffff), }, - { .addr = cpu_to_be32(0x53fa8174), .val = cpu_to_be32(0x00000011), }, - { .addr = cpu_to_be32(0x63fd800c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00200040), }, - { .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00200000), }, - { .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00280000), }, - { .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000200), }, - { .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x06000000), }, - { .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x36353b38), }, - { .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x49434942), }, - { .addr = cpu_to_be32(0x63fd90f8), .val = cpu_to_be32(0x00000800), }, - { .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01350138), }, - { .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x01380139), }, - { .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00001710), }, - { .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0x84110000), }, - { .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x4d5122d2), }, - { .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb6f18a22), }, - { .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x00c700db), }, - { .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), }, - { .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f000e), }, - { .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12272000), }, - { .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x00030012), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008010), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008020), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0a528030), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x03868031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00068031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), }, - { .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00005800), }, - { .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00033332), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00448031), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008018), }, - { .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), }, - { .addr = cpu_to_be32(0x53fa8004), .val = cpu_to_be32(0x00194005), }, - { .addr = cpu_to_be32(0x53fa819c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81a0), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81a4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81a8), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81ac), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81b0), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81b4), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81b8), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81dc), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa81e0), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8228), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa822c), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8230), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8234), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa8238), .val = cpu_to_be32(0x00000000), }, - { .addr = cpu_to_be32(0x53fa84ec), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84f0), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84f4), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84f8), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa84fc), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa8500), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa8504), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa8508), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa852c), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa8530), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa85a0), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa85a4), .val = cpu_to_be32(0x00000004), }, - { .addr = cpu_to_be32(0x53fa85a8), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa85ac), .val = cpu_to_be32(0x000000e4), }, - { .addr = cpu_to_be32(0x53fa85b0), .val = cpu_to_be32(0x00000004), }, -}; +#ifdef CONFIG_TX53_REV_1011 -#define APP_DEST 0x70000000 +#define DCD_NAME_1011 struct imx_dcd_v2_entry __dcd_entry_section dcd_entry + +#include "dcd-data-1011.h" + +#elif defined(CONFIG_TX53_REV_XX30) + +#define DCD_NAME_XX30 u32 __dcd_entry_section dcd_entry + +#include "dcd-data-xx30.h" + +#endif + +#define APP_DEST 0x71000000 + +int tx53_dcdentry_size = sizeof(dcd_entry); +void *tx53_dcd_entry = &dcd_entry; struct imx_flash_header_v2 __flash_header_section flash_header = { .header.tag = IVT_HEADER_TAG, @@ -142,6 +64,10 @@ .dcd.header.version = DCD_VERSION, .dcd.command.tag = DCD_COMMAND_WRITE_TAG, +#ifdef CONFIG_TX53_REV_1011 .dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)), +#elif defined(CONFIG_TX53_REV_XX30) + .dcd.command.length = cpu_to_be16(0x21c), +#endif .dcd.command.param = DCD_COMMAND_WRITE_PARAM, }; diff --git a/arch/arm/boards/karo-tx53/lowlevel.c b/arch/arm/boards/karo-tx53/lowlevel.c new file mode 100644 index 0000000..0ca164b --- /dev/null +++ b/arch/arm/boards/karo-tx53/lowlevel.c @@ -0,0 +1,22 @@ +#include +#include +#include +#include + +#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT + +void __naked reset(void) +{ + common_reset(); + + /* + * For the TX53 rev 8030 the SDRAM setup is not stable without + * the proper PLL setup. It will crash once we enable the MMU, + * so do the PLL setup here. + */ + if (IS_ENABLED(CONFIG_TX53_REV_XX30)) + imx53_init_lowlevel(800); + + board_init_lowlevel_return(); +} +#endif diff --git a/arch/arm/boards/pcm037/lowlevel_init.S b/arch/arm/boards/pcm037/lowlevel_init.S index a6747c2..f9ecce1 100644 --- a/arch/arm/boards/pcm037/lowlevel_init.S +++ b/arch/arm/boards/pcm037/lowlevel_init.S @@ -17,9 +17,10 @@ * */ -#include +#include #include #include +#include #define writel(val, reg) \ ldr r0, =reg; \ @@ -46,24 +47,30 @@ common_reset r0 - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + CCM_CCMR) + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) DELAY 0x40000 - writel(0x074B0BF5 | CCMR_MPE, MX31_CCM_BASE_ADDR + CCM_CCMR) - writel((0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS, MX31_CCM_BASE_ADDR + CCM_CCMR) + writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + + MX31_CCM_CCMR) + writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, + MX31_CCM_BASE_ADDR + MX31_CCM_CCMR) - writel(PDR0_CSI_PODF(0xff1) | \ - PDR0_PER_PODF(7) | \ - PDR0_HSP_PODF(3) | \ - PDR0_NFC_PODF(5) | \ - PDR0_IPG_PODF(1) | \ - PDR0_MAX_PODF(3) | \ - PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + CCM_PDR0) + writel(MX31_PDR0_CSI_PODF(0xff1) | \ + MX31_PDR0_PER_PODF(7) | \ + MX31_PDR0_HSP_PODF(3) | \ + MX31_PDR0_NFC_PODF(5) | \ + MX31_PDR0_IPG_PODF(1) | \ + MX31_PDR0_MAX_PODF(3) | \ + MX31_PDR0_MCU_PODF(0), \ + MX31_CCM_BASE_ADDR + MX31_CCM_PDR0) - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), MX31_CCM_BASE_ADDR + CCM_MPCTL) - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + CCM_SPCTL) + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | + IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), + MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL) + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | + IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + + MX31_CCM_SPCTL) /* Configure IOMUXC * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) @@ -96,19 +103,19 @@ #elif defined CONFIG_PCM037_SDRAM_BANK0_256MB #define ROWS0 ESDCTL0_ROW14 #endif - writel(0x00000004, ESDMISC) - writel(0x006ac73a, ESDCFG0) - writel(0x90100000 | ROWS0, ESDCTL0) + writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0) + writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS0, ESDCTL0) + writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x12344321, MX31_CSD0_BASE_ADDR) writel(0x12344321, MX31_CSD0_BASE_ADDR) - writel(0xb0100000 | ROWS0, ESDCTL0) + writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33) writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS0, ESDCTL0) + writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR) - writel(0x0000000c, ESDMISC) + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) #ifndef CONFIG_PCM037_SDRAM_BANK1_NONE #if defined CONFIG_PCM037_SDRAM_BANK1_128MB @@ -116,18 +123,18 @@ #elif defined CONFIG_PCM037_SDRAM_BANK1_256MB #define ROWS1 ESDCTL0_ROW14 #endif - writel(0x006ac73a, ESDCFG1) - writel(0x90100000 | ROWS1, ESDCTL1) + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1) + writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00) - writel(0xa0100000 | ROWS1, ESDCTL1) + writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0x12344321, MX31_CSD1_BASE_ADDR) writel(0x12344321, MX31_CSD1_BASE_ADDR) - writel(0xb0100000 | ROWS1, ESDCTL1) + writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33) writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000) - writel(0x80226080 | ROWS1, ESDCTL1) + writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1) writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR) - writel(0x0000000c, ESDMISC) + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC) #endif #ifdef CONFIG_NAND_IMX_BOOT diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c index 1a1688d..ff4089a 100644 --- a/arch/arm/boards/pcm037/pcm037.c +++ b/arch/arm/boards/pcm037/pcm037.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include @@ -96,7 +96,7 @@ /* Host 2 */ tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x8); tmp |= 1 << 11; - writel(tmp, IOMUXC_BASE + 0x8); + writel(tmp, MX31_IOMUXC_BASE_ADDR + 0x8); imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c index de86a06..2f93c31 100644 --- a/arch/arm/boards/pcm038/lowlevel.c +++ b/arch/arm/boards/pcm038/lowlevel.c @@ -18,7 +18,7 @@ */ #include #include -#include +#include #include #include #include @@ -34,8 +34,6 @@ #ifdef CONFIG_NAND_IMX_BOOT static void __bare_init __naked insdram(void) { - PCCR1 |= PCCR1_NFC_BAUDEN; - /* setup a stack to be able to call imx_nand_load_image() */ arm_setup_stack(STACK_BASE + STACK_SIZE - 12); @@ -57,10 +55,10 @@ common_reset(); /* ahb lite ip interface */ - AIPI1_PSR0 = 0x20040304; - AIPI1_PSR1 = 0xDFFBFCFB; - AIPI2_PSR0 = 0x00000000; - AIPI2_PSR1 = 0xFFFFFFFF; + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); /* Skip SDRAM initialization if we run from RAM */ r = get_pc(); @@ -68,37 +66,46 @@ board_init_lowlevel_return(); /* re-program the PLL prior(!) starting the SDRAM controller */ - MPCTL0 = MPCTL0_VAL; - SPCTL0 = SPCTL0_VAL; - CSCR = CSCR_VAL | CSCR_UPDATE_DIS | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART; + writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0); + writel(SPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_SPCTL0); + writel(CSCR_VAL | MX27_CSCR_UPDATE_DIS | MX27_CSCR_MPLL_RESTART | + MX27_CSCR_SPLL_RESTART, MX27_CCM_BASE_ADDR + MX27_CSCR); /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - DSCR(3) = 0x55555555; /* Set the driving strength */ - DSCR(5) = 0x55555555; - DSCR(6) = 0x55555555; - DSCR(7) = 0x00005005; - DSCR(8) = 0x15555555; + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); - writel(0x00000004, ESDMISC); /* Initial reset */ - writel(0x006ac73a, ESDCFG0); + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */ + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); for (i = 0; i < 8; i++) writel(0, 0xa0000f00); - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); writeb(0xda, 0xa0000033); writeb(0xff, 0xa1000000); writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0); + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c index 58b1ec9..715d604 100644 --- a/arch/arm/boards/pcm038/pcm038.c +++ b/arch/arm/boards/pcm038/pcm038.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -39,6 +39,7 @@ #include #include #include +#include #include "pll.h" @@ -111,8 +112,8 @@ { uint32_t reg; - reg = SPCTL0; - SPCTL0 = reg; + reg = readl(MX27_CCM_BASE_ADDR + MX27_SPCTL0); + writel(reg, MX27_CCM_BASE_ADDR + MX27_SPCTL0); return reg; } @@ -126,7 +127,8 @@ struct mc13xxx *mc13xxx = mc13xxx_get(); /* PLL registers already set to their final values? */ - if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) { + if (spctl0 == SPCTL0_VAL && + readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) { console_flush(); if (mc13xxx) { mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), @@ -161,9 +163,9 @@ /* wait for required power level to run the CPU at 400 MHz */ udelay(100000); - CSCR = CSCR_VAL_FINAL; - PCDR0 = 0x130410c3; - PCDR1 = 0x09030911; + writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR); + writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); + writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); /* Clocks have changed. Notify clients */ clock_notifier_call_chain(); @@ -173,7 +175,7 @@ } /* clock gating enable */ - GPCR = 0x00050f08; + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); return 0; } @@ -281,9 +283,6 @@ for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - PCCR0 |= PCCR0_CSPI1_EN; - PCCR1 |= PCCR1_PERCLK2_EN; - spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); imx27_add_spi0(&pcm038_spi_0_data); @@ -293,7 +292,6 @@ imx27_add_nand(&nand_info); imx27_add_fb(&pcm038_fb_data); - PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN; imx27_add_i2c0(NULL); imx27_add_i2c1(NULL); @@ -302,11 +300,8 @@ */ imx27_add_fec(&fec_info); - switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) { - case GPCR_BOOT_8BIT_NAND_2k: - case GPCR_BOOT_16BIT_NAND_2k: - case GPCR_BOOT_16BIT_NAND_512: - case GPCR_BOOT_8BIT_NAND_512: + switch (imx_bootsource()) { + case bootsource_nand: devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw"); dev_add_bb_dev("self_raw", "self0"); diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c index a6b6c83..93a1839 100644 --- a/arch/arm/boards/pcm038/pcm970.c +++ b/arch/arm/boards/pcm038/pcm970.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -112,35 +112,38 @@ mdelay(10); /* Reset PCMCIA Status Change Register */ - writel(0x00000fff, PCMCIA_PSCR); + writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR); mdelay(10); /* Check PCMCIA Input Pins Register for Card Detect & Power */ - if ((readl(PCMCIA_PIPR) & ((1 << 8) | (3 << 3))) != (1 << 8)) { + if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) & + ((1 << 8) | (3 << 3))) != (1 << 8)) { printf("CompactFlash card not found. Driver not enabled.\n"); return; } /* Disable all interrupts */ - writel(0, PCMCIA_PER); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER); /* Disable all PCMCIA banks */ for (i = 0; i < 5; i++) - writel(0, PCMCIA_POR(i)); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(i)); /* Not use internal PCOE */ - writel(0, PCMCIA_PGCR); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR); /* Setup PCMCIA bank0 for Common memory mode */ - writel(0, PCMCIA_PBR(0)); - writel(0, PCMCIA_POFR(0)); - writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, PCMCIA_POR(0)); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0)); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0)); + writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, + MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); /* Clear PCMCIA General Status Register */ - writel(0x0000001f, PCMCIA_PGSR); + writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR); /* Make PCMCIA bank0 valid */ - writel(readl(PCMCIA_POR(0)) | (1 << 29), PCMCIA_POR(0)); + writel(readl(MX27_PCMCIA_POR(0)) | (1 << 29), + MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); platform_device_register(&pcm970_ide_device); } @@ -162,7 +165,6 @@ for (i = 0; i < ARRAY_SIZE(mode); i++) imx_gpio_mode(mode[i]); - PCCR0 |= PCCR0_SDHC2_EN; imx27_add_mmc1(NULL); } diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h index a7da4a4..8bdb76d 100644 --- a/arch/arm/boards/pcm038/pll.h +++ b/arch/arm/boards/pcm038/pll.h @@ -22,35 +22,35 @@ /* define the PLL setting we want to run the system */ /* main clock divider settings immediately after reset (at 1.25 V core supply) */ -#define CSCR_VAL (CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_SP_SEL | /* 26 MHz reference */ \ - CSCR_MCU_SEL | /* 26 MHz reference */ \ - CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ - CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ - CSCR_FPM_EN | \ - CSCR_SPEN | \ - CSCR_MPEN) +#define CSCR_VAL (MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ + MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ + MX27_CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ + MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + MX27_CSCR_FPM_EN | \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN) /* main clock divider settings after core voltage increases to 1.45 V */ -#define CSCR_VAL_FINAL (CSCR_USB_DIV(3) | \ - CSCR_SD_CNT(3) | \ - CSCR_MSHC_SEL | \ - CSCR_H264_SEL | \ - CSCR_SSI1_SEL | \ - CSCR_SSI2_SEL | \ - CSCR_SP_SEL | /* 26 MHz reference */ \ - CSCR_MCU_SEL | /* 26 MHz reference */ \ - CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ - CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ - CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ - CSCR_FPM_EN | /* do not disable it! */ \ - CSCR_SPEN | \ - CSCR_MPEN) +#define CSCR_VAL_FINAL (MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ + MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ + MX27_CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ + MX27_CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ + MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + MX27_CSCR_FPM_EN | /* do not disable it! */ \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN) /* MPLL should provide a 399 MHz clock from the 26 MHz reference */ #define MPCTL0_VAL (IMX_PLL_PD(0) | \ diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c index 6bd6508..06f05ab 100644 --- a/arch/arm/boards/pcm043/lowlevel.c +++ b/arch/arm/boards/pcm043/lowlevel.c @@ -18,7 +18,7 @@ */ #include #include -#include +#include #include #include #include @@ -65,6 +65,7 @@ uint32_t r, s; unsigned long ccm_base = MX35_CCM_BASE_ADDR; unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR; + unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR; #ifdef CONFIG_NAND_IMX_BOOT unsigned int *trg, *src; int i; @@ -109,28 +110,28 @@ * End of ARM1136 init */ - writel(0x003F4208, ccm_base + CCM_CCMR); + writel(0x003F4208, ccm_base + MX35_CCM_CCMR); /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL); + writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL); + writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); /* Check silicon revision and use 532MHz if >=2.1 */ r = readl(MX35_IIM_BASE_ADDR + 0x24); if (r >= IMX35_CHIP_REVISION_2_1) - writel(CCM_PDR0_532, ccm_base + CCM_PDR0); + writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0); else - writel(CCM_PDR0_399, ccm_base + CCM_PDR0); + writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0); - r = readl(ccm_base + CCM_CGR0); + r = readl(ccm_base + MX35_CCM_CGR0); r |= 0x00300000; - writel(r, ccm_base + CCM_CGR0); + writel(r, ccm_base + MX35_CCM_CGR0); - r = readl(ccm_base + CCM_CGR1); + r = readl(ccm_base + MX35_CCM_CGR1); r |= 0x00000C00; r |= 0x00000003; - writel(r, ccm_base + CCM_CGR1); + writel(r, ccm_base + MX35_CCM_CGR1); r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); r |= 0x1000; @@ -153,17 +154,17 @@ writel(r, iomuxc_base + 0x7a4); /* MDDR init, enable mDDR*/ - writel(0x00000304, ESDMISC); /* was 0x00000004 */ + writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */ /* set timing paramters */ - writel(0x0025541F, ESDCFG0); + writel(0x0025541F, esdctl_base + IMX_ESDCFG0); /* select Precharge-All mode */ - writel(0x92220000, ESDCTL0); + writel(0x92220000, esdctl_base + IMX_ESDCTL0); /* Precharge-All */ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Load-Mode-Register mode */ - writel(0xB8001000, ESDCTL0); + writel(0xB8001000, esdctl_base + IMX_ESDCTL0); /* Load reg EMR2 */ writeb(0xda, 0x84000000); /* Load reg EMR3 */ @@ -174,18 +175,18 @@ writeb(0xda, 0x80000333); /* select Precharge-All mode */ - writel(0x92220000, ESDCTL0); + writel(0x92220000, esdctl_base + IMX_ESDCTL0); /* Precharge-All */ writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); /* select Manual-Refresh mode */ - writel(0xA2220000, ESDCTL0); + writel(0xA2220000, esdctl_base + IMX_ESDCTL0); /* Manual-Refresh 2 times */ writel(0x87654321, MX35_CSD0_BASE_ADDR); writel(0x87654321, MX35_CSD0_BASE_ADDR); /* select Load-Mode-Register mode */ - writel(0xB2220000, ESDCTL0); + writel(0xB2220000, esdctl_base + IMX_ESDCTL0); /* Load reg MR -- CL3, BL8, end DLL reset */ writeb(0xda, 0x80000233); /* Load reg EMR1 -- OCD default */ @@ -197,12 +198,12 @@ * DSIZ32-bit, BL8, COL10-bit, ROW13-bit * disable PWT & PRCT * disable Auto-Refresh */ - writel(0x82220080, ESDCTL0); + writel(0x82220080, esdctl_base + IMX_ESDCTL0); /* enable Auto-Refresh */ - writel(0x82228080, ESDCTL0); + writel(0x82228080, esdctl_base + IMX_ESDCTL0); /* enable Auto-Refresh */ - writel(0x00002000, ESDCTL1); + writel(0x00002000, esdctl_base + IMX_ESDCTL1); #ifdef CONFIG_NAND_IMX_BOOT /* skip NAND boot if not running from NFC space */ diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c index 09bc96a..abfeaf1 100644 --- a/arch/arm/boards/pcm043/pcm043.c +++ b/arch/arm/boards/pcm043/pcm043.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include @@ -127,7 +127,7 @@ led_gpio_register(&led0); - reg = readl(MX35_CCM_BASE_ADDR + CCM_RCSR); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); /* some fuses provide us vital information about connected hardware */ if (reg & 0x20000000) nand_info.width = 2; /* 16 bit */ @@ -308,10 +308,10 @@ switch (freq) { case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + CCM_MPCTL); + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); break; default: return COMMAND_ERROR_USAGE; diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S index 3c36889..8f0000f 100644 --- a/arch/arm/boards/phycard-i.MX27/lowlevel_init.S +++ b/arch/arm/boards/phycard-i.MX27/lowlevel_init.S @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include @@ -21,20 +21,26 @@ /* * DDR on CSD0 */ - writel(0x00000008, ESDMISC) /* Enable DDR SDRAM operation */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) - writel(0x55555555, DSCR(3)) /* Set the driving strength */ - writel(0x55555555, DSCR(5)) - writel(0x55555555, DSCR(6)) - writel(0x00005005, DSCR(7)) - writel(0x15555555, DSCR(8)) + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)) + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)) + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)) + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)) - writel(0x00000004, ESDMISC) /* Initial reset */ - writel(0x006ac73a, ESDCFG0) + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC) + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0) - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0) /* precharge CSD0 all banks */ + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xa0000f00 mov r1, #0 @@ -44,14 +50,17 @@ subs r2, #1 bne 1b - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) ldr r0, =0xA0000033 mov r1, #0xda strb r1, [r0] ldr r0, =0xA1000000 mov r1, #0xff strb r1, [r0] - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0) + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0) .endm .section ".text_bare_init","ax" @@ -61,10 +70,10 @@ common_reset r0 /* ahb lite ip interface */ - writel(0x20040304, AIPI1_PSR0) - writel(0xDFFBFCFB, AIPI1_PSR1) - writel(0x00000000, AIPI2_PSR0) - writel(0xFFFFFFFF, AIPI2_PSR1) + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) /* skip sdram initialization if we run from ram */ cmp pc, #0xa0000000 @@ -75,21 +84,26 @@ b board_init_lowlevel_return 1: + /* 399 MHz */ writel(IMX_PLL_PD(0) | IMX_PLL_MFD(51) | IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ + IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0) + /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ writel(IMX_PLL_PD(1) | IMX_PLL_MFD(12) | IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0) - writel(CSCR_MPLL_RESTART | CSCR_SPLL_RESTART | CSCR_ARM_SRC_MPLL | - CSCR_MCU_SEL | CSCR_SP_SEL | CSCR_FPM_EN | CSCR_MPEN | - CSCR_SPEN | CSCR_ARM_DIV(0) | CSCR_AHB_DIV(1) | CSCR_USB_DIV(3) | - CSCR_SD_CNT(3) | CSCR_SSI2_SEL | CSCR_SSI1_SEL | CSCR_H264_SEL | - CSCR_MSHC_SEL, CSCR) + writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | + MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | + MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | + MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | + MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | + MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | + MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | + MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR) sdram_init diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c index 45e59fb..0b66b04 100644 --- a/arch/arm/boards/phycard-i.MX27/pca100.c +++ b/arch/arm/boards/phycard-i.MX27/pca100.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -279,8 +279,6 @@ PD18_PF_I2C_CLK, }; - PCCR0 |= PCCR0_SDHC2_EN; - pca100_usb_init(); /* initizalize gpios */ @@ -292,8 +290,6 @@ imx27_add_mmc1(NULL); imx27_add_fb(&pca100_fb_data); - PCCR1 |= PCCR1_PERCLK2_EN; - #ifdef CONFIG_USB pca100_usb_register(); #endif diff --git a/arch/arm/boards/scb9328/lowlevel_init.S b/arch/arm/boards/scb9328/lowlevel_init.S index fabc89e..cefac84 100644 --- a/arch/arm/boards/scb9328/lowlevel_init.S +++ b/arch/arm/boards/scb9328/lowlevel_init.S @@ -12,7 +12,7 @@ * GNU General Public License for more details. */ -#include +#include #include #define CPU200 @@ -82,13 +82,13 @@ common_reset r0 /* Change PERCLK1DIV to 14 ie 14+1 */ - writel(CFG_PCDR_VAL, PCDR) + writel(CFG_PCDR_VAL, MX1_CCM_BASE_ADDR + MX1_PCDR) /* set MCU PLL Control Register 0 */ - writel(CFG_MPCTL0_VAL, MPCTL0) + writel(CFG_MPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_MPCTL0) /* set mpll restart bit */ - ldr r0, =CSCR + ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR ldr r1, [r0] orr r1,r1,#(1<<21) str r1, [r0] @@ -104,10 +104,10 @@ bne 1b /* set System PLL Control Register 0 */ - writel(CFG_SPCTL0_VAL, SPCTL0) + writel(CFG_SPCTL0_VAL, MX1_CCM_BASE_ADDR + MX1_SPCTL0) /* set spll restart bit */ - ldr r0, =CSCR + ldr r0, =MX1_CCM_BASE_ADDR + MX1_CSCR ldr r1, [r0] orr r1,r1,#(1<<22) str r1, [r0] @@ -122,7 +122,7 @@ subs r2,r2,#1 bne 1b - writel(CFG_CSCR_VAL, CSCR) + writel(CFG_CSCR_VAL, MX1_CCM_BASE_ADDR + MX1_CSCR) /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon *this..... @@ -157,9 +157,12 @@ /* SDRAM Setup */ - writel(0x910a8200, SDCTL0) /* Precharge cmd, CAS = 2 */ - writel(0x0, 0x08200000) /* Issue Precharge all Command */ - writel(0xa10a8200, SDCTL0) /* Autorefresh cmd, CAS = 2 */ + /* Precharge cmd, CAS = 2 */ + writel(0x910a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) + /* Issue Precharge all Command */ + writel(0x0, 0x08200000) + /* Autorefresh cmd, CAS = 2 */ + writel(0xa10a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) ldr r0, =0x08000000 ldr r1, =0x0 /* Issue AutoRefresh Command */ @@ -172,8 +175,10 @@ str r1, [r0] str r1, [r0] - writel(0xb10a8300, SDCTL0) - writel(0x0, 0x08223000) /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */ - writel(0x810a8200, SDCTL0) /* Set to Normal Mode CAS 2 */ + writel(0xb10a8300, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) + /* CAS Latency 2, issue Mode Register Command, Burst Length = 8 */ + writel(0x0, 0x08223000) + /* Set to Normal Mode CAS 2 */ + writel(0x810a8200, MX1_SDRAMC_BASE_ADDR + MX1_SDCTL0) b board_init_lowlevel_return diff --git a/arch/arm/boards/scb9328/scb9328.c b/arch/arm/boards/scb9328/scb9328.c index c83132a..c70852c 100644 --- a/arch/arm/boards/scb9328/scb9328.c +++ b/arch/arm/boards/scb9328/scb9328.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include @@ -29,6 +29,7 @@ #include #include #include +#include #include static struct dm9000_platform_data dm9000_data = { @@ -68,8 +69,8 @@ for (i = 0; i < ARRAY_SIZE(leds); i++) led_gpio_register(&leds[i]); -/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ - FMCR = 0x1; + /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */ + writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR); imx1_setup_eimcs(0, 0x000F2000, 0x11110d01); imx1_setup_eimcs(1, 0x000F0a00, 0x11110601); diff --git a/arch/arm/boards/tqma53/board.c b/arch/arm/boards/tqma53/board.c index 8c3d855..77535b5 100644 --- a/arch/arm/boards/tqma53/board.c +++ b/arch/arm/boards/tqma53/board.c @@ -30,7 +30,7 @@ #include #include -#include +#include #include #include #include diff --git a/arch/arm/configs/tx53stk5_defconfig b/arch/arm/configs/tx53stk5_defconfig index 95cf460..e0ab9c8 100644 --- a/arch/arm/configs/tx53stk5_defconfig +++ b/arch/arm/configs/tx53stk5_defconfig @@ -1,13 +1,16 @@ CONFIG_ARCH_IMX=y CONFIG_ARCH_IMX53=y CONFIG_MACH_TX53=y +CONFIG_TX53_REV_XX30=y CONFIG_IMX_IIM=y CONFIG_AEABI=y CONFIG_THUMB2_BAREBOX=y CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y CONFIG_ARM_UNWIND=y +CONFIG_PBL_IMAGE=y +CONFIG_IMAGE_COMPRESSION_GZIP=y CONFIG_MMU=y -CONFIG_TEXT_BASE=0x97f00000 +CONFIG_TEXT_BASE=0x87f00000 CONFIG_MALLOC_SIZE=0x2000000 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y @@ -16,7 +19,6 @@ CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y -CONFIG_DEFAULT_ENVIRONMENT_COMPRESSED_LZO=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/karo-tx53/env" CONFIG_RESET_SOURCE=y @@ -36,8 +38,6 @@ CONFIG_CMD_IOMEM=y CONFIG_CMD_CRC=y CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y CONFIG_CMD_FLASH=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y @@ -47,6 +47,8 @@ CONFIG_CMD_UIMAGE=y CONFIG_CMD_RESET=y CONFIG_CMD_GO=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y @@ -57,8 +59,6 @@ CONFIG_NET=y CONFIG_NET_DHCP=y CONFIG_NET_PING=y -CONFIG_NET_TFTP=y -CONFIG_NET_TFTP_PUSH=y CONFIG_DRIVER_NET_FEC_IMX=y CONFIG_MTD=y CONFIG_NAND=y diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index d27d4f3..cca8394 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -27,7 +27,7 @@ default 0x4fc00000 if MACH_MX6Q_ARM2 default 0x97f00000 if MACH_CCMX51 default 0x4fc00000 if MACH_SABRELITE - default 0x7fe00000 if MACH_TX53 + default 0x8fe00000 if MACH_TX53 config BOARDINFO default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 @@ -464,11 +464,22 @@ config MACH_TX53 bool "Ka-Ro TX53" select HAVE_DEFAULT_ENVIRONMENT_NEW + select MACH_HAS_LOWLEVEL_INIT help Say Y here if you are using the Ka-Ro tx53 board endchoice +if MACH_TX53 +choice + prompt "TX53 board revision" +config TX53_REV_1011 + bool "1011" +config TX53_REV_XX30 + bool "8030 / 1030" +endchoice +endif + endif if ARCH_IMX6 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e43f92e..259733e 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -1,5 +1,4 @@ obj-y += clocksource.o gpio.o -obj-$(CONFIG_RESET_SOURCE) += reset_source.o obj-$(CONFIG_ARCH_IMX1) += imx1.o iomux-v1.o clk-imx1.o obj-$(CONFIG_ARCH_IMX25) += imx25.o iomux-v3.o clk-imx25.o obj-$(CONFIG_ARCH_IMX21) += imx21.o iomux-v1.o clk-imx21.o @@ -8,11 +7,13 @@ obj-$(CONFIG_ARCH_IMX35) += imx35.o iomux-v3.o clk-imx35.o obj-$(CONFIG_ARCH_IMX51) += imx51.o iomux-v3.o imx5.o clk-imx5.o obj-$(CONFIG_ARCH_IMX53) += imx53.o iomux-v3.o imx5.o clk-imx5.o +pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o obj-$(CONFIG_ARCH_IMX6) += imx6.o iomux-v3.o usb-imx6.o clk-imx6.o obj-$(CONFIG_IMX_IIM) += iim.o obj-$(CONFIG_NAND_IMX) += nand.o obj-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o pbl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o -obj-y += devices.o +obj-y += devices.o imx.o obj-y += boot.o +obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c index 11c688e..cdddbe5 100644 --- a/arch/arm/mach-imx/boot.c +++ b/arch/arm/mach-imx/boot.c @@ -17,9 +17,65 @@ #include #include -#include +#include -#if defined(CONFIG_ARCH_IMX25) || defined(CONFIG_ARCH_IMX35) +static const char *bootsource_str[] = { + [bootsource_unknown] = "unknown", + [bootsource_nand] = "nand", + [bootsource_nor] = "nor", + [bootsource_mmc] = "mmc", + [bootsource_i2c] = "i2c", + [bootsource_spi] = "spi", + [bootsource_serial] = "serial", + [bootsource_onenand] = "onenand", + [bootsource_hd] = "harddisk", +}; + +static enum imx_bootsource bootsource; + +void imx_set_bootsource(enum imx_bootsource src) +{ + if (src >= ARRAY_SIZE(bootsource_str)) + src = bootsource_unknown; + + bootsource = src; + + setenv("barebox_loc", bootsource_str[src]); + export("barebox_loc"); +} + +enum imx_bootsource imx_bootsource(void) +{ + return bootsource; +} + +BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from"); + +/* [CTRL][TYPE] */ +static const enum imx_bootsource locations[4][4] = { + { /* CTRL = WEIM */ + bootsource_nor, + bootsource_unknown, + bootsource_onenand, + bootsource_unknown, + }, { /* CTRL == NAND */ + bootsource_nand, + bootsource_nand, + bootsource_nand, + bootsource_nand, + }, { /* CTRL == ATA, (imx35 only) */ + bootsource_unknown, + bootsource_unknown, /* might be p-ata */ + bootsource_unknown, + bootsource_unknown, + }, { /* CTRL == expansion */ + bootsource_mmc, /* note imx25 could also be: movinand, ce-ata */ + bootsource_unknown, + bootsource_i2c, + bootsource_spi, + } +}; + /* * Saves the boot source media into the $barebox_loc enviroment variable * @@ -38,43 +94,14 @@ * Note also that I suspect that the boot source pins are only sampled at * power up. */ -static int imx_25_35_boot_save_loc(void) +int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type) { const char *bareboxloc = NULL; - uint32_t reg; - unsigned int ctrl, type; + enum imx_bootsource src; - /* [CTRL][TYPE] */ - const char *const locations[4][4] = { - { /* CTRL = WEIM */ - "nor", - NULL, - "onenand", - NULL, - }, { /* CTRL == NAND */ - "nand", - "nand", - "nand", - "nand", - }, { /* CTRL == ATA, (imx35 only) */ - NULL, - NULL, /* might be p-ata */ - NULL, - NULL, - }, { /* CTRL == expansion */ - "mmc", /* note imx25 could also be: movinand, ce-ata */ - NULL, - "i2c", - "spi", - } - }; + src = locations[ctrl][type]; - reg = readl(IMX_CCM_BASE + CCM_RCSR); - ctrl = (reg >> CCM_RCSR_MEM_CTRL_SHIFT) & 0x3; - type = (reg >> CCM_RCSR_MEM_TYPE_SHIFT) & 0x3; - - bareboxloc = locations[ctrl][type]; - + imx_set_bootsource(src); if (bareboxloc) { setenv("barebox_loc", bareboxloc); export("barebox_loc"); @@ -82,32 +109,112 @@ return 0; } -coredevice_initcall(imx_25_35_boot_save_loc); -#endif -#if defined(CONFIG_ARCH_IMX27) -static int imx_27_boot_save_loc(void) +#define IMX27_SYSCTRL_GPCR 0x18 +#define IMX27_GPCR_BOOT_SHIFT 16 +#define IMX27_GPCR_BOOT_MASK (0xf << IMX27_GPCR_BOOT_SHIFT) +#define IMX27_GPCR_BOOT_UART_USB 0 +#define IMX27_GPCR_BOOT_8BIT_NAND_2k 2 +#define IMX27_GPCR_BOOT_16BIT_NAND_2k 3 +#define IMX27_GPCR_BOOT_16BIT_NAND_512 4 +#define IMX27_GPCR_BOOT_16BIT_CS0 5 +#define IMX27_GPCR_BOOT_32BIT_CS0 6 +#define IMX27_GPCR_BOOT_8BIT_NAND_512 7 + +void imx_27_boot_save_loc(void __iomem *sysctrl_base) { - switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) { - case GPCR_BOOT_UART_USB: - setenv("barebox_loc", "serial"); + enum imx_bootsource src; + uint32_t val; + + val = readl(sysctrl_base + IMX27_SYSCTRL_GPCR); + val &= IMX27_GPCR_BOOT_MASK; + val >>= IMX27_GPCR_BOOT_SHIFT; + + switch (val) { + case IMX27_GPCR_BOOT_UART_USB: + src = bootsource_serial; break; - case GPCR_BOOT_8BIT_NAND_2k: - case GPCR_BOOT_16BIT_NAND_2k: - case GPCR_BOOT_16BIT_NAND_512: - case GPCR_BOOT_8BIT_NAND_512: - setenv("barebox_loc", "nand"); + case IMX27_GPCR_BOOT_8BIT_NAND_2k: + case IMX27_GPCR_BOOT_16BIT_NAND_2k: + case IMX27_GPCR_BOOT_16BIT_NAND_512: + case IMX27_GPCR_BOOT_8BIT_NAND_512: + src = bootsource_nand; break; default: - setenv("barebox_loc", "nor"); + src = bootsource_nor; break; } - export("barebox_loc"); + imx_set_bootsource(src); +} + +#define IMX51_SRC_SBMR 0x4 +#define IMX51_SBMR_BT_MEM_TYPE_SHIFT 7 +#define IMX51_SBMR_BT_MEM_CTL_SHIFT 0 +#define IMX51_SBMR_BMOD_SHIFT 14 + +int imx51_boot_save_loc(void __iomem *src_base) +{ + enum imx_bootsource src = bootsource_unknown; + uint32_t reg; + unsigned int ctrl, type; + + reg = readl(src_base + IMX51_SRC_SBMR); + + switch ((reg >> IMX51_SBMR_BMOD_SHIFT) & 0x3) { + case 0: + case 2: + /* internal boot */ + ctrl = (reg >> IMX51_SBMR_BT_MEM_CTL_SHIFT) & 0x3; + type = (reg >> IMX51_SBMR_BT_MEM_TYPE_SHIFT) & 0x3; + + src = locations[ctrl][type]; + break; + case 1: + /* reserved */ + src = bootsource_unknown; + break; + case 3: + src = bootsource_serial; + break; + + } + + imx_set_bootsource(src); return 0; } -coredevice_initcall(imx_27_boot_save_loc); -#endif -BAREBOX_MAGICVAR(barebox_loc, "The source barebox has been booted from"); +#define IMX53_SRC_SBMR 0x4 +int imx53_boot_save_loc(void __iomem *src_base) +{ + enum imx_bootsource src = bootsource_unknown; + uint32_t cfg1 = readl(src_base + IMX53_SRC_SBMR) & 0xff; + + switch (cfg1 >> 4) { + case 2: + src = bootsource_hd; + break; + case 3: + if (cfg1 & (1 << 3)) + src = bootsource_spi; + else + src = bootsource_i2c; + break; + case 4: + case 5: + case 6: + case 7: + src = bootsource_mmc; + break; + default: + break; + } + + if (cfg1 & (1 << 7)) + src = bootsource_nand; + + imx_set_bootsource(src); + + return 0; +} diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 45e9c66..0d04a92 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -96,9 +96,18 @@ return 0; } +static __maybe_unused struct of_device_id imx1_ccm_dt_ids[] = { + { + .compatible = "fsl,imx1-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx1_ccm_driver = { .probe = imx1_ccm_probe, .name = "imx1-ccm", + .of_compatible = DRV_OF_COMPAT(imx1_ccm_dt_ids), }; static int imx1_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c index 69aaa9e..9e7af81 100644 --- a/arch/arm/mach-imx/clk-imx21.c +++ b/arch/arm/mach-imx/clk-imx21.c @@ -47,7 +47,7 @@ enum imx21_clks { ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1, - per2, per3, per4, usb_div, nfc_div, clk_max + per2, per3, per4, usb_div, nfc_div, lcdc_per_gate, clk_max }; static struct clk *clks[clk_max]; @@ -70,6 +70,16 @@ base = dev_request_mem_region(dev, 0); + writel((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | + (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12) | + (1 << 13) | (1 << 14) | (1 << 19) | (1 << 22) | + (1 << 24) | (1 << 26) | (1 << 30), + base + CCM_PCCR0); + + writel((1 << 23) | (1 << 24) | (1 << 25) | (1 << 26) | (1 << 27) | + (1 << 28) | (1 << 29) | (1 << 30) | (1 << 31), + base + CCM_PCCR1); + clks[ckil] = clk_fixed("ckil", lref); clks[ckih] = clk_fixed("ckih", href); clks[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); @@ -88,6 +98,7 @@ clks[per4] = imx_clk_divider("per4", "mpll", base + CCM_PCDR1, 24, 6); clks[usb_div] = imx_clk_divider("usb_div", "spll", base + CCM_CSCR, 26, 3); clks[nfc_div] = imx_clk_divider("nfc_div", "ipg", base + CCM_PCDR0, 12, 4); + clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3", base + CCM_PCCR0, 18); clkdev_add_physbase(clks[per1], MX21_GPT1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per1], MX21_GPT2_BASE_ADDR, NULL); @@ -98,18 +109,27 @@ clkdev_add_physbase(clks[per1], MX21_UART4_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2], MX21_CSPI1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2], MX21_CSPI2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[per2], MX21_CSPI3_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX21_I2C_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX21_SDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX21_SDHC2_BASE_ADDR, NULL); - clkdev_add_physbase(clks[per3], MX21_CSPI3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[per3], MX21_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[lcdc_per_gate], MX21_LCDC_BASE_ADDR, NULL); return 0; } +static __maybe_unused struct of_device_id imx21_ccm_dt_ids[] = { + { + .compatible = "fsl,imx21-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx21_ccm_driver = { .probe = imx21_ccm_probe, .name = "imx21-ccm", + .of_compatible = DRV_OF_COMPAT(imx21_ccm_dt_ids), }; static int imx21_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c index 9583cb4..38f15a6 100644 --- a/arch/arm/mach-imx/clk-imx25.c +++ b/arch/arm/mach-imx/clk-imx25.c @@ -55,7 +55,7 @@ per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel, per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5, per6, per7, per8, per9, per10, per11, per12, per13, per14, per15, - clk_max + lcdc_per_gate, clk_max }; static struct clk *clks[clk_max]; @@ -132,6 +132,7 @@ clks[per13] = imx_clk_divider("per13", "per13_sel", base + CCM_PCDR3, 8, 6); clks[per14] = imx_clk_divider("per14", "per14_sel", base + CCM_PCDR3, 16, 6); clks[per15] = imx_clk_divider("per15", "per15_sel", base + CCM_PCDR3, 24, 6); + clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per7", base + CCM_CGCR0, 7); clkdev_add_physbase(clks[per15], MX25_UART1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per15], MX25_UART2_BASE_ADDR, NULL); @@ -148,13 +149,23 @@ clkdev_add_physbase(clks[ipg], MX25_CSPI3_BASE_ADDR, NULL); clkdev_add_physbase(clks[per3], MX25_ESDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per4], MX25_ESDHC2_BASE_ADDR, NULL); + clkdev_add_physbase(clks[lcdc_per_gate], MX25_LCDC_BASE_ADDR, NULL); return 0; } +static __maybe_unused struct of_device_id imx25_ccm_dt_ids[] = { + { + .compatible = "fsl,imx25-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx25_ccm_driver = { .probe = imx25_ccm_probe, .name = "imx25-ccm", + .of_compatible = DRV_OF_COMPAT(imx25_ccm_dt_ids), }; static int imx25_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index abfde0f..222d2a6 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "clk.h" @@ -26,10 +27,73 @@ #define CCM_PMCOUNT 0x30 #define CCM_WKGDCTL 0x34 +#define PCCR0_SSI2_EN (1 << 0) +#define PCCR0_SSI1_EN (1 << 1) +#define PCCR0_SLCDC_EN (1 << 2) +#define PCCR0_SDHC3_EN (1 << 3) +#define PCCR0_SDHC2_EN (1 << 4) +#define PCCR0_SDHC1_EN (1 << 5) +#define PCCR0_SDC_EN (1 << 6) +#define PCCR0_SAHARA_EN (1 << 7) +#define PCCR0_RTIC_EN (1 << 8) +#define PCCR0_RTC_EN (1 << 9) +#define PCCR0_PWM_EN (1 << 11) +#define PCCR0_OWIRE_EN (1 << 12) +#define PCCR0_MSHC_EN (1 << 13) +#define PCCR0_LCDC_EN (1 << 14) +#define PCCR0_KPP_EN (1 << 15) +#define PCCR0_IIM_EN (1 << 16) +#define PCCR0_I2C2_EN (1 << 17) +#define PCCR0_I2C1_EN (1 << 18) +#define PCCR0_GPT6_EN (1 << 19) +#define PCCR0_GPT5_EN (1 << 20) +#define PCCR0_GPT4_EN (1 << 21) +#define PCCR0_GPT3_EN (1 << 22) +#define PCCR0_GPT2_EN (1 << 23) +#define PCCR0_GPT1_EN (1 << 24) +#define PCCR0_GPIO_EN (1 << 25) +#define PCCR0_FEC_EN (1 << 26) +#define PCCR0_EMMA_EN (1 << 27) +#define PCCR0_DMA_EN (1 << 28) +#define PCCR0_CSPI3_EN (1 << 29) +#define PCCR0_CSPI2_EN (1 << 30) +#define PCCR0_CSPI1_EN (1 << 31) + +#define PCCR1_MSHC_BAUDEN (1 << 2) +#define PCCR1_NFC_BAUDEN (1 << 3) +#define PCCR1_SSI2_BAUDEN (1 << 4) +#define PCCR1_SSI1_BAUDEN (1 << 5) +#define PCCR1_H264_BAUDEN (1 << 6) +#define PCCR1_PERCLK4_EN (1 << 7) +#define PCCR1_PERCLK3_EN (1 << 8) +#define PCCR1_PERCLK2_EN (1 << 9) +#define PCCR1_PERCLK1_EN (1 << 10) +#define PCCR1_HCLK_USB (1 << 11) +#define PCCR1_HCLK_SLCDC (1 << 12) +#define PCCR1_HCLK_SAHARA (1 << 13) +#define PCCR1_HCLK_RTIC (1 << 14) +#define PCCR1_HCLK_LCDC (1 << 15) +#define PCCR1_HCLK_H264 (1 << 16) +#define PCCR1_HCLK_FEC (1 << 17) +#define PCCR1_HCLK_EMMA (1 << 18) +#define PCCR1_HCLK_EMI (1 << 19) +#define PCCR1_HCLK_DMA (1 << 20) +#define PCCR1_HCLK_CSI (1 << 21) +#define PCCR1_HCLK_BROM (1 << 22) +#define PCCR1_HCLK_ATA (1 << 23) +#define PCCR1_WDT_EN (1 << 24) +#define PCCR1_USB_EN (1 << 25) +#define PCCR1_UART6_EN (1 << 26) +#define PCCR1_UART5_EN (1 << 27) +#define PCCR1_UART4_EN (1 << 28) +#define PCCR1_UART3_EN (1 << 29) +#define PCCR1_UART2_EN (1 << 30) +#define PCCR1_UART1_EN (1 << 31) + enum mx27_clks { dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div, per2_div, per3_div, per4_div, usb_div, cpu_sel, clko_sel, cpu_div, clko_div, - clko_en, clk_max + clko_en, lcdc_per_gate, clk_max }; static struct clk *clks[clk_max]; @@ -72,18 +136,18 @@ base = dev_request_mem_region(dev, 0); writel(PCCR0_SDHC3_EN | PCCR0_SDHC2_EN | PCCR0_SDHC1_EN | - PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_IIM_EN | PCCR0_I2C2_EN | - PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN | PCCR0_GPT4_EN | - PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN | PCCR0_GPIO_EN | - PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN | PCCR0_CSPI1_EN, + PCCR0_PWM_EN | PCCR0_KPP_EN | PCCR0_LCDC_EN | PCCR0_IIM_EN | + PCCR0_I2C2_EN | PCCR0_I2C1_EN | PCCR0_GPT6_EN | PCCR0_GPT5_EN | + PCCR0_GPT4_EN | PCCR0_GPT3_EN | PCCR0_GPT2_EN | PCCR0_GPT1_EN | + PCCR0_GPIO_EN | PCCR0_FEC_EN | PCCR0_CSPI3_EN | PCCR0_CSPI2_EN | + PCCR0_CSPI1_EN, base + CCM_PCCR0); - writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK3_EN | - PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN | PCCR1_HCLK_USB | - PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | PCCR1_WDT_EN | PCCR1_USB_EN | - PCCR1_UART6_EN | PCCR1_UART5_EN | PCCR1_UART4_EN | - PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN, - base + CCM_PCCR1); + writel(PCCR1_NFC_BAUDEN | PCCR1_PERCLK4_EN | PCCR1_PERCLK2_EN | PCCR1_PERCLK1_EN | + PCCR1_HCLK_USB | PCCR1_HCLK_LCDC | PCCR1_HCLK_FEC | PCCR1_HCLK_EMI | + PCCR1_WDT_EN | PCCR1_USB_EN | PCCR1_UART6_EN | PCCR1_UART5_EN | + PCCR1_UART4_EN | PCCR1_UART3_EN | PCCR1_UART2_EN | PCCR1_UART1_EN, + base + CCM_PCCR1); clks[dummy] = clk_fixed("dummy", 0); clks[ckih] = clk_fixed("ckih", 26000000); @@ -92,7 +156,7 @@ clks[spll] = imx_clk_pllv1("spll", "ckih", base + CCM_SPCTL0); clks[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); - if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0) { + if (imx_silicon_revision() >= IMX_CHIP_REV_2_0) { clks[ahb] = imx_clk_divider("ahb", "mpll_main2", base + CCM_CSCR, 8, 2); clks[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); } else { @@ -110,11 +174,12 @@ ARRAY_SIZE(cpu_sel_clks)); clks[clko_sel] = imx_clk_mux("clko_sel", base + CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); - if (imx_silicon_revision() >= IMX27_CHIP_REVISION_2_0) + if (imx_silicon_revision() >= IMX_CHIP_REV_2_0) clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 12, 2); else clks[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", base + CCM_CSCR, 13, 3); clks[clko_div] = imx_clk_divider("clko_div", "clko_sel", base + CCM_PCDR0, 22, 3); + clks[lcdc_per_gate] = imx_clk_gate("lcdc_per_gate", "per3_div", base + CCM_PCCR1, 7); clkdev_add_physbase(clks[per1_div], MX27_GPT1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per1_div], MX27_GPT2_BASE_ADDR, NULL); @@ -136,15 +201,24 @@ clkdev_add_physbase(clks[per2_div], MX27_SDHC1_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2_div], MX27_SDHC2_BASE_ADDR, NULL); clkdev_add_physbase(clks[per2_div], MX27_SDHC3_BASE_ADDR, NULL); - clkdev_add_physbase(clks[per3_div], MX27_LCDC_BASE_ADDR, NULL); + clkdev_add_physbase(clks[lcdc_per_gate], MX27_LCDC_BASE_ADDR, NULL); clkdev_add_physbase(clks[ipg], MX27_FEC_BASE_ADDR, NULL); return 0; } +static __maybe_unused struct of_device_id imx27_ccm_dt_ids[] = { + { + .compatible = "fsl,imx27-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx27_ccm_driver = { .probe = imx27_ccm_probe, .name = "imx27-ccm", + .of_compatible = DRV_OF_COMPAT(imx27_ccm_dt_ids), }; static int imx27_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index cf8963a..aa1b652 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c @@ -121,9 +121,18 @@ return 0; } +static __maybe_unused struct of_device_id imx31_ccm_dt_ids[] = { + { + .compatible = "fsl,imx31-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx31_ccm_driver = { .probe = imx31_ccm_probe, .name = "imx31-ccm", + .of_compatible = DRV_OF_COMPAT(imx31_ccm_dt_ids), }; static int imx31_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c index dfa7561..5b5a9e7 100644 --- a/arch/arm/mach-imx/clk-imx35.c +++ b/arch/arm/mach-imx/clk-imx35.c @@ -174,9 +174,18 @@ return 0; } +static __maybe_unused struct of_device_id imx35_ccm_dt_ids[] = { + { + .compatible = "fsl,imx35-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx35_ccm_driver = { .probe = imx35_ccm_probe, .name = "imx35-ccm", + .of_compatible = DRV_OF_COMPAT(imx35_ccm_dt_ids), }; static int imx35_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c index 365fcb3..050842d 100644 --- a/arch/arm/mach-imx/clk-imx5.c +++ b/arch/arm/mach-imx/clk-imx5.c @@ -13,7 +13,8 @@ #include #include #include -#include +#include +#include #include "clk.h" @@ -233,9 +234,18 @@ return 0; } +static __maybe_unused struct of_device_id imx51_ccm_dt_ids[] = { + { + .compatible = "fsl,imx51-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx51_ccm_driver = { .probe = imx51_ccm_probe, .name = "imx51-ccm", + .of_compatible = DRV_OF_COMPAT(imx51_ccm_dt_ids), }; static int imx51_ccm_init(void) @@ -285,9 +295,18 @@ return 0; } +static __maybe_unused struct of_device_id imx53_ccm_dt_ids[] = { + { + .compatible = "fsl,imx53-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx53_ccm_driver = { .probe = imx53_ccm_probe, .name = "imx53-ccm", + .of_compatible = DRV_OF_COMPAT(imx53_ccm_dt_ids), }; static int imx53_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c index 19a8bc6..a1da47a 100644 --- a/arch/arm/mach-imx/clk-imx6.c +++ b/arch/arm/mach-imx/clk-imx6.c @@ -294,9 +294,18 @@ return 0; } +static __maybe_unused struct of_device_id imx6_ccm_dt_ids[] = { + { + .compatible = "fsl,imx6-ccm", + }, { + /* sentinel */ + } +}; + static struct driver_d imx6_ccm_driver = { .probe = imx6_ccm_probe, .name = "imx6-ccm", + .of_compatible = DRV_OF_COMPAT(imx6_ccm_dt_ids), }; static int imx6_ccm_init(void) diff --git a/arch/arm/mach-imx/clk-pllv2.c b/arch/arm/mach-imx/clk-pllv2.c index 6907269..7e087c1 100644 --- a/arch/arm/mach-imx/clk-pllv2.c +++ b/arch/arm/mach-imx/clk-pllv2.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c index a99eec5..e337e87 100644 --- a/arch/arm/mach-imx/clk-pllv3.c +++ b/arch/arm/mach-imx/clk-pllv3.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index 3d79950..0f30082 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -19,6 +19,12 @@ return clk_mux(name, reg, shift, width, parents, num_parents); } +static inline struct clk *imx_clk_gate(const char *name, const char *parent, + void __iomem *reg, u8 shift) +{ + return clk_gate(name, parent, reg, shift); +} + struct clk *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c index 69a688c..e18685e 100644 --- a/arch/arm/mach-imx/clocksource.c +++ b/arch/arm/mach-imx/clocksource.c @@ -32,7 +32,6 @@ #include #include #include -#include #include /* Part 1: Registers */ @@ -108,18 +107,6 @@ /* setup GP Timer 1 */ writel(TCTL_SWR, timer_base + GPT_TCTL); -#ifdef CONFIG_ARCH_IMX21 - PCCR1 |= PCCR1_GPT1_EN; -#endif -#ifdef CONFIG_ARCH_IMX27 - PCCR0 |= PCCR0_GPT1_EN; - PCCR1 |= PCCR1_PERCLK1_EN; -#endif -#ifdef CONFIG_ARCH_IMX25 - writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 19), - IMX_CCM_BASE + CCM_CGCR1); -#endif - for (i = 0; i < 100; i++) writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */ @@ -179,40 +166,3 @@ return platform_driver_register(&imx_gpt_driver); } coredevice_initcall(imx_gpt_init); - -/* - * Watchdog Registers - */ -#ifdef CONFIG_ARCH_IMX1 -#define WDOG_WCR 0x00 /* Watchdog Control Register */ -#define WDOG_WSR 0x04 /* Watchdog Service Register */ -#define WDOG_WSTR 0x08 /* Watchdog Status Register */ -#define WDOG_WCR_WDE (1 << 0) -#else -#define WDOG_WCR 0x00 /* Watchdog Control Register */ -#define WDOG_WSR 0x02 /* Watchdog Service Register */ -#define WDOG_WSTR 0x04 /* Watchdog Status Register */ -#define WDOG_WCR_WDE (1 << 2) -#endif - -/* - * Reset the cpu by setting up the watchdog timer and let it time out - */ -void __noreturn reset_cpu (unsigned long addr) -{ - void __iomem *wdt = IOMEM(IMX_WDT_BASE); - - /* Disable watchdog and set Time-Out field to 0 */ - writew(0x0, wdt + WDOG_WCR); - - /* Write Service Sequence */ - writew(0x5555, wdt + WDOG_WSR); - writew(0xaaaa, wdt + WDOG_WSR); - - /* Enable watchdog */ - writew(WDOG_WCR_WDE, wdt + WDOG_WCR); - - while (1); - /*NOTREACHED*/ -} -EXPORT_SYMBOL(reset_cpu); diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c index 9fde84f..4ee4e6c 100644 --- a/arch/arm/mach-imx/devices.c +++ b/arch/arm/mach-imx/devices.c @@ -8,9 +8,14 @@ IORESOURCE_MEM, pdata); } -struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata) +struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata) { - return imx_add_device("fec_imx", -1, base, 0x1000, pdata); + return imx_add_device("imx27-fec", -1, base, 0x1000, pdata); +} + +struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata) +{ + return imx_add_device("imx6-fec", -1, base, 0x1000, pdata); } struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata) @@ -23,9 +28,14 @@ return imx_add_device("i2c-fsl", id, base, 0x1000, pdata); } -struct device_d *imx_add_uart(void *base, int id) +struct device_d *imx_add_uart_imx1(void *base, int id) { - return imx_add_device("imx_serial", id, base, 0x1000, NULL); + return imx_add_device("imx1-uart", id, base, 0x1000, NULL); +} + +struct device_d *imx_add_uart_imx21(void *base, int id) +{ + return imx_add_device("imx21-uart", id, base, 0x1000, NULL); } struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata) diff --git a/arch/arm/mach-imx/external-nand-boot.c b/arch/arm/mach-imx/external-nand-boot.c index a590992..2e9e475 100644 --- a/arch/arm/mach-imx/external-nand-boot.c +++ b/arch/arm/mach-imx/external-nand-boot.c @@ -17,7 +17,11 @@ #include #include #include -#include +#include +#include +#include +#include +#include static void __bare_init noinline imx_nandboot_wait_op_done(void *regs) { @@ -116,7 +120,13 @@ static int __maybe_unused is_pagesize_2k(void) { #ifdef CONFIG_ARCH_IMX21 - if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5)) + if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5)) + return 1; + else + return 0; +#endif +#if defined(CONFIG_ARCH_IMX25) + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8)) return 1; else return 0; @@ -128,13 +138,13 @@ return 0; #endif #ifdef CONFIG_ARCH_IMX31 - if (readl(IMX_CCM_BASE + CCM_RCSR) & RCSR_NFMS) + if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS) return 1; else return 0; #endif -#if defined(CONFIG_ARCH_IMX35) || defined(CONFIG_ARCH_IMX25) - if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 8)) +#if defined(CONFIG_ARCH_IMX35) + if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8)) return 1; else return 0; @@ -163,7 +173,21 @@ blocksize = 16 * 1024; } - base = (void __iomem *)IMX_NFC_BASE; +#ifdef CONFIG_ARCH_IMX21 + base = (void __iomem *)MX21_NFC_BASE_ADDR; +#endif +#ifdef CONFIG_ARCH_IMX25 + base = (void __iomem *)MX25_NFC_BASE_ADDR; +#endif +#ifdef CONFIG_ARCH_IMX27 + base = (void __iomem *)MX27_NFC_BASE_ADDR; +#endif +#ifdef CONFIG_ARCH_IMX31 + base = (void __iomem *)MX31_NFC_BASE_ADDR; +#endif +#ifdef CONFIG_ARCH_IMX35 + base = (void __iomem *)MX35_NFC_BASE_ADDR; +#endif if (nfc_is_v21()) { regs = base + 0x1e00; spare0 = base + 0x1000; diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c index cd7655a..1bf4100 100644 --- a/arch/arm/mach-imx/gpio.c +++ b/arch/arm/mach-imx/gpio.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c new file mode 100644 index 0000000..85d10cf --- /dev/null +++ b/arch/arm/mach-imx/imx-bbu-internal.c @@ -0,0 +1,543 @@ +/* + * imx-bbu-internal.c - i.MX specific update functions for internal boot + * + * Copyright (c) 2012 Sascha Hauer , Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define IMX_INTERNAL_NAND_BBU + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define FLASH_HEADER_OFFSET_MMC 0x400 + +#define IMX_INTERNAL_FLAG_NAND (1 << 0) +#define IMX_INTERNAL_FLAG_KEEP_DOSPART (1 << 1) + +struct imx_internal_bbu_handler { + struct bbu_handler handler; + const void *dcd; + int dcdsize; + unsigned long app_dest; + unsigned long flash_header_offset; + size_t device_size; + unsigned long flags; +}; + +/* + * Actually write an image to the target device, eventually keeping a + * DOS partition table on the device + */ +static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler, + struct bbu_data *data, void *buf, int image_len) +{ + int fd, ret; + + fd = open(data->devicefile, O_RDWR | O_CREAT); + if (fd < 0) + return fd; + + if (imx_handler->flags & IMX_INTERNAL_FLAG_KEEP_DOSPART) { + void *mbr = xzalloc(512); + + debug("%s: reading DOS partition table in order to keep it\n"); + + ret = read(fd, mbr, 512); + if (ret < 0) { + free(mbr); + goto err_close; + } + + memcpy(buf + 0x1b8, mbr + 0x1b8, 0x48); + free(buf); + + ret = lseek(fd, 0, SEEK_SET); + if (ret) + goto err_close; + } + + ret = write(fd, buf, image_len); + if (ret < 0) + goto err_close; + + ret = 0; + +err_close: + close(fd); + + return ret; +} + +/* + * Update barebox on a v1 type internal boot (i.MX25, i.MX35, i.MX51) + * + * This constructs a DCD header, adds the specific DCD data and writes + * the resulting image to the device. Currently this handles MMC/SD + * devices. + */ +static int imx_bbu_internal_v1_update(struct bbu_handler *handler, struct bbu_data *data) +{ + struct imx_internal_bbu_handler *imx_handler = + container_of(handler, struct imx_internal_bbu_handler, handler); + struct imx_flash_header *flash_header; + unsigned long flash_header_offset = imx_handler->flash_header_offset; + u32 *dcd_image_size; + void *imx_pre_image; + int imx_pre_image_size = 0x2000; + int ret, image_len; + void *buf; + + if (file_detect_type(data->image) != filetype_arm_barebox) { + if (!bbu_force(data, "Not an ARM barebox image")) + return -EINVAL; + } + + ret = bbu_confirm(data); + if (ret) + return ret; + + printf("updating to %s\n", data->devicefile); + + imx_pre_image = xzalloc(imx_pre_image_size); + flash_header = imx_pre_image + flash_header_offset; + + flash_header->app_code_jump_vector = imx_handler->app_dest + 0x1000; + flash_header->app_code_barker = APP_CODE_BARKER; + flash_header->app_code_csf = 0; + flash_header->dcd_ptr_ptr = imx_handler->app_dest + flash_header_offset + + offsetof(struct imx_flash_header, dcd); + flash_header->super_root_key = 0; + flash_header->dcd = imx_handler->app_dest + flash_header_offset + + offsetof(struct imx_flash_header, dcd_barker); + flash_header->app_dest = imx_handler->app_dest; + flash_header->dcd_barker = DCD_BARKER; + flash_header->dcd_block_len = imx_handler->dcdsize; + + memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize); + + dcd_image_size = (imx_pre_image + flash_header_offset + sizeof(*flash_header) + imx_handler->dcdsize); + + *dcd_image_size = ALIGN(imx_pre_image_size + data->len, 4096); + + /* Create a buffer containing header and image data */ + image_len = data->len + imx_pre_image_size; + buf = xzalloc(image_len); + memcpy(buf, imx_pre_image, imx_pre_image_size); + memcpy(buf + imx_pre_image_size, data->image, data->len); + + ret = imx_bbu_write_device(imx_handler, data, buf, image_len); + + free(buf); + + free(imx_pre_image); + + return ret; +} + +#define DBBT_MAGIC 0x44424254 +#define FCB_MAGIC 0x20424346 + +/* + * Write an image to NAND. This creates a FCB header and a DBBT (Discovered Bad + * Block Table). The DBBT is initialized with the bad blocks known from the mtd + * layer. + */ +static int imx_bbu_internal_v2_write_nand_dbbt(struct imx_internal_bbu_handler *imx_handler, + struct bbu_data *data, void *image, int image_len) +{ + struct mtd_info_user meminfo; + int fd; + struct stat s; + int size_available, size_need; + int ret; + uint32_t *ptr, *num_bb, *bb; + uint64_t offset; + int block = 0, len, now, blocksize; + + ret = stat(data->devicefile, &s); + if (ret) + return ret; + + size_available = s.st_size; + + fd = open(data->devicefile, O_RDWR); + if (fd < 0) + return fd; + + ret = ioctl(fd, MEMGETINFO, &meminfo); + if (ret) + goto out; + + blocksize = meminfo.erasesize; + + ptr = image + 0x4; + *ptr++ = FCB_MAGIC; /* FCB */ + *ptr++ = 1; /* FCB version */ + + ptr = image + 0x78; /* DBBT start page */ + *ptr = 4; + + ptr = image + 4 * 2048 + 4; + *ptr++ = DBBT_MAGIC; /* DBBT */ + *ptr = 1; /* DBBT version */ + + ptr = (u32*)(image + 0x2010); + /* + * This is marked as reserved in the i.MX53 reference manual, but + * must be != 0. Otherwise the ROM ignores the DBBT + */ + *ptr = 1; + + ptr = (u32*)(image + 0x4004); /* start of DBBT */ + num_bb = ptr; + bb = ptr + 1; + offset = 0; + + size_need = data->len + 0x8000; + + /* + * Collect bad blocks and construct DBBT + */ + while (size_need > 0) { + ret = ioctl(fd, MEMGETBADBLOCK, &offset); + if (ret < 0) + goto out; + + if (ret) { + if (!offset) { + printf("1st block is bad. This is not supported\n"); + ret = -EINVAL; + goto out; + } + + debug("bad block at 0x%08llx\n", offset); + *num_bb += 1; + if (*num_bb == 425) { + /* Maximum number of bad blocks the ROM supports */ + printf("maximum number of bad blocks reached\n"); + ret = -ENOSPC; + goto out; + } + *bb++ = block; + offset += blocksize; + block++; + continue; + } + size_need -= blocksize; + size_available -= blocksize; + offset += blocksize; + block++; + + if (size_available < 0) { + printf("device is too small"); + ret = -ENOSPC; + goto out; + } + } + + debug("total image size: 0x%08x. Space needed including bad blocks: 0x%08x\n", + data->len + 0x8000, + data->len + 0x8000 + *num_bb * blocksize); + + if (data->len + 0x8000 + *num_bb * blocksize > imx_handler->device_size) { + printf("needed space (0x%08x) exceeds partition space (0x%08x)\n", + data->len + 0x8000 + *num_bb * blocksize, + imx_handler->device_size); + ret = -ENOSPC; + goto out; + } + + len = data->len + 0x8000; + offset = 0; + + /* + * Write image to NAND skipping bad blocks + */ + while (len > 0) { + now = min(len, blocksize); + + ret = ioctl(fd, MEMGETBADBLOCK, &offset); + if (ret < 0) + goto out; + + if (ret) { + ret = lseek(fd, offset + blocksize, SEEK_SET); + if (ret < 0) + goto out; + offset += blocksize; + continue; + } + + debug("writing %d bytes at 0x%08llx\n", now, offset); + + ret = erase(fd, blocksize, offset); + if (ret) + goto out; + + ret = write(fd, image, now); + if (ret < 0) + goto out; + + len -= now; + image += now; + offset += now; + } + + ret = 0; + +out: + close(fd); + + return ret; +} + +/* + * Update barebox on a v2 type internal boot (i.MX53) + * + * This constructs a DCD header, adds the specific DCD data and writes + * the resulting image to the device. Currently this handles MMC/SD + * and NAND devices. + */ +static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_data *data) +{ + struct imx_internal_bbu_handler *imx_handler = + container_of(handler, struct imx_internal_bbu_handler, handler); + struct imx_flash_header_v2 *flash_header; + unsigned long flash_header_offset = imx_handler->flash_header_offset; + void *imx_pre_image; + int imx_pre_image_size; + int ret, image_len; + void *buf; + + if (file_detect_type(data->image) != filetype_arm_barebox) { + if (!bbu_force(data, "Not an ARM barebox image")) + return -EINVAL; + } + + ret = bbu_confirm(data); + if (ret) + return ret; + + printf("updating to %s\n", data->devicefile); + + if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) + /* NAND needs additional space for the DBBT */ + imx_pre_image_size = 0x8000; + else + imx_pre_image_size = 0x2000; + + imx_pre_image = xzalloc(imx_pre_image_size); + flash_header = imx_pre_image + flash_header_offset; + + flash_header->header.tag = IVT_HEADER_TAG; + flash_header->header.length = cpu_to_be16(32); + flash_header->header.version = IVT_VERSION; + + flash_header->entry = imx_handler->app_dest + imx_pre_image_size; + flash_header->dcd_ptr = imx_handler->app_dest + flash_header_offset + + offsetof(struct imx_flash_header_v2, dcd); + flash_header->boot_data_ptr = imx_handler->app_dest + + flash_header_offset + offsetof(struct imx_flash_header_v2, boot_data); + flash_header->self = imx_handler->app_dest + flash_header_offset; + + flash_header->boot_data.start = imx_handler->app_dest; + flash_header->boot_data.size = ALIGN(imx_pre_image_size + data->len, 4096);; + + flash_header->dcd.header.tag = DCD_HEADER_TAG; + flash_header->dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + + imx_handler->dcdsize); + flash_header->dcd.header.version = DCD_VERSION; + + /* Add dcd data */ + memcpy((void *)flash_header + sizeof(*flash_header), imx_handler->dcd, imx_handler->dcdsize); + + /* Create a buffer containing header and image data */ + image_len = data->len + imx_pre_image_size; + buf = xzalloc(image_len); + memcpy(buf, imx_pre_image, imx_pre_image_size); + memcpy(buf + imx_pre_image_size, data->image, data->len); + + if (imx_handler->flags & IMX_INTERNAL_FLAG_NAND) { + ret = imx_bbu_internal_v2_write_nand_dbbt(imx_handler, data, buf, + image_len); + goto out_free_buf; + } + + ret = imx_bbu_write_device(imx_handler, data, buf, image_len); + +out_free_buf: + free(buf); + + free(imx_pre_image); + return ret; +} + +/* + * On the i.MX53 the dcd data can contain several commands. Each of them must + * have its length encoded into it. We can't express that during compile time, + * so use this function if you are using multiple dcd commands and wish to + * concatenate them together to a single dcd table with the correct sizes for + * each command. + */ +void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries) +{ + int i; + unsigned int dcdsize = 0, pos = 0; + void *dcdptr; + + for (i = 0; i < num_entries; i++) + dcdsize += table[i].size; + + dcdptr = xmalloc(dcdsize); + + for (i = 0; i < num_entries; i++) { + u32 *current = dcdptr + pos; + memcpy(current, table[i].data, table[i].size); + *current |= cpu_to_be32(table[i].size << 8); + pos += table[i].size; + } + + return dcdptr; +} + +static struct imx_internal_bbu_handler *__init_handler(const char *name, char *devicefile, + unsigned long flags) +{ + struct imx_internal_bbu_handler *imx_handler; + struct bbu_handler *handler; + + imx_handler = xzalloc(sizeof(*imx_handler)); + handler = &imx_handler->handler; + handler->devicefile = devicefile; + handler->name = name; + handler->flags = flags; + + return imx_handler; +} + +static int __register_handler(struct imx_internal_bbu_handler *imx_handler) +{ + int ret; + + ret = bbu_register_handler(&imx_handler->handler); + if (ret) + free(imx_handler); + + return ret; +} + +/* + * Register a i.MX51 internal boot update handler for MMC/SD + */ +int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, + unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize) +{ + struct imx_internal_bbu_handler *imx_handler; + + imx_handler = __init_handler(name, devicefile, flags); + imx_handler->dcd = dcd; + imx_handler->dcdsize = dcdsize; + imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; + imx_handler->app_dest = 0x90000000; + imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART; + imx_handler->handler.handler = imx_bbu_internal_v1_update; + + return __register_handler(imx_handler); +} + +#define DCD_WR_CMD(len) cpu_to_be32(0xcc << 24 | (((len) & 0xffff) << 8) | 0x04) + +static int imx53_bbu_internal_init_dcd(struct imx_internal_bbu_handler *imx_handler, + void *dcd, int dcdsize) +{ + uint32_t *dcd32 = dcd; + + /* + * The DCD data we have compiled in does not have a DCD_WR_CMD at + * the beginning. Instead it is contained in struct imx_flash_header_v2. + * This is necessary to generate the DCD size at compile time. If + * we are passed such a DCD data here, prepend a DCD_WR_CMD. + */ + if ((*dcd32 & 0xff0000ff) != DCD_WR_CMD(0)) { + __be32 *buf; + + debug("%s: dcd does not have a DCD_WR_CMD. Prepending one\n"); + + buf = xmalloc(dcdsize + sizeof(__be32)); + + *buf = DCD_WR_CMD(dcdsize + sizeof(__be32)); + memcpy(&buf[1], dcd, dcdsize); + + imx_handler->dcd = buf; + imx_handler->dcdsize = dcdsize + sizeof(__be32); + } else { + debug("%s: dcd already has a DCD_WR_CMD. Using original dcd data\n"); + + imx_handler->dcd = dcd; + imx_handler->dcdsize = dcdsize; + } + + return 0; +} + +/* + * Register a i.MX53 internal boot update handler for MMC/SD + */ +int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, + unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize) +{ + struct imx_internal_bbu_handler *imx_handler; + + imx_handler = __init_handler(name, devicefile, flags); + imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize); + imx_handler->flash_header_offset = FLASH_HEADER_OFFSET_MMC; + imx_handler->app_dest = 0x70000000; + imx_handler->flags = IMX_INTERNAL_FLAG_KEEP_DOSPART; + imx_handler->handler.handler = imx_bbu_internal_v2_update; + + return __register_handler(imx_handler); +} + +/* + * Register a i.MX53 internal boot update handler for NAND + */ +int imx53_bbu_internal_nand_register_handler(const char *name, + unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize, + int partition_size) +{ + struct imx_internal_bbu_handler *imx_handler; + + imx_handler = __init_handler(name, NULL, flags); + imx53_bbu_internal_init_dcd(imx_handler, dcd, dcdsize); + imx_handler->flash_header_offset = 0x400; + imx_handler->app_dest = 0x70000000; + imx_handler->handler.handler = imx_bbu_internal_v2_update; + imx_handler->flags = IMX_INTERNAL_FLAG_NAND; + imx_handler->handler.devicefile = "/dev/nand0"; + imx_handler->device_size = partition_size; + + return __register_handler(imx_handler); +} diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c new file mode 100644 index 0000000..d36f3d9 --- /dev/null +++ b/arch/arm/mach-imx/imx.c @@ -0,0 +1,31 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +static int __imx_silicon_revision = IMX_CHIP_REV_UNKNOWN; + +int imx_silicon_revision(void) +{ + return __imx_silicon_revision; +} + +void imx_set_silicon_revision(const char *soc, int revision) +{ + __imx_silicon_revision = revision; + + printf("detected %s revision %d.%d\n", soc, + (revision >> 4) & 0xf, + revision & 0xf); +} diff --git a/arch/arm/mach-imx/imx1.c b/arch/arm/mach-imx/imx1.c index 790e453..18901ea 100644 --- a/arch/arm/mach-imx/imx1.c +++ b/arch/arm/mach-imx/imx1.c @@ -14,8 +14,34 @@ #include #include #include -#include +#include #include +#include +#include + +#define MX1_RSR MX1_SCM_BASE_ADDR +#define RSR_EXR (1 << 0) +#define RSR_WDR (1 << 1) + +static void imx1_detect_reset_source(void) +{ + u32 val = readl((void *)MX1_RSR) & 0x3; + + switch (val) { + case RSR_EXR: + set_reset_source(RESET_RST); + return; + case RSR_WDR: + set_reset_source(RESET_WDG); + return; + case 0: + set_reset_source(RESET_POR); + return; + default: + /* else keep the default 'unknown' state */ + return; + } +} void imx1_setup_eimcs(size_t cs, unsigned upper, unsigned lower) { @@ -25,12 +51,16 @@ static int imx1_init(void) { + imx_iomuxv1_init((void *)MX1_GPIO1_BASE_ADDR); + imx1_detect_reset_source(); + add_generic_device("imx1-ccm", 0, NULL, MX1_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpt", 0, NULL, MX1_TIM1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpio", 0, NULL, MX1_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpio", 1, NULL, MX1_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpio", 2, NULL, MX1_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpio", 3, NULL, MX1_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx1-wdt", 0, NULL, MX1_WDT_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx21.c b/arch/arm/mach-imx/imx21.c index 7ed0809..cddf3c0 100644 --- a/arch/arm/mach-imx/imx21.c +++ b/arch/arm/mach-imx/imx21.c @@ -14,8 +14,9 @@ #include #include #include -#include +#include #include +#include void imx21_setup_eimcs(size_t cs, unsigned upper, unsigned lower) { @@ -23,16 +24,10 @@ writel(lower, MX21_EIM_BASE_ADDR + 4 + cs * 8); } -int imx_silicon_revision(void) -{ - // Known values: - // 0x101D101D : mask set ID 0M55B - // 0x201D101D : mask set ID 1M55B or M55B - return CID; -} - static int imx21_init(void) { + imx_iomuxv1_init((void *)MX21_GPIO1_BASE_ADDR); + add_generic_device("imx21-ccm", 0, NULL, MX21_CCM_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpt", 0, NULL, MX21_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 0, NULL, MX21_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); @@ -41,6 +36,7 @@ add_generic_device("imx-gpio", 3, NULL, MX21_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 4, NULL, MX21_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 5, NULL, MX21_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX21_WDOG_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx25.c b/arch/arm/mach-imx/imx25.c index 5e6532a..3bd95c1 100644 --- a/arch/arm/mach-imx/imx25.c +++ b/arch/arm/mach-imx/imx25.c @@ -13,10 +13,11 @@ #include #include -#include +#include #include #include #include +#include #include void imx25_setup_weimcs(size_t cs, unsigned upper, unsigned lower, @@ -58,6 +59,12 @@ static int imx25_init(void) { + uint32_t val; + + val = readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR); + imx_25_35_boot_save_loc((val >> MX25_CCM_RCSR_MEM_CTRL_SHIFT) & 0x3, + (val >> MX25_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3); + add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, &imx25_iim_pdata); @@ -67,6 +74,7 @@ add_generic_device("imx31-gpio", 1, NULL, MX25_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 2, NULL, MX25_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 3, NULL, MX25_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX25_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx27.c b/arch/arm/mach-imx/imx27.c index 8116e6f..a0a510f 100644 --- a/arch/arm/mach-imx/imx27.c +++ b/arch/arm/mach-imx/imx27.c @@ -12,15 +12,40 @@ */ #include -#include +#include #include +#include #include +#include +#include #include #include -int imx_silicon_revision(void) +static int imx27_silicon_revision(void) { - return CID >> 28; + uint32_t val; + int rev; + + val = readl(MX27_SYSCTRL_BASE_ADDR); + + switch (val >> 28) { + case 0: + rev = IMX_CHIP_REV_1_0; + break; + case 1: + rev = IMX_CHIP_REV_2_0; + break; + case 2: + rev = IMX_CHIP_REV_2_1; + break; + default: + rev = IMX_CHIP_REV_UNKNOWN; + break; + } + + imx_set_silicon_revision("i.MX27", rev); + + return 0; } void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, @@ -73,6 +98,11 @@ static int imx27_init(void) { + imx27_silicon_revision(); + imx_27_boot_save_loc((void *)MX27_SYSCTRL_BASE_ADDR); + + imx_iomuxv1_init((void *)MX27_GPIO1_BASE_ADDR); + add_generic_device("imx_iim", 0, NULL, MX27_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); @@ -86,6 +116,7 @@ add_generic_device("imx1-gpio", 3, NULL, MX27_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpio", 4, NULL, MX27_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX27_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx31.c b/arch/arm/mach-imx/imx31.c index 90eee0a..b2f0724 100644 --- a/arch/arm/mach-imx/imx31.c +++ b/arch/arm/mach-imx/imx31.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include void imx31_setup_weimcs(size_t cs, unsigned upper, unsigned lower, @@ -31,11 +31,13 @@ add_generic_device("imx_iim", 0, NULL, MX31_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx31-iomux", 0, NULL, MX31_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-ccm", 0, NULL, MX31_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpt", 0, NULL, MX31_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 0, NULL, MX31_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 1, NULL, MX31_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 2, NULL, MX31_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX31_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index 722dd4c..737eb3a 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -16,8 +16,9 @@ #include #include #include -#include +#include #include +#include #include void imx35_setup_weimcs(size_t cs, unsigned upper, unsigned lower, @@ -28,14 +29,14 @@ writel(additional, MX35_WEIM_BASE_ADDR + (cs * 0x10) + 0x8); } -int imx_silicon_revision() +static void imx35_silicon_revision(void) { uint32_t reg; reg = readl(MX35_IIM_BASE_ADDR + IIM_SREV); /* 0×00 = TO 1.0, First silicon */ reg += IMX_CHIP_REV_1_0; - return (reg & 0xFF); + imx_set_silicon_revision("i.MX35", reg & 0xFF); } /* @@ -58,14 +59,24 @@ static int imx35_init(void) { + uint32_t val; + + imx35_silicon_revision(); + + val = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); + imx_25_35_boot_save_loc((val >> MX35_CCM_RCSR_MEM_CTRL_SHIFT) & 0x3, + (val >> MX35_CCM_RCSR_MEM_TYPE_SHIFT) & 0x3); + add_generic_device("imx_iim", 0, NULL, MX35_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx-iomuxv3", 0, NULL, MX35_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx35-ccm", 0, NULL, MX35_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpt", 0, NULL, MX35_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 0, NULL, MX35_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX35_WDOG_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c index 8709c43..f5a867b 100644 --- a/arch/arm/mach-imx/imx51.c +++ b/arch/arm/mach-imx/imx51.c @@ -17,69 +17,58 @@ #include #include #include -#include +#include +#include #include +#include #define SI_REV 0x48 -static u32 mx51_silicon_revision; -static char *mx51_rev_string = "unknown"; - -int imx_silicon_revision(void) -{ - return mx51_silicon_revision; -} - -static int query_silicon_revision(void) +static int imx51_silicon_revision(void) { void __iomem *rom = MX51_IROM_BASE_ADDR; + u32 mx51_silicon_revision; u32 rev; rev = readl(rom + SI_REV); switch (rev) { case 0x1: mx51_silicon_revision = IMX_CHIP_REV_1_0; - mx51_rev_string = "1.0"; break; case 0x2: mx51_silicon_revision = IMX_CHIP_REV_1_1; - mx51_rev_string = "1.1"; break; case 0x10: mx51_silicon_revision = IMX_CHIP_REV_2_0; - mx51_rev_string = "2.0"; break; case 0x20: mx51_silicon_revision = IMX_CHIP_REV_3_0; - mx51_rev_string = "3.0"; break; default: mx51_silicon_revision = 0; } - return 0; -} -core_initcall(query_silicon_revision); - -static int imx51_print_silicon_rev(void) -{ - printf("detected i.MX51 rev %s\n", mx51_rev_string); + imx_set_silicon_revision("i.MX51", mx51_silicon_revision); return 0; } -device_initcall(imx51_print_silicon_rev); static int imx51_init(void) { + imx51_silicon_revision(); + imx51_boot_save_loc((void *)MX51_SRC_BASE_ADDR); + add_generic_device("imx_iim", 0, NULL, MX51_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx-iomuxv3", 0, NULL, MX51_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx51-ccm", 0, NULL, MX51_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpt", 0, NULL, MX51_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 0, NULL, MX51_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 1, NULL, MX51_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 2, NULL, MX51_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 3, NULL, MX51_GPIO4_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX51_WDOG_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } @@ -104,73 +93,6 @@ * power up. */ -#define SRC_SBMR 0x4 -#define SBMR_BT_MEM_TYPE_SHIFT 7 -#define SBMR_BT_MEM_CTL_SHIFT 0 -#define SBMR_BMOD_SHIFT 14 - -static int imx51_boot_save_loc(void) -{ - const char *bareboxloc = NULL; - uint32_t reg; - unsigned int ctrl, type; - - /* [CTRL][TYPE] */ - const char *const locations[4][4] = { - { /* CTRL = WEIM */ - "nor", - NULL, - "onenand", - NULL, - }, { /* CTRL == NAND */ - "nand", - "nand", - "nand", - "nand", - }, { /* CTRL == reserved */ - NULL, - NULL, - NULL, - NULL, - }, { /* CTRL == expansion */ - "mmc", - NULL, - "i2c", - "spi", - } - }; - - reg = readl(MX51_SRC_BASE_ADDR + SRC_SBMR); - - switch ((reg >> SBMR_BMOD_SHIFT) & 0x3) { - case 0: - case 2: - /* internal boot */ - ctrl = (reg >> SBMR_BT_MEM_CTL_SHIFT) & 0x3; - type = (reg >> SBMR_BT_MEM_TYPE_SHIFT) & 0x3; - - bareboxloc = locations[ctrl][type]; - break; - case 1: - /* reserved */ - bareboxloc = "unknown"; - break; - case 3: - bareboxloc = "serial"; - break; - - } - - if (bareboxloc) { - setenv("barebox_loc", bareboxloc); - export("barebox_loc"); - } - - return 0; -} - -coredevice_initcall(imx51_boot_save_loc); - #define setup_pll_800(base) imx5_setup_pll((base), 800, (( 8 << 4) + ((1 - 1) << 0)), ( 3 - 1), 1) #define setup_pll_665(base) imx5_setup_pll((base), 665, (( 6 << 4) + ((1 - 1) << 0)), (96 - 1), 89) #define setup_pll_600(base) imx5_setup_pll((base), 600, (( 6 << 4) + ((1 - 1) << 0)), ( 4 - 1), 1) diff --git a/arch/arm/mach-imx/imx53.c b/arch/arm/mach-imx/imx53.c index 88b4274..e424e7d 100644 --- a/arch/arm/mach-imx/imx53.c +++ b/arch/arm/mach-imx/imx53.c @@ -17,59 +17,48 @@ #include #include #include -#include +#include +#include #include +#include #define SI_REV 0x48 -static u32 mx53_silicon_revision; -static char *mx53_rev_string = "unknown"; - -int imx_silicon_revision(void) -{ - return mx53_silicon_revision; -} - -static int query_silicon_revision(void) +static int imx53_silicon_revision(void) { void __iomem *rom = MX53_IROM_BASE_ADDR; u32 rev; + u32 mx53_silicon_revision; rev = readl(rom + SI_REV); switch (rev) { case 0x10: mx53_silicon_revision = IMX_CHIP_REV_1_0; - mx53_rev_string = "1.0"; break; case 0x20: mx53_silicon_revision = IMX_CHIP_REV_2_0; - mx53_rev_string = "2.0"; break; case 0x21: mx53_silicon_revision = IMX_CHIP_REV_2_1; - mx53_rev_string = "2.1"; break; default: mx53_silicon_revision = 0; } - return 0; -} -core_initcall(query_silicon_revision); - -static int imx53_print_silicon_rev(void) -{ - printf("detected i.MX53 rev %s\n", mx53_rev_string); + imx_set_silicon_revision("i.MX53", mx53_silicon_revision); return 0; } -device_initcall(imx53_print_silicon_rev); static int imx53_init(void) { + imx53_silicon_revision(); + imx53_boot_save_loc((void *)MX53_SRC_BASE_ADDR); + add_generic_device("imx_iim", 0, NULL, MX53_IIM_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); + add_generic_device("imx-iomuxv3", 0, NULL, MX53_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx53-ccm", 0, NULL, MX53_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpt", 0, NULL, 0X53fa0000, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 0, NULL, MX53_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); @@ -79,6 +68,7 @@ add_generic_device("imx31-gpio", 4, NULL, MX53_GPIO5_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 5, NULL, MX53_GPIO6_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 6, NULL, MX53_GPIO7_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX53_WDOG1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); return 0; } @@ -203,6 +193,8 @@ writel(0xffffffff, ccm + MX5_CCM_CCGR6); writel(0xffffffff, ccm + MX53_CCM_CCGR7); - clock_notifier_call_chain(); + if (!IS_ENABLED(__PBL__)) + clock_notifier_call_chain(); + writel(0, ccm + MX5_CCM_CCDR); } diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c index a5ec364..c9eec5a 100644 --- a/arch/arm/mach-imx/imx6.c +++ b/arch/arm/mach-imx/imx6.c @@ -54,6 +54,7 @@ static int imx6_init(void) { + add_generic_device("imx-iomuxv3", 0, NULL, MX6_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx6-ccm", 0, NULL, MX6_CCM_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpt", 0, NULL, 0x02098000, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 0, NULL, MX6_GPIO1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); @@ -63,6 +64,7 @@ add_generic_device("imx31-gpio", 4, NULL, MX6_GPIO5_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 5, NULL, MX6_GPIO6_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 6, NULL, MX6_GPIO7_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx21-wdt", 0, NULL, MX6_WDOG1_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h new file mode 100644 index 0000000..f9ec1cc --- /dev/null +++ b/arch/arm/mach-imx/include/mach/bbu.h @@ -0,0 +1,51 @@ +#ifndef __MACH_BBU_H +#define __MACH_BBU_H + +#include + +struct imx_dcd_entry; +struct imx_dcd_v2_entry; + +#ifdef CONFIG_BAREBOX_UPDATE + +int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, + unsigned long flags, struct imx_dcd_entry *, int dcdsize); + +int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, + unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize); + +int imx53_bbu_internal_nand_register_handler(const char *name, + unsigned long flags, struct imx_dcd_v2_entry *, int dcdsize, + int partition_size); + +#else + +static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, + unsigned long flags, struct imx_dcd_entry *dcd, int dcdsize) +{ + return -ENOSYS; +} + +static inline int imx53_bbu_internal_mmc_register_handler(const char *name, char *devicefile, + unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize) +{ + return -ENOSYS; +} + +static inline int imx53_bbu_internal_nand_register_handler(const char *name, + unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize, + int partition_size) +{ + return -ENOSYS; +} + +#endif + +struct dcd_table { + void *data; + unsigned int size; +}; + +void *imx53_bbu_internal_concat_dcd_table(struct dcd_table *table, int num_entries); + +#endif diff --git a/arch/arm/mach-imx/include/mach/devices-imx1.h b/arch/arm/mach-imx/include/mach/devices-imx1.h index c73113c..391c1a9 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx1.h +++ b/arch/arm/mach-imx/include/mach/devices-imx1.h @@ -2,10 +2,10 @@ static inline struct device_d *imx1_add_uart0(void) { - return imx_add_uart((void *)MX1_UART1_BASE_ADDR, 0); + return imx_add_uart_imx1((void *)MX1_UART1_BASE_ADDR, 0); } static inline struct device_d *imx1_add_uart1(void) { - return imx_add_uart((void *)MX1_UART2_BASE_ADDR, 1); + return imx_add_uart_imx1((void *)MX1_UART2_BASE_ADDR, 1); } diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h index 31c5f8c..ad7ee5e 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx21.h +++ b/arch/arm/mach-imx/include/mach/devices-imx21.h @@ -3,22 +3,22 @@ static inline struct device_d *imx21_add_uart0(void) { - return imx_add_uart((void *)MX21_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX21_UART1_BASE_ADDR, 0); } static inline struct device_d *imx21_add_uart1(void) { - return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 1); } static inline struct device_d *imx21_add_uart2(void) { - return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 2); } static inline struct device_d *imx21_add_uart3(void) { - return imx_add_uart((void *)MX21_UART2_BASE_ADDR, 3); + return imx_add_uart_imx21((void *)MX21_UART2_BASE_ADDR, 3); } static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h index 86cda35..a655be9 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx25.h +++ b/arch/arm/mach-imx/include/mach/devices-imx25.h @@ -33,27 +33,27 @@ static inline struct device_d *imx25_add_uart0(void) { - return imx_add_uart((void *)MX25_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX25_UART1_BASE_ADDR, 0); } static inline struct device_d *imx25_add_uart1(void) { - return imx_add_uart((void *)MX25_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX25_UART2_BASE_ADDR, 1); } static inline struct device_d *imx25_add_uart2(void) { - return imx_add_uart((void *)MX25_UART3_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX25_UART3_BASE_ADDR, 2); } static inline struct device_d *imx25_add_uart3(void) { - return imx_add_uart((void *)MX25_UART4_BASE_ADDR, 3); + return imx_add_uart_imx21((void *)MX25_UART4_BASE_ADDR, 3); } static inline struct device_d *imx25_add_uart4(void) { - return imx_add_uart((void *)MX25_UART5_BASE_ADDR, 4); + return imx_add_uart_imx21((void *)MX25_UART5_BASE_ADDR, 4); } static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata) @@ -68,7 +68,7 @@ static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)MX25_FEC_BASE_ADDR, pdata); + return imx_add_fec_imx27((void *)MX25_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx25_add_mmc0(struct esdhc_platform_data *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h index 2799343..79da935 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx27.h +++ b/arch/arm/mach-imx/include/mach/devices-imx27.h @@ -23,22 +23,22 @@ static inline struct device_d *imx27_add_uart0(void) { - return imx_add_uart((void *)MX27_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX27_UART1_BASE_ADDR, 0); } static inline struct device_d *imx27_add_uart1(void) { - return imx_add_uart((void *)MX27_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX27_UART2_BASE_ADDR, 1); } static inline struct device_d *imx27_add_uart2(void) { - return imx_add_uart((void *)MX27_UART3_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX27_UART3_BASE_ADDR, 2); } static inline struct device_d *imx27_add_uart3(void) { - return imx_add_uart((void *)MX27_UART4_BASE_ADDR, 3); + return imx_add_uart_imx21((void *)MX27_UART4_BASE_ADDR, 3); } static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata) @@ -53,7 +53,7 @@ static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)MX27_FEC_BASE_ADDR, pdata); + return imx_add_fec_imx27((void *)MX27_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx27_add_mmc0(void *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h index d45e4e1..fe71930 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx31.h +++ b/arch/arm/mach-imx/include/mach/devices-imx31.h @@ -1,5 +1,5 @@ -#include +#include #include static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata) @@ -19,27 +19,27 @@ static inline struct device_d *imx31_add_uart0(void) { - return imx_add_uart((void *)MX31_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX31_UART1_BASE_ADDR, 0); } static inline struct device_d *imx31_add_uart1(void) { - return imx_add_uart((void *)MX31_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX31_UART2_BASE_ADDR, 1); } static inline struct device_d *imx31_add_uart2(void) { - return imx_add_uart((void *)MX31_UART3_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX31_UART3_BASE_ADDR, 2); } static inline struct device_d *imx31_add_uart3(void) { - return imx_add_uart((void *)MX31_UART4_BASE_ADDR, 3); + return imx_add_uart_imx21((void *)MX31_UART4_BASE_ADDR, 3); } static inline struct device_d *imx31_add_uart4(void) { - return imx_add_uart((void *)MX31_UART5_BASE_ADDR, 4); + return imx_add_uart_imx21((void *)MX31_UART5_BASE_ADDR, 4); } static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h index 27c49e7..912c418 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx35.h +++ b/arch/arm/mach-imx/include/mach/devices-imx35.h @@ -28,17 +28,17 @@ static inline struct device_d *imx35_add_uart0(void) { - return imx_add_uart((void *)MX35_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX35_UART1_BASE_ADDR, 0); } static inline struct device_d *imx35_add_uart1(void) { - return imx_add_uart((void *)MX35_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX35_UART2_BASE_ADDR, 1); } static inline struct device_d *imx35_add_uart2(void) { - return imx_add_uart((void *)MX35_UART3_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX35_UART3_BASE_ADDR, 2); } static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata) @@ -53,7 +53,7 @@ static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)MX35_FEC_BASE_ADDR, pdata); + return imx_add_fec_imx27((void *)MX35_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx35_add_mmc0(struct esdhc_platform_data *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h index 4b35c96..8ee3c17 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx51.h +++ b/arch/arm/mach-imx/include/mach/devices-imx51.h @@ -29,22 +29,22 @@ static inline struct device_d *imx51_add_uart0(void) { - return imx_add_uart((void *)MX51_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX51_UART1_BASE_ADDR, 0); } static inline struct device_d *imx51_add_uart1(void) { - return imx_add_uart((void *)MX51_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX51_UART2_BASE_ADDR, 1); } static inline struct device_d *imx51_add_uart2(void) { - return imx_add_uart((void *)MX51_UART3_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX51_UART3_BASE_ADDR, 2); } static inline struct device_d *imx51_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)MX51_MXC_FEC_BASE_ADDR, pdata); + return imx_add_fec_imx27((void *)MX51_MXC_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx51_add_mmc0(struct esdhc_platform_data *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h index 54d7b27..5f967ea 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx53.h +++ b/arch/arm/mach-imx/include/mach/devices-imx53.h @@ -23,22 +23,22 @@ static inline struct device_d *imx53_add_uart0(void) { - return imx_add_uart((void *)MX53_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX53_UART1_BASE_ADDR, 0); } static inline struct device_d *imx53_add_uart1(void) { - return imx_add_uart((void *)MX53_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX53_UART2_BASE_ADDR, 1); } static inline struct device_d *imx53_add_uart2(void) { - return imx_add_uart((void *)MX53_UART3_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX53_UART3_BASE_ADDR, 2); } static inline struct device_d *imx53_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)MX53_FEC_BASE_ADDR, pdata); + return imx_add_fec_imx27((void *)MX53_FEC_BASE_ADDR, pdata); } static inline struct device_d *imx53_add_mmc0(struct esdhc_platform_data *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices-imx6.h b/arch/arm/mach-imx/include/mach/devices-imx6.h index c73e488..f8282e7 100644 --- a/arch/arm/mach-imx/include/mach/devices-imx6.h +++ b/arch/arm/mach-imx/include/mach/devices-imx6.h @@ -2,22 +2,22 @@ static inline struct device_d *imx6_add_uart0(void) { - return imx_add_uart((void *)MX6_UART1_BASE_ADDR, 0); + return imx_add_uart_imx21((void *)MX6_UART1_BASE_ADDR, 0); } static inline struct device_d *imx6_add_uart1(void) { - return imx_add_uart((void *)MX6_UART2_BASE_ADDR, 1); + return imx_add_uart_imx21((void *)MX6_UART2_BASE_ADDR, 1); } static inline struct device_d *imx6_add_uart2(void) { - return imx_add_uart((void *)MX6_UART3_BASE_ADDR, 2); + return imx_add_uart_imx21((void *)MX6_UART3_BASE_ADDR, 2); } static inline struct device_d *imx6_add_uart3(void) { - return imx_add_uart((void *)MX6_UART4_BASE_ADDR, 3); + return imx_add_uart_imx21((void *)MX6_UART4_BASE_ADDR, 3); } static inline struct device_d *imx6_add_mmc0(struct esdhc_platform_data *pdata) @@ -42,7 +42,7 @@ static inline struct device_d *imx6_add_fec(struct fec_platform_data *pdata) { - return imx_add_fec((void *)MX6_ENET_BASE_ADDR, pdata); + return imx_add_fec_imx6((void *)MX6_ENET_BASE_ADDR, pdata); } static inline struct device_d *imx6_add_spi0(struct spi_imx_master *pdata) diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h index da91646..f7824f5 100644 --- a/arch/arm/mach-imx/include/mach/devices.h +++ b/arch/arm/mach-imx/include/mach/devices.h @@ -8,10 +8,12 @@ #include #include -struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata); +struct device_d *imx_add_fec_imx27(void *base, struct fec_platform_data *pdata); +struct device_d *imx_add_fec_imx6(void *base, struct fec_platform_data *pdata); struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata); struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata); -struct device_d *imx_add_uart(void *base, int id); +struct device_d *imx_add_uart_imx1(void *base, int id); +struct device_d *imx_add_uart_imx21(void *base, int id); struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata); struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata); struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata); diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h index 10c8b9b..8124c87 100644 --- a/arch/arm/mach-imx/include/mach/esdctl.h +++ b/arch/arm/mach-imx/include/mach/esdctl.h @@ -1,10 +1,10 @@ /* SDRAM Controller registers */ -#define ESDCTL0 (IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */ -#define ESDCFG0 (IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */ -#define ESDCTL1 (IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */ -#define ESDCFG1 (IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */ -#define ESDMISC (IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */ +#define IMX_ESDCTL0 0x00 /* Enhanced SDRAM Control Register 0 */ +#define IMX_ESDCFG0 0x04 /* Enhanced SDRAM Configuration Register 0 */ +#define IMX_ESDCTL1 0x08 /* Enhanced SDRAM Control Register 1 */ +#define IMX_ESDCFG1 0x0C /* Enhanced SDRAM Configuration Register 1 */ +#define IMX_ESDMISC 0x10 /* Enhanced SDRAM Miscellanious Register */ #define ESDCTL0_SDE (1 << 31) #define ESDCTL0_SMODE_NORMAL (0 << 28) diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 99f3012..39bb7e3 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -1,10 +1,29 @@ -int imx_silicon_revision(void); -#define IMX27_CHIP_REVISION_1_0 0 -#define IMX27_CHIP_REVISION_2_0 1 - u64 imx_uid(void); +enum imx_bootsource { + bootsource_unknown, + bootsource_nand, + bootsource_nor, + bootsource_mmc, + bootsource_i2c, + bootsource_spi, + bootsource_serial, + bootsource_onenand, + bootsource_hd, +}; + +enum imx_bootsource imx_bootsource(void); +void imx_set_bootsource(enum imx_bootsource src); + +int imx_25_35_boot_save_loc(unsigned int ctrl, unsigned int type); +void imx_27_boot_save_loc(void __iomem *sysctrl_base); +int imx51_boot_save_loc(void __iomem *src_base); +int imx53_boot_save_loc(void __iomem *src_base); + +/* There's a off-by-one betweem the gpio bank number and the gpiochip */ +/* range e.g. GPIO_1_5 is gpio 5 under linux */ +#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) #ifdef CONFIG_ARCH_IMX1 #define cpu_is_mx1() (1) diff --git a/arch/arm/mach-imx/include/mach/imx-flash-header.h b/arch/arm/mach-imx/include/mach/imx-flash-header.h index a51d473..9a351ad 100644 --- a/arch/arm/mach-imx/include/mach/imx-flash-header.h +++ b/arch/arm/mach-imx/include/mach/imx-flash-header.h @@ -120,7 +120,9 @@ struct imx_dcd { struct imx_ivt_header header; +#ifndef IMX_INTERNAL_NAND_BBU struct imx_dcd_command command; +#endif }; struct imx_boot_data { @@ -144,4 +146,37 @@ struct imx_dcd dcd; }; +/* + * A variant of the standard barebox header in the i.MX FCB + * format. Needed for i.MX53 NAND boot + */ +static inline void barebox_arm_imx_fcb_head(void) +{ + __asm__ __volatile__ ( + ".arm\n" + " b 1f\n" + ".word 0x20424346\n" /* FCB */ + ".word 0x1\n" +#ifdef CONFIG_THUMB2_BAREBOX + "1: adr r9, 1f + 1\n" + " bx r9\n" + ".thumb\n" + "1:\n" + "bl reset\n" +#else + "1: b reset\n" + ".word 0x0\n" + ".word 0x0\n" +#endif + ".word 0x0\n" + ".word 0x0\n" + + ".asciz \"barebox\"\n" + ".word _text\n" /* text base. If copied there, + * barebox can skip relocation + */ + ".word _barebox_image_size\n" /* image size to copy */ + ); +} + #endif /* __MACH_FLASH_HEADER_H */ diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h deleted file mode 100644 index 235bac3..0000000 --- a/arch/arm/mach-imx/include/mach/imx-regs.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _IMX_REGS_H -#define _IMX_REGS_H - -/* ------------------------------------------------------------------------ - * Motorola IMX system registers - * ------------------------------------------------------------------------ - */ - -# ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)(x))) -# define __REG16(x) (*(volatile u16 *)(x)) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# define __REG16(x) (x) -# define __REG2(x,y) ((x)+(y)) -#endif - -#ifdef CONFIG_ARCH_IMX1 -# include -#elif defined CONFIG_ARCH_IMX21 -# include -#elif defined CONFIG_ARCH_IMX27 -# include -#elif defined CONFIG_ARCH_IMX31 -# include -#elif defined CONFIG_ARCH_IMX35 -# include -#elif defined CONFIG_ARCH_IMX25 -# include -#elif defined CONFIG_ARCH_IMX51 -# include -#elif defined CONFIG_ARCH_IMX53 -# include -#elif defined CONFIG_ARCH_IMX6 -# include -#else -# error "unknown i.MX soc type" -#endif - -/* There's a off-by-one betweem the gpio bank number and the gpiochip */ -/* range e.g. GPIO_1_5 is gpio 5 under linux */ -#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr)) - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) - -#define GPIO_GIUS (1<<16) - -/* silicon revisions */ -#define IMX_CHIP_REV_1_0 0x10 -#define IMX_CHIP_REV_1_1 0x11 -#define IMX_CHIP_REV_1_2 0x12 -#define IMX_CHIP_REV_1_3 0x13 -#define IMX_CHIP_REV_2_0 0x20 -#define IMX_CHIP_REV_2_1 0x21 -#define IMX_CHIP_REV_2_2 0x22 -#define IMX_CHIP_REV_2_3 0x23 -#define IMX_CHIP_REV_3_0 0x30 -#define IMX_CHIP_REV_3_1 0x31 -#define IMX_CHIP_REV_3_2 0x32 - -#endif /* _IMX_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h index cb60c84..df6ede5 100644 --- a/arch/arm/mach-imx/include/mach/imx1-regs.h +++ b/arch/arm/mach-imx/include/mach/imx1-regs.h @@ -59,161 +59,25 @@ #define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) #define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) -/* FIXME: get rid of these */ -#define IMX_TIM1_BASE MX1_CCM_BASE_ADDR -#define IMX_WDT_BASE MX1_WDT_BASE_ADDR -#define IMX_GPIO_BASE MX1_GPIO_BASE_ADDR +/* SYSCTRL Registers (base MX1_SCM_BASE_ADDR) */ +#define MX1_SIDR 0x4 /* Silicon ID Register */ +#define MX1_FMCR 0x8 /* Function Multiplex Control Register */ +#define MX1_GPCR 0xC /* Function Multiplex Control Register */ -/* SYSCTRL Registers */ -#define SIDR __REG(MX1_SCM_BASE_ADDR + 0x4) /* Silicon ID Register */ -#define FMCR __REG(MX1_SCM_BASE_ADDR + 0x8) /* Function Multiplex Control Register */ -#define GPCR __REG(MX1_SCM_BASE_ADDR + 0xC) /* Function Multiplex Control Register */ +/* SDRAM controller registers (base MX1_SDRAMC_BASE_ADDR) */ +#define MX1_SDCTL0 0x0 /* SDRAM 0 Control Register */ +#define MX1_SDCTL1 0x4 /* SDRAM 1 Control Register */ +#define MX1_SDMISC 0x14 /* Miscellaneous Register */ +#define MX1_SDRST 0x18 /* SDRAM Reset Register */ -/* SDRAM controller registers */ +/* PLL registers (base MX1_CCM_BASE_ADDR) */ +#define MX1_CSCR 0x0 /* Clock Source Control Register */ +#define MX1_MPCTL0 0x4 /* MCU PLL Control Register 0 */ +#define MX1_MPCTL1 0x8 /* MCU PLL and System Clock Register 1 */ +#define MX1_SPCTL0 0xc /* System PLL Control Register 0 */ +#define MX1_SPCTL1 0x10 /* System PLL Control Register 1 */ +#define MX1_PCDR 0x20 /* Peripheral Clock Divider Register */ -#define SDCTL0 __REG(MX1_SDRAMC_BASE_ADDR) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(MX1_SDRAMC_BASE_ADDR + 0x4) /* SDRAM 1 Control Register */ -#define SDMISC __REG(MX1_SDRAMC_BASE_ADDR + 0x14) /* Miscellaneous Register */ -#define SDRST __REG(MX1_SDRAMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */ - -/* PLL registers */ -#define CSCR __REG(MX1_CCM_BASE_ADDR) /* Clock Source Control Register */ -#define MPCTL0 __REG(MX1_CCM_BASE_ADDR + 0x4) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x8) /* MCU PLL and System Clock Register 1 */ -#define SPCTL0 __REG(MX1_CCM_BASE_ADDR + 0xc) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */ -#define PCDR __REG(MX1_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Divider Register */ - -#define CSCR_MPLL_RESTART (1<<21) - -/* assignements for GPIO alternate/primary functions */ - -/* FIXME: This list is not completed. The correct directions are - * missing on some (many) pins - */ -#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) -#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) -#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) -#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) -#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) -#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) -#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) -#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) -#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) -#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) -#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) -#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) -#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) -#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) -#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) -#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) -#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) -#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) -#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) -#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) -#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) -#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) -#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) -#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) -#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) -#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) -#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) -#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) -#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) -#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) -#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) -#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) -#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) -#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) -#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) -#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) -#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) -#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) -#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) -#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) -#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) -#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) -#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) -#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) -#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) -#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) -#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) -#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) -#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) -#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) -#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) -#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) -#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) -#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) -#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) -#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) -#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) -#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) -#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) -#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) -#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) -#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) -#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) -#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) -#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) -#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) -#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) -#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) -#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) -#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) -#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) -#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) -#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) -#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) -#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) -#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) -#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) -#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) -#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) -#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) -#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) -#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) -#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) -#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) -#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) -#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) -#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) -#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) -#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) -#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) -#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) -#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) -#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) -#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) -#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) -#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) -#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) -#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) -#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) -#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) -#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) -#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) -#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) -#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) -#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) -#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) -#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) -#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) -#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) -#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) -#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) -#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) -#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) -#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) -#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) -#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) -#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) -#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) -#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) -#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) -#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) -#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) -#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) -#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) +#define MX1_CSCR_MPLL_RESTART (1<<21) #endif /* _IMX1_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h index 9952b8b..1c4b550 100644 --- a/arch/arm/mach-imx/include/mach/imx21-regs.h +++ b/arch/arm/mach-imx/include/mach/imx21-regs.h @@ -71,76 +71,70 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ -/* FIXME: Get rid of these */ -#define IMX_GPIO_BASE MX21_GPIO_BASE_ADDR -#define IMX_TIM1_BASE MX21_GPT1_BASE_ADDR -#define IMX_WDT_BASE MX21_WDOG_BASE_ADDR -#define IMX_SYSTEM_CTL_BASE MX21_SYSCTRL_BASE_ADDR +/* AIPI (base MX21_AIPI_BASE_ADDR) */ +#define MX21_AIPI1_PSR0 0x00 +#define MX21_AIPI1_PSR1 0x04 +#define MX21_AIPI2_PSR0 (0x20000 + 0x00) +#define MX21_AIPI2_PSR1 (0x20000 + 0x04) -/* AIPI */ -#define AIPI1_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x00) -#define AIPI1_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x04) -#define AIPI2_PSR0 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x00) -#define AIPI2_PSR1 __REG(MX21_AIPI_BASE_ADDR + 0x20000 + 0x04) +/* System Control (base: MX21_SYSCTRL_BASE_ADDR) */ +#define MX21_SUID0 0x4 /* Silicon ID Register (12 bytes) */ +#define MX21_SUID1 0x8 /* Silicon ID Register (12 bytes) */ +#define MX21_CID 0xC /* Silicon ID Register (12 bytes) */ +#define MX21_FMCR 0x14 /* Function Multeplexing Control Register */ +#define MX21_GPCR 0x18 /* Global Peripheral Control Register */ +#define MX21_WBCR 0x1C /* Well Bias Control Register */ +#define MX21_DSCR(x) 0x1C + ((x) << 2) /* Driving Strength Control Register 1 - 13 */ -/* System Control */ -#define SUID0 __REG(MX21_SYSCTRL_BASE_ADDR + 0x4) /* Silicon ID Register (12 bytes) */ -#define SUID1 __REG(MX21_SYSCTRL_BASE_ADDR + 0x8) /* Silicon ID Register (12 bytes) */ -#define CID __REG(MX21_SYSCTRL_BASE_ADDR + 0xC) /* Silicon ID Register (12 bytes) */ -#define FMCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */ -#define GPCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */ -#define WBCR __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */ -#define DSCR(x) __REG(MX21_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ +#define MX21_GPCR_BOOT_SHIFT 16 +#define MX21_GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) +#define MX21_GPCR_BOOT_UART_USB 0 +#define MX21_GPCR_BOOT_8BIT_NAND_2k 2 +#define MX21_GPCR_BOOT_16BIT_NAND_2k 3 +#define MX21_GPCR_BOOT_16BIT_NAND_512 4 +#define MX21_GPCR_BOOT_16BIT_CS0 5 +#define MX21_GPCR_BOOT_32BIT_CS0 6 +#define MX21_GPCR_BOOT_8BIT_NAND_512 7 -#define GPCR_BOOT_SHIFT 16 -#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) -#define GPCR_BOOT_UART_USB 0 -#define GPCR_BOOT_8BIT_NAND_2k 2 -#define GPCR_BOOT_16BIT_NAND_2k 3 -#define GPCR_BOOT_16BIT_NAND_512 4 -#define GPCR_BOOT_16BIT_CS0 5 -#define GPCR_BOOT_32BIT_CS0 6 -#define GPCR_BOOT_8BIT_NAND_512 7 +/* SDRAM Controller registers bitfields (base: MX21_X_MEMC_BASE_ADDR) */ +#define MX21_SDCTL0 0x00 /* SDRAM 0 Control Register */ +#define MX21_SDCTL1 0x04 /* SDRAM 0 Control Register */ +#define MX21_SDRST 0x18 /* SDRAM Reset Register */ +#define MX21_SDMISC 0x14 /* SDRAM Miscellaneous Register */ -/* SDRAM Controller registers bitfields */ -#define SDCTL0 __REG(MX21_X_MEMC_BASE_ADDR + 0x00) /* SDRAM 0 Control Register */ -#define SDCTL1 __REG(MX21_X_MEMC_BASE_ADDR + 0x04) /* SDRAM 0 Control Register */ -#define SDRST __REG(MX21_X_MEMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */ -#define SDMISC __REG(MX21_X_MEMC_BASE_ADDR + 0x14) /* SDRAM Miscellaneous Register */ +/* PLL registers (base: MX21_CCM_BASE_ADDR) */ +#define MX21_CSCR 0x00 /* Clock Source Control Register */ +#define MX21_MPCTL0 0x04 /* MCU PLL Control Register 0 */ +#define MX21_MPCTL1 0x08 /* MCU PLL Control Register 1 */ +#define MX21_SPCTL0 0x0c /* System PLL Control Register 0 */ +#define MX21_SPCTL1 0x10 /* System PLL Control Register 1 */ +#define MX21_OSC26MCTL 0x14 /* Oscillator 26M Register */ +#define MX21_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */ +#define MX21_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */ +#define MX21_PCCR0 0x20 /* Peripheral Clock Control Register 0 */ +#define MX21_PCCR1 0x24 /* Peripheral Clock Control Register 1 */ +#define MX21_CCSR 0x28 /* Clock Control Status Register */ -/* PLL registers */ -#define CSCR __REG(MX21_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */ -#define MPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */ -#define SPCTL0 __REG(MX21_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(MX21_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */ -#define OSC26MCTL __REG(MX21_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */ -#define PCDR0 __REG(MX21_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */ -#define PCDR1 __REG(MX21_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */ -#define PCCR0 __REG(MX21_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */ -#define PCCR1 __REG(MX21_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */ -#define CCSR __REG(MX21_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */ +#define MX21_CSCR_MPEN (1 << 0) +#define MX21_CSCR_SPEN (1 << 1) +#define MX21_CSCR_FPM_EN (1 << 2) +#define MX21_CSCR_OSC26M_DIS (1 << 3) +#define MX21_CSCR_OSC26M_DIV1P5 (1 << 4) +#define MX21_CSCR_MCU_SEL (1 << 16) +#define MX21_CSCR_SP_SEL (1 << 17) +#define MX21_CSCR_SD_CNT(d) (((d) & 0x3) << 24) +#define MX21_CSCR_USB_DIV(d) (((d) & 0x7) << 26) +#define MX21_CSCR_PRESC(d) (((d) & 0x7) << 29) -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_SD_CNT(d) (((d) & 0x3) << 24) -#define CSCR_USB_DIV(d) (((d) & 0x7) << 26) -#define CSCR_PRESC(d) (((d) & 0x7) << 29) +#define MX21_MPCTL1_BRMO (1 << 6) +#define MX21_MPCTL1_LF (1 << 15) -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) +#define MX21_PCCR0_PERCLK3_EN (1 << 18) +#define MX21_PCCR0_NFC_EN (1 << 19) +#define MX21_PCCR0_HCLK_LCDC_EN (1 << 26) -#define PCCR0_PERCLK3_EN (1 << 18) -#define PCCR0_NFC_EN (1 << 19) -#define PCCR0_HCLK_LCDC_EN (1 << 26) +#define MX21_PCCR1_GPT1_EN (1 << 25) -#define PCCR1_GPT1_EN (1 << 25) - -#define CCSR_32K_SR (1 << 15) +#define MX21_CCSR_32K_SR (1 << 15) #endif /* _IMX21_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx25-regs.h b/arch/arm/mach-imx/include/mach/imx25-regs.h index 0bf6e11..b8ae45a 100644 --- a/arch/arm/mach-imx/include/mach/imx25-regs.h +++ b/arch/arm/mach-imx/include/mach/imx25-regs.h @@ -76,46 +76,39 @@ #define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) #define MX25_CSI_BASE_ADDR 0x53ff8000 -/* FIXME: Get rid of these */ -#define IMX_TIM1_BASE MX25_GPT1_BASE_ADDR -#define IMX_IOMUXC_BASE MX25_IOMUXC_BASE_ADDR -#define IMX_WDT_BASE MX25_WDOG_BASE_ADDR -#define IMX_CCM_BASE MX25_CCM_BASE_ADDR -#define IMX_ESD_BASE MX25_ESDCTL_BASE_ADDR - /* * Clock Controller Module (CCM) */ -#define CCM_MPCTL 0x00 -#define CCM_UPCTL 0x04 -#define CCM_CCTL 0x08 -#define CCM_CGCR0 0x0C -#define CCM_CGCR1 0x10 -#define CCM_CGCR2 0x14 -#define CCM_PCDR0 0x18 -#define CCM_PCDR1 0x1C -#define CCM_PCDR2 0x20 -#define CCM_PCDR3 0x24 -#define CCM_RCSR 0x28 -#define CCM_CRDR 0x2C -#define CCM_DCVR0 0x30 -#define CCM_DCVR1 0x34 -#define CCM_DCVR2 0x38 -#define CCM_DCVR3 0x3c -#define CCM_LTR0 0x40 -#define CCM_LTR1 0x44 -#define CCM_LTR2 0x48 -#define CCM_LTR3 0x4c +#define MX25_CCM_MPCTL 0x00 +#define MX25_CCM_UPCTL 0x04 +#define MX25_CCM_CCTL 0x08 +#define MX25_CCM_CGCR0 0x0C +#define MX25_CCM_CGCR1 0x10 +#define MX25_CCM_CGCR2 0x14 +#define MX25_CCM_PCDR0 0x18 +#define MX25_CCM_PCDR1 0x1C +#define MX25_CCM_PCDR2 0x20 +#define MX25_CCM_PCDR3 0x24 +#define MX25_CCM_RCSR 0x28 +#define MX25_CCM_CRDR 0x2C +#define MX25_CCM_DCVR0 0x30 +#define MX25_CCM_DCVR1 0x34 +#define MX25_CCM_DCVR2 0x38 +#define MX25_CCM_DCVR3 0x3c +#define MX25_CCM_LTR0 0x40 +#define MX25_CCM_LTR1 0x44 +#define MX25_CCM_LTR2 0x48 +#define MX25_CCM_LTR3 0x4c -#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) -#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) -#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20) -#define PDR0_AUTO_CON (1 << 0) -#define PDR0_PER_SEL (1 << 26) +#define MX25_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) +#define MX25_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) +#define MX25_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) +#define MX25_PDR0_HSP_PODF(x) (((x) & 0x3) << 20) +#define MX25_PDR0_AUTO_CON (1 << 0) +#define MX25_PDR0_PER_SEL (1 << 26) -#define CCM_RCSR_MEM_CTRL_SHIFT 30 -#define CCM_RCSR_MEM_TYPE_SHIFT 28 +#define MX25_CCM_RCSR_MEM_CTRL_SHIFT 30 +#define MX25_CCM_RCSR_MEM_TYPE_SHIFT 28 /* * Adresses and ranges of the external chip select lines @@ -139,14 +132,4 @@ #define MX25_ESDCTL_BASE_ADDR 0xb8001000 #define MX25_WEIM_BASE_ADDR 0xb8002000 -/* - * Watchdog Registers - */ -#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ -#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ -#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ - -/* important definition of some bits of WCR */ -#define WCR_WDE 0x04 - #endif /* __ASM_ARCH_MX25_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h index 5db1a3c..90b4614 100644 --- a/arch/arm/mach-imx/include/mach/imx27-regs.h +++ b/arch/arm/mach-imx/include/mach/imx27-regs.h @@ -86,7 +86,7 @@ #define MX27_X_MEMC_BASE_ADDR 0xd8000000 #define MX27_X_MEMC_SIZE SZ_1M #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) -#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) +#define MX27_ESDCTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) #define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) @@ -101,181 +101,65 @@ /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ -/* FIXME: get rid of these */ -#define IMX_GPIO_BASE MX27_GPIO_BASE_ADDR -#define IMX_NFC_BASE MX27_NFC_BASE_ADDR -#define IMX_WDT_BASE MX27_WDOG_BASE_ADDR -#define IMX_ESD_BASE MX27_SDRAMC_BASE_ADDR +/* PCMCIA (base: MX27_PCMCIA_CTL_BASE_ADDR) */ +#define MX27_PCMCIA_PIPR 0x00 +#define MX27_PCMCIA_PSCR 0x04 +#define MX27_PCMCIA_PER 0x08 +#define MX27_PCMCIA_PBR(x) (0x0c + ((x) << 2)) +#define MX27_PCMCIA_POR(x) (0x28 + ((x) << 2)) +#define MX27_PCMCIA_POFR(x) (0x44 + ((x) << 2)) +#define MX27_PCMCIA_PGCR 0x60 +#define MX27_PCMCIA_PGSR 0x64 -#define PCMCIA_PIPR (MX27_PCMCIA_CTL_BASE_ADDR + 0x00) -#define PCMCIA_PSCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x04) -#define PCMCIA_PER (MX27_PCMCIA_CTL_BASE_ADDR + 0x08) -#define PCMCIA_PBR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x0c + ((x) << 2)) -#define PCMCIA_POR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x28 + ((x) << 2)) -#define PCMCIA_POFR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x44 + ((x) << 2)) -#define PCMCIA_PGCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x60) -#define PCMCIA_PGSR (MX27_PCMCIA_CTL_BASE_ADDR + 0x64) +/* AIPI (base: MX27_AIPI_BASE_ADDR) */ +#define MX27_AIPI1_PSR0 0x00 +#define MX27_AIPI1_PSR1 0x04 +#define MX27_AIPI2_PSR0 (0x20000 + 0x00) +#define MX27_AIPI2_PSR1 (0x20000 + 0x04) -/* AIPI */ -#define AIPI1_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x00) -#define AIPI1_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x04) -#define AIPI2_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x00) -#define AIPI2_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x04) - -/* System Control */ -#define CID __REG(MX27_SYSCTRL_BASE_ADDR + 0x0) /* Chip ID Register */ -#define FMCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */ -#define GPCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */ -#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */ -#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ - -#define GPCR_BOOT_SHIFT 16 -#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT) -#define GPCR_BOOT_UART_USB 0 -#define GPCR_BOOT_8BIT_NAND_2k 2 -#define GPCR_BOOT_16BIT_NAND_2k 3 -#define GPCR_BOOT_16BIT_NAND_512 4 -#define GPCR_BOOT_16BIT_CS0 5 -#define GPCR_BOOT_32BIT_CS0 6 -#define GPCR_BOOT_8BIT_NAND_512 7 +/* System Control (base: MX27_SYSCTRL_BASE_ADDR) */ +#define MX27_CID 0x0 /* Chip ID Register */ +#define MX27_FMCR 0x14 /* Function Multeplexing Control Register */ +#define MX27_GPCR 0x18 /* Global Peripheral Control Register */ +#define MX27_WBCR 0x1C /* Well Bias Control Register */ +#define MX27_DSCR(x) (0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */ #include "esdctl.h" -/* PLL registers */ -#define CSCR __REG(MX27_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */ -#define MPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */ -#define MPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */ -#define SPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */ -#define SPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */ -#define OSC26MCTL __REG(MX27_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */ -#define PCDR0 __REG(MX27_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */ -#define PCDR1 __REG(MX27_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */ -#define PCCR0 __REG(MX27_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */ -#define PCCR1 __REG(MX27_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */ -#define CCSR __REG(MX27_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */ +/* PLL registers (base: MX27_CCM_BASE_ADDR) */ +#define MX27_CSCR 0x00 /* Clock Source Control Register */ +#define MX27_MPCTL0 0x04 /* MCU PLL Control Register 0 */ +#define MX27_MPCTL1 0x08 /* MCU PLL Control Register 1 */ +#define MX27_SPCTL0 0x0c /* System PLL Control Register 0 */ +#define MX27_SPCTL1 0x10 /* System PLL Control Register 1 */ +#define MX27_OSC26MCTL 0x14 /* Oscillator 26M Register */ +#define MX27_PCDR0 0x18 /* Peripheral Clock Divider Register 0 */ +#define MX27_PCDR1 0x1c /* Peripheral Clock Divider Register 1 */ +#define MX27_PCCR0 0x20 /* Peripheral Clock Control Register 0 */ +#define MX27_PCCR1 0x24 /* Peripheral Clock Control Register 1 */ +#define MX27_CCSR 0x28 /* Clock Control Status Register */ -#define CSCR_MPEN (1 << 0) -#define CSCR_SPEN (1 << 1) -#define CSCR_FPM_EN (1 << 2) -#define CSCR_OSC26M_DIS (1 << 3) -#define CSCR_OSC26M_DIV1P5 (1 << 4) -#define CSCR_AHB_DIV(d) (((d) & 0x3) << 8) -#define CSCR_ARM_DIV(d) (((d) & 0x3) << 12) -#define CSCR_ARM_SRC_MPLL (1 << 15) -#define CSCR_MCU_SEL (1 << 16) -#define CSCR_SP_SEL (1 << 17) -#define CSCR_MPLL_RESTART (1 << 18) -#define CSCR_SPLL_RESTART (1 << 19) -#define CSCR_MSHC_SEL (1 << 20) -#define CSCR_H264_SEL (1 << 21) -#define CSCR_SSI1_SEL (1 << 22) -#define CSCR_SSI2_SEL (1 << 23) -#define CSCR_SD_CNT(d) (((d) & 0x3) << 24) -#define CSCR_USB_DIV(d) (((d) & 0x7) << 28) -#define CSCR_UPDATE_DIS (1 << 31) +#define MX27_CSCR_MPEN (1 << 0) +#define MX27_CSCR_SPEN (1 << 1) +#define MX27_CSCR_FPM_EN (1 << 2) +#define MX27_CSCR_OSC26M_DIS (1 << 3) +#define MX27_CSCR_OSC26M_DIV1P5 (1 << 4) +#define MX27_CSCR_AHB_DIV(d) (((d) & 0x3) << 8) +#define MX27_CSCR_ARM_DIV(d) (((d) & 0x3) << 12) +#define MX27_CSCR_ARM_SRC_MPLL (1 << 15) +#define MX27_CSCR_MCU_SEL (1 << 16) +#define MX27_CSCR_SP_SEL (1 << 17) +#define MX27_CSCR_MPLL_RESTART (1 << 18) +#define MX27_CSCR_SPLL_RESTART (1 << 19) +#define MX27_CSCR_MSHC_SEL (1 << 20) +#define MX27_CSCR_H264_SEL (1 << 21) +#define MX27_CSCR_SSI1_SEL (1 << 22) +#define MX27_CSCR_SSI2_SEL (1 << 23) +#define MX27_CSCR_SD_CNT(d) (((d) & 0x3) << 24) +#define MX27_CSCR_USB_DIV(d) (((d) & 0x7) << 28) +#define MX27_CSCR_UPDATE_DIS (1 << 31) -#define MPCTL1_BRMO (1 << 6) -#define MPCTL1_LF (1 << 15) - -#define PCCR0_SSI2_EN (1 << 0) -#define PCCR0_SSI1_EN (1 << 1) -#define PCCR0_SLCDC_EN (1 << 2) -#define PCCR0_SDHC3_EN (1 << 3) -#define PCCR0_SDHC2_EN (1 << 4) -#define PCCR0_SDHC1_EN (1 << 5) -#define PCCR0_SDC_EN (1 << 6) -#define PCCR0_SAHARA_EN (1 << 7) -#define PCCR0_RTIC_EN (1 << 8) -#define PCCR0_RTC_EN (1 << 9) -#define PCCR0_PWM_EN (1 << 11) -#define PCCR0_OWIRE_EN (1 << 12) -#define PCCR0_MSHC_EN (1 << 13) -#define PCCR0_LCDC_EN (1 << 14) -#define PCCR0_KPP_EN (1 << 15) -#define PCCR0_IIM_EN (1 << 16) -#define PCCR0_I2C2_EN (1 << 17) -#define PCCR0_I2C1_EN (1 << 18) -#define PCCR0_GPT6_EN (1 << 19) -#define PCCR0_GPT5_EN (1 << 20) -#define PCCR0_GPT4_EN (1 << 21) -#define PCCR0_GPT3_EN (1 << 22) -#define PCCR0_GPT2_EN (1 << 23) -#define PCCR0_GPT1_EN (1 << 24) -#define PCCR0_GPIO_EN (1 << 25) -#define PCCR0_FEC_EN (1 << 26) -#define PCCR0_EMMA_EN (1 << 27) -#define PCCR0_DMA_EN (1 << 28) -#define PCCR0_CSPI3_EN (1 << 29) -#define PCCR0_CSPI2_EN (1 << 30) -#define PCCR0_CSPI1_EN (1 << 31) - -#define PCCR1_MSHC_BAUDEN (1 << 2) -#define PCCR1_NFC_BAUDEN (1 << 3) -#define PCCR1_SSI2_BAUDEN (1 << 4) -#define PCCR1_SSI1_BAUDEN (1 << 5) -#define PCCR1_H264_BAUDEN (1 << 6) -#define PCCR1_PERCLK4_EN (1 << 7) -#define PCCR1_PERCLK3_EN (1 << 8) -#define PCCR1_PERCLK2_EN (1 << 9) -#define PCCR1_PERCLK1_EN (1 << 10) -#define PCCR1_HCLK_USB (1 << 11) -#define PCCR1_HCLK_SLCDC (1 << 12) -#define PCCR1_HCLK_SAHARA (1 << 13) -#define PCCR1_HCLK_RTIC (1 << 14) -#define PCCR1_HCLK_LCDC (1 << 15) -#define PCCR1_HCLK_H264 (1 << 16) -#define PCCR1_HCLK_FEC (1 << 17) -#define PCCR1_HCLK_EMMA (1 << 18) -#define PCCR1_HCLK_EMI (1 << 19) -#define PCCR1_HCLK_DMA (1 << 20) -#define PCCR1_HCLK_CSI (1 << 21) -#define PCCR1_HCLK_BROM (1 << 22) -#define PCCR1_HCLK_ATA (1 << 23) -#define PCCR1_WDT_EN (1 << 24) -#define PCCR1_USB_EN (1 << 25) -#define PCCR1_UART6_EN (1 << 26) -#define PCCR1_UART5_EN (1 << 27) -#define PCCR1_UART4_EN (1 << 28) -#define PCCR1_UART3_EN (1 << 29) -#define PCCR1_UART2_EN (1 << 30) -#define PCCR1_UART1_EN (1 << 31) - -#define CCSR_32K_SR (1 << 15) - -/* SDRAM Controller registers bitfields */ -#define ESDCTL_PRCT(x) (((x) & 3f) << 0) -#define ESDCTL_BL (1 << 7) -#define ESDCTL_FP (1 << 8) -#define ESDCTL_PWDT(x) (((x) & 3) << 10) -#define ESDCTL_SREFR(x) (((x) & 7) << 13) -#define ESDCTL_DSIZ_16_UPPER (0 << 16) -#define ESDCTL_DSIZ_16_LOWER (0 << 16) -#define ESDCTL_DSIZ_32 (0 << 16) -#define ESDCTL_COL8 (0 << 20) -#define ESDCTL_COL9 (1 << 20) -#define ESDCTL_COL10 (2 << 20) -#define ESDCTL_ROW11 (0 << 24) -#define ESDCTL_ROW12 (1 << 24) -#define ESDCTL_ROW13 (2 << 24) -#define ESDCTL_ROW14 (3 << 24) -#define ESDCTL_ROW15 (4 << 24) -#define ESDCTL_SP (1 << 27) -#define ESDCTL_SMODE_NORMAL (0 << 28) -#define ESDCTL_SMODE_PRECHAGRE (1 << 28) -#define ESDCTL_SMODE_AUTO_REF (2 << 28) -#define ESDCTL_SMODE_LOAD_MODE (3 << 28) -#define ESDCTL_SMODE_MAN_REF (4 << 28) -#define ESDCTL_SDE (1 << 31) - -#define ESDCFG_TRC(x) (((x) & 0xf) << 0) -#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) -#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) -#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) -#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) -#define ESDCFG_TWR (1 << 15) -#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) -#define ESDCFG_TRP(x) (((x) & 0x3) << 18) -#define ESDCFG_TWTR (1 << 20) -#define ESDCFG_TXP(x) (((x) & 0x3) << 21) +#define MX27_MPCTL1_BRMO (1 << 6) +#define MX27_MPCTL1_LF (1 << 15) #endif /* _IMX27_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h index 57f65da..f641fe6 100644 --- a/arch/arm/mach-imx/include/mach/imx31-regs.h +++ b/arch/arm/mach-imx/include/mach/imx31-regs.h @@ -130,105 +130,61 @@ #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 -/* FIXME: Get rid of these */ -#define IMX_TIM1_BASE MX31_GPT1_BASE_ADDR -#define IMX_WDT_BASE MX31_WDOG_BASE_ADDR -#define IMX_ESD_BASE MX31_ESDCTL_BASE_ADDR -#define IMX_NFC_BASE MX31_NFC_BASE_ADDR -#define IOMUXC_BASE MX31_IOMUXC_BASE_ADDR - /* * Clock Controller Module (CCM) */ -#define CCM_CCMR 0x00 -#define CCM_PDR0 0x04 -#define CCM_PDR1 0x08 -#define CCM_RCSR 0x0c -#define CCM_MPCTL 0x10 -#define CCM_UPCTL 0x14 -#define CCM_SPCTL 0x18 -#define CCM_COSR 0x1C +#define MX31_CCM_CCMR 0x00 +#define MX31_CCM_PDR0 0x04 +#define MX31_CCM_PDR1 0x08 +#define MX31_CCM_RCSR 0x0c +#define MX31_CCM_MPCTL 0x10 +#define MX31_CCM_UPCTL 0x14 +#define MX31_CCM_SPCTL 0x18 +#define MX31_CCM_COSR 0x1C -/* - * ????????????? - */ -#define CCMR_MDS (1 << 7) -#define CCMR_SBYCS (1 << 4) -#define CCMR_MPE (1 << 3) -#define CCMR_PRCS_MASK (3 << 1) -#define CCMR_FPM (1 << 1) -#define CCMR_CKIH (2 << 1) +#define MX31_CCMR_MDS (1 << 7) +#define MX31_CCMR_SBYCS (1 << 4) +#define MX31_CCMR_MPE (1 << 3) +#define MX31_CCMR_PRCS_MASK (3 << 1) +#define MX31_CCMR_FPM (1 << 1) +#define MX31_CCMR_CKIH (2 << 1) -#define RCSR_NFMS (1 << 30) +#define MX31_RCSR_NFMS (1 << 30) -/* - * ????????????? - */ -#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) -#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11) -#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8) -#define PDR0_IPG_PODF(x) (((x) & 0x3) << 6) -#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3) -#define PDR0_MCU_PODF(x) ((x) & 0x7) +#define MX31_PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23) +#define MX31_PDR0_PER_PODF(x) (((x) & 0x1f) << 16) +#define MX31_PDR0_HSP_PODF(x) (((x) & 0x7) << 11) +#define MX31_PDR0_NFC_PODF(x) (((x) & 0x7) << 8) +#define MX31_PDR0_IPG_PODF(x) (((x) & 0x3) << 6) +#define MX31_PDR0_MAX_PODF(x) (((x) & 0x7) << 3) +#define MX31_PDR0_MCU_PODF(x) ((x) & 0x7) -#include "esdctl.h" - -/* - * ??????????? - */ -#define IOMUXC_GPR (IOMUXC_BASE + 0x8) -#define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) -#define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) +#define MX31_IOMUXC_GPR (IOMUXC_BASE + 0x8) +#define MX31_IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4) +#define MX31_IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4) /* * Signal Multiplexing (IOMUX) */ /* bits in the SW_MUX_CTL registers */ -#define MUX_CTL_OUT_GPIO_DR (0 << 4) -#define MUX_CTL_OUT_FUNC (1 << 4) -#define MUX_CTL_OUT_ALT1 (2 << 4) -#define MUX_CTL_OUT_ALT2 (3 << 4) -#define MUX_CTL_OUT_ALT3 (4 << 4) -#define MUX_CTL_OUT_ALT4 (5 << 4) -#define MUX_CTL_OUT_ALT5 (6 << 4) -#define MUX_CTL_OUT_ALT6 (7 << 4) -#define MUX_CTL_IN_NONE (0 << 0) -#define MUX_CTL_IN_GPIO (1 << 0) -#define MUX_CTL_IN_FUNC (2 << 0) -#define MUX_CTL_IN_ALT1 (4 << 0) -#define MUX_CTL_IN_ALT2 (8 << 0) +#define MX31_MUX_CTL_OUT_GPIO_DR (0 << 4) +#define MX31_MUX_CTL_OUT_FUNC (1 << 4) +#define MX31_MUX_CTL_OUT_ALT1 (2 << 4) +#define MX31_MUX_CTL_OUT_ALT2 (3 << 4) +#define MX31_MUX_CTL_OUT_ALT3 (4 << 4) +#define MX31_MUX_CTL_OUT_ALT4 (5 << 4) +#define MX31_MUX_CTL_OUT_ALT5 (6 << 4) +#define MX31_MUX_CTL_OUT_ALT6 (7 << 4) +#define MX31_MUX_CTL_IN_NONE (0 << 0) +#define MX31_MUX_CTL_IN_GPIO (1 << 0) +#define MX31_MUX_CTL_IN_FUNC (2 << 0) +#define MX31_MUX_CTL_IN_ALT1 (4 << 0) +#define MX31_MUX_CTL_IN_ALT2 (8 << 0) -#define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC) -#define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1) -#define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2) -#define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO) - -/* Register offsets based on IOMUXC_BASE */ -/* 0x00 .. 0x7b */ -#define MUX_CTL_RTS1 0x7c -#define MUX_CTL_CTS1 0x7d -#define MUX_CTL_DTR_DCE1 0x7e -#define MUX_CTL_DSR_DCE1 0x7f -#define MUX_CTL_CSPI2_SCLK 0x80 -#define MUX_CTL_CSPI2_SPI_RDY 0x81 -#define MUX_CTL_RXD1 0x82 -#define MUX_CTL_TXD1 0x83 -#define MUX_CTL_CSPI2_MISO 0x84 -/* 0x85 .. 0x8a */ -#define MUX_CTL_CSPI2_MOSI 0x8b - -/* The modes a specific pin can be in - * these macros can be used in mx31_gpio_mux() and have the form - * MUX_[contact name]__[pin function] - */ -#define MUX_RXD1_UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1) -#define MUX_TXD1_UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1) -#define MUX_RTS1_UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1) -#define MUX_RTS1_UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1) - -#define MUX_CSPI2_MOSI_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) -#define MUX_CSPI2_MISO_I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) +#define MX31_MUX_CTL_FUNC (MX31_MUX_CTL_OUT_FUNC | MX31_MUX_CTL_IN_FUNC) +#define MX31_MUX_CTL_ALT1 (MX31_MUX_CTL_OUT_ALT1 | MX31_MUX_CTL_IN_ALT1) +#define MX31_MUX_CTL_ALT2 (MX31_MUX_CTL_OUT_ALT2 | MX31_MUX_CTL_IN_ALT2) +#define MX31_MUX_CTL_GPIO (MX31_MUX_CTL_OUT_GPIO_DR | MX31_MUX_CTL_IN_GPIO) #endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h index 19f6389..bbfde23 100644 --- a/arch/arm/mach-imx/include/mach/imx35-regs.h +++ b/arch/arm/mach-imx/include/mach/imx35-regs.h @@ -130,47 +130,39 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 -/* FIXME: Get rid of these */ -#define IMX_WDT_BASE MX35_WDOG_BASE_ADDR -#define IMX_TIM1_BASE MX35_GPT1_BASE_ADDR -#define IMX_ESD_BASE MX35_ESDCTL_BASE_ADDR -#define IMX_IOMUXC_BASE MX35_IOMUXC_BASE_ADDR -#define IMX_CCM_BASE MX35_CCM_BASE_ADDR -#define IMX_NFC_BASE MX35_NFC_BASE_ADDR - /* * Clock Controller Module (CCM) */ -#define CCM_CCMR 0x00 -#define CCM_PDR0 0x04 -#define CCM_PDR1 0x08 -#define CCM_PDR2 0x0C -#define CCM_PDR3 0x10 -#define CCM_PDR4 0x14 -#define CCM_RCSR 0x18 -#define CCM_MPCTL 0x1C -#define CCM_PPCTL 0x20 -#define CCM_ACMR 0x24 -#define CCM_COSR 0x28 -#define CCM_CGR0 0x2C -#define CCM_CGR1 0x30 -#define CCM_CGR2 0x34 -#define CCM_CGR3 0x38 +#define MX35_CCM_CCMR 0x00 +#define MX35_CCM_PDR0 0x04 +#define MX35_CCM_PDR1 0x08 +#define MX35_CCM_PDR2 0x0C +#define MX35_CCM_PDR3 0x10 +#define MX35_CCM_PDR4 0x14 +#define MX35_CCM_RCSR 0x18 +#define MX35_CCM_MPCTL 0x1C +#define MX35_CCM_PPCTL 0x20 +#define MX35_CCM_ACMR 0x24 +#define MX35_CCM_COSR 0x28 +#define MX35_CCM_CGR0 0x2C +#define MX35_CCM_CGR1 0x30 +#define MX35_CCM_CGR2 0x34 +#define MX35_CCM_CGR3 0x38 -#define CCM_CGR0_CSPI1_SHIFT 10 -#define CCM_CGR1_FEC_SHIFT 0 -#define CCM_CGR1_I2C1_SHIFT 10 -#define CCM_CGR1_SDHC1_SHIFT 26 -#define CCM_CGR2_USB_SHIFT 22 +#define MX35_CCM_CGR0_CSPI1_SHIFT 10 +#define MX35_CCM_CGR1_FEC_SHIFT 0 +#define MX35_CCM_CGR1_I2C1_SHIFT 10 +#define MX35_CCM_CGR1_SDHC1_SHIFT 26 +#define MX35_CCM_CGR2_USB_SHIFT 22 -#define CCM_RCSR_MEM_CTRL_SHIFT 25 -#define CCM_RCSR_MEM_TYPE_SHIFT 23 +#define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25 +#define MX35_CCM_RCSR_MEM_TYPE_SHIFT 23 -#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) -#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) -#define PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) -#define PDR0_HSP_PODF(x) (((x) & 0x3) << 20) -#define PDR0_AUTO_CON (1 << 0) -#define PDR0_PER_SEL (1 << 26) +#define MX35_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) +#define MX35_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) +#define MX35_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16) +#define MX35_PDR0_HSP_PODF(x) (((x) & 0x3) << 20) +#define MX35_PDR0_AUTO_CON (1 << 0) +#define MX35_PDR0_PER_SEL (1 << 26) #endif /* __ASM_ARCH_MX35_REGS_H */ diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h index c451004..8eb74cd 100644 --- a/arch/arm/mach-imx/include/mach/imx51-regs.h +++ b/arch/arm/mach-imx/include/mach/imx51-regs.h @@ -1,10 +1,6 @@ #ifndef __MACH_IMX51_REGS_H #define __MACH_IMX51_REGS_H -#define IMX_TIM1_BASE 0x73fa0000 -#define IMX_WDT_BASE 0x73f98000 -#define IMX_IOMUXC_BASE 0x73fa8000 - /* WEIM registers */ #define WEIM_CSxGCR1(n) (((n) * 0x18) + 0x00) #define WEIM_CSxGCR2(n) (((n) * 0x18) + 0x04) diff --git a/arch/arm/mach-imx/include/mach/imx53-regs.h b/arch/arm/mach-imx/include/mach/imx53-regs.h index e57d1ab..8025e97 100644 --- a/arch/arm/mach-imx/include/mach/imx53-regs.h +++ b/arch/arm/mach-imx/include/mach/imx53-regs.h @@ -1,10 +1,6 @@ #ifndef __MACH_IMX53_REGS_H #define __MACH_IMX53_REGS_H -#define IMX_TIM1_BASE 0X53FA0000 -#define IMX_WDT_BASE 0X53F98000 -#define IMX_IOMUXC_BASE 0X53FA8000 - #define MX53_IROM_BASE_ADDR 0x0 /* diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index eca4fa6..716e6b4 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -1,10 +1,6 @@ #ifndef __MACH_IMX6_REGS_H #define __MACH_IMX6_REGS_H -#define IMX_TIM1_BASE 0x02098000 -#define IMX_WDT_BASE 0x020bc000 -#define IMX_IOMUXC_BASE 0x020e0000 - #define MX6_AIPS1_ARB_BASE_ADDR 0x02000000 #define MX6_AIPS2_ARB_BASE_ADDR 0x02100000 @@ -12,8 +8,6 @@ #define MX6_ATZ1_BASE_ADDR MX6_AIPS1_ARB_BASE_ADDR #define MX6_ATZ2_BASE_ADDR MX6_AIPS2_ARB_BASE_ADDR -#define IPU_CTRL_BASE_ADDR 0x02400000 - /* slots 0,7 of SDMA reserved, therefore left unused in IPMUX3 */ #define MX6_SPDIF_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x04000) #define MX6_ECSPI1_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x08000) diff --git a/arch/arm/mach-imx/include/mach/iomux-mx1.h b/arch/arm/mach-imx/include/mach/iomux-mx1.h new file mode 100644 index 0000000..51317d3 --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-mx1.h @@ -0,0 +1,135 @@ +#ifndef __MACH_IOMUX_MX1_H +#define __MACH_IOMUX_MX1_H + +#include + +/* + * FIXME: This list is not completed. The correct directions are + * missing on some (many) pins + */ +#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) +#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) +#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) +#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) +#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) +#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) +#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) +#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) +#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) +#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) +#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) +#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) +#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) +#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) +#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) +#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) +#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) +#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) +#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) +#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) +#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) +#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) +#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) +#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) +#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) +#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) +#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) +#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) +#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) +#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) +#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) +#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) +#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) +#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) +#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) +#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) +#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) +#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) +#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) +#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) +#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) +#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) +#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) +#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) +#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) +#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) +#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) +#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) +#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) +#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) +#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) +#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) +#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) +#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) +#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) +#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) +#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) +#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) +#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) +#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) +#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) +#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) +#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) +#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) +#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) +#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) +#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) +#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) +#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) +#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) +#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) +#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) +#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) +#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) +#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) +#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) +#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) +#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) +#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) +#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) +#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) +#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) +#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) +#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) +#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) +#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) +#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) +#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) +#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) +#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) +#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) +#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) +#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) +#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) +#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) +#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) +#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) +#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) +#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) +#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) +#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) +#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) +#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) +#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) +#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) +#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) +#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) +#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) +#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) +#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) +#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) +#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) +#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) +#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) +#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) +#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) +#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) +#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) +#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) +#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) +#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) +#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) +#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) +#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) + +#endif /* __MACH_IOMUX_MX1_H */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx21.h b/arch/arm/mach-imx/include/mach/iomux-mx21.h index 482c4f2..203190d 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx21.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx21.h @@ -13,6 +13,7 @@ #ifndef __MACH_IOMUX_MX21_H__ #define __MACH_IOMUX_MX21_H__ +#include #include /* Primary GPIO pin functions */ diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h index ff9d657..7d24967 100644 --- a/arch/arm/mach-imx/include/mach/iomux-mx27.h +++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h @@ -15,6 +15,7 @@ #ifndef __MACH_IOMUX_MX27_H__ #define __MACH_IOMUX_MX27_H__ +#include #include /* Primary GPIO pin functions */ diff --git a/arch/arm/mach-imx/include/mach/iomux-v1.h b/arch/arm/mach-imx/include/mach/iomux-v1.h new file mode 100644 index 0000000..55fbcdb --- /dev/null +++ b/arch/arm/mach-imx/include/mach/iomux-v1.h @@ -0,0 +1,48 @@ +#ifndef __MACH_IOMUX_V1_H__ +#define __MACH_IOMUX_V1_H__ + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +#define GPIO_GIUS (1 << 16) + +void imx_iomuxv1_init(void __iomem *base); + +#endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/mach-imx/include/mach/revision.h b/arch/arm/mach-imx/include/mach/revision.h new file mode 100644 index 0000000..bc6f20a --- /dev/null +++ b/arch/arm/mach-imx/include/mach/revision.h @@ -0,0 +1,22 @@ +#ifndef __MACH_REVISION_H__ +#define __MACH_REVISION_H__ + +/* silicon revisions */ +#define IMX_CHIP_REV_1_0 0x10 +#define IMX_CHIP_REV_1_1 0x11 +#define IMX_CHIP_REV_1_2 0x12 +#define IMX_CHIP_REV_1_3 0x13 +#define IMX_CHIP_REV_2_0 0x20 +#define IMX_CHIP_REV_2_1 0x21 +#define IMX_CHIP_REV_2_2 0x22 +#define IMX_CHIP_REV_2_3 0x23 +#define IMX_CHIP_REV_3_0 0x30 +#define IMX_CHIP_REV_3_1 0x31 +#define IMX_CHIP_REV_3_2 0x32 +#define IMX_CHIP_REV_UNKNOWN 0xff + +int imx_silicon_revision(void); + +void imx_set_silicon_revision(const char *soc, int revision); + +#endif /* __MACH_REVISION_H__ */ diff --git a/arch/arm/mach-imx/iomux-v1.c b/arch/arm/mach-imx/iomux-v1.c index f2dfdb3..f8f9061 100644 --- a/arch/arm/mach-imx/iomux-v1.c +++ b/arch/arm/mach-imx/iomux-v1.c @@ -1,5 +1,6 @@ #include -#include +#include +#include /* * GPIO Module and I/O Multiplexer @@ -8,23 +9,25 @@ * i.MX1 and i.MXL: 0 <= x <= 3 * i.MX27 : 0 <= x <= 5 */ -#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8) -#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8) -#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8) -#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8) -#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8) -#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8) -#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8) -#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8) -#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8) -#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8) -#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8) -#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8) -#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8) -#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8) -#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8) -#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8) -#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8) +#define DDIR 0x00 +#define OCR1 0x04 +#define OCR2 0x08 +#define ICONFA1 0x0c +#define ICONFA2 0x10 +#define ICONFB1 0x14 +#define ICONFB2 0x18 +#define DR 0x1c +#define GIUS 0x20 +#define SSR 0x24 +#define ICR1 0x28 +#define ICR2 0x2c +#define IMR 0x30 +#define ISR 0x34 +#define GPR 0x38 +#define SWR 0x3c +#define PUEN 0x40 + +static void __iomem *iomuxv1_base; void imx_gpio_mode(int gpio_mode) { @@ -33,55 +36,81 @@ unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; - unsigned int tmp; + void __iomem *portbase = iomuxv1_base + port * 0x100; + uint32_t val; + + if (!iomuxv1_base) + return; /* Pullup enable */ - if(gpio_mode & GPIO_PUEN) - PUEN(port) |= (1 << pin); + val = readl(portbase + PUEN); + if (gpio_mode & GPIO_PUEN) + val |= (1 << pin); else - PUEN(port) &= ~(1 << pin); + val &= ~(1 << pin); + writel(val, portbase + PUEN); /* Data direction */ - if(gpio_mode & GPIO_OUT) - DDIR(port) |= 1 << pin; + val = readl(portbase + DDIR); + if (gpio_mode & GPIO_OUT) + val |= 1 << pin; else - DDIR(port) &= ~(1 << pin); + val &= ~(1 << pin); + writel(val, portbase + DDIR); /* Primary / alternate function */ - if(gpio_mode & GPIO_AF) - GPR(port) |= (1 << pin); + val = readl(portbase + GPR); + if (gpio_mode & GPIO_AF) + val |= (1 << pin); else - GPR(port) &= ~(1 << pin); + val &= ~(1 << pin); + writel(val, portbase + GPR); /* use as gpio? */ - if(!(gpio_mode & (GPIO_PF | GPIO_AF))) - GIUS(port) |= (1 << pin); + val = readl(portbase + GIUS); + if (!(gpio_mode & (GPIO_PF | GPIO_AF))) + val |= (1 << pin); else - GIUS(port) &= ~(1 << pin); + val &= ~(1 << pin); + writel(val, portbase + GIUS); /* Output / input configuration */ if (pin < 16) { - tmp = OCR1(port); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - OCR1(port) = tmp; + val = readl(portbase + OCR1); + val &= ~(3 << (pin * 2)); + val |= (ocr << (pin * 2)); + writel(val, portbase + OCR1); - ICONFA1(port) &= ~(3 << (pin * 2)); - ICONFA1(port) |= aout << (pin * 2); - ICONFB1(port) &= ~(3 << (pin * 2)); - ICONFB1(port) |= bout << (pin * 2); + val = readl(portbase + ICONFA1); + val &= ~(3 << (pin * 2)); + val |= aout << (pin * 2); + writel(val, portbase + ICONFA1); + + val = readl(portbase + ICONFB1); + val &= ~(3 << (pin * 2)); + val |= bout << (pin * 2); + writel(val, portbase + ICONFB1); } else { pin -= 16; - tmp = OCR2(port); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - OCR2(port) = tmp; + val = readl(portbase + OCR2); + val &= ~(3 << (pin * 2)); + val |= (ocr << (pin * 2)); + writel(val, portbase + OCR2); - ICONFA2(port) &= ~(3 << (pin * 2)); - ICONFA2(port) |= aout << (pin * 2); - ICONFB2(port) &= ~(3 << (pin * 2)); - ICONFB2(port) |= bout << (pin * 2); + val = readl(portbase + ICONFA2); + val &= ~(3 << (pin * 2)); + val |= aout << (pin * 2); + writel(val, portbase + ICONFA2); + + val = readl(portbase + ICONFB2); + val &= ~(3 << (pin * 2)); + val |= bout << (pin * 2); + writel(val, portbase + ICONFB2); } } +void imx_iomuxv1_init(void __iomem *base) +{ + iomuxv1_base = base; +} diff --git a/arch/arm/mach-imx/iomux-v2.c b/arch/arm/mach-imx/iomux-v2.c index 08af54c..dbbb8a2 100644 --- a/arch/arm/mach-imx/iomux-v2.c +++ b/arch/arm/mach-imx/iomux-v2.c @@ -16,19 +16,22 @@ #include #include -#include +#include #include /* * IOMUX register (base) addresses */ -#define IOMUXINT_OBS1 (IOMUXC_BASE + 0x000) -#define IOMUXINT_OBS2 (IOMUXC_BASE + 0x004) -#define IOMUXGPR (IOMUXC_BASE + 0x008) -#define IOMUXSW_MUX_CTL (IOMUXC_BASE + 0x00C) -#define IOMUXSW_PAD_CTL (IOMUXC_BASE + 0x154) +#define IOMUXINT_OBS1 0x000 +#define IOMUXINT_OBS2 0x004 +#define IOMUXGPR 0x008 +#define IOMUXSW_MUX_CTL 0x00C +#define IOMUXSW_PAD_CTL 0x154 #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) + +static void __iomem *base; + /* * set the mode for a IOMUX pin. */ @@ -37,7 +40,10 @@ u32 field, l, mode, ret = 0; void __iomem *reg; - reg = (void *)(IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK)); + if (!base) + return -EINVAL; + + reg = base + IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); field = pin_mode & 0x3; mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; @@ -61,8 +67,11 @@ u32 field, l; void __iomem *reg; + if (!base) + return; + pin &= IOMUX_PADNUM_MASK; - reg = (void *)(IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4); + reg = base + IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4; field = (pin + 2) % 3; pr_debug("%s: reg offset = 0x%x, field = %d\n", @@ -83,14 +92,51 @@ { u32 l; - l = readl(IOMUXGPR); + if (!base) + return; + + l = readl(base + IOMUXGPR); if (en) l |= gp; else l &= ~gp; - writel(l, IOMUXGPR); + writel(l, base + IOMUXGPR); } EXPORT_SYMBOL(mxc_iomux_set_gpr); +static int imx_iomux_probe(struct device_d *dev) +{ + base = dev_request_mem_region(dev, 0); + return 0; +} + +static __maybe_unused struct of_device_id imx_iomux_dt_ids[] = { + { + .compatible = "fsl,imx31-iomux", + }, { + /* sentinel */ + } +}; + +static struct platform_device_id imx_iomux_ids[] = { + { + .name = "imx31-iomux", + }, { + /* sentinel */ + }, +}; + +static struct driver_d imx_iomux_driver = { + .name = "imx-iomuxv2", + .probe = imx_iomux_probe, + .of_compatible = DRV_OF_COMPAT(imx_iomux_dt_ids), + .id_table = imx_iomux_ids, +}; + +static int imx_iomux_init(void) +{ + return platform_driver_register(&imx_iomux_driver); +} +postcore_initcall(imx_iomux_init); diff --git a/arch/arm/mach-imx/iomux-v3.c b/arch/arm/mach-imx/iomux-v3.c index 948b610..8a6064d 100644 --- a/arch/arm/mach-imx/iomux-v3.c +++ b/arch/arm/mach-imx/iomux-v3.c @@ -15,11 +15,11 @@ * */ #include +#include #include #include -#include -static void __iomem *base = (void *)IMX_IOMUXC_BASE; +static void __iomem *base; /* * configures a single pad in the iomuxer @@ -33,6 +33,9 @@ u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; + if (!base) + return -EINVAL; + debug("%s: mux 0x%08x -> 0x%04x pad: 0x%08x -> 0x%04x sel_inp: 0x%08x -> 0x%04x\n", __func__, mux_mode, mux_ctrl_ofs, pad_ctrl, pad_ctrl_ofs, sel_input, sel_input_ofs); @@ -66,3 +69,39 @@ return 0; } EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); + +static int imx_iomux_probe(struct device_d *dev) +{ + base = dev_request_mem_region(dev, 0); + + return 0; +} + +static __maybe_unused struct of_device_id imx_iomux_dt_ids[] = { + { + .compatible = "fsl,imx35-iomux", + }, { + /* sentinel */ + } +}; + +static struct platform_device_id imx_iomux_ids[] = { + { + .name = "imx35-iomux", + }, { + /* sentinel */ + }, +}; + +static struct driver_d imx_iomux_driver = { + .name = "imx-iomuxv3", + .probe = imx_iomux_probe, + .of_compatible = DRV_OF_COMPAT(imx_iomux_dt_ids), + .id_table = imx_iomux_ids, +}; + +static int imx_iomux_init(void) +{ + return platform_driver_register(&imx_iomux_driver); +} +postcore_initcall(imx_iomux_init); diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c index fff9a12..f298a36 100644 --- a/arch/arm/mach-imx/nand.c +++ b/arch/arm/mach-imx/nand.c @@ -12,20 +12,23 @@ */ #include -#include +#include +#include +#include +#include +#include #include -#if defined(CONFIG_ARCH_IMX35) || defined (CONFIG_ARCH_IMX25) - #define RCSR_NFC_FMS (1 << 8) #define RCSR_NFC_4K (1 << 9) #define RCSR_NFC_16BIT_SEL (1 << 14) -void imx_nand_set_layout(int writesize, int datawidth) +static __maybe_unused void imx25_35_nand_set_layout(void __iomem *reg_rcsr, + int writesize, int datawidth) { unsigned int rcsr; - rcsr = readl(IMX_CCM_BASE + CCM_RCSR); + rcsr = readl(reg_rcsr); switch (writesize) { case 512: @@ -52,19 +55,18 @@ break; } - writel(rcsr, IMX_CCM_BASE + CCM_RCSR); + writel(rcsr, reg_rcsr); } -#elif defined(CONFIG_ARCH_IMX21) || defined (CONFIG_ARCH_IMX27) - #define FMCR_NF_FMS (1 << 5) #define FMCR_NF_16BIT_SEL (1 << 4) -void imx_nand_set_layout(int writesize, int datawidth) +static __maybe_unused void imx21_27_nand_set_layout(void __iomem *reg_fmcr, + int writesize, int datawidth) { unsigned int fmcr; - fmcr = FMCR; + fmcr = readl(reg_fmcr); switch (writesize) { case 512: @@ -88,23 +90,29 @@ break; } - FMCR = fmcr; + writel(fmcr, reg_fmcr); } -#elif defined CONFIG_ARCH_IMX51 || defined CONFIG_ARCH_IMX53 - void imx_nand_set_layout(int writesize, int datawidth) { - /* Just silence the compiler warning below. On i.MX51 we don't - * have external boot. - */ -} - -#else -#warning using empty imx_nand_set_layout(). NAND flash will not work properly if not booting from it - -void imx_nand_set_layout(int writesize, int datawidth) -{ -} - +#ifdef CONFIG_ARCH_IMX21 + if (cpu_is_mx21()) + imx21_27_nand_set_layout((void *)(MX21_SYSCTRL_BASE_ADDR + + 0x14), writesize, datawidth); #endif +#ifdef CONFIG_ARCH_IMX27 + if (cpu_is_mx27()) + imx21_27_nand_set_layout((void *)(MX27_SYSCTRL_BASE_ADDR + + 0x14), writesize, datawidth); +#endif +#ifdef CONFIG_ARCH_IMX25 + if (cpu_is_mx25()) + imx25_35_nand_set_layout((void *)MX25_CCM_BASE_ADDR + + MX25_CCM_RCSR, writesize, datawidth); +#endif +#ifdef CONFIG_ARCH_IMX35 + if (cpu_is_mx35()) + imx25_35_nand_set_layout((void *)MX35_CCM_BASE_ADDR + + MX35_CCM_RCSR, writesize, datawidth); +#endif +} diff --git a/arch/arm/mach-imx/reset_source.c b/arch/arm/mach-imx/reset_source.c deleted file mode 100644 index e7b2a90..0000000 --- a/arch/arm/mach-imx/reset_source.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2012 Juergen Beisert - - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_ARCH_IMX1 -# define IMX_RESET_SRC_WDOG (1 << 1) -# define IMX_RESET_SRC_HRDRESET (1 << 0) -/* let the compiler sort out useless code on this arch */ -# define IMX_RESET_SRC_WARMSTART 0 -# define IMX_RESET_SRC_COLDSTART 0 -#else - /* WRSR checked for i.MX25, i.MX27, i.MX31, i.MX35 and i.MX51 */ -# define WDOG_WRSR 0x04 - /* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */ -# define IMX_RESET_SRC_WARMSTART (1 << 0) - /* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */ -# define IMX_RESET_SRC_WDOG (1 << 1) - /* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */ -# define IMX_RESET_SRC_HRDRESET (1 << 3) - /* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */ -# define IMX_RESET_SRC_COLDSTART (1 << 4) -#endif - -static unsigned read_detection_register(void) -{ -#ifdef CONFIG_ARCH_IMX1 - return readl(IMX_SYSCTRL_BASE); -#else - return readw(IMX_WDT_BASE + WDOG_WRSR); -#endif -} - -static int imx_detect_reset_source(void) -{ - unsigned reg = read_detection_register(); - - if (reg & IMX_RESET_SRC_COLDSTART) { - set_reset_source(RESET_POR); - return 0; - } - - if (reg & (IMX_RESET_SRC_HRDRESET | IMX_RESET_SRC_WARMSTART)) { - set_reset_source(RESET_RST); - return 0; - } - - if (reg & IMX_RESET_SRC_WDOG) { - set_reset_source(RESET_WDG); - return 0; - } - - /* else keep the default 'unknown' state */ - return 0; -} - -device_initcall(imx_detect_reset_source); diff --git a/commands/Kconfig b/commands/Kconfig index 460bc2c..1336097 100644 --- a/commands/Kconfig +++ b/commands/Kconfig @@ -514,6 +514,11 @@ endmenu +config CMD_BAREBOX_UPDATE + tristate + select BAREBOX_UPDATE + prompt "barebox-update" + config CMD_TIMEOUT tristate prompt "timeout" diff --git a/commands/Makefile b/commands/Makefile index 6540802..53c8c51 100644 --- a/commands/Makefile +++ b/commands/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_CMD_CLK) += clk.o obj-$(CONFIG_CMD_TFTP) += tftp.o obj-$(CONFIG_CMD_FILETYPE) += filetype.o +obj-$(CONFIG_CMD_BAREBOX_UPDATE)+= barebox-update.o diff --git a/commands/barebox-update.c b/commands/barebox-update.c new file mode 100644 index 0000000..f550572 --- /dev/null +++ b/commands/barebox-update.c @@ -0,0 +1,86 @@ +/* + * barebox-update.c - update barebox + * + * Copyright (c) 2012 Sascha Hauer , Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include + +static int do_barebox_update(int argc, char *argv[]) +{ + int opt, ret; + struct bbu_data data = {}; + + while ((opt = getopt(argc, argv, "t:yf:ld:")) > 0) { + switch (opt) { + case 'd': + data.devicefile = optarg; + break; + case 'f': + data.force = simple_strtoul(optarg, NULL, 0); + data.flags |= BBU_FLAG_FORCE; + break; + case 't': + data.handler_name = optarg; + break; + case 'y': + data.flags |= BBU_FLAG_YES; + break; + case 'l': + printf("registered update handlers:\n"); + bbu_handlers_list(); + return 0; + default: + return COMMAND_ERROR_USAGE; + } + } + + if (!(argc - optind)) + return COMMAND_ERROR_USAGE; + + data.imagefile = argv[optind]; + + data.image = read_file(data.imagefile, &data.len); + if (!data.image) + return -errno; + + ret = barebox_update(&data); + + free(data.image); + + return ret; +} + +BAREBOX_CMD_HELP_START(barebox_update) +BAREBOX_CMD_HELP_USAGE("barebox_update [OPTIONS] \n") +BAREBOX_CMD_HELP_SHORT("Update barebox to persistent media\n") +BAREBOX_CMD_HELP_OPT("-t ", "\n") +BAREBOX_CMD_HELP_OPT("-d ", "write image to instead of handler default\n") +BAREBOX_CMD_HELP_OPT(" ", "Can be used for debugging purposes (-d /tmpfile)\n") +BAREBOX_CMD_HELP_OPT("-y\t", "yes. Do not ask for confirmation\n") +BAREBOX_CMD_HELP_OPT("-f ", "Set force level\n") +BAREBOX_CMD_HELP_OPT("-l\t", "list registered targets\n") +BAREBOX_CMD_HELP_END + +BAREBOX_CMD_START(barebox_update) + .cmd = do_barebox_update, + .usage = "update barebox", + BAREBOX_CMD_HELP(cmd_barebox_update_help) +BAREBOX_CMD_END diff --git a/common/Kconfig b/common/Kconfig index 107774c..d60db80 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -58,6 +58,9 @@ config STDDEV bool +config BAREBOX_UPDATE + bool + menu "General Settings " config LOCALVERSION diff --git a/common/Makefile b/common/Makefile index 132bd06..d82fc99 100644 --- a/common/Makefile +++ b/common/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PASSWORD) += password.o obj-$(CONFIG_MODULES) += module.o obj-$(CONFIG_FLEXIBLE_BOOTARGS) += bootargs.o +obj-$(CONFIG_BAREBOX_UPDATE) += bbu.o extra-$(CONFIG_MODULES) += module.lds extra-y += barebox_default_env barebox_default_env.h diff --git a/common/bbu.c b/common/bbu.c new file mode 100644 index 0000000..92f8d2b --- /dev/null +++ b/common/bbu.c @@ -0,0 +1,150 @@ +/* + * bbu.c - barebox update functions + * + * Copyright (c) 2012 Sascha Hauer , Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include + +static LIST_HEAD(bbu_image_handlers); + +int bbu_force(struct bbu_data *data, const char *fmt, ...) +{ + va_list args; + + printf("UPDATE: "); + + va_start(args, fmt); + + vprintf(fmt, args); + + va_end(args); + + if (!(data->flags & BBU_FLAG_FORCE)) + goto out; + + if (!data->force) + goto out; + + data->force--; + + printf(" (forced)\n"); + + return 1; +out: + printf("\n"); + + return 0; +} + +int bbu_confirm(struct bbu_data *data) +{ + int key; + + if (data->flags & BBU_FLAG_YES) + return 0; + + printf("update barebox from %s using handler %s to %s (y/n)?\n", + data->imagefile, data->handler_name, + data->devicefile); + + key = read_key(); + + if (key == 'y') + return 0; + + return -EINTR; +} + +static struct bbu_handler *bbu_find_handler(const char *name, unsigned long flags) +{ + struct bbu_handler *handler; + + list_for_each_entry(handler, &bbu_image_handlers, list) { + if (!name) { + if (flags & BBU_HANDLER_FLAG_DEFAULT) + return handler; + continue; + } + + if (!strcmp(handler->name, name)) + return handler; + } + + return NULL; +} + +/* + * do a barebox update with data from *data + */ +int barebox_update(struct bbu_data *data) +{ + struct bbu_handler *handler; + int ret; + + handler = bbu_find_handler(data->handler_name, data->flags); + if (!handler) + return -ENODEV; + + if (!data->devicefile) + data->devicefile = handler->devicefile; + + ret = handler->handler(handler, data); + if (ret == -EINTR) + printf("update aborted\n"); + + if (!ret) + printf("update succeeded\n"); + + return ret; +} + +/* + * print a list of all registered update handlers + */ +void bbu_handlers_list(void) +{ + struct bbu_handler *handler; + + if (list_empty(&bbu_image_handlers)) + printf("(none)\n"); + + list_for_each_entry(handler, &bbu_image_handlers, list) + printf("%s%-11s -> %-10s\n", + handler->flags & BBU_HANDLER_FLAG_DEFAULT ? + "* " : " ", + handler->name, + handler->devicefile); +} + +/* + * register a new update handler + */ +int bbu_register_handler(struct bbu_handler *handler) +{ + if (bbu_find_handler(handler->name, 0)) + return -EBUSY; + + if (handler->flags & BBU_HANDLER_FLAG_DEFAULT && + bbu_find_handler(NULL, BBU_HANDLER_FLAG_DEFAULT)) + return -EBUSY; + + list_add_tail(&handler->list, &bbu_image_handlers); + + return 0; +} diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 39a75a4..3cc7163 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -1,2 +1,3 @@ -obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o clk-mux.o +obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \ + clk-mux.o clk-gate.o obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c new file mode 100644 index 0000000..cf1bb1a --- /dev/null +++ b/drivers/clk/clk-gate.c @@ -0,0 +1,78 @@ +/* + * clk-gate.c - generic barebox clock support. Based on Linux clk support + * + * Copyright (c) 2012 Sascha Hauer , Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include + +struct clk_gate { + struct clk clk; + void __iomem *reg; + int shift; + const char *parent; +}; + +static int clk_gate_enable(struct clk *clk) +{ + struct clk_gate *g = container_of(clk, struct clk_gate, clk); + u32 val; + + val = readl(g->reg); + val |= 1 << g->shift; + writel(val, g->reg); + + return 0; +} + +static void clk_gate_disable(struct clk *clk) +{ + struct clk_gate *g = container_of(clk, struct clk_gate, clk); + u32 val; + + val = readl(g->reg); + val &= ~(1 << g->shift); + writel(val, g->reg); +} + +struct clk_ops clk_gate_ops = { + .enable = clk_gate_enable, + .disable = clk_gate_disable, +}; + +struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg, + u8 shift) +{ + struct clk_gate *g = xzalloc(sizeof(*g)); + int ret; + + g->parent = parent; + g->reg = reg; + g->shift = shift; + g->clk.ops = &clk_gate_ops; + g->clk.name = name; + g->clk.parent_names = &g->parent; + g->clk.num_parents = 1; + + ret = clk_register(&g->clk); + if (ret) { + free(g); + return ERR_PTR(ret); + } + + return &g->clk; +} diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c index ef927c5..7a207e3 100644 --- a/drivers/mtd/nand/nand_imx.c +++ b/drivers/mtd/nand/nand_imx.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -1107,12 +1106,6 @@ struct nand_ecclayout *oob_smallpage, *oob_largepage, *oob_4kpage; int err = 0; -#ifdef CONFIG_ARCH_IMX27 - PCCR1 |= PCCR1_NFC_BAUDEN; -#endif -#ifdef CONFIG_ARCH_IMX21 - PCCR0 |= PCCR0_NFC_EN; -#endif /* Allocate memory for MTD device structure and private data */ host = kzalloc(sizeof(struct imx_nand_host) + NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL); diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c index de4bd6e..2378a19 100644 --- a/drivers/net/fec_imx.c +++ b/drivers/net/fec_imx.c @@ -30,7 +30,6 @@ #include #include -#include #include #ifndef CONFIG_ARCH_MXS # include @@ -310,7 +309,7 @@ } if (fec->xcv_type == RMII) { - if (cpu_is_mx28()) { + if (fec_is_imx28(fec)) { rcntl |= FEC_R_CNTRL_RMII_MODE | FEC_R_CNTRL_FCE | FEC_R_CNTRL_NO_LGTH_CHECK; } else { @@ -340,7 +339,7 @@ xwmrk = 0x2; /* set ENET tx at store and forward mode */ - if (cpu_is_mx6()) + if (fec_is_imx6(fec)) xwmrk |= 1 << 8; writel(xwmrk, fec->regs + FEC_X_WMRK); @@ -407,7 +406,7 @@ ecr = FEC_ECNTRL_ETHER_EN; /* Enable Swap to support little-endian device */ - if (cpu_is_mx6()) + if (fec_is_imx6(fec)) ecr |= 0x100; writel(ecr, fec->regs + FEC_ECNTRL); @@ -481,7 +480,7 @@ * Note: We are always using the first buffer for transmission, * the second will be empty and only used to stop the DMA engine */ - if (cpu_is_mx28()) + if (fec_is_imx28(fec)) eth_data = imx28_fix_endianess_wr(eth_data, (data_length + 3) >> 2); writew(data_length, &fec->tbd_base[fec->tbd_index].data_length); @@ -548,7 +547,7 @@ printf("some error: 0x%08x\n", ievent); return 0; } - if (!cpu_is_mx28()) { + if (!fec_is_imx28(fec)) { if (ievent & FEC_IEVENT_HBERR) { /* Heartbeat error */ writel(readl(fec->regs + FEC_X_CNTRL) | 0x1, @@ -574,7 +573,7 @@ if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && ((readw(&rbd->data_length) - 4) > 14)) { - if (cpu_is_mx28()) + if (fec_is_imx28(fec)) imx28_fix_endianess_rd( phys_to_virt(readl(&rbd->data_pointer)), (readw(&rbd->data_length) + 3) >> 2); @@ -628,10 +627,14 @@ struct fec_priv *fec; void *base; int ret; -#ifdef CONFIG_ARCH_IMX27 - PCCR0 |= PCCR0_FEC_EN; -#endif + enum fec_type type; + + ret = dev_get_drvdata(dev, (unsigned long *)&type); + if (ret) + return ret; + fec = xzalloc(sizeof(*fec)); + fec->type = type; edev = &fec->edev; dev->priv = fec; edev->priv = fec; @@ -674,16 +677,21 @@ fec_alloc_receive_packets(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); - fec->xcv_type = pdata->xcv_type; + if (pdata) { + fec->xcv_type = pdata->xcv_type; + fec->phy_init = pdata->phy_init; + fec->phy_addr = pdata->phy_addr; + } else { + fec->xcv_type = MII100; + fec->phy_addr = -1; + } fec_init(edev); if (fec->xcv_type != SEVENWIRE) { - fec->phy_init = pdata->phy_init; fec->miibus.read = fec_miibus_read; fec->miibus.write = fec_miibus_write; - fec->phy_addr = pdata->phy_addr; - switch (pdata->xcv_type) { + switch (fec->xcv_type) { case RMII: fec->interface = PHY_INTERFACE_MODE_RMII; break; @@ -720,13 +728,45 @@ fec_halt(&fec->edev); } +static __maybe_unused struct of_device_id imx_fec_dt_ids[] = { + { + .compatible = "fsl,imx27-fec", + .data = FEC_TYPE_IMX27, + }, { + .compatible = "fsl,imx28-fec", + .data = FEC_TYPE_IMX28, + }, { + .compatible = "fsl,imx6q-fec", + .data = FEC_TYPE_IMX6, + }, { + /* sentinel */ + } +}; + +static struct platform_device_id imx_fec_ids[] = { + { + .name = "imx27-fec", + .driver_data = (unsigned long)FEC_TYPE_IMX27, + }, { + .name = "imx28-fec", + .driver_data = (unsigned long)FEC_TYPE_IMX28, + }, { + .name = "imx6-fec", + .driver_data = (unsigned long)FEC_TYPE_IMX6, + }, { + /* sentinel */ + }, +}; + /** * Driver description for registering */ static struct driver_d fec_driver = { - .name = "fec_imx", - .probe = fec_probe, + .name = "fec_imx", + .probe = fec_probe, .remove = fec_remove, + .of_compatible = DRV_OF_COMPAT(imx_fec_dt_ids), + .id_table = imx_fec_ids, }; static int fec_register(void) diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h index d147dca..1eb1eba 100644 --- a/drivers/net/fec_imx.h +++ b/drivers/net/fec_imx.h @@ -122,6 +122,12 @@ uint32_t data_pointer; /**< payload's buffer address */ }; +enum fec_type { + FEC_TYPE_IMX27, + FEC_TYPE_IMX28, + FEC_TYPE_IMX6, +}; + /** * @brief i.MX27-FEC private structure */ @@ -139,8 +145,24 @@ struct mii_bus miibus; void (*phy_init)(struct phy_device *dev); struct clk *clk; + enum fec_type type; }; +static inline int fec_is_imx27(struct fec_priv *priv) +{ + return priv->type == FEC_TYPE_IMX27; +} + +static inline int fec_is_imx28(struct fec_priv *priv) +{ + return priv->type == FEC_TYPE_IMX28; +} + +static inline int fec_is_imx6(struct fec_priv *priv) +{ + return priv->type == FEC_TYPE_IMX6; +} + /** * @brief Numbers of buffer descriptors for receiving * diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c index a711940..694eac2 100644 --- a/drivers/serial/serial_imx.c +++ b/drivers/serial/serial_imx.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -38,20 +37,6 @@ #define UBIR 0xa4 /* BRM Incremental Register */ #define UBMR 0xa8 /* BRM Modulator Register */ #define UBRC 0xac /* Baud Rate Count Register */ -#ifdef CONFIG_ARCH_IMX1 -#define BIPR1 0xb0 /* Incremental Preset Register 1 */ -#define BIPR2 0xb4 /* Incremental Preset Register 2 */ -#define BIPR3 0xb8 /* Incremental Preset Register 3 */ -#define BIPR4 0xbc /* Incremental Preset Register 4 */ -#define BMPR1 0xc0 /* BRM Modulator Register 1 */ -#define BMPR2 0xc4 /* BRM Modulator Register 2 */ -#define BMPR3 0xc8 /* BRM Modulator Register 3 */ -#define BMPR4 0xcc /* BRM Modulator Register 4 */ -#define UTS 0xd0 /* UART Test Register */ -#else -#define ONEMS 0xb0 /* One Millisecond register */ -#define UTS 0xb4 /* UART Test Register */ -#endif /* UART Control Register Bit Fields.*/ #define URXD_CHARRDY (1<<15) @@ -148,23 +133,29 @@ /* * create default values for different platforms */ -#ifdef CONFIG_ARCH_IMX1 -# define UCR1_VAL (UCR1_UARTCLKEN) -# define UCR3_VAL 0 -# define UCR4_VAL (UCR4_CTSTL_32 | UCR4_REF16) -#endif -#if defined CONFIG_ARCH_IMX21 || defined CONFIG_ARCH_IMX27 -# define UCR1_VAL (UCR1_UARTCLKEN) -# define UCR3_VAL (0x700 | UCR3_RXDMUXSEL) -# define UCR4_VAL UCR4_CTSTL_32 -#endif -#if defined CONFIG_ARCH_IMX31 || defined CONFIG_ARCH_IMX35 || \ - defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX51 || \ - defined CONFIG_ARCH_IMX53 || defined CONFIG_ARCH_IMX6 -# define UCR1_VAL (0) -# define UCR3_VAL (0x700 | UCR3_RXDMUXSEL) -# define UCR4_VAL UCR4_CTSTL_32 -#endif +struct imx_serial_devtype_data { + u32 ucr1_val; + u32 ucr3_val; + u32 ucr4_val; + u32 uts; + u32 onems; +}; + +struct imx_serial_devtype_data imx1_data = { + .ucr1_val = UCR1_UARTCLKEN, + .ucr3_val = 0, + .ucr4_val = UCR4_CTSTL_32 | UCR4_REF16, + .uts = 0xd0, + .onems = 0, +}; + +struct imx_serial_devtype_data imx21_data = { + .ucr1_val = 0, + .ucr3_val = 0x700 | UCR3_RXDMUXSEL, + .ucr4_val = UCR4_CTSTL_32, + .uts = 0xb4, + .onems = 0xb0, +}; struct imx_serial_priv { struct console_device cdev; @@ -172,6 +163,7 @@ struct notifier_block notify; void __iomem *regs; struct clk *clk; + struct imx_serial_devtype_data *devtype; }; static int imx_serial_reffreq(struct imx_serial_priv *priv) @@ -196,23 +188,23 @@ void __iomem *regs = priv->regs; uint32_t val; - writel(UCR1_VAL, regs + UCR1); + writel(priv->devtype->ucr1_val, regs + UCR1); writel(UCR2_WS | UCR2_IRTS, regs + UCR2); - writel(UCR3_VAL, regs + UCR3); - writel(UCR4_VAL, regs + UCR4); + writel(priv->devtype->ucr3_val, regs + UCR3); + writel(priv->devtype->ucr4_val, regs + UCR4); writel(0x0000002B, regs + UESC); writel(0, regs + UTIM); writel(0, regs + UBIR); writel(0, regs + UBMR); - writel(0, regs + UTS); + writel(0, regs + priv->devtype->uts); /* Configure FIFOs */ writel(0xa81, regs + UFCR); -#ifdef ONEMS - writel(imx_serial_reffreq(priv) / 1000, regs + ONEMS); -#endif + + if (priv->devtype->onems) + writel(imx_serial_reffreq(priv) / 1000, regs + priv->devtype->onems); /* Enable FIFOs */ val = readl(regs + UCR2); @@ -240,7 +232,7 @@ struct imx_serial_priv, cdev); /* Wait for Tx FIFO not full */ - while (readl(priv->regs + UTS) & UTS_TXFULL); + while (readl(priv->regs + priv->devtype->uts) & UTS_TXFULL); writel(c, priv->regs + URTX0); } @@ -251,7 +243,7 @@ struct imx_serial_priv, cdev); /* If receive fifo is empty, return false */ - if (readl(priv->regs + UTS) & UTS_RXEMPTY) + if (readl(priv->regs + priv->devtype->uts) & UTS_RXEMPTY) return 0; return 1; } @@ -262,7 +254,7 @@ struct imx_serial_priv, cdev); unsigned char ch; - while (readl(priv->regs + UTS) & UTS_RXEMPTY); + while (readl(priv->regs + priv->devtype->uts) & UTS_RXEMPTY); ch = readl(priv->regs + URXD0); @@ -318,9 +310,15 @@ struct console_device *cdev; struct imx_serial_priv *priv; uint32_t val; + struct imx_serial_devtype_data *devtype; int ret; + ret = dev_get_drvdata(dev, (unsigned long *)&devtype); + if (ret) + return ret; + priv = xzalloc(sizeof(*priv)); + priv->devtype = devtype; cdev = &priv->cdev; dev->priv = priv; @@ -371,20 +369,33 @@ static __maybe_unused struct of_device_id imx_serial_dt_ids[] = { { .compatible = "fsl,imx1-uart", - .data = 0, + .data = (unsigned long)&imx1_data, }, { .compatible = "fsl,imx21-uart", - .data = 1, + .data = (unsigned long)&imx21_data, }, { /* sentinel */ } }; +static struct platform_device_id imx_serial_ids[] = { + { + .name = "imx1-uart", + .driver_data = (unsigned long)&imx1_data, + }, { + .name = "imx21-uart", + .driver_data = (unsigned long)&imx21_data, + }, { + /* sentinel */ + }, +}; + static struct driver_d imx_serial_driver = { .name = "imx_serial", .probe = imx_serial_probe, .remove = imx_serial_remove, .of_compatible = DRV_OF_COMPAT(imx_serial_dt_ids), + .id_table = imx_serial_ids, }; static int imx_serial_init(void) diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c index 3f8fd33..a29920d 100644 --- a/drivers/video/imx-ipu-fb.c +++ b/drivers/video/imx-ipu-fb.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include @@ -742,9 +742,9 @@ /* ipu_idmac.c::ipu_probe() */ /* Start the clock */ - reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); reg |= (3 << 18); - writel(reg, IMX_CCM_BASE + CCM_CGR1); + writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); /* ipu_idmac.c::ipu_idmac_init() */ diff --git a/drivers/video/imx.c b/drivers/video/imx.c index 9406b36..39ecf6a 100644 --- a/drivers/video/imx.c +++ b/drivers/video/imx.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #define LCDC_SSA 0x00 @@ -252,19 +251,9 @@ struct imxfb_info *fbi = info->priv; writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR); -#ifdef CONFIG_ARCH_IMX21 - PCCR0 |= PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN; -#endif -#ifdef CONFIG_ARCH_IMX27 - PCCR0 |= PCCR0_LCDC_EN; - PCCR1 |= PCCR1_HCLK_LCDC; -#endif -#ifdef CONFIG_ARCH_IMX25 - writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 24) | (1 << 7), - IMX_CCM_BASE + CCM_CGCR0); - writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 29), - IMX_CCM_BASE + CCM_CGCR1); -#endif + + clk_enable(fbi->clk); + if (fbi->enable) fbi->enable(1); } @@ -277,19 +266,8 @@ fbi->enable(0); writel(0, fbi->regs + LCDC_RMCR); -#ifdef CONFIG_ARCH_IMX21 - PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN); -#endif -#ifdef CONFIG_ARCH_IMX27 - PCCR0 &= ~PCCR0_LCDC_EN; - PCCR1 &= ~PCCR1_HCLK_LCDC; -#endif -#ifdef CONFIG_ARCH_IMX25 - writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)), - IMX_CCM_BASE + CCM_CGCR0); - writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29), - IMX_CCM_BASE + CCM_CGCR1); -#endif + + clk_disable(fbi->clk); } /* @@ -541,19 +519,6 @@ if (!pdata) return -ENODEV; -#ifdef CONFIG_ARCH_IMX21 - PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN); -#endif -#ifdef CONFIG_ARCH_IMX27 - PCCR0 &= ~PCCR0_LCDC_EN; - PCCR1 &= ~PCCR1_HCLK_LCDC; -#endif -#ifdef CONFIG_ARCH_IMX25 - writel(readl(IMX_CCM_BASE + CCM_CGCR0) & ~((1 << 24) | (1 << 7)), - IMX_CCM_BASE + CCM_CGCR0); - writel(readl(IMX_CCM_BASE + CCM_CGCR1) & ~(1 << 29), - IMX_CCM_BASE + CCM_CGCR1); -#endif if (!pdata->num_modes) { dev_err(dev, "no modes. bailing out\n"); return -EINVAL; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8fdc7a5..ba33617 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -1,3 +1,7 @@ + +config WATCHDOG_IMX_RESET_SOURCE + bool + menuconfig WATCHDOG bool "Watchdog support " help @@ -12,4 +16,9 @@ help Add support for watchdog management for the i.MX28 SoC. +config WATCHDOG_IMX + bool "i.MX watchdog" + depends on ARCH_IMX + help + Add support for watchdog found on Freescale i.MX SoCs. endif diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index b29103b..f522b88 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_WATCHDOG) += wd_core.o obj-$(CONFIG_WATCHDOG_MXS28) += im28wd.o +obj-$(CONFIG_WATCHDOG_IMX_RESET_SOURCE) += imxwd.o diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c new file mode 100644 index 0000000..c422f98 --- /dev/null +++ b/drivers/watchdog/imxwd.c @@ -0,0 +1,235 @@ +/* + * (c) 2012 Sascha Hauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +struct imx_wd { + struct watchdog wd; + void __iomem *base; + struct device_d *dev; + int (*set_timeout)(struct imx_wd *, unsigned); +}; + +#define to_imx_wd(h) container_of(h, struct imx_wd, wd) + +#define IMX1_WDOG_WCR 0x00 /* Watchdog Control Register */ +#define IMX1_WDOG_WSR 0x04 /* Watchdog Service Register */ +#define IMX1_WDOG_WSTR 0x08 /* Watchdog Status Register */ +#define IMX1_WDOG_WCR_WDE (1 << 0) +#define IMX1_WDOG_WCR_WHALT (1 << 15) + +#define IMX21_WDOG_WCR 0x00 /* Watchdog Control Register */ +#define IMX21_WDOG_WSR 0x02 /* Watchdog Service Register */ +#define IMX21_WDOG_WSTR 0x04 /* Watchdog Status Register */ +#define IMX21_WDOG_WCR_WDE (1 << 2) +#define IMX21_WDOG_WCR_SRS (1 << 4) +#define IMX21_WDOG_WCR_WDA (1 << 5) + +/* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */ +#define WSTR_WARMSTART (1 << 0) +/* valid for i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 */ +#define WSTR_WDOG (1 << 1) +/* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */ +#define WSTR_HARDRESET (1 << 3) +/* valid for i.MX27, i.MX31, always '0' on i.MX25, i.MX35, i.MX51 */ +#define WSTR_COLDSTART (1 << 4) + +static int imx1_watchdog_set_timeout(struct imx_wd *priv, int timeout) +{ + u16 val; + + dev_dbg(priv->dev, "%s: %d\n", __func__, timeout); + + if (timeout > 64) + return -EINVAL; + + if (!timeout) { + writew(IMX1_WDOG_WCR_WHALT, priv->base + IMX1_WDOG_WCR); + return 0; + } + + if (timeout > 0) + val = (timeout * 2 - 1) << 8; + else + val = 0; + + writew(val, priv->base + IMX1_WDOG_WCR); + writew(IMX1_WDOG_WCR_WDE | val, priv->base + IMX1_WDOG_WCR); + + /* Write Service Sequence */ + writew(0x5555, priv->base + IMX1_WDOG_WSR); + writew(0xaaaa, priv->base + IMX1_WDOG_WSR); + + return 0; +} + +static int imx21_watchdog_set_timeout(struct imx_wd *priv, int timeout) +{ + u16 val; + + dev_dbg(priv->dev, "%s: %d\n", __func__, timeout); + + if (!timeout || timeout > 128) + return -EINVAL; + + if (timeout > 0) + val = ((timeout * 2 - 1) << 8) | IMX21_WDOG_WCR_SRS | + IMX21_WDOG_WCR_WDA; + else + val = 0; + + writew(val, priv->base + IMX21_WDOG_WCR); + writew(IMX21_WDOG_WCR_WDE | val, priv->base + IMX21_WDOG_WCR); + + /* Write Service Sequence */ + writew(0x5555, priv->base + IMX21_WDOG_WSR); + writew(0xaaaa, priv->base + IMX21_WDOG_WSR); + + return 0; +} + +static int imx_watchdog_set_timeout(struct watchdog *wd, unsigned timeout) +{ + struct imx_wd *priv = (struct imx_wd *)to_imx_wd(wd); + + return priv->set_timeout(priv, timeout); +} + +static struct imx_wd *reset_wd; + +void __noreturn reset_cpu(unsigned long addr) +{ + if (reset_wd) + reset_wd->set_timeout(reset_wd, -1); + + mdelay(1000); + + hang(); +} + +static void imx_watchdog_detect_reset_source(struct imx_wd *priv) +{ + u16 val = readw(priv->base + IMX21_WDOG_WSTR); + + if (val & WSTR_COLDSTART) { + set_reset_source(RESET_POR); + return; + } + + if (val & (WSTR_HARDRESET | WSTR_WARMSTART)) { + set_reset_source(RESET_RST); + return; + } + + if (val & WSTR_WDOG) { + set_reset_source(RESET_WDG); + return; + } + + /* else keep the default 'unknown' state */ +} + +static int imx_wd_probe(struct device_d *dev) +{ + struct imx_wd *priv; + void *fn; + int ret; + + ret = dev_get_drvdata(dev, (unsigned long *)&fn); + if (ret) + return ret; + + priv = xzalloc(sizeof(struct imx_wd)); + priv->base = dev_request_mem_region(dev, 0); + priv->set_timeout = fn; + priv->wd.set_timeout = imx_watchdog_set_timeout; + priv->dev = dev; + + if (!reset_wd) + reset_wd = priv; + + if (IS_ENABLED(CONFIG_WATCHDOG_IMX)) { + ret = watchdog_register(&priv->wd); + if (ret) + goto on_error; + } + + if (fn != imx1_watchdog_set_timeout) + imx_watchdog_detect_reset_source(priv); + + dev->priv = priv; + + return 0; + +on_error: + if (reset_wd && reset_wd != priv) + free(priv); + return ret; +} + +static void imx_wd_remove(struct device_d *dev) +{ + struct imx_wd *priv = dev->priv; + + if (IS_ENABLED(CONFIG_WATCHDOG_IMX)) + watchdog_deregister(&priv->wd); + + if (reset_wd && reset_wd != priv) + free(priv); +} + +static __maybe_unused struct of_device_id imx_wdt_dt_ids[] = { + { + .compatible = "fsl,imx1-wdt", + .data = (unsigned long)&imx1_watchdog_set_timeout, + }, { + .compatible = "fsl,imx21-wdt", + .data = (unsigned long)&imx21_watchdog_set_timeout, + }, { + /* sentinel */ + } +}; + +static struct platform_device_id imx_wdt_ids[] = { + { + .name = "imx1-wdt", + .driver_data = (unsigned long)&imx1_watchdog_set_timeout, + }, { + .name = "imx21-wdt", + .driver_data = (unsigned long)&imx21_watchdog_set_timeout, + }, { + /* sentinel */ + }, +}; + +static struct driver_d imx_wd_driver = { + .name = "imx-watchdog", + .probe = imx_wd_probe, + .remove = imx_wd_remove, + .of_compatible = DRV_OF_COMPAT(imx_wdt_dt_ids), + .id_table = imx_wdt_ids, +}; + +static int imx_wd_init(void) +{ + return platform_driver_register(&imx_wd_driver); +} + +device_initcall(imx_wd_init); diff --git a/include/bbu.h b/include/bbu.h new file mode 100644 index 0000000..095eebc --- /dev/null +++ b/include/bbu.h @@ -0,0 +1,49 @@ +#ifndef __INCLUDE_BBU_H +#define __INCLUDE_BBU_H + +struct bbu_data { +#define BBU_FLAG_FORCE (1 << 0) +#define BBU_FLAG_YES (1 << 1) + unsigned long flags; + int force; + void *image; + const char *imagefile; + const char *devicefile; + size_t len; + const char *handler_name; +}; + +struct bbu_handler { + int (*handler)(struct bbu_handler *, struct bbu_data *); + const char *name; + struct list_head list; +#define BBU_HANDLER_FLAG_DEFAULT (1 << 0) + unsigned long flags; + + /* default device file, can be overwritten on the command line */ + const char *devicefile; +}; + +int bbu_force(struct bbu_data *, const char *fmt, ...) + __attribute__ ((format(__printf__, 2, 3))); + +int bbu_confirm(struct bbu_data *); + +int barebox_update(struct bbu_data *); + +void bbu_handlers_list(void); + +#ifdef CONFIG_BAREBOX_UPDATE + +int bbu_register_handler(struct bbu_handler *); + +#else + +static inline int bbu_register_handler(struct bbu_handler *unused) +{ + return -EINVAL; +} + +#endif + +#endif /* __INCLUDE_BBU_H */ diff --git a/include/linux/clk.h b/include/linux/clk.h index e9031dd..00588bf 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -188,6 +188,8 @@ const char *parent, unsigned int mult, unsigned int div); struct clk *clk_mux(const char *name, void __iomem *reg, u8 shift, u8 width, const char **parents, u8 num_parents); +struct clk *clk_gate(const char *name, const char *parent, void __iomem *reg, + u8 shift); int clk_register(struct clk *clk); diff --git a/include/reset_source.h b/include/reset_source.h index 6734fbde..75e7ba8 100644 --- a/include/reset_source.h +++ b/include/reset_source.h @@ -22,6 +22,12 @@ RESET_JTAG, /* JTAG reset */ }; +#ifdef CONFIG_RESET_SOURCE void set_reset_source(enum reset_src_type); +#else +static inline void set_reset_source(enum reset_src_type unused) +{ +} +#endif #endif /* __INCLUDE_RESET_SOURCE_H */