diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6ef2bf7..75761b5 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -80,6 +80,7 @@ machine-$(CONFIG_MACH_MIPS_ATH79) := ath79 board-$(CONFIG_BOARD_TPLINK_MR3020) := tplink-mr3020 +board-$(CONFIG_BOARD_BLACK_SWIFT) := black-swift machine-$(CONFIG_MACH_MIPS_BCM47XX) := bcm47xx board-$(CONFIG_BOARD_DLINK_DIR320) := dlink-dir-320 diff --git a/arch/mips/boards/black-swift/Makefile b/arch/mips/boards/black-swift/Makefile new file mode 100644 index 0000000..dcfc293 --- /dev/null +++ b/arch/mips/boards/black-swift/Makefile @@ -0,0 +1 @@ +obj-y += board.o diff --git a/arch/mips/boards/black-swift/board.c b/arch/mips/boards/black-swift/board.c new file mode 100644 index 0000000..2e2ed20 --- /dev/null +++ b/arch/mips/boards/black-swift/board.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Antony Pavlov + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +static int model_hostname_init(void) +{ + barebox_set_hostname("black-swift"); + + return 0; +} +postcore_initcall(model_hostname_init); diff --git a/arch/mips/boards/black-swift/include/board/board_pbl_start.h b/arch/mips/boards/black-swift/include/board/board_pbl_start.h new file mode 100644 index 0000000..f78e0d9 --- /dev/null +++ b/arch/mips/boards/black-swift/include/board/board_pbl_start.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013, 2015 Antony Pavlov + * Copyright (C) 2013 Oleksij Rempel + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + + .macro board_pbl_start + .set push + .set noreorder + + mips_barebox_10h + + mips_disable_interrupts + + pbl_ar9331_pll + pbl_ar9331_ddr2_config + + pbl_ar9331_uart_enable + debug_ll_ar9331_init + mips_nmon + + copy_to_link_location pbl_start + + .set pop + .endm diff --git a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h index 944a510..08204fe 100644 --- a/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h +++ b/arch/mips/boards/tplink-mr3020/include/board/board_pbl_start.h @@ -17,6 +17,7 @@ */ #include +#include #include .macro board_pbl_start @@ -27,6 +28,11 @@ mips_disable_interrupts + pbl_ar9331_pll + pbl_ar9331_ddr1_config + + pbl_ar9331_uart_enable + debug_ll_ar9331_init mips_nmon copy_to_link_location pbl_start diff --git a/arch/mips/configs/black-swift_defconfig b/arch/mips/configs/black-swift_defconfig new file mode 100644 index 0000000..7444968 --- /dev/null +++ b/arch/mips/configs/black-swift_defconfig @@ -0,0 +1,46 @@ +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="black-swift" +CONFIG_MACH_MIPS_ATH79=y +CONFIG_BOARD_BLACK_SWIFT=y +CONFIG_NMON=y +CONFIG_NMON_USER_START=y +CONFIG_NMON_1S_DELAY=0x100000 +CONFIG_NMON_USER_START_DELAY=0x5 +CONFIG_NMON_HELP=y +CONFIG_PBL_IMAGE=y +CONFIG_IMAGE_COMPRESSION_XZKERN=y +CONFIG_MALLOC_TLSF=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_IMD=y +CONFIG_PARTITION=y +CONFIG_DEBUG_LL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_BOOTM is not set +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_LET=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_SPI=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_OFDEVICE=y +CONFIG_DRIVER_SERIAL_AR933X=y +CONFIG_DRIVER_SPI_ATH79=y +CONFIG_MTD=y +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_MTD_M25P80=y +CONFIG_DIGEST_SHA224_GENERIC=y +CONFIG_DIGEST_SHA256_GENERIC=y diff --git a/arch/mips/configs/tplink-mr3020_defconfig b/arch/mips/configs/tplink-mr3020_defconfig index b675993..f2ba2da 100644 --- a/arch/mips/configs/tplink-mr3020_defconfig +++ b/arch/mips/configs/tplink-mr3020_defconfig @@ -1,6 +1,9 @@ CONFIG_BUILTIN_DTB=y CONFIG_BUILTIN_DTB_NAME="tplink-mr3020" CONFIG_MACH_MIPS_ATH79=y +CONFIG_PBL_IMAGE=y +CONFIG_IMAGE_COMPRESSION_XZKERN=y +CONFIG_MALLOC_TLSF=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_LONGHELP=y diff --git a/arch/mips/dts/black-swift.dts b/arch/mips/dts/black-swift.dts new file mode 100644 index 0000000..270374d --- /dev/null +++ b/arch/mips/dts/black-swift.dts @@ -0,0 +1,34 @@ +/dts-v1/; + +#include "ar9331.dtsi" + +/ { + model = "Black Swift"; + compatible = "smartlx,black-swift"; + + memory { + reg = <0x00000000 0x4000000>; + }; + + aliases { + spiflash = &spiflash; + }; +}; + +&serial0 { + status = "okay"; +}; + +&spi { + num-chipselects = <1>; + status = "okay"; + + /* Winbond W25Q128FV SPI flash */ + spiflash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80"; + spi-max-frequency = <104000000>; + reg = <0>; + }; +}; diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h index 1d9d6ab..681b40a 100644 --- a/arch/mips/include/asm/pbl_macros.h +++ b/arch/mips/include/asm/pbl_macros.h @@ -28,6 +28,38 @@ #include #include + .macro pbl_reg_writel val addr + .set push + .set noreorder + li t9, \addr + li t8, \val + sw t8, 0(t9) + .set pop + .endm + + .macro pbl_reg_set val addr + .set push + .set noreorder + li t9, \addr + li t8, \val + lw t7, 0(t9) + or t7, t8 + sw t7, 0(t9) + .set pop + .endm + + .macro pbl_reg_clr clr addr + .set push + .set noreorder + li t9, \addr + li t8, \clr + lw t7, 0(t9) + not t8, t8 + and t7, t8 + sw t7, 0(t9) + .set pop + .endm + .macro pbl_sleep reg count .set push .set noreorder diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c index 01b8665..0a9dd0e 100644 --- a/arch/mips/lib/c-r4k.c +++ b/arch/mips/lib/c-r4k.c @@ -91,7 +91,38 @@ } } +#define CONFIG_M (1 << 31) +#define CONFIG2_SS_OFFSET 8 +#define CONFIG2_SL_OFFSET 4 +#define CONFIG2_SA_OFFSET 0 +static void probe_scache(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config2, config1, config = read_c0_config(); + unsigned int ss, sl, sa; + + if ((config & CONFIG_M) == 0) + goto noscache; + config1 = read_c0_config1(); + if ((config1 & CONFIG_M) == 0) + goto noscache; + config2 = read_c0_config2(); + ss = 0xf & (config2 >> CONFIG2_SS_OFFSET); + sl = 0xf & (config2 >> CONFIG2_SL_OFFSET); + sa = 0xf & (config2 >> CONFIG2_SA_OFFSET); + if (sl == 0) + goto noscache; + c->scache.linesz = 1 << (sl + 1); + c->scache.sets = 64 << ss; + c->scache.ways = 1 + sa; + c->scache.waysize = c->scache.linesz * c->scache.sets; + return; +noscache: + c->scache.flags = MIPS_CACHE_NOT_PRESENT; +} + void r4k_cache_init(void) { probe_pcache(); + probe_scache(); } diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c index 4622bcd..71dbaf6 100644 --- a/arch/mips/lib/cpu-probe.c +++ b/arch/mips/lib/cpu-probe.c @@ -75,8 +75,6 @@ c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; - c->scache.flags = MIPS_CACHE_NOT_PRESENT; - ok = decode_config0(c); /* Read Config registers. */ BUG_ON(!ok); /* Arch spec violation! */ } diff --git a/arch/mips/lib/cpuinfo.c b/arch/mips/lib/cpuinfo.c index 1b17169..fb02a4d 100644 --- a/arch/mips/lib/cpuinfo.c +++ b/arch/mips/lib/cpuinfo.c @@ -28,7 +28,7 @@ static int do_cpuinfo(int argc, char *argv[]) { - unsigned int icache_size, dcache_size; + unsigned int icache_size, dcache_size, scache_size; struct cpuinfo_mips *c = ¤t_cpu_data; printk(KERN_INFO "CPU revision is: %08x (%s)\n", @@ -48,6 +48,15 @@ (c->dcache.flags & MIPS_CACHE_ALIASES) ? "cache aliases" : "no aliases", c->dcache.linesz); + if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) + return 0; + scache_size = c->scache.sets * c->scache.ways * c->scache.linesz; + printk("Secondary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", + scache_size >> 10, way_string[c->scache.ways], + (c->scache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", + (c->scache.flags & MIPS_CACHE_ALIASES) ? + "cache aliases" : "no aliases", + c->scache.linesz); return 0; } diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index f730b37..9b8e394 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -13,6 +13,12 @@ select HAVE_IMAGE_COMPRESSION select HAS_NMON +config BOARD_BLACK_SWIFT + bool "Black Swift" + select HAVE_PBL_IMAGE + select HAVE_IMAGE_COMPRESSION + select HAS_NMON + endchoice endif diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index b82a8c3..4cbe94a 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -23,6 +23,8 @@ #define AR71XX_APB_BASE 0x18000000 +#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) #define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) @@ -34,6 +36,24 @@ #define AR933X_UART_SIZE 0x14 /* + * DDR_CTRL block + */ +#define AR933X_DDR_CONFIG 0x00 +#define AR933X_DDR_CONFIG2 0x04 +#define AR933X_DDR_MODE 0x08 +#define AR933X_DDR_EXT_MODE 0x0c +#define AR933X_DDR_CTRL 0x10 +#define AR933X_DDR_REFRESH 0x14 +#define AR933X_DDR_RD_DATA 0x18 +#define AR933X_DDR_TAP_CTRL0 0x1c +#define AR933X_DDR_TAP_CTRL1 0x20 +#define AR933X_DDR_TAP_CTRL1 0x20 + +#define AR933X_DDR_DDR_DDR2_CONFIG 0x8c +#define AR933X_DDR_DDR_EMR2 0x90 +#define AR933X_DDR_DDR_EMR3 0x94 + +/* * GPIO block */ #define AR71XX_GPIO_REG_OE 0x00 @@ -47,6 +67,9 @@ #define AR71XX_GPIO_REG_INT_PENDING 0x20 #define AR71XX_GPIO_REG_INT_ENABLE 0x24 #define AR71XX_GPIO_REG_FUNC 0x28 +/* Warning! GPIO_FUNC[15] must be written with 1 */ +#define AR933X_GPIO_FUNC_RSRV15 BIT(15) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) /* * PLL block @@ -63,6 +86,7 @@ #define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f #define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 #define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 +#define AR933X_PLL_CPU_CONFIG_PLLPWD BIT(30) #define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2) #define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5 diff --git a/arch/mips/mach-ath79/include/mach/debug_ll.h b/arch/mips/mach-ath79/include/mach/debug_ll.h index d3813af..e0c3f79 100644 --- a/arch/mips/mach-ath79/include/mach/debug_ll.h +++ b/arch/mips/mach-ath79/include/mach/debug_ll.h @@ -63,6 +63,35 @@ * Macros for use in assembly language code */ +#define AR933X_UART_CS_REG 0x04 +#define UART_CS_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CS_REG) +#define AR933X_UART_CS_IF_MODE_S 2 +#define AR933X_UART_CS_IF_MODE_DCE 2 +#define AR933X_UART_CS_TX_READY_ORIDE BIT(7) +#define AR933X_UART_CS_RX_READY_ORIDE BIT(8) + +/* + * simple uart clock setup + * from u-boot_mod/u-boot/cpu/mips/ar7240/hornet_serial.c + */ +#define BAUD_CLOCK 25000000 +#define CLOCK_SCALE ((BAUD_CLOCK / (16 * CONFIG_BAUDRATE)) - 1) +#define CLOCK_STEP 0x2000 + +#define AR933X_UART_CLOCK_REG 0x08 +#define CLOCK_REG ((KSEG1 | AR933X_UART_BASE) | AR933X_UART_CLOCK_REG) + +.macro debug_ll_ar9331_init +#ifdef CONFIG_DEBUG_LL + + pbl_reg_writel ((AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S) \ + | AR933X_UART_CS_TX_READY_ORIDE \ + | AR933X_UART_CS_RX_READY_ORIDE), UART_CS_REG + pbl_reg_writel ((CLOCK_SCALE << 16) | CLOCK_STEP), CLOCK_REG + +#endif /* CONFIG_DEBUG_LL */ +.endm + /* * output a character in a0 */ diff --git a/arch/mips/mach-ath79/include/mach/pbl_macros.h b/arch/mips/mach-ath79/include/mach/pbl_macros.h new file mode 100644 index 0000000..c00dd28 --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/pbl_macros.h @@ -0,0 +1,182 @@ +#ifndef __ASM_MACH_ATH79_PBL_MACROS_H +#define __ASM_MACH_ATH79_PBL_MACROS_H + +#include +#include +#include + +#define PLL_BASE (KSEG1 | AR71XX_PLL_BASE) +#define PLL_CPU_CONFIG_REG (PLL_BASE | AR933X_PLL_CPU_CONFIG_REG) +#define PLL_CPU_CONFIG2_REG (PLL_BASE | AR933X_PLL_CPU_CONFIG2_REG) +#define PLL_CLOCK_CTRL_REG (PLL_BASE | AR933X_PLL_CLOCK_CTRL_REG) + +#define DEF_25MHZ_PLL_CLOCK_CTRL \ + ((2 - 1) << AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT \ + | (1 - 1) << AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT \ + | (1 - 1) << AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) +#define DEF_25MHZ_SETTLE_TIME (34000 / 40) +#define DEF_25MHZ_PLL_CONFIG ( 1 << AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT \ + | 1 << AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT \ + | 32 << AR933X_PLL_CPU_CONFIG_NINT_SHIFT) + +.macro pbl_ar9331_pll + .set push + .set noreorder + + /* Most devices have 25 MHz Ref clock. */ + pbl_reg_writel (DEF_25MHZ_PLL_CLOCK_CTRL | AR933X_PLL_CLOCK_CTRL_BYPASS), \ + PLL_CLOCK_CTRL_REG + pbl_reg_writel DEF_25MHZ_SETTLE_TIME, PLL_CPU_CONFIG2_REG + pbl_reg_writel (DEF_25MHZ_PLL_CONFIG | AR933X_PLL_CPU_CONFIG_PLLPWD), \ + PLL_CPU_CONFIG_REG + + /* power on CPU PLL */ + pbl_reg_clr AR933X_PLL_CPU_CONFIG_PLLPWD, PLL_CPU_CONFIG_REG + /* disable PLL bypass */ + pbl_reg_clr AR933X_PLL_CLOCK_CTRL_BYPASS, PLL_CLOCK_CTRL_REG + + pbl_sleep t2, 40 + + .set pop +.endm + +#define DDR_BASE (KSEG1 | AR71XX_DDR_CTRL_BASE) +#define DDR_CONFIG (DDR_BASE | AR933X_DDR_CONFIG) +#define DDR_CONFIG2 (DDR_BASE | AR933X_DDR_CONFIG2) +#define DDR_MODE (DDR_BASE | AR933X_DDR_MODE) +#define DDR_EXT_MODE (DDR_BASE | AR933X_DDR_EXT_MODE) + +#define DDR_CTRL (DDR_BASE | AR933X_DDR_CTRL) +/* Forces an EMR3S (Extended Mode Register 3 Set) update cycle */ +#define DDR_CTRL_EMR3 BIT(5) +/* Forces an EMR2S (Extended Mode Register 2 Set) update cycle */ +#define DDR_CTRL_EMR2 BIT(4) +#define DDR_CTRL_PREA BIT(3) /* Forces a PRECHARGE ALL cycle */ +#define DDR_CTRL_REF BIT(2) /* Forces an AUTO REFRESH cycle */ +/* Forces an EMRS (Extended Mode Register 2 Set) update cycle */ +#define DDR_CTRL_EMRS BIT(1) +/* Forces a MRS (Mode Register Set) update cycle */ +#define DDR_CTRL_MRS BIT(0) + +#define DDR_REFRESH (DDR_BASE | AR933X_DDR_REFRESH) +#define DDR_RD_DATA (DDR_BASE | AR933X_DDR_RD_DATA) +#define DDR_TAP_CTRL0 (DDR_BASE | AR933X_DDR_TAP_CTRL0) +#define DDR_TAP_CTRL1 (DDR_BASE | AR933X_DDR_TAP_CTRL1) + +#define DDR_DDR2_CONFIG (DDR_BASE | AR933X_DDR_DDR_DDR2_CONFIG) +#define DDR_EMR2 (DDR_BASE | AR933X_DDR_DDR_EMR2) +#define DDR_EMR3 (DDR_BASE | AR933X_DDR_DDR_EMR3) + +.macro pbl_ar9331_ddr1_config + .set push + .set noreorder + + pbl_reg_writel 0x7fbc8cd0, DDR_CONFIG + pbl_reg_writel 0x9dd0e6a8, DDR_CONFIG2 + + pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL + + /* 0x133: on reset Mode Register value */ + pbl_reg_writel 0x133, DDR_MODE + pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL + + /* + * DDR_EXT_MODE[1] = 1: Reduced Drive Strength + * DDR_EXT_MODE[0] = 0: Enable DLL + */ + pbl_reg_writel 0x2, DDR_EXT_MODE + pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL + + pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL + + /* DLL out of reset, CAS Latency 3 */ + pbl_reg_writel 0x33, DDR_MODE + pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL + + /* Refresh control. Bit 14 is enable. Bits<13:0> Refresh time */ + pbl_reg_writel 0x4186, DDR_REFRESH + /* This register is used along with DQ Lane 0; DQ[7:0], DQS_0 */ + pbl_reg_writel 0x8, DDR_TAP_CTRL0 + /* This register is used along with DQ Lane 1; DQ[15:8], DQS_1 */ + pbl_reg_writel 0x9, DDR_TAP_CTRL1 + + /* + * DDR read and capture bit mask. + * Each bit represents a cycle of valid data. + * 0xff: use 16-bit DDR + */ + pbl_reg_writel 0xff, DDR_RD_DATA + + .set pop +.endm + +.macro pbl_ar9331_ddr2_config + .set push + .set noreorder + + pbl_reg_writel 0x7fbc8cd0, DDR_CONFIG + pbl_reg_writel 0x9dd0e6a8, DDR_CONFIG2 + + /* Enable DDR2 */ + pbl_reg_writel 0x00000a59, DDR_DDR2_CONFIG + pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL + + /* Disable High Temperature Self-Refresh Rate */ + pbl_reg_writel 0x00000000, DDR_EMR2 + pbl_reg_writel DDR_CTRL_EMR2, DDR_CTRL + + pbl_reg_writel 0x00000000, DDR_EMR3 + pbl_reg_writel DDR_CTRL_EMR3, DDR_CTRL + + /* Enable DLL */ + pbl_reg_writel 0x00000000, DDR_EXT_MODE + pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL + + /* Reset DLL */ + pbl_reg_writel 0x00000100, DDR_MODE + pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL + + pbl_reg_writel DDR_CTRL_PREA, DDR_CTRL + pbl_reg_writel DDR_CTRL_REF, DDR_CTRL + pbl_reg_writel DDR_CTRL_REF, DDR_CTRL + + /* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */ + pbl_reg_writel 0x00000a33, DDR_MODE + pbl_reg_writel DDR_CTRL_MRS, DDR_CTRL + + /* + * DDR_EXT_MODE[9:7] = 0x7: (OCD Calibration defaults) + * DDR_EXT_MODE[1] = 1: Reduced Drive Strength + * DDR_EXT_MODE[0] = 0: Enable DLL + */ + pbl_reg_writel 0x00000382, DDR_EXT_MODE + pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL + + /* + * DDR_EXT_MODE[9:7] = 0x0: (OCD exit) + * DDR_EXT_MODE[1] = 1: Reduced Drive Strength + * DDR_EXT_MODE[0] = 0: Enable DLL + */ + pbl_reg_writel 0x00000402, DDR_EXT_MODE + pbl_reg_writel DDR_CTRL_EMRS, DDR_CTRL + + /* Refresh control. Bit 14 is enable. Bits <13:0> Refresh time */ + pbl_reg_writel 0x00004186, DDR_REFRESH + /* DQS 0 Tap Control (needs tuning) */ + pbl_reg_writel 0x00000008, DDR_TAP_CTRL0 + /* DQS 1 Tap Control (needs tuning) */ + pbl_reg_writel 0x00000009, DDR_TAP_CTRL1 + /* For 16-bit DDR */ + pbl_reg_writel 0x000000ff, DDR_RD_DATA + + .set pop +.endm + +#define GPIO_FUNC ((KSEG1 | AR71XX_GPIO_BASE) | AR71XX_GPIO_REG_FUNC) + +.macro pbl_ar9331_uart_enable + pbl_reg_set AR933X_GPIO_FUNC_UART_EN \ + | AR933X_GPIO_FUNC_RSRV15, GPIO_FUNC +.endm + +#endif /* __ASM_MACH_ATH79_PBL_MACROS_H */