diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c index 6451e5d..e3fdc64 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c +++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c @@ -67,30 +67,8 @@ BUG_ON(ret); } -/* - * Power-on execution flow of start_nxp_imx8mq_evk() might not be - * obvious for a very first read, so here's, hopefully helpful, - * summary: - * - * 1. MaskROM uploads PBL into OCRAM and that's where this function is - * executed for the first time - * - * 2. DDR is initialized and full i.MX image is loaded to the - * beginning of RAM - * - * 3. start_nxp_imx8mq_evk, now in RAM, is executed again - * - * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it - * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, - * executing start_nxp_imx8mq_evk() the third time - * - * 6. Standard barebox boot flow continues - */ -ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) +static __noreturn noinline void nxp_imx8mq_evk_start(void) { - imx8mq_cpu_lowlevel_init(); - if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); @@ -125,3 +103,33 @@ imx8mq_barebox_entry(__dtb_imx8mq_evk_start); } +/* + * Power-on execution flow of start_nxp_imx8mq_evk() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time + * + * 2. DDR is initialized and full i.MX image is loaded to the + * beginning of RAM + * + * 3. start_nxp_imx8mq_evk, now in RAM, is executed again + * + * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it + * + * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * executing start_nxp_imx8mq_evk() the third time + * + * 6. Standard barebox boot flow continues + */ +ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2) +{ + imx8mq_cpu_lowlevel_init(); + + relocate_to_current_adr(); + setup_c(); + + nxp_imx8mq_evk_start(); +} + diff --git a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c index e42e7a6..4e52b92 100644 --- a/arch/arm/boards/phytec-som-imx8mq/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx8mq/lowlevel.c @@ -61,30 +61,8 @@ BUG_ON(ret); } -/* - * Power-on execution flow of start_phytec_phycore_imx8mq() might not be - * obvious for a very first read, so here's, hopefully helpful, - * summary: - * - * 1. MaskROM uploads PBL into OCRAM and that's where this function is - * executed for the first time - * - * 2. DDR is initialized and full i.MX image is loaded to the - * beginning of RAM - * - * 3. start_phytec_phycore_imx8mq, now in RAM, is executed again - * - * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it - * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, - * executing start_phytec_phycore_imx8mq() the third time - * - * 6. Standard barebox boot flow continues - */ -ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) +static __noreturn noinline void phytec_phycore_imx8mq_start(void) { - imx8mq_cpu_lowlevel_init(); - if (IS_ENABLED(CONFIG_DEBUG_LL)) setup_uart(); @@ -118,3 +96,32 @@ */ imx8mq_barebox_entry(__dtb_imx8mq_phytec_phycore_som_start); } + +/* + * Power-on execution flow of start_phytec_phycore_imx8mq() might not be + * obvious for a very first read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time + * + * 2. DDR is initialized and full i.MX image is loaded to the + * beginning of RAM + * + * 3. start_phytec_phycore_imx8mq, now in RAM, is executed again + * + * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it + * + * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * executing start_phytec_phycore_imx8mq() the third time + * + * 6. Standard barebox boot flow continues + */ +ENTRY_FUNCTION(start_phytec_phycore_imx8mq, r0, r1, r2) +{ + imx8mq_cpu_lowlevel_init(); + relocate_to_current_adr(); + setup_c(); + + phytec_phycore_imx8mq_start(); +} diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c index 33c007e..7eb8b68 100644 --- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c +++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c @@ -120,36 +120,11 @@ extern char __dtb_imx8mq_zii_ultra_rmb3_start[]; extern char __dtb_imx8mq_zii_ultra_zest_start[]; -/* - * Power-on execution flow of start_zii_imx8mq_dev() might not be - * obvious for a very frist read, so here's, hopefully helpful, - * summary: - * - * 1. MaskROM uploads PBL into OCRAM and that's where this function is - * executed for the first time - * - * 2. DDR is initialized and full i.MX image is loaded to the - * beginning of RAM - * - * 3. start_nxp_imx8mq_evk, now in RAM, is executed again - * - * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it - * - * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, - * executing start_nxp_imx8mq_evk() the third time - * - * 6. Standard barebox boot flow continues - */ -ENTRY_FUNCTION(start_zii_imx8mq_dev, r0, r1, r2) +static __noreturn noinline void zii_imx8mq_dev_start(void) { unsigned int system_type; void *fdt; - imx8mq_cpu_lowlevel_init(); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) { /* * We assume that we were just loaded by MaskROM into @@ -202,3 +177,35 @@ */ imx8mq_barebox_entry(fdt); } + +/* + * Power-on execution flow of start_zii_imx8mq_dev() might not be + * obvious for a very frist read, so here's, hopefully helpful, + * summary: + * + * 1. MaskROM uploads PBL into OCRAM and that's where this function is + * executed for the first time + * + * 2. DDR is initialized and full i.MX image is loaded to the + * beginning of RAM + * + * 3. start_nxp_imx8mq_evk, now in RAM, is executed again + * + * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it + * + * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR, + * executing start_nxp_imx8mq_evk() the third time + * + * 6. Standard barebox boot flow continues + */ +ENTRY_FUNCTION(start_zii_imx8mq_dev, r0, r1, r2) +{ + imx8mq_cpu_lowlevel_init(); + relocate_to_current_adr(); + setup_c(); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + zii_imx8mq_dev_start(); +} diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c index 4a2b673..4d957da 100644 --- a/arch/arm/cpu/common.c +++ b/arch/arm/cpu/common.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -147,3 +148,10 @@ return __cpu_architecture; } #endif + +extern int __boot_cpu_mode; + +int boot_cpu_mode(void) +{ + return __boot_cpu_mode; +} diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c index b7a9eae..1f2c236 100644 --- a/arch/arm/cpu/sm.c +++ b/arch/arm/cpu/sm.c @@ -157,7 +157,7 @@ return -EINVAL; } - if (__boot_cpu_mode == HYP_MODE) + if (boot_cpu_mode() == HYP_MODE) return 0; mmuon = get_cr() & CR_M; @@ -235,7 +235,7 @@ bootm_secure_state_names, ARRAY_SIZE(bootm_secure_state_names)); - if (__boot_cpu_mode == HYP_MODE) + if (boot_cpu_mode() == HYP_MODE) bootm_secure_state = ARM_STATE_HYP; return 0; diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c index f5c7cfe..796239d 100644 --- a/arch/arm/cpu/start-pbl.c +++ b/arch/arm/cpu/start-pbl.c @@ -102,7 +102,7 @@ else barebox = (void *)barebox_base; - if (IS_ENABLED(CONFIG_CPU_V7) && __boot_cpu_mode == HYP_MODE) + if (IS_ENABLED(CONFIG_CPU_V7) && boot_cpu_mode() == HYP_MODE) armv7_switch_to_hyp(); barebox(membase, memsize, boarddata); diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c index c7851c5..4f16af2 100644 --- a/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c @@ -103,7 +103,7 @@ pr_debug("jumping to uncompressed image at 0x%p\n", barebox); - if (IS_ENABLED(CONFIG_CPU_V7) && __boot_cpu_mode == HYP_MODE) + if (IS_ENABLED(CONFIG_CPU_V7) && boot_cpu_mode() == HYP_MODE) armv7_switch_to_hyp(); barebox(membase, memsize, boarddata); diff --git a/arch/arm/include/asm/barebox-arm.h b/arch/arm/include/asm/barebox-arm.h index 9840482..8b2ecd9 100644 --- a/arch/arm/include/asm/barebox-arm.h +++ b/arch/arm/include/asm/barebox-arm.h @@ -31,6 +31,7 @@ #include #include #include +#include /* * We have a 4GiB address space split into 1MiB sections, with each @@ -43,15 +44,22 @@ /* global_variable_offset() - Access global variables when not running at link address * * Get the offset of global variables when not running at the address we are - * linked at. ARM uses absolute addresses, so we must add the runtime offset - * whereas aarch64 uses PC relative addresses, so nothing must be done here. + * linked at. */ static inline unsigned long global_variable_offset(void) { - if (IS_ENABLED(CONFIG_CPU_32)) - return get_runtime_offset(); - else - return 0; +#ifdef CONFIG_CPU_V8 + unsigned long text; + + __asm__ __volatile__( + "adr %0, _text\n" + : "=r" (text) + : + : "memory"); + return text - (unsigned long)_text; +#else + return get_runtime_offset(); +#endif } void setup_c(void); diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h index 663d81e..e0c2623 100644 --- a/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h @@ -10,7 +10,8 @@ void armv7_hyp_install(void); extern unsigned char secure_monitor_init_vectors[]; -extern int __boot_cpu_mode; + +int boot_cpu_mode(void); enum arm_security_state { ARM_STATE_SECURE,