diff --git a/arch/arm/Makefile b/arch/arm/Makefile index fbc6480..c0b725d 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -88,7 +88,7 @@ board-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp board-$(CONFIG_MACH_MINI2440) += friendlyarm-mini2440 board-$(CONFIG_MACH_MINI6410) += friendlyarm-mini6410 -board-$(CONFIG_MACH_PCM027) += pcm027 +board-$(CONFIG_MACH_PCM027) += phytec-phycore-pxa270 board-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ board-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox board-$(CONFIG_MACH_TINY210) += friendlyarm-tiny210 diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index a4219d7..befddd0 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -32,10 +32,10 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27/ obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += eukrea_cpuimx35/ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += eukrea_cpuimx51/ -obj-$(CONFIG_MACH_FREESCALE_MX25_3STACK) += freescale-mx25-3-stack/ -obj-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += freescale-mx35-3-stack/ -obj-$(CONFIG_MACH_FREESCALE_MX51_PDK) += freescale-mx51-pdk/ -obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += freescale-mx53-loco/ +obj-$(CONFIG_MACH_FREESCALE_MX25_3STACK) += freescale-mx25-3ds/ +obj-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += freescale-mx35-3ds/ +obj-$(CONFIG_MACH_FREESCALE_MX51_PDK) += freescale-mx51-babbage/ +obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += freescale-mx53-qsb/ obj-$(CONFIG_MACH_FREESCALE_MX53_SMD) += freescale-mx53-smd/ obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += freescale-mx53-vmx53/ obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/ @@ -43,9 +43,9 @@ obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/ obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/ obj-$(CONFIG_MACH_HIGHBANK) += highbank/ -obj-$(CONFIG_MACH_IMX21ADS) += imx21ads/ +obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/ -obj-$(CONFIG_MACH_IMX27ADS) += imx27ads/ +obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/ obj-$(CONFIG_MACH_MIOA701) += mioa701/ obj-$(CONFIG_MACH_MMCCPU) += mmccpu/ obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/ @@ -57,21 +57,21 @@ obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/ obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/ obj-$(CONFIG_MACH_PANDA) += panda/ -obj-$(CONFIG_MACH_PCA100) += phycard-i.MX27/ -obj-$(CONFIG_MACH_PCAAL1) += phycard-a-l1/ -obj-$(CONFIG_MACH_PCAAXL2) += phycard-a-xl2/ -obj-$(CONFIG_MACH_PCM037) += pcm037/ -obj-$(CONFIG_MACH_PCM038) += pcm038/ -obj-$(CONFIG_MACH_PCM043) += pcm043/ -obj-$(CONFIG_MACH_PCM049) += pcm049/ -obj-$(CONFIG_MACH_PCM051) += pcm051/ -obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-pfla02/ +obj-$(CONFIG_MACH_PCA100) += phytec-phycard-imx27/ +obj-$(CONFIG_MACH_PCAAL1) += phytec-phycard-omap3/ +obj-$(CONFIG_MACH_PCAAXL2) += phytec-phycard-omap4/ +obj-$(CONFIG_MACH_PCM037) += phytec-phycore-imx31/ +obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/ +obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/ +obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ +obj-$(CONFIG_MACH_PCM051) += phytec-phycore-am335x/ +obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-phyflex-imx6/ obj-$(CONFIG_MACH_PM9261) += pm9261/ obj-$(CONFIG_MACH_PM9263) += pm9263/ obj-$(CONFIG_MACH_PM9G45) += pm9g45/ obj-$(CONFIG_MACH_QIL_A9260) += qil-a926x/ obj-$(CONFIG_MACH_QIL_A9G20) += qil-a926x/ -obj-$(CONFIG_MACH_REALQ7) += dmo-mx6-realq7/ +obj-$(CONFIG_MACH_REALQ7) += datamodul-edm-qmx6/ obj-$(CONFIG_MACH_RPI) += raspberry-pi/ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/ obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/ diff --git a/arch/arm/boards/datamodul-edm-qmx6/Makefile b/arch/arm/boards/datamodul-edm-qmx6/Makefile new file mode 100644 index 0000000..bb6d9d8 --- /dev/null +++ b/arch/arm/boards/datamodul-edm-qmx6/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o lowlevel.o +pbl-y += lowlevel.o diff --git a/arch/arm/boards/datamodul-edm-qmx6/board.c b/arch/arm/boards/datamodul-edm-qmx6/board.c new file mode 100644 index 0000000..8a49bee --- /dev/null +++ b/arch/arm/boards/datamodul-edm-qmx6/board.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2012 Steffen Trumtrar, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define RQ7_GPIO_ENET_PHYADD2 IMX_GPIO_NR(6, 30) +#define RQ7_GPIO_ENET_MODE0 IMX_GPIO_NR(6, 25) +#define RQ7_GPIO_ENET_MODE1 IMX_GPIO_NR(6, 27) +#define RQ7_GPIO_ENET_MODE2 IMX_GPIO_NR(6, 28) +#define RQ7_GPIO_ENET_MODE3 IMX_GPIO_NR(6, 29) +#define RQ7_GPIO_ENET_EN_CLK125 IMX_GPIO_NR(6, 24) + +static iomux_v3_cfg_t realq7_pads_gpio[] = { + MX6Q_PAD_RGMII_RXC__GPIO_6_30, + MX6Q_PAD_RGMII_RD0__GPIO_6_25, + MX6Q_PAD_RGMII_RD1__GPIO_6_27, + MX6Q_PAD_RGMII_RD2__GPIO_6_28, + MX6Q_PAD_RGMII_RD3__GPIO_6_29, + MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24, +}; + +static int ksz9031rn_phy_fixup(struct phy_device *dev) +{ + /* + * min rx data delay, max rx/tx clock delay, + * min rx/tx control delay + */ + phy_write_mmd_indirect(dev, 4, 2, 0); + phy_write_mmd_indirect(dev, 5, 2, 0); + phy_write_mmd_indirect(dev, 8, 2, 0x03ff); + + return 0; +} + +static int realq7_enet_init(void) +{ + if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) + return 0; + + mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio)); + gpio_direction_output(RQ7_GPIO_ENET_PHYADD2, 0); + gpio_direction_output(RQ7_GPIO_ENET_MODE0, 1); + gpio_direction_output(RQ7_GPIO_ENET_MODE1, 1); + gpio_direction_output(RQ7_GPIO_ENET_MODE2, 1); + gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1); + gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1); + + gpio_direction_output(25, 0); + mdelay(50); + + gpio_direction_output(25, 1); + mdelay(50); + + phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, + ksz9031rn_phy_fixup); + + return 0; +} +fs_initcall(realq7_enet_init); + +static int realq7_env_init(void) +{ + if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) + return 0; + + imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", + BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0x00907000); + imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.barebox", + 0, NULL, 0, 0x00907000); + return 0; +} +late_initcall(realq7_env_init); + +static int realq7_console_init(void) +{ + if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) + return 0; + + barebox_set_hostname("eDM-QMX6"); + + imx6_init_lowlevel(); + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + of_device_enable_path("/chosen/environment-emmc"); + break; + default: + case BOOTSOURCE_SPI: + of_device_enable_path("/chosen/environment-spi"); + break; + } + + return 0; +} +postcore_initcall(realq7_console_init); diff --git a/arch/arm/boards/datamodul-edm-qmx6/env/boot/mmc b/arch/arm/boards/datamodul-edm-qmx6/env/boot/mmc new file mode 100644 index 0000000..e311763 --- /dev/null +++ b/arch/arm/boards/datamodul-edm-qmx6/env/boot/mmc @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "MMC" + exit +fi + +global.bootm.image="/mnt/mmc/zImage" +global.bootm.oftree="/mnt/mmc/oftree" +global.linux.bootargs.dyn.root="root=mmcblk0p2 rootfstype=ext3 rootwait" diff --git a/arch/arm/boards/datamodul-edm-qmx6/env/config-board b/arch/arm/boards/datamodul-edm-qmx6/env/config-board new file mode 100644 index 0000000..4cabac6 --- /dev/null +++ b/arch/arm/boards/datamodul-edm-qmx6/env/config-board @@ -0,0 +1,6 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.linux.bootargs.base="console=ttymxc1,115200" diff --git a/arch/arm/boards/datamodul-edm-qmx6/env/init/automount b/arch/arm/boards/datamodul-edm-qmx6/env/init/automount new file mode 100644 index 0000000..2ce37c7 --- /dev/null +++ b/arch/arm/boards/datamodul-edm-qmx6/env/init/automount @@ -0,0 +1,14 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mci0.probe=1 && [ -e /dev/disk0.0 ] && mount /dev/disk0.0 /mnt/fat' diff --git a/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg new file mode 100644 index 0000000..400a870 --- /dev/null +++ b/arch/arm/boards/datamodul-edm-qmx6/flash-header.imxcfg @@ -0,0 +1,3 @@ +soc imx6 +loadaddr 0x00907000 +dcdofs 0x400 diff --git a/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c new file mode 100644 index 0000000..de7cc98 --- /dev/null +++ b/arch/arm/boards/datamodul-edm-qmx6/lowlevel.c @@ -0,0 +1,173 @@ +/* + * Copyright (C) 2013 Sascha Hauer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void sdram_init(void) +{ + writel(0x0, 0x021b0000); + writel(0xffffffff, 0x020c4068); + writel(0xffffffff, 0x020c406c); + writel(0xffffffff, 0x020c4070); + writel(0xffffffff, 0x020c4074); + writel(0xffffffff, 0x020c4078); + writel(0xffffffff, 0x020c407c); + writel(0xffffffff, 0x020c4080); + writel(0xffffffff, 0x020c4084); + writel(0x000C0000, 0x020e0798); + writel(0x00000000, 0x020e0758); + writel(0x00000030, 0x020e0588); + writel(0x00000030, 0x020e0594); + writel(0x00000030, 0x020e056c); + writel(0x00000030, 0x020e0578); + writel(0x00000030, 0x020e074c); + writel(0x00000030, 0x020e057c); + writel(0x00000000, 0x020e058c); + writel(0x00000030, 0x020e059c); + writel(0x00000030, 0x020e05a0); + writel(0x00000030, 0x020e078c); + writel(0x00020000, 0x020e0750); + writel(0x00000038, 0x020e05a8); + writel(0x00000038, 0x020e05b0); + writel(0x00000038, 0x020e0524); + writel(0x00000038, 0x020e051c); + writel(0x00000038, 0x020e0518); + writel(0x00000038, 0x020e050c); + writel(0x00000038, 0x020e05b8); + writel(0x00000038, 0x020e05c0); + writel(0x00020000, 0x020e0774); + writel(0x00000030, 0x020e0784); + writel(0x00000030, 0x020e0788); + writel(0x00000030, 0x020e0794); + writel(0x00000030, 0x020e079c); + writel(0x00000030, 0x020e07a0); + writel(0x00000030, 0x020e07a4); + writel(0x00000030, 0x020e07a8); + writel(0x00000030, 0x020e0748); + writel(0x00000030, 0x020e05ac); + writel(0x00000030, 0x020e05b4); + writel(0x00000030, 0x020e0528); + writel(0x00000030, 0x020e0520); + writel(0x00000030, 0x020e0514); + writel(0x00000030, 0x020e0510); + writel(0x00000030, 0x020e05bc); + writel(0x00000030, 0x020e05c4); + writel(0xa1390003, 0x021b0800); + writel(0x0059005C, 0x021b080c); + writel(0x00590056, 0x021b0810); + writel(0x002E0049, 0x021b480c); + writel(0x001B0033, 0x021b4810); + writel(0x434F035B, 0x021b083c); + writel(0x033F033F, 0x021b0840); + writel(0x4337033D, 0x021b483c); + writel(0x03210275, 0x021b4840); + writel(0x4C454344, 0x021b0848); + writel(0x463F3E4A, 0x021b4848); + writel(0x46314742, 0x021b0850); + writel(0x4D2A4B39, 0x021b4850); + writel(0x33333333, 0x021b081c); + writel(0x33333333, 0x021b0820); + writel(0x33333333, 0x021b0824); + writel(0x33333333, 0x021b0828); + writel(0x33333333, 0x021b481c); + writel(0x33333333, 0x021b4820); + writel(0x33333333, 0x021b4824); + writel(0x33333333, 0x021b4828); + writel(0x00000800, 0x021b08b8); + writel(0x00000800, 0x021b48b8); + writel(0x00020036, 0x021b0004); + writel(0x09555050, 0x021b0008); + writel(0x8A8F7934, 0x021b000c); + writel(0xDB568E65, 0x021b0010); + writel(0x01FF00DB, 0x021b0014); + writel(0x00000740, 0x021b0018); + writel(0x00008000, 0x021b001c); + writel(0x000026d2, 0x021b002c); + writel(0x008F0E21, 0x021b0030); + writel(0x00000047, 0x021b0040); + writel(0x11420000, 0x021b0400); + writel(0x11420000, 0x021b4400); + writel(0x841A0000, 0x021b0000); + writel(0x04108032, 0x021b001c); + writel(0x00008033, 0x021b001c); + writel(0x00048031, 0x021b001c); + writel(0x09308030, 0x021b001c); + writel(0x04008040, 0x021b001c); + writel(0x0410803A, 0x021b001c); + writel(0x0000803B, 0x021b001c); + writel(0x00048039, 0x021b001c); + writel(0x09308038, 0x021b001c); + writel(0x04008048, 0x021b001c); + writel(0x00005800, 0x021b0020); + writel(0x00011117, 0x021b0818); + writel(0x00011117, 0x021b4818); + writel(0x00025576, 0x021b0004); + writel(0x00011006, 0x021b0404); + writel(0x00000000, 0x021b001c); + + /* Enable UART for lowlevel debugging purposes. Can be removed later */ + writel(0x4, 0x020e00bc); + writel(0x4, 0x020e00c0); + writel(0x1, 0x020e0928); + writel(0x00000000, 0x021e8080); + writel(0x00004027, 0x021e8084); + writel(0x00000704, 0x021e8088); + writel(0x00000a81, 0x021e8090); + writel(0x0000002b, 0x021e809c); + writel(0x00013880, 0x021e80b0); + writel(0x0000047f, 0x021e80a4); + writel(0x0000c34f, 0x021e80a8); + writel(0x00000001, 0x021e8080); + putc_ll('>'); +} + +extern char __dtb_imx6q_dmo_edmqmx6_start[]; +extern char __dtb_imx6q_dmo_edmqmx6_end[]; + +ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2) +{ + unsigned long fdt, sdram = 0x10000000; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00940000 - 8); + + fdt = (unsigned long)__dtb_imx6q_dmo_edmqmx6_start - get_runtime_offset(); + + if (get_pc() < 0x10000000) { + sdram_init(); + + mmdc_do_write_level_calibration(); + mmdc_do_dqs_calibration(); + + /* + * Copy the devicetree blob to sdram so that the barebox code finds it + * inside valid SDRAM instead of SRAM. + */ + memcpy((void *)sdram, (void *)fdt, + __dtb_imx6q_dmo_edmqmx6_start - + __dtb_imx6q_dmo_edmqmx6_end); + fdt = sdram; + } + + barebox_arm_entry(sdram, SZ_2G, fdt); +} diff --git a/arch/arm/boards/dmo-mx6-realq7/Makefile b/arch/arm/boards/dmo-mx6-realq7/Makefile deleted file mode 100644 index bb6d9d8..0000000 --- a/arch/arm/boards/dmo-mx6-realq7/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += board.o lowlevel.o -pbl-y += lowlevel.o diff --git a/arch/arm/boards/dmo-mx6-realq7/board.c b/arch/arm/boards/dmo-mx6-realq7/board.c deleted file mode 100644 index 8a49bee..0000000 --- a/arch/arm/boards/dmo-mx6-realq7/board.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 2012 Steffen Trumtrar, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#define RQ7_GPIO_ENET_PHYADD2 IMX_GPIO_NR(6, 30) -#define RQ7_GPIO_ENET_MODE0 IMX_GPIO_NR(6, 25) -#define RQ7_GPIO_ENET_MODE1 IMX_GPIO_NR(6, 27) -#define RQ7_GPIO_ENET_MODE2 IMX_GPIO_NR(6, 28) -#define RQ7_GPIO_ENET_MODE3 IMX_GPIO_NR(6, 29) -#define RQ7_GPIO_ENET_EN_CLK125 IMX_GPIO_NR(6, 24) - -static iomux_v3_cfg_t realq7_pads_gpio[] = { - MX6Q_PAD_RGMII_RXC__GPIO_6_30, - MX6Q_PAD_RGMII_RD0__GPIO_6_25, - MX6Q_PAD_RGMII_RD1__GPIO_6_27, - MX6Q_PAD_RGMII_RD2__GPIO_6_28, - MX6Q_PAD_RGMII_RD3__GPIO_6_29, - MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24, -}; - -static int ksz9031rn_phy_fixup(struct phy_device *dev) -{ - /* - * min rx data delay, max rx/tx clock delay, - * min rx/tx control delay - */ - phy_write_mmd_indirect(dev, 4, 2, 0); - phy_write_mmd_indirect(dev, 5, 2, 0); - phy_write_mmd_indirect(dev, 8, 2, 0x03ff); - - return 0; -} - -static int realq7_enet_init(void) -{ - if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) - return 0; - - mxc_iomux_v3_setup_multiple_pads(realq7_pads_gpio, ARRAY_SIZE(realq7_pads_gpio)); - gpio_direction_output(RQ7_GPIO_ENET_PHYADD2, 0); - gpio_direction_output(RQ7_GPIO_ENET_MODE0, 1); - gpio_direction_output(RQ7_GPIO_ENET_MODE1, 1); - gpio_direction_output(RQ7_GPIO_ENET_MODE2, 1); - gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1); - gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1); - - gpio_direction_output(25, 0); - mdelay(50); - - gpio_direction_output(25, 1); - mdelay(50); - - phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, - ksz9031rn_phy_fixup); - - return 0; -} -fs_initcall(realq7_enet_init); - -static int realq7_env_init(void) -{ - if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) - return 0; - - imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox", - BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0x00907000); - imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc3.barebox", - 0, NULL, 0, 0x00907000); - return 0; -} -late_initcall(realq7_env_init); - -static int realq7_console_init(void) -{ - if (!of_machine_is_compatible("dmo,imx6q-edmqmx6")) - return 0; - - barebox_set_hostname("eDM-QMX6"); - - imx6_init_lowlevel(); - - switch (bootsource_get()) { - case BOOTSOURCE_MMC: - of_device_enable_path("/chosen/environment-emmc"); - break; - default: - case BOOTSOURCE_SPI: - of_device_enable_path("/chosen/environment-spi"); - break; - } - - return 0; -} -postcore_initcall(realq7_console_init); diff --git a/arch/arm/boards/dmo-mx6-realq7/env/boot/mmc b/arch/arm/boards/dmo-mx6-realq7/env/boot/mmc deleted file mode 100644 index e311763..0000000 --- a/arch/arm/boards/dmo-mx6-realq7/env/boot/mmc +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "MMC" - exit -fi - -global.bootm.image="/mnt/mmc/zImage" -global.bootm.oftree="/mnt/mmc/oftree" -global.linux.bootargs.dyn.root="root=mmcblk0p2 rootfstype=ext3 rootwait" diff --git a/arch/arm/boards/dmo-mx6-realq7/env/config-board b/arch/arm/boards/dmo-mx6-realq7/env/config-board deleted file mode 100644 index 4cabac6..0000000 --- a/arch/arm/boards/dmo-mx6-realq7/env/config-board +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.linux.bootargs.base="console=ttymxc1,115200" diff --git a/arch/arm/boards/dmo-mx6-realq7/env/init/automount b/arch/arm/boards/dmo-mx6-realq7/env/init/automount deleted file mode 100644 index 2ce37c7..0000000 --- a/arch/arm/boards/dmo-mx6-realq7/env/init/automount +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - -# automount tftp server based on $eth0.serverip - -mkdir -p /mnt/tftp -automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' - -mkdir -p /mnt/mmc -automount -d /mnt/mmc 'mci0.probe=1 && [ -e /dev/disk0.0 ] && mount /dev/disk0.0 /mnt/fat' diff --git a/arch/arm/boards/dmo-mx6-realq7/flash-header.imxcfg b/arch/arm/boards/dmo-mx6-realq7/flash-header.imxcfg deleted file mode 100644 index 400a870..0000000 --- a/arch/arm/boards/dmo-mx6-realq7/flash-header.imxcfg +++ /dev/null @@ -1,3 +0,0 @@ -soc imx6 -loadaddr 0x00907000 -dcdofs 0x400 diff --git a/arch/arm/boards/dmo-mx6-realq7/lowlevel.c b/arch/arm/boards/dmo-mx6-realq7/lowlevel.c deleted file mode 100644 index de7cc98..0000000 --- a/arch/arm/boards/dmo-mx6-realq7/lowlevel.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (C) 2013 Sascha Hauer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void sdram_init(void) -{ - writel(0x0, 0x021b0000); - writel(0xffffffff, 0x020c4068); - writel(0xffffffff, 0x020c406c); - writel(0xffffffff, 0x020c4070); - writel(0xffffffff, 0x020c4074); - writel(0xffffffff, 0x020c4078); - writel(0xffffffff, 0x020c407c); - writel(0xffffffff, 0x020c4080); - writel(0xffffffff, 0x020c4084); - writel(0x000C0000, 0x020e0798); - writel(0x00000000, 0x020e0758); - writel(0x00000030, 0x020e0588); - writel(0x00000030, 0x020e0594); - writel(0x00000030, 0x020e056c); - writel(0x00000030, 0x020e0578); - writel(0x00000030, 0x020e074c); - writel(0x00000030, 0x020e057c); - writel(0x00000000, 0x020e058c); - writel(0x00000030, 0x020e059c); - writel(0x00000030, 0x020e05a0); - writel(0x00000030, 0x020e078c); - writel(0x00020000, 0x020e0750); - writel(0x00000038, 0x020e05a8); - writel(0x00000038, 0x020e05b0); - writel(0x00000038, 0x020e0524); - writel(0x00000038, 0x020e051c); - writel(0x00000038, 0x020e0518); - writel(0x00000038, 0x020e050c); - writel(0x00000038, 0x020e05b8); - writel(0x00000038, 0x020e05c0); - writel(0x00020000, 0x020e0774); - writel(0x00000030, 0x020e0784); - writel(0x00000030, 0x020e0788); - writel(0x00000030, 0x020e0794); - writel(0x00000030, 0x020e079c); - writel(0x00000030, 0x020e07a0); - writel(0x00000030, 0x020e07a4); - writel(0x00000030, 0x020e07a8); - writel(0x00000030, 0x020e0748); - writel(0x00000030, 0x020e05ac); - writel(0x00000030, 0x020e05b4); - writel(0x00000030, 0x020e0528); - writel(0x00000030, 0x020e0520); - writel(0x00000030, 0x020e0514); - writel(0x00000030, 0x020e0510); - writel(0x00000030, 0x020e05bc); - writel(0x00000030, 0x020e05c4); - writel(0xa1390003, 0x021b0800); - writel(0x0059005C, 0x021b080c); - writel(0x00590056, 0x021b0810); - writel(0x002E0049, 0x021b480c); - writel(0x001B0033, 0x021b4810); - writel(0x434F035B, 0x021b083c); - writel(0x033F033F, 0x021b0840); - writel(0x4337033D, 0x021b483c); - writel(0x03210275, 0x021b4840); - writel(0x4C454344, 0x021b0848); - writel(0x463F3E4A, 0x021b4848); - writel(0x46314742, 0x021b0850); - writel(0x4D2A4B39, 0x021b4850); - writel(0x33333333, 0x021b081c); - writel(0x33333333, 0x021b0820); - writel(0x33333333, 0x021b0824); - writel(0x33333333, 0x021b0828); - writel(0x33333333, 0x021b481c); - writel(0x33333333, 0x021b4820); - writel(0x33333333, 0x021b4824); - writel(0x33333333, 0x021b4828); - writel(0x00000800, 0x021b08b8); - writel(0x00000800, 0x021b48b8); - writel(0x00020036, 0x021b0004); - writel(0x09555050, 0x021b0008); - writel(0x8A8F7934, 0x021b000c); - writel(0xDB568E65, 0x021b0010); - writel(0x01FF00DB, 0x021b0014); - writel(0x00000740, 0x021b0018); - writel(0x00008000, 0x021b001c); - writel(0x000026d2, 0x021b002c); - writel(0x008F0E21, 0x021b0030); - writel(0x00000047, 0x021b0040); - writel(0x11420000, 0x021b0400); - writel(0x11420000, 0x021b4400); - writel(0x841A0000, 0x021b0000); - writel(0x04108032, 0x021b001c); - writel(0x00008033, 0x021b001c); - writel(0x00048031, 0x021b001c); - writel(0x09308030, 0x021b001c); - writel(0x04008040, 0x021b001c); - writel(0x0410803A, 0x021b001c); - writel(0x0000803B, 0x021b001c); - writel(0x00048039, 0x021b001c); - writel(0x09308038, 0x021b001c); - writel(0x04008048, 0x021b001c); - writel(0x00005800, 0x021b0020); - writel(0x00011117, 0x021b0818); - writel(0x00011117, 0x021b4818); - writel(0x00025576, 0x021b0004); - writel(0x00011006, 0x021b0404); - writel(0x00000000, 0x021b001c); - - /* Enable UART for lowlevel debugging purposes. Can be removed later */ - writel(0x4, 0x020e00bc); - writel(0x4, 0x020e00c0); - writel(0x1, 0x020e0928); - writel(0x00000000, 0x021e8080); - writel(0x00004027, 0x021e8084); - writel(0x00000704, 0x021e8088); - writel(0x00000a81, 0x021e8090); - writel(0x0000002b, 0x021e809c); - writel(0x00013880, 0x021e80b0); - writel(0x0000047f, 0x021e80a4); - writel(0x0000c34f, 0x021e80a8); - writel(0x00000001, 0x021e8080); - putc_ll('>'); -} - -extern char __dtb_imx6q_dmo_edmqmx6_start[]; -extern char __dtb_imx6q_dmo_edmqmx6_end[]; - -ENTRY_FUNCTION(start_imx6_realq7, r0, r1, r2) -{ - unsigned long fdt, sdram = 0x10000000; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(0x00940000 - 8); - - fdt = (unsigned long)__dtb_imx6q_dmo_edmqmx6_start - get_runtime_offset(); - - if (get_pc() < 0x10000000) { - sdram_init(); - - mmdc_do_write_level_calibration(); - mmdc_do_dqs_calibration(); - - /* - * Copy the devicetree blob to sdram so that the barebox code finds it - * inside valid SDRAM instead of SRAM. - */ - memcpy((void *)sdram, (void *)fdt, - __dtb_imx6q_dmo_edmqmx6_start - - __dtb_imx6q_dmo_edmqmx6_end); - fdt = sdram; - } - - barebox_arm_entry(sdram, SZ_2G, fdt); -} diff --git a/arch/arm/boards/freescale-mx21-ads/Makefile b/arch/arm/boards/freescale-mx21-ads/Makefile new file mode 100644 index 0000000..a43425b --- /dev/null +++ b/arch/arm/boards/freescale-mx21-ads/Makefile @@ -0,0 +1,2 @@ +lwl-y += lowlevel_init.o +obj-y += imx21ads.o diff --git a/arch/arm/boards/freescale-mx21-ads/env/bin/init b/arch/arm/boards/freescale-mx21-ads/env/bin/init new file mode 100644 index 0000000..224a6b4 --- /dev/null +++ b/arch/arm/boards/freescale-mx21-ads/env/bin/init @@ -0,0 +1 @@ +# Dummy Init environment script diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.c b/arch/arm/boards/freescale-mx21-ads/imx21ads.c new file mode 100644 index 0000000..1bbd8cb --- /dev/null +++ b/arch/arm/boards/freescale-mx21-ads/imx21ads.c @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2009 Ivo Clarysse + * + * Based on imx27ads.c, + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MX21ADS_IO_REG 0xCC800000 +#define MX21ADS_IO_LCDON (1 << 9) + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +/* Sharp LQ035Q7DB02 QVGA display */ +static struct imx_fb_videomode imx_fb_modedata = { + .mode = { + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 188679, + .left_margin = 6, + .right_margin = 16, + .upper_margin = 8, + .lower_margin = 10, + .hsync_len = 2, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, + .pcr = 0xfb108bc7, + .bpp = 16, +}; + +static struct imx_fb_platform_data imx_fb_data = { + .mode = &imx_fb_modedata, + .num_modes = 1, + .cmap_greyscale = 0, + .cmap_inverse = 0, + .cmap_static = 0, + .pwmr = 0x00a903ff, + .lscr1 = 0x00120300, + .dmacr = 0x00020008, +}; + +static int imx21ads_timing_init(void) +{ + u32 temp; + + /* Configure External Interface Module */ + /* CS0: burst flash */ + imx21_setup_eimcs(0, 0x00003E00, 0x00000E01); + + /* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */ + imx21_setup_eimcs(1, 0x00002000, 0x11118501); + + /* CS2-CS5: disable */ + imx21_setup_eimcs(2, 0x0, 0x0); + imx21_setup_eimcs(3, 0x0, 0x0); + imx21_setup_eimcs(4, 0x0, 0x0); + imx21_setup_eimcs(5, 0x0, 0x0); + + temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0); + temp &= ~0xF000; + temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */ + writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0); + + return 0; +} + +core_initcall(imx21ads_timing_init); + +static int mx21ads_mem_init(void) +{ + arm_add_mem_device("ram0", 0xc0000000, SZ_64M); + + return 0; +} +mem_initcall(mx21ads_mem_init); + +static int mx21ads_devices_init(void) +{ + int i; + unsigned int mode[] = { + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA24_PF_REV, + PA25_PF_CLS, + PA26_PF_PS, + PA27_PF_SPL_SPR, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + }; + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR, + 32 * 1024 * 1024, 0); + imx21_add_nand(&nand_info); + add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, + MX21_CS1_BASE_ADDR, 0x1000, + IORESOURCE_MEM, NULL); + imx21_add_fb(&imx_fb_data); + + armlinux_set_architecture(MACH_TYPE_MX21ADS); + + return 0; +} + +device_initcall(mx21ads_devices_init); + +static int mx21ads_enable_display(void) +{ + u16 tmp; + + tmp = readw(MX21ADS_IO_REG); + tmp |= MX21ADS_IO_LCDON; + writew(tmp, MX21ADS_IO_REG); + return 0; +} + +late_initcall(mx21ads_enable_display); + +static int mx21ads_console_init(void) +{ + barebox_set_model("Freescale i.MX21 ADS"); + barebox_set_hostname("mx21ads"); + + imx21_add_uart0(); + return 0; +} + +console_initcall(mx21ads_console_init); diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.dox b/arch/arm/boards/freescale-mx21-ads/imx21ads.dox new file mode 100644 index 0000000..9f11ffa --- /dev/null +++ b/arch/arm/boards/freescale-mx21-ads/imx21ads.dox @@ -0,0 +1,5 @@ +/** @page imx21ads Freescale i.MX21ads + +This is the Freescale evaluation board for the i.MX21 Processor + +*/ diff --git a/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S new file mode 100644 index 0000000..471390f --- /dev/null +++ b/arch/arm/boards/freescale-mx21-ads/lowlevel_init.S @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2010 Jaccon Bastiaansen + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + + .section ".text_bare_init","ax" + +.globl barebox_arm_reset_vector +barebox_arm_reset_vector: + + bl arm_cpu_lowlevel_init + +/* + * Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to + * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21 + * reference manual. + */ + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0 + ldr r1, =0x00040304 + str r1, [r0] + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1 + ldr r1, =0xfffbfcfb + str r1, [r0] + + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0 + ldr r1, =0x3ffc0000 + str r1, [r0] + ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1 + ldr r1, =0xffffffff + str r1, [r0] + +/* + * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable + * the clock to peripherals. + */ + ldr r0, =MX21_CCM_BASE_ADDR + MX21_CSCR + ldr r1, =0x17180607 + str r1, [r0] + + ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1 + ldr r1, =0x0e000000 + str r1, [r0] + + +/* + * SDRAM and SDRAM controller configuration + */ + + /* + * CSD1 not required, because the MX21ADS board only contains 64Mbyte. + * CS3 can therefore be made available. + */ + ldr r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR + ldr r1, =0xffffffc9 + str r1, [r0] + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0xc0000000 + bls 1f + cmp pc, #0xc8000000 + bhi 1f + + b ret +1: + + /* Precharge */ + ldr r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0 + ldr r1, =0x92120300 + str r1, [r0] + ldr r2, =0xc0200000 + ldr r1, [r2] + + bl mem_delay + + /* Auto refresh */ + ldr r1, =0xa2120300 + str r1, [r0] + ldr r2, =0xc0000000 + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + ldr r1, [r2] + + /* Set mode register */ + ldr r1, =0xB2120300 + str r1, [r0] + ldr r1, =0xC0119800 + ldr r2, [r1] + + bl mem_delay + + /* Back to Normal Mode */ + ldr r1, =0x8212F339 + str r1, [r0] + + /* Set NFC_CLK to 24MHz */ + ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0 + ldr r1, =0x6419a007 + str r1, [r0] + +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND { + + /* Setup a temporary stack in SRAM */ + ldr sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4 + + b imx21_barebox_boot_nand_external +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ + +ret: + mov r0, #0xc0000000 + mov r1, #SZ_64M + mov r2, #0 + b barebox_arm_entry + +/* + * spin for a while. we need to wait at least 200 usecs. + */ +mem_delay: + mov r4, #0x4000 +spin: subs r4, r4, #1 + bne spin + mov pc, lr + diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c deleted file mode 100644 index bd0e839..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void __naked __flash_header_start go(void) -{ - barebox_arm_head(); -} - -struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { - { .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, }, - { .ptr_type = 4, .addr = 0xb8002054, .val = 0x22252521, }, - { .ptr_type = 4, .addr = 0xb8002058, .val = 0x22220a00, }, -#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 - { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, - { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000304, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, - { .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, - { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x83000000, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x80000333, .val = 0xda, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, - { .ptr_type = 4, .addr = 0x80000400, .val = 0x12344321, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2210000, }, - { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, - { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, - { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x81000780, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, -#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR - { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, }, - { .ptr_type = 1, .addr = 0x80000400, .val = 0x21, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, }, - { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, - { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, }, - { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x81000000, .val = 0xff, }, - { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216880, }, - { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, }, -#else -#error "Unsupported SDRAM type" -#endif - { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, -}; - -struct imx_flash_header __flash_header_section flash_header = { - .app_code_jump_vector = DEST_BASE + 0x1000, - .app_code_barker = APP_CODE_BARKER, - .app_code_csf = 0, - .dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd), - .super_root_key = 0, - .dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker), - .app_dest = DEST_BASE, - .dcd_barker = DCD_BARKER, - .dcd_block_len = sizeof(dcd_entry), -}; - -unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_RMII, - .phy_addr = 1, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, -}; - -#ifdef CONFIG_USB -static void imx25_usb_init(void) -{ - unsigned int tmp; - - /* Host 2 */ - tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~(3 << 21); - tmp |= (2 << 21) | (1 << 4) | (1 << 5); - writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584); - tmp |= 3 << 30; - writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584); - - /* Set to Host mode */ - tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8); - writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8); -} -#endif - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("mc34704", 0x54), - }, -}; - -static int imx25_3ds_pmic_init(void) -{ - struct mc34704 *pmic; - - pmic = mc34704_get(); - if (pmic == NULL) - return -EIO; - - return mc34704_reg_write(pmic, 0x2, 0x9); -} - -static int imx25_3ds_fec_init(void) -{ - int ret; - - ret = imx25_3ds_pmic_init(); - if (ret < 0) - return ret; - - /* - * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. - * Assert FEC_RESET_B, then power up the PHY by asserting - * FEC_ENABLE, at the same time lifting FEC_RESET_B. - * - * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 - * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 - */ - writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */ - writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */ - -#define FEC_ENABLE_GPIO 35 -#define FEC_RESET_B_GPIO 104 - - /* make the pins output */ - gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ - gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ - udelay(2); - - /* turn on power & lift reset */ - gpio_set_value(FEC_ENABLE_GPIO, 1); - gpio_set_value(FEC_RESET_B_GPIO, 1); - - return 0; -} -late_initcall(imx25_3ds_fec_init); - -static int imx25_3ds_devices_init(void) -{ -#ifdef CONFIG_USB - /* USB does not work yet. Don't know why. Maybe - * the CPLD has to be initialized. - */ - imx25_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL); -#endif - - imx25_iim_register_fec_ethaddr(); - imx25_add_fec(&fec_info); - - add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE); - - if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) - nand_info.width = 2; - - imx25_add_nand(&nand_info); - - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - imx25_add_i2c0(NULL); - - armlinux_set_architecture(MACH_TYPE_MX25_3DS); - armlinux_set_serial(imx_uid()); - - return 0; -} - -device_initcall(imx25_3ds_devices_init); - -static iomux_v3_cfg_t imx25_pads[] = { - MX25_PAD_FEC_MDC__FEC_MDC, - MX25_PAD_FEC_MDIO__FEC_MDIO, - MX25_PAD_FEC_RDATA0__FEC_RDATA0, - MX25_PAD_FEC_RDATA1__FEC_RDATA1, - MX25_PAD_FEC_RX_DV__FEC_RX_DV, - MX25_PAD_FEC_TDATA0__FEC_TDATA0, - MX25_PAD_FEC_TDATA1__FEC_TDATA1, - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX25_PAD_FEC_TX_EN__FEC_TX_EN, - MX25_PAD_POWER_FAIL__POWER_FAIL, - MX25_PAD_A17__GPIO_2_3, - MX25_PAD_D12__GPIO_4_8, - /* UART1 */ - MX25_PAD_UART1_RXD__UART1_RXD, - MX25_PAD_UART1_TXD__UART1_TXD, - MX25_PAD_UART1_RTS__UART1_RTS, - MX25_PAD_UART1_CTS__UART1_CTS, - /* USBH2 */ - MX25_PAD_D9__USBH2_PWR, - MX25_PAD_D8__USBH2_OC, - MX25_PAD_LD0__USBH2_CLK, - MX25_PAD_LD1__USBH2_DIR, - MX25_PAD_LD2__USBH2_STP, - MX25_PAD_LD3__USBH2_NXT, - MX25_PAD_LD4__USBH2_DATA0, - MX25_PAD_LD5__USBH2_DATA1, - MX25_PAD_LD6__USBH2_DATA2, - MX25_PAD_LD7__USBH2_DATA3, - MX25_PAD_HSYNC__USBH2_DATA4, - MX25_PAD_VSYNC__USBH2_DATA5, - MX25_PAD_LSCLK__USBH2_DATA6, - MX25_PAD_OE_ACD__USBH2_DATA7, - /* i2c */ - MX25_PAD_I2C1_CLK__I2C1_CLK, - MX25_PAD_I2C1_DAT__I2C1_DAT, -}; - -static int imx25_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads)); - - writel(0x03010101, 0x53f80024); - - barebox_set_model("Freescale i.MX25 3DS"); - barebox_set_hostname("mx25-3stack"); - - imx25_add_uart0(); - return 0; -} - -console_initcall(imx25_console_init); - -static int imx25_core_setup(void) -{ - writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); - return 0; - -} -core_initcall(imx25_core_setup); diff --git a/arch/arm/boards/freescale-mx25-3-stack/Makefile b/arch/arm/boards/freescale-mx25-3-stack/Makefile deleted file mode 100644 index 52c416e..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel_init.o -obj-y += 3stack.o diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update b/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update deleted file mode 100644 index 014bce3..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/env/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot b/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot deleted file mode 100644 index 7bbff2d..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/env/bin/boot +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xnand ]; then - root=nand - kernel=nand -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$1 = xnor ]; then - root=nor - kernel=nor -fi - -if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" -else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" -fi - -if [ x$root = xnand ]; then - bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" -elif [ x$root = xnor ]; then - bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" -else - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" -fi - -bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" - -if [ $kernel = net ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -elif [ $kernel = nor ]; then - bootm /dev/nor0.kernel -else - bootm /dev/nand0.kernel.bb -fi - diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack b/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack deleted file mode 100644 index 5fffa92..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/env/bin/hush_hack +++ /dev/null @@ -1 +0,0 @@ -nand -a /dev/nand0.* diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/init b/arch/arm/boards/freescale-mx25-3-stack/env/bin/init deleted file mode 100644 index 0600b9e..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/env/bin/init +++ /dev/null @@ -1,30 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -if [ -e /dev/nor0 ]; then - addpart /dev/nor0 $nor_parts -fi - -if [ -e /dev/nand0 ]; then - addpart /dev/nand0 $nand_parts - - # Uh, oh, hush first expands wildcards and then starts executing - # commands. What a bug! - source /env/bin/hush_hack -fi - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel nand|nor [] to update kernel into flash" - echo "type update_root nand|nor [] to update rootfs into flash" - echo - exit -fi - -boot diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel deleted file mode 100644 index 05c822d..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_kernel +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -if [ x$1 = xnand ]; then - part=/dev/nand0.kernel.bb -elif [ x$1 = xnor ]; then - part=/dev/nor0.kernel -else - echo "usage: $0 nor|nand [imagename]" - exit 1 -fi - -. /env/bin/_update $2 diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root b/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root deleted file mode 100644 index eaf36eb..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/env/bin/update_root +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -if [ x$1 = xnand ]; then - part=/dev/nand0.root.bb -elif [ x$1 = xnor ]; then - part=/dev/nor0.root -else - echo "usage: $0 nor|nand [imagename]" - exit 1 -fi - -. /env/bin/_update $2 - diff --git a/arch/arm/boards/freescale-mx25-3-stack/env/config b/arch/arm/boards/freescale-mx25-3-stack/env/config deleted file mode 100644 index a5e492e..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/env/config +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/sh - -# can be either 'net', 'nor' or 'nand'' -kernel=net -root=net - -uimage=uImage-pcm043 -jffs2=root-pcm043.jffs2 - -autoboot_timeout=3 - -nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root" -bootargs="console=ttymxc0,115200" - -nor_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)" -rootpart_nor="/dev/mtdblock3" - -nand_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),108416k(root),-(kernel1)" -rootpart_nand="/dev/mtdblock7" - -# use 'dhcp' to do dhcp in barebox and in kernel -#ip=dhcp - -# or set your networking parameters here -eth0.ipaddr=192.168.3.11 -eth0.netmask=255.255.255.0 -#eth0.gateway=a.b.c.d -eth0.serverip=192.168.3.10 -eth0.ethaddr=00:50:c2:8c:e6:0e diff --git a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S deleted file mode 100644 index 4ca4c82..0000000 --- a/arch/arm/boards/freescale-mx25-3-stack/lowlevel_init.S +++ /dev/null @@ -1,229 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define writeb(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - strb r1, [r0]; - -/* Assuming 24MHz input clock */ -#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) -#define MPCTL_PARAM_532 (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) -#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) - -.section ".text_bare_init","ax" - -ARM_PPMRR: .word 0x40000015 -L2CACHE_PARAM: .word 0x00030024 -CCM_CCMR_W: .word 0x003F4208 -CCM_PDR0_W: .word 0x00801000 -MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 -MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 -PPCTL_PARAM_W: .word PPCTL_PARAM_300 -CCM_BASE_ADDR_W: .word MX25_CCM_BASE_ADDR - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - -#define MX25_CCM_MCR 0x64 - - ldr r0, CCM_BASE_ADDR_W - /* default CLKO to 1/32 of the ARM core */ - ldr r1, [r0, #MX25_CCM_MCR] - bic r1, r1, #0x00F00000 - bic r1, r1, #0x7F000000 - mov r2, #0x5F000000 - add r2, r2, #0x00200000 - orr r1, r1, r2 - str r1, [r0, #MX25_CCM_MCR] - - /* enable all the clocks */ - writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0) - writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1) - writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2) - writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR) - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #0x80000000 - bls 1f - cmp pc, #0x90000000 - bhi 1f - - b imx25_barebox_entry - -1: - ldr r0, ESDCTL_BASE_W - mov r3, #0x2000 - str r3, [r0, #0x0] - str r3, [r0, #0x8] - - mov r12, #0x00 - mov r2, #0x1 /* mDDR */ - mov r1, #MX25_CSD0_BASE_ADDR - bl setup_sdram_bank -// cmp r3, #0x0 -// orreq r12, r12, #1 -// eorne r2, r2, #0x1 -// blne setup_sdram_bank - - ldr r3, ESDCTL_DELAY5 - str r3, [r0, #0x30] - -#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - - /* Setup a temporary stack in SRAM */ - ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 - - mov r0, #0 - b imx25_barebox_boot_nand_external -#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ - -ret: - b imx25_barebox_entry - -/* - * r0: control base, r1: ram bank base - * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working - */ -setup_sdram_bank: - mov r3, #0xE /* 0xA + 0x4 */ - tst r2, #0x1 - orreq r3, r3, #0x300 /* DDR2 */ - str r3, [r0, #0x10] - bic r3, r3, #0x00A - str r3, [r0, #0x10] - beq 2f - - mov r3, #0x20000 -1: subs r3, r3, #1 - bne 1b - -2: adr r4, ESDCTL_CONFIG - tst r2, #0x1 - ldreq r3, [r4, #0x0] - ldrne r3, [r4, #0x4] - cmp r1, #MX25_CSD1_BASE_ADDR - strlo r3, [r0, #0x4] - strhs r3, [r0, #0xC] - - ldr r3, ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, RAM_PARAM1_MDDR - strb r3, [r1, r4] - - tst r2, #0x1 - bne skip_set_mode - - cmp r1, #MX25_CSD1_BASE_ADDR - ldr r3, ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, RAM_PARAM4_MDDR - strb r3, [r1, r4] - ldr r4, RAM_PARAM5_MDDR - strb r3, [r1, r4] - ldr r4, RAM_PARAM3_MDDR - strb r3, [r1, r4] - ldr r4, RAM_PARAM2_MDDR - strb r3, [r1, r4] - - ldr r3, ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, RAM_PARAM1_MDDR - strb r3, [r1, r4] - -skip_set_mode: - cmp r1, #MX25_CSD1_BASE_ADDR - ldr r3, ESDCTL_0xA2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - strb r3, [r1] - strb r3, [r1] - - ldr r3, ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - adr r4, RAM_PARAM6_MDDR - tst r2, #0x1 - ldreq r4, [r4, #0x0] - ldrne r4, [r4, #0x4] - mov r3, #0xDA - strb r3, [r1, r4] - ldreq r4, RAM_PARAM7_MDDR - streqb r3, [r1, r4] - adr r4, RAM_PARAM3_MDDR - ldreq r4, [r4, #0x0] - ldrne r4, [r4, #0x4] - strb r3, [r1, r4] - - cmp r1, #MX25_CSD1_BASE_ADDR - ldr r3, ESDCTL_0x82226080 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - - tst r2, #0x1 - moveq r4, #0x20000 - movne r4, #0x200 -1: subs r4, r4, #1 - bne 1b - - str r3, [r1, #0x100] - ldr r4, [r1, #0x100] - cmp r3, r4 - movne r3, #1 - moveq r3, #0 - - mov pc, lr - -RAM_PARAM1_MDDR: .word 0x00000400 -RAM_PARAM2_MDDR: .word 0x00000333 -RAM_PARAM3_MDDR: .word 0x02000400 - .word 0x02000000 -RAM_PARAM4_MDDR: .word 0x04000000 -RAM_PARAM5_MDDR: .word 0x06000000 -RAM_PARAM6_MDDR: .word 0x00000233 - .word 0x00000033 -RAM_PARAM7_MDDR: .word 0x02000780 -ESDCTL_0x92220000: .word 0x92210000 -ESDCTL_0xA2220000: .word 0xA2210000 -ESDCTL_0xB2220000: .word 0xB2210000 -ESDCTL_0x82226080: .word 0x82216080 -ESDCTL_CONFIG: .word 0x007FFC3F - .word 0x007FFC3F -ESDCTL_DELAY5: .word 0x00F49F00 -ESDCTL_BASE_W: .word MX25_ESDCTL_BASE_ADDR - diff --git a/arch/arm/boards/freescale-mx25-3ds/3stack.c b/arch/arm/boards/freescale-mx25-3ds/3stack.c new file mode 100644 index 0000000..bd0e839 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/3stack.c @@ -0,0 +1,285 @@ +/* + * (C) 2009 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { + { .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, }, + { .ptr_type = 4, .addr = 0xb8002054, .val = 0x22252521, }, + { .ptr_type = 4, .addr = 0xb8002058, .val = 0x22220a00, }, +#if defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_64MB_DDR2 + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0076e83a, }, + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000304, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, + { .ptr_type = 4, .addr = 0x80000f00, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, + { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x83000000, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x80000333, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92210000, }, + { .ptr_type = 4, .addr = 0x80000400, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2210000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2210000, }, + { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000780, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000400, .val = 0xda, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216080, }, +#elif defined CONFIG_FREESCALE_MX25_3STACK_SDRAM_128MB_MDDR + { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92100000, }, + { .ptr_type = 1, .addr = 0x80000400, .val = 0x21, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2100000, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2100000, }, + { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x81000000, .val = 0xff, }, + { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82216880, }, + { .ptr_type = 4, .addr = 0xb8001004, .val = 0x00295729, }, +#else +#error "Unsupported SDRAM type" +#endif + { .ptr_type = 4, .addr = 0x53f80008, .val = 0x20034000, }, +}; + +struct imx_flash_header __flash_header_section flash_header = { + .app_code_jump_vector = DEST_BASE + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = DEST_BASE, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof(dcd_entry), +}; + +unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; + +static struct fec_platform_data fec_info = { + .xcv_type = PHY_INTERFACE_MODE_RMII, + .phy_addr = 1, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +}; + +#ifdef CONFIG_USB +static void imx25_usb_init(void) +{ + unsigned int tmp; + + /* Host 2 */ + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x600); + tmp &= ~(3 << 21); + tmp |= (2 << 21) | (1 << 4) | (1 << 5); + writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x600); + + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x584); + tmp |= 3 << 30; + writel(tmp, MX25_USB_OTG_BASE_ADDR + 0x584); + + /* Set to Host mode */ + tmp = readl(MX25_USB_OTG_BASE_ADDR + 0x5a8); + writel(tmp | 0x3, MX25_USB_OTG_BASE_ADDR + 0x5a8); +} +#endif + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("mc34704", 0x54), + }, +}; + +static int imx25_3ds_pmic_init(void) +{ + struct mc34704 *pmic; + + pmic = mc34704_get(); + if (pmic == NULL) + return -EIO; + + return mc34704_reg_write(pmic, 0x2, 0x9); +} + +static int imx25_3ds_fec_init(void) +{ + int ret; + + ret = imx25_3ds_pmic_init(); + if (ret < 0) + return ret; + + /* + * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins. + * Assert FEC_RESET_B, then power up the PHY by asserting + * FEC_ENABLE, at the same time lifting FEC_RESET_B. + * + * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17 + * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12 + */ + writel(0x8, MX25_IOMUXC_BASE_ADDR + 0x0238); /* open drain */ + writel(0x0, MX25_IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */ + +#define FEC_ENABLE_GPIO 35 +#define FEC_RESET_B_GPIO 104 + + /* make the pins output */ + gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */ + gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */ + udelay(2); + + /* turn on power & lift reset */ + gpio_set_value(FEC_ENABLE_GPIO, 1); + gpio_set_value(FEC_RESET_B_GPIO, 1); + + return 0; +} +late_initcall(imx25_3ds_fec_init); + +static int imx25_3ds_devices_init(void) +{ +#ifdef CONFIG_USB + /* USB does not work yet. Don't know why. Maybe + * the CPLD has to be initialized. + */ + imx25_usb_init(); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX25_USB_OTG_BASE_ADDR + 0x400, NULL); +#endif + + imx25_iim_register_fec_ethaddr(); + imx25_add_fec(&fec_info); + + add_mem_device("sram0", 0x78000000, 128 * 1024, IORESOURCE_MEM_WRITEABLE); + + if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 14)) + nand_info.width = 2; + + imx25_add_nand(&nand_info); + + devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + imx25_add_i2c0(NULL); + + armlinux_set_architecture(MACH_TYPE_MX25_3DS); + armlinux_set_serial(imx_uid()); + + return 0; +} + +device_initcall(imx25_3ds_devices_init); + +static iomux_v3_cfg_t imx25_pads[] = { + MX25_PAD_FEC_MDC__FEC_MDC, + MX25_PAD_FEC_MDIO__FEC_MDIO, + MX25_PAD_FEC_RDATA0__FEC_RDATA0, + MX25_PAD_FEC_RDATA1__FEC_RDATA1, + MX25_PAD_FEC_RX_DV__FEC_RX_DV, + MX25_PAD_FEC_TDATA0__FEC_TDATA0, + MX25_PAD_FEC_TDATA1__FEC_TDATA1, + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX25_PAD_FEC_TX_EN__FEC_TX_EN, + MX25_PAD_POWER_FAIL__POWER_FAIL, + MX25_PAD_A17__GPIO_2_3, + MX25_PAD_D12__GPIO_4_8, + /* UART1 */ + MX25_PAD_UART1_RXD__UART1_RXD, + MX25_PAD_UART1_TXD__UART1_TXD, + MX25_PAD_UART1_RTS__UART1_RTS, + MX25_PAD_UART1_CTS__UART1_CTS, + /* USBH2 */ + MX25_PAD_D9__USBH2_PWR, + MX25_PAD_D8__USBH2_OC, + MX25_PAD_LD0__USBH2_CLK, + MX25_PAD_LD1__USBH2_DIR, + MX25_PAD_LD2__USBH2_STP, + MX25_PAD_LD3__USBH2_NXT, + MX25_PAD_LD4__USBH2_DATA0, + MX25_PAD_LD5__USBH2_DATA1, + MX25_PAD_LD6__USBH2_DATA2, + MX25_PAD_LD7__USBH2_DATA3, + MX25_PAD_HSYNC__USBH2_DATA4, + MX25_PAD_VSYNC__USBH2_DATA5, + MX25_PAD_LSCLK__USBH2_DATA6, + MX25_PAD_OE_ACD__USBH2_DATA7, + /* i2c */ + MX25_PAD_I2C1_CLK__I2C1_CLK, + MX25_PAD_I2C1_DAT__I2C1_DAT, +}; + +static int imx25_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(imx25_pads, ARRAY_SIZE(imx25_pads)); + + writel(0x03010101, 0x53f80024); + + barebox_set_model("Freescale i.MX25 3DS"); + barebox_set_hostname("mx25-3stack"); + + imx25_add_uart0(); + return 0; +} + +console_initcall(imx25_console_init); + +static int imx25_core_setup(void) +{ + writel(0x01010103, MX25_CCM_BASE_ADDR + MX25_CCM_PCDR2); + return 0; + +} +core_initcall(imx25_core_setup); diff --git a/arch/arm/boards/freescale-mx25-3ds/Makefile b/arch/arm/boards/freescale-mx25-3ds/Makefile new file mode 100644 index 0000000..52c416e --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/Makefile @@ -0,0 +1,20 @@ +# +# (C) Copyright 2007 Juergen Beisert +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# + +lwl-y += lowlevel_init.o +obj-y += 3stack.o diff --git a/arch/arm/boards/freescale-mx25-3ds/env/bin/_update b/arch/arm/boards/freescale-mx25-3ds/env/bin/_update new file mode 100644 index 0000000..014bce3 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/freescale-mx25-3ds/env/bin/boot b/arch/arm/boards/freescale-mx25-3ds/env/bin/boot new file mode 100644 index 0000000..7bbff2d --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/env/bin/boot @@ -0,0 +1,47 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xnand ]; then + root=nand + kernel=nand +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$1 = xnor ]; then + root=nor + kernel=nor +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xnand ]; then + bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +elif [ x$root = xnor ]; then + bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +elif [ $kernel = nor ]; then + bootm /dev/nor0.kernel +else + bootm /dev/nand0.kernel.bb +fi + diff --git a/arch/arm/boards/freescale-mx25-3ds/env/bin/hush_hack b/arch/arm/boards/freescale-mx25-3ds/env/bin/hush_hack new file mode 100644 index 0000000..5fffa92 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/env/bin/hush_hack @@ -0,0 +1 @@ +nand -a /dev/nand0.* diff --git a/arch/arm/boards/freescale-mx25-3ds/env/bin/init b/arch/arm/boards/freescale-mx25-3ds/env/bin/init new file mode 100644 index 0000000..0600b9e --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/env/bin/init @@ -0,0 +1,30 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts +fi + +if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + + # Uh, oh, hush first expands wildcards and then starts executing + # commands. What a bug! + source /env/bin/hush_hack +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel nand|nor [] to update kernel into flash" + echo "type update_root nand|nor [] to update rootfs into flash" + echo + exit +fi + +boot diff --git a/arch/arm/boards/freescale-mx25-3ds/env/bin/update_kernel b/arch/arm/boards/freescale-mx25-3ds/env/bin/update_kernel new file mode 100644 index 0000000..05c822d --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/env/bin/update_kernel @@ -0,0 +1,15 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.kernel.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.kernel +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 diff --git a/arch/arm/boards/freescale-mx25-3ds/env/bin/update_root b/arch/arm/boards/freescale-mx25-3ds/env/bin/update_root new file mode 100644 index 0000000..eaf36eb --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/env/bin/update_root @@ -0,0 +1,16 @@ +#!/bin/sh + +. /env/config + +image=$uimage +if [ x$1 = xnand ]; then + part=/dev/nand0.root.bb +elif [ x$1 = xnor ]; then + part=/dev/nor0.root +else + echo "usage: $0 nor|nand [imagename]" + exit 1 +fi + +. /env/bin/_update $2 + diff --git a/arch/arm/boards/freescale-mx25-3ds/env/config b/arch/arm/boards/freescale-mx25-3ds/env/config new file mode 100644 index 0000000..a5e492e --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/env/config @@ -0,0 +1,29 @@ +#!/bin/sh + +# can be either 'net', 'nor' or 'nand'' +kernel=net +root=net + +uimage=uImage-pcm043 +jffs2=root-pcm043.jffs2 + +autoboot_timeout=3 + +nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root" +bootargs="console=ttymxc0,115200" + +nor_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)" +rootpart_nor="/dev/mtdblock3" + +nand_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),108416k(root),-(kernel1)" +rootpart_nand="/dev/mtdblock7" + +# use 'dhcp' to do dhcp in barebox and in kernel +#ip=dhcp + +# or set your networking parameters here +eth0.ipaddr=192.168.3.11 +eth0.netmask=255.255.255.0 +#eth0.gateway=a.b.c.d +eth0.serverip=192.168.3.10 +eth0.ethaddr=00:50:c2:8c:e6:0e diff --git a/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S new file mode 100644 index 0000000..4ca4c82 --- /dev/null +++ b/arch/arm/boards/freescale-mx25-3ds/lowlevel_init.S @@ -0,0 +1,229 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define writeb(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + strb r1, [r0]; + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 (IMX_PLL_PD(1) | IMX_PLL_MFD(0) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + +.section ".text_bare_init","ax" + +ARM_PPMRR: .word 0x40000015 +L2CACHE_PARAM: .word 0x00030024 +CCM_CCMR_W: .word 0x003F4208 +CCM_PDR0_W: .word 0x00801000 +MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 +MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 +PPCTL_PARAM_W: .word PPCTL_PARAM_300 +CCM_BASE_ADDR_W: .word MX25_CCM_BASE_ADDR + +.globl barebox_arm_reset_vector +barebox_arm_reset_vector: + bl arm_cpu_lowlevel_init + +#define MX25_CCM_MCR 0x64 + + ldr r0, CCM_BASE_ADDR_W + /* default CLKO to 1/32 of the ARM core */ + ldr r1, [r0, #MX25_CCM_MCR] + bic r1, r1, #0x00F00000 + bic r1, r1, #0x7F000000 + mov r2, #0x5F000000 + add r2, r2, #0x00200000 + orr r1, r1, r2 + str r1, [r0, #MX25_CCM_MCR] + + /* enable all the clocks */ + writel(0x1FFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR0) + writel(0xFFFFFFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1) + writel(0x000FDFFF, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2) + writel(0x0000FEFF, MX25_CCM_BASE_ADDR + MX25_CCM_MCR) + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #0x80000000 + bls 1f + cmp pc, #0x90000000 + bhi 1f + + b imx25_barebox_entry + +1: + ldr r0, ESDCTL_BASE_W + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + mov r12, #0x00 + mov r2, #0x1 /* mDDR */ + mov r1, #MX25_CSD0_BASE_ADDR + bl setup_sdram_bank +// cmp r3, #0x0 +// orreq r12, r12, #1 +// eorne r2, r2, #0x1 +// blne setup_sdram_bank + + ldr r3, ESDCTL_DELAY5 + str r3, [r0, #0x30] + +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND + + /* Setup a temporary stack in SRAM */ + ldr sp, =MX25_IRAM_BASE_ADDR + MX25_IRAM_SIZE - 4 + + mov r0, #0 + b imx25_barebox_boot_nand_external +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ + +ret: + b imx25_barebox_entry + +/* + * r0: control base, r1: ram bank base + * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working + */ +setup_sdram_bank: + mov r3, #0xE /* 0xA + 0x4 */ + tst r2, #0x1 + orreq r3, r3, #0x300 /* DDR2 */ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: adr r4, ESDCTL_CONFIG + tst r2, #0x1 + ldreq r3, [r4, #0x0] + ldrne r3, [r4, #0x4] + cmp r1, #MX25_CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM1_MDDR + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #MX25_CSD1_BASE_ADDR + ldr r3, ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM4_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM5_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM3_MDDR + strb r3, [r1, r4] + ldr r4, RAM_PARAM2_MDDR + strb r3, [r1, r4] + + ldr r3, ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, RAM_PARAM1_MDDR + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #MX25_CSD1_BASE_ADDR + ldr r3, ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + adr r4, RAM_PARAM6_MDDR + tst r2, #0x1 + ldreq r4, [r4, #0x0] + ldrne r4, [r4, #0x4] + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, RAM_PARAM7_MDDR + streqb r3, [r1, r4] + adr r4, RAM_PARAM3_MDDR + ldreq r4, [r4, #0x0] + ldrne r4, [r4, #0x4] + strb r3, [r1, r4] + + cmp r1, #MX25_CSD1_BASE_ADDR + ldr r3, ESDCTL_0x82226080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr + +RAM_PARAM1_MDDR: .word 0x00000400 +RAM_PARAM2_MDDR: .word 0x00000333 +RAM_PARAM3_MDDR: .word 0x02000400 + .word 0x02000000 +RAM_PARAM4_MDDR: .word 0x04000000 +RAM_PARAM5_MDDR: .word 0x06000000 +RAM_PARAM6_MDDR: .word 0x00000233 + .word 0x00000033 +RAM_PARAM7_MDDR: .word 0x02000780 +ESDCTL_0x92220000: .word 0x92210000 +ESDCTL_0xA2220000: .word 0xA2210000 +ESDCTL_0xB2220000: .word 0xB2210000 +ESDCTL_0x82226080: .word 0x82216080 +ESDCTL_CONFIG: .word 0x007FFC3F + .word 0x007FFC3F +ESDCTL_DELAY5: .word 0x00F49F00 +ESDCTL_BASE_W: .word MX25_ESDCTL_BASE_ADDR + diff --git a/arch/arm/boards/freescale-mx27-ads/Makefile b/arch/arm/boards/freescale-mx27-ads/Makefile new file mode 100644 index 0000000..398db9b --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/Makefile @@ -0,0 +1,3 @@ + +lwl-y += lowlevel_init.o +obj-y += imx27ads.o diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/_update b/arch/arm/boards/freescale-mx27-ads/env/bin/_update new file mode 100644 index 0000000..014bce3 --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/env/bin/_update @@ -0,0 +1,36 @@ +#!/bin/sh + +if [ -z "$part" -o -z "$image" ]; then + echo "define \$part and \$image" + exit 1 +fi + +if [ ! -e "$part" ]; then + echo "Partition $part does not exist" + exit 1 +fi + +if [ $# = 1 ]; then + image=$1 +fi + +if [ x$ip = xdhcp ]; then + dhcp +fi + +ping $eth0.serverip +if [ $? -ne 0 ] ; then + echo "update aborted" + exit 1 +fi + +unprotect $part + +echo +echo "erasing partition $part" +erase $part + +echo +echo "flashing $image to $part" +echo +tftp $image $part diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/boot b/arch/arm/boards/freescale-mx27-ads/env/bin/boot new file mode 100644 index 0000000..3859dc1 --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/env/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xflash ]; then + root=flash + kernel=flash +fi + +if [ x$1 = xnet ]; then + root=net + kernel=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +else + bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$root = xflash ]; then + bootargs="$bootargs root=$rootpart rootfstype=jffs2" +else + bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" +fi + +bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" + +if [ $kernel = net ]; then + if [ x$ip = xdhcp ]; then + dhcp + fi + tftp $uimage uImage || exit 1 + bootm uImage +else + bootm /dev/nor0.kernel +fi + diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/init b/arch/arm/boards/freescale-mx27-ads/env/bin/init new file mode 100644 index 0000000..48e2139 --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/env/bin/init @@ -0,0 +1,20 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config +addpart /dev/nor0 $mtdparts + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + echo + echo "type update_kernel [] to update kernel into flash" + echo "type udate_root [] to update rootfs into flash" + echo + exit +fi + +boot \ No newline at end of file diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel b/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel new file mode 100644 index 0000000..1ad95fc --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/env/bin/update_kernel @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$uimage +part=/dev/nor0.kernel + +. /env/bin/_update $1 diff --git a/arch/arm/boards/freescale-mx27-ads/env/bin/update_root b/arch/arm/boards/freescale-mx27-ads/env/bin/update_root new file mode 100644 index 0000000..b757a5b --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/env/bin/update_root @@ -0,0 +1,8 @@ +#!/bin/sh + +. /env/config + +image=$jffs2 +part=/dev/nor0.root + +. /env/bin/_update $1 diff --git a/arch/arm/boards/freescale-mx27-ads/env/config b/arch/arm/boards/freescale-mx27-ads/env/config new file mode 100644 index 0000000..f18a86b --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/env/config @@ -0,0 +1,25 @@ +#!/bin/sh + +# can be either 'net' or 'flash' +kernel=net +root=net + +# use 'dhcp' todo dhcp in barebox and in kernel +ip=dhcp + +eth0.ipaddr=192.168.23.164 +eth0.netmask=255.255.255.0 +eth0.gateway=192.168.23.2 +eth0.serverip=192.168.23.2 + +uimage=uImage-mx27ads +jffs2=root-mx27ads.jffs2 + +autoboot_timeout=3 + +nfsroot="/tmp/imx27ads" +bootargs="console=ttymxc0,115200" + +mtdparts="128k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" +rootpart="/dev/mtdblock3" + diff --git a/arch/arm/boards/freescale-mx27-ads/imx27ads.c b/arch/arm/boards/freescale-mx27-ads/imx27ads.c new file mode 100644 index 0000000..9fb1760 --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/imx27ads.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct fec_platform_data fec_info = { + .xcv_type = PHY_INTERFACE_MODE_MII, + .phy_addr = 1, +}; + +static int imx27ads_timing_init(void) +{ + /* configure cpld on cs4 */ + imx27_setup_weimcs(4, 0x0000DCF6, 0x444A4541, 0x44443302); + + /* configure synchronous mode for + * 16 bit nor flash on cs0 */ + imx27_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800); + + writew(0x00f0, 0xc0000000); + writew(0x00aa, 0xc0000aaa); + writew(0x0055, 0xc0000554); + writew(0x00d0, 0xc0000aaa); + writew(0x66ca, 0xc0000aaa); + writew(0x00f0, 0xc0000000); + + imx27_setup_weimcs(0, 0x23524E80, 0x10000D03, 0x00720900); + + /* Select FEC data through data path */ + writew(0x0020, MX27_CS4_BASE_ADDR + 0x10); + + /* Enable CPLD FEC data path */ + writew(0x0010, MX27_CS4_BASE_ADDR + 0x14); + + return 0; +} + +core_initcall(imx27ads_timing_init); + +static int mx27ads_devices_init(void) +{ + int i; + unsigned int mode[] = { + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + }; + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); + + imx27_add_fec(&fec_info); + devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + + armlinux_set_architecture(MACH_TYPE_MX27ADS); + + return 0; +} + +device_initcall(mx27ads_devices_init); + +static int mx27ads_console_init(void) +{ + barebox_set_model("Freescale i.MX27 ADS"); + barebox_set_hostname("mx27ads"); + + imx27_add_uart0(); + return 0; +} + +console_initcall(mx27ads_console_init); + diff --git a/arch/arm/boards/freescale-mx27-ads/imx27ads.dox b/arch/arm/boards/freescale-mx27-ads/imx27ads.dox new file mode 100644 index 0000000..e14d8e3 --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/imx27ads.dox @@ -0,0 +1,5 @@ +/** @page imx27ads Freescale i.MX27ads + +This is the Freescale evaluation board for the i.MX27 Processor + +*/ diff --git a/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S new file mode 100644 index 0000000..45f3992 --- /dev/null +++ b/arch/arm/boards/freescale-mx27-ads/lowlevel_init.S @@ -0,0 +1,112 @@ +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + */ + +#include +#include +#include + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0)) + +.macro sdram_init + /* + * DDR on CSD0 + */ + writel(0x00000008, 0xD8001010) + writel(0x55555555, 0x10027828) + writel(0x55555555, 0x10027830) + writel(0x55555555, 0x10027834) + writel(0x00005005, 0x10027838) + writel(0x15555555, 0x1002783C) + writel(0x00000004, 0xD8001010) + writel(0x006ac73a, 0xD8001004) + writel(0x92100000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0xA2100000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0xA2200000, 0xD8001000) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0x00000000, 0xA0000F00) + writel(0xb2100000, 0xD8001000) + ldr r0, =0xA0000033 + mov r1, #0xda + strb r1, [r0] + ldr r0, =0xA1000000 + mov r1, #0xff + strb r1, [r0] + writel(0x82226080, 0xD8001000) +.endm + +.globl barebox_arm_reset_vector +barebox_arm_reset_vector: + + bl arm_cpu_lowlevel_init + + /* ahb lite ip interface */ + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) + + /* disable mpll/spll */ + ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR + ldr r1, [r0] + bic r1, r1, #0x03 + str r1, [r0] + + /* + * pll clock initialization - see section 3.4.3 of the i.MX27 manual + * + * FIXME: Using the 399*2 MHz values from table 3-8 doens't work + * with 1.2 V core voltage! Find out if this is + * documented somewhere. + */ + writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */ + writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */ + + /* + * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz + * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz + * System clock (HCLK) = 133 MHz + */ + writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, + MX27_CCM_BASE_ADDR + MX27_CSCR) + + /* add some delay here */ + mov r1, #0x1000 +1: subs r1, r1, #0x1 + bne 1b + + /* clock gating enable */ + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) + + /* peripheral clock divider */ + /* FIXME */ + writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0) + /* PERDIV1=08 @133 MHz */ + /* PERDIV1=04 @266 MHz */ + writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1) + /* skip sdram initialization if we run from ram */ + cmp pc, #0xa0000000 + bls 1f + cmp pc, #0xc0000000 + bhi 1f + + b imx27_barebox_entry +1: + sdram_init + + b imx27_barebox_entry + diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c deleted file mode 100644 index dbd1c7a..0000000 --- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * 2009 Marc Kleine-Budde, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Derived from: - * - * * mx35_3stack.c - board file for uboot-v1 - * Copyright (C) 2007, Guennadi Liakhovetski - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - - -/* Board rev for the PDK 3stack */ -#define MX35PDK_BOARD_REV_1 0 -#define MX35PDK_BOARD_REV_2 1 - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 0x1F, -}; - -struct imx_nand_platform_data nand_info = { - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("mc13892", 0x08), - }, { - I2C_BOARD_INFO("mc9sdz60", 0x69), - }, -}; - -/* - * Generic display, shipped with the PDK - */ -static struct fb_videomode CTP_CLAA070LC0ACW = { - /* 800x480 @ 60 Hz */ - .name = "CTP-CLAA070LC0ACW", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = KHZ2PICOS(27000), - .left_margin = 50, - .right_margin = 50, /* whole line should have 900 clocks */ - .upper_margin = 10, - .lower_margin = 10, /* whole frame should have 500 lines */ - .hsync_len = 1, /* note: DE only display */ - .vsync_len = 1, /* note: DE only display */ - .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, -}; - -static struct imx_ipu_fb_platform_data ipu_fb_data = { - .mode = &CTP_CLAA070LC0ACW, - .num_modes = 1, - .bpp = 16, -}; - -/* - * Revision to be passed to kernel. The kernel provided - * by freescale relies on this. - * - * C --> CPU type - * S --> Silicon revision - * B --> Board rev - * - * 31 20 16 12 8 4 0 - * | Cmaj | Cmin | B | Smaj | Smin| - * - * e.g 0x00035120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2 -*/ -static unsigned int imx35_3ds_system_rev = 0x00035000; - -static void set_silicon_rev( int rev) -{ - imx35_3ds_system_rev = imx35_3ds_system_rev | (rev & 0xFF); -} - -static void set_board_rev(int rev) -{ - imx35_3ds_system_rev = (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; -} - -static int f3s_devices_init(void) -{ - uint32_t reg; - - /* CS0: Nor Flash */ - imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); - - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); - /* some fuses provide us vital information about connected hardware */ - if (reg & 0x20000000) - nand_info.width = 2; /* 16 bit */ - else - nand_info.width = 1; /* 8 bit */ - - /* - * This platform supports NOR and NAND - */ - imx35_add_nand(&nand_info); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0); - - switch ((reg >> 25) & 0x3) { - case 0x01: /* NAND is the source */ - devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - break; - - case 0x00: /* NOR is the source */ - devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0"); - protect_file("/dev/env0", 1); - break; - } - - set_silicon_rev(imx_silicon_revision()); - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - imx35_add_i2c0(NULL); - - imx35_add_fec(&fec_info); - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE, - IORESOURCE_MEM, NULL); - - imx35_add_mmc0(NULL); - - imx35_add_fb(&ipu_fb_data); - - armlinux_set_architecture(MACH_TYPE_MX35_3DS); - - return 0; -} - -device_initcall(f3s_devices_init); - -static int f3s_enable_display(void) -{ - /* Enable power to the LCD. (bit 6 hi.) */ - mc9sdz60_set_bits(mc9sdz60_get(), MC9SDZ60_REG_GPIO_1, 0x40, 0x40); - - return 0; -} - -late_initcall(f3s_enable_display); - -static iomux_v3_cfg_t f3s_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - - MX35_PAD_RXD1__UART1_RXD_MUX, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_CTS1__UART1_CTS, - - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - - MX35_PAD_WDOG_RST__GPIO1_6, - MX35_PAD_COMPARE__GPIO1_5, - - /* Display */ - MX35_PAD_LD0__IPU_DISPB_DAT_0, - MX35_PAD_LD1__IPU_DISPB_DAT_1, - MX35_PAD_LD2__IPU_DISPB_DAT_2, - MX35_PAD_LD3__IPU_DISPB_DAT_3, - MX35_PAD_LD4__IPU_DISPB_DAT_4, - MX35_PAD_LD5__IPU_DISPB_DAT_5, - MX35_PAD_LD6__IPU_DISPB_DAT_6, - MX35_PAD_LD7__IPU_DISPB_DAT_7, - MX35_PAD_LD8__IPU_DISPB_DAT_8, - MX35_PAD_LD9__IPU_DISPB_DAT_9, - MX35_PAD_LD10__IPU_DISPB_DAT_10, - MX35_PAD_LD11__IPU_DISPB_DAT_11, - MX35_PAD_LD12__IPU_DISPB_DAT_12, - MX35_PAD_LD13__IPU_DISPB_DAT_13, - MX35_PAD_LD14__IPU_DISPB_DAT_14, - MX35_PAD_LD15__IPU_DISPB_DAT_15, - MX35_PAD_LD16__IPU_DISPB_DAT_16, - MX35_PAD_LD17__IPU_DISPB_DAT_17, - MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, - MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, - MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, - MX35_PAD_CONTRAST__IPU_DISPB_CONTR, - MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, - MX35_PAD_D3_REV__IPU_DISPB_D3_REV, - MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, -}; - -static int f3s_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); - - barebox_set_model("Freescale i.MX35 3DS"); - barebox_set_hostname("mx35-3stack"); - - imx35_add_uart0(); - return 0; -} - -console_initcall(f3s_console_init); - -static int f3s_core_init(void) -{ - u32 reg; - - /* CS5: smc9117 */ - imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00); - - /* enable clock for I2C1 and FEC */ - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; - reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; - reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); - - /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, MX35_AIPS1_BASE_ADDR); - writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); - writel(0x77777777, MX35_AIPS2_BASE_ADDR); - writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); - reg = readl(MX35_AIPS1_BASE_ADDR + 0x50); - reg &= 0x00FFFFFF; - writel(reg, MX35_AIPS1_BASE_ADDR + 0x50); - - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); - reg = readl(MX35_AIPS2_BASE_ADDR + 0x50); - reg &= 0x00FFFFFF; - writel(reg, MX35_AIPS2_BASE_ADDR + 0x50); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup */ - - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ - - /* SGPCR - always park on last master */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ - - /* MGPCR - restore default values */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - - return 0; -} - -core_initcall(f3s_core_init); - -static int f3s_get_rev(struct mc13xxx *mc13xxx) -{ - u32 rev; - int err; - - err = mc13xxx_reg_read(mc13xxx, MC13XXX_REG_IDENTIFICATION, &rev); - if (err) - return err; - - if (rev == 0x00ffffff) - return -ENODEV; - - return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1; -} - -static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx) -{ - int err = 0; - - /* COMPARE pin (GPIO1_5) as output and set high */ - gpio_direction_output( 32*0 + 5 , 1); - - err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03); - err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01); - if (err) - printf("mc13892 Init sequence failed, the system might not be working!\n"); - - return err; -} - -static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60) -{ - int err = 0; - - err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04); - - err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00); - mdelay(200); - err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80); - - if (err) - dev_err(&mc9sdz60->client->dev, - "Init sequence failed, the system might not be working!\n"); - - return err; -} - -static int f3s_pmic_init(void) -{ - struct mc13xxx *mc13xxx; - struct mc9sdz60 *mc9sdz60; - int rev; - - mc13xxx = mc13xxx_get(); - if (!mc13xxx) { - printf("FAILED to get PMIC handle!\n"); - return 0; - } - - rev = f3s_get_rev(mc13xxx); - switch (rev) { - case MX35PDK_BOARD_REV_1: - break; - case MX35PDK_BOARD_REV_2: - f3s_pmic_init_v2(mc13xxx); - break; - default: - printf("FAILED to identify board revision!\n"); - return 0; - } - - set_board_rev(rev); - printf("i.MX35 PDK CPU board version %d.\n", rev ); - - mc9sdz60 = mc9sdz60_get(); - if (!mc9sdz60) { - printf("FAILED to get mc9sdz60 handle!\n"); - return 0; - } - - f3s_pmic_init_all(mc9sdz60); - - armlinux_set_revision(imx35_3ds_system_rev); - - return 0; -} - -late_initcall(f3s_pmic_init); diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.dox b/arch/arm/boards/freescale-mx35-3-stack/3stack.dox deleted file mode 100644 index 15c5b6e..0000000 --- a/arch/arm/boards/freescale-mx35-3-stack/3stack.dox +++ /dev/null @@ -1,4 +0,0 @@ -/** @page the3stack Freescale MX35 3-Stack Board - - -*/ diff --git a/arch/arm/boards/freescale-mx35-3-stack/Makefile b/arch/arm/boards/freescale-mx35-3-stack/Makefile deleted file mode 100644 index a1110c2..0000000 --- a/arch/arm/boards/freescale-mx35-3-stack/Makefile +++ /dev/null @@ -1,4 +0,0 @@ - -obj-y += 3stack.o -lwl-y += lowlevel_init.o -lwl-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o diff --git a/arch/arm/boards/freescale-mx35-3-stack/board-mx35_3stack.h b/arch/arm/boards/freescale-mx35-3-stack/board-mx35_3stack.h deleted file mode 100644 index 3bcb470..0000000 --- a/arch/arm/boards/freescale-mx35-3-stack/board-mx35_3stack.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * (C) Copyright 2008 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __BOARD_MX35_3STACK_H -#define __BOARD_MX35_3STACK_H - -#define UNALIGNED_ACCESS_ENABLE -#define LOW_INT_LATENCY_ENABLE -#define BRANCH_PREDICTION_ENABLE - -#define L2CC_AUX_CTL_CONFIG 0x00030024 - -#define AIPS_MPR_CONFIG 0x77777777 -#define AIPS_OPACR_CONFIG 0x00000000 - -/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_MPR_CONFIG 0x00302154 -/* SGPCR - always park on last master */ -#define MAX_SGPCR_CONFIG 0x00000010 -/* MGPCR - restore default values */ -#define MAX_MGPCR_CONFIG 0x00000000 - -/* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ -#define M3IF_CONFIG 0x00000040 - -#define DBG_BASE_ADDR WEIM_CTRL_CS5 -#define DBG_CSCR_U_CONFIG 0x0000D843 -#define DBG_CSCR_L_CONFIG 0x22252521 -#define DBG_CSCR_A_CONFIG 0x22220A00 - -#define CCM_CCMR_CONFIG 0x003F4208 -#define CCM_PDR0_CONFIG 0x00821000 - -#define PLL_BRM_OFFSET 31 -#define PLL_PD_OFFSET 26 -#define PLL_MFD_OFFSET 16 -#define PLL_MFI_OFFSET 10 - -#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) -#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) -#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) -#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) -#define _PLL_MFN(x) (x) -#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ - (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ - _PLL_MFN(mfn)) - -#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) -#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) -#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) - -/*MEMORY SETING*/ -#define ESDCTL_0x92220000 0x92220000 -#define ESDCTL_0xA2220000 0xA2220000 -#define ESDCTL_0xB2220000 0xB2220000 -#define ESDCTL_0x82228080 0x82228080 - -#define ESDCTL_PRECHARGE 0x00000400 - -#define ESDCTL_MDDR_CONFIG 0x007FFC3F -#define ESDCTL_MDDR_MR 0x00000033 -#define ESDCTL_MDDR_EMR 0x02000000 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F -#define ESDCTL_DDR2_EMR2 0x04000000 -#define ESDCTL_DDR2_EMR3 0x06000000 -#define ESDCTL_DDR2_EN_DLL 0x02000400 -#define ESDCTL_DDR2_RESET_DLL 0x00000333 -#define ESDCTL_DDR2_MR 0x00000233 -#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 - -#define ESDCTL_DELAY_LINE5 0x00F49F00 -#endif /* __BOARD_MX35_3STACK_H */ diff --git a/arch/arm/boards/freescale-mx35-3-stack/env/config b/arch/arm/boards/freescale-mx35-3-stack/env/config deleted file mode 100644 index af2fb6b..0000000 --- a/arch/arm/boards/freescale-mx35-3-stack/env/config +++ /dev/null @@ -1,51 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttymxc0,115200" - -nor_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nor=3 - -nand_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nand=7 -nand_device=mxc_nand - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c b/arch/arm/boards/freescale-mx35-3-stack/flash_header.c deleted file mode 100644 index 076b816..0000000 --- a/arch/arm/boards/freescale-mx35-3-stack/flash_header.c +++ /dev/null @@ -1,72 +0,0 @@ -#include -#include -#include -#include - -void __naked __flash_header_start go(void) -{ - barebox_arm_head(); -} - -struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { - { .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, }, - { .ptr_type = 4, .addr = 0xB8002054, .val = 0x22252521, }, - { .ptr_type = 4, .addr = 0xB8002058, .val = 0x22220a00, }, - - { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, }, - { .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000030C, }, - - { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, - { .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, }, - - { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, }, - { .ptr_type = 4, .addr = 0xB8001008, .val = 0x92220000, }, - - { .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, }, - { .ptr_type = 4, .addr = 0x90000400, .val = 0x12345678, }, - - { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, }, - { .ptr_type = 4, .addr = 0xB8001008, .val = 0xA2220000, }, - - { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, - { .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, }, - - { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, - { .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, }, - - { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, }, - { .ptr_type = 4, .addr = 0xB8001008, .val = 0xB2220000, }, - - { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x90000233, .val = 0xda, }, - - { .ptr_type = 1, .addr = 0x82000780, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x92000780, .val = 0xda, }, - - { .ptr_type = 1, .addr = 0x82000400, .val = 0xda, }, - { .ptr_type = 1, .addr = 0x92000400, .val = 0xda, }, - - { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82226080, }, - { .ptr_type = 4, .addr = 0xB8001008, .val = 0x82226080, }, - - { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, - { .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, }, - - { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, }, -}; - - -struct imx_flash_header __flash_header_section flash_header = { - .app_code_jump_vector = DEST_BASE + 0x1000, - .app_code_barker = APP_CODE_BARKER, - .app_code_csf = 0, - .dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd), - .super_root_key = 0, - .dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker), - .app_dest = DEST_BASE, - .dcd_barker = DCD_BARKER, - .dcd_block_len = sizeof(dcd_entry), -}; - -unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; - diff --git a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S deleted file mode 100644 index 6d37f35..0000000 --- a/arch/arm/boards/freescale-mx35-3-stack/lowlevel_init.S +++ /dev/null @@ -1,262 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include - -#include "board-mx35_3stack.h" - -#define CSD0_BASE_ADDR 0x80000000 -#define CSD1_BASE_ADDR 0x90000000 -#define ESDCTL_BASE_ADDR 0xB8001000 - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define writeb(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - strb r1, [r0]; - -/* Assuming 24MHz input clock */ -#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) -#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) -#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) - - .section ".text_bare_init","ax" - -ARM_PPMRR: .word 0x40000015 -L2CACHE_PARAM: .word 0x00030024 -CCM_CCMR_W: .word 0x003F4208 -CCM_PDR0_W: .word 0x00001000 -MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 -MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 -PPCTL_PARAM_W: .word PPCTL_PARAM_300 -CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - - mrc 15, 0, r1, c1, c0, 0 - - mrc 15, 0, r0, c1, c0, 1 - orr r0, r0, #7 - mcr 15, 0, r0, c1, c0, 1 - - orr r1, r1, #(1 << 11) /* Flow prediction (Z) */ - orr r1, r1, #(1 << 22) /* unaligned accesses */ - orr r1, r1, #(1 << 21) /* Low Int Latency */ - - mcr 15, 0, r1, c1, c0, 0 - - mov r0, #0 - mcr 15, 0, r0, c15, c2, 4 - - /* - * Branch predicition is now enabled. Flush the BTAC to ensure a valid - * starting point. Don't flush BTAC while it is disabled to avoid - * ARM1136 erratum 408023. - */ - mov r0, #0 - mcr p15, 0, r0, c7, c5, 6 /* flush entire BTAC */ - - mov r0, #0 - mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ - mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ - mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ - - /* Also setup the Peripheral Port Remap register inside the core */ - ldr r0, ARM_PPMRR /* start from AIPS 2GB region */ - mcr p15, 0, r0, c15, c2, 4 - -/* - * End of ARM1136 init - */ - ldr r0, CCM_BASE_ADDR_W - - ldr r2, CCM_CCMR_W - str r2, [r0, #MX35_CCM_CCMR] - - ldr r3, MPCTL_PARAM_532_W /* consumer path*/ - - /* Set MPLL, arm clock and ahb clock */ - str r3, [r0, #MX35_CCM_MPCTL] - - ldr r1, PPCTL_PARAM_W - str r1, [r0, #MX35_CCM_PPCTL] - - ldr r1, CCM_PDR0_W - str r1, [r0, #MX35_CCM_PDR0] - - ldr r1, [r0, #MX35_CCM_CGR0] - orr r1, r1, #0x00300000 - str r1, [r0, #MX35_CCM_CGR0] - - ldr r1, [r0, #MX35_CCM_CGR1] - orr r1, r1, #0x00000C00 - orr r1, r1, #0x00000003 - str r1, [r0, #MX35_CCM_CGR1] - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #CSD0_BASE_ADDR - bls 1f - cmp pc, #CSD1_BASE_ADDR - bhi 1f - - b imx35_barebox_entry - -1: - ldr r0, =ESDCTL_BASE_ADDR - mov r3, #0x2000 - str r3, [r0, #0x0] - str r3, [r0, #0x8] - - /* ip(r12) has used to save lr register in upper calling */ - mov fp, lr - - /* setup bank 0 */ - mov r5, #0x00 - mov r2, #0x00 - mov r1, #MX35_CSD0_BASE_ADDR - bl setup_sdram_bank - - /* setup bank 1 */ - mov r5, #0x00 - mov r2, #0x00 - mov r1, #MX35_CSD1_BASE_ADDR - bl setup_sdram_bank - - mov lr, fp - - ldr r3, =ESDCTL_DELAY_LINE5 - str r3, [r0, #0x30] - -#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND - /* Setup a temporary stack in internal SRAM */ - ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 - - mov r0, #0 - b imx35_barebox_boot_nand_external -#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ - - b imx35_barebox_entry - -/* - * r0: ESDCTL control base, r1: sdram slot base - * r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base - */ -setup_sdram_bank: - mov r3, #0xE /* 0xA + 0x4 */ - tst r2, #0x1 - orreq r3, r3, #0x300 /* DDR2 */ - str r3, [r0, #0x10] - bic r3, r3, #0x00A - str r3, [r0, #0x10] - beq 2f - - mov r3, #0x20000 -1: subs r3, r3, #1 - bne 1b - -2: tst r2, #0x1 - ldreq r3, =ESDCTL_DDR2_CONFIG - ldrne r3, =ESDCTL_MDDR_CONFIG - cmp r1, #CSD1_BASE_ADDR - strlo r3, [r0, #0x4] - strhs r3, [r0, #0xC] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - - tst r2, #0x1 - bne skip_set_mode - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_DDR2_EMR2 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EMR3 - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_EN_DLL - strb r3, [r1, r4] - ldr r4, =ESDCTL_DDR2_RESET_DLL - strb r3, [r1, r4] - - ldr r3, =ESDCTL_0x92220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - ldr r4, =ESDCTL_PRECHARGE - strb r3, [r1, r4] - -skip_set_mode: - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0xA2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - mov r3, #0xDA - strb r3, [r1] - strb r3, [r1] - - ldr r3, =ESDCTL_0xB2220000 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - tst r2, #0x1 - ldreq r4, =ESDCTL_DDR2_MR - ldrne r4, =ESDCTL_MDDR_MR - mov r3, #0xDA - strb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT - streqb r3, [r1, r4] - ldreq r4, =ESDCTL_DDR2_EN_DLL - ldrne r4, =ESDCTL_MDDR_EMR - strb r3, [r1, r4] - - cmp r1, #CSD1_BASE_ADDR - ldr r3, =ESDCTL_0x82228080 - strlo r3, [r0, #0x0] - strhs r3, [r0, #0x8] - - tst r2, #0x1 - moveq r4, #0x20000 - movne r4, #0x200 -1: subs r4, r4, #1 - bne 1b - - str r3, [r1, #0x100] - ldr r4, [r1, #0x100] - cmp r3, r4 - movne r3, #1 - moveq r3, #0 - - mov pc, lr diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.c b/arch/arm/boards/freescale-mx35-3ds/3stack.c new file mode 100644 index 0000000..dbd1c7a --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3ds/3stack.c @@ -0,0 +1,432 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * 2009 Marc Kleine-Budde, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * Derived from: + * + * * mx35_3stack.c - board file for uboot-v1 + * Copyright (C) 2007, Guennadi Liakhovetski + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +/* Board rev for the PDK 3stack */ +#define MX35PDK_BOARD_REV_1 0 +#define MX35PDK_BOARD_REV_2 1 + +static struct fec_platform_data fec_info = { + .xcv_type = PHY_INTERFACE_MODE_MII, + .phy_addr = 0x1F, +}; + +struct imx_nand_platform_data nand_info = { + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("mc13892", 0x08), + }, { + I2C_BOARD_INFO("mc9sdz60", 0x69), + }, +}; + +/* + * Generic display, shipped with the PDK + */ +static struct fb_videomode CTP_CLAA070LC0ACW = { + /* 800x480 @ 60 Hz */ + .name = "CTP-CLAA070LC0ACW", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(27000), + .left_margin = 50, + .right_margin = 50, /* whole line should have 900 clocks */ + .upper_margin = 10, + .lower_margin = 10, /* whole frame should have 500 lines */ + .hsync_len = 1, /* note: DE only display */ + .vsync_len = 1, /* note: DE only display */ + .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct imx_ipu_fb_platform_data ipu_fb_data = { + .mode = &CTP_CLAA070LC0ACW, + .num_modes = 1, + .bpp = 16, +}; + +/* + * Revision to be passed to kernel. The kernel provided + * by freescale relies on this. + * + * C --> CPU type + * S --> Silicon revision + * B --> Board rev + * + * 31 20 16 12 8 4 0 + * | Cmaj | Cmin | B | Smaj | Smin| + * + * e.g 0x00035120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2 +*/ +static unsigned int imx35_3ds_system_rev = 0x00035000; + +static void set_silicon_rev( int rev) +{ + imx35_3ds_system_rev = imx35_3ds_system_rev | (rev & 0xFF); +} + +static void set_board_rev(int rev) +{ + imx35_3ds_system_rev = (imx35_3ds_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +static int f3s_devices_init(void) +{ + uint32_t reg; + + /* CS0: Nor Flash */ + imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); + + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); + /* some fuses provide us vital information about connected hardware */ + if (reg & 0x20000000) + nand_info.width = 2; /* 16 bit */ + else + nand_info.width = 1; /* 8 bit */ + + /* + * This platform supports NOR and NAND + */ + imx35_add_nand(&nand_info); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0); + + switch ((reg >> 25) & 0x3) { + case 0x01: /* NAND is the source */ + devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + break; + + case 0x00: /* NOR is the source */ + devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + break; + } + + set_silicon_rev(imx_silicon_revision()); + + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + imx35_add_i2c0(NULL); + + imx35_add_fec(&fec_info); + add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE, + IORESOURCE_MEM, NULL); + + imx35_add_mmc0(NULL); + + imx35_add_fb(&ipu_fb_data); + + armlinux_set_architecture(MACH_TYPE_MX35_3DS); + + return 0; +} + +device_initcall(f3s_devices_init); + +static int f3s_enable_display(void) +{ + /* Enable power to the LCD. (bit 6 hi.) */ + mc9sdz60_set_bits(mc9sdz60_get(), MC9SDZ60_REG_GPIO_1, 0x40, 0x40); + + return 0; +} + +late_initcall(f3s_enable_display); + +static iomux_v3_cfg_t f3s_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + + MX35_PAD_RXD1__UART1_RXD_MUX, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_CTS1__UART1_CTS, + + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA, + + MX35_PAD_WDOG_RST__GPIO1_6, + MX35_PAD_COMPARE__GPIO1_5, + + /* Display */ + MX35_PAD_LD0__IPU_DISPB_DAT_0, + MX35_PAD_LD1__IPU_DISPB_DAT_1, + MX35_PAD_LD2__IPU_DISPB_DAT_2, + MX35_PAD_LD3__IPU_DISPB_DAT_3, + MX35_PAD_LD4__IPU_DISPB_DAT_4, + MX35_PAD_LD5__IPU_DISPB_DAT_5, + MX35_PAD_LD6__IPU_DISPB_DAT_6, + MX35_PAD_LD7__IPU_DISPB_DAT_7, + MX35_PAD_LD8__IPU_DISPB_DAT_8, + MX35_PAD_LD9__IPU_DISPB_DAT_9, + MX35_PAD_LD10__IPU_DISPB_DAT_10, + MX35_PAD_LD11__IPU_DISPB_DAT_11, + MX35_PAD_LD12__IPU_DISPB_DAT_12, + MX35_PAD_LD13__IPU_DISPB_DAT_13, + MX35_PAD_LD14__IPU_DISPB_DAT_14, + MX35_PAD_LD15__IPU_DISPB_DAT_15, + MX35_PAD_LD16__IPU_DISPB_DAT_16, + MX35_PAD_LD17__IPU_DISPB_DAT_17, + MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, + MX35_PAD_CONTRAST__IPU_DISPB_CONTR, + MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, + MX35_PAD_D3_REV__IPU_DISPB_D3_REV, + MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, +}; + +static int f3s_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); + + barebox_set_model("Freescale i.MX35 3DS"); + barebox_set_hostname("mx35-3stack"); + + imx35_add_uart0(); + return 0; +} + +console_initcall(f3s_console_init); + +static int f3s_core_init(void) +{ + u32 reg; + + /* CS5: smc9117 */ + imx35_setup_weimcs(5, 0x0000D843, 0x22252521, 0x22220A00); + + /* enable clock for I2C1 and FEC */ + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + reg |= 0x3 << MX35_CCM_CGR1_FEC_SHIFT; + reg |= 0x3 << MX35_CCM_CGR1_I2C1_SHIFT; + reg = writel(reg, MX35_CCM_BASE_ADDR + MX35_CCM_CGR1); + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, MX35_AIPS1_BASE_ADDR); + writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); + writel(0x77777777, MX35_AIPS2_BASE_ADDR); + writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS1_BASE_ADDR + 0x50); + reg &= 0x00FFFFFF; + writel(reg, MX35_AIPS1_BASE_ADDR + 0x50); + + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); + reg = readl(MX35_AIPS2_BASE_ADDR + 0x50); + reg &= 0x00FFFFFF; + writel(reg, MX35_AIPS2_BASE_ADDR + 0x50); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_PARAM1 0x00302154 + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x000); /* for S0 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ + + /* SGPCR - always park on last master */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ + + /* MGPCR - restore default values */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ + + return 0; +} + +core_initcall(f3s_core_init); + +static int f3s_get_rev(struct mc13xxx *mc13xxx) +{ + u32 rev; + int err; + + err = mc13xxx_reg_read(mc13xxx, MC13XXX_REG_IDENTIFICATION, &rev); + if (err) + return err; + + if (rev == 0x00ffffff) + return -ENODEV; + + return ((rev >> 6) & 0x7) ? MX35PDK_BOARD_REV_2 : MX35PDK_BOARD_REV_1; +} + +static int f3s_pmic_init_v2(struct mc13xxx *mc13xxx) +{ + int err = 0; + + /* COMPARE pin (GPIO1_5) as output and set high */ + gpio_direction_output( 32*0 + 5 , 1); + + err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_SETTING_0, 0x03, 0x03); + err |= mc13xxx_set_bits(mc13xxx, MC13892_REG_MODE_0, 0x01, 0x01); + if (err) + printf("mc13892 Init sequence failed, the system might not be working!\n"); + + return err; +} + +static int f3s_pmic_init_all(struct mc9sdz60 *mc9sdz60) +{ + int err = 0; + + err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_GPIO_1, 0x04, 0x04); + + err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x00); + mdelay(200); + err |= mc9sdz60_set_bits(mc9sdz60, MC9SDZ60_REG_RESET_1, 0x80, 0x80); + + if (err) + dev_err(&mc9sdz60->client->dev, + "Init sequence failed, the system might not be working!\n"); + + return err; +} + +static int f3s_pmic_init(void) +{ + struct mc13xxx *mc13xxx; + struct mc9sdz60 *mc9sdz60; + int rev; + + mc13xxx = mc13xxx_get(); + if (!mc13xxx) { + printf("FAILED to get PMIC handle!\n"); + return 0; + } + + rev = f3s_get_rev(mc13xxx); + switch (rev) { + case MX35PDK_BOARD_REV_1: + break; + case MX35PDK_BOARD_REV_2: + f3s_pmic_init_v2(mc13xxx); + break; + default: + printf("FAILED to identify board revision!\n"); + return 0; + } + + set_board_rev(rev); + printf("i.MX35 PDK CPU board version %d.\n", rev ); + + mc9sdz60 = mc9sdz60_get(); + if (!mc9sdz60) { + printf("FAILED to get mc9sdz60 handle!\n"); + return 0; + } + + f3s_pmic_init_all(mc9sdz60); + + armlinux_set_revision(imx35_3ds_system_rev); + + return 0; +} + +late_initcall(f3s_pmic_init); diff --git a/arch/arm/boards/freescale-mx35-3ds/3stack.dox b/arch/arm/boards/freescale-mx35-3ds/3stack.dox new file mode 100644 index 0000000..15c5b6e --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3ds/3stack.dox @@ -0,0 +1,4 @@ +/** @page the3stack Freescale MX35 3-Stack Board + + +*/ diff --git a/arch/arm/boards/freescale-mx35-3ds/Makefile b/arch/arm/boards/freescale-mx35-3ds/Makefile new file mode 100644 index 0000000..a1110c2 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3ds/Makefile @@ -0,0 +1,4 @@ + +obj-y += 3stack.o +lwl-y += lowlevel_init.o +lwl-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o diff --git a/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h new file mode 100644 index 0000000..3bcb470 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3ds/board-mx35_3stack.h @@ -0,0 +1,103 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * (C) Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __BOARD_MX35_3STACK_H +#define __BOARD_MX35_3STACK_H + +#define UNALIGNED_ACCESS_ENABLE +#define LOW_INT_LATENCY_ENABLE +#define BRANCH_PREDICTION_ENABLE + +#define L2CC_AUX_CTL_CONFIG 0x00030024 + +#define AIPS_MPR_CONFIG 0x77777777 +#define AIPS_OPACR_CONFIG 0x00000000 + +/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_MPR_CONFIG 0x00302154 +/* SGPCR - always park on last master */ +#define MAX_SGPCR_CONFIG 0x00000010 +/* MGPCR - restore default values */ +#define MAX_MGPCR_CONFIG 0x00000000 + +/* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ +#define M3IF_CONFIG 0x00000040 + +#define DBG_BASE_ADDR WEIM_CTRL_CS5 +#define DBG_CSCR_U_CONFIG 0x0000D843 +#define DBG_CSCR_L_CONFIG 0x22252521 +#define DBG_CSCR_A_CONFIG 0x22220A00 + +#define CCM_CCMR_CONFIG 0x003F4208 +#define CCM_PDR0_CONFIG 0x00821000 + +#define PLL_BRM_OFFSET 31 +#define PLL_PD_OFFSET 26 +#define PLL_MFD_OFFSET 16 +#define PLL_MFI_OFFSET 10 + +#define _PLL_BRM(x) ((x) << PLL_BRM_OFFSET) +#define _PLL_PD(x) (((x) - 1) << PLL_PD_OFFSET) +#define _PLL_MFD(x) (((x) - 1) << PLL_MFD_OFFSET) +#define _PLL_MFI(x) ((x) << PLL_MFI_OFFSET) +#define _PLL_MFN(x) (x) +#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ + (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ + _PLL_MFN(mfn)) + +#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) +#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) +#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) + +/*MEMORY SETING*/ +#define ESDCTL_0x92220000 0x92220000 +#define ESDCTL_0xA2220000 0xA2220000 +#define ESDCTL_0xB2220000 0xB2220000 +#define ESDCTL_0x82228080 0x82228080 + +#define ESDCTL_PRECHARGE 0x00000400 + +#define ESDCTL_MDDR_CONFIG 0x007FFC3F +#define ESDCTL_MDDR_MR 0x00000033 +#define ESDCTL_MDDR_EMR 0x02000000 + +#define ESDCTL_DDR2_CONFIG 0x007FFC3F +#define ESDCTL_DDR2_EMR2 0x04000000 +#define ESDCTL_DDR2_EMR3 0x06000000 +#define ESDCTL_DDR2_EN_DLL 0x02000400 +#define ESDCTL_DDR2_RESET_DLL 0x00000333 +#define ESDCTL_DDR2_MR 0x00000233 +#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780 + +#define ESDCTL_DELAY_LINE5 0x00F49F00 +#endif /* __BOARD_MX35_3STACK_H */ diff --git a/arch/arm/boards/freescale-mx35-3ds/env/config b/arch/arm/boards/freescale-mx35-3ds/env/config new file mode 100644 index 0000000..af2fb6b --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3ds/env/config @@ -0,0 +1,51 @@ +#!/bin/sh + +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=tftp +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-${global.hostname}.$rootfs_type + +kernelimage=zImage-${global.hostname} +#kernelimage=uImage-${global.hostname} +#kernelimage=Image-${global.hostname} +#kernelimage=Image-${global.hostname}.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttymxc0,115200" + +nor_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)" +rootfs_mtdblock_nor=3 + +nand_parts="256k(barebox)ro,512k(bareboxenv),4M(kernel),-(root)" +rootfs_mtdblock_nand=7 +nand_device=mxc_nand + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/freescale-mx35-3ds/flash_header.c b/arch/arm/boards/freescale-mx35-3ds/flash_header.c new file mode 100644 index 0000000..076b816 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3ds/flash_header.c @@ -0,0 +1,72 @@ +#include +#include +#include +#include + +void __naked __flash_header_start go(void) +{ + barebox_arm_head(); +} + +struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { + { .ptr_type = 4, .addr = 0xb8002050, .val = 0x0000d843, }, + { .ptr_type = 4, .addr = 0xB8002054, .val = 0x22252521, }, + { .ptr_type = 4, .addr = 0xB8002058, .val = 0x22220a00, }, + + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, }, + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000030C, }, + + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, + { .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, }, + + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, }, + { .ptr_type = 4, .addr = 0xB8001008, .val = 0x92220000, }, + + { .ptr_type = 4, .addr = 0x80000400, .val = 0x12345678, }, + { .ptr_type = 4, .addr = 0x90000400, .val = 0x12345678, }, + + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, }, + { .ptr_type = 4, .addr = 0xB8001008, .val = 0xA2220000, }, + + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, }, + + { .ptr_type = 4, .addr = 0x80000000, .val = 0x87654321, }, + { .ptr_type = 4, .addr = 0x90000000, .val = 0x87654321, }, + + { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, }, + { .ptr_type = 4, .addr = 0xB8001008, .val = 0xB2220000, }, + + { .ptr_type = 1, .addr = 0x80000233, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x90000233, .val = 0xda, }, + + { .ptr_type = 1, .addr = 0x82000780, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x92000780, .val = 0xda, }, + + { .ptr_type = 1, .addr = 0x82000400, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x92000400, .val = 0xda, }, + + { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82226080, }, + { .ptr_type = 4, .addr = 0xB8001008, .val = 0x82226080, }, + + { .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, }, + { .ptr_type = 4, .addr = 0xB800100C, .val = 0x007ffc3f, }, + + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000304, }, +}; + + +struct imx_flash_header __flash_header_section flash_header = { + .app_code_jump_vector = DEST_BASE + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, + .dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, + .dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker), + .app_dest = DEST_BASE, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof(dcd_entry), +}; + +unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; + diff --git a/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S new file mode 100644 index 0000000..6d37f35 --- /dev/null +++ b/arch/arm/boards/freescale-mx35-3ds/lowlevel_init.S @@ -0,0 +1,262 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "board-mx35_3stack.h" + +#define CSD0_BASE_ADDR 0x80000000 +#define CSD1_BASE_ADDR 0x90000000 +#define ESDCTL_BASE_ADDR 0xB8001000 + +#define writel(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + str r1, [r0]; + +#define writeb(val, reg) \ + ldr r0, =reg; \ + ldr r1, =val; \ + strb r1, [r0]; + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + + .section ".text_bare_init","ax" + +ARM_PPMRR: .word 0x40000015 +L2CACHE_PARAM: .word 0x00030024 +CCM_CCMR_W: .word 0x003F4208 +CCM_PDR0_W: .word 0x00001000 +MPCTL_PARAM_399_W: .word MPCTL_PARAM_399 +MPCTL_PARAM_532_W: .word MPCTL_PARAM_532 +PPCTL_PARAM_W: .word PPCTL_PARAM_300 +CCM_BASE_ADDR_W: .word MX35_CCM_BASE_ADDR + +.globl barebox_arm_reset_vector +barebox_arm_reset_vector: + bl arm_cpu_lowlevel_init + + mrc 15, 0, r1, c1, c0, 0 + + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #7 + mcr 15, 0, r0, c1, c0, 1 + + orr r1, r1, #(1 << 11) /* Flow prediction (Z) */ + orr r1, r1, #(1 << 22) /* unaligned accesses */ + orr r1, r1, #(1 << 21) /* Low Int Latency */ + + mcr 15, 0, r1, c1, c0, 0 + + mov r0, #0 + mcr 15, 0, r0, c15, c2, 4 + + /* + * Branch predicition is now enabled. Flush the BTAC to ensure a valid + * starting point. Don't flush BTAC while it is disabled to avoid + * ARM1136 erratum 408023. + */ + mov r0, #0 + mcr p15, 0, r0, c7, c5, 6 /* flush entire BTAC */ + + mov r0, #0 + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */ + + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + +/* + * End of ARM1136 init + */ + ldr r0, CCM_BASE_ADDR_W + + ldr r2, CCM_CCMR_W + str r2, [r0, #MX35_CCM_CCMR] + + ldr r3, MPCTL_PARAM_532_W /* consumer path*/ + + /* Set MPLL, arm clock and ahb clock */ + str r3, [r0, #MX35_CCM_MPCTL] + + ldr r1, PPCTL_PARAM_W + str r1, [r0, #MX35_CCM_PPCTL] + + ldr r1, CCM_PDR0_W + str r1, [r0, #MX35_CCM_PDR0] + + ldr r1, [r0, #MX35_CCM_CGR0] + orr r1, r1, #0x00300000 + str r1, [r0, #MX35_CCM_CGR0] + + ldr r1, [r0, #MX35_CCM_CGR1] + orr r1, r1, #0x00000C00 + orr r1, r1, #0x00000003 + str r1, [r0, #MX35_CCM_CGR1] + + /* Skip SDRAM initialization if we run from RAM */ + cmp pc, #CSD0_BASE_ADDR + bls 1f + cmp pc, #CSD1_BASE_ADDR + bhi 1f + + b imx35_barebox_entry + +1: + ldr r0, =ESDCTL_BASE_ADDR + mov r3, #0x2000 + str r3, [r0, #0x0] + str r3, [r0, #0x8] + + /* ip(r12) has used to save lr register in upper calling */ + mov fp, lr + + /* setup bank 0 */ + mov r5, #0x00 + mov r2, #0x00 + mov r1, #MX35_CSD0_BASE_ADDR + bl setup_sdram_bank + + /* setup bank 1 */ + mov r5, #0x00 + mov r2, #0x00 + mov r1, #MX35_CSD1_BASE_ADDR + bl setup_sdram_bank + + mov lr, fp + + ldr r3, =ESDCTL_DELAY_LINE5 + str r3, [r0, #0x30] + +#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND + /* Setup a temporary stack in internal SRAM */ + ldr sp, =MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 4 + + mov r0, #0 + b imx35_barebox_boot_nand_external +#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ + + b imx35_barebox_entry + +/* + * r0: ESDCTL control base, r1: sdram slot base + * r2: DDR type (0: DDR2, 1: MDDR) r3, r4: working base + */ +setup_sdram_bank: + mov r3, #0xE /* 0xA + 0x4 */ + tst r2, #0x1 + orreq r3, r3, #0x300 /* DDR2 */ + str r3, [r0, #0x10] + bic r3, r3, #0x00A + str r3, [r0, #0x10] + beq 2f + + mov r3, #0x20000 +1: subs r3, r3, #1 + bne 1b + +2: tst r2, #0x1 + ldreq r3, =ESDCTL_DDR2_CONFIG + ldrne r3, =ESDCTL_MDDR_CONFIG + cmp r1, #CSD1_BASE_ADDR + strlo r3, [r0, #0x4] + strhs r3, [r0, #0xC] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + + tst r2, #0x1 + bne skip_set_mode + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_DDR2_EMR2 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EMR3 + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_EN_DLL + strb r3, [r1, r4] + ldr r4, =ESDCTL_DDR2_RESET_DLL + strb r3, [r1, r4] + + ldr r3, =ESDCTL_0x92220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + ldr r4, =ESDCTL_PRECHARGE + strb r3, [r1, r4] + +skip_set_mode: + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0xA2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + mov r3, #0xDA + strb r3, [r1] + strb r3, [r1] + + ldr r3, =ESDCTL_0xB2220000 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + tst r2, #0x1 + ldreq r4, =ESDCTL_DDR2_MR + ldrne r4, =ESDCTL_MDDR_MR + mov r3, #0xDA + strb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT + streqb r3, [r1, r4] + ldreq r4, =ESDCTL_DDR2_EN_DLL + ldrne r4, =ESDCTL_MDDR_EMR + strb r3, [r1, r4] + + cmp r1, #CSD1_BASE_ADDR + ldr r3, =ESDCTL_0x82228080 + strlo r3, [r0, #0x0] + strhs r3, [r0, #0x8] + + tst r2, #0x1 + moveq r4, #0x20000 + movne r4, #0x200 +1: subs r4, r4, #1 + bne 1b + + str r3, [r1, #0x100] + ldr r4, [r1, #0x100] + cmp r3, r4 + movne r3, #1 + moveq r3, #0 + + mov pc, lr diff --git a/arch/arm/boards/freescale-mx51-babbage/Makefile b/arch/arm/boards/freescale-mx51-babbage/Makefile new file mode 100644 index 0000000..6252c88 --- /dev/null +++ b/arch/arm/boards/freescale-mx51-babbage/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o flash-header-imx51-babbage.dcd.o +extra-y += flash-header-imx51-babbage.dcd.S flash-header-imx51-babbage.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx51-babbage/board.c b/arch/arm/boards/freescale-mx51-babbage/board.c new file mode 100644 index 0000000..bfe5338 --- /dev/null +++ b/arch/arm/boards/freescale-mx51-babbage/board.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MX51_CCM_CACRR 0x10 + +static void babbage_power_init(void) +{ + struct mc13xxx *mc13xxx; + u32 val; + + mc13xxx = mc13xxx_get(); + if (!mc13xxx) { + printf("could not get PMIC\n"); + return; + } + + /* Write needed to Power Gate 2 register */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val); + val &= ~0x10000; + mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val); + + /* Write needed to update Charger 0 */ + mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F); + + /* power up the system first */ + mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000); + + if (imx_silicon_revision() < IMX_CHIP_REV_3_0) { + /* Set core voltage to 1.1V */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val); + val &= ~0x1f; + val |= 0x14; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); + val &= ~0x1f; + val |= 0x1a; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); + val &= ~0x1f; + val |= 0x1a; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); + } else { + /* Setup VCC (SW2) to 1.225 */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); + val &= ~0x1f; + val |= 0x19; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.2 */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); + val &= ~0x1f; + val |= 0x18; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); + } + + if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) { + /* Set switchers in PWM mode for Atlas 2.0 and lower */ + /* Setup the switcher mode for SW1 & SW2*/ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); + val &= ~0x3c0f; + val |= 0x1405; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); + val &= ~0xf0f; + val |= 0x505; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); + } else { + /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ + /* Setup the switcher mode for SW1 & SW2*/ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); + val &= ~0x3c0f; + val |= 0x2008; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); + val &= ~0xf0f; + val |= 0x808; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); + } + + /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val); + val &= ~0x34030; + val |= 0x10020; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val); + val &= ~0x1FC; + val |= 0x1F4; + mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = 0x208; + mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); + + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = 0x49249; + mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); + + udelay(200); +} + +extern char flash_header_imx51_babbage_start[]; +extern char flash_header_imx51_babbage_end[]; + +static int imx51_babbage_late_init(void) +{ + if (!of_machine_is_compatible("fsl,imx51-babbage")) + return 0; + + babbage_power_init(); + + console_flush(); + imx51_init_lowlevel(800); + clock_notifier_call_chain(); + + armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); + + imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", + BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx51_babbage_start, + flash_header_imx51_babbage_end - flash_header_imx51_babbage_start, 0); + + return 0; +} +late_initcall(imx51_babbage_late_init); diff --git a/arch/arm/boards/freescale-mx51-babbage/env/config-board b/arch/arm/boards/freescale-mx51-babbage/env/config-board new file mode 100644 index 0000000..cfc483e --- /dev/null +++ b/arch/arm/boards/freescale-mx51-babbage/env/config-board @@ -0,0 +1,7 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=babbage +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg new file mode 100644 index 0000000..bac6816 --- /dev/null +++ b/arch/arm/boards/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg @@ -0,0 +1,59 @@ +loadaddr 0x90000000 +soc imx51 +dcdofs 0x400 +wm 32 0x73fa88a0 0x00000200 +wm 32 0x73fa850c 0x000020c5 +wm 32 0x73fa8510 0x000020c5 +wm 32 0x73fa883c 0x00000002 +wm 32 0x73fa8848 0x00000002 +wm 32 0x73fa84b8 0x000000e7 +wm 32 0x73fa84bc 0x00000045 +wm 32 0x73fa84c0 0x00000045 +wm 32 0x73fa84c4 0x00000045 +wm 32 0x73fa84c8 0x00000045 +wm 32 0x73fa8820 0x00000000 +wm 32 0x73fa84a4 0x00000003 +wm 32 0x73fa84a8 0x00000003 +wm 32 0x73fa84ac 0x000000e3 +wm 32 0x73fa84b0 0x000000e3 +wm 32 0x73fa84b4 0x000000e3 +wm 32 0x73fa84cc 0x000000e3 +wm 32 0x73fa84d0 0x000000e2 +wm 32 0x73fa882c 0x00000004 +wm 32 0x73fa88a4 0x00000004 +wm 32 0x73fa88ac 0x00000004 +wm 32 0x73fa88b8 0x00000004 +wm 32 0x83fd9000 0x82a20000 +wm 32 0x83fd9008 0x82a20000 +wm 32 0x83fd9010 0x000ad0d0 +wm 32 0x83fd9004 0x3f3584ab +wm 32 0x83fd900c 0x3f3584ab +wm 32 0x83fd9014 0x04008008 +wm 32 0x83fd9014 0x0000801a +wm 32 0x83fd9014 0x0000801b +wm 32 0x83fd9014 0x00448019 +wm 32 0x83fd9014 0x07328018 +wm 32 0x83fd9014 0x04008008 +wm 32 0x83fd9014 0x00008010 +wm 32 0x83fd9014 0x00008010 +wm 32 0x83fd9014 0x06328018 +wm 32 0x83fd9014 0x03808019 +wm 32 0x83fd9014 0x00408019 +wm 32 0x83fd9014 0x00008000 +wm 32 0x83fd9014 0x0400800c +wm 32 0x83fd9014 0x0000801e +wm 32 0x83fd9014 0x0000801f +wm 32 0x83fd9014 0x0000801d +wm 32 0x83fd9014 0x0732801c +wm 32 0x83fd9014 0x0400800c +wm 32 0x83fd9014 0x00008014 +wm 32 0x83fd9014 0x00008014 +wm 32 0x83fd9014 0x0632801c +wm 32 0x83fd9014 0x0380801d +wm 32 0x83fd9014 0x0040801d +wm 32 0x83fd9014 0x00008004 +wm 32 0x83fd9000 0xb2a20000 +wm 32 0x83fd9008 0xb2a20000 +wm 32 0x83fd9010 0x000ad6d0 +wm 32 0x83fd9034 0x90000000 +wm 32 0x83fd9014 0x00000000 diff --git a/arch/arm/boards/freescale-mx51-babbage/lowlevel.c b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c new file mode 100644 index 0000000..f606011 --- /dev/null +++ b/arch/arm/boards/freescale-mx51-babbage/lowlevel.c @@ -0,0 +1,17 @@ +#include +#include +#include +#include + +extern char __dtb_imx51_babbage_start[]; + +ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx51_babbage_start - get_runtime_offset(); + + imx51_barebox_entry(fdt); +} diff --git a/arch/arm/boards/freescale-mx51-babbage/mx51-pdk.dox b/arch/arm/boards/freescale-mx51-babbage/mx51-pdk.dox new file mode 100644 index 0000000..d9ea823 --- /dev/null +++ b/arch/arm/boards/freescale-mx51-babbage/mx51-pdk.dox @@ -0,0 +1,4 @@ +/** @page board_babage Freescale i.MX51 PDK (Babbage) Board + + +*/ diff --git a/arch/arm/boards/freescale-mx51-pdk/Makefile b/arch/arm/boards/freescale-mx51-pdk/Makefile deleted file mode 100644 index 6252c88..0000000 --- a/arch/arm/boards/freescale-mx51-pdk/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += board.o flash-header-imx51-babbage.dcd.o -extra-y += flash-header-imx51-babbage.dcd.S flash-header-imx51-babbage.dcd -lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c deleted file mode 100644 index bfe5338..0000000 --- a/arch/arm/boards/freescale-mx51-pdk/board.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MX51_CCM_CACRR 0x10 - -static void babbage_power_init(void) -{ - struct mc13xxx *mc13xxx; - u32 val; - - mc13xxx = mc13xxx_get(); - if (!mc13xxx) { - printf("could not get PMIC\n"); - return; - } - - /* Write needed to Power Gate 2 register */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val); - val &= ~0x10000; - mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val); - - /* Write needed to update Charger 0 */ - mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F); - - /* power up the system first */ - mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000); - - if (imx_silicon_revision() < IMX_CHIP_REV_3_0) { - /* Set core voltage to 1.1V */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val); - val &= ~0x1f; - val |= 0x14; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val); - - /* Setup VCC (SW2) to 1.25 */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); - val &= ~0x1f; - val |= 0x1a; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.25 */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); - val &= ~0x1f; - val |= 0x1a; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); - } else { - /* Setup VCC (SW2) to 1.225 */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val); - val &= ~0x1f; - val |= 0x19; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.2 */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val); - val &= ~0x1f; - val |= 0x18; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val); - } - - if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) { - /* Set switchers in PWM mode for Atlas 2.0 and lower */ - /* Setup the switcher mode for SW1 & SW2*/ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); - val &= ~0x3c0f; - val |= 0x1405; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); - val &= ~0xf0f; - val |= 0x505; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); - } else { - /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ - /* Setup the switcher mode for SW1 & SW2*/ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val); - val &= ~0x3c0f; - val |= 0x2008; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val); - val &= ~0xf0f; - val |= 0x808; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val); - } - - /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val); - val &= ~0x34030; - val |= 0x10020; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val); - - /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val); - val &= ~0x1FC; - val |= 0x1F4; - mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val); - - /* Configure VGEN3 and VCAM regulators to use external PNP */ - val = 0x208; - mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); - - udelay(200); - - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ - val = 0x49249; - mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val); - - udelay(200); -} - -extern char flash_header_imx51_babbage_start[]; -extern char flash_header_imx51_babbage_end[]; - -static int imx51_babbage_late_init(void) -{ - if (!of_machine_is_compatible("fsl,imx51-babbage")) - return 0; - - babbage_power_init(); - - console_flush(); - imx51_init_lowlevel(800); - clock_notifier_call_chain(); - - armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); - - imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", - BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx51_babbage_start, - flash_header_imx51_babbage_end - flash_header_imx51_babbage_start, 0); - - return 0; -} -late_initcall(imx51_babbage_late_init); diff --git a/arch/arm/boards/freescale-mx51-pdk/env/config-board b/arch/arm/boards/freescale-mx51-pdk/env/config-board deleted file mode 100644 index cfc483e..0000000 --- a/arch/arm/boards/freescale-mx51-pdk/env/config-board +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.hostname=babbage -global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/freescale-mx51-pdk/flash-header-imx51-babbage.imxcfg b/arch/arm/boards/freescale-mx51-pdk/flash-header-imx51-babbage.imxcfg deleted file mode 100644 index bac6816..0000000 --- a/arch/arm/boards/freescale-mx51-pdk/flash-header-imx51-babbage.imxcfg +++ /dev/null @@ -1,59 +0,0 @@ -loadaddr 0x90000000 -soc imx51 -dcdofs 0x400 -wm 32 0x73fa88a0 0x00000200 -wm 32 0x73fa850c 0x000020c5 -wm 32 0x73fa8510 0x000020c5 -wm 32 0x73fa883c 0x00000002 -wm 32 0x73fa8848 0x00000002 -wm 32 0x73fa84b8 0x000000e7 -wm 32 0x73fa84bc 0x00000045 -wm 32 0x73fa84c0 0x00000045 -wm 32 0x73fa84c4 0x00000045 -wm 32 0x73fa84c8 0x00000045 -wm 32 0x73fa8820 0x00000000 -wm 32 0x73fa84a4 0x00000003 -wm 32 0x73fa84a8 0x00000003 -wm 32 0x73fa84ac 0x000000e3 -wm 32 0x73fa84b0 0x000000e3 -wm 32 0x73fa84b4 0x000000e3 -wm 32 0x73fa84cc 0x000000e3 -wm 32 0x73fa84d0 0x000000e2 -wm 32 0x73fa882c 0x00000004 -wm 32 0x73fa88a4 0x00000004 -wm 32 0x73fa88ac 0x00000004 -wm 32 0x73fa88b8 0x00000004 -wm 32 0x83fd9000 0x82a20000 -wm 32 0x83fd9008 0x82a20000 -wm 32 0x83fd9010 0x000ad0d0 -wm 32 0x83fd9004 0x3f3584ab -wm 32 0x83fd900c 0x3f3584ab -wm 32 0x83fd9014 0x04008008 -wm 32 0x83fd9014 0x0000801a -wm 32 0x83fd9014 0x0000801b -wm 32 0x83fd9014 0x00448019 -wm 32 0x83fd9014 0x07328018 -wm 32 0x83fd9014 0x04008008 -wm 32 0x83fd9014 0x00008010 -wm 32 0x83fd9014 0x00008010 -wm 32 0x83fd9014 0x06328018 -wm 32 0x83fd9014 0x03808019 -wm 32 0x83fd9014 0x00408019 -wm 32 0x83fd9014 0x00008000 -wm 32 0x83fd9014 0x0400800c -wm 32 0x83fd9014 0x0000801e -wm 32 0x83fd9014 0x0000801f -wm 32 0x83fd9014 0x0000801d -wm 32 0x83fd9014 0x0732801c -wm 32 0x83fd9014 0x0400800c -wm 32 0x83fd9014 0x00008014 -wm 32 0x83fd9014 0x00008014 -wm 32 0x83fd9014 0x0632801c -wm 32 0x83fd9014 0x0380801d -wm 32 0x83fd9014 0x0040801d -wm 32 0x83fd9014 0x00008004 -wm 32 0x83fd9000 0xb2a20000 -wm 32 0x83fd9008 0xb2a20000 -wm 32 0x83fd9010 0x000ad6d0 -wm 32 0x83fd9034 0x90000000 -wm 32 0x83fd9014 0x00000000 diff --git a/arch/arm/boards/freescale-mx51-pdk/lowlevel.c b/arch/arm/boards/freescale-mx51-pdk/lowlevel.c deleted file mode 100644 index f606011..0000000 --- a/arch/arm/boards/freescale-mx51-pdk/lowlevel.c +++ /dev/null @@ -1,17 +0,0 @@ -#include -#include -#include -#include - -extern char __dtb_imx51_babbage_start[]; - -ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2) -{ - uint32_t fdt; - - arm_cpu_lowlevel_init(); - - fdt = (uint32_t)__dtb_imx51_babbage_start - get_runtime_offset(); - - imx51_barebox_entry(fdt); -} diff --git a/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox b/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox deleted file mode 100644 index d9ea823..0000000 --- a/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox +++ /dev/null @@ -1,4 +0,0 @@ -/** @page board_babage Freescale i.MX51 PDK (Babbage) Board - - -*/ diff --git a/arch/arm/boards/freescale-mx53-loco/Makefile b/arch/arm/boards/freescale-mx53-loco/Makefile deleted file mode 100644 index bcaa974..0000000 --- a/arch/arm/boards/freescale-mx53-loco/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += board.o flash-header-imx53-loco.dcd.o -extra-y += flash-header-imx53-loco.dcd.S flash-header-imx53-loco.dcd -lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx53-loco/board.c b/arch/arm/boards/freescale-mx53-loco/board.c deleted file mode 100644 index 69036da..0000000 --- a/arch/arm/boards/freescale-mx53-loco/board.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * Copyright (C) 2011 Marc Kleine-Budde - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -/* - * Revision to be passed to kernel. The kernel provided - * by freescale relies on this. - * - * C --> CPU type - * S --> Silicon revision - * B --> Board rev - * - * 31 20 16 12 8 4 0 - * | Cmaj | Cmin | B | Smaj | Smin| - * - * e.g 0x00053120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2 -*/ -static unsigned int loco_system_rev = 0x00053000; - -static void set_silicon_rev( int rev) -{ - loco_system_rev = loco_system_rev | (rev & 0xFF); -} - -static void set_board_rev(int rev) -{ - loco_system_rev = (loco_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; -} - -#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) - -static void loco_fec_reset(void) -{ - gpio_direction_output(LOCO_FEC_PHY_RST, 0); - mdelay(1); - gpio_set_value(LOCO_FEC_PHY_RST, 1); -} - -#define MX53_LOCO_USB_PWREN IMX_GPIO_NR(7, 8) - -extern char flash_header_imx53_loco_start[]; -extern char flash_header_imx53_loco_end[]; - -static int loco_late_init(void) -{ - struct mc13xxx *mc34708; - int rev; - - if (!of_machine_is_compatible("fsl,imx53-qsb")) - return 0; - - device_detect_by_name("mmc0"); - - devfs_add_partition("mmc0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - - mc34708 = mc13xxx_get(); - if (mc34708) { - /* get the board revision from fuse */ - rev = readl(MX53_IIM_BASE_ADDR + 0x878); - set_board_rev(rev); - printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' ); - armlinux_set_revision(loco_system_rev); - } else { - /* so we have a DA9053 based board */ - printf("MCIMX53-START board 1.0\n"); - armlinux_set_revision(loco_system_rev); - return 0; - } - - /* USB PWR enable */ - gpio_direction_output(MX53_LOCO_USB_PWREN, 0); - gpio_set_value(MX53_LOCO_USB_PWREN, 1); - - loco_fec_reset(); - - set_silicon_rev(imx_silicon_revision()); - - armlinux_set_architecture(MACH_TYPE_MX53_LOCO); - - imx53_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", - BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx53_loco_start, - flash_header_imx53_loco_end - flash_header_imx53_loco_start, 0); - - return 0; -} -late_initcall(loco_late_init); - -static int loco_postcore_init(void) -{ - if (!of_machine_is_compatible("fsl,imx53-qsb")) - return 0; - - imx53_init_lowlevel(1000); - - return 0; -} -postcore_initcall(loco_postcore_init); diff --git a/arch/arm/boards/freescale-mx53-loco/env/config-board b/arch/arm/boards/freescale-mx53-loco/env/config-board deleted file mode 100644 index a6cf69d..0000000 --- a/arch/arm/boards/freescale-mx53-loco/env/config-board +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.hostname=loco -global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/freescale-mx53-loco/flash-header-imx53-loco.imxcfg b/arch/arm/boards/freescale-mx53-loco/flash-header-imx53-loco.imxcfg deleted file mode 100644 index 95bcd19..0000000 --- a/arch/arm/boards/freescale-mx53-loco/flash-header-imx53-loco.imxcfg +++ /dev/null @@ -1,54 +0,0 @@ -loadaddr 0x70000000 -soc imx53 -dcdofs 0x400 -wm 32 0x53fa8554 0x00300000 -wm 32 0x53fa8558 0x00300040 -wm 32 0x53fa8560 0x00300000 -wm 32 0x53fa8564 0x00300040 -wm 32 0x53fa8568 0x00300040 -wm 32 0x53fa8570 0x00300000 -wm 32 0x53fa8574 0x00300000 -wm 32 0x53fa8578 0x00300000 -wm 32 0x53fa857c 0x00300040 -wm 32 0x53fa8580 0x00300040 -wm 32 0x53fa8584 0x00300000 -wm 32 0x53fa8588 0x00300000 -wm 32 0x53fa8590 0x00300040 -wm 32 0x53fa8594 0x00300000 -wm 32 0x53fa86f0 0x00300000 -wm 32 0x53fa86f4 0x00000000 -wm 32 0x53fa86fc 0x00000000 -wm 32 0x53fa8714 0x00000000 -wm 32 0x53fa8718 0x00300000 -wm 32 0x53fa871c 0x00300000 -wm 32 0x53fa8720 0x00300000 -wm 32 0x53fa8724 0x04000000 -wm 32 0x53fa8728 0x00300000 -wm 32 0x53fa872c 0x00300000 -wm 32 0x63fd9088 0x35343535 -wm 32 0x63fd9090 0x4d444c44 -wm 32 0x63fd907c 0x01370138 -wm 32 0x63fd9080 0x013b013c -wm 32 0x63fd9018 0x00011740 -wm 32 0x63fd9000 0xc3190000 -wm 32 0x63fd900c 0x9f5152e3 -wm 32 0x63fd9010 0xb68e8a63 -wm 32 0x63fd9014 0x01ff00db -wm 32 0x63fd902c 0x000026d2 -wm 32 0x63fd9030 0x009f0e21 -wm 32 0x63fd9008 0x12273030 -wm 32 0x63fd9004 0x0002002d -wm 32 0x63fd901c 0x00008032 -wm 32 0x63fd901c 0x00008033 -wm 32 0x63fd901c 0x00028031 -wm 32 0x63fd901c 0x052080b0 -wm 32 0x63fd901c 0x04008040 -wm 32 0x63fd901c 0x0000803a -wm 32 0x63fd901c 0x0000803b -wm 32 0x63fd901c 0x00028039 -wm 32 0x63fd901c 0x05208138 -wm 32 0x63fd901c 0x04008048 -wm 32 0x63fd9020 0x00005800 -wm 32 0x63fd9040 0x04b80003 -wm 32 0x63fd9058 0x00022227 -wm 32 0x63fd901c 0x00000000 diff --git a/arch/arm/boards/freescale-mx53-loco/lowlevel.c b/arch/arm/boards/freescale-mx53-loco/lowlevel.c deleted file mode 100644 index c9e057a..0000000 --- a/arch/arm/boards/freescale-mx53-loco/lowlevel.c +++ /dev/null @@ -1,30 +0,0 @@ -#include -#include -#include -#include - -extern char __dtb_imx53_qsb_start[]; - -ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2) -{ - uint32_t fdt; - - arm_cpu_lowlevel_init(); - - fdt = (uint32_t)__dtb_imx53_qsb_start - get_runtime_offset(); - - imx53_barebox_entry(fdt); -} - -extern char __dtb_imx53_qsrb_start[]; - -ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2) -{ - uint32_t fdt; - - arm_cpu_lowlevel_init(); - - fdt = (uint32_t)__dtb_imx53_qsrb_start - get_runtime_offset(); - - imx53_barebox_entry(fdt); -} diff --git a/arch/arm/boards/freescale-mx53-loco/mx53-pdk.dox b/arch/arm/boards/freescale-mx53-loco/mx53-pdk.dox deleted file mode 100644 index 3a2c84f..0000000 --- a/arch/arm/boards/freescale-mx53-loco/mx53-pdk.dox +++ /dev/null @@ -1,4 +0,0 @@ -/** @page board_loco Freescale i.MX53 PDK (Loco) Board - - -*/ diff --git a/arch/arm/boards/freescale-mx53-qsb/Makefile b/arch/arm/boards/freescale-mx53-qsb/Makefile new file mode 100644 index 0000000..bcaa974 --- /dev/null +++ b/arch/arm/boards/freescale-mx53-qsb/Makefile @@ -0,0 +1,3 @@ +obj-y += board.o flash-header-imx53-loco.dcd.o +extra-y += flash-header-imx53-loco.dcd.S flash-header-imx53-loco.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c new file mode 100644 index 0000000..69036da --- /dev/null +++ b/arch/arm/boards/freescale-mx53-qsb/board.c @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * Copyright (C) 2011 Marc Kleine-Budde + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +/* + * Revision to be passed to kernel. The kernel provided + * by freescale relies on this. + * + * C --> CPU type + * S --> Silicon revision + * B --> Board rev + * + * 31 20 16 12 8 4 0 + * | Cmaj | Cmin | B | Smaj | Smin| + * + * e.g 0x00053120 --> i.MX35, Cpu silicon rev 2.0, Board rev 2 +*/ +static unsigned int loco_system_rev = 0x00053000; + +static void set_silicon_rev( int rev) +{ + loco_system_rev = loco_system_rev | (rev & 0xFF); +} + +static void set_board_rev(int rev) +{ + loco_system_rev = (loco_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; +} + +#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) + +static void loco_fec_reset(void) +{ + gpio_direction_output(LOCO_FEC_PHY_RST, 0); + mdelay(1); + gpio_set_value(LOCO_FEC_PHY_RST, 1); +} + +#define MX53_LOCO_USB_PWREN IMX_GPIO_NR(7, 8) + +extern char flash_header_imx53_loco_start[]; +extern char flash_header_imx53_loco_end[]; + +static int loco_late_init(void) +{ + struct mc13xxx *mc34708; + int rev; + + if (!of_machine_is_compatible("fsl,imx53-qsb")) + return 0; + + device_detect_by_name("mmc0"); + + devfs_add_partition("mmc0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); + + mc34708 = mc13xxx_get(); + if (mc34708) { + /* get the board revision from fuse */ + rev = readl(MX53_IIM_BASE_ADDR + 0x878); + set_board_rev(rev); + printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' ); + armlinux_set_revision(loco_system_rev); + } else { + /* so we have a DA9053 based board */ + printf("MCIMX53-START board 1.0\n"); + armlinux_set_revision(loco_system_rev); + return 0; + } + + /* USB PWR enable */ + gpio_direction_output(MX53_LOCO_USB_PWREN, 0); + gpio_set_value(MX53_LOCO_USB_PWREN, 1); + + loco_fec_reset(); + + set_silicon_rev(imx_silicon_revision()); + + armlinux_set_architecture(MACH_TYPE_MX53_LOCO); + + imx53_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0", + BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx53_loco_start, + flash_header_imx53_loco_end - flash_header_imx53_loco_start, 0); + + return 0; +} +late_initcall(loco_late_init); + +static int loco_postcore_init(void) +{ + if (!of_machine_is_compatible("fsl,imx53-qsb")) + return 0; + + imx53_init_lowlevel(1000); + + return 0; +} +postcore_initcall(loco_postcore_init); diff --git a/arch/arm/boards/freescale-mx53-qsb/env/config-board b/arch/arm/boards/freescale-mx53-qsb/env/config-board new file mode 100644 index 0000000..a6cf69d --- /dev/null +++ b/arch/arm/boards/freescale-mx53-qsb/env/config-board @@ -0,0 +1,7 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=loco +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg new file mode 100644 index 0000000..95bcd19 --- /dev/null +++ b/arch/arm/boards/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg @@ -0,0 +1,54 @@ +loadaddr 0x70000000 +soc imx53 +dcdofs 0x400 +wm 32 0x53fa8554 0x00300000 +wm 32 0x53fa8558 0x00300040 +wm 32 0x53fa8560 0x00300000 +wm 32 0x53fa8564 0x00300040 +wm 32 0x53fa8568 0x00300040 +wm 32 0x53fa8570 0x00300000 +wm 32 0x53fa8574 0x00300000 +wm 32 0x53fa8578 0x00300000 +wm 32 0x53fa857c 0x00300040 +wm 32 0x53fa8580 0x00300040 +wm 32 0x53fa8584 0x00300000 +wm 32 0x53fa8588 0x00300000 +wm 32 0x53fa8590 0x00300040 +wm 32 0x53fa8594 0x00300000 +wm 32 0x53fa86f0 0x00300000 +wm 32 0x53fa86f4 0x00000000 +wm 32 0x53fa86fc 0x00000000 +wm 32 0x53fa8714 0x00000000 +wm 32 0x53fa8718 0x00300000 +wm 32 0x53fa871c 0x00300000 +wm 32 0x53fa8720 0x00300000 +wm 32 0x53fa8724 0x04000000 +wm 32 0x53fa8728 0x00300000 +wm 32 0x53fa872c 0x00300000 +wm 32 0x63fd9088 0x35343535 +wm 32 0x63fd9090 0x4d444c44 +wm 32 0x63fd907c 0x01370138 +wm 32 0x63fd9080 0x013b013c +wm 32 0x63fd9018 0x00011740 +wm 32 0x63fd9000 0xc3190000 +wm 32 0x63fd900c 0x9f5152e3 +wm 32 0x63fd9010 0xb68e8a63 +wm 32 0x63fd9014 0x01ff00db +wm 32 0x63fd902c 0x000026d2 +wm 32 0x63fd9030 0x009f0e21 +wm 32 0x63fd9008 0x12273030 +wm 32 0x63fd9004 0x0002002d +wm 32 0x63fd901c 0x00008032 +wm 32 0x63fd901c 0x00008033 +wm 32 0x63fd901c 0x00028031 +wm 32 0x63fd901c 0x052080b0 +wm 32 0x63fd901c 0x04008040 +wm 32 0x63fd901c 0x0000803a +wm 32 0x63fd901c 0x0000803b +wm 32 0x63fd901c 0x00028039 +wm 32 0x63fd901c 0x05208138 +wm 32 0x63fd901c 0x04008048 +wm 32 0x63fd9020 0x00005800 +wm 32 0x63fd9040 0x04b80003 +wm 32 0x63fd9058 0x00022227 +wm 32 0x63fd901c 0x00000000 diff --git a/arch/arm/boards/freescale-mx53-qsb/lowlevel.c b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c new file mode 100644 index 0000000..c9e057a --- /dev/null +++ b/arch/arm/boards/freescale-mx53-qsb/lowlevel.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include + +extern char __dtb_imx53_qsb_start[]; + +ENTRY_FUNCTION(start_imx53_loco, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx53_qsb_start - get_runtime_offset(); + + imx53_barebox_entry(fdt); +} + +extern char __dtb_imx53_qsrb_start[]; + +ENTRY_FUNCTION(start_imx53_loco_r, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + fdt = (uint32_t)__dtb_imx53_qsrb_start - get_runtime_offset(); + + imx53_barebox_entry(fdt); +} diff --git a/arch/arm/boards/freescale-mx53-qsb/mx53-pdk.dox b/arch/arm/boards/freescale-mx53-qsb/mx53-pdk.dox new file mode 100644 index 0000000..3a2c84f --- /dev/null +++ b/arch/arm/boards/freescale-mx53-qsb/mx53-pdk.dox @@ -0,0 +1,4 @@ +/** @page board_loco Freescale i.MX53 PDK (Loco) Board + + +*/ diff --git a/arch/arm/boards/imx21ads/Makefile b/arch/arm/boards/imx21ads/Makefile deleted file mode 100644 index a43425b..0000000 --- a/arch/arm/boards/imx21ads/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -lwl-y += lowlevel_init.o -obj-y += imx21ads.o diff --git a/arch/arm/boards/imx21ads/env/bin/init b/arch/arm/boards/imx21ads/env/bin/init deleted file mode 100644 index 224a6b4..0000000 --- a/arch/arm/boards/imx21ads/env/bin/init +++ /dev/null @@ -1 +0,0 @@ -# Dummy Init environment script diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c deleted file mode 100644 index 1bbd8cb..0000000 --- a/arch/arm/boards/imx21ads/imx21ads.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (C) 2009 Ivo Clarysse - * - * Based on imx27ads.c, - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MX21ADS_IO_REG 0xCC800000 -#define MX21ADS_IO_LCDON (1 << 9) - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, -}; - -/* Sharp LQ035Q7DB02 QVGA display */ -static struct imx_fb_videomode imx_fb_modedata = { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, - .left_margin = 6, - .right_margin = 16, - .upper_margin = 8, - .lower_margin = 10, - .hsync_len = 2, - .vsync_len = 1, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, - .pcr = 0xfb108bc7, - .bpp = 16, -}; - -static struct imx_fb_platform_data imx_fb_data = { - .mode = &imx_fb_modedata, - .num_modes = 1, - .cmap_greyscale = 0, - .cmap_inverse = 0, - .cmap_static = 0, - .pwmr = 0x00a903ff, - .lscr1 = 0x00120300, - .dmacr = 0x00020008, -}; - -static int imx21ads_timing_init(void) -{ - u32 temp; - - /* Configure External Interface Module */ - /* CS0: burst flash */ - imx21_setup_eimcs(0, 0x00003E00, 0x00000E01); - - /* CS1: Ethernet controller, external UART, memory-mapped I/O (16-bit) */ - imx21_setup_eimcs(1, 0x00002000, 0x11118501); - - /* CS2-CS5: disable */ - imx21_setup_eimcs(2, 0x0, 0x0); - imx21_setup_eimcs(3, 0x0, 0x0); - imx21_setup_eimcs(4, 0x0, 0x0); - imx21_setup_eimcs(5, 0x0, 0x0); - - temp = readl(MX21_CCM_BASE_ADDR + MX21_PCDR0); - temp &= ~0xF000; - temp |= 0xA000; /* Set NFC divider; 0xA yields 24.18MHz */ - writel(temp, MX21_CCM_BASE_ADDR + MX21_PCDR0); - - return 0; -} - -core_initcall(imx21ads_timing_init); - -static int mx21ads_mem_init(void) -{ - arm_add_mem_device("ram0", 0xc0000000, SZ_64M); - - return 0; -} -mem_initcall(mx21ads_mem_init); - -static int mx21ads_devices_init(void) -{ - int i; - unsigned int mode[] = { - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - }; - - /* initizalize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX21_CS0_BASE_ADDR, - 32 * 1024 * 1024, 0); - imx21_add_nand(&nand_info); - add_generic_device("cs8900", DEVICE_ID_DYNAMIC, NULL, - MX21_CS1_BASE_ADDR, 0x1000, - IORESOURCE_MEM, NULL); - imx21_add_fb(&imx_fb_data); - - armlinux_set_architecture(MACH_TYPE_MX21ADS); - - return 0; -} - -device_initcall(mx21ads_devices_init); - -static int mx21ads_enable_display(void) -{ - u16 tmp; - - tmp = readw(MX21ADS_IO_REG); - tmp |= MX21ADS_IO_LCDON; - writew(tmp, MX21ADS_IO_REG); - return 0; -} - -late_initcall(mx21ads_enable_display); - -static int mx21ads_console_init(void) -{ - barebox_set_model("Freescale i.MX21 ADS"); - barebox_set_hostname("mx21ads"); - - imx21_add_uart0(); - return 0; -} - -console_initcall(mx21ads_console_init); diff --git a/arch/arm/boards/imx21ads/imx21ads.dox b/arch/arm/boards/imx21ads/imx21ads.dox deleted file mode 100644 index 9f11ffa..0000000 --- a/arch/arm/boards/imx21ads/imx21ads.dox +++ /dev/null @@ -1,5 +0,0 @@ -/** @page imx21ads Freescale i.MX21ads - -This is the Freescale evaluation board for the i.MX21 Processor - -*/ diff --git a/arch/arm/boards/imx21ads/lowlevel_init.S b/arch/arm/boards/imx21ads/lowlevel_init.S deleted file mode 100644 index 471390f..0000000 --- a/arch/arm/boards/imx21ads/lowlevel_init.S +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2010 Jaccon Bastiaansen - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include - - .section ".text_bare_init","ax" - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - -/* - * Initialize the AHB-Lite IP Interface (AIPI) module (to enable access to - * on chip peripherals) as described in section 7.2 of rev3 of the i.MX21 - * reference manual. - */ - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR0 - ldr r1, =0x00040304 - str r1, [r0] - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI1_PSR1 - ldr r1, =0xfffbfcfb - str r1, [r0] - - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR0 - ldr r1, =0x3ffc0000 - str r1, [r0] - ldr r0, =MX21_AIPI_BASE_ADDR + MX21_AIPI2_PSR1 - ldr r1, =0xffffffff - str r1, [r0] - -/* - * Configure CPU core clock (266MHz), peripheral clock (133MHz) and enable - * the clock to peripherals. - */ - ldr r0, =MX21_CCM_BASE_ADDR + MX21_CSCR - ldr r1, =0x17180607 - str r1, [r0] - - ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCCR1 - ldr r1, =0x0e000000 - str r1, [r0] - - -/* - * SDRAM and SDRAM controller configuration - */ - - /* - * CSD1 not required, because the MX21ADS board only contains 64Mbyte. - * CS3 can therefore be made available. - */ - ldr r0, =MX21_SYSCTRL_BASE_ADDR + MX21_FMCR - ldr r1, =0xffffffc9 - str r1, [r0] - - /* Skip SDRAM initialization if we run from RAM */ - cmp pc, #0xc0000000 - bls 1f - cmp pc, #0xc8000000 - bhi 1f - - b ret -1: - - /* Precharge */ - ldr r0, =MX21_X_MEMC_BASE_ADDR + MX21_SDCTL0 - ldr r1, =0x92120300 - str r1, [r0] - ldr r2, =0xc0200000 - ldr r1, [r2] - - bl mem_delay - - /* Auto refresh */ - ldr r1, =0xa2120300 - str r1, [r0] - ldr r2, =0xc0000000 - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - ldr r1, [r2] - - /* Set mode register */ - ldr r1, =0xB2120300 - str r1, [r0] - ldr r1, =0xC0119800 - ldr r2, [r1] - - bl mem_delay - - /* Back to Normal Mode */ - ldr r1, =0x8212F339 - str r1, [r0] - - /* Set NFC_CLK to 24MHz */ - ldr r0, =MX21_CCM_BASE_ADDR + MX21_PCDR0 - ldr r1, =0x6419a007 - str r1, [r0] - -#ifdef CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND { - - /* Setup a temporary stack in SRAM */ - ldr sp, =MX21_IRAM_BASE_ADDR + MX21_IRAM_SIZE - 4 - - b imx21_barebox_boot_nand_external -#endif /* CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND */ - -ret: - mov r0, #0xc0000000 - mov r1, #SZ_64M - mov r2, #0 - b barebox_arm_entry - -/* - * spin for a while. we need to wait at least 200 usecs. - */ -mem_delay: - mov r4, #0x4000 -spin: subs r4, r4, #1 - bne spin - mov pc, lr - diff --git a/arch/arm/boards/imx27ads/Makefile b/arch/arm/boards/imx27ads/Makefile deleted file mode 100644 index 398db9b..0000000 --- a/arch/arm/boards/imx27ads/Makefile +++ /dev/null @@ -1,3 +0,0 @@ - -lwl-y += lowlevel_init.o -obj-y += imx27ads.o diff --git a/arch/arm/boards/imx27ads/env/bin/_update b/arch/arm/boards/imx27ads/env/bin/_update deleted file mode 100644 index 014bce3..0000000 --- a/arch/arm/boards/imx27ads/env/bin/_update +++ /dev/null @@ -1,36 +0,0 @@ -#!/bin/sh - -if [ -z "$part" -o -z "$image" ]; then - echo "define \$part and \$image" - exit 1 -fi - -if [ ! -e "$part" ]; then - echo "Partition $part does not exist" - exit 1 -fi - -if [ $# = 1 ]; then - image=$1 -fi - -if [ x$ip = xdhcp ]; then - dhcp -fi - -ping $eth0.serverip -if [ $? -ne 0 ] ; then - echo "update aborted" - exit 1 -fi - -unprotect $part - -echo -echo "erasing partition $part" -erase $part - -echo -echo "flashing $image to $part" -echo -tftp $image $part diff --git a/arch/arm/boards/imx27ads/env/bin/boot b/arch/arm/boards/imx27ads/env/bin/boot deleted file mode 100644 index 3859dc1..0000000 --- a/arch/arm/boards/imx27ads/env/bin/boot +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x$1 = xflash ]; then - root=flash - kernel=flash -fi - -if [ x$1 = xnet ]; then - root=net - kernel=net -fi - -if [ x$ip = xdhcp ]; then - bootargs="$bootargs ip=dhcp" -else - bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" -fi - -if [ x$root = xflash ]; then - bootargs="$bootargs root=$rootpart rootfstype=jffs2" -else - bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" -fi - -bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" - -if [ $kernel = net ]; then - if [ x$ip = xdhcp ]; then - dhcp - fi - tftp $uimage uImage || exit 1 - bootm uImage -else - bootm /dev/nor0.kernel -fi - diff --git a/arch/arm/boards/imx27ads/env/bin/init b/arch/arm/boards/imx27ads/env/bin/init deleted file mode 100644 index 48e2139..0000000 --- a/arch/arm/boards/imx27ads/env/bin/init +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -addpart /dev/nor0 $mtdparts - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - echo - echo "type update_kernel [] to update kernel into flash" - echo "type udate_root [] to update rootfs into flash" - echo - exit -fi - -boot \ No newline at end of file diff --git a/arch/arm/boards/imx27ads/env/bin/update_kernel b/arch/arm/boards/imx27ads/env/bin/update_kernel deleted file mode 100644 index 1ad95fc..0000000 --- a/arch/arm/boards/imx27ads/env/bin/update_kernel +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$uimage -part=/dev/nor0.kernel - -. /env/bin/_update $1 diff --git a/arch/arm/boards/imx27ads/env/bin/update_root b/arch/arm/boards/imx27ads/env/bin/update_root deleted file mode 100644 index b757a5b..0000000 --- a/arch/arm/boards/imx27ads/env/bin/update_root +++ /dev/null @@ -1,8 +0,0 @@ -#!/bin/sh - -. /env/config - -image=$jffs2 -part=/dev/nor0.root - -. /env/bin/_update $1 diff --git a/arch/arm/boards/imx27ads/env/config b/arch/arm/boards/imx27ads/env/config deleted file mode 100644 index f18a86b..0000000 --- a/arch/arm/boards/imx27ads/env/config +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh - -# can be either 'net' or 'flash' -kernel=net -root=net - -# use 'dhcp' todo dhcp in barebox and in kernel -ip=dhcp - -eth0.ipaddr=192.168.23.164 -eth0.netmask=255.255.255.0 -eth0.gateway=192.168.23.2 -eth0.serverip=192.168.23.2 - -uimage=uImage-mx27ads -jffs2=root-mx27ads.jffs2 - -autoboot_timeout=3 - -nfsroot="/tmp/imx27ads" -bootargs="console=ttymxc0,115200" - -mtdparts="128k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)" -rootpart="/dev/mtdblock3" - diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c deleted file mode 100644 index 9fb1760..0000000 --- a/arch/arm/boards/imx27ads/imx27ads.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 1, -}; - -static int imx27ads_timing_init(void) -{ - /* configure cpld on cs4 */ - imx27_setup_weimcs(4, 0x0000DCF6, 0x444A4541, 0x44443302); - - /* configure synchronous mode for - * 16 bit nor flash on cs0 */ - imx27_setup_weimcs(0, 0x0000CC03, 0xa0330D01, 0x00220800); - - writew(0x00f0, 0xc0000000); - writew(0x00aa, 0xc0000aaa); - writew(0x0055, 0xc0000554); - writew(0x00d0, 0xc0000aaa); - writew(0x66ca, 0xc0000aaa); - writew(0x00f0, 0xc0000000); - - imx27_setup_weimcs(0, 0x23524E80, 0x10000D03, 0x00720900); - - /* Select FEC data through data path */ - writew(0x0020, MX27_CS4_BASE_ADDR + 0x10); - - /* Enable CPLD FEC data path */ - writew(0x0010, MX27_CS4_BASE_ADDR + 0x14); - - return 0; -} - -core_initcall(imx27ads_timing_init); - -static int mx27ads_devices_init(void) -{ - int i; - unsigned int mode[] = { - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - }; - - /* initizalize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); - - imx27_add_fec(&fec_info); - devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - protect_file("/dev/env0", 1); - - armlinux_set_architecture(MACH_TYPE_MX27ADS); - - return 0; -} - -device_initcall(mx27ads_devices_init); - -static int mx27ads_console_init(void) -{ - barebox_set_model("Freescale i.MX27 ADS"); - barebox_set_hostname("mx27ads"); - - imx27_add_uart0(); - return 0; -} - -console_initcall(mx27ads_console_init); - diff --git a/arch/arm/boards/imx27ads/imx27ads.dox b/arch/arm/boards/imx27ads/imx27ads.dox deleted file mode 100644 index e14d8e3..0000000 --- a/arch/arm/boards/imx27ads/imx27ads.dox +++ /dev/null @@ -1,5 +0,0 @@ -/** @page imx27ads Freescale i.MX27ads - -This is the Freescale evaluation board for the i.MX27 Processor - -*/ diff --git a/arch/arm/boards/imx27ads/lowlevel_init.S b/arch/arm/boards/imx27ads/lowlevel_init.S deleted file mode 100644 index 45f3992..0000000 --- a/arch/arm/boards/imx27ads/lowlevel_init.S +++ /dev/null @@ -1,112 +0,0 @@ -/* - * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia - * Applications Processor Reference Manual, Rev. 0.2". - * - */ - -#include -#include -#include - -#define writel(val, reg) \ - ldr r0, =reg; \ - ldr r1, =val; \ - str r1, [r0]; - -#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0)) - -.macro sdram_init - /* - * DDR on CSD0 - */ - writel(0x00000008, 0xD8001010) - writel(0x55555555, 0x10027828) - writel(0x55555555, 0x10027830) - writel(0x55555555, 0x10027834) - writel(0x00005005, 0x10027838) - writel(0x15555555, 0x1002783C) - writel(0x00000004, 0xD8001010) - writel(0x006ac73a, 0xD8001004) - writel(0x92100000, 0xD8001000) - writel(0x00000000, 0xA0000F00) - writel(0xA2100000, 0xD8001000) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0xA2200000, 0xD8001000) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0x00000000, 0xA0000F00) - writel(0xb2100000, 0xD8001000) - ldr r0, =0xA0000033 - mov r1, #0xda - strb r1, [r0] - ldr r0, =0xA1000000 - mov r1, #0xff - strb r1, [r0] - writel(0x82226080, 0xD8001000) -.endm - -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - - bl arm_cpu_lowlevel_init - - /* ahb lite ip interface */ - writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0) - writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1) - writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0) - writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1) - - /* disable mpll/spll */ - ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR - ldr r1, [r0] - bic r1, r1, #0x03 - str r1, [r0] - - /* - * pll clock initialization - see section 3.4.3 of the i.MX27 manual - * - * FIXME: Using the 399*2 MHz values from table 3-8 doens't work - * with 1.2 V core voltage! Find out if this is - * documented somewhere. - */ - writel(0x00191403, MX27_CCM_BASE_ADDR + MX27_MPCTL0) /* MPLL = 199.5*2 MHz */ - writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0) /* SPLL = FIXME (needs review) */ - - /* - * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz - * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz - * System clock (HCLK) = 133 MHz - */ - writel(0x33F30307 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART, - MX27_CCM_BASE_ADDR + MX27_CSCR) - - /* add some delay here */ - mov r1, #0x1000 -1: subs r1, r1, #0x1 - bne 1b - - /* clock gating enable */ - writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR) - - /* peripheral clock divider */ - /* FIXME */ - writel(0x23C8F403, MX27_CCM_BASE_ADDR + MX27_PCDR0) - /* PERDIV1=08 @133 MHz */ - /* PERDIV1=04 @266 MHz */ - writel(0x09030913, MX27_CCM_BASE_ADDR + MX27_PCDR1) - /* skip sdram initialization if we run from ram */ - cmp pc, #0xa0000000 - bls 1f - cmp pc, #0xc0000000 - bhi 1f - - b imx27_barebox_entry -1: - sdram_init - - b imx27_barebox_entry - diff --git a/arch/arm/boards/pcm027/Makefile b/arch/arm/boards/pcm027/Makefile deleted file mode 100644 index 040cf93..0000000 --- a/arch/arm/boards/pcm027/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += board.o -lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/pcm027/board.c b/arch/arm/boards/pcm027/board.c deleted file mode 100644 index 509569e..0000000 --- a/arch/arm/boards/pcm027/board.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) 2009 Pengutronix, Sascha Hauer - * 2010 by Marc Kleine-Budde - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define PCM990_CTRL_PHYS (void *)PXA_CS1_PHYS - -#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ -#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ -#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ -#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ -#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ - -static void lcd_power(int on) -{ - void __iomem *ctrl3 = PCM990_CTRL_PHYS + PCM990_CTRL_REG3; - - if (on) - writeb(PCM990_CTRL_LCDPWR | PCM990_CTRL_LCDON, ctrl3); - else - writeb(0x0, ctrl3); -} - -static void backlight_power(int on) -{ - if (on) { - mdelay(20); - gpio_set_value(16, 1); - } else { - gpio_set_value(16, 0); - } -} - -static struct pxafb_videomode pxafb_mode = { - .mode = { - .pixclock = 28000, - .xres = 640, - .yres = 480, - .hsync_len = 20, - .left_margin = 103, - .right_margin = 47, - .vsync_len = 6, - .upper_margin = 28, - .lower_margin = 5, - .sync = 0, - }, - .bpp = 16, -}; - -static struct pxafb_platform_data fb_pdata = { - .mode = &pxafb_mode, - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, - .lcd_power = lcd_power, - .backlight_power = backlight_power, -}; - -static int pcm027_mem_init(void) -{ - arm_add_mem_device("ram0", 0xa0000000, SZ_64M); - - return 0; -} -mem_initcall(pcm027_mem_init); - -static unsigned long pin_config[] = { - /* Chip Selects */ - GPIO20_nSDCS_2, - GPIO21_nSDCS_3, - GPIO15_nCS_1, - GPIO78_nCS_2, - GPIO80_nCS_4, - - /* Variable Latency I/O Ready Pin */ - GPIO18_RDY, - - /* FFUART */ - GPIO85_nPCE_1, /* enables RX */ - GPIO34_FFUART_RXD, - GPIO35_FFUART_CTS, - GPIO36_FFUART_DCD, - GPIO37_FFUART_DSR, - GPIO38_FFUART_RI, - GPIO39_FFUART_TXD, - GPIO40_FFUART_DTR, - GPIO41_FFUART_RTS, - - /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, - MFP_CFG_OUT(GPIO16, AF0, DRIVE_LOW), /* backlight */ - - /* NIC */ - GPIO33_nCS_5, - GPIO49_nPWE, -}; - -static int pcm027_devices_init(void) -{ - void *cfi_iospace; - - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x14000300, 16, - IORESOURCE_MEM, NULL); - - cfi_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_32M); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_iospace, SZ_32M, 0); - - pxa_add_fb((void *)0x44000000, &fb_pdata); - - armlinux_set_architecture(MACH_TYPE_PCM027); - - devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env0"); - protect_file("/dev/env0", 1); - - return 0; -} - -device_initcall(pcm027_devices_init); - -static int pcm027_console_init(void) -{ - /* route pins */ - pxa2xx_mfp_config(ARRAY_AND_SIZE(pin_config)); - - /* enable clock */ - CKEN |= CKEN_FFUART; - - barebox_set_model("Phytec phyCORE-PXA270"); - barebox_set_hostname("pcm027"); - - pxa_add_uart((void *)0x40100000, 0); - - return 0; -} - -console_initcall(pcm027_console_init); diff --git a/arch/arm/boards/pcm027/config.h b/arch/arm/boards/pcm027/config.h deleted file mode 100644 index ca02b11..0000000 --- a/arch/arm/boards/pcm027/config.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (C) 2005 Phytec Messtechnik GmbH - * Juergen Kilb, H. Klaholz - * - * Copyright (C) 2006 Pengutronix - * Sascha Hauer - * Robert Schwebel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * phyCORE-PXA270 configuration settings - * Set these to 0/1 to enable or disable the features. - */ - -#define PHYCORE_PXA270_USE_K3FLASH 0 - -/* 260 MHz or 520 MHZ */ -#define PHYCORE_PXA270_SPEED 520 - -/********************************************************************* - * CONFIG PXA270 GPIO settings * - *********************************************************************/ - -/* - * GPIO set "1" - * - *** REG GPSR0 - * GP15 == nCS1 is 1 - * GP20 == nSDCS2 is 1 - * GP21 == nSDCS3 is 1 - *** REG GPSR1 - * GP33 == nCS5 is 1 - *** REG GPSR2 - * GP78 == nCS2 is 1 - * GP80 == nCS4 is 1 - */ -#define GPSR0_DFT 0x00308000 -#define GPSR1_DFT 0x00000002 -#define GPSR2_DFT 0x00014000 - -#define CONFIG_GPSR0_VAL GPSR0_DFT -#define CONFIG_GPSR1_VAL GPSR1_DFT -#define CONFIG_GPSR2_VAL GPSR2_DFT -#define CONFIG_GPSR3_VAL GPSR3_DFT - -/* - * set Direction "1" GPIO == output else input - * - ** REG GPDR0 - * GP03 == PWR_SDA is output - * GP04 == PWR_SCL is output - * GP15 == nCS1 is output - * GP20 == nSDCS2 is output - * GP21 == nSDCS3 is output - ** REG GPDR1 - * GP33 == nCS5 is output - ** REG GPDR2 - * GP78 == nCS2 is output - * GP80 == nCS4 is output - * GP90 == LED0 is output - * GP91 == LED1 is output - */ - -#define GPDR0_DFT 0x00308018 -#define GPDR1_DFT 0x00000002 -#define GPDR2_DFT 0x00014000 - -#define CONFIG_GPDR0_VAL GPDR0_DFT -#define CONFIG_GPDR1_VAL GPDR1_DFT -#define CONFIG_GPDR2_VAL GPDR2_DFT - -/* - * set Alternate Funktions - * - ** REG GAFR0_L - * GP15 == nCS1 is AF10 - ** REG GAFR0_U - * GP18 == RDY is AF01 - * GP20 == nSDCS2 is AF01 - * GP21 == nSDCS3 is AF01 - ** REG GAFR1_L - * GP33 == nCS5 is AF10 - ** REG GAFR2_L - * GP78 == nCS2 is AF10 - ** REG GAFR2_U - * GP80 == nCS4 is AF10 - */ - -#define GAFR0_L_DFT 0x80000000 -#define GAFR0_U_DFT 0x00000510 -#define GAFR1_L_DFT 0x00000008 -#define GAFR1_U_DFT 0x00000000 -#define GAFR2_L_DFT 0x20000000 -#define GAFR2_U_DFT 0x00000002 - -#define CONFIG_GAFR0_L_VAL GAFR0_L_DFT -#define CONFIG_GAFR0_U_VAL GAFR0_U_DFT -#define CONFIG_GAFR1_L_VAL GAFR1_L_DFT -#define CONFIG_GAFR1_U_VAL GAFR1_U_DFT -#define CONFIG_GAFR2_L_VAL GAFR2_L_DFT -#define CONFIG_GAFR2_U_VAL GAFR2_U_DFT - - -/* - * Power Manager Sleep Status Register (PSSR) - * - * [6] = 0 OTG pad is not holding it's state - * [5] = 1 Read Disable Hold: receivers of all gpio pins are disabled - * [4] = 1 gpio pins are held in their sleep mode state - * [3] = 0 The processor has not been placed in standby mode by - * configuring the PWRMODE register since STS was cleared - * by a reset or by software. - * [2] = 1 nVDD_FAULT has been asserted and caused the processor to - * enter deep-sleep mode. - * [1] = 1 nBATT_FAULT has been asserted and caused the processor to - * enter deep-sleep mode. - * [0] = 1 The processor was placed in sleep mode by configuring the - * PWRMODE register. - */ - -#define CONFIG_PSSR_VAL 0x37 - - -/********************************************************************* - * CONFIG PXA270 Chipselect settings * - *********************************************************************/ - -/* - * Memory settings - * - * This is the configuration for nCS1/0 -> PLD / flash - * configuration for nCS1: - * [31] 0 - Slower Device - * [30:28] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [19] 1 - 16 Bit bus width - * [18:16] 011 - burst RAM or FLASH - * configuration for nCS0 (J3 Flash): - * [15] 0 - Slower Device - * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [03] 0 - 32 Bit bus width - * [02:00] 011 - burst RAM or FLASH - */ -#if PHYCORE_PXA270_USE_K3FLASH == 0 -#define CONFIG_MSC0_VAL 0x128C1262 -#else -/* configuration for nCS0 (K3 Flash): - * [15] 0 - Slower Device - * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [03] 0 - 32 Bit bus width - * [02:00] 011 - burst RAM or FLASH - */ -#define CONFIG_MSC0_VAL 0x128C12B3 -#endif - -/* - * This is the configuration for nCS3/2 - * configuration for nCS3: POWER - * - * [31] 0 - Slower Device - * [30:28] 111 - RRR3: CS deselect to CS time: 7*(2*MemClk) = 140 ns - * [27:24] 1111 - RDN3: Address to data valid in bursts: (15+1)*MemClk = 160 ns - * [23:20] 1111 - RDF3: Address for first access: (23+1)*MemClk = 240 ns - * [19] 0 - 32 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS2: PLD - * [15] 0 - Slower Device - * [14:12] 111 - RRR2: CS deselect to CS time: 7*(2*MemClk) = 140 ns - * [11:08] 1111 - RDN2: Address to data valid in bursts: (15+1)*MemClk = 160 ns - * [07:04] 1111 - RDF2: Address for first access: (23+1)*MemClk = 240 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_MSC1_VAL 0x128c128c - -/* - * This is the configuration for nCS5/4 - * - * configuration for nCS5: LAN Controller - * [31] 0 - Slower Device - * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns - * [19] 0 - 32 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS4: USB - * [15] 0 - Slower Device - * [14:12] 111 - RRR4: CS deselect to CS time: 7*(2*MemClk) = 140 ns - * [11:08] 1111 - RDN4: Address to data valid in bursts: (15+1)*MemClk = 160 ns - * [07:04] 1111 - RDF4: Address for first access: (23+1)*MemClk = 240 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_MSC2_VAL 0x1234128C - -/********************************************************************* - * CONFIG PXA270 SDRAM settings * - *********************************************************************/ - -#define CONFIG_DRAM_BASE 0xa0000000 - - -/* MDCNFG: SDRAM Configuration Register - * - * [31] 0 - Stack1 - * [30] 0 - dcacx2 - * [20] 0 - reserved - * [31:29] 000 - reserved - * [28] 1 - SA1111 compatiblity mode - * [27] 1 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 10 - timings - * [23] 1 - internal banks in lower partition 2/3 (not used) - * [22:21] 10 - row address bits for partition 2/3 (not used) - * [20:19] 01 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15] 0 - Stack1 - * [14] 0 - dcacx0 - * [13] 0 - Stack0 - * [12] 0 - SA1110 compatiblity mode - * [11] 1 - always 1 - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk - * [7] 1 - 4 internal banks in lower partition pair - * [06:05] 10 - 13 row address bits for partition 0/1 - * [04:03] 01 - 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 0 - disable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - */ - -/* K4S561633*/ -#define CONFIG_MDCNFG_VAL 0x0AC90AC9 - -/* MDREFR: SDRAM Refresh Control Register - * - * [31] 0 - ALTREFA - * [30] 0 - ALTREFB - * [29] 1 - K0DB4 - * [28] 0 - reserved - * [27] 0 - reserved - * [26] 0 - reserved - * [25] 1 - K2FREE: not free running - * [24] 0 - K1FREE: not free running - * [23] 1 - K0FREE: not free running - * [22] 0 - SLFRSH: self refresh disabled - * [21] 0 - reserved - * [20] 0 - APD: no auto power down - * [19] 0 - K2DB2: SDCLK2 is MemClk - * [18] 0 - K2RUN: disable SDCLK2 - * [17] 0 - K1DB2: SDCLK1 is MemClk - * [16] 1 - K1RUN: enable SDCLK1 - * [15] 1 - E1PIN: SDRAM clock enable - * [14] 1 - K0DB2: SDCLK0 is MemClk - * [13] 0 - K0RUN: disable SDCLK0 - * [12] 0 - RESERVED - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 - */ -#define CONFIG_MDREFR_VAL 0x2281C018 - -/* MDMRS: Mode Register Set Configuration Register - * - * [31] 0 - reserved - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) - * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) - * [15] 0 - reserved - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. - * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. - */ -#define CONFIG_MDMRS_VAL 0x00020022 - -/********************************************************************* - * CONFIG PXA270 Clock generation * - *********************************************************************/ -#define CONFIG_FLYCNFG_VAL 0x00010001 -#define CONFIG_SXCNFG_VAL 0x40044004 -#define CONFIG_CKEN (CKEN_MEMC | CKEN_OSTIMER) - -#if PHYCORE_PXA270_SPEED == 520 -#define CONFIG_CCCR 0x00000290 /* Memory Clock is f. Table; N=2.5, L=16 => 16x13=208, 208x2,5=520 MHz */ -#elif PHYCORE_PXA270_SPEED == 260 -#define CONFIG_CCCR 0x02000288 /* Memory Clock is System-Bus Freq., N=2.5, L=8 => 8x13=104, 104x2,5=260 MHz */ -#else -#error You have specified an illegal speed. -#endif - -/********************************************************************* - * CONFIG PXA270 CF interface * - *********************************************************************/ -#define CONFIG_MECR_VAL 0x00000003 -#define CONFIG_MCMEM0_VAL 0x00010504 -#define CONFIG_MCMEM1_VAL 0x00010504 -#define CONFIG_MCATT0_VAL 0x00010504 -#define CONFIG_MCATT1_VAL 0x00010504 -#define CONFIG_MCIO0_VAL 0x00004715 -#define CONFIG_MCIO1_VAL 0x00004715 - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/pcm027/env/config b/arch/arm/boards/pcm027/env/config deleted file mode 100644 index d427800..0000000 --- a/arch/arm/boards/pcm027/env/config +++ /dev/null @@ -1,45 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyS0,115200" - -nor_parts="512k(barebox)ro,256k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nor=3 - -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/pcm027/lowlevel_init.S b/arch/arm/boards/pcm027/lowlevel_init.S deleted file mode 100644 index c7dacce..0000000 --- a/arch/arm/boards/pcm027/lowlevel_init.S +++ /dev/null @@ -1,459 +0,0 @@ -/* - * This was originally from the Lubbock u-boot port. - * - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include - -#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO <31:00> */ -#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO <63:32> */ -#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO <80:64> */ - -#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO <31:00> */ -#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO <31:0o> */ -#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO <63:32> */ -#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO <80:64> */ - -#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO <15:00> */ -#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO <31:16> */ -#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO <47:32> */ -#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO <63:48> */ -#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO <79:64> */ -#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO <95:80> */ - -/* - * Memory setup - */ -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - - @ Preserve r8/r7 i.e. kernel entry values - - @ Data cache might be active. - @ Be sure to flush kernel binary out of the cache, - @ whatever state it is, before it is turned off. - @ This is done by fetching through currently executed - @ memory to be sure we hit the same cache. - bic r2, pc, #0x1f - add r3, r2, #0x10000 @ 64 kb is quite enough... -1: ldr r0, [r2], #32 - teq r2, r3 - bne 1b - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches - - @ disabling MMU and caches - mrc p15, 0, r0, c1, c0, 0 @ read control reg - bic r0, r0, #0x05 @ clear DC, MMU - bic r0, r0, #0x1000 @ clear Icache - mcr p15, 0, r0, c1, c0, 0 - /* set output */ - ldr r0, =GPSR0 - ldr r1, =CONFIG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CONFIG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CONFIG_GPSR2_VAL - str r1, [r0] - - /* set direction */ - ldr r0, =GPDR0 - ldr r1, =CONFIG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CONFIG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CONFIG_GPDR2_VAL - str r1, [r0] - - /* alternate function */ - ldr r0, =GAFR0_L - ldr r1, =CONFIG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CONFIG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CONFIG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CONFIG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CONFIG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CONFIG_GAFR2_U_VAL - str r1, [r0] - - /* enable GPIO pins */ - ldr r0, =PSSR - ldr r1, =CONFIG_PSSR_VAL - str r1, [r0] - - /* -------------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* -------------------------------------------------------------------- */ - - /* -------------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* -------------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - cmp pc, #0xa0000000 - bls mem_init - cmp pc, #0xb0000000 - bhi mem_init - b skip_mem_init - -mem_init: - ldr r1, =MDCNFG /* get memory controller base addr. */ - - /* -------------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* -------------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CONFIG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CONFIG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CONFIG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* -------------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CONFIG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CONFIG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CONFIG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CONFIG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CONFIG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CONFIG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CONFIG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* -------------------------------------------------------------------- */ - ldr r2, =CONFIG_FLYCNFG_VAL - str r2, [r1, #FLYCNFG_OFFSET] - str r2, [r1, #FLYCNFG_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* -------------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r4, [r1, #MDREFR_OFFSET] - ldr r2, =0xFFF - bic r4, r4, r2 - - ldr r3, =CONFIG_MDREFR_VAL - and r3, r3, r2 - - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - - orr r4, r4, #MDREFR_K0RUN - orr r4, r4, #MDREFR_K0DB4 - orr r4, r4, #MDREFR_K0FREE - orr r4, r4, #MDREFR_K2FREE - orr r4, r4, #MDREFR_K0DB2 - orr r4, r4, #MDREFR_K1DB2 - bic r4, r4, #MDREFR_K1FREE - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - - /* -------------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* -------------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be - * written at this time. - */ - ldr r2, =CONFIG_SXCNFG_VAL - str r2, [r1, #SXCNFG_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* -------------------------------------------------------------------- */ - bic r4, r4, #(MDREFR_K1FREE | MDREFR_K0FREE) - - orr r4, r4, #MDREFR_K1RUN - orr r4, r4, #MDREFR_K2FREE - bic r4, r4, #MDREFR_K2DB2 - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - bic r4, r4, #MDREFR_SLFRSH - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - orr r4, r4, #MDREFR_E1PIN - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - nop - nop - - - /* - * Step 4d: write MDCNFG with MDCNFG:DEx deasserted - * (set to 0), to configure but not enable each SDRAM - * partition pair. - */ - ldr r4, =CONFIG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* - * Step 4e: Wait for the clock to the SDRAMs to stabilize, - * 100..200 usec. - */ - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200 usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - ldr r3, =CONFIG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - - /* - * Step 4g: Write MDCNFG with enable bits asserted - * (MDCNFG:DEx set to 1) - */ - ldr r3, [r1, #MDCNFG_OFFSET] - mov r4, r3 - orr r3, r3, #MDCNFG_DE0 - str r3, [r1, #MDCNFG_OFFSET] - mov r0, r3 - - /* Step 4h: Write MDMRS. */ - ldr r2, =CONFIG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - /* enable APD */ - ldr r3, [r1, #MDREFR_OFFSET] - orr r3, r3, #MDREFR_APD - str r3, [r1, #MDREFR_OFFSET] - - /* We are finished with Intel's memory controller initialisation */ -skip_mem_init: - -wakeup: - /* Are we waking from sleep? */ - ldr r0, =RCSR - ldr r1, [r0] - and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) - str r1, [r0] - teq r1, #RCSR_SMR - - bne initirqs - - ldr r0, =PSSR - mov r1, #PSSR_PH - str r1, [r0] - - /* if so, resume at PSPR */ - ldr r0, =PSPR - ldr r1, [r0] - mov pc, r1 - - /* -------------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* -------------------------------------------------------------------- */ - -initirqs: - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - /* -------------------------------------------------------------------- */ - /* Clock initialisation */ - /* -------------------------------------------------------------------- */ - -initclks: - /* Disable the peripheral clocks, and set the core clock frequency */ - - /* Turn Off on-chip peripheral clocks (except for memory) */ - /* for re-configuration. */ - ldr r1, =CKEN - ldr r2, =CONFIG_CKEN - str r2, [r1] - - /* ... and write the core clock config register */ - ldr r2, =CONFIG_CCCR - ldr r1, =CCCR - str r2, [r1] - - /* Turn on turbo mode */ - mrc p14, 0, r2, c6, c0, 0 - orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change */ - mcr p14, 0, r2, c6, c0, 0 - - /* Re-write MDREFR */ - ldr r1, =MDCNFG - ldr r2, [r1, #MDREFR_OFFSET] - str r2, [r1, #MDREFR_OFFSET] - - /* enable the 32Khz oscillator for RTC and PowerManager */ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - /* FIXME */ - -#ifdef NODEBUG - /* Disable software and data breakpoints */ - mov r0, #0 - mcr p15, 0, r0, c14, c8, 0 /* ibcr0 */ - mcr p15, 0, r0, c14, c9, 0 /* ibcr1 */ - mcr p15, 0, r0, c14, c4, 0 /* dbcon */ - - /* Enable all debug functionality */ - mov r0, #0x80000000 - mcr p14, 0, r0, c10, c0, 0 /* dcsr */ -#endif - - /* -------------------------------------------------------------------- */ - /* End lowlevel_init */ - /* -------------------------------------------------------------------- */ - -endlowlevel_init: - mov r0, #0xa0000000 - mov r1, #SZ_64M - mov r2, #0 - b barebox_arm_entry diff --git a/arch/arm/boards/pcm037/Makefile b/arch/arm/boards/pcm037/Makefile deleted file mode 100644 index 6c9ca69..0000000 --- a/arch/arm/boards/pcm037/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel.o -obj-y += pcm037.o diff --git a/arch/arm/boards/pcm037/env/boot/nand-ubi b/arch/arm/boards/pcm037/env/boot/nand-ubi deleted file mode 100644 index 67b0cb4..0000000 --- a/arch/arm/boards/pcm037/env/boot/nand-ubi +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "nand (UBI)" - exit -fi - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/pcm037/env/config-board b/arch/arm/boards/pcm037/env/config-board deleted file mode 100644 index e8e8378..0000000 --- a/arch/arm/boards/pcm037/env/config-board +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nand b/arch/arm/boards/pcm037/env/init/mtdparts-nand deleted file mode 100644 index 84220b7..0000000 --- a/arch/arm/boards/pcm037/env/init/mtdparts-nand +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - -mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" -kernelname="mxc_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm037/env/init/mtdparts-nor b/arch/arm/boards/pcm037/env/init/mtdparts-nor deleted file mode 100644 index 2ef6ead..0000000 --- a/arch/arm/boards/pcm037/env/init/mtdparts-nor +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - -mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm037/lowlevel.c b/arch/arm/boards/pcm037/lowlevel.c deleted file mode 100644 index cd894c2..0000000 --- a/arch/arm/boards/pcm037/lowlevel.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) - -void __bare_init __naked barebox_arm_reset_vector(void) -{ - uint32_t r; - volatile int v; - - arm_cpu_lowlevel_init(); - - writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); - - writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); - - for (v = 0; v < 0x4000; v++); - - writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + - MX31_CCM_CCMR); - writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, - MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); - - writel(MX31_PDR0_CSI_PODF(0xff1) | \ - MX31_PDR0_PER_PODF(7) | \ - MX31_PDR0_HSP_PODF(3) | \ - MX31_PDR0_NFC_PODF(5) | \ - MX31_PDR0_IPG_PODF(1) | \ - MX31_PDR0_MAX_PODF(3) | \ - MX31_PDR0_MCU_PODF(0), \ - MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); - - writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | - IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), - MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); - writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | - IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + - MX31_CCM_SPCTL); - - /* - * Configure IOMUXC - * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), - * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) - * (behaviour copied by sha, source unknown) - */ - writel(0, 0x43fac26c); - writel(0, 0x43fac270); - writel(0, 0x43fac274); - - writel(0x1000, 0x43fac27c); - - for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) - writel(0, r); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0xa0000000) - imx31_barebox_entry(0); - -#if defined CONFIG_PCM037_SDRAM_BANK0_128MB -#define ROWS0 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB -#define ROWS0 ESDCTL0_ROW14 -#endif - writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); - writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x12344321, MX31_CSD0_BASE_ADDR); - writel(0x12344321, MX31_CSD0_BASE_ADDR); - writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); - writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); - writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); - -#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE -#if defined CONFIG_PCM037_SDRAM_BANK1_128MB -#define ROWS1 ESDCTL0_ROW13 -#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB -#define ROWS1 ESDCTL0_ROW14 -#endif - writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1); - writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00); - writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writel(0x12344321, MX31_CSD1_BASE_ADDR); - writel(0x12344321, MX31_CSD1_BASE_ADDR); - writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33); - writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000); - writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); - writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR); - writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); -#endif - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ - arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); - - imx31_barebox_boot_nand_external(0); - } else { - imx31_barebox_entry(0); - } -} diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c deleted file mode 100644 index a1ffb2e..0000000 --- a/arch/arm/boards/pcm037/pcm037.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for Phytec's, i.MX31 based CPU card, called: PCM037 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -#ifdef CONFIG_USB -static void pcm037_usb_init(void) -{ - u32 tmp; - - /* enable clock */ - tmp = readl(0x53f80000); - tmp |= (1 << 9); - writel(tmp, 0x53f80000); - - /* Host 1 */ - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~((3 << 21) | 1); - tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184); - tmp &= ~(3 << 30); - tmp |= 2 << 30; - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184); - - imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0); - imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1); - imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2); - imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3); - imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4); - imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5); - imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6); - imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7); - imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK); - imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR); - imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT); - imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP); - - mdelay(50); - ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1); - - /* Host 2 */ - tmp = readl(MX31_IOMUXC_GPR); - tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */ - writel(tmp, MX31_IOMUXC_GPR); - - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)); - imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)); - -#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) - imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); - imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ - imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ - imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ - imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ - imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ - imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ - imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ - imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~((3 << 21) | 1); - tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584); - tmp &= ~(3 << 30); - tmp |= 2 << 30; - writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584); - - mdelay(50); - ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1); - - /* Set to Host mode */ - tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8); - writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8); - -} -#endif - -static int pcm037_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(pcm037_mmu_init); - -static struct smc911x_plat smsc9217_pdata = { - .flags = SMC911X_FORCE_INTERNAL_PHY, -}; - -static int pcm037_devices_init(void) -{ - /* CS0: Nor Flash */ - imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); - /* CS1: Network Controller */ - imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302); - /* CS4: SRAM */ - imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00); - /* CS5: SJA1000 */ - imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); - - /* - * Up to 32MiB NOR type flash, connected to - * CS line 0, data width is 16 bit - */ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); - - imx31_add_mmc0(NULL); - - /* - * Create partitions that should be - * not touched by any regular user - */ - devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */ - devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */ - - protect_file("/dev/env0", 1); - - /* - * up to 2MiB static RAM type memory, connected - * to CS4, data width is 16 bit - */ - add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */ - IORESOURCE_MEM_WRITEABLE); - imx31_add_nand(&nand_info); - - /* - * SMSC 9217 network controller - * connected to CS line 1 and interrupt line - * GPIO3, data width is 16 bit - */ - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR, - MX31_CS1_SIZE, IORESOURCE_MEM, &smsc9217_pdata); - -#ifdef CONFIG_USB - pcm037_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL); -#endif - armlinux_set_architecture(MACH_TYPE_PCM037); - - return 0; -} - -device_initcall(pcm037_devices_init); - -static unsigned int pcm037_iomux[] = { - /* UART1 */ - MX31_PIN_RXD1__RXD1, - MX31_PIN_TXD1__TXD1, - MX31_PIN_CTS1__CTS1, - MX31_PIN_RTS1__RTS1, - /* I2C */ - MX31_PIN_CSPI2_MOSI__SCL, - MX31_PIN_CSPI2_MISO__SDA, - MX31_PIN_CSPI2_SS2__I2C3_SDA, - MX31_PIN_CSPI2_SCLK__I2C3_SCL, - /* SDHC1 */ - MX31_PIN_SD1_DATA3__SD1_DATA3, - MX31_PIN_SD1_DATA2__SD1_DATA2, - MX31_PIN_SD1_DATA1__SD1_DATA1, - MX31_PIN_SD1_DATA0__SD1_DATA0, - MX31_PIN_SD1_CLK__SD1_CLK, - MX31_PIN_SD1_CMD__SD1_CMD, - IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ - IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ - /* SPI1 */ - MX31_PIN_CSPI1_MOSI__MOSI, - MX31_PIN_CSPI1_MISO__MISO, - MX31_PIN_CSPI1_SCLK__SCLK, - MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, - MX31_PIN_CSPI1_SS0__SS0, - MX31_PIN_CSPI1_SS1__SS1, - MX31_PIN_CSPI1_SS2__SS2, - /* UART2 */ - MX31_PIN_TXD2__TXD2, - MX31_PIN_RXD2__RXD2, - MX31_PIN_CTS2__CTS2, - MX31_PIN_RTS2__RTS2, - /* UART3 */ - MX31_PIN_CSPI3_MOSI__RXD3, - MX31_PIN_CSPI3_MISO__TXD3, - MX31_PIN_CSPI3_SCLK__RTS3, - MX31_PIN_CSPI3_SPI_RDY__CTS3, -}; - -static int imx31_console_init(void) -{ - imx_iomux_setup_multiple_pins(pcm037_iomux, ARRAY_SIZE(pcm037_iomux)); - - barebox_set_model("Phytec phyCORE-i.MX31"); - barebox_set_hostname("phycore-imx31"); - - imx31_add_uart0(); - return 0; -} - -console_initcall(imx31_console_init); diff --git a/arch/arm/boards/pcm037/pcm037.dox b/arch/arm/boards/pcm037/pcm037.dox deleted file mode 100644 index b2afdd6..0000000 --- a/arch/arm/boards/pcm037/pcm037.dox +++ /dev/null @@ -1,11 +0,0 @@ -/** @page pcm037 Phytec's phyCORE-i.MX31 - -This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with: - -- up to 64MiB NOR type Flash Memory -- up to 2MiB static RAM -- 64MiB NAND type Flash Memory -- SMSC 9217 network controller -- 128MiB synchronous dynamic RAM - -*/ diff --git a/arch/arm/boards/pcm038/Makefile b/arch/arm/boards/pcm038/Makefile deleted file mode 100644 index bfb55d3..0000000 --- a/arch/arm/boards/pcm038/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += pcm038.o -lwl-y += lowlevel.o -obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970.o diff --git a/arch/arm/boards/pcm038/env/boot/nand-ubi b/arch/arm/boards/pcm038/env/boot/nand-ubi deleted file mode 100644 index 67b0cb4..0000000 --- a/arch/arm/boards/pcm038/env/boot/nand-ubi +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "nand (UBI)" - exit -fi - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/pcm038/env/config-board b/arch/arm/boards/pcm038/env/config-board deleted file mode 100644 index e8e8378..0000000 --- a/arch/arm/boards/pcm038/env/config-board +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/pcm038/env/init/mtdparts-nand b/arch/arm/boards/pcm038/env/init/mtdparts-nand deleted file mode 100644 index 84220b7..0000000 --- a/arch/arm/boards/pcm038/env/init/mtdparts-nand +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - -mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" -kernelname="mxc_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm038/env/init/mtdparts-nor b/arch/arm/boards/pcm038/env/init/mtdparts-nor deleted file mode 100644 index c2c4065..0000000 --- a/arch/arm/boards/pcm038/env/init/mtdparts-nor +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - -mtdparts="512k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c deleted file mode 100644 index 4f55af8..0000000 --- a/arch/arm/boards/pcm038/lowlevel.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pll.h" - -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) - -void __bare_init __naked barebox_arm_reset_vector(void) -{ - uint32_t r; - int i; - - arm_cpu_lowlevel_init(); - - /* ahb lite ip interface */ - writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); - writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); - writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); - writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0xa0000000 && r < 0xb0000000) - goto out; - - /* re-program the PLL prior(!) starting the SDRAM controller */ - writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0); - writel(SPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_SPCTL0); - writel(CSCR_VAL | MX27_CSCR_UPDATE_DIS | MX27_CSCR_MPLL_RESTART | - MX27_CSCR_SPLL_RESTART, MX27_CCM_BASE_ADDR + MX27_CSCR); - - /* - * DDR on CSD0 - */ - /* Enable DDR SDRAM operation */ - writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - - /* Set the driving strength */ - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); - writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); - writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); - - /* Initial reset */ - writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - - /* precharge CSD0 all banks */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - for (i = 0; i < 8; i++) - writel(0, 0xa0000f00); - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - writeb(0xda, 0xa0000033); - writeb(0xff, 0xa1000000); - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* setup a stack to be able to call mx27_barebox_boot_nand_external() */ - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); - - imx27_barebox_boot_nand_external(0); - } -out: - imx27_barebox_entry(0); -} diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c deleted file mode 100644 index 1733261..0000000 --- a/arch/arm/boards/pcm038/pcm038.c +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ -#define pr_fmt(fmt) "pcm038: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "pll.h" - -#define PCM038_GPIO_PMIC_IRQ (GPIO_PORTB + 23) -#define PCM038_GPIO_FEC_RST (GPIO_PORTC + 30) -#define PCM970_GPIO_SPI_CS1 (GPIO_PORTD + 27) -#define PCM038_GPIO_SPI_CS0 (GPIO_PORTD + 28) -#define PCM038_GPIO_OTG_STP (GPIO_PORTE + 1) - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 1, -}; - -static int pcm038_spi_cs[] = { - PCM038_GPIO_SPI_CS0, -#ifdef CONFIG_MACH_PCM970_BASEBOARD - PCM970_GPIO_SPI_CS1, -#endif -}; - -static struct spi_imx_master pcm038_spi_0_data = { - .chipselect = pcm038_spi_cs, - .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), -}; - -static struct spi_board_info pcm038_spi_board_info[] = { - { - .name = "mc13783", - .bus_num = 0, - .chip_select = 0, - } -}; - -static struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct imx_fb_videomode imxfb_mode = { - .mode = { - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 188679, /* in ps (5.3MHz) */ - .hsync_len = 7, - .left_margin = 5, - .right_margin = 16, - .vsync_len = 1, - .upper_margin = 7, - .lower_margin = 9, - }, - /* - * - HSYNC active high - * - VSYNC active high - * - clk notenabled while idle - * - clock not inverted - * - data not inverted - * - data enable low active - * - enable sharp mode - */ - .pcr = 0xF00080C0, - .bpp = 16, -}; - -static struct imx_fb_platform_data pcm038_fb_data = { - .mode = &imxfb_mode, - .num_modes = 1, - .pwmr = 0x00A903FF, - .lscr1 = 0x00120300, - .dmacr = 0x00020010, -}; - -/** - * The spctl0 register is a beast: Seems you can read it - * only one times without writing it again. - */ -static inline uint32_t get_pll_spctl10(void) -{ - uint32_t reg; - - reg = readl(MX27_CCM_BASE_ADDR + MX27_SPCTL0); - writel(reg, MX27_CCM_BASE_ADDR + MX27_SPCTL0); - - return reg; -} - -/** - * If the PLL settings are in place switch the CPU core frequency to the max. value - */ -static int pcm038_power_init(void) -{ - uint32_t spctl0 = get_pll_spctl10(); - struct mc13xxx *mc13xxx = mc13xxx_get(); - - /* PLL registers already set to their final values? */ - if (spctl0 == SPCTL0_VAL && - readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) { - console_flush(); - if (mc13xxx) { - mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), - MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) | - MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) | - MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450)); - - mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4), - MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1A_SOFTSTART | - MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | - MC13783_SW1B_SOFTSTART | - MC13783_SW_PLL_FACTOR(32)); - - /* Setup VMMC voltage */ - if (IS_ENABLED(CONFIG_MCI_IMX)) { - u32 val; - - mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_SETTING(1), &val); - /* VMMC1 = 3.00 V */ - val &= ~(7 << 6); - val |= 6 << 6; - mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_SETTING(1), val); - - mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_MODE(1), &val); - /* Enable VMMC1 */ - val |= 1 << 18; - mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_MODE(1), val); - } - - /* wait for required power level to run the CPU at 400 MHz */ - udelay(100000); - writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR); - writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); - writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); - - /* Clocks have changed. Notify clients */ - clock_notifier_call_chain(); - } else { - pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n"); - } - } - - /* clock gating enable */ - writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); - - return 0; -} - -struct imxusb_platformdata pcm038_otg_pdata = { - .mode = IMX_USB_MODE_DEVICE, - .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, -}; - -static int pcm038_devices_init(void) -{ - int i; - u64 uid = 0; - char *envdev; - long sram_size; - - unsigned int mode[] = { - /* FEC */ - PD0_AIN_FEC_TXD0, - PD1_AIN_FEC_TXD1, - PD2_AIN_FEC_TXD2, - PD3_AIN_FEC_TXD3, - PD4_AOUT_FEC_RX_ER, - PD5_AOUT_FEC_RXD1, - PD6_AOUT_FEC_RXD2, - PD7_AOUT_FEC_RXD3, - PD8_AF_FEC_MDIO, - PD9_AIN_FEC_MDC | GPIO_PUEN, - PD10_AOUT_FEC_CRS, - PD11_AOUT_FEC_TX_CLK, - PD12_AOUT_FEC_RXD0, - PD13_AOUT_FEC_RX_DV, - PD14_AOUT_FEC_RX_CLK, - PD15_AOUT_FEC_COL, - PD16_AIN_FEC_TX_ER, - PF23_AIN_FEC_TX_EN, - /* UART1 */ - PE12_PF_UART1_TXD, - PE13_PF_UART1_RXD, - PE14_PF_UART1_CTS, - PE15_PF_UART1_RTS, - /* CSPI1 */ - PD25_PF_CSPI1_RDY, - PD29_PF_CSPI1_SCLK, - PD30_PF_CSPI1_MISO, - PD31_PF_CSPI1_MOSI, - /* Display */ - PA5_PF_LSCLK, - PA6_PF_LD0, - PA7_PF_LD1, - PA8_PF_LD2, - PA9_PF_LD3, - PA10_PF_LD4, - PA11_PF_LD5, - PA12_PF_LD6, - PA13_PF_LD7, - PA14_PF_LD8, - PA15_PF_LD9, - PA16_PF_LD10, - PA17_PF_LD11, - PA18_PF_LD12, - PA19_PF_LD13, - PA20_PF_LD14, - PA21_PF_LD15, - PA22_PF_LD16, - PA23_PF_LD17, - PA24_PF_REV, - PA25_PF_CLS, - PA26_PF_PS, - PA27_PF_SPL_SPR, - PA28_PF_HSYNC, - PA29_PF_VSYNC, - PA30_PF_CONTRAST, - PA31_PF_OE_ACD, - /* USB OTG */ - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - /* I2C1 */ - PD17_PF_I2C_DATA | GPIO_PUEN, - PD18_PF_I2C_CLK, - /* I2C2 */ - PC5_PF_I2C2_SDA, - PC6_PF_I2C2_SCL, - /* Misc */ - PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT, - PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT, -#ifdef CONFIG_MACH_PCM970_BASEBOARD - PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT, -#endif - PCM038_GPIO_PMIC_IRQ | GPIO_GPIO | GPIO_IN, - }; - - /* configure 16 bit nor flash on cs0 */ - imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900); - - /* configure SRAM on cs1 */ - imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); - - /* SRAM can be up to 2MiB */ - sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M); - if (sram_size) - add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size, - IORESOURCE_MEM_WRITEABLE); - - /* initizalize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - - spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); - imx27_add_spi0(&pcm038_spi_0_data); - - pcm038_power_init(); - - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); - imx27_add_nand(&nand_info); - imx27_add_fb(&pcm038_fb_data); - - imx27_add_i2c0(NULL); - imx27_add_i2c1(NULL); - - /* Register the fec device after the PLL re-initialisation - * as the fec depends on the (now higher) ipg clock - */ - gpio_set_value(PCM038_GPIO_FEC_RST, 1); - imx27_add_fec(&fec_info); - - /* Apply delay for STP line to stop ULPI */ - gpio_direction_output(PCM038_GPIO_OTG_STP, 1); - mdelay(1); - imx_gpio_mode(PE1_PF_USBOTG_STP); - - if (IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC)) - imx27_add_usbotg(&pcm038_otg_pdata); - - switch (bootsource_get()) { - case BOOTSOURCE_NAND: - devfs_add_partition("nand0", 0, SZ_512K, - DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_512K, SZ_128K, - DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - envdev = "NAND"; - break; - default: - devfs_add_partition("nor0", 0, SZ_512K, - DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", SZ_512K, SZ_128K, - DEVFS_PARTITION_FIXED, "env0"); - protect_file("/dev/env0", 1); - envdev = "NOR"; - } - - pr_notice("Using environment in %s Flash\n", envdev); - - if (imx_iim_read(1, 0, &uid, 6) == 6) - armlinux_set_serial(uid); - armlinux_set_architecture(MACH_TYPE_PCM038); - - return 0; -} - -device_initcall(pcm038_devices_init); - -static int pcm038_console_init(void) -{ - barebox_set_model("Phytec phyCORE-i.MX27"); - barebox_set_hostname("phycore-imx27"); - - imx27_add_uart0(); - - return 0; -} - -console_initcall(pcm038_console_init); diff --git a/arch/arm/boards/pcm038/pcm038.dox b/arch/arm/boards/pcm038/pcm038.dox deleted file mode 100644 index 85177d2..0000000 --- a/arch/arm/boards/pcm038/pcm038.dox +++ /dev/null @@ -1,9 +0,0 @@ -/** @page pcm038 Phytec's phyCORE-i.MX27 - -This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: - -- up to 64MB NOR Flash Memory -- up to 1GB NAND Flash Memory -- up to 256MB DRAM - -*/ diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c deleted file mode 100644 index 2b2483b..0000000 --- a/arch/arm/boards/pcm038/pcm970.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define GPIO_IDE_POWER (GPIO_PORTE + 18) -#define GPIO_IDE_PCOE (GPIO_PORTF + 7) -#define GPIO_IDE_RESET (GPIO_PORTF + 10) - -static struct resource pcm970_ide_resources[] = { - { - .start = MX27_PCMCIA_MEM_BASE_ADDR, - .end = MX27_PCMCIA_MEM_BASE_ADDR + SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static void pcm970_ide_reset(int state) -{ - /* Switch reset line to low/high state */ - gpio_set_value(GPIO_IDE_RESET, !!state); -} - -static struct ide_port_info pcm970_ide_pdata = { - .ioport_shift = 0, - .reset = &pcm970_ide_reset, -}; - -static struct device_d pcm970_ide_device = { - .id = DEVICE_ID_DYNAMIC, - .name = "ide_intf", - .num_resources = ARRAY_SIZE(pcm970_ide_resources), - .resource = pcm970_ide_resources, - .platform_data = &pcm970_ide_pdata, -}; - -static void pcm970_ide_init(void) -{ - uint32_t i; - unsigned int mode[] = { - /* PCMCIA */ - PF20_PF_PC_CD1, - PF19_PF_PC_CD2, - PF18_PF_PC_WAIT, - PF17_PF_PC_READY, - PF16_PF_PC_PWRON, - PF14_PF_PC_VS1, - PF13_PF_PC_VS2, - PF12_PF_PC_BVD1, - PF11_PF_PC_BVD2, - PF9_PF_PC_IOIS16, - PF8_PF_PC_RW, - GPIO_IDE_PCOE | GPIO_GPIO | GPIO_OUT, /* PCOE */ - GPIO_IDE_RESET | GPIO_GPIO | GPIO_OUT, /* Reset */ - GPIO_IDE_POWER | GPIO_GPIO | GPIO_OUT, /* Power */ - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i] | GPIO_PUEN); - - /* Always set PCOE signal to low */ - gpio_set_value(GPIO_IDE_PCOE, 0); - - /* Assert RESET line */ - gpio_set_value(GPIO_IDE_RESET, 0); - - /* Power up CF-card (Also switched on User-LED) */ - gpio_set_value(GPIO_IDE_POWER, 1); - mdelay(10); - - /* Reset PCMCIA Status Change Register */ - writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR); - mdelay(10); - - /* Check PCMCIA Input Pins Register for Card Detect & Power */ - if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) & - ((1 << 8) | (3 << 3))) != (1 << 8)) { - printf("CompactFlash card not found. Driver not enabled.\n"); - return; - } - - /* Disable all interrupts */ - writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER); - - /* Disable all PCMCIA banks */ - for (i = 0; i < 5; i++) - writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(i)); - - /* Not use internal PCOE */ - writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR); - - /* Setup PCMCIA bank0 for Common memory mode */ - writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0)); - writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0)); - writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, - MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); - - /* Clear PCMCIA General Status Register */ - writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR); - - /* Make PCMCIA bank0 valid */ - i = readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); - writel(i | (1 << 29), MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); - - platform_device_register(&pcm970_ide_device); -} - -static void pcm970_mmc_init(void) -{ - uint32_t i; - unsigned int mode[] = { - /* SD2 */ - PB4_PF_SD2_D0, - PB5_PF_SD2_D1, - PB6_PF_SD2_D2, - PB7_PF_SD2_D3, - PB8_PF_SD2_CMD, - PB9_PF_SD2_CLK, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - - imx27_add_mmc1(NULL); -} - -struct imxusb_platformdata pcm970_usbh2_pdata = { - .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, - .mode = IMX_USB_MODE_HOST, -}; - -static int pcm970_init(void) -{ - int i; - unsigned int mode[] = { - /* USB Host 2 */ - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - 4 | GPIO_PORTA | GPIO_GPIO | GPIO_OUT, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, - }; - - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - - /* Configure SJA1000 on cs4 */ - imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); - - if (IS_ENABLED(CONFIG_USB)) { - /* Stop ULPI */ - gpio_direction_output(4, 1); - mdelay(1); - imx_gpio_mode(PA4_PF_USBH2_STP); - - imx27_add_usbh2(&pcm970_usbh2_pdata); - } - - if (IS_ENABLED(CONFIG_DISK_INTF_PLATFORM_IDE)) - pcm970_ide_init(); - - if (IS_ENABLED(CONFIG_MCI_IMX)) - pcm970_mmc_init(); - - return 0; -} - -late_initcall(pcm970_init); diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h deleted file mode 100644 index 8bdb76d..0000000 --- a/arch/arm/boards/pcm038/pll.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/** - * @file - * @brief phyCORE-i.MX27 specific PLL setup - */ - -#ifndef __PCM038_PLL_H -#define __PCM038_PLL_H - -/* define the PLL setting we want to run the system */ - -/* main clock divider settings immediately after reset (at 1.25 V core supply) */ -#define CSCR_VAL (MX27_CSCR_USB_DIV(3) | \ - MX27_CSCR_SD_CNT(3) | \ - MX27_CSCR_MSHC_SEL | \ - MX27_CSCR_H264_SEL | \ - MX27_CSCR_SSI1_SEL | \ - MX27_CSCR_SSI2_SEL | \ - MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ - MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ - MX27_CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ - MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ - MX27_CSCR_FPM_EN | \ - MX27_CSCR_SPEN | \ - MX27_CSCR_MPEN) - -/* main clock divider settings after core voltage increases to 1.45 V */ -#define CSCR_VAL_FINAL (MX27_CSCR_USB_DIV(3) | \ - MX27_CSCR_SD_CNT(3) | \ - MX27_CSCR_MSHC_SEL | \ - MX27_CSCR_H264_SEL | \ - MX27_CSCR_SSI1_SEL | \ - MX27_CSCR_SSI2_SEL | \ - MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ - MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ - MX27_CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ - MX27_CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ - MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ - MX27_CSCR_FPM_EN | /* do not disable it! */ \ - MX27_CSCR_SPEN | \ - MX27_CSCR_MPEN) - -/* MPLL should provide a 399 MHz clock from the 26 MHz reference */ -#define MPCTL0_VAL (IMX_PLL_PD(0) | \ - IMX_PLL_MFD(51) | \ - IMX_PLL_MFI(7) | \ - IMX_PLL_MFN(35)) - -/* SPLL should provide a 240 MHz clock from the 26 MHz reference */ -#define SPCTL0_VAL (IMX_PLL_PD(1) | \ - IMX_PLL_MFD(12) | \ - IMX_PLL_MFI(9) | \ - IMX_PLL_MFN(3)) - - -#endif /* __PCM038_PLL_H */ diff --git a/arch/arm/boards/pcm043/Makefile b/arch/arm/boards/pcm043/Makefile deleted file mode 100644 index 72275ea..0000000 --- a/arch/arm/boards/pcm043/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# -# (C) Copyright 2007 Juergen Beisert -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# - -lwl-y += lowlevel.o -obj-y += pcm043.o diff --git a/arch/arm/boards/pcm043/env/boot/nand-ubi b/arch/arm/boards/pcm043/env/boot/nand-ubi deleted file mode 100644 index 67b0cb4..0000000 --- a/arch/arm/boards/pcm043/env/boot/nand-ubi +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "nand (UBI)" - exit -fi - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/pcm043/env/config-board b/arch/arm/boards/pcm043/env/config-board deleted file mode 100644 index e8e8378..0000000 --- a/arch/arm/boards/pcm043/env/config-board +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/pcm043/env/init/mtdparts-nand b/arch/arm/boards/pcm043/env/init/mtdparts-nand deleted file mode 100644 index 8a41f62..0000000 --- a/arch/arm/boards/pcm043/env/init/mtdparts-nand +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NAND partitions" - exit -fi - -mtdparts="512k(nand0.barebox),256k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" -kernelname="mxc_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm043/env/init/mtdparts-nor b/arch/arm/boards/pcm043/env/init/mtdparts-nor deleted file mode 100644 index f787f28..0000000 --- a/arch/arm/boards/pcm043/env/init/mtdparts-nor +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "NOR partitions" - exit -fi - -mtdparts="512k(nor0.barebox),128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/pcm043/lowlevel.c b/arch/arm/boards/pcm043/lowlevel.c deleted file mode 100644 index 8376bb4..0000000 --- a/arch/arm/boards/pcm043/lowlevel.c +++ /dev/null @@ -1,200 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Assuming 24MHz input clock */ -#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) -#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) -#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) - -#define IMX35_CHIP_REVISION_2_1 0x11 - -#define CCM_PDR0_399 0x00011000 -#define CCM_PDR0_532 0x00001000 - -void __bare_init __naked barebox_arm_reset_vector(void) -{ - uint32_t r, s; - unsigned long ccm_base = MX35_CCM_BASE_ADDR; - unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR; - unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR; - - arm_cpu_lowlevel_init(); - - r = get_cr(); - r |= CR_Z; /* Flow prediction (Z) */ - r |= CR_U; /* unaligned accesses */ - r |= CR_FI; /* Low Int Latency */ - - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s)); - s |= 0x7; - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); - - set_cr(r); - - r = 0; - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * Branch predicition is now enabled. Flush the BTAC to ensure a valid - * starting point. Don't flush BTAC while it is disabled to avoid - * ARM1136 erratum 408023. - */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); - - /* invalidate I cache and D cache */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); - - /* invalidate TLBs */ - __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); - - /* Drain the write buffer */ - __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); - - /* Also setup the Peripheral Port Remap register inside the core */ - r = 0x40000015; /* start from AIPS 2GB region */ - __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); - - /* - * End of ARM1136 init - */ - - writel(0x003F4208, ccm_base + MX35_CCM_CCMR); - - /* Set MPLL , arm clock and ahb clock*/ - writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); - - writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); - - /* Check silicon revision and use 532MHz if >=2.1 */ - r = readl(MX35_IIM_BASE_ADDR + 0x24); - if (r >= IMX35_CHIP_REVISION_2_1) - writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0); - else - writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0); - - r = readl(ccm_base + MX35_CCM_CGR0); - r |= 0x00300000; - writel(r, ccm_base + MX35_CCM_CGR0); - - r = readl(ccm_base + MX35_CCM_CGR1); - r |= 0x00000C00; - r |= 0x00000003; - writel(r, ccm_base + MX35_CCM_CGR1); - - r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - r |= 0x1000; - writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0x80000000 && r < 0x90000000) - goto out; - - /* Set DDR Type to SDRAM, drive strength workaround * - * 0x00000000 MDDR * - * 0x00000800 3,3V SDRAM */ - - r = 0x00000800; - writel(r, iomuxc_base + 0x794); - writel(r, iomuxc_base + 0x798); - writel(r, iomuxc_base + 0x79c); - writel(r, iomuxc_base + 0x7a0); - writel(r, iomuxc_base + 0x7a4); - - /* MDDR init, enable mDDR*/ - writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */ - - /* set timing paramters */ - writel(0x0025541F, esdctl_base + IMX_ESDCFG0); - /* select Precharge-All mode */ - writel(0x92220000, esdctl_base + IMX_ESDCTL0); - /* Precharge-All */ - writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); - - /* select Load-Mode-Register mode */ - writel(0xB8001000, esdctl_base + IMX_ESDCTL0); - /* Load reg EMR2 */ - writeb(0xda, 0x84000000); - /* Load reg EMR3 */ - writeb(0xda, 0x86000000); - /* Load reg EMR1 -- enable DLL */ - writeb(0xda, 0x82000400); - /* Load reg MR -- reset DLL */ - writeb(0xda, 0x80000333); - - /* select Precharge-All mode */ - writel(0x92220000, esdctl_base + IMX_ESDCTL0); - /* Precharge-All */ - writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); - - /* select Manual-Refresh mode */ - writel(0xA2220000, esdctl_base + IMX_ESDCTL0); - /* Manual-Refresh 2 times */ - writel(0x87654321, MX35_CSD0_BASE_ADDR); - writel(0x87654321, MX35_CSD0_BASE_ADDR); - - /* select Load-Mode-Register mode */ - writel(0xB2220000, esdctl_base + IMX_ESDCTL0); - /* Load reg MR -- CL3, BL8, end DLL reset */ - writeb(0xda, 0x80000233); - /* Load reg EMR1 -- OCD default */ - writeb(0xda, 0x82000780); - /* Load reg EMR1 -- OCD exit */ - writeb(0xda, 0x82000400); - - /* select normal-operation mode - * DSIZ32-bit, BL8, COL10-bit, ROW13-bit - * disable PWT & PRCT - * disable Auto-Refresh */ - writel(0x82220080, esdctl_base + IMX_ESDCTL0); - - /* enable Auto-Refresh */ - writel(0x82228080, esdctl_base + IMX_ESDCTL0); - /* enable Auto-Refresh */ - writel(0x00002000, esdctl_base + IMX_ESDCTL1); - - if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { - /* Speed up NAND controller by adjusting the NFC divider */ - r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - r &= ~(0xf << 28); - r |= 0x1 << 28; - writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); - - /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ - arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); - - imx35_barebox_boot_nand_external(0); - } - -out: - imx35_barebox_entry(0); -} diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c deleted file mode 100644 index 46821a7..0000000 --- a/arch/arm/boards/pcm043/pcm043.c +++ /dev/null @@ -1,339 +0,0 @@ -/* - * (C) 2007 Pengutronix, Sascha Hauer - * (C) 2009 Pengutronix, Juergen Beisert - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - * Board support for Phytec's, i.MX35 based CPU card, called: PCM043 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct fec_platform_data fec_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, -}; - -struct imx_nand_platform_data nand_info = { - .width = 1, - .hw_ecc = 1, - .flash_bbt = 1, -}; - -static struct fb_videomode pcm043_fb_mode[] = { - { - /* 240x320 @ 60 Hz */ - .name = "TX090", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 38255, - .left_margin = 144, - .right_margin = 0, - .upper_margin = 7, - .lower_margin = 40, - .hsync_len = 96, - .vsync_len = 1, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - }, { - /* 240x320 @ 60 Hz */ - .name = "Sharp-LQ035Q7", - .refresh = 60, - .xres = 240, - .yres = 320, - .pixclock = 185925, - .left_margin = 9, - .right_margin = 16, - .upper_margin = 7, - .lower_margin = 9, - .hsync_len = 1, - .vsync_len = 1, - .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | \ - FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, - } -}; - -static struct imx_ipu_fb_platform_data ipu_fb_data = { - .mode = pcm043_fb_mode, - .num_modes = ARRAY_SIZE(pcm043_fb_mode), - .framebuffer_ovl = (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M), - .bpp = 16, -}; - -static int pcm043_mmu_init(void) -{ - l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); - - return 0; -} -postmmu_initcall(pcm043_mmu_init); - -struct gpio_led led0 = { - .gpio = 1 * 32 + 6, -}; - -static int pcm043_devices_init(void) -{ - uint32_t reg; - char *envstr; - unsigned long bbu_nand_flags = 0; - - /* CS0: Nor Flash */ - imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900); - - led_gpio_register(&led0); - - reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); - /* some fuses provide us vital information about connected hardware */ - if (reg & 0x20000000) - nand_info.width = 2; /* 16 bit */ - else - nand_info.width = 1; /* 8 bit */ - - imx35_add_fec(&fec_info); - /* - * This platform supports NOR and NAND - */ - imx35_add_nand(&nand_info); - /* - * Up to 32MiB NOR type flash, connected to - * CS line 0, data width is 16 bit - */ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); - - switch (bootsource_get()) { - case BOOTSOURCE_NAND: - devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - envstr = "NAND"; - bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT; - break; - case BOOTSOURCE_NOR: - default: - devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */ - devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); /* environment */ - protect_file("/dev/env0", 1); - envstr = "NOR"; - break; - } - - pr_info("using environment from %s flash\n", envstr); - - imx35_add_fb(&ipu_fb_data); - - armlinux_set_architecture(MACH_TYPE_PCM043); - - imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox", - bbu_nand_flags); - - return 0; -} - -device_initcall(pcm043_devices_init); - -static iomux_v3_cfg_t pcm043_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - MX35_PAD_RXD1__UART1_RXD_MUX, - MX35_PAD_TXD1__UART1_TXD_MUX, - MX35_PAD_RTS1__UART1_RTS, - MX35_PAD_CTS1__UART1_CTS, - MX35_PAD_I2C1_CLK__I2C1_SCL, - MX35_PAD_I2C1_DAT__I2C1_SDA, - MX35_PAD_ATA_CS0__GPIO2_6, /* LED */ -}; - -static int imx35_console_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); - - barebox_set_model("Phytec phyCORE-i.MX35"); - barebox_set_hostname("phycore-imx35"); - - imx35_add_uart0(); - - return 0; -} - -console_initcall(imx35_console_init); - -static int pcm043_core_setup(void) -{ - u32 tmp; - - /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - writel(0x77777777, MX35_AIPS1_BASE_ADDR); - writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); - writel(0x77777777, MX35_AIPS2_BASE_ADDR); - writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); - - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50); - - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); - writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); - tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50); - tmp &= 0x00FFFFFF; - writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50); - - /* MAX (Multi-Layer AHB Crossbar Switch) setup */ - - /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ -#define MAX_PARAM1 0x00302154 - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ - writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ - - /* SGPCR - always park on last master */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ - writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ - - /* MGPCR - restore default values */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ - writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ - - /* - * M3IF Control Register (M3IFCTL) - * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 - * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 - * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 - * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 - * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 - * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 - * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 - * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 - * ------------ - * 0x00000040 - */ - writel(0x40, MX35_M3IF_BASE_ADDR); - - return 0; -} - -core_initcall(pcm043_core_setup); - -#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) -#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) - -static int do_cpufreq(int argc, char *argv[]) -{ - unsigned long freq; - - if (argc != 2) - return COMMAND_ERROR_USAGE; - - freq = simple_strtoul(argv[1], NULL, 0); - - switch (freq) { - case 399: - writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - case 532: - writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); - break; - default: - return COMMAND_ERROR_USAGE; - } - - printf("Switched CPU frequency to %ldMHz\n", freq); - - return 0; -} - -static const __maybe_unused char cmd_cpufreq_help[] = -"Usage: cpufreq 399|532\n" -"\n" -"Set CPU frequency to MHz\n"; - -BAREBOX_CMD_START(cpufreq) - .cmd = do_cpufreq, - .usage = "adjust CPU frequency", - BAREBOX_CMD_HELP(cmd_cpufreq_help) -BAREBOX_CMD_END - diff --git a/arch/arm/boards/pcm043/pcm043.dox b/arch/arm/boards/pcm043/pcm043.dox deleted file mode 100644 index c6715ff..0000000 --- a/arch/arm/boards/pcm043/pcm043.dox +++ /dev/null @@ -1,28 +0,0 @@ -/** @page pcm043 Phytec's phyCORE-i.MX35 - -This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with: - - -FIXME: -- up to 64 MiB NOR type Flash Memory -- up to 2 MiB static RAM -- 1 GiB or 2 GiB NAND type Flash Memory - - Micron NAND 1 GiB 3,3V 8-bit - - 256 kiB block size - - ? kiB page size - - Manufacturer ID: 0x2c - - Device ID: 0xd3 - - Samsung K9K8G08, 1 GiB - - 128 kiB block size - - 2 kiB page size - - Manufacturer ID: ? - - Device ID: ? - - ST NAND08G, 1 GiB - - 128 kiB block size - - 2 kiB page size - - Manufacturer ID: ? - - Device ID: ? -- 128MiB synchronous dynamic RAM - - -*/ diff --git a/arch/arm/boards/pcm049/Makefile b/arch/arm/boards/pcm049/Makefile deleted file mode 100644 index 5d4eb10..0000000 --- a/arch/arm/boards/pcm049/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -obj-y += board.o -lwl-y += lowlevel.o mux.o diff --git a/arch/arm/boards/pcm049/board.c b/arch/arm/boards/pcm049/board.c deleted file mode 100644 index baf88a3..0000000 --- a/arch/arm/boards/pcm049/board.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int pcm049_console_init(void) -{ - barebox_set_model("Phytec phyCORE-OMAP4460"); - barebox_set_hostname("phycore-omap4460"); - - omap44xx_add_uart3(); - - return 0; -} -console_initcall(pcm049_console_init); - -static int pcm049_mem_init(void) -{ -#ifdef CONFIG_1024MB_DDR2RAM - omap_add_ram0(SZ_1G); -#else - omap_add_ram0(SZ_512M); -#endif - - omap44xx_add_sram0(); - return 0; -} -mem_initcall(pcm049_mem_init); - -static struct gpmc_config net_cfg = { - .cfg = { - 0xc1001000, /* CONF1 */ - 0x00070700, /* CONF2 */ - 0x00000000, /* CONF3 */ - 0x07000700, /* CONF4 */ - 0x09060909, /* CONF5 */ - 0x000003c2, /* CONF6 */ - }, - .base = 0x2C000000, - .size = GPMC_SIZE_16M, -}; - -static void pcm049_network_init(void) -{ - gpmc_cs_config(5, &net_cfg); - - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x2C000000, 0x4000, - IORESOURCE_MEM, NULL); -} - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("twl6030", 0x48), - }, -}; - -static struct gpmc_nand_platform_data nand_plat = { - .wait_mon_pin = 1, - .ecc_mode = OMAP_ECC_BCH8_CODE_HW, - .nand_cfg = &omap4_nand_cfg, -}; - -static struct omapfb_display const pcm049_displays[] = { - { - .mode = { - .name = "pd050vl1", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 25000, - .left_margin = 46, - .right_margin = 18, - .hsync_len = 96, - .upper_margin = 33, - .lower_margin = 10, - .vsync_len = 2, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* Prime-View PM070WL4 */ - { - .mode = { - .name = "pm070wl4", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 32000, - .left_margin = 86, - .right_margin = 42, - .hsync_len = 128, - .lower_margin = 10, - .upper_margin = 33, - .vsync_len = 2, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* Prime-View PD104SLF */ - { - .mode = { - .name = "pd104slf", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 40000, - .left_margin = 86, - .right_margin = 42, - .hsync_len = 128, - .lower_margin = 1, - .upper_margin = 23, - .vsync_len = 4, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* EDT ETM0350G0DH6 */ - { - .mode = { - .name = "edt_etm0350G0dh6", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = 15720, - .left_margin = 68, - .right_margin = 20, - .hsync_len = 88, - .lower_margin = 4, - .upper_margin = 18, - .vsync_len = 22, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* EDT ETM0430G0DH6 */ - { - .mode = { - .name = "edt_etm0430G0dh6", - .refresh = 60, - .xres = 480, - .yres = 272, - .pixclock = 9000, - .left_margin = 2, - .right_margin = 2, - .hsync_len = 41, - .lower_margin = 2, - .upper_margin = 2, - .vsync_len = 10, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* EDT ETMV570G2DHU */ - { - .mode = { - .name = "edt_etmv570G2dhu", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 25175, - .left_margin = 114, - .right_margin = 16, - .hsync_len = 30, - .lower_margin = 10, - .upper_margin = 35, - .vsync_len = 3, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* ETD ETM0700G0DH6 */ - { - .mode = { - .name = "edt_etm0700G0dh6", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 33260, - .left_margin = 216, - .right_margin = 40, - .hsync_len = 128, - .lower_margin = 10, - .upper_margin = 35, - .vsync_len = 2, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - - /* CHIMEI G104X1-L03 */ - { - .mode = { - .name = "g104x1", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 64000, - .left_margin = 320, - .right_margin = 1, - .hsync_len = 320, - .upper_margin = 38, - .lower_margin = 38, - .vsync_len = 2, - }, - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - - .power_on_delay = 50, - .power_off_delay = 100, - }, -}; - -#define GPIO_DISPENABLE 118 -#define GPIO_BACKLIGHT 122 - -static void pcm049_fb_enable(int e) -{ - gpio_direction_output(GPIO_DISPENABLE, e); - gpio_direction_output(GPIO_BACKLIGHT, e); -} - -static struct omapfb_platform_data pcm049_fb_data = { - .displays = pcm049_displays, - .num_displays = ARRAY_SIZE(pcm049_displays), - - .dss_clk_hz = 19200000, - - .bpp = 32, - .enable = pcm049_fb_enable, -}; - -static int pcm049_devices_init(void) -{ - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - omap44xx_add_i2c1(NULL); - omap44xx_add_mmc1(NULL); - - gpmc_generic_init(0x10); - - if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X)) - pcm049_network_init(); - - omap_add_gpmc_nand_device(&nand_plat); - -#ifdef CONFIG_PARTITION - devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "xload_raw"); - dev_add_bb_dev("xload_raw", "xload"); - devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - - armlinux_set_architecture(MACH_TYPE_PCM049); - - if (IS_ENABLED(CONFIG_DRIVER_VIDEO_OMAP)) - omap_add_display(&pcm049_fb_data); - - return 0; -} -device_initcall(pcm049_devices_init); diff --git a/arch/arm/boards/pcm049/env/bin/init_board b/arch/arm/boards/pcm049/env/bin/init_board deleted file mode 100644 index d5142ee..0000000 --- a/arch/arm/boards/pcm049/env/bin/init_board +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/sh -global displayargs -. /env/config - -if [ -z $display ]; then - echo "no display configured" - exit 0 -fi - -if [ $display = dvi ]; then - global.displayargs="omapdss.def_disp=dvi omapfb.mode=dvi:$dvi_resolution" - exit 0 -fi - -# Display a splash screen - -if [ -e /dev/fb0 ]; then - fb0.mode_name=$display - splash /dev/nand0.splash.bb - fb0.enable=1 -fi - -global.displayargs="panel_generic_dpi.name=$display" diff --git a/arch/arm/boards/pcm049/env/bin/nand_bootstrap b/arch/arm/boards/pcm049/env/bin/nand_bootstrap deleted file mode 100644 index 49e38dc..0000000 --- a/arch/arm/boards/pcm049/env/bin/nand_bootstrap +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh -echo "copying barebox to nand..." - -mci0.probe=1 -mkdir mnt - -mount /dev/disk0.0 /mnt -if [ $? != 0 ]; then - echo "failed to mount mmc card" - exit 1 -fi - -if [ ! -f /mnt/mlo-nand.bin ]; then - echo "mlo-nand.bin not found on mmc card" - exit 1 -fi - -if [ ! -f /mnt/barebox.bin ]; then - echo "barebox.bin not found on mmc card" -fi - -gpmc_nand0.eccmode=bch8_hw_romcode -erase /dev/nand0.xload.bb -cp /mnt/mlo-nand.bin /dev/nand0.xload.bb - -gpmc_nand0.eccmode=bch8_hw -erase /dev/nand0.barebox.bb -cp /mnt/barebox.bin /dev/nand0.barebox.bb - -echo "success" - diff --git a/arch/arm/boards/pcm049/env/config b/arch/arm/boards/pcm049/env/config deleted file mode 100644 index 1a252dd..0000000 --- a/arch/arm/boards/pcm049/env/config +++ /dev/null @@ -1,61 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyO2,115200" - -nand_parts="128k(xload)ro,512k(barebox),128k(bareboxenv),4M(kernel),4M(splash),-(root)" -nand_device="omap2-nand.0" -rootfs_mtdblock_nand=5 - -#Displays -# Splashscreen-Display can be either '', 'pd050vl1', 'pm070wl4', 'pd104slf', 'g104x1' -# 'edt_etm0350G0dh6', 'edt_etm0430G0dh6', 'edt_etmv570G2dhu' or 'edt_etm0700G0dh6' -# to use dvi output in kernel set 'display=dvi' and -# dvi_resolution to '640x480-60' '800x600-60' or '1024x768-60' - -display=edt_etm0700G0dh6 -#dvi_resolution=1024x768-60 - -if [ -n ${global.displayargs} ]; then - bootargs="$bootargs ${global.displayargs}" -fi - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c deleted file mode 100644 index 4f39600..0000000 --- a/arch/arm/boards/pcm049/lowlevel.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TPS62361_VSEL0_GPIO 182 - -void set_muxconf_regs(void); - -/* 512MB */ -static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { - .tim1 = 0x0EEB0662, - .tim2 = 0x20370DD2, - .tim3 = 0x00BFC33F, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80001AB1, - .config_final = 0x80001AB1, - .zq_config = 0xd0093215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -/* 1GB */ -static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = { - .tim1 = 0x0EEB0663, - .tim2 = 0x205715D2, - .tim3 = 0x00BFC53F, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80001AB9, - .config_final = 0x80001AB9, - .zq_config = 0x50093215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -static void noinline pcm049_init_lowlevel(void) -{ - struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; - struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; - struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; - struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; - struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; - struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; - unsigned int rev = omap4_revision(); - - set_muxconf_regs(); - -#ifdef CONFIG_1024MB_DDR2RAM - omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core); -#else - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); -#endif - - /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - if (rev < OMAP4460_ES1_0) - omap4430_scale_vcores(); - else - omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); - - writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); - - /* Configure all DPLL's at 100% OPP */ - if (rev < OMAP4460_ES1_0) - omap4_configure_mpu_dpll(&mpu44xx); - else - omap4_configure_mpu_dpll(&mpu4460); - - omap4_configure_iva_dpll(&iva); - omap4_configure_per_dpll(&per); - omap4_configure_abe_dpll(&abe); - omap4_configure_usb_dpll(&usb); - - /* Enable all clocks */ - omap4_enable_all_clocks(); - - sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1); /* enable software ioreq */ - sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ - sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x0); /* set divisor to 1 */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1); /* activate clock source */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) -{ - omap4_save_bootinfo(data); - - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) - goto out; - - arm_setup_stack(0x4030d000); - - pcm049_init_lowlevel(); -out: - barebox_arm_entry(0x80000000, SZ_512M, 0); -} diff --git a/arch/arm/boards/pcm049/mux.c b/arch/arm/boards/pcm049/mux.c deleted file mode 100644 index fda4c51..0000000 --- a/arch/arm/boards/pcm049/mux.c +++ /dev/null @@ -1,253 +0,0 @@ -#include -#include -#include -#include -#include -#include - -static const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ - {GPMC_AD1, (IEN | PTD | DIS | M0)}, /* gpmc_ad1 */ - {GPMC_AD2, (IEN | PTD | DIS | M0)}, /* gpmc_ad2 */ - {GPMC_AD3, (IEN | PTD | DIS | M0)}, /* gpmc_ad3 */ - {GPMC_AD4, (IEN | PTD | DIS | M0)}, /* gpmc_ad4 */ - {GPMC_AD5, (IEN | PTD | DIS | M0)}, /* gpmc_ad5 */ - {GPMC_AD6, (IEN | PTD | DIS | M0)}, /* gpmc_ad6 */ - {GPMC_AD7, (IEN | PTD | DIS | M0)}, /* gpmc_ad7 */ - {GPMC_AD8, (IEN | PTD | DIS | M0)}, /* gpmc_ad8 */ - {GPMC_AD9, (IEN | PTD | DIS | M0)}, /* gpmc_ad9 */ - {GPMC_AD10, (IEN | PTD | DIS | M0)}, /* gpmc_ad10 */ - {GPMC_AD11, (IEN | PTD | DIS | M0)}, /* gpmc_ad11 */ - {GPMC_AD12, (IEN | PTD | DIS | M0)}, /* gpmc_ad12 */ - {GPMC_AD13, (IEN | PTD | DIS | M0)}, /* gpmc_ad13 */ - {GPMC_AD14, (IEN | PTD | DIS | M0)}, /* gpmc_ad14 */ - {GPMC_AD15, (IEN | PTD | DIS | M0)}, /* gpmc_ad15 */ - {GPMC_A16, (IEN | PTD | DIS | M0)}, /* gpmc_a16 */ - {GPMC_A17, (IEN | PTD | DIS | M0)}, /* gpmc_a17 */ - {GPMC_A18, (IEN | PTD | DIS | M0)}, /* gpmc_a18 */ - {GPMC_A19, (IEN | PTD | DIS | M0)}, /* gpmc_a19 */ - {GPMC_A20, (IEN | PTD | DIS | M0)}, /* gpmc_a20 */ - {GPMC_A21, (IEN | PTD | DIS | M0)}, /* gpmc_a21 */ - {GPMC_A22, (IEN | PTD | DIS | M0)}, /* gpmc_a22 */ - {GPMC_A23, (IEN | PTD | DIS | M0)}, /* gpmc_a23 */ - {GPMC_A24, (IEN | PTD | DIS | M0)}, /* gpmc_a24 */ - {GPMC_A25, (IEN | PTD | DIS | M0)}, /* gpmc_a25 */ - {GPMC_NCS0, (IDIS | PTU | EN | M0)}, /* gpmc_nsc0 */ - {GPMC_NCS1, (IDIS | PTU | EN | M0)}, /* gpmc_nsc1 */ - {GPMC_NCS2, (SAFE_MODE)}, /* nc */ - {GPMC_NCS3, (SAFE_MODE)}, /* nc */ - {GPMC_NWP, (IEN | PTD | DIS | M0)}, /* gpmc_nwp */ - {GPMC_CLK, (SAFE_MODE)}, /* nc */ - {GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)}, /* gpmc_ndav_ale */ - {GPMC_NOE, (IDIS | PTD | DIS | M0)}, /* gpmc_noe */ - {GPMC_NWE, (IDIS | PTD | DIS | M0)}, /* gpmc_nwe */ - {GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)}, /* gpmc_nbe0_cle */ - {GPMC_NBE1, (SAFE_MODE)}, /* nc */ - {GPMC_WAIT0, (IEN | PTU | EN | M0)}, /* gpmc_wait0 */ - {GPMC_WAIT1, (SAFE_MODE)}, /* nc */ - {C2C_DATA11, (SAFE_MODE)}, /* nc */ - {C2C_DATA12, (SAFE_MODE)}, /* nc */ - {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */ - {C2C_DATA14, (SAFE_MODE)}, /* nc */ - {C2C_DATA15, (SAFE_MODE)}, /* nc */ - {HDMI_HPD, (SAFE_MODE)}, /* unused */ - {HDMI_CEC, (SAFE_MODE)}, /* unused */ - {HDMI_DDC_SCL, (SAFE_MODE)}, /* unused */ - {HDMI_DDC_SDA, (SAFE_MODE)}, /* unused */ - {CSI21_DX0, (SAFE_MODE)}, /* unused */ - {CSI21_DY0, (SAFE_MODE)}, /* unused */ - {CSI21_DX1, (SAFE_MODE)}, /* unused */ - {CSI21_DY1, (SAFE_MODE)}, /* unused */ - {CSI21_DX2, (SAFE_MODE)}, /* unused */ - {CSI21_DY2, (SAFE_MODE)}, /* unused */ - {CSI21_DX3, (SAFE_MODE)}, /* unused */ - {CSI21_DY3, (SAFE_MODE)}, /* unused */ - {CSI21_DX4, (SAFE_MODE)}, /* unused */ - {CSI21_DY4, (SAFE_MODE)}, /* unused */ - {CSI22_DX0, (SAFE_MODE)}, /* unused */ - {CSI22_DY0, (SAFE_MODE)}, /* unused */ - {CSI22_DX1, (SAFE_MODE)}, /* unused */ - {CSI22_DY1, (SAFE_MODE)}, /* unused */ - {CAM_SHUTTER, (SAFE_MODE)}, /* unused */ - {CAM_STROBE, (SAFE_MODE)}, /* unused */ - {CAM_GLOBALRESET, (SAFE_MODE)}, /* unused */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (SAFE_MODE)}, /* nc */ - {USBB1_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {USBC1_ICUSB_DP, (SAFE_MODE)}, /* unused */ - {USBC1_ICUSB_DM, (SAFE_MODE)}, /* unused */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (SAFE_MODE)}, /* unused */ - {SDMMC1_DAT5, (SAFE_MODE)}, /* unused */ - {SDMMC1_DAT6, (SAFE_MODE)}, /* unused */ - {SDMMC1_DAT7, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_CLKX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_DR, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_DX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_FSX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_CLKX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DR, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_FSX, (SAFE_MODE)}, /* unused */ - {ABE_PDM_UL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_DL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_FRAME, (SAFE_MODE)}, /* unused */ - {ABE_PDM_LB_CLK, (SAFE_MODE)}, /* unused */ - {ABE_CLKS, (M3)}, /* gpio_118 */ - {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN1, (SAFE_MODE)}, /* unused */ - {ABE_DMIC_DIN2, (DIS | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (M3)}, /* gpio_122 */ - {UART2_CTS, (SAFE_MODE)}, /* unused */ - {UART2_RTS, (SAFE_MODE)}, /* unused */ - {UART2_RX, (SAFE_MODE)}, /* unused */ - {UART2_TX, (SAFE_MODE)}, /* unused */ - {HDQ_SIO, (SAFE_MODE)}, /* unused */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (SAFE_MODE)}, /* unused */ - {I2C2_SDA, (SAFE_MODE)}, /* unused */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ - {MCSPI1_CLK, (SAFE_MODE)}, /* unused */ - {MCSPI1_SOMI, (SAFE_MODE)}, /* unused */ - {MCSPI1_SIMO, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS0, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS1, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS2, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS3, (SAFE_MODE)}, /* unused */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (SAFE_MODE)}, /* nc */ - {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */ - {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */ - {MCSPI4_CS0, (SAFE_MODE)}, /* nc */ - {UART4_RX, (SAFE_MODE)}, /* unused */ - {UART4_TX, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_CLK, (SAFE_MODE)}, /* nc */ - {USBB2_ULPITLL_STP, (M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (SAFE_MODE)}, /* nc */ - {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX0, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY0, (SAFE_MODE)}, /* unused */ - {UNIPRO_TX1, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY1, (SAFE_MODE)}, /* unused */ - {UNIPRO_TX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY2, (SAFE_MODE)}, /* unused */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */ - {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M0)}, /* sys_boot0 */ - {SYS_BOOT0, (M0)}, /* sys_boot */ - {SYS_BOOT1, (M0)}, /* sys_boot */ - {SYS_BOOT2, (M0)}, /* sys_boot */ - {SYS_BOOT3, (M0)}, /* sys_boot */ - {SYS_BOOT4, (M0)}, /* sys_boot */ - {SYS_BOOT5, (M0)}, /* sys_boot */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (SAFE_MODE)}, /* unused */ - {DPM_EMU3, (M5)}, /* dispc2_data10 */ - {DPM_EMU4, (M5)}, /* dispc2_data9 */ - {DPM_EMU5, (M5)}, /* dispc2_data16 */ - {DPM_EMU6, (M5)}, /* dispc2_data17 */ - {DPM_EMU7, (M5)}, /* dispc2_hsync */ - {DPM_EMU8, (M5)}, /* dispc2_pclk */ - {DPM_EMU9, (M5)}, /* dispc2_vsync */ - {DPM_EMU10, (M5)}, /* dispc2_de */ - {DPM_EMU11, (M5)}, /* dispc2_data8 */ - {DPM_EMU12, (M5)}, /* dispc2_data7 */ - {DPM_EMU13, (M5)}, /* dispc2_data6 */ - {DPM_EMU14, (M5)}, /* dispc2_data5 */ - {DPM_EMU15, (M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M5)}, /* dispc2_data3 */ - {DPM_EMU17, (M5)}, /* dispc2_data2 */ - {DPM_EMU18, (M5)}, /* dispc2_data1 */ - {DPM_EMU19, (M5)}, /* dispc2_data0 */ -}; - -static const struct pad_conf_entry wkup_padconf_array[] = { - {GPIO_WK0, (SAFE_MODE)}, /* nc */ - {GPIO_WK1, (SAFE_MODE)}, /* nc */ - {GPIO_WK2, (SAFE_MODE)}, /* nc */ - {GPIO_WK3, (SAFE_MODE)}, /* nc */ - {GPIO_WK4, (SAFE_MODE)}, /* nc */ - {SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ - {FREF_XTAL_IN, (M0)}, /* # */ - {FREF_SLICER_IN, (SAFE_MODE)}, /* nc */ - {FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ - {FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {FREF_CLK3_REQ, (IEN | M3)}, /* gpio_wk30 */ - {FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {FREF_CLK4_REQ, (M0)}, /* fref_clk4_req */ - {FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */ - {SYS_32K, (IEN | M0)}, /* sys_32k */ - {SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {SYS_PWRON_RESET_OUT, (M0)}, /* sys_pwron_reset_out */ - {SYS_BOOT6, (M0)}, /* sys_boot6 */ - {SYS_BOOT7, (M0)}, /* sys_boot7 */ -}; - -void set_muxconf_regs(void) -{ - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, - ARRAY_SIZE(core_padconf_array)); - - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, - ARRAY_SIZE(wkup_padconf_array)); - - /* gpio_182 is used for controlling TPS on 4460 */ - if (omap4_revision() >= OMAP4460_ES1_0) { - writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT); - /* Enable GPIO-1 clocks before TPS initialization */ - omap4_enable_gpio_clocks(); - } -} diff --git a/arch/arm/boards/pcm051/Makefile b/arch/arm/boards/pcm051/Makefile deleted file mode 100644 index 092c31d..0000000 --- a/arch/arm/boards/pcm051/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -lwl-y += lowlevel.o -obj-y += board.o diff --git a/arch/arm/boards/pcm051/board.c b/arch/arm/boards/pcm051/board.c deleted file mode 100644 index 59de42b..0000000 --- a/arch/arm/boards/pcm051/board.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * pcm051 - phyCORE-AM335x Board Initalization Code - * - * Copyright (C) 2012 Teresa Gámez, Phytec Messtechnik GmbH - * - * Based on arch/arm/boards/omap/board-beagle.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -static int pcm051_coredevice_init(void) -{ - if (!of_machine_is_compatible("phytec,pcm051")) - return 0; - - am33xx_register_ethaddr(0, 0); - return 0; -} -coredevice_initcall(pcm051_coredevice_init); - -static struct omap_barebox_part pcm051_barebox_part = { - .nand_offset = SZ_512K, - .nand_size = SZ_512K, - .nor_offset = SZ_128K, - .nor_size = SZ_512K, -}; - -static int pcm051_devices_init(void) -{ - if (!of_machine_is_compatible("phytec,pcm051")) - return 0; - - switch (bootsource_get()) { - case BOOTSOURCE_SPI: - of_device_enable_path("/chosen/environment-spi"); - break; - case BOOTSOURCE_MMC: - omap_set_bootmmc_devname("mmc0"); - break; - default: - of_device_enable_path("/chosen/environment-nand"); - break; - } - - omap_set_barebox_part(&pcm051_barebox_part); - armlinux_set_architecture(MACH_TYPE_PCM051); - - am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload"); - - return 0; -} -device_initcall(pcm051_devices_init); diff --git a/arch/arm/boards/pcm051/env/boot/mmc b/arch/arm/boards/pcm051/env/boot/mmc deleted file mode 100644 index 93a2357..0000000 --- a/arch/arm/boards/pcm051/env/boot/mmc +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "kernel & rootfs on SD card" - exit -fi - -global.bootm.image=/boot/uImage -#global.bootm.oftree=/boot/oftree -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" diff --git a/arch/arm/boards/pcm051/env/boot/nand b/arch/arm/boards/pcm051/env/boot/nand deleted file mode 100644 index 22d657e..0000000 --- a/arch/arm/boards/pcm051/env/boot/nand +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "nand (UBI)" - exit -fi - -global.bootm.image="/dev/nand0.kernel.bb" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs" diff --git a/arch/arm/boards/pcm051/env/boot/spi b/arch/arm/boards/pcm051/env/boot/spi deleted file mode 100644 index 2d10184..0000000 --- a/arch/arm/boards/pcm051/env/boot/spi +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - boot-menu-add-entry "$0" "SPI NOR Flash" - exit -fi - -global.bootm.image="/dev/m25p0.kernel" - -# Use rootfs form NAND for now as rootfs partition < 4MB -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs" diff --git a/arch/arm/boards/pcm051/env/config-board b/arch/arm/boards/pcm051/env/config-board deleted file mode 100644 index 7f0b2b7..0000000 --- a/arch/arm/boards/pcm051/env/config-board +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -# board defaults, do not change in running system. Change /env/config -# instead - -global.hostname=pcm051 -global.linux.bootargs.base="console=ttyO0,115200" diff --git a/arch/arm/boards/pcm051/lowlevel.c b/arch/arm/boards/pcm051/lowlevel.c deleted file mode 100644 index d3cac68..0000000 --- a/arch/arm/boards/pcm051/lowlevel.c +++ /dev/null @@ -1,120 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = { - .slave_ratio0 = 0x40, - .dll_lock_diff0 = 0x0, - .invert_clkout0 = 0x1, - .slave_ratio1 = 0x40, - .dll_lock_diff1 = 0x0, - .invert_clkout1 = 0x1, - .slave_ratio2 = 0x40, - .dll_lock_diff2 = 0x0, - .invert_clkout2 = 0x1, -}; - -static const struct am33xx_emif_regs MT41J256M8HX15E_2x256M8_regs = { - .emif_read_latency = 0x6, - .emif_tim1 = 0x0668A39B, - .emif_tim2 = 0x26337FDA, - .emif_tim3 = 0x501F830F, - .sdram_config = 0x61C04832, - .zq_config = 0x50074BE4, - .sdram_ref_ctrl = 0x0000093B, -}; - -static const struct am33xx_ddr_data MT41J256M8HX15E_2x256M8_data = { - .rd_slave_ratio0 = 0x3B, - .wr_dqs_slave_ratio0 = 0x85, - .fifo_we_slave_ratio0 = 0x100, - .wr_slave_ratio0 = 0xC1, - .use_rank0_delay = 0x01, - .dll_lock_diff0 = 0x0, -}; - -extern char __dtb_am335x_phytec_phycore_start[]; -extern char __dtb_am335x_phytec_phycore_end[]; - -/** - * @brief The basic entry point for board initialization. - * - * This is called as part of machine init (after arch init). - * This is again called with stack in SRAM, so not too many - * constructs possible here. - * - * @return void - */ -static noinline void pcm051_board_init(void) -{ - unsigned long sdram = 0x80000000, fdt; - - /* WDT1 is already running when the bootloader gets control - * Disable it to avoid "random" resets - */ - writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - - writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); - while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); - - am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); - - am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd, - &MT41J256M8HX15E_2x256M8_regs, - &MT41J256M8HX15E_2x256M8_data); - - am33xx_uart0_soft_reset(); - am33xx_enable_uart0_pin_mux(); - omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); - putc_ll('>'); - - /* - * Copy the devicetree blob to sdram so that the barebox code finds it - * inside valid SDRAM instead of SRAM. - */ - memcpy((void *)sdram, __dtb_am335x_phytec_phycore_start, - __dtb_am335x_phytec_phycore_end - - __dtb_am335x_phytec_phycore_start); - fdt = sdram; - - barebox_arm_entry(sdram, SZ_512M, fdt); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2) -{ - am33xx_save_bootinfo((void *)bootinfo); - - arm_cpu_lowlevel_init(); - - /* - * Setup C environment, the board init code uses global variables. - * Stackpointer has already been initialized by the ROM code. - */ - relocate_to_current_adr(); - setup_c(); - - pcm051_board_init(); -} - -ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) -{ - uint32_t fdt; - - fdt = (uint32_t)__dtb_am335x_phytec_phycore_start - get_runtime_offset(); - - barebox_arm_entry(0x80000000, SZ_512M, fdt); -} diff --git a/arch/arm/boards/phycard-a-l1/Makefile b/arch/arm/boards/phycard-a-l1/Makefile deleted file mode 100644 index a71feec..0000000 --- a/arch/arm/boards/phycard-a-l1/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# (C) Copyright 2011 Juergen Kilb -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -obj-y += pca-a-l1.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/phycard-a-l1/env/config b/arch/arm/boards/phycard-a-l1/env/config deleted file mode 100644 index a3f452b..0000000 --- a/arch/arm/boards/phycard-a-l1/env/config +++ /dev/null @@ -1,77 +0,0 @@ -#!/bin/sh - -#user= - -# Enter MAC address here if not retrieved automatically -#eth0.ethaddr=de:ad:be:ef:00:00 - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.serverip=a.b.c.d -#eth0.gateway=a.b.c.d - -# can be either 'tftp', 'nfs', 'nand' or 'disk' -kernel_loc=nand -# can be either 'net', 'nand', 'disk' or 'initrd' -rootfs_loc=nand - -# for flash based rootfs: 'jffs2' or 'ubifs' -# in case of disk any regular filesystem like 'ext2', 'ext3', 'reiserfs' -rootfs_type=jffs2 -# where is the rootfs in case of 'rootfs_loc=disk' (linux name) -rootfs_part_linux_dev=mmcblk0p4 -rootfsimage=rootfs-${global.hostname}.$rootfs_type - -# where is the kernel image in case of 'kernel_loc=disk' -kernel_part=disk0.2 - -# The image type of the kernel. Can be uimage, zimage, raw or raw_lzo -#kernelimage=zImage-${global.hostname} -kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -bareboximage=barebox-${global.hostname}.bin -bareboxenvimage=barebox-${global.hostname}.bin - -if [ -n $user ]; then - bareboximage="$user"-"$bareboximage" - bareboxenvimage="$user"-"$bareboxenvimage" - kernelimage="$user"-"$kernelimage" - rootfsimage="$user"-"$rootfsimage" - nfsroot="/home/$user/nfsroot/${global.hostname}" -else - nfsroot="/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyO2,115200" - -# the following displays are supported -# pd050vl1 (640 x 480) -# pd035vl1 (640 x 480) -# pd104slf (800 x 600) -# pm070wl4 (800 x 480) -# -# omapfb.mode=:,[,...] -# omapfb.debug= -# - Enable debug printing. You have to have OMAPFB debug support enabled -# in kernel config. -# -bootargs="$bootargs omapdss.def_disp=pd050vl1" -#bootargs="$bootargs omapdss.def_disp=pd035vl1" -#bootargs="$bootargs omapdss.def_disp=pd104slf" -#bootargs="$bootargs omapdss.def_disp=pm070wl4" - -nand_parts="128k(x-loader)ro,512k(barebox),128k(bareboxenv),4M(kernel),-(root)" -nand_device=omap2-nand.0 -rootfs_mtdblock_nand=4 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c deleted file mode 100644 index 7a67493..0000000 --- a/arch/arm/boards/phycard-a-l1/lowlevel.c +++ /dev/null @@ -1,264 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Slower full frequency range default timings for x32 operation */ -#define SDP_SDRC_SHARING 0x00000100 -/* Diabling power down mode using CKE pin */ -#define SDP_SDRC_POWER_POP 0x00000081 -/* rkw - need to find of 90/72 degree recommendation for speed like before. */ -#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ - (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) - -/* used to create an array of memory configuartions. */ -struct sdrc_config { - u32 cs_cfg; - u32 mcfg; - u32 mr; - u32 actim_ctrla; - u32 actim_ctrlb; - u32 rfr_ctrl; -} const sdrc_config[] = { -/* max cs_size for autodetection, common timing */ -/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */ -{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201}, -/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */ -{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201}, -/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */ -{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201}, -/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */ -{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201}, -}; - -/* - * Boot-time initialization(s) - */ - -/********************************************************************* - * init_sdram_ddr() - Init DDR controller. - *********************************************************************/ -void init_sdram_ddr(void) -{ - /* reset sdrc controller */ - writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG)); - wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000); - writel(0, OMAP3_SDRC_REG(SYSCONFIG)); - - /* setup sdrc to ball mux */ - writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING)); - writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER)); - - /* set up dll */ - writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL)); - sdelay(0x2000); /* give time to lock */ - -} -/********************************************************************* - * config_sdram_ddr() - Init DDR on dev board. - *********************************************************************/ -void config_sdram_ddr(u8 cs, u8 cfg) -{ - - writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs)); - writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs)); - writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs)); - writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs)); - - writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - - sdelay(5000); - - writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - - /* set mr0 */ - writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs)); - - sdelay(2000); -} - -/** - * @brief Initialize the SDRC module - * Initialisation for 1x256MByte but normally - * done by x-loader. - * @return void - */ -static void pcaal1_sdrc_init(void) -{ - u32 test0, test1; - char cfg; - - init_sdram_ddr(); - - config_sdram_ddr(0, 0); /* 256MByte at CS0 */ - config_sdram_ddr(1, 0); /* 256MByte at CS1 */ - - test0 = get_ram_size((long *) 0x80000000, SZ_256M); - test1 = get_ram_size((long *) 0xA0000000, SZ_256M); - - /* mask out lower nible, its not tested with - in common/memsize.c */ - test1 &= 0xfffffff0; - - if ((test1 > 0) && (test1 != test0)) - hang(); - - cfg = -1; /* illegal configuration found */ - - if (test1 == 0) { - init_sdram_ddr(); - writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1)); - - /* 1 x 256MByte */ - if (test0 == SZ_256M) - cfg = 2; - - if (cfg != -1) { - config_sdram_ddr(0, cfg); - writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG)); - } - return; - } - - /* reinit both cs with correct size */ - /* 2 x 128MByte */ - if (test0 == SZ_128M) - cfg = 1; - /* 2 x 256MByte */ - if (test0 == SZ_256M) - cfg = 3; - - if (cfg != -1) { - init_sdram_ddr(); - writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG)); - config_sdram_ddr(0, cfg); - config_sdram_ddr(1, cfg); - } -} - -/** - * @brief Do the necessary pin muxing required for phyCARD-A-L1. - * Some pins in OMAP3 do not have alternate modes. - * We don't program these pins. - * - * See @ref MUX_VAL for description of the muxing mode. - * - * @return void - */ -static void pcaal1_mux_config(void) -{ - /* - * Serial Interface - */ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M0)); - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); - - /* GPMC */ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); - - /* ETH_PME (GPIO_55) */ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M4)); - /* #CS5 (Ethernet) */ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); - /* ETH_FIFO_SEL (GPIO_57) */ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M4)); - /* ETH_AMDIX_EN (GPIO_58) */ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M4)); - /* ETH_nRST (GPIO_64) */ - MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTU | EN | M4)); - - /* HSMMC1 */ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); - - /* USBOTG_nRST (GPIO_63) */ - MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4)); - - /* USBH_nRST (GPIO_65) */ - MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)); -} - -/** - * @brief The basic entry point for board initialization. - * - * This is called as part of machine init (after arch init). - * This is again called with stack in SRAM, so not too many - * constructs possible here. - * - * @return void - */ -static int pcaal1_board_init(void) -{ - int in_sdram = omap3_running_in_sdram(); - - if (!in_sdram) - omap3_core_init(); - - pcaal1_mux_config(); - /* Dont reconfigure SDRAM while running in SDRAM! */ - if (!in_sdram) - pcaal1_sdrc_init(); - - return 0; -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) -{ - omap3_save_bootinfo(data); - - arm_cpu_lowlevel_init(); - - pcaal1_board_init(); - - barebox_arm_entry(0x80000000, SZ_256M, 0); -} diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.c b/arch/arm/boards/phycard-a-l1/pca-a-l1.c deleted file mode 100644 index 68a17bf..0000000 --- a/arch/arm/boards/phycard-a-l1/pca-a-l1.c +++ /dev/null @@ -1,173 +0,0 @@ -/** - * @file - * @brief Board Initialization routines for the phyCARD-A-L1 - * - * This board is based on OMAP3530. - * More on OMAP3530 (including documentation can be found here): - * http://focus.ti.com/docs/prod/folders/print/omap3530.html - * - * This file provides initialization in two stages: - * @li Boot time initialization - just get SDRAM working. - * This is run from SRAM - so no case constructs and global vars can be used. - * @li Run time initialization - this is for the rest of the initializations - * such as flash, uart etc. - * - * Boot time initialization includes: - * @li SDRAM initialization. - * @li Pin Muxing relevant for the EVM. - * - * Run time initialization includes - * @li serial @ref serial_ns16550.c driver device definition - * - * Originally from arch/arm/boards/omap/board-beagle.c - * - * Copyright (C) 2011 Phytec Messtechnik GmbH - http://www.phytec.de/ - * Juergen Kilb - * - * based on code from Texas Instruments / board-beagle.c - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * Sanjeev Premi - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SMC911X_BASE 0x2c000000 - -/** - * @brief Initialize the serial port to be used as console. - * - * @return result of device registration - */ -static int pcaal1_init_console(void) -{ - barebox_set_model("Phytec phyCARD-OMAP3"); - barebox_set_hostname("phycard-omap3"); - - omap3_add_uart3(); - - return 0; -} -console_initcall(pcaal1_init_console); - -#ifdef CONFIG_DRIVER_NET_SMC911X -/** GPMC timing for our SMSC9221 device */ -static struct gpmc_config smsc_cfg = { - .cfg = { - 0x41001000, /*CONF1 */ - 0x00040500, /*CONF2 */ - 0x00000000, /*CONF3 */ - 0x04000500, /*CONF4 */ - 0x05050505, /*CONF5 */ - 0x000002c1, /*CONF6 */ - }, - .base = SMC911X_BASE, - /* GPMC address map as small as possible */ - .size = GPMC_SIZE_16M, -}; - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void pcaal1_setup_net_chip(void) -{ - gpmc_cs_config(5, &smsc_cfg); -} -#endif - -static int pcaal1_mem_init(void) -{ - -#ifdef CONFIG_OMAP_GPMC - /* - * WP is made high and WAIT1 active Low - */ - gpmc_generic_init(0x10); -#endif - omap3_add_sram0(); - - - omap_add_ram0(get_sdr_cs_size(SDRC_CS0_OSET)); - printf("found %s at SDCS0\n", size_human_readable(get_sdr_cs_size(SDRC_CS0_OSET))); - - if ((get_sdr_cs_size(SDRC_CS1_OSET) != 0) && (get_sdr_cs1_base() != OMAP_SDRC_CS0)) { - arm_add_mem_device("ram1", get_sdr_cs1_base(), get_sdr_cs_size(SDRC_CS1_OSET)); - printf("found %s at SDCS1\n", size_human_readable(get_sdr_cs_size(SDRC_CS1_OSET))); - } - - return 0; -} -mem_initcall(pcaal1_mem_init); - -struct omap_hsmmc_platform_data pcaal1_hsmmc_plat = { - .f_max = 26000000, -}; - -static struct gpmc_nand_platform_data nand_plat = { - .device_width = 16, - .ecc_mode = OMAP_ECC_BCH8_CODE_HW, - .nand_cfg = &omap3_nand_cfg, -}; - -static int pcaal1_init_devices(void) -{ - omap_add_gpmc_nand_device(&nand_plat); - - omap3_add_mmc1(&pcaal1_hsmmc_plat); - -#ifdef CONFIG_DRIVER_NET_SMC911X - pcaal1_setup_net_chip(); - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, SMC911X_BASE, SZ_4K, - IORESOURCE_MEM, NULL); -#endif - - armlinux_set_architecture(MACH_TYPE_PCAAL1); - - return 0; -} -device_initcall(pcaal1_init_devices); - -static int pcaal1_late_init(void) -{ -#ifdef CONFIG_PARTITION - devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "x-loader"); - dev_add_bb_dev("self_raw", "x_loader0"); - - devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - return 0; -} -late_initcall(pcaal1_late_init); diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.dox b/arch/arm/boards/phycard-a-l1/pca-a-l1.dox deleted file mode 100644 index d93c574..0000000 --- a/arch/arm/boards/phycard-a-l1/pca-a-l1.dox +++ /dev/null @@ -1,16 +0,0 @@ -/** @page phycard-a-l1 Phytec's phyCARD-A-L1 (OMAP35xx) - -This phyCARD is based on a Texas Instruments OMAP35xx CPU. -The card is shipped with: - -- 256MiB DDR-RAM -- 256MiB NAND Flash Memory -- SMSC9221 ethernet controller -- USB-host interface -- USB-OTG interface -- LVDS camera interface -- LVDS display interface -- TPS65023 Power-Managmanet IC -- 4kB I2C EEPROM - -*/ diff --git a/arch/arm/boards/phycard-a-l1/pca-a-l1.h b/arch/arm/boards/phycard-a-l1/pca-a-l1.h deleted file mode 100644 index f6f8996..0000000 --- a/arch/arm/boards/phycard-a-l1/pca-a-l1.h +++ /dev/null @@ -1,28 +0,0 @@ -/** - * @file - * @brief exported generic APIs which various board files implement - * - * This file will not contain any board specific implementations. - * - * (C) Copyright 2008 - * Texas Instruments, - * Raghavendra KH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __BOARD_OMAP_H_ -#define __BOARD_OMAP_H_ - -/** Generic Board initialization called from platform.S */ -void board_init(void); - -#endif /* __BOARD_OMAP_H_ */ diff --git a/arch/arm/boards/phycard-a-xl2/Makefile b/arch/arm/boards/phycard-a-xl2/Makefile deleted file mode 100644 index 64782e0..0000000 --- a/arch/arm/boards/phycard-a-xl2/Makefile +++ /dev/null @@ -1,17 +0,0 @@ -# (C) Copyright 2012 Jan Weitzel -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -obj-y += pca-a-xl2.o -lwl-y += mux.o lowlevel.o diff --git a/arch/arm/boards/phycard-a-xl2/env/bin/nand_bootstrap b/arch/arm/boards/phycard-a-xl2/env/bin/nand_bootstrap deleted file mode 100644 index f8873fa..0000000 --- a/arch/arm/boards/phycard-a-xl2/env/bin/nand_bootstrap +++ /dev/null @@ -1,31 +0,0 @@ - -echo "copying barebox to nand..." - -mci0.probe=1 -mkdir mnt - -mount /dev/disk0.0 /mnt -if [ $? != 0 ]; then - echo "failed to mount mmc card" - exit 1 -fi - -if [ ! -f /mnt/mlo-nand.bin ]; then - echo "mlo-nand.bin not found on mmc card" - exit 1 -fi - -if [ ! -f /mnt/barebox.bin ]; then - echo "barebox.bin not found on mmc card" -fi - -gpmc_nand0.eccmode=bch8_hw_romcode -erase /dev/nand0.xload.bb -cp /mnt/mlo-nand.bin /dev/nand0.xload.bb - -gpmc_nand0.eccmode=bch8_hw -erase /dev/nand0.barebox.bb -cp /mnt/barebox.bin /dev/nand0.barebox.bb - -echo "success" - diff --git a/arch/arm/boards/phycard-a-xl2/env/config b/arch/arm/boards/phycard-a-xl2/env/config deleted file mode 100644 index 998f9fa..0000000 --- a/arch/arm/boards/phycard-a-xl2/env/config +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/sh - -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyO2,115200" - -nand_parts="128k(xload)ro,512k(barebox),128k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nand=4 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c deleted file mode 100644 index 1ddf8a0..0000000 --- a/arch/arm/boards/phycard-a-xl2/lowlevel.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2004-2009 - * Texas Instruments, - * Richard Woodruff - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TPS62361_VSEL0_GPIO 7 - -void set_muxconf_regs(void); - -static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { - .tim1 = 0x0EEB0662, - .tim2 = 0x20370DD2, - .tim3 = 0x00BFC33F, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80001AB1, - .config_final = 0x80001AB1, - .zq_config = 0xd0093215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -static noinline void pcaaxl2_init_lowlevel(void) -{ - struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; - struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; - struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; - struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; - struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; - struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; - unsigned int rev = omap4_revision(); - - set_muxconf_regs(); - - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); - - if (rev < OMAP4460_ES1_0) - omap4430_scale_vcores(); - else - omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); - - writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); - - /* Configure all DPLL's at 100% OPP */ - if (rev < OMAP4460_ES1_0) - omap4_configure_mpu_dpll(&mpu44xx); - else - omap4_configure_mpu_dpll(&mpu4460); - - omap4_configure_iva_dpll(&iva); - omap4_configure_per_dpll(&per); - omap4_configure_abe_dpll(&abe); - omap4_configure_usb_dpll(&usb); - - /* Enable all clocks */ - omap4_enable_all_clocks(); - - sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ - sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ - sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */ - sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ - sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) -{ - omap4_save_bootinfo(data); - - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) - goto out; - - arm_setup_stack(0x4030d000); - - pcaaxl2_init_lowlevel(); -out: - barebox_arm_entry(0x80000000, SZ_512M, 0); -} diff --git a/arch/arm/boards/phycard-a-xl2/mux.c b/arch/arm/boards/phycard-a-xl2/mux.c deleted file mode 100644 index a31d995..0000000 --- a/arch/arm/boards/phycard-a-xl2/mux.c +++ /dev/null @@ -1,253 +0,0 @@ -#include -#include -#include -#include -#include -#include - -static const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ - {GPMC_AD1, (IEN | PTD | DIS | M0)}, /* gpmc_ad1 */ - {GPMC_AD2, (IEN | PTD | DIS | M0)}, /* gpmc_ad2 */ - {GPMC_AD3, (IEN | PTD | DIS | M0)}, /* gpmc_ad3 */ - {GPMC_AD4, (IEN | PTD | DIS | M0)}, /* gpmc_ad4 */ - {GPMC_AD5, (IEN | PTD | DIS | M0)}, /* gpmc_ad5 */ - {GPMC_AD6, (IEN | PTD | DIS | M0)}, /* gpmc_ad6 */ - {GPMC_AD7, (IEN | PTD | DIS | M0)}, /* gpmc_ad7 */ - {GPMC_AD8, (IEN | PTD | DIS | M0)}, /* gpmc_ad8 */ - {GPMC_AD9, (IEN | PTD | DIS | M0)}, /* gpmc_ad9 */ - {GPMC_AD10, (IEN | PTD | DIS | M0)}, /* gpmc_ad10 */ - {GPMC_AD11, (IEN | PTD | DIS | M0)}, /* gpmc_ad11 */ - {GPMC_AD12, (IEN | PTD | DIS | M0)}, /* gpmc_ad12 */ - {GPMC_AD13, (IEN | PTD | DIS | M0)}, /* gpmc_ad13 */ - {GPMC_AD14, (IEN | PTD | DIS | M0)}, /* gpmc_ad14 */ - {GPMC_AD15, (IEN | PTD | DIS | M0)}, /* gpmc_ad15 */ - {GPMC_A16, (IEN | PTD | DIS | M0)}, /* gpmc_a16 */ - {GPMC_A17, (SAFE_MODE)}, /* nc */ - {GPMC_A18, (SAFE_MODE)}, /* nc */ - {GPMC_A19, (SAFE_MODE)}, /* nc */ - {GPMC_A20, (SAFE_MODE)}, /* nc */ - {GPMC_A21, (SAFE_MODE)}, /* nc */ - {GPMC_A22, (SAFE_MODE)}, /* nc */ - {GPMC_A23, (SAFE_MODE)}, /* nc */ - {GPMC_A24, (SAFE_MODE)}, /* nc */ - {GPMC_A25, (SAFE_MODE)}, /* nc */ - {GPMC_NCS0, (IDIS | PTU | EN | M0)}, /* gpmc_nsc0 */ - {GPMC_NCS1, (IDIS | PTU | EN | M0)}, /* gpmc_nsc1 */ - {GPMC_NCS2, (SAFE_MODE)}, /* nc */ - {GPMC_NCS3, (SAFE_MODE)}, /* nc */ - {GPMC_NWP, (IEN | PTD | DIS | M0)}, /* gpmc_nwp */ - {GPMC_CLK, (PTU | IEN | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)}, /* gpmc_ndav_ale */ - {GPMC_NOE, (IDIS | PTD | DIS | M0)}, /* gpmc_noe */ - {GPMC_NWE, (IDIS | PTD | DIS | M0)}, /* gpmc_nwe */ - {GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)}, /* gpmc_nbe0_cle */ - {GPMC_NBE1, (SAFE_MODE)}, /* nc */ - {GPMC_WAIT0, (IEN | PTU | EN | M0)}, /* gpmc_wait0 */ - {GPMC_WAIT1, (IEN | PTU | EN | M0)}, /* gpmc_wait1 */ - {C2C_DATA11, (SAFE_MODE)}, /* nc */ - {C2C_DATA12, (SAFE_MODE)}, /* nc */ - {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */ - {C2C_DATA14, (SAFE_MODE)}, /* nc */ - {C2C_DATA15, (SAFE_MODE)}, /* nc */ - {HDMI_HPD, (SAFE_MODE)}, /* nc */ - {HDMI_CEC, (SAFE_MODE)}, /* nc */ - {HDMI_DDC_SCL, (SAFE_MODE)}, /* nc */ - {HDMI_DDC_SDA, (SAFE_MODE)}, /* nc */ - {CSI21_DX0, (SAFE_MODE)}, /* nc */ - {CSI21_DY0, (SAFE_MODE)}, /* nc */ - {CSI21_DX1, (SAFE_MODE)}, /* nc */ - {CSI21_DY1, (SAFE_MODE)}, /* nc */ - {CSI21_DX2, (SAFE_MODE)}, /* nc */ - {CSI21_DY2, (SAFE_MODE)}, /* nc */ - {CSI21_DX3, (SAFE_MODE)}, /* nc */ - {CSI21_DY3, (SAFE_MODE)}, /* nc */ - {CSI21_DX4, (SAFE_MODE)}, /* nc */ - {CSI21_DY4, (SAFE_MODE)}, /* nc */ - {CSI22_DX0, (SAFE_MODE)}, /* nc */ - {CSI22_DY0, (SAFE_MODE)}, /* nc */ - {CSI22_DX1, (SAFE_MODE)}, /* nc */ - {CSI22_DY1, (SAFE_MODE)}, /* nc */ - {CAM_SHUTTER, (SAFE_MODE)}, /* unused */ - {CAM_STROBE, (SAFE_MODE)}, /* unused */ - {CAM_GLOBALRESET, (SAFE_MODE)}, /* unused */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (SAFE_MODE)}, /* nc */ - {USBB1_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {USBC1_ICUSB_DP, (SAFE_MODE)}, /* nc */ - {USBC1_ICUSB_DM, (SAFE_MODE)}, /* nc */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (SAFE_MODE)}, /* nc */ - {SDMMC1_DAT5, (SAFE_MODE)}, /* nc */ - {SDMMC1_DAT6, (SAFE_MODE)}, /* nc */ - {SDMMC1_DAT7, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_CLKX, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_DR, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_DX, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_FSX, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP1_CLKX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DR, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_FSX, (SAFE_MODE)}, /* nc */ - {ABE_PDM_UL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_DL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_FRAME, (SAFE_MODE)}, /* unused */ - {ABE_PDM_LB_CLK, (SAFE_MODE)}, /* unused */ - {ABE_CLKS, (SAFE_MODE)}, /* unused */ - {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN1, (SAFE_MODE)}, /* unused */ - {ABE_DMIC_DIN2, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN3, (SAFE_MODE)}, /* unused */ - {UART2_CTS, (SAFE_MODE)}, /* nc */ - {UART2_RTS, (SAFE_MODE)}, /* nc */ - {UART2_RX, (SAFE_MODE)}, /* nc */ - {UART2_TX, (SAFE_MODE)}, /* nc */ - {HDQ_SIO, (SAFE_MODE)}, /* unused */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (SAFE_MODE)}, /* unused */ - {I2C2_SDA, (SAFE_MODE)}, /* unused */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (SAFE_MODE)}, /* nc */ - {I2C4_SDA, (SAFE_MODE)}, /* nc */ - {MCSPI1_CLK, (SAFE_MODE)}, /* unused */ - {MCSPI1_SOMI, (SAFE_MODE)}, /* unused */ - {MCSPI1_SIMO, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS0, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS1, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS2, (SAFE_MODE)}, /* nc */ - {MCSPI1_CS3, (SAFE_MODE)}, /* nc */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ - {SDMMC5_CLK, (PTU | IEN | M3)}, /* goio_145 */ - {SDMMC5_CMD, (PTU | IEN | M3)}, /* goio_146 */ - {SDMMC5_DAT0, (SAFE_MODE)}, /* nc */ - {SDMMC5_DAT1, (SAFE_MODE)}, /* nc */ - {SDMMC5_DAT2, (SAFE_MODE)}, /* nc */ - {SDMMC5_DAT3, (SAFE_MODE)}, /* nc */ - {MCSPI4_CLK, (PTU | IEN | M3)}, /* gpio_151 */ - {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */ - {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */ - {MCSPI4_CS0, (SAFE_MODE)}, /* nc */ - {UART4_RX, (SAFE_MODE)}, /* nc */ - {UART4_TX, (SAFE_MODE)}, /* nc */ - {USBB2_ULPITLL_CLK, (SAFE_MODE)}, /* nc */ - {USBB2_ULPITLL_STP, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DIR, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_NXT, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT0, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT1, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT2, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT3, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT4, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT5, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT6, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT7, (SAFE_MODE)}, /* unused */ - {USBB2_HSIC_DATA, (SAFE_MODE)}, /* unused */ - {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX0, (SAFE_MODE)}, /* nc */ - {UNIPRO_TY0, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX1, (SAFE_MODE)}, /* nc */ - {UNIPRO_TY1, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY2, (SAFE_MODE)}, /* unused */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */ - {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (SAFE_MODE)}, /* nc */ - {SYS_BOOT0, (M0)}, /* sys_boot */ - {SYS_BOOT1, (M0)}, /* sys_boot */ - {SYS_BOOT2, (M0)}, /* sys_boot */ - {SYS_BOOT3, (M0)}, /* sys_boot */ - {SYS_BOOT4, (M0)}, /* sys_boot */ - {SYS_BOOT5, (M0)}, /* sys_boot */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (SAFE_MODE)}, /* unused */ - {DPM_EMU3, (SAFE_MODE)}, /* unused */ - {DPM_EMU4, (SAFE_MODE)}, /* unused */ - {DPM_EMU5, (SAFE_MODE)}, /* unused */ - {DPM_EMU6, (SAFE_MODE)}, /* unused */ - {DPM_EMU7, (SAFE_MODE)}, /* unused */ - {DPM_EMU8, (SAFE_MODE)}, /* unused */ - {DPM_EMU9, (SAFE_MODE)}, /* unused */ - {DPM_EMU10, (SAFE_MODE)}, /* unused */ - {DPM_EMU11, (SAFE_MODE)}, /* unused */ - {DPM_EMU12, (SAFE_MODE)}, /* unused */ - {DPM_EMU13, (SAFE_MODE)}, /* unused */ - {DPM_EMU14, (SAFE_MODE)}, /* unused */ - {DPM_EMU15, (SAFE_MODE)}, /* unused */ - {DPM_EMU16, (SAFE_MODE)}, /* unused */ - {DPM_EMU17, (SAFE_MODE)}, /* unused */ - {DPM_EMU18, (SAFE_MODE)}, /* unused */ - {DPM_EMU19, (SAFE_MODE)}, /* unused */ -}; - -static const struct pad_conf_entry wkup_padconf_array[] = { - {GPIO_WK0, (SAFE_MODE)}, /* tbd */ - {GPIO_WK1, (SAFE_MODE)}, /* nc */ - {GPIO_WK2, (SAFE_MODE)}, /* nc */ - {GPIO_WK3, (SAFE_MODE)}, /* nc */ - {GPIO_WK4, (SAFE_MODE)}, /* nc */ - {SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ - {FREF_XTAL_IN, (M0)}, /* # */ - {FREF_SLICER_IN, (SAFE_MODE)}, /* nc */ - {FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ - {FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {FREF_CLK3_REQ, (SAFE_MODE)}, /* nc */ - {FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {FREF_CLK4_REQ, (IEN | M3)}, /* gpio_wk7 */ - {FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */ - {SYS_32K, (IEN | M0)}, /* sys_32k */ - {SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {SYS_PWRON_RESET_OUT, (M0)}, /* sys_pwron_reset_out */ - {SYS_BOOT6, (M0)}, /* sys_boot6 */ - {SYS_BOOT7, (M0)}, /* sys_boot7 */ -}; - -void set_muxconf_regs(void) -{ - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, - ARRAY_SIZE(core_padconf_array)); - - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, - ARRAY_SIZE(wkup_padconf_array)); - - /* gpio_wk7 is used for controlling TPS on 4460 */ - if (omap4_revision() >= OMAP4460_ES1_0) { - writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ); - /* Enable GPIO-1 clocks before TPS initialization */ - omap4_enable_gpio1_wup_clocks(); - } -} diff --git a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c b/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c deleted file mode 100644 index 6429722..0000000 --- a/arch/arm/boards/phycard-a-xl2/pca-a-xl2.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 2011 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int pcaaxl2_console_init(void) -{ - barebox_set_model("Phytec phyCARD-OMAP4"); - barebox_set_hostname("phycard-omap4"); - - omap44xx_add_uart3(); - - return 0; -} -console_initcall(pcaaxl2_console_init); - -static int pcaaxl2_mem_init(void) -{ - omap_add_ram0(SZ_512M); - - omap44xx_add_sram0(); - - return 0; -} -mem_initcall(pcaaxl2_mem_init); - -static struct gpmc_config net_cfg = { - .cfg = { - 0x00001000, /* CONF1 */ - 0x00080800, /* CONF2 */ - 0x00000000, /* CONF3 */ - 0x08000800, /* CONF4 */ - 0x000a0a0a, /* CONF5 */ - 0x000003c2, /* CONF6 */ - }, - .base = 0x2C000000, - .size = GPMC_SIZE_16M, -}; - -static void pcaaxl2_network_init(void) -{ - gpmc_cs_config(5, &net_cfg); - - add_ks8851_device(DEVICE_ID_DYNAMIC, net_cfg.base, net_cfg.base + 2, - IORESOURCE_MEM_16BIT, NULL); -} - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("twlcore", 0x48), - }, -}; - -static struct omap_hsmmc_platform_data mmc_device = { - .f_max = 26000000, -}; - -#define OMAP4_CONTROL_PBIASLITE 0x4A100600 -#define OMAP4_MMC1_PBIASLITE_VMODE (1<<21) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1<<22) -#define OMAP4_MMC1_PWRDNZ (1<<26) - -static struct gpmc_nand_platform_data nand_plat = { - .device_width = 16, - .ecc_mode = OMAP_ECC_BCH8_CODE_HW, - .nand_cfg = &omap4_nand_cfg, -}; - -static int pcaaxl2_devices_init(void) -{ - u32 value; - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - omap44xx_add_i2c1(NULL); - - value = readl(OMAP4_CONTROL_PBIASLITE); - value &= ~OMAP4_MMC1_PBIASLITE_VMODE; - value |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ); - writel(value, OMAP4_CONTROL_PBIASLITE); - - omap44xx_add_mmc1(&mmc_device); - - gpmc_generic_init(0x10); - - pcaaxl2_network_init(); - - omap_add_gpmc_nand_device(&nand_plat); - -#ifdef CONFIG_PARTITION - devfs_add_partition("nand0", 0x00000, SZ_128K, - DEVFS_PARTITION_FIXED, "xload_raw"); - dev_add_bb_dev("xload_raw", "xload"); - devfs_add_partition("nand0", SZ_128K, SZ_512K, - DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, - DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - - armlinux_set_architecture(MACH_TYPE_PCAAXL2); - - return 0; -} -device_initcall(pcaaxl2_devices_init); diff --git a/arch/arm/boards/phycard-i.MX27/Makefile b/arch/arm/boards/phycard-i.MX27/Makefile deleted file mode 100644 index 34492bb..0000000 --- a/arch/arm/boards/phycard-i.MX27/Makefile +++ /dev/null @@ -1,3 +0,0 @@ - -lwl-y += lowlevel.o -obj-y += pca100.o diff --git a/arch/arm/boards/phycard-i.MX27/lowlevel.c b/arch/arm/boards/phycard-i.MX27/lowlevel.c deleted file mode 100644 index 5b3bdaf..0000000 --- a/arch/arm/boards/phycard-i.MX27/lowlevel.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia - * Applications Processor Reference Manual, Rev. 0.2". - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) - -static void sdram_init(void) -{ - int i; - - /* - * DDR on CSD0 - */ - /* Enable DDR SDRAM operation */ - writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - - /* Set the driving strength */ - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); - writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); - writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); - writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); - - /* Initial reset */ - writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); - writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); - - /* precharge CSD0 all banks */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */ - writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - - for (i = 0; i < 8; i++) - writel(0, 0xa0000f00); - - writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); - writeb(0xda, 0xa0000033); - writeb(0xff, 0xa1000000); - - writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | - ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, - MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); -} - -void __bare_init __naked barebox_arm_reset_vector(void) -{ - unsigned long r; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); - - /* ahb lite ip interface */ - writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); - writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); - writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); - writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); - - /* Skip SDRAM initialization if we run from RAM */ - r = get_pc(); - if (r > 0xa0000000 && r < 0xc0000000) - imx27_barebox_entry(0); - - /* 399 MHz */ - writel(IMX_PLL_PD(0) | - IMX_PLL_MFD(51) | - IMX_PLL_MFI(7) | - IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0); - - /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ - writel(IMX_PLL_PD(1) | - IMX_PLL_MFD(12) | - IMX_PLL_MFI(9) | - IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0); - - writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | - MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | - MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | - MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | - MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | - MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | - MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | - MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR); - - sdram_init(); - - imx27_barebox_boot_nand_external(0); -} diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c deleted file mode 100644 index 4b355bc..0000000 --- a/arch/arm/boards/phycard-i.MX27/pca100.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (C) 2007 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void pca100_usb_register(void) -{ - mdelay(10); - - gpio_direction_output(GPIO_PORTB + 24, 0); - gpio_direction_output(GPIO_PORTB + 23, 0); - - mdelay(10); - - ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL); - ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); -} - -static void pca100_usb_init(void) -{ - u32 reg; - - reg = readl(MX27_USB_OTG_BASE_ADDR + 0x600); - reg &= ~((3 << 21) | 1); - reg |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); - writel(reg, MX27_USB_OTG_BASE_ADDR + 0x600); - - /* - * switch usbotg and usbh2 to ulpi mode. Do this *before* - * the iomux setup to prevent funny hardware bugs from - * triggering. Also, do this even when USB support is - * disabled to give Linux USB support a good start. - */ - reg = readl(MX27_USB_OTG_BASE_ADDR + 0x584); - reg &= ~(3 << 30); - reg |= 2 << 30; - writel(reg, MX27_USB_OTG_BASE_ADDR + 0x584); - - reg = readl(MX27_USB_OTG_BASE_ADDR + 0x184); - reg &= ~(3 << 30); - reg |= 2 << 30; - writel(reg, MX27_USB_OTG_BASE_ADDR + 0x184); - - /* disable the usb phys */ - imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN); - gpio_direction_output(GPIO_PORTB + 23, 1); - imx_gpio_mode((GPIO_PORTB | 24) | GPIO_GPIO | GPIO_IN); - gpio_direction_output(GPIO_PORTB + 24, 1); -} - -static int pca100_devices_init(void) -{ - int i; - unsigned int mode[] = { - /* USB host 2 */ - PA0_PF_USBH2_CLK, - PA1_PF_USBH2_DIR, - PA2_PF_USBH2_DATA7, - PA3_PF_USBH2_NXT, - PA4_PF_USBH2_STP, - PD19_AF_USBH2_DATA4, - PD20_AF_USBH2_DATA3, - PD21_AF_USBH2_DATA6, - PD22_AF_USBH2_DATA0, - PD23_AF_USBH2_DATA2, - PD24_AF_USBH2_DATA1, - PD26_AF_USBH2_DATA5, - PC7_PF_USBOTG_DATA5, - PC8_PF_USBOTG_DATA6, - PC9_PF_USBOTG_DATA0, - PC10_PF_USBOTG_DATA2, - PC11_PF_USBOTG_DATA1, - PC12_PF_USBOTG_DATA4, - PC13_PF_USBOTG_DATA3, - PE0_PF_USBOTG_NXT, - PE1_PF_USBOTG_STP, - PE2_PF_USBOTG_DIR, - PE24_PF_USBOTG_CLK, - PE25_PF_USBOTG_DATA7, - }; - - pca100_usb_init(); - - /* initizalize gpios */ - for (i = 0; i < ARRAY_SIZE(mode); i++) - imx_gpio_mode(mode[i]); - - if (IS_ENABLED(CONFIG_USB)) - pca100_usb_register(); - - imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot", - BBU_HANDLER_FLAG_DEFAULT); - - armlinux_set_architecture(2149); - - return 0; -} - -device_initcall(pca100_devices_init); - -static int pca100_console_init(void) -{ - barebox_set_model("Phytec phyCARD-i.MX27"); - barebox_set_hostname("phycard-imx27"); - - return 0; -} - -console_initcall(pca100_console_init); diff --git a/arch/arm/boards/phycard-i.MX27/pca100.dox b/arch/arm/boards/phycard-i.MX27/pca100.dox deleted file mode 100644 index 9b17674..0000000 --- a/arch/arm/boards/phycard-i.MX27/pca100.dox +++ /dev/null @@ -1,8 +0,0 @@ -/** @page pcm038 Phytec's phyCORE-i.MX27 - -This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: - -- up to 32MiB NOR type Flash Memory -- 32MiB synchronous dynamic RAM - -*/ diff --git a/arch/arm/boards/phytec-pfla02/Makefile b/arch/arm/boards/phytec-pfla02/Makefile deleted file mode 100644 index 93e7308..0000000 --- a/arch/arm/boards/phytec-pfla02/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -obj-y += board.o -obj-y += flash-header-phytec-pfla02-1gib.dcd.o flash-header-phytec-pfla02-2gib.dcd.o -extra-y += flash-header-phytec-pfla02-1gib.dcd.S flash-header-phytec-pfla02-2gib.dcd.S -extra-y += flash-header-phytec-pfla02-1gib.dcd flash-header-phytec-pfla02-2gib.dcd -lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-pfla02/board.c b/arch/arm/boards/phytec-pfla02/board.c deleted file mode 100644 index e9bd168..0000000 --- a/arch/arm/boards/phytec-pfla02/board.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ - -#include -#include -#include -#include - -#include - -#define ETH_PHY_RST IMX_GPIO_NR(3, 23) - -static int eth_phy_reset(void) -{ - gpio_request(ETH_PHY_RST, "phy reset"); - gpio_direction_output(ETH_PHY_RST, 0); - mdelay(1); - gpio_set_value(ETH_PHY_RST, 1); - - return 0; -} - -static int phytec_pfla02_init(void) -{ - if (!of_machine_is_compatible("phytec,imx6q-pfla02")) - return 0; - - eth_phy_reset(); - - return 0; -} -device_initcall(phytec_pfla02_init); - -static int phytec_pfla02_core_init(void) -{ - if (!of_machine_is_compatible("phytec,imx6q-pfla02")) - return 0; - - imx6_init_lowlevel(); - - return 0; -} -postcore_initcall(phytec_pfla02_core_init); diff --git a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-1gib.imxcfg deleted file mode 100644 index 524ebca..0000000 --- a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-1gib.imxcfg +++ /dev/null @@ -1,6 +0,0 @@ - -#define SETUP_1GIB_2GIB \ - wm 32 0x021b0040 0x00000017; \ - wm 32 0x021b0000 0xc21a0000 - -#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-2gib.imxcfg deleted file mode 100644 index bf6e0ab..0000000 --- a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-2gib.imxcfg +++ /dev/null @@ -1,6 +0,0 @@ - -#define SETUP_1GIB_2GIB \ - wm 32 0x021b0040 0x00000027; \ - wm 32 0x021b0000 0xC31A0000 - -#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02.h deleted file mode 100644 index b90f7cb..0000000 --- a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02.h +++ /dev/null @@ -1,99 +0,0 @@ -soc imx6 -loadaddr 0x20000000 -dcdofs 0x400 - -wm 32 0x020e05a8 0x00000030 -wm 32 0x020e05b0 0x00000030 -wm 32 0x020e0524 0x00000030 -wm 32 0x020e051c 0x00000030 -wm 32 0x020e0518 0x00000030 -wm 32 0x020e050c 0x00000030 -wm 32 0x020e05b8 0x00000030 -wm 32 0x020e05c0 0x00000030 -wm 32 0x020e05ac 0x00020030 -wm 32 0x020e05b4 0x00020030 -wm 32 0x020e0528 0x00020030 -wm 32 0x020e0520 0x00020030 -wm 32 0x020e0514 0x00020030 -wm 32 0x020e0510 0x00020030 -wm 32 0x020e05bc 0x00020030 -wm 32 0x020e05c4 0x00020030 -wm 32 0x020e056c 0x00020030 -wm 32 0x020e0578 0x00020030 -wm 32 0x020e0588 0x00020030 -wm 32 0x020e0594 0x00020030 -wm 32 0x020e057c 0x00020030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00003030 -wm 32 0x020e05a0 0x00003030 -wm 32 0x020e0784 0x00000030 -wm 32 0x020e0788 0x00000030 -wm 32 0x020e0794 0x00000030 -wm 32 0x020e079c 0x00000030 -wm 32 0x020e07a0 0x00000030 -wm 32 0x020e07a4 0x00000030 -wm 32 0x020e07a8 0x00000030 -wm 32 0x020e0748 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0798 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00081740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b000c 0x555a7975 -wm 32 0x021b0010 0xff538e64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x005b0e21 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 - -SETUP_1GIB_2GIB - -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1380003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00022227 -wm 32 0x021b4818 0x00022227 -wm 32 0x021b083c 0x433c033f -wm 32 0x021b0840 0x033e033d -wm 32 0x021b483c 0x43490351 -wm 32 0x021b4840 0x0344032f -wm 32 0x021b0848 0x4a434146 -wm 32 0x021b4848 0x4745434b -wm 32 0x021b0850 0x3d3d433a -wm 32 0x021b4850 0x48334b3e -wm 32 0x021b080c 0x000f0011 -wm 32 0x021b0810 0x00200022 -wm 32 0x021b480c 0x0033002e -wm 32 0x021b4810 0x003e003b -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 -wm 32 0x020e0010 0xf00000ff -wm 32 0x020e0018 0x007f007f -wm 32 0x020e001c 0x007f007f -wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-pfla02/lowlevel.c b/arch/arm/boards/phytec-pfla02/lowlevel.c deleted file mode 100644 index 6422bc4..0000000 --- a/arch/arm/boards/phytec-pfla02/lowlevel.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (C) 2013 Sascha Hauer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline void setup_uart(void) -{ - void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR; - void __iomem *uartbase = (void *)MX6_UART4_BASE_ADDR; - void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; - - writel(0x4, iomuxbase + 0x01f8); - - writel(0xffffffff, ccmbase + 0x68); - writel(0xffffffff, ccmbase + 0x6c); - writel(0xffffffff, ccmbase + 0x70); - writel(0xffffffff, ccmbase + 0x74); - writel(0xffffffff, ccmbase + 0x78); - writel(0xffffffff, ccmbase + 0x7c); - writel(0xffffffff, ccmbase + 0x80); - - writel(0x00000000, uartbase + 0x80); - writel(0x00004027, uartbase + 0x84); - writel(0x00000704, uartbase + 0x88); - writel(0x00000a81, uartbase + 0x90); - writel(0x0000002b, uartbase + 0x9c); - writel(0x00013880, uartbase + 0xb0); - writel(0x0000047f, uartbase + 0xa4); - writel(0x0000c34f, uartbase + 0xa8); - writel(0x00000001, uartbase + 0x80); - - putc_ll('>'); -} - -extern char __dtb_imx6q_phytec_pbab01_start[]; - -ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2) -{ - uint32_t fdt; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(0x00920000 - 8); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - - fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); - - barebox_arm_entry(0x10000000, SZ_1G, fdt); -} - -ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2) -{ - uint32_t fdt; - - arm_cpu_lowlevel_init(); - - arm_setup_stack(0x00920000 - 8); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - - fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); - - barebox_arm_entry(0x10000000, SZ_2G, fdt); -} diff --git a/arch/arm/boards/phytec-phycard-imx27/Makefile b/arch/arm/boards/phytec-phycard-imx27/Makefile new file mode 100644 index 0000000..34492bb --- /dev/null +++ b/arch/arm/boards/phytec-phycard-imx27/Makefile @@ -0,0 +1,3 @@ + +lwl-y += lowlevel.o +obj-y += pca100.o diff --git a/arch/arm/boards/phytec-phycard-imx27/lowlevel.c b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c new file mode 100644 index 0000000..5b3bdaf --- /dev/null +++ b/arch/arm/boards/phytec-phycard-imx27/lowlevel.c @@ -0,0 +1,103 @@ +/* + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia + * Applications Processor Reference Manual, Rev. 0.2". + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +static void sdram_init(void) +{ + int i; + + /* + * DDR on CSD0 + */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); + + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x00000000, 0xa0000f00); /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + + for (i = 0; i < 8; i++) + writel(0, 0xa0000f00); + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writeb(0xda, 0xa0000033); + writeb(0xff, 0xa1000000); + + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); +} + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + unsigned long r; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12); + + /* ahb lite ip interface */ + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); + writel(0xdffbfcfb, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); + writel(0xffffffff, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0xa0000000 && r < 0xc0000000) + imx27_barebox_entry(0); + + /* 399 MHz */ + writel(IMX_PLL_PD(0) | + IMX_PLL_MFD(51) | + IMX_PLL_MFI(7) | + IMX_PLL_MFN(35), MX27_CCM_BASE_ADDR + MX27_MPCTL0); + + /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ + writel(IMX_PLL_PD(1) | + IMX_PLL_MFD(12) | + IMX_PLL_MFI(9) | + IMX_PLL_MFN(3), MX27_CCM_BASE_ADDR + MX27_SPCTL0); + + writel(MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART | + MX27_CSCR_ARM_SRC_MPLL | MX27_CSCR_MCU_SEL | + MX27_CSCR_SP_SEL | MX27_CSCR_FPM_EN | + MX27_CSCR_MPEN | MX27_CSCR_SPEN | MX27_CSCR_ARM_DIV(0) | + MX27_CSCR_AHB_DIV(1) | MX27_CSCR_USB_DIV(3) | + MX27_CSCR_SD_CNT(3) | MX27_CSCR_SSI2_SEL | + MX27_CSCR_SSI1_SEL | MX27_CSCR_H264_SEL | + MX27_CSCR_MSHC_SEL, MX27_CCM_BASE_ADDR + MX27_CSCR); + + sdram_init(); + + imx27_barebox_boot_nand_external(0); +} diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.c b/arch/arm/boards/phytec-phycard-imx27/pca100.c new file mode 100644 index 0000000..4b355bc --- /dev/null +++ b/arch/arm/boards/phytec-phycard-imx27/pca100.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void pca100_usb_register(void) +{ + mdelay(10); + + gpio_direction_output(GPIO_PORTB + 24, 0); + gpio_direction_output(GPIO_PORTB + 23, 0); + + mdelay(10); + + ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL); + ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL); +} + +static void pca100_usb_init(void) +{ + u32 reg; + + reg = readl(MX27_USB_OTG_BASE_ADDR + 0x600); + reg &= ~((3 << 21) | 1); + reg |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); + writel(reg, MX27_USB_OTG_BASE_ADDR + 0x600); + + /* + * switch usbotg and usbh2 to ulpi mode. Do this *before* + * the iomux setup to prevent funny hardware bugs from + * triggering. Also, do this even when USB support is + * disabled to give Linux USB support a good start. + */ + reg = readl(MX27_USB_OTG_BASE_ADDR + 0x584); + reg &= ~(3 << 30); + reg |= 2 << 30; + writel(reg, MX27_USB_OTG_BASE_ADDR + 0x584); + + reg = readl(MX27_USB_OTG_BASE_ADDR + 0x184); + reg &= ~(3 << 30); + reg |= 2 << 30; + writel(reg, MX27_USB_OTG_BASE_ADDR + 0x184); + + /* disable the usb phys */ + imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN); + gpio_direction_output(GPIO_PORTB + 23, 1); + imx_gpio_mode((GPIO_PORTB | 24) | GPIO_GPIO | GPIO_IN); + gpio_direction_output(GPIO_PORTB + 24, 1); +} + +static int pca100_devices_init(void) +{ + int i; + unsigned int mode[] = { + /* USB host 2 */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PC9_PF_USBOTG_DATA0, + PC10_PF_USBOTG_DATA2, + PC11_PF_USBOTG_DATA1, + PC12_PF_USBOTG_DATA4, + PC13_PF_USBOTG_DATA3, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PE2_PF_USBOTG_DIR, + PE24_PF_USBOTG_CLK, + PE25_PF_USBOTG_DATA7, + }; + + pca100_usb_init(); + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + if (IS_ENABLED(CONFIG_USB)) + pca100_usb_register(); + + imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot", + BBU_HANDLER_FLAG_DEFAULT); + + armlinux_set_architecture(2149); + + return 0; +} + +device_initcall(pca100_devices_init); + +static int pca100_console_init(void) +{ + barebox_set_model("Phytec phyCARD-i.MX27"); + barebox_set_hostname("phycard-imx27"); + + return 0; +} + +console_initcall(pca100_console_init); diff --git a/arch/arm/boards/phytec-phycard-imx27/pca100.dox b/arch/arm/boards/phytec-phycard-imx27/pca100.dox new file mode 100644 index 0000000..9b17674 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-imx27/pca100.dox @@ -0,0 +1,8 @@ +/** @page pcm038 Phytec's phyCORE-i.MX27 + +This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: + +- up to 32MiB NOR type Flash Memory +- 32MiB synchronous dynamic RAM + +*/ diff --git a/arch/arm/boards/phytec-phycard-omap3/Makefile b/arch/arm/boards/phytec-phycard-omap3/Makefile new file mode 100644 index 0000000..a71feec --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap3/Makefile @@ -0,0 +1,18 @@ +# (C) Copyright 2011 Juergen Kilb +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +obj-y += pca-a-l1.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-phycard-omap3/env/config b/arch/arm/boards/phytec-phycard-omap3/env/config new file mode 100644 index 0000000..a3f452b --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap3/env/config @@ -0,0 +1,77 @@ +#!/bin/sh + +#user= + +# Enter MAC address here if not retrieved automatically +#eth0.ethaddr=de:ad:be:ef:00:00 + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.serverip=a.b.c.d +#eth0.gateway=a.b.c.d + +# can be either 'tftp', 'nfs', 'nand' or 'disk' +kernel_loc=nand +# can be either 'net', 'nand', 'disk' or 'initrd' +rootfs_loc=nand + +# for flash based rootfs: 'jffs2' or 'ubifs' +# in case of disk any regular filesystem like 'ext2', 'ext3', 'reiserfs' +rootfs_type=jffs2 +# where is the rootfs in case of 'rootfs_loc=disk' (linux name) +rootfs_part_linux_dev=mmcblk0p4 +rootfsimage=rootfs-${global.hostname}.$rootfs_type + +# where is the kernel image in case of 'kernel_loc=disk' +kernel_part=disk0.2 + +# The image type of the kernel. Can be uimage, zimage, raw or raw_lzo +#kernelimage=zImage-${global.hostname} +kernelimage=uImage-${global.hostname} +#kernelimage=Image-${global.hostname} +#kernelimage=Image-${global.hostname}.lzo + +bareboximage=barebox-${global.hostname}.bin +bareboxenvimage=barebox-${global.hostname}.bin + +if [ -n $user ]; then + bareboximage="$user"-"$bareboximage" + bareboxenvimage="$user"-"$bareboxenvimage" + kernelimage="$user"-"$kernelimage" + rootfsimage="$user"-"$rootfsimage" + nfsroot="/home/$user/nfsroot/${global.hostname}" +else + nfsroot="/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttyO2,115200" + +# the following displays are supported +# pd050vl1 (640 x 480) +# pd035vl1 (640 x 480) +# pd104slf (800 x 600) +# pm070wl4 (800 x 480) +# +# omapfb.mode=:,[,...] +# omapfb.debug= +# - Enable debug printing. You have to have OMAPFB debug support enabled +# in kernel config. +# +bootargs="$bootargs omapdss.def_disp=pd050vl1" +#bootargs="$bootargs omapdss.def_disp=pd035vl1" +#bootargs="$bootargs omapdss.def_disp=pd104slf" +#bootargs="$bootargs omapdss.def_disp=pm070wl4" + +nand_parts="128k(x-loader)ro,512k(barebox),128k(bareboxenv),4M(kernel),-(root)" +nand_device=omap2-nand.0 +rootfs_mtdblock_nand=4 + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c new file mode 100644 index 0000000..7a67493 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c @@ -0,0 +1,264 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Slower full frequency range default timings for x32 operation */ +#define SDP_SDRC_SHARING 0x00000100 +/* Diabling power down mode using CKE pin */ +#define SDP_SDRC_POWER_POP 0x00000081 +/* rkw - need to find of 90/72 degree recommendation for speed like before. */ +#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ + (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) + +/* used to create an array of memory configuartions. */ +struct sdrc_config { + u32 cs_cfg; + u32 mcfg; + u32 mr; + u32 actim_ctrla; + u32 actim_ctrlb; + u32 rfr_ctrl; +} const sdrc_config[] = { +/* max cs_size for autodetection, common timing */ +/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */ +{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201}, +/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */ +{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201}, +/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */ +{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201}, +/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */ +{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201}, +}; + +/* + * Boot-time initialization(s) + */ + +/********************************************************************* + * init_sdram_ddr() - Init DDR controller. + *********************************************************************/ +void init_sdram_ddr(void) +{ + /* reset sdrc controller */ + writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG)); + wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000); + writel(0, OMAP3_SDRC_REG(SYSCONFIG)); + + /* setup sdrc to ball mux */ + writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING)); + writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER)); + + /* set up dll */ + writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL)); + sdelay(0x2000); /* give time to lock */ + +} +/********************************************************************* + * config_sdram_ddr() - Init DDR on dev board. + *********************************************************************/ +void config_sdram_ddr(u8 cs, u8 cfg) +{ + + writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs)); + writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs)); + writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs)); + writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs)); + + writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); + + sdelay(5000); + + writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); + writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); + writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); + + /* set mr0 */ + writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs)); + + sdelay(2000); +} + +/** + * @brief Initialize the SDRC module + * Initialisation for 1x256MByte but normally + * done by x-loader. + * @return void + */ +static void pcaal1_sdrc_init(void) +{ + u32 test0, test1; + char cfg; + + init_sdram_ddr(); + + config_sdram_ddr(0, 0); /* 256MByte at CS0 */ + config_sdram_ddr(1, 0); /* 256MByte at CS1 */ + + test0 = get_ram_size((long *) 0x80000000, SZ_256M); + test1 = get_ram_size((long *) 0xA0000000, SZ_256M); + + /* mask out lower nible, its not tested with + in common/memsize.c */ + test1 &= 0xfffffff0; + + if ((test1 > 0) && (test1 != test0)) + hang(); + + cfg = -1; /* illegal configuration found */ + + if (test1 == 0) { + init_sdram_ddr(); + writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1)); + + /* 1 x 256MByte */ + if (test0 == SZ_256M) + cfg = 2; + + if (cfg != -1) { + config_sdram_ddr(0, cfg); + writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG)); + } + return; + } + + /* reinit both cs with correct size */ + /* 2 x 128MByte */ + if (test0 == SZ_128M) + cfg = 1; + /* 2 x 256MByte */ + if (test0 == SZ_256M) + cfg = 3; + + if (cfg != -1) { + init_sdram_ddr(); + writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG)); + config_sdram_ddr(0, cfg); + config_sdram_ddr(1, cfg); + } +} + +/** + * @brief Do the necessary pin muxing required for phyCARD-A-L1. + * Some pins in OMAP3 do not have alternate modes. + * We don't program these pins. + * + * See @ref MUX_VAL for description of the muxing mode. + * + * @return void + */ +static void pcaal1_mux_config(void) +{ + /* + * Serial Interface + */ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M0)); + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); + + /* GPMC */ + MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); + + /* ETH_PME (GPIO_55) */ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M4)); + /* #CS5 (Ethernet) */ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); + /* ETH_FIFO_SEL (GPIO_57) */ + MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M4)); + /* ETH_AMDIX_EN (GPIO_58) */ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M4)); + /* ETH_nRST (GPIO_64) */ + MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTU | EN | M4)); + + /* HSMMC1 */ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); + + /* USBOTG_nRST (GPIO_63) */ + MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4)); + + /* USBH_nRST (GPIO_65) */ + MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)); +} + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +static int pcaal1_board_init(void) +{ + int in_sdram = omap3_running_in_sdram(); + + if (!in_sdram) + omap3_core_init(); + + pcaal1_mux_config(); + /* Dont reconfigure SDRAM while running in SDRAM! */ + if (!in_sdram) + pcaal1_sdrc_init(); + + return 0; +} + +void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +{ + omap3_save_bootinfo(data); + + arm_cpu_lowlevel_init(); + + pcaal1_board_init(); + + barebox_arm_entry(0x80000000, SZ_256M, 0); +} diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c new file mode 100644 index 0000000..68a17bf --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c @@ -0,0 +1,173 @@ +/** + * @file + * @brief Board Initialization routines for the phyCARD-A-L1 + * + * This board is based on OMAP3530. + * More on OMAP3530 (including documentation can be found here): + * http://focus.ti.com/docs/prod/folders/print/omap3530.html + * + * This file provides initialization in two stages: + * @li Boot time initialization - just get SDRAM working. + * This is run from SRAM - so no case constructs and global vars can be used. + * @li Run time initialization - this is for the rest of the initializations + * such as flash, uart etc. + * + * Boot time initialization includes: + * @li SDRAM initialization. + * @li Pin Muxing relevant for the EVM. + * + * Run time initialization includes + * @li serial @ref serial_ns16550.c driver device definition + * + * Originally from arch/arm/boards/omap/board-beagle.c + * + * Copyright (C) 2011 Phytec Messtechnik GmbH - http://www.phytec.de/ + * Juergen Kilb + * + * based on code from Texas Instruments / board-beagle.c + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ + * Sanjeev Premi + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMC911X_BASE 0x2c000000 + +/** + * @brief Initialize the serial port to be used as console. + * + * @return result of device registration + */ +static int pcaal1_init_console(void) +{ + barebox_set_model("Phytec phyCARD-OMAP3"); + barebox_set_hostname("phycard-omap3"); + + omap3_add_uart3(); + + return 0; +} +console_initcall(pcaal1_init_console); + +#ifdef CONFIG_DRIVER_NET_SMC911X +/** GPMC timing for our SMSC9221 device */ +static struct gpmc_config smsc_cfg = { + .cfg = { + 0x41001000, /*CONF1 */ + 0x00040500, /*CONF2 */ + 0x00000000, /*CONF3 */ + 0x04000500, /*CONF4 */ + 0x05050505, /*CONF5 */ + 0x000002c1, /*CONF6 */ + }, + .base = SMC911X_BASE, + /* GPMC address map as small as possible */ + .size = GPMC_SIZE_16M, +}; + +/* + * Routine: setup_net_chip + * Description: Setting up the configuration GPMC registers specific to the + * Ethernet hardware. + */ +static void pcaal1_setup_net_chip(void) +{ + gpmc_cs_config(5, &smsc_cfg); +} +#endif + +static int pcaal1_mem_init(void) +{ + +#ifdef CONFIG_OMAP_GPMC + /* + * WP is made high and WAIT1 active Low + */ + gpmc_generic_init(0x10); +#endif + omap3_add_sram0(); + + + omap_add_ram0(get_sdr_cs_size(SDRC_CS0_OSET)); + printf("found %s at SDCS0\n", size_human_readable(get_sdr_cs_size(SDRC_CS0_OSET))); + + if ((get_sdr_cs_size(SDRC_CS1_OSET) != 0) && (get_sdr_cs1_base() != OMAP_SDRC_CS0)) { + arm_add_mem_device("ram1", get_sdr_cs1_base(), get_sdr_cs_size(SDRC_CS1_OSET)); + printf("found %s at SDCS1\n", size_human_readable(get_sdr_cs_size(SDRC_CS1_OSET))); + } + + return 0; +} +mem_initcall(pcaal1_mem_init); + +struct omap_hsmmc_platform_data pcaal1_hsmmc_plat = { + .f_max = 26000000, +}; + +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap3_nand_cfg, +}; + +static int pcaal1_init_devices(void) +{ + omap_add_gpmc_nand_device(&nand_plat); + + omap3_add_mmc1(&pcaal1_hsmmc_plat); + +#ifdef CONFIG_DRIVER_NET_SMC911X + pcaal1_setup_net_chip(); + add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, SMC911X_BASE, SZ_4K, + IORESOURCE_MEM, NULL); +#endif + + armlinux_set_architecture(MACH_TYPE_PCAAL1); + + return 0; +} +device_initcall(pcaal1_init_devices); + +static int pcaal1_late_init(void) +{ +#ifdef CONFIG_PARTITION + devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "x-loader"); + dev_add_bb_dev("self_raw", "x_loader0"); + + devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + + devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); +#endif + return 0; +} +late_initcall(pcaal1_late_init); diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.dox b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.dox new file mode 100644 index 0000000..d93c574 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.dox @@ -0,0 +1,16 @@ +/** @page phycard-a-l1 Phytec's phyCARD-A-L1 (OMAP35xx) + +This phyCARD is based on a Texas Instruments OMAP35xx CPU. +The card is shipped with: + +- 256MiB DDR-RAM +- 256MiB NAND Flash Memory +- SMSC9221 ethernet controller +- USB-host interface +- USB-OTG interface +- LVDS camera interface +- LVDS display interface +- TPS65023 Power-Managmanet IC +- 4kB I2C EEPROM + +*/ diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h new file mode 100644 index 0000000..f6f8996 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h @@ -0,0 +1,28 @@ +/** + * @file + * @brief exported generic APIs which various board files implement + * + * This file will not contain any board specific implementations. + * + * (C) Copyright 2008 + * Texas Instruments, + * Raghavendra KH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BOARD_OMAP_H_ +#define __BOARD_OMAP_H_ + +/** Generic Board initialization called from platform.S */ +void board_init(void); + +#endif /* __BOARD_OMAP_H_ */ diff --git a/arch/arm/boards/phytec-phycard-omap4/Makefile b/arch/arm/boards/phytec-phycard-omap4/Makefile new file mode 100644 index 0000000..64782e0 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap4/Makefile @@ -0,0 +1,17 @@ +# (C) Copyright 2012 Jan Weitzel +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +obj-y += pca-a-xl2.o +lwl-y += mux.o lowlevel.o diff --git a/arch/arm/boards/phytec-phycard-omap4/env/bin/nand_bootstrap b/arch/arm/boards/phytec-phycard-omap4/env/bin/nand_bootstrap new file mode 100644 index 0000000..f8873fa --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap4/env/bin/nand_bootstrap @@ -0,0 +1,31 @@ + +echo "copying barebox to nand..." + +mci0.probe=1 +mkdir mnt + +mount /dev/disk0.0 /mnt +if [ $? != 0 ]; then + echo "failed to mount mmc card" + exit 1 +fi + +if [ ! -f /mnt/mlo-nand.bin ]; then + echo "mlo-nand.bin not found on mmc card" + exit 1 +fi + +if [ ! -f /mnt/barebox.bin ]; then + echo "barebox.bin not found on mmc card" +fi + +gpmc_nand0.eccmode=bch8_hw_romcode +erase /dev/nand0.xload.bb +cp /mnt/mlo-nand.bin /dev/nand0.xload.bb + +gpmc_nand0.eccmode=bch8_hw +erase /dev/nand0.barebox.bb +cp /mnt/barebox.bin /dev/nand0.barebox.bb + +echo "success" + diff --git a/arch/arm/boards/phytec-phycard-omap4/env/config b/arch/arm/boards/phytec-phycard-omap4/env/config new file mode 100644 index 0000000..998f9fa --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap4/env/config @@ -0,0 +1,46 @@ +#!/bin/sh + +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=tftp +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-${global.hostname}.$rootfs_type + +kernelimage=zImage-${global.hostname} +#kernelimage=uImage-${global.hostname} +#kernelimage=Image-${global.hostname} +#kernelimage=Image-${global.hostname}.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttyO2,115200" + +nand_parts="128k(xload)ro,512k(barebox),128k(bareboxenv),4M(kernel),-(root)" +rootfs_mtdblock_nand=4 + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c new file mode 100644 index 0000000..1ddf8a0 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TPS62361_VSEL0_GPIO 7 + +void set_muxconf_regs(void); + +static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { + .tim1 = 0x0EEB0662, + .tim2 = 0x20370DD2, + .tim3 = 0x00BFC33F, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x00000618, + .config_init = 0x80001AB1, + .config_final = 0x80001AB1, + .zq_config = 0xd0093215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +static noinline void pcaaxl2_init_lowlevel(void) +{ + struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; + struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; + struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; + struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; + struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; + struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; + unsigned int rev = omap4_revision(); + + set_muxconf_regs(); + + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); + + if (rev < OMAP4460_ES1_0) + omap4430_scale_vcores(); + else + omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); + + writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); + + /* Configure all DPLL's at 100% OPP */ + if (rev < OMAP4460_ES1_0) + omap4_configure_mpu_dpll(&mpu44xx); + else + omap4_configure_mpu_dpll(&mpu4460); + + omap4_configure_iva_dpll(&iva); + omap4_configure_per_dpll(&per); + omap4_configure_abe_dpll(&abe); + omap4_configure_usb_dpll(&usb); + + /* Enable all clocks */ + omap4_enable_all_clocks(); + + sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ + sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ + sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */ + sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ + sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ +} + +void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +{ + omap4_save_bootinfo(data); + + arm_cpu_lowlevel_init(); + + if (get_pc() > 0x80000000) + goto out; + + arm_setup_stack(0x4030d000); + + pcaaxl2_init_lowlevel(); +out: + barebox_arm_entry(0x80000000, SZ_512M, 0); +} diff --git a/arch/arm/boards/phytec-phycard-omap4/mux.c b/arch/arm/boards/phytec-phycard-omap4/mux.c new file mode 100644 index 0000000..a31d995 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap4/mux.c @@ -0,0 +1,253 @@ +#include +#include +#include +#include +#include +#include + +static const struct pad_conf_entry core_padconf_array[] = { + {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ + {GPMC_AD1, (IEN | PTD | DIS | M0)}, /* gpmc_ad1 */ + {GPMC_AD2, (IEN | PTD | DIS | M0)}, /* gpmc_ad2 */ + {GPMC_AD3, (IEN | PTD | DIS | M0)}, /* gpmc_ad3 */ + {GPMC_AD4, (IEN | PTD | DIS | M0)}, /* gpmc_ad4 */ + {GPMC_AD5, (IEN | PTD | DIS | M0)}, /* gpmc_ad5 */ + {GPMC_AD6, (IEN | PTD | DIS | M0)}, /* gpmc_ad6 */ + {GPMC_AD7, (IEN | PTD | DIS | M0)}, /* gpmc_ad7 */ + {GPMC_AD8, (IEN | PTD | DIS | M0)}, /* gpmc_ad8 */ + {GPMC_AD9, (IEN | PTD | DIS | M0)}, /* gpmc_ad9 */ + {GPMC_AD10, (IEN | PTD | DIS | M0)}, /* gpmc_ad10 */ + {GPMC_AD11, (IEN | PTD | DIS | M0)}, /* gpmc_ad11 */ + {GPMC_AD12, (IEN | PTD | DIS | M0)}, /* gpmc_ad12 */ + {GPMC_AD13, (IEN | PTD | DIS | M0)}, /* gpmc_ad13 */ + {GPMC_AD14, (IEN | PTD | DIS | M0)}, /* gpmc_ad14 */ + {GPMC_AD15, (IEN | PTD | DIS | M0)}, /* gpmc_ad15 */ + {GPMC_A16, (IEN | PTD | DIS | M0)}, /* gpmc_a16 */ + {GPMC_A17, (SAFE_MODE)}, /* nc */ + {GPMC_A18, (SAFE_MODE)}, /* nc */ + {GPMC_A19, (SAFE_MODE)}, /* nc */ + {GPMC_A20, (SAFE_MODE)}, /* nc */ + {GPMC_A21, (SAFE_MODE)}, /* nc */ + {GPMC_A22, (SAFE_MODE)}, /* nc */ + {GPMC_A23, (SAFE_MODE)}, /* nc */ + {GPMC_A24, (SAFE_MODE)}, /* nc */ + {GPMC_A25, (SAFE_MODE)}, /* nc */ + {GPMC_NCS0, (IDIS | PTU | EN | M0)}, /* gpmc_nsc0 */ + {GPMC_NCS1, (IDIS | PTU | EN | M0)}, /* gpmc_nsc1 */ + {GPMC_NCS2, (SAFE_MODE)}, /* nc */ + {GPMC_NCS3, (SAFE_MODE)}, /* nc */ + {GPMC_NWP, (IEN | PTD | DIS | M0)}, /* gpmc_nwp */ + {GPMC_CLK, (PTU | IEN | M3)}, /* gpio_55 */ + {GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)}, /* gpmc_ndav_ale */ + {GPMC_NOE, (IDIS | PTD | DIS | M0)}, /* gpmc_noe */ + {GPMC_NWE, (IDIS | PTD | DIS | M0)}, /* gpmc_nwe */ + {GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)}, /* gpmc_nbe0_cle */ + {GPMC_NBE1, (SAFE_MODE)}, /* nc */ + {GPMC_WAIT0, (IEN | PTU | EN | M0)}, /* gpmc_wait0 */ + {GPMC_WAIT1, (IEN | PTU | EN | M0)}, /* gpmc_wait1 */ + {C2C_DATA11, (SAFE_MODE)}, /* nc */ + {C2C_DATA12, (SAFE_MODE)}, /* nc */ + {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */ + {C2C_DATA14, (SAFE_MODE)}, /* nc */ + {C2C_DATA15, (SAFE_MODE)}, /* nc */ + {HDMI_HPD, (SAFE_MODE)}, /* nc */ + {HDMI_CEC, (SAFE_MODE)}, /* nc */ + {HDMI_DDC_SCL, (SAFE_MODE)}, /* nc */ + {HDMI_DDC_SDA, (SAFE_MODE)}, /* nc */ + {CSI21_DX0, (SAFE_MODE)}, /* nc */ + {CSI21_DY0, (SAFE_MODE)}, /* nc */ + {CSI21_DX1, (SAFE_MODE)}, /* nc */ + {CSI21_DY1, (SAFE_MODE)}, /* nc */ + {CSI21_DX2, (SAFE_MODE)}, /* nc */ + {CSI21_DY2, (SAFE_MODE)}, /* nc */ + {CSI21_DX3, (SAFE_MODE)}, /* nc */ + {CSI21_DY3, (SAFE_MODE)}, /* nc */ + {CSI21_DX4, (SAFE_MODE)}, /* nc */ + {CSI21_DY4, (SAFE_MODE)}, /* nc */ + {CSI22_DX0, (SAFE_MODE)}, /* nc */ + {CSI22_DY0, (SAFE_MODE)}, /* nc */ + {CSI22_DX1, (SAFE_MODE)}, /* nc */ + {CSI22_DY1, (SAFE_MODE)}, /* nc */ + {CAM_SHUTTER, (SAFE_MODE)}, /* unused */ + {CAM_STROBE, (SAFE_MODE)}, /* unused */ + {CAM_GLOBALRESET, (SAFE_MODE)}, /* unused */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (SAFE_MODE)}, /* nc */ + {USBB1_HSIC_STROBE, (SAFE_MODE)}, /* nc */ + {USBC1_ICUSB_DP, (SAFE_MODE)}, /* nc */ + {USBC1_ICUSB_DM, (SAFE_MODE)}, /* nc */ + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {SDMMC1_DAT4, (SAFE_MODE)}, /* nc */ + {SDMMC1_DAT5, (SAFE_MODE)}, /* nc */ + {SDMMC1_DAT6, (SAFE_MODE)}, /* nc */ + {SDMMC1_DAT7, (SAFE_MODE)}, /* nc */ + {ABE_MCBSP2_CLKX, (SAFE_MODE)}, /* nc */ + {ABE_MCBSP2_DR, (SAFE_MODE)}, /* nc */ + {ABE_MCBSP2_DX, (SAFE_MODE)}, /* nc */ + {ABE_MCBSP2_FSX, (SAFE_MODE)}, /* nc */ + {ABE_MCBSP1_CLKX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_DR, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_DX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_FSX, (SAFE_MODE)}, /* nc */ + {ABE_PDM_UL_DATA, (SAFE_MODE)}, /* unused */ + {ABE_PDM_DL_DATA, (SAFE_MODE)}, /* unused */ + {ABE_PDM_FRAME, (SAFE_MODE)}, /* unused */ + {ABE_PDM_LB_CLK, (SAFE_MODE)}, /* unused */ + {ABE_CLKS, (SAFE_MODE)}, /* unused */ + {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */ + {ABE_DMIC_DIN1, (SAFE_MODE)}, /* unused */ + {ABE_DMIC_DIN2, (SAFE_MODE)}, /* nc */ + {ABE_DMIC_DIN3, (SAFE_MODE)}, /* unused */ + {UART2_CTS, (SAFE_MODE)}, /* nc */ + {UART2_RTS, (SAFE_MODE)}, /* nc */ + {UART2_RX, (SAFE_MODE)}, /* nc */ + {UART2_TX, (SAFE_MODE)}, /* nc */ + {HDQ_SIO, (SAFE_MODE)}, /* unused */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (SAFE_MODE)}, /* unused */ + {I2C2_SDA, (SAFE_MODE)}, /* unused */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (SAFE_MODE)}, /* nc */ + {I2C4_SDA, (SAFE_MODE)}, /* nc */ + {MCSPI1_CLK, (SAFE_MODE)}, /* unused */ + {MCSPI1_SOMI, (SAFE_MODE)}, /* unused */ + {MCSPI1_SIMO, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS0, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS1, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS2, (SAFE_MODE)}, /* nc */ + {MCSPI1_CS3, (SAFE_MODE)}, /* nc */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)}, /* uart3_tx */ + {SDMMC5_CLK, (PTU | IEN | M3)}, /* goio_145 */ + {SDMMC5_CMD, (PTU | IEN | M3)}, /* goio_146 */ + {SDMMC5_DAT0, (SAFE_MODE)}, /* nc */ + {SDMMC5_DAT1, (SAFE_MODE)}, /* nc */ + {SDMMC5_DAT2, (SAFE_MODE)}, /* nc */ + {SDMMC5_DAT3, (SAFE_MODE)}, /* nc */ + {MCSPI4_CLK, (PTU | IEN | M3)}, /* gpio_151 */ + {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */ + {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */ + {MCSPI4_CS0, (SAFE_MODE)}, /* nc */ + {UART4_RX, (SAFE_MODE)}, /* nc */ + {UART4_TX, (SAFE_MODE)}, /* nc */ + {USBB2_ULPITLL_CLK, (SAFE_MODE)}, /* nc */ + {USBB2_ULPITLL_STP, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DIR, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_NXT, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT0, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT1, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT2, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT3, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT4, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT5, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT6, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_DAT7, (SAFE_MODE)}, /* unused */ + {USBB2_HSIC_DATA, (SAFE_MODE)}, /* unused */ + {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */ + {UNIPRO_TX0, (SAFE_MODE)}, /* nc */ + {UNIPRO_TY0, (SAFE_MODE)}, /* nc */ + {UNIPRO_TX1, (SAFE_MODE)}, /* nc */ + {UNIPRO_TY1, (SAFE_MODE)}, /* nc */ + {UNIPRO_TX2, (SAFE_MODE)}, /* unused */ + {UNIPRO_TY2, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX0, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY0, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX1, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY1, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX2, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY2, (SAFE_MODE)}, /* unused */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */ + {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (SAFE_MODE)}, /* nc */ + {SYS_BOOT0, (M0)}, /* sys_boot */ + {SYS_BOOT1, (M0)}, /* sys_boot */ + {SYS_BOOT2, (M0)}, /* sys_boot */ + {SYS_BOOT3, (M0)}, /* sys_boot */ + {SYS_BOOT4, (M0)}, /* sys_boot */ + {SYS_BOOT5, (M0)}, /* sys_boot */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (SAFE_MODE)}, /* unused */ + {DPM_EMU3, (SAFE_MODE)}, /* unused */ + {DPM_EMU4, (SAFE_MODE)}, /* unused */ + {DPM_EMU5, (SAFE_MODE)}, /* unused */ + {DPM_EMU6, (SAFE_MODE)}, /* unused */ + {DPM_EMU7, (SAFE_MODE)}, /* unused */ + {DPM_EMU8, (SAFE_MODE)}, /* unused */ + {DPM_EMU9, (SAFE_MODE)}, /* unused */ + {DPM_EMU10, (SAFE_MODE)}, /* unused */ + {DPM_EMU11, (SAFE_MODE)}, /* unused */ + {DPM_EMU12, (SAFE_MODE)}, /* unused */ + {DPM_EMU13, (SAFE_MODE)}, /* unused */ + {DPM_EMU14, (SAFE_MODE)}, /* unused */ + {DPM_EMU15, (SAFE_MODE)}, /* unused */ + {DPM_EMU16, (SAFE_MODE)}, /* unused */ + {DPM_EMU17, (SAFE_MODE)}, /* unused */ + {DPM_EMU18, (SAFE_MODE)}, /* unused */ + {DPM_EMU19, (SAFE_MODE)}, /* unused */ +}; + +static const struct pad_conf_entry wkup_padconf_array[] = { + {GPIO_WK0, (SAFE_MODE)}, /* tbd */ + {GPIO_WK1, (SAFE_MODE)}, /* nc */ + {GPIO_WK2, (SAFE_MODE)}, /* nc */ + {GPIO_WK3, (SAFE_MODE)}, /* nc */ + {GPIO_WK4, (SAFE_MODE)}, /* nc */ + {SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {FREF_XTAL_IN, (M0)}, /* # */ + {FREF_SLICER_IN, (SAFE_MODE)}, /* nc */ + {FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ + {FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {FREF_CLK3_REQ, (SAFE_MODE)}, /* nc */ + {FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {FREF_CLK4_REQ, (IEN | M3)}, /* gpio_wk7 */ + {FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */ + {SYS_32K, (IEN | M0)}, /* sys_32k */ + {SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {SYS_PWRON_RESET_OUT, (M0)}, /* sys_pwron_reset_out */ + {SYS_BOOT6, (M0)}, /* sys_boot6 */ + {SYS_BOOT7, (M0)}, /* sys_boot7 */ +}; + +void set_muxconf_regs(void) +{ + omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, + ARRAY_SIZE(core_padconf_array)); + + omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, + ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_wk7 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio1_wup_clocks(); + } +} diff --git a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c new file mode 100644 index 0000000..6429722 --- /dev/null +++ b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2011 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int pcaaxl2_console_init(void) +{ + barebox_set_model("Phytec phyCARD-OMAP4"); + barebox_set_hostname("phycard-omap4"); + + omap44xx_add_uart3(); + + return 0; +} +console_initcall(pcaaxl2_console_init); + +static int pcaaxl2_mem_init(void) +{ + omap_add_ram0(SZ_512M); + + omap44xx_add_sram0(); + + return 0; +} +mem_initcall(pcaaxl2_mem_init); + +static struct gpmc_config net_cfg = { + .cfg = { + 0x00001000, /* CONF1 */ + 0x00080800, /* CONF2 */ + 0x00000000, /* CONF3 */ + 0x08000800, /* CONF4 */ + 0x000a0a0a, /* CONF5 */ + 0x000003c2, /* CONF6 */ + }, + .base = 0x2C000000, + .size = GPMC_SIZE_16M, +}; + +static void pcaaxl2_network_init(void) +{ + gpmc_cs_config(5, &net_cfg); + + add_ks8851_device(DEVICE_ID_DYNAMIC, net_cfg.base, net_cfg.base + 2, + IORESOURCE_MEM_16BIT, NULL); +} + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("twlcore", 0x48), + }, +}; + +static struct omap_hsmmc_platform_data mmc_device = { + .f_max = 26000000, +}; + +#define OMAP4_CONTROL_PBIASLITE 0x4A100600 +#define OMAP4_MMC1_PBIASLITE_VMODE (1<<21) +#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1<<22) +#define OMAP4_MMC1_PWRDNZ (1<<26) + +static struct gpmc_nand_platform_data nand_plat = { + .device_width = 16, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap4_nand_cfg, +}; + +static int pcaaxl2_devices_init(void) +{ + u32 value; + + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + omap44xx_add_i2c1(NULL); + + value = readl(OMAP4_CONTROL_PBIASLITE); + value &= ~OMAP4_MMC1_PBIASLITE_VMODE; + value |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ); + writel(value, OMAP4_CONTROL_PBIASLITE); + + omap44xx_add_mmc1(&mmc_device); + + gpmc_generic_init(0x10); + + pcaaxl2_network_init(); + + omap_add_gpmc_nand_device(&nand_plat); + +#ifdef CONFIG_PARTITION + devfs_add_partition("nand0", 0x00000, SZ_128K, + DEVFS_PARTITION_FIXED, "xload_raw"); + dev_add_bb_dev("xload_raw", "xload"); + devfs_add_partition("nand0", SZ_128K, SZ_512K, + DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, + DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); +#endif + + armlinux_set_architecture(MACH_TYPE_PCAAXL2); + + return 0; +} +device_initcall(pcaaxl2_devices_init); diff --git a/arch/arm/boards/phytec-phycore-am335x/Makefile b/arch/arm/boards/phytec-phycore-am335x/Makefile new file mode 100644 index 0000000..092c31d --- /dev/null +++ b/arch/arm/boards/phytec-phycore-am335x/Makefile @@ -0,0 +1,2 @@ +lwl-y += lowlevel.o +obj-y += board.o diff --git a/arch/arm/boards/phytec-phycore-am335x/board.c b/arch/arm/boards/phytec-phycore-am335x/board.c new file mode 100644 index 0000000..59de42b --- /dev/null +++ b/arch/arm/boards/phytec-phycore-am335x/board.c @@ -0,0 +1,75 @@ +/* + * pcm051 - phyCORE-AM335x Board Initalization Code + * + * Copyright (C) 2012 Teresa Gámez, Phytec Messtechnik GmbH + * + * Based on arch/arm/boards/omap/board-beagle.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +static int pcm051_coredevice_init(void) +{ + if (!of_machine_is_compatible("phytec,pcm051")) + return 0; + + am33xx_register_ethaddr(0, 0); + return 0; +} +coredevice_initcall(pcm051_coredevice_init); + +static struct omap_barebox_part pcm051_barebox_part = { + .nand_offset = SZ_512K, + .nand_size = SZ_512K, + .nor_offset = SZ_128K, + .nor_size = SZ_512K, +}; + +static int pcm051_devices_init(void) +{ + if (!of_machine_is_compatible("phytec,pcm051")) + return 0; + + switch (bootsource_get()) { + case BOOTSOURCE_SPI: + of_device_enable_path("/chosen/environment-spi"); + break; + case BOOTSOURCE_MMC: + omap_set_bootmmc_devname("mmc0"); + break; + default: + of_device_enable_path("/chosen/environment-nand"); + break; + } + + omap_set_barebox_part(&pcm051_barebox_part); + armlinux_set_architecture(MACH_TYPE_PCM051); + + am33xx_bbu_spi_nor_mlo_register_handler("MLO.spi", "/dev/m25p0.xload"); + + return 0; +} +device_initcall(pcm051_devices_init); diff --git a/arch/arm/boards/phytec-phycore-am335x/env/boot/mmc b/arch/arm/boards/phytec-phycore-am335x/env/boot/mmc new file mode 100644 index 0000000..93a2357 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-am335x/env/boot/mmc @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "kernel & rootfs on SD card" + exit +fi + +global.bootm.image=/boot/uImage +#global.bootm.oftree=/boot/oftree +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" diff --git a/arch/arm/boards/phytec-phycore-am335x/env/boot/nand b/arch/arm/boards/phytec-phycore-am335x/env/boot/nand new file mode 100644 index 0000000..22d657e --- /dev/null +++ b/arch/arm/boards/phytec-phycore-am335x/env/boot/nand @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-am335x/env/boot/spi b/arch/arm/boards/phytec-phycore-am335x/env/boot/spi new file mode 100644 index 0000000..2d10184 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-am335x/env/boot/spi @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "SPI NOR Flash" + exit +fi + +global.bootm.image="/dev/m25p0.kernel" + +# Use rootfs form NAND for now as rootfs partition < 4MB +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root,2048 rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-am335x/env/config-board b/arch/arm/boards/phytec-phycore-am335x/env/config-board new file mode 100644 index 0000000..7f0b2b7 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-am335x/env/config-board @@ -0,0 +1,7 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.hostname=pcm051 +global.linux.bootargs.base="console=ttyO0,115200" diff --git a/arch/arm/boards/phytec-phycore-am335x/lowlevel.c b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c new file mode 100644 index 0000000..d3cac68 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-am335x/lowlevel.c @@ -0,0 +1,120 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = { + .slave_ratio0 = 0x40, + .dll_lock_diff0 = 0x0, + .invert_clkout0 = 0x1, + .slave_ratio1 = 0x40, + .dll_lock_diff1 = 0x0, + .invert_clkout1 = 0x1, + .slave_ratio2 = 0x40, + .dll_lock_diff2 = 0x0, + .invert_clkout2 = 0x1, +}; + +static const struct am33xx_emif_regs MT41J256M8HX15E_2x256M8_regs = { + .emif_read_latency = 0x6, + .emif_tim1 = 0x0668A39B, + .emif_tim2 = 0x26337FDA, + .emif_tim3 = 0x501F830F, + .sdram_config = 0x61C04832, + .zq_config = 0x50074BE4, + .sdram_ref_ctrl = 0x0000093B, +}; + +static const struct am33xx_ddr_data MT41J256M8HX15E_2x256M8_data = { + .rd_slave_ratio0 = 0x3B, + .wr_dqs_slave_ratio0 = 0x85, + .fifo_we_slave_ratio0 = 0x100, + .wr_slave_ratio0 = 0xC1, + .use_rank0_delay = 0x01, + .dll_lock_diff0 = 0x0, +}; + +extern char __dtb_am335x_phytec_phycore_start[]; +extern char __dtb_am335x_phytec_phycore_end[]; + +/** + * @brief The basic entry point for board initialization. + * + * This is called as part of machine init (after arch init). + * This is again called with stack in SRAM, so not too many + * constructs possible here. + * + * @return void + */ +static noinline void pcm051_board_init(void) +{ + unsigned long sdram = 0x80000000, fdt; + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR)); + while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); + + writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR)); + while (readl(AM33XX_WDT_REG(WWPS)) != 0x0); + + am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303); + + am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd, + &MT41J256M8HX15E_2x256M8_regs, + &MT41J256M8HX15E_2x256M8_data); + + am33xx_uart0_soft_reset(); + am33xx_enable_uart0_pin_mux(); + omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE); + putc_ll('>'); + + /* + * Copy the devicetree blob to sdram so that the barebox code finds it + * inside valid SDRAM instead of SRAM. + */ + memcpy((void *)sdram, __dtb_am335x_phytec_phycore_start, + __dtb_am335x_phytec_phycore_end - + __dtb_am335x_phytec_phycore_start); + fdt = sdram; + + barebox_arm_entry(sdram, SZ_512M, fdt); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2) +{ + am33xx_save_bootinfo((void *)bootinfo); + + arm_cpu_lowlevel_init(); + + /* + * Setup C environment, the board init code uses global variables. + * Stackpointer has already been initialized by the ROM code. + */ + relocate_to_current_adr(); + setup_c(); + + pcm051_board_init(); +} + +ENTRY_FUNCTION(start_am33xx_phytec_phycore_sdram, r0, r1, r2) +{ + uint32_t fdt; + + fdt = (uint32_t)__dtb_am335x_phytec_phycore_start - get_runtime_offset(); + + barebox_arm_entry(0x80000000, SZ_512M, fdt); +} diff --git a/arch/arm/boards/phytec-phycore-imx27/Makefile b/arch/arm/boards/phytec-phycore-imx27/Makefile new file mode 100644 index 0000000..bfb55d3 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/Makefile @@ -0,0 +1,3 @@ +obj-y += pcm038.o +lwl-y += lowlevel.o +obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970.o diff --git a/arch/arm/boards/phytec-phycore-imx27/env/boot/nand-ubi b/arch/arm/boards/phytec-phycore-imx27/env/boot/nand-ubi new file mode 100644 index 0000000..67b0cb4 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/env/boot/nand-ubi @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-imx27/env/config-board b/arch/arm/boards/phytec-phycore-imx27/env/config-board new file mode 100644 index 0000000..e8e8378 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/env/config-board @@ -0,0 +1,6 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nand new file mode 100644 index 0000000..84220b7 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" +kernelname="mxc_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nor new file mode 100644 index 0000000..c2c4065 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="512k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx27/lowlevel.c b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c new file mode 100644 index 0000000..4f55af8 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/lowlevel.c @@ -0,0 +1,104 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pll.h" + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + uint32_t r; + int i; + + arm_cpu_lowlevel_init(); + + /* ahb lite ip interface */ + writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0); + writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1); + writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0); + writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0xa0000000 && r < 0xb0000000) + goto out; + + /* re-program the PLL prior(!) starting the SDRAM controller */ + writel(MPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_MPCTL0); + writel(SPCTL0_VAL, MX27_CCM_BASE_ADDR + MX27_SPCTL0); + writel(CSCR_VAL | MX27_CSCR_UPDATE_DIS | MX27_CSCR_MPLL_RESTART | + MX27_CSCR_SPLL_RESTART, MX27_CCM_BASE_ADDR + MX27_CSCR); + + /* + * DDR on CSD0 + */ + /* Enable DDR SDRAM operation */ + writel(0x00000008, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + + /* Set the driving strength */ + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5)); + writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6)); + writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7)); + writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8)); + + /* Initial reset */ + writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + + /* precharge CSD0 all banks */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */ + writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + + for (i = 0; i < 8; i++) + writel(0, 0xa0000f00); + + writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + + writeb(0xda, 0xa0000033); + writeb(0xff, 0xa1000000); + writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 | + ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, + MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call mx27_barebox_boot_nand_external() */ + arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8); + + imx27_barebox_boot_nand_external(0); + } +out: + imx27_barebox_entry(0); +} diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.c b/arch/arm/boards/phytec-phycore-imx27/pcm038.c new file mode 100644 index 0000000..1733261 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/pcm038.c @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ +#define pr_fmt(fmt) "pcm038: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pll.h" + +#define PCM038_GPIO_PMIC_IRQ (GPIO_PORTB + 23) +#define PCM038_GPIO_FEC_RST (GPIO_PORTC + 30) +#define PCM970_GPIO_SPI_CS1 (GPIO_PORTD + 27) +#define PCM038_GPIO_SPI_CS0 (GPIO_PORTD + 28) +#define PCM038_GPIO_OTG_STP (GPIO_PORTE + 1) + +static struct fec_platform_data fec_info = { + .xcv_type = PHY_INTERFACE_MODE_MII, + .phy_addr = 1, +}; + +static int pcm038_spi_cs[] = { + PCM038_GPIO_SPI_CS0, +#ifdef CONFIG_MACH_PCM970_BASEBOARD + PCM970_GPIO_SPI_CS1, +#endif +}; + +static struct spi_imx_master pcm038_spi_0_data = { + .chipselect = pcm038_spi_cs, + .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), +}; + +static struct spi_board_info pcm038_spi_board_info[] = { + { + .name = "mc13783", + .bus_num = 0, + .chip_select = 0, + } +}; + +static struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 188679, /* in ps (5.3MHz) */ + .hsync_len = 7, + .left_margin = 5, + .right_margin = 16, + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 9, + }, + /* + * - HSYNC active high + * - VSYNC active high + * - clk notenabled while idle + * - clock not inverted + * - data not inverted + * - data enable low active + * - enable sharp mode + */ + .pcr = 0xF00080C0, + .bpp = 16, +}; + +static struct imx_fb_platform_data pcm038_fb_data = { + .mode = &imxfb_mode, + .num_modes = 1, + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + +/** + * The spctl0 register is a beast: Seems you can read it + * only one times without writing it again. + */ +static inline uint32_t get_pll_spctl10(void) +{ + uint32_t reg; + + reg = readl(MX27_CCM_BASE_ADDR + MX27_SPCTL0); + writel(reg, MX27_CCM_BASE_ADDR + MX27_SPCTL0); + + return reg; +} + +/** + * If the PLL settings are in place switch the CPU core frequency to the max. value + */ +static int pcm038_power_init(void) +{ + uint32_t spctl0 = get_pll_spctl10(); + struct mc13xxx *mc13xxx = mc13xxx_get(); + + /* PLL registers already set to their final values? */ + if (spctl0 == SPCTL0_VAL && + readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) { + console_flush(); + if (mc13xxx) { + mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0), + MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) | + MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) | + MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450)); + + mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4), + MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1A_SOFTSTART | + MC13783_SW1B_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1B_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) | + MC13783_SW1B_SOFTSTART | + MC13783_SW_PLL_FACTOR(32)); + + /* Setup VMMC voltage */ + if (IS_ENABLED(CONFIG_MCI_IMX)) { + u32 val; + + mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_SETTING(1), &val); + /* VMMC1 = 3.00 V */ + val &= ~(7 << 6); + val |= 6 << 6; + mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_SETTING(1), val); + + mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_MODE(1), &val); + /* Enable VMMC1 */ + val |= 1 << 18; + mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_MODE(1), val); + } + + /* wait for required power level to run the CPU at 400 MHz */ + udelay(100000); + writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR); + writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0); + writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1); + + /* Clocks have changed. Notify clients */ + clock_notifier_call_chain(); + } else { + pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n"); + } + } + + /* clock gating enable */ + writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR); + + return 0; +} + +struct imxusb_platformdata pcm038_otg_pdata = { + .mode = IMX_USB_MODE_DEVICE, + .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static int pcm038_devices_init(void) +{ + int i; + u64 uid = 0; + char *envdev; + long sram_size; + + unsigned int mode[] = { + /* FEC */ + PD0_AIN_FEC_TXD0, + PD1_AIN_FEC_TXD1, + PD2_AIN_FEC_TXD2, + PD3_AIN_FEC_TXD3, + PD4_AOUT_FEC_RX_ER, + PD5_AOUT_FEC_RXD1, + PD6_AOUT_FEC_RXD2, + PD7_AOUT_FEC_RXD3, + PD8_AF_FEC_MDIO, + PD9_AIN_FEC_MDC | GPIO_PUEN, + PD10_AOUT_FEC_CRS, + PD11_AOUT_FEC_TX_CLK, + PD12_AOUT_FEC_RXD0, + PD13_AOUT_FEC_RX_DV, + PD14_AOUT_FEC_RX_CLK, + PD15_AOUT_FEC_COL, + PD16_AIN_FEC_TX_ER, + PF23_AIN_FEC_TX_EN, + /* UART1 */ + PE12_PF_UART1_TXD, + PE13_PF_UART1_RXD, + PE14_PF_UART1_CTS, + PE15_PF_UART1_RTS, + /* CSPI1 */ + PD25_PF_CSPI1_RDY, + PD29_PF_CSPI1_SCLK, + PD30_PF_CSPI1_MISO, + PD31_PF_CSPI1_MOSI, + /* Display */ + PA5_PF_LSCLK, + PA6_PF_LD0, + PA7_PF_LD1, + PA8_PF_LD2, + PA9_PF_LD3, + PA10_PF_LD4, + PA11_PF_LD5, + PA12_PF_LD6, + PA13_PF_LD7, + PA14_PF_LD8, + PA15_PF_LD9, + PA16_PF_LD10, + PA17_PF_LD11, + PA18_PF_LD12, + PA19_PF_LD13, + PA20_PF_LD14, + PA21_PF_LD15, + PA22_PF_LD16, + PA23_PF_LD17, + PA24_PF_REV, + PA25_PF_CLS, + PA26_PF_PS, + PA27_PF_SPL_SPR, + PA28_PF_HSYNC, + PA29_PF_VSYNC, + PA30_PF_CONTRAST, + PA31_PF_OE_ACD, + /* USB OTG */ + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PC9_PF_USBOTG_DATA0, + PC10_PF_USBOTG_DATA2, + PC11_PF_USBOTG_DATA1, + PC12_PF_USBOTG_DATA4, + PC13_PF_USBOTG_DATA3, + PE0_PF_USBOTG_NXT, + PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT, + PE2_PF_USBOTG_DIR, + PE24_PF_USBOTG_CLK, + PE25_PF_USBOTG_DATA7, + /* I2C1 */ + PD17_PF_I2C_DATA | GPIO_PUEN, + PD18_PF_I2C_CLK, + /* I2C2 */ + PC5_PF_I2C2_SDA, + PC6_PF_I2C2_SCL, + /* Misc */ + PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT, + PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT, +#ifdef CONFIG_MACH_PCM970_BASEBOARD + PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT, +#endif + PCM038_GPIO_PMIC_IRQ | GPIO_GPIO | GPIO_IN, + }; + + /* configure 16 bit nor flash on cs0 */ + imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900); + + /* configure SRAM on cs1 */ + imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); + + /* SRAM can be up to 2MiB */ + sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M); + if (sram_size) + add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size, + IORESOURCE_MEM_WRITEABLE); + + /* initizalize gpios */ + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); + imx27_add_spi0(&pcm038_spi_0_data); + + pcm038_power_init(); + + add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0); + imx27_add_nand(&nand_info); + imx27_add_fb(&pcm038_fb_data); + + imx27_add_i2c0(NULL); + imx27_add_i2c1(NULL); + + /* Register the fec device after the PLL re-initialisation + * as the fec depends on the (now higher) ipg clock + */ + gpio_set_value(PCM038_GPIO_FEC_RST, 1); + imx27_add_fec(&fec_info); + + /* Apply delay for STP line to stop ULPI */ + gpio_direction_output(PCM038_GPIO_OTG_STP, 1); + mdelay(1); + imx_gpio_mode(PE1_PF_USBOTG_STP); + + if (IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC)) + imx27_add_usbotg(&pcm038_otg_pdata); + + switch (bootsource_get()) { + case BOOTSOURCE_NAND: + devfs_add_partition("nand0", 0, SZ_512K, + DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_512K, SZ_128K, + DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + envdev = "NAND"; + break; + default: + devfs_add_partition("nor0", 0, SZ_512K, + DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", SZ_512K, SZ_128K, + DEVFS_PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + envdev = "NOR"; + } + + pr_notice("Using environment in %s Flash\n", envdev); + + if (imx_iim_read(1, 0, &uid, 6) == 6) + armlinux_set_serial(uid); + armlinux_set_architecture(MACH_TYPE_PCM038); + + return 0; +} + +device_initcall(pcm038_devices_init); + +static int pcm038_console_init(void) +{ + barebox_set_model("Phytec phyCORE-i.MX27"); + barebox_set_hostname("phycore-imx27"); + + imx27_add_uart0(); + + return 0; +} + +console_initcall(pcm038_console_init); diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.dox b/arch/arm/boards/phytec-phycore-imx27/pcm038.dox new file mode 100644 index 0000000..85177d2 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/pcm038.dox @@ -0,0 +1,9 @@ +/** @page pcm038 Phytec's phyCORE-i.MX27 + +This CPU card is based on a Freescale i.MX27 CPU. The card is shipped with: + +- up to 64MB NOR Flash Memory +- up to 1GB NAND Flash Memory +- up to 256MB DRAM + +*/ diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm970.c b/arch/arm/boards/phytec-phycore-imx27/pcm970.c new file mode 100644 index 0000000..2b2483b --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/pcm970.c @@ -0,0 +1,195 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_IDE_POWER (GPIO_PORTE + 18) +#define GPIO_IDE_PCOE (GPIO_PORTF + 7) +#define GPIO_IDE_RESET (GPIO_PORTF + 10) + +static struct resource pcm970_ide_resources[] = { + { + .start = MX27_PCMCIA_MEM_BASE_ADDR, + .end = MX27_PCMCIA_MEM_BASE_ADDR + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static void pcm970_ide_reset(int state) +{ + /* Switch reset line to low/high state */ + gpio_set_value(GPIO_IDE_RESET, !!state); +} + +static struct ide_port_info pcm970_ide_pdata = { + .ioport_shift = 0, + .reset = &pcm970_ide_reset, +}; + +static struct device_d pcm970_ide_device = { + .id = DEVICE_ID_DYNAMIC, + .name = "ide_intf", + .num_resources = ARRAY_SIZE(pcm970_ide_resources), + .resource = pcm970_ide_resources, + .platform_data = &pcm970_ide_pdata, +}; + +static void pcm970_ide_init(void) +{ + uint32_t i; + unsigned int mode[] = { + /* PCMCIA */ + PF20_PF_PC_CD1, + PF19_PF_PC_CD2, + PF18_PF_PC_WAIT, + PF17_PF_PC_READY, + PF16_PF_PC_PWRON, + PF14_PF_PC_VS1, + PF13_PF_PC_VS2, + PF12_PF_PC_BVD1, + PF11_PF_PC_BVD2, + PF9_PF_PC_IOIS16, + PF8_PF_PC_RW, + GPIO_IDE_PCOE | GPIO_GPIO | GPIO_OUT, /* PCOE */ + GPIO_IDE_RESET | GPIO_GPIO | GPIO_OUT, /* Reset */ + GPIO_IDE_POWER | GPIO_GPIO | GPIO_OUT, /* Power */ + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i] | GPIO_PUEN); + + /* Always set PCOE signal to low */ + gpio_set_value(GPIO_IDE_PCOE, 0); + + /* Assert RESET line */ + gpio_set_value(GPIO_IDE_RESET, 0); + + /* Power up CF-card (Also switched on User-LED) */ + gpio_set_value(GPIO_IDE_POWER, 1); + mdelay(10); + + /* Reset PCMCIA Status Change Register */ + writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR); + mdelay(10); + + /* Check PCMCIA Input Pins Register for Card Detect & Power */ + if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) & + ((1 << 8) | (3 << 3))) != (1 << 8)) { + printf("CompactFlash card not found. Driver not enabled.\n"); + return; + } + + /* Disable all interrupts */ + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER); + + /* Disable all PCMCIA banks */ + for (i = 0; i < 5; i++) + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(i)); + + /* Not use internal PCOE */ + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR); + + /* Setup PCMCIA bank0 for Common memory mode */ + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0)); + writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0)); + writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf, + MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); + + /* Clear PCMCIA General Status Register */ + writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR); + + /* Make PCMCIA bank0 valid */ + i = readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); + writel(i | (1 << 29), MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0)); + + platform_device_register(&pcm970_ide_device); +} + +static void pcm970_mmc_init(void) +{ + uint32_t i; + unsigned int mode[] = { + /* SD2 */ + PB4_PF_SD2_D0, + PB5_PF_SD2_D1, + PB6_PF_SD2_D2, + PB7_PF_SD2_D3, + PB8_PF_SD2_CMD, + PB9_PF_SD2_CLK, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + imx27_add_mmc1(NULL); +} + +struct imxusb_platformdata pcm970_usbh2_pdata = { + .flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI, + .mode = IMX_USB_MODE_HOST, +}; + +static int pcm970_init(void) +{ + int i; + unsigned int mode[] = { + /* USB Host 2 */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + 4 | GPIO_PORTA | GPIO_GPIO | GPIO_OUT, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, + }; + + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + + /* Configure SJA1000 on cs4 */ + imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); + + if (IS_ENABLED(CONFIG_USB)) { + /* Stop ULPI */ + gpio_direction_output(4, 1); + mdelay(1); + imx_gpio_mode(PA4_PF_USBH2_STP); + + imx27_add_usbh2(&pcm970_usbh2_pdata); + } + + if (IS_ENABLED(CONFIG_DISK_INTF_PLATFORM_IDE)) + pcm970_ide_init(); + + if (IS_ENABLED(CONFIG_MCI_IMX)) + pcm970_mmc_init(); + + return 0; +} + +late_initcall(pcm970_init); diff --git a/arch/arm/boards/phytec-phycore-imx27/pll.h b/arch/arm/boards/phytec-phycore-imx27/pll.h new file mode 100644 index 0000000..8bdb76d --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx27/pll.h @@ -0,0 +1,68 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/** + * @file + * @brief phyCORE-i.MX27 specific PLL setup + */ + +#ifndef __PCM038_PLL_H +#define __PCM038_PLL_H + +/* define the PLL setting we want to run the system */ + +/* main clock divider settings immediately after reset (at 1.25 V core supply) */ +#define CSCR_VAL (MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ + MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ + MX27_CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ + MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + MX27_CSCR_FPM_EN | \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN) + +/* main clock divider settings after core voltage increases to 1.45 V */ +#define CSCR_VAL_FINAL (MX27_CSCR_USB_DIV(3) | \ + MX27_CSCR_SD_CNT(3) | \ + MX27_CSCR_MSHC_SEL | \ + MX27_CSCR_H264_SEL | \ + MX27_CSCR_SSI1_SEL | \ + MX27_CSCR_SSI2_SEL | \ + MX27_CSCR_SP_SEL | /* 26 MHz reference */ \ + MX27_CSCR_MCU_SEL | /* 26 MHz reference */ \ + MX27_CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ + MX27_CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ + MX27_CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ + MX27_CSCR_FPM_EN | /* do not disable it! */ \ + MX27_CSCR_SPEN | \ + MX27_CSCR_MPEN) + +/* MPLL should provide a 399 MHz clock from the 26 MHz reference */ +#define MPCTL0_VAL (IMX_PLL_PD(0) | \ + IMX_PLL_MFD(51) | \ + IMX_PLL_MFI(7) | \ + IMX_PLL_MFN(35)) + +/* SPLL should provide a 240 MHz clock from the 26 MHz reference */ +#define SPCTL0_VAL (IMX_PLL_PD(1) | \ + IMX_PLL_MFD(12) | \ + IMX_PLL_MFI(9) | \ + IMX_PLL_MFN(3)) + + +#endif /* __PCM038_PLL_H */ diff --git a/arch/arm/boards/phytec-phycore-imx31/Makefile b/arch/arm/boards/phytec-phycore-imx31/Makefile new file mode 100644 index 0000000..6c9ca69 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/Makefile @@ -0,0 +1,20 @@ +# +# (C) Copyright 2007 Juergen Beisert +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# + +lwl-y += lowlevel.o +obj-y += pcm037.o diff --git a/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi b/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi new file mode 100644 index 0000000..67b0cb4 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/env/boot/nand-ubi @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-imx31/env/config-board b/arch/arm/boards/phytec-phycore-imx31/env/config-board new file mode 100644 index 0000000..e8e8378 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/env/config-board @@ -0,0 +1,6 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand new file mode 100644 index 0000000..84220b7 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" +kernelname="mxc_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor new file mode 100644 index 0000000..2ef6ead --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="256k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx31/lowlevel.c b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c new file mode 100644 index 0000000..cd894c2 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/lowlevel.c @@ -0,0 +1,136 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10) + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + uint32_t r; + volatile int v; + + arm_cpu_lowlevel_init(); + + writel(1 << 6, MX31_IPU_CTRL_BASE_ADDR); + + writel(0x074B0BF5, MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + for (v = 0; v < 0x4000; v++); + + writel(0x074B0BF5 | MX31_CCMR_MPE, MX31_CCM_BASE_ADDR + + MX31_CCM_CCMR); + writel((0x074B0BF5 | MX31_CCMR_MPE) & ~MX31_CCMR_MDS, + MX31_CCM_BASE_ADDR + MX31_CCM_CCMR); + + writel(MX31_PDR0_CSI_PODF(0xff1) | \ + MX31_PDR0_PER_PODF(7) | \ + MX31_PDR0_HSP_PODF(3) | \ + MX31_PDR0_NFC_PODF(5) | \ + MX31_PDR0_IPG_PODF(1) | \ + MX31_PDR0_MAX_PODF(3) | \ + MX31_PDR0_MCU_PODF(0), \ + MX31_CCM_BASE_ADDR + MX31_CCM_PDR0); + + writel(IMX_PLL_PD(0) | IMX_PLL_MFD(0xe) | + IMX_PLL_MFI(9) | IMX_PLL_MFN(0xd), + MX31_CCM_BASE_ADDR + MX31_CCM_MPCTL); + writel(IMX_PLL_PD(1) | IMX_PLL_MFD(0x43) | IMX_PLL_MFI(12) | + IMX_PLL_MFN(1), MX31_CCM_BASE_ADDR + + MX31_CCM_SPCTL); + + /* + * Configure IOMUXC + * Clears 0x43fa_c26c - 0x43fa_c2dc with 0, except 0x43fa_c278 (untouched), + * 0x43fa_c27c (set to 0x1000) and 0x43fa_c280 (untouched) + * (behaviour copied by sha, source unknown) + */ + writel(0, 0x43fac26c); + writel(0, 0x43fac270); + writel(0, 0x43fac274); + + writel(0x1000, 0x43fac27c); + + for (r = 0x43fac284; r <= 0x43fac2dc; r += 4) + writel(0, r); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0xa0000000) + imx31_barebox_entry(0); + +#if defined CONFIG_PCM037_SDRAM_BANK0_128MB +#define ROWS0 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK0_256MB +#define ROWS0 ESDCTL0_ROW14 +#endif + writel(0x00000004, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG0); + writel(0x90100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR + 0xf00); + writel(0xa0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0x12344321, MX31_CSD0_BASE_ADDR); + writel(0xb0100000 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writeb(0xda, MX31_CSD0_BASE_ADDR + 0x33); + writeb(0xff, MX31_CSD0_BASE_ADDR + 0x01000000); + writel(0x80226080 | ROWS0, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL0); + writel(0xDEADBEEF, MX31_CSD0_BASE_ADDR); + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); + +#ifndef CONFIG_PCM037_SDRAM_BANK1_NONE +#if defined CONFIG_PCM037_SDRAM_BANK1_128MB +#define ROWS1 ESDCTL0_ROW13 +#elif defined CONFIG_PCM037_SDRAM_BANK1_256MB +#define ROWS1 ESDCTL0_ROW14 +#endif + writel(0x006ac73a, MX31_ESDCTL_BASE_ADDR + IMX_ESDCFG1); + writel(0x90100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0x12344321, MX31_CSD1_BASE_ADDR + 0xf00); + writel(0xa0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0x12344321, MX31_CSD1_BASE_ADDR); + writel(0x12344321, MX31_CSD1_BASE_ADDR); + writel(0xb0100000 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writeb(0xda, MX31_CSD1_BASE_ADDR + 0x33); + writeb(0xff, MX31_CSD1_BASE_ADDR + 0x01000000); + writel(0x80226080 | ROWS1, MX31_ESDCTL_BASE_ADDR + IMX_ESDCTL1); + writel(0xDEADBEEF, MX31_CSD1_BASE_ADDR); + writel(0x0000000c, MX31_ESDCTL_BASE_ADDR + IMX_ESDMISC); +#endif + + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* setup a stack to be able to call imx31_barebox_boot_nand_external() */ + arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 12); + + imx31_barebox_boot_nand_external(0); + } else { + imx31_barebox_entry(0); + } +} diff --git a/arch/arm/boards/phytec-phycore-imx31/pcm037.c b/arch/arm/boards/phytec-phycore-imx31/pcm037.c new file mode 100644 index 0000000..a1ffb2e --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/pcm037.c @@ -0,0 +1,256 @@ +/* + * (C) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * Board support for Phytec's, i.MX31 based CPU card, called: PCM037 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +#ifdef CONFIG_USB +static void pcm037_usb_init(void) +{ + u32 tmp; + + /* enable clock */ + tmp = readl(0x53f80000); + tmp |= (1 << 9); + writel(tmp, 0x53f80000); + + /* Host 1 */ + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); + tmp &= ~((3 << 21) | 1); + tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20); + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); + + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x184); + tmp &= ~(3 << 30); + tmp |= 2 << 30; + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x184); + + imx_iomux_mode(MX31_PIN_USBOTG_DATA0__USBOTG_DATA0); + imx_iomux_mode(MX31_PIN_USBOTG_DATA1__USBOTG_DATA1); + imx_iomux_mode(MX31_PIN_USBOTG_DATA2__USBOTG_DATA2); + imx_iomux_mode(MX31_PIN_USBOTG_DATA3__USBOTG_DATA3); + imx_iomux_mode(MX31_PIN_USBOTG_DATA4__USBOTG_DATA4); + imx_iomux_mode(MX31_PIN_USBOTG_DATA5__USBOTG_DATA5); + imx_iomux_mode(MX31_PIN_USBOTG_DATA6__USBOTG_DATA6); + imx_iomux_mode(MX31_PIN_USBOTG_DATA7__USBOTG_DATA7); + imx_iomux_mode(MX31_PIN_USBOTG_CLK__USBOTG_CLK); + imx_iomux_mode(MX31_PIN_USBOTG_DIR__USBOTG_DIR); + imx_iomux_mode(MX31_PIN_USBOTG_NXT__USBOTG_NXT); + imx_iomux_mode(MX31_PIN_USBOTG_STP__USBOTG_STP); + + mdelay(50); + ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x170), 1); + + /* Host 2 */ + tmp = readl(MX31_IOMUXC_GPR); + tmp |= 1 << 11; /* IOMUX GPR: enable USBH2 signals */ + writel(tmp, MX31_IOMUXC_GPR); + + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)); + imx_iomux_mode(IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)); + +#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + imx_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); + imx_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ + imx_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ + imx_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ + imx_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ + imx_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ + imx_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ + imx_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ + imx_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ + + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x600); + tmp &= ~((3 << 21) | 1); + tmp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20); + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x600); + + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x584); + tmp &= ~(3 << 30); + tmp |= 2 << 30; + writel(tmp, MX31_USB_OTG_BASE_ADDR + 0x584); + + mdelay(50); + ulpi_setup((void *)(MX31_USB_OTG_BASE_ADDR + 0x570), 1); + + /* Set to Host mode */ + tmp = readl(MX31_USB_OTG_BASE_ADDR + 0x1a8); + writel(tmp | 0x3, MX31_USB_OTG_BASE_ADDR + 0x1a8); + +} +#endif + +static int pcm037_mmu_init(void) +{ + l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); + + return 0; +} +postmmu_initcall(pcm037_mmu_init); + +static struct smc911x_plat smsc9217_pdata = { + .flags = SMC911X_FORCE_INTERNAL_PHY, +}; + +static int pcm037_devices_init(void) +{ + /* CS0: Nor Flash */ + imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900); + /* CS1: Network Controller */ + imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302); + /* CS4: SRAM */ + imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00); + /* CS5: SJA1000 */ + imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302); + + /* + * Up to 32MiB NOR type flash, connected to + * CS line 0, data width is 16 bit + */ + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); + + imx31_add_mmc0(NULL); + + /* + * Create partitions that should be + * not touched by any regular user + */ + devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */ + devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */ + + protect_file("/dev/env0", 1); + + /* + * up to 2MiB static RAM type memory, connected + * to CS4, data width is 16 bit + */ + add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */ + IORESOURCE_MEM_WRITEABLE); + imx31_add_nand(&nand_info); + + /* + * SMSC 9217 network controller + * connected to CS line 1 and interrupt line + * GPIO3, data width is 16 bit + */ + add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR, + MX31_CS1_SIZE, IORESOURCE_MEM, &smsc9217_pdata); + +#ifdef CONFIG_USB + pcm037_usb_init(); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL); + add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL); +#endif + armlinux_set_architecture(MACH_TYPE_PCM037); + + return 0; +} + +device_initcall(pcm037_devices_init); + +static unsigned int pcm037_iomux[] = { + /* UART1 */ + MX31_PIN_RXD1__RXD1, + MX31_PIN_TXD1__TXD1, + MX31_PIN_CTS1__CTS1, + MX31_PIN_RTS1__RTS1, + /* I2C */ + MX31_PIN_CSPI2_MOSI__SCL, + MX31_PIN_CSPI2_MISO__SDA, + MX31_PIN_CSPI2_SS2__I2C3_SDA, + MX31_PIN_CSPI2_SCLK__I2C3_SCL, + /* SDHC1 */ + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, + IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ + IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ + /* SPI1 */ + MX31_PIN_CSPI1_MOSI__MOSI, + MX31_PIN_CSPI1_MISO__MISO, + MX31_PIN_CSPI1_SCLK__SCLK, + MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, + MX31_PIN_CSPI1_SS0__SS0, + MX31_PIN_CSPI1_SS1__SS1, + MX31_PIN_CSPI1_SS2__SS2, + /* UART2 */ + MX31_PIN_TXD2__TXD2, + MX31_PIN_RXD2__RXD2, + MX31_PIN_CTS2__CTS2, + MX31_PIN_RTS2__RTS2, + /* UART3 */ + MX31_PIN_CSPI3_MOSI__RXD3, + MX31_PIN_CSPI3_MISO__TXD3, + MX31_PIN_CSPI3_SCLK__RTS3, + MX31_PIN_CSPI3_SPI_RDY__CTS3, +}; + +static int imx31_console_init(void) +{ + imx_iomux_setup_multiple_pins(pcm037_iomux, ARRAY_SIZE(pcm037_iomux)); + + barebox_set_model("Phytec phyCORE-i.MX31"); + barebox_set_hostname("phycore-imx31"); + + imx31_add_uart0(); + return 0; +} + +console_initcall(imx31_console_init); diff --git a/arch/arm/boards/phytec-phycore-imx31/pcm037.dox b/arch/arm/boards/phytec-phycore-imx31/pcm037.dox new file mode 100644 index 0000000..b2afdd6 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx31/pcm037.dox @@ -0,0 +1,11 @@ +/** @page pcm037 Phytec's phyCORE-i.MX31 + +This CPU card is based on a Freescale i.MX31 CPU. The card is shipped with: + +- up to 64MiB NOR type Flash Memory +- up to 2MiB static RAM +- 64MiB NAND type Flash Memory +- SMSC 9217 network controller +- 128MiB synchronous dynamic RAM + +*/ diff --git a/arch/arm/boards/phytec-phycore-imx35/Makefile b/arch/arm/boards/phytec-phycore-imx35/Makefile new file mode 100644 index 0000000..72275ea --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/Makefile @@ -0,0 +1,20 @@ +# +# (C) Copyright 2007 Juergen Beisert +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# + +lwl-y += lowlevel.o +obj-y += pcm043.o diff --git a/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi b/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi new file mode 100644 index 0000000..67b0cb4 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/env/boot/nand-ubi @@ -0,0 +1,10 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + boot-menu-add-entry "$0" "nand (UBI)" + exit +fi + +global.bootm.image="/dev/nand0.kernel.bb" +#global.bootm.oftree="/env/oftree" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=nand0.root rootfstype=ubifs" diff --git a/arch/arm/boards/phytec-phycore-imx35/env/config-board b/arch/arm/boards/phytec-phycore-imx35/env/config-board new file mode 100644 index 0000000..e8e8378 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/env/config-board @@ -0,0 +1,6 @@ +#!/bin/sh + +# board defaults, do not change in running system. Change /env/config +# instead + +global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand new file mode 100644 index 0000000..8a41f62 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nand @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NAND partitions" + exit +fi + +mtdparts="512k(nand0.barebox),256k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)" +kernelname="mxc_nand" + +mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor new file mode 100644 index 0000000..f787f28 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/env/init/mtdparts-nor @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "NOR partitions" + exit +fi + +mtdparts="512k(nor0.barebox),128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" +kernelname="physmap-flash.0" + +mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-imx35/lowlevel.c b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c new file mode 100644 index 0000000..8376bb4 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/lowlevel.c @@ -0,0 +1,200 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Assuming 24MHz input clock */ +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) +#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) + +#define IMX35_CHIP_REVISION_2_1 0x11 + +#define CCM_PDR0_399 0x00011000 +#define CCM_PDR0_532 0x00001000 + +void __bare_init __naked barebox_arm_reset_vector(void) +{ + uint32_t r, s; + unsigned long ccm_base = MX35_CCM_BASE_ADDR; + unsigned long iomuxc_base = MX35_IOMUXC_BASE_ADDR; + unsigned long esdctl_base = MX35_ESDCTL_BASE_ADDR; + + arm_cpu_lowlevel_init(); + + r = get_cr(); + r |= CR_Z; /* Flow prediction (Z) */ + r |= CR_U; /* unaligned accesses */ + r |= CR_FI; /* Low Int Latency */ + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s)); + s |= 0x7; + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s)); + + set_cr(r); + + r = 0; + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * Branch predicition is now enabled. Flush the BTAC to ensure a valid + * starting point. Don't flush BTAC while it is disabled to avoid + * ARM1136 erratum 408023. + */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r)); + + /* invalidate I cache and D cache */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r)); + + /* invalidate TLBs */ + __asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r)); + + /* Drain the write buffer */ + __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r)); + + /* Also setup the Peripheral Port Remap register inside the core */ + r = 0x40000015; /* start from AIPS 2GB region */ + __asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r)); + + /* + * End of ARM1136 init + */ + + writel(0x003F4208, ccm_base + MX35_CCM_CCMR); + + /* Set MPLL , arm clock and ahb clock*/ + writel(MPCTL_PARAM_532, ccm_base + MX35_CCM_MPCTL); + + writel(PPCTL_PARAM_300, ccm_base + MX35_CCM_PPCTL); + + /* Check silicon revision and use 532MHz if >=2.1 */ + r = readl(MX35_IIM_BASE_ADDR + 0x24); + if (r >= IMX35_CHIP_REVISION_2_1) + writel(CCM_PDR0_532, ccm_base + MX35_CCM_PDR0); + else + writel(CCM_PDR0_399, ccm_base + MX35_CCM_PDR0); + + r = readl(ccm_base + MX35_CCM_CGR0); + r |= 0x00300000; + writel(r, ccm_base + MX35_CCM_CGR0); + + r = readl(ccm_base + MX35_CCM_CGR1); + r |= 0x00000C00; + r |= 0x00000003; + writel(r, ccm_base + MX35_CCM_CGR1); + + r = readl(MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); + r |= 0x1000; + writel(r, MX35_L2CC_BASE_ADDR + L2X0_AUX_CTRL); + + /* Skip SDRAM initialization if we run from RAM */ + r = get_pc(); + if (r > 0x80000000 && r < 0x90000000) + goto out; + + /* Set DDR Type to SDRAM, drive strength workaround * + * 0x00000000 MDDR * + * 0x00000800 3,3V SDRAM */ + + r = 0x00000800; + writel(r, iomuxc_base + 0x794); + writel(r, iomuxc_base + 0x798); + writel(r, iomuxc_base + 0x79c); + writel(r, iomuxc_base + 0x7a0); + writel(r, iomuxc_base + 0x7a4); + + /* MDDR init, enable mDDR*/ + writel(0x00000304, esdctl_base + IMX_ESDMISC); /* was 0x00000004 */ + + /* set timing paramters */ + writel(0x0025541F, esdctl_base + IMX_ESDCFG0); + /* select Precharge-All mode */ + writel(0x92220000, esdctl_base + IMX_ESDCTL0); + /* Precharge-All */ + writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); + + /* select Load-Mode-Register mode */ + writel(0xB8001000, esdctl_base + IMX_ESDCTL0); + /* Load reg EMR2 */ + writeb(0xda, 0x84000000); + /* Load reg EMR3 */ + writeb(0xda, 0x86000000); + /* Load reg EMR1 -- enable DLL */ + writeb(0xda, 0x82000400); + /* Load reg MR -- reset DLL */ + writeb(0xda, 0x80000333); + + /* select Precharge-All mode */ + writel(0x92220000, esdctl_base + IMX_ESDCTL0); + /* Precharge-All */ + writel(0x12345678, MX35_CSD0_BASE_ADDR + 0x400); + + /* select Manual-Refresh mode */ + writel(0xA2220000, esdctl_base + IMX_ESDCTL0); + /* Manual-Refresh 2 times */ + writel(0x87654321, MX35_CSD0_BASE_ADDR); + writel(0x87654321, MX35_CSD0_BASE_ADDR); + + /* select Load-Mode-Register mode */ + writel(0xB2220000, esdctl_base + IMX_ESDCTL0); + /* Load reg MR -- CL3, BL8, end DLL reset */ + writeb(0xda, 0x80000233); + /* Load reg EMR1 -- OCD default */ + writeb(0xda, 0x82000780); + /* Load reg EMR1 -- OCD exit */ + writeb(0xda, 0x82000400); + + /* select normal-operation mode + * DSIZ32-bit, BL8, COL10-bit, ROW13-bit + * disable PWT & PRCT + * disable Auto-Refresh */ + writel(0x82220080, esdctl_base + IMX_ESDCTL0); + + /* enable Auto-Refresh */ + writel(0x82228080, esdctl_base + IMX_ESDCTL0); + /* enable Auto-Refresh */ + writel(0x00002000, esdctl_base + IMX_ESDCTL1); + + if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) { + /* Speed up NAND controller by adjusting the NFC divider */ + r = readl(MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + r &= ~(0xf << 28); + r |= 0x1 << 28; + writel(r, MX35_CCM_BASE_ADDR + MX35_CCM_PDR4); + + /* setup a stack to be able to call imx35_barebox_boot_nand_external() */ + arm_setup_stack(MX35_IRAM_BASE_ADDR + MX35_IRAM_SIZE - 8); + + imx35_barebox_boot_nand_external(0); + } + +out: + imx35_barebox_entry(0); +} diff --git a/arch/arm/boards/phytec-phycore-imx35/pcm043.c b/arch/arm/boards/phytec-phycore-imx35/pcm043.c new file mode 100644 index 0000000..46821a7 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/pcm043.c @@ -0,0 +1,339 @@ +/* + * (C) 2007 Pengutronix, Sascha Hauer + * (C) 2009 Pengutronix, Juergen Beisert + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * Board support for Phytec's, i.MX35 based CPU card, called: PCM043 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct fec_platform_data fec_info = { + .xcv_type = PHY_INTERFACE_MODE_MII, +}; + +struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct fb_videomode pcm043_fb_mode[] = { + { + /* 240x320 @ 60 Hz */ + .name = "TX090", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 38255, + .left_margin = 144, + .right_margin = 0, + .upper_margin = 7, + .lower_margin = 40, + .hsync_len = 96, + .vsync_len = 1, + .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }, { + /* 240x320 @ 60 Hz */ + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, + .yres = 320, + .pixclock = 185925, + .left_margin = 9, + .right_margin = 16, + .upper_margin = 7, + .lower_margin = 9, + .hsync_len = 1, + .vsync_len = 1, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | \ + FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + } +}; + +static struct imx_ipu_fb_platform_data ipu_fb_data = { + .mode = pcm043_fb_mode, + .num_modes = ARRAY_SIZE(pcm043_fb_mode), + .framebuffer_ovl = (void *) (MX35_CSD0_BASE_ADDR + SZ_128M - SZ_1M), + .bpp = 16, +}; + +static int pcm043_mmu_init(void) +{ + l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); + + return 0; +} +postmmu_initcall(pcm043_mmu_init); + +struct gpio_led led0 = { + .gpio = 1 * 32 + 6, +}; + +static int pcm043_devices_init(void) +{ + uint32_t reg; + char *envstr; + unsigned long bbu_nand_flags = 0; + + /* CS0: Nor Flash */ + imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900); + + led_gpio_register(&led0); + + reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR); + /* some fuses provide us vital information about connected hardware */ + if (reg & 0x20000000) + nand_info.width = 2; /* 16 bit */ + else + nand_info.width = 1; /* 8 bit */ + + imx35_add_fec(&fec_info); + /* + * This platform supports NOR and NAND + */ + imx35_add_nand(&nand_info); + /* + * Up to 32MiB NOR type flash, connected to + * CS line 0, data width is 16 bit + */ + add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0); + + switch (bootsource_get()) { + case BOOTSOURCE_NAND: + devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + envstr = "NAND"; + bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT; + break; + case BOOTSOURCE_NOR: + default: + devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */ + devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); /* environment */ + protect_file("/dev/env0", 1); + envstr = "NOR"; + break; + } + + pr_info("using environment from %s flash\n", envstr); + + imx35_add_fb(&ipu_fb_data); + + armlinux_set_architecture(MACH_TYPE_PCM043); + + imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox", + bbu_nand_flags); + + return 0; +} + +device_initcall(pcm043_devices_init); + +static iomux_v3_cfg_t pcm043_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, + MX35_PAD_FEC_RX_DV__FEC_RX_DV, + MX35_PAD_FEC_COL__FEC_COL, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_TX_EN__FEC_TX_EN, + MX35_PAD_FEC_MDC__FEC_MDC, + MX35_PAD_FEC_MDIO__FEC_MDIO, + MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, + MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, + MX35_PAD_FEC_CRS__FEC_CRS, + MX35_PAD_FEC_RDATA0__FEC_RDATA_0, + MX35_PAD_FEC_TDATA0__FEC_TDATA_0, + MX35_PAD_FEC_RDATA1__FEC_RDATA_1, + MX35_PAD_FEC_TDATA1__FEC_TDATA_1, + MX35_PAD_FEC_RDATA2__FEC_RDATA_2, + MX35_PAD_FEC_TDATA2__FEC_TDATA_2, + MX35_PAD_FEC_RDATA3__FEC_RDATA_3, + MX35_PAD_FEC_TDATA3__FEC_TDATA_3, + MX35_PAD_RXD1__UART1_RXD_MUX, + MX35_PAD_TXD1__UART1_TXD_MUX, + MX35_PAD_RTS1__UART1_RTS, + MX35_PAD_CTS1__UART1_CTS, + MX35_PAD_I2C1_CLK__I2C1_SCL, + MX35_PAD_I2C1_DAT__I2C1_SDA, + MX35_PAD_ATA_CS0__GPIO2_6, /* LED */ +}; + +static int imx35_console_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); + + barebox_set_model("Phytec phyCORE-i.MX35"); + barebox_set_hostname("phycore-imx35"); + + imx35_add_uart0(); + + return 0; +} + +console_initcall(imx35_console_init); + +static int pcm043_core_setup(void) +{ + u32 tmp; + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + writel(0x77777777, MX35_AIPS1_BASE_ADDR); + writel(0x77777777, MX35_AIPS1_BASE_ADDR + 0x4); + writel(0x77777777, MX35_AIPS2_BASE_ADDR); + writel(0x77777777, MX35_AIPS2_BASE_ADDR + 0x4); + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS1_BASE_ADDR + 0x4C); + tmp = readl(MX35_AIPS1_BASE_ADDR + 0x50); + tmp &= 0x00FFFFFF; + writel(tmp, MX35_AIPS1_BASE_ADDR + 0x50); + + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x40); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x44); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x48); + writel(0x0, MX35_AIPS2_BASE_ADDR + 0x4C); + tmp = readl(MX35_AIPS2_BASE_ADDR + 0x50); + tmp &= 0x00FFFFFF; + writel(tmp, MX35_AIPS2_BASE_ADDR + 0x50); + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ +#define MAX_PARAM1 0x00302154 + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x0); /* for S0 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x100); /* for S1 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x200); /* for S2 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x300); /* for S3 */ + writel(MAX_PARAM1, MX35_MAX_BASE_ADDR + 0x400); /* for S4 */ + + /* SGPCR - always park on last master */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x10); /* for S0 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x110); /* for S1 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x210); /* for S2 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x310); /* for S3 */ + writel(0x10, MX35_MAX_BASE_ADDR + 0x410); /* for S4 */ + + /* MGPCR - restore default values */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x800); /* for M0 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0x900); /* for M1 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xa00); /* for M2 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xb00); /* for M3 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xc00); /* for M4 */ + writel(0x0, MX35_MAX_BASE_ADDR + 0xd00); /* for M5 */ + + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + writel(0x40, MX35_M3IF_BASE_ADDR); + + return 0; +} + +core_initcall(pcm043_core_setup); + +#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) +#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) + +static int do_cpufreq(int argc, char *argv[]) +{ + unsigned long freq; + + if (argc != 2) + return COMMAND_ERROR_USAGE; + + freq = simple_strtoul(argv[1], NULL, 0); + + switch (freq) { + case 399: + writel(MPCTL_PARAM_399, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); + break; + case 532: + writel(MPCTL_PARAM_532, MX35_CCM_BASE_ADDR + MX35_CCM_MPCTL); + break; + default: + return COMMAND_ERROR_USAGE; + } + + printf("Switched CPU frequency to %ldMHz\n", freq); + + return 0; +} + +static const __maybe_unused char cmd_cpufreq_help[] = +"Usage: cpufreq 399|532\n" +"\n" +"Set CPU frequency to MHz\n"; + +BAREBOX_CMD_START(cpufreq) + .cmd = do_cpufreq, + .usage = "adjust CPU frequency", + BAREBOX_CMD_HELP(cmd_cpufreq_help) +BAREBOX_CMD_END + diff --git a/arch/arm/boards/phytec-phycore-imx35/pcm043.dox b/arch/arm/boards/phytec-phycore-imx35/pcm043.dox new file mode 100644 index 0000000..c6715ff --- /dev/null +++ b/arch/arm/boards/phytec-phycore-imx35/pcm043.dox @@ -0,0 +1,28 @@ +/** @page pcm043 Phytec's phyCORE-i.MX35 + +This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with: + + +FIXME: +- up to 64 MiB NOR type Flash Memory +- up to 2 MiB static RAM +- 1 GiB or 2 GiB NAND type Flash Memory + - Micron NAND 1 GiB 3,3V 8-bit + - 256 kiB block size + - ? kiB page size + - Manufacturer ID: 0x2c + - Device ID: 0xd3 + - Samsung K9K8G08, 1 GiB + - 128 kiB block size + - 2 kiB page size + - Manufacturer ID: ? + - Device ID: ? + - ST NAND08G, 1 GiB + - 128 kiB block size + - 2 kiB page size + - Manufacturer ID: ? + - Device ID: ? +- 128MiB synchronous dynamic RAM + + +*/ diff --git a/arch/arm/boards/phytec-phycore-omap4460/Makefile b/arch/arm/boards/phytec-phycore-omap4460/Makefile new file mode 100644 index 0000000..5d4eb10 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o mux.o diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c new file mode 100644 index 0000000..baf88a3 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/board.c @@ -0,0 +1,313 @@ +/* + * Copyright (C) 2011 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int pcm049_console_init(void) +{ + barebox_set_model("Phytec phyCORE-OMAP4460"); + barebox_set_hostname("phycore-omap4460"); + + omap44xx_add_uart3(); + + return 0; +} +console_initcall(pcm049_console_init); + +static int pcm049_mem_init(void) +{ +#ifdef CONFIG_1024MB_DDR2RAM + omap_add_ram0(SZ_1G); +#else + omap_add_ram0(SZ_512M); +#endif + + omap44xx_add_sram0(); + return 0; +} +mem_initcall(pcm049_mem_init); + +static struct gpmc_config net_cfg = { + .cfg = { + 0xc1001000, /* CONF1 */ + 0x00070700, /* CONF2 */ + 0x00000000, /* CONF3 */ + 0x07000700, /* CONF4 */ + 0x09060909, /* CONF5 */ + 0x000003c2, /* CONF6 */ + }, + .base = 0x2C000000, + .size = GPMC_SIZE_16M, +}; + +static void pcm049_network_init(void) +{ + gpmc_cs_config(5, &net_cfg); + + add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x2C000000, 0x4000, + IORESOURCE_MEM, NULL); +} + +static struct i2c_board_info i2c_devices[] = { + { + I2C_BOARD_INFO("twl6030", 0x48), + }, +}; + +static struct gpmc_nand_platform_data nand_plat = { + .wait_mon_pin = 1, + .ecc_mode = OMAP_ECC_BCH8_CODE_HW, + .nand_cfg = &omap4_nand_cfg, +}; + +static struct omapfb_display const pcm049_displays[] = { + { + .mode = { + .name = "pd050vl1", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 25000, + .left_margin = 46, + .right_margin = 18, + .hsync_len = 96, + .upper_margin = 33, + .lower_margin = 10, + .vsync_len = 2, + }, + + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + }, + /* Prime-View PM070WL4 */ + { + .mode = { + .name = "pm070wl4", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 32000, + .left_margin = 86, + .right_margin = 42, + .hsync_len = 128, + .lower_margin = 10, + .upper_margin = 33, + .vsync_len = 2, + }, + + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + }, + /* Prime-View PD104SLF */ + { + .mode = { + .name = "pd104slf", + .refresh = 60, + .xres = 800, + .yres = 600, + .pixclock = 40000, + .left_margin = 86, + .right_margin = 42, + .hsync_len = 128, + .lower_margin = 1, + .upper_margin = 23, + .vsync_len = 4, + }, + + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + }, + /* EDT ETM0350G0DH6 */ + { + .mode = { + .name = "edt_etm0350G0dh6", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = 15720, + .left_margin = 68, + .right_margin = 20, + .hsync_len = 88, + .lower_margin = 4, + .upper_margin = 18, + .vsync_len = 22, + }, + + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + }, + /* EDT ETM0430G0DH6 */ + { + .mode = { + .name = "edt_etm0430G0dh6", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 9000, + .left_margin = 2, + .right_margin = 2, + .hsync_len = 41, + .lower_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + }, + + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + }, + /* EDT ETMV570G2DHU */ + { + .mode = { + .name = "edt_etmv570G2dhu", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 25175, + .left_margin = 114, + .right_margin = 16, + .hsync_len = 30, + .lower_margin = 10, + .upper_margin = 35, + .vsync_len = 3, + }, + + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + }, + /* ETD ETM0700G0DH6 */ + { + .mode = { + .name = "edt_etm0700G0dh6", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = 33260, + .left_margin = 216, + .right_margin = 40, + .hsync_len = 128, + .lower_margin = 10, + .upper_margin = 35, + .vsync_len = 2, + }, + + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + }, + + /* CHIMEI G104X1-L03 */ + { + .mode = { + .name = "g104x1", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 64000, + .left_margin = 320, + .right_margin = 1, + .hsync_len = 320, + .upper_margin = 38, + .lower_margin = 38, + .vsync_len = 2, + }, + .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | + OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | + OMAP_DSS_LCD_DATALINES_24), + + .power_on_delay = 50, + .power_off_delay = 100, + }, +}; + +#define GPIO_DISPENABLE 118 +#define GPIO_BACKLIGHT 122 + +static void pcm049_fb_enable(int e) +{ + gpio_direction_output(GPIO_DISPENABLE, e); + gpio_direction_output(GPIO_BACKLIGHT, e); +} + +static struct omapfb_platform_data pcm049_fb_data = { + .displays = pcm049_displays, + .num_displays = ARRAY_SIZE(pcm049_displays), + + .dss_clk_hz = 19200000, + + .bpp = 32, + .enable = pcm049_fb_enable, +}; + +static int pcm049_devices_init(void) +{ + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + omap44xx_add_i2c1(NULL); + omap44xx_add_mmc1(NULL); + + gpmc_generic_init(0x10); + + if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X)) + pcm049_network_init(); + + omap_add_gpmc_nand_device(&nand_plat); + +#ifdef CONFIG_PARTITION + devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "xload_raw"); + dev_add_bb_dev("xload_raw", "xload"); + devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); +#endif + + armlinux_set_architecture(MACH_TYPE_PCM049); + + if (IS_ENABLED(CONFIG_DRIVER_VIDEO_OMAP)) + omap_add_display(&pcm049_fb_data); + + return 0; +} +device_initcall(pcm049_devices_init); diff --git a/arch/arm/boards/phytec-phycore-omap4460/env/bin/init_board b/arch/arm/boards/phytec-phycore-omap4460/env/bin/init_board new file mode 100644 index 0000000..d5142ee --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/env/bin/init_board @@ -0,0 +1,23 @@ +#!/bin/sh +global displayargs +. /env/config + +if [ -z $display ]; then + echo "no display configured" + exit 0 +fi + +if [ $display = dvi ]; then + global.displayargs="omapdss.def_disp=dvi omapfb.mode=dvi:$dvi_resolution" + exit 0 +fi + +# Display a splash screen + +if [ -e /dev/fb0 ]; then + fb0.mode_name=$display + splash /dev/nand0.splash.bb + fb0.enable=1 +fi + +global.displayargs="panel_generic_dpi.name=$display" diff --git a/arch/arm/boards/phytec-phycore-omap4460/env/bin/nand_bootstrap b/arch/arm/boards/phytec-phycore-omap4460/env/bin/nand_bootstrap new file mode 100644 index 0000000..49e38dc --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/env/bin/nand_bootstrap @@ -0,0 +1,31 @@ +#!/bin/sh +echo "copying barebox to nand..." + +mci0.probe=1 +mkdir mnt + +mount /dev/disk0.0 /mnt +if [ $? != 0 ]; then + echo "failed to mount mmc card" + exit 1 +fi + +if [ ! -f /mnt/mlo-nand.bin ]; then + echo "mlo-nand.bin not found on mmc card" + exit 1 +fi + +if [ ! -f /mnt/barebox.bin ]; then + echo "barebox.bin not found on mmc card" +fi + +gpmc_nand0.eccmode=bch8_hw_romcode +erase /dev/nand0.xload.bb +cp /mnt/mlo-nand.bin /dev/nand0.xload.bb + +gpmc_nand0.eccmode=bch8_hw +erase /dev/nand0.barebox.bb +cp /mnt/barebox.bin /dev/nand0.barebox.bb + +echo "success" + diff --git a/arch/arm/boards/phytec-phycore-omap4460/env/config b/arch/arm/boards/phytec-phycore-omap4460/env/config new file mode 100644 index 0000000..1a252dd --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/env/config @@ -0,0 +1,61 @@ +#!/bin/sh + +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=tftp +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-${global.hostname}.$rootfs_type + +kernelimage=zImage-${global.hostname} +#kernelimage=uImage-${global.hostname} +#kernelimage=Image-${global.hostname} +#kernelimage=Image-${global.hostname}.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttyO2,115200" + +nand_parts="128k(xload)ro,512k(barebox),128k(bareboxenv),4M(kernel),4M(splash),-(root)" +nand_device="omap2-nand.0" +rootfs_mtdblock_nand=5 + +#Displays +# Splashscreen-Display can be either '', 'pd050vl1', 'pm070wl4', 'pd104slf', 'g104x1' +# 'edt_etm0350G0dh6', 'edt_etm0430G0dh6', 'edt_etmv570G2dhu' or 'edt_etm0700G0dh6' +# to use dvi output in kernel set 'display=dvi' and +# dvi_resolution to '640x480-60' '800x600-60' or '1024x768-60' + +display=edt_etm0700G0dh6 +#dvi_resolution=1024x768-60 + +if [ -n ${global.displayargs} ]; then + bootargs="$bootargs ${global.displayargs}" +fi + +# set a fancy prompt (if support is compiled in) +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " + diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c new file mode 100644 index 0000000..4f39600 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TPS62361_VSEL0_GPIO 182 + +void set_muxconf_regs(void); + +/* 512MB */ +static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { + .tim1 = 0x0EEB0662, + .tim2 = 0x20370DD2, + .tim3 = 0x00BFC33F, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x00000618, + .config_init = 0x80001AB1, + .config_final = 0x80001AB1, + .zq_config = 0xd0093215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +/* 1GB */ +static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = { + .tim1 = 0x0EEB0663, + .tim2 = 0x205715D2, + .tim3 = 0x00BFC53F, + .phy_ctrl_1 = 0x849FF408, + .ref_ctrl = 0x00000618, + .config_init = 0x80001AB9, + .config_final = 0x80001AB9, + .zq_config = 0x50093215, + .mr1 = 0x83, + .mr2 = 0x4 +}; + +static void noinline pcm049_init_lowlevel(void) +{ + struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; + struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; + struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; + struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; + struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; + struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; + struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; + unsigned int rev = omap4_revision(); + + set_muxconf_regs(); + +#ifdef CONFIG_1024MB_DDR2RAM + omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core); +#else + omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); +#endif + + /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ + if (rev < OMAP4460_ES1_0) + omap4430_scale_vcores(); + else + omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); + + writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); + + /* Configure all DPLL's at 100% OPP */ + if (rev < OMAP4460_ES1_0) + omap4_configure_mpu_dpll(&mpu44xx); + else + omap4_configure_mpu_dpll(&mpu4460); + + omap4_configure_iva_dpll(&iva); + omap4_configure_per_dpll(&per); + omap4_configure_abe_dpll(&abe); + omap4_configure_usb_dpll(&usb); + + /* Enable all clocks */ + omap4_enable_all_clocks(); + + sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1); /* enable software ioreq */ + sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ + sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x0); /* set divisor to 1 */ + sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1); /* activate clock source */ + sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ +} + +void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) +{ + omap4_save_bootinfo(data); + + arm_cpu_lowlevel_init(); + + if (get_pc() > 0x80000000) + goto out; + + arm_setup_stack(0x4030d000); + + pcm049_init_lowlevel(); +out: + barebox_arm_entry(0x80000000, SZ_512M, 0); +} diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.c b/arch/arm/boards/phytec-phycore-omap4460/mux.c new file mode 100644 index 0000000..fda4c51 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-omap4460/mux.c @@ -0,0 +1,253 @@ +#include +#include +#include +#include +#include +#include + +static const struct pad_conf_entry core_padconf_array[] = { + {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ + {GPMC_AD1, (IEN | PTD | DIS | M0)}, /* gpmc_ad1 */ + {GPMC_AD2, (IEN | PTD | DIS | M0)}, /* gpmc_ad2 */ + {GPMC_AD3, (IEN | PTD | DIS | M0)}, /* gpmc_ad3 */ + {GPMC_AD4, (IEN | PTD | DIS | M0)}, /* gpmc_ad4 */ + {GPMC_AD5, (IEN | PTD | DIS | M0)}, /* gpmc_ad5 */ + {GPMC_AD6, (IEN | PTD | DIS | M0)}, /* gpmc_ad6 */ + {GPMC_AD7, (IEN | PTD | DIS | M0)}, /* gpmc_ad7 */ + {GPMC_AD8, (IEN | PTD | DIS | M0)}, /* gpmc_ad8 */ + {GPMC_AD9, (IEN | PTD | DIS | M0)}, /* gpmc_ad9 */ + {GPMC_AD10, (IEN | PTD | DIS | M0)}, /* gpmc_ad10 */ + {GPMC_AD11, (IEN | PTD | DIS | M0)}, /* gpmc_ad11 */ + {GPMC_AD12, (IEN | PTD | DIS | M0)}, /* gpmc_ad12 */ + {GPMC_AD13, (IEN | PTD | DIS | M0)}, /* gpmc_ad13 */ + {GPMC_AD14, (IEN | PTD | DIS | M0)}, /* gpmc_ad14 */ + {GPMC_AD15, (IEN | PTD | DIS | M0)}, /* gpmc_ad15 */ + {GPMC_A16, (IEN | PTD | DIS | M0)}, /* gpmc_a16 */ + {GPMC_A17, (IEN | PTD | DIS | M0)}, /* gpmc_a17 */ + {GPMC_A18, (IEN | PTD | DIS | M0)}, /* gpmc_a18 */ + {GPMC_A19, (IEN | PTD | DIS | M0)}, /* gpmc_a19 */ + {GPMC_A20, (IEN | PTD | DIS | M0)}, /* gpmc_a20 */ + {GPMC_A21, (IEN | PTD | DIS | M0)}, /* gpmc_a21 */ + {GPMC_A22, (IEN | PTD | DIS | M0)}, /* gpmc_a22 */ + {GPMC_A23, (IEN | PTD | DIS | M0)}, /* gpmc_a23 */ + {GPMC_A24, (IEN | PTD | DIS | M0)}, /* gpmc_a24 */ + {GPMC_A25, (IEN | PTD | DIS | M0)}, /* gpmc_a25 */ + {GPMC_NCS0, (IDIS | PTU | EN | M0)}, /* gpmc_nsc0 */ + {GPMC_NCS1, (IDIS | PTU | EN | M0)}, /* gpmc_nsc1 */ + {GPMC_NCS2, (SAFE_MODE)}, /* nc */ + {GPMC_NCS3, (SAFE_MODE)}, /* nc */ + {GPMC_NWP, (IEN | PTD | DIS | M0)}, /* gpmc_nwp */ + {GPMC_CLK, (SAFE_MODE)}, /* nc */ + {GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)}, /* gpmc_ndav_ale */ + {GPMC_NOE, (IDIS | PTD | DIS | M0)}, /* gpmc_noe */ + {GPMC_NWE, (IDIS | PTD | DIS | M0)}, /* gpmc_nwe */ + {GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)}, /* gpmc_nbe0_cle */ + {GPMC_NBE1, (SAFE_MODE)}, /* nc */ + {GPMC_WAIT0, (IEN | PTU | EN | M0)}, /* gpmc_wait0 */ + {GPMC_WAIT1, (SAFE_MODE)}, /* nc */ + {C2C_DATA11, (SAFE_MODE)}, /* nc */ + {C2C_DATA12, (SAFE_MODE)}, /* nc */ + {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */ + {C2C_DATA14, (SAFE_MODE)}, /* nc */ + {C2C_DATA15, (SAFE_MODE)}, /* nc */ + {HDMI_HPD, (SAFE_MODE)}, /* unused */ + {HDMI_CEC, (SAFE_MODE)}, /* unused */ + {HDMI_DDC_SCL, (SAFE_MODE)}, /* unused */ + {HDMI_DDC_SDA, (SAFE_MODE)}, /* unused */ + {CSI21_DX0, (SAFE_MODE)}, /* unused */ + {CSI21_DY0, (SAFE_MODE)}, /* unused */ + {CSI21_DX1, (SAFE_MODE)}, /* unused */ + {CSI21_DY1, (SAFE_MODE)}, /* unused */ + {CSI21_DX2, (SAFE_MODE)}, /* unused */ + {CSI21_DY2, (SAFE_MODE)}, /* unused */ + {CSI21_DX3, (SAFE_MODE)}, /* unused */ + {CSI21_DY3, (SAFE_MODE)}, /* unused */ + {CSI21_DX4, (SAFE_MODE)}, /* unused */ + {CSI21_DY4, (SAFE_MODE)}, /* unused */ + {CSI22_DX0, (SAFE_MODE)}, /* unused */ + {CSI22_DY0, (SAFE_MODE)}, /* unused */ + {CSI22_DX1, (SAFE_MODE)}, /* unused */ + {CSI22_DY1, (SAFE_MODE)}, /* unused */ + {CAM_SHUTTER, (SAFE_MODE)}, /* unused */ + {CAM_STROBE, (SAFE_MODE)}, /* unused */ + {CAM_GLOBALRESET, (SAFE_MODE)}, /* unused */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (SAFE_MODE)}, /* nc */ + {USBB1_HSIC_STROBE, (SAFE_MODE)}, /* nc */ + {USBC1_ICUSB_DP, (SAFE_MODE)}, /* unused */ + {USBC1_ICUSB_DM, (SAFE_MODE)}, /* unused */ + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {SDMMC1_DAT4, (SAFE_MODE)}, /* unused */ + {SDMMC1_DAT5, (SAFE_MODE)}, /* unused */ + {SDMMC1_DAT6, (SAFE_MODE)}, /* unused */ + {SDMMC1_DAT7, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_CLKX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_DR, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_DX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP2_FSX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_CLKX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_DR, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_DX, (SAFE_MODE)}, /* unused */ + {ABE_MCBSP1_FSX, (SAFE_MODE)}, /* unused */ + {ABE_PDM_UL_DATA, (SAFE_MODE)}, /* unused */ + {ABE_PDM_DL_DATA, (SAFE_MODE)}, /* unused */ + {ABE_PDM_FRAME, (SAFE_MODE)}, /* unused */ + {ABE_PDM_LB_CLK, (SAFE_MODE)}, /* unused */ + {ABE_CLKS, (M3)}, /* gpio_118 */ + {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */ + {ABE_DMIC_DIN1, (SAFE_MODE)}, /* unused */ + {ABE_DMIC_DIN2, (DIS | IEN | M3)}, /* gpio_121 */ + {ABE_DMIC_DIN3, (M3)}, /* gpio_122 */ + {UART2_CTS, (SAFE_MODE)}, /* unused */ + {UART2_RTS, (SAFE_MODE)}, /* unused */ + {UART2_RX, (SAFE_MODE)}, /* unused */ + {UART2_TX, (SAFE_MODE)}, /* unused */ + {HDQ_SIO, (SAFE_MODE)}, /* unused */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (SAFE_MODE)}, /* unused */ + {I2C2_SDA, (SAFE_MODE)}, /* unused */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ + {MCSPI1_CLK, (SAFE_MODE)}, /* unused */ + {MCSPI1_SOMI, (SAFE_MODE)}, /* unused */ + {MCSPI1_SIMO, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS0, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS1, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS2, (SAFE_MODE)}, /* unused */ + {MCSPI1_CS3, (SAFE_MODE)}, /* unused */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)}, /* uart3_tx */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (SAFE_MODE)}, /* nc */ + {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */ + {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */ + {MCSPI4_CS0, (SAFE_MODE)}, /* nc */ + {UART4_RX, (SAFE_MODE)}, /* unused */ + {UART4_TX, (SAFE_MODE)}, /* unused */ + {USBB2_ULPITLL_CLK, (SAFE_MODE)}, /* nc */ + {USBB2_ULPITLL_STP, (M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (M5)}, /* dispc2_data21 */ + {USBB2_ULPITLL_DAT0, (M5)}, /* dispc2_data20 */ + {USBB2_ULPITLL_DAT1, (M5)}, /* dispc2_data19 */ + {USBB2_ULPITLL_DAT2, (M5)}, /* dispc2_data18 */ + {USBB2_ULPITLL_DAT3, (M5)}, /* dispc2_data15 */ + {USBB2_ULPITLL_DAT4, (M5)}, /* dispc2_data14 */ + {USBB2_ULPITLL_DAT5, (M5)}, /* dispc2_data13 */ + {USBB2_ULPITLL_DAT6, (M5)}, /* dispc2_data12 */ + {USBB2_ULPITLL_DAT7, (M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (SAFE_MODE)}, /* nc */ + {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */ + {UNIPRO_TX0, (SAFE_MODE)}, /* unused */ + {UNIPRO_TY0, (SAFE_MODE)}, /* unused */ + {UNIPRO_TX1, (SAFE_MODE)}, /* unused */ + {UNIPRO_TY1, (SAFE_MODE)}, /* unused */ + {UNIPRO_TX2, (SAFE_MODE)}, /* unused */ + {UNIPRO_TY2, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX0, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY0, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX1, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY1, (SAFE_MODE)}, /* unused */ + {UNIPRO_RX2, (SAFE_MODE)}, /* unused */ + {UNIPRO_RY2, (SAFE_MODE)}, /* unused */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */ + {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (M0)}, /* sys_boot0 */ + {SYS_BOOT0, (M0)}, /* sys_boot */ + {SYS_BOOT1, (M0)}, /* sys_boot */ + {SYS_BOOT2, (M0)}, /* sys_boot */ + {SYS_BOOT3, (M0)}, /* sys_boot */ + {SYS_BOOT4, (M0)}, /* sys_boot */ + {SYS_BOOT5, (M0)}, /* sys_boot */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (SAFE_MODE)}, /* unused */ + {DPM_EMU3, (M5)}, /* dispc2_data10 */ + {DPM_EMU4, (M5)}, /* dispc2_data9 */ + {DPM_EMU5, (M5)}, /* dispc2_data16 */ + {DPM_EMU6, (M5)}, /* dispc2_data17 */ + {DPM_EMU7, (M5)}, /* dispc2_hsync */ + {DPM_EMU8, (M5)}, /* dispc2_pclk */ + {DPM_EMU9, (M5)}, /* dispc2_vsync */ + {DPM_EMU10, (M5)}, /* dispc2_de */ + {DPM_EMU11, (M5)}, /* dispc2_data8 */ + {DPM_EMU12, (M5)}, /* dispc2_data7 */ + {DPM_EMU13, (M5)}, /* dispc2_data6 */ + {DPM_EMU14, (M5)}, /* dispc2_data5 */ + {DPM_EMU15, (M5)}, /* dispc2_data4 */ + {DPM_EMU16, (M5)}, /* dispc2_data3 */ + {DPM_EMU17, (M5)}, /* dispc2_data2 */ + {DPM_EMU18, (M5)}, /* dispc2_data1 */ + {DPM_EMU19, (M5)}, /* dispc2_data0 */ +}; + +static const struct pad_conf_entry wkup_padconf_array[] = { + {GPIO_WK0, (SAFE_MODE)}, /* nc */ + {GPIO_WK1, (SAFE_MODE)}, /* nc */ + {GPIO_WK2, (SAFE_MODE)}, /* nc */ + {GPIO_WK3, (SAFE_MODE)}, /* nc */ + {GPIO_WK4, (SAFE_MODE)}, /* nc */ + {SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {FREF_XTAL_IN, (M0)}, /* # */ + {FREF_SLICER_IN, (SAFE_MODE)}, /* nc */ + {FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ + {FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {FREF_CLK3_REQ, (IEN | M3)}, /* gpio_wk30 */ + {FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {FREF_CLK4_REQ, (M0)}, /* fref_clk4_req */ + {FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */ + {SYS_32K, (IEN | M0)}, /* sys_32k */ + {SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {SYS_PWRON_RESET_OUT, (M0)}, /* sys_pwron_reset_out */ + {SYS_BOOT6, (M0)}, /* sys_boot6 */ + {SYS_BOOT7, (M0)}, /* sys_boot7 */ +}; + +void set_muxconf_regs(void) +{ + omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, + ARRAY_SIZE(core_padconf_array)); + + omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, + ARRAY_SIZE(wkup_padconf_array)); + + /* gpio_182 is used for controlling TPS on 4460 */ + if (omap4_revision() >= OMAP4460_ES1_0) { + writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT); + /* Enable GPIO-1 clocks before TPS initialization */ + omap4_enable_gpio_clocks(); + } +} diff --git a/arch/arm/boards/phytec-phycore-pxa270/Makefile b/arch/arm/boards/phytec-phycore-pxa270/Makefile new file mode 100644 index 0000000..040cf93 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-pxa270/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/phytec-phycore-pxa270/board.c b/arch/arm/boards/phytec-phycore-pxa270/board.c new file mode 100644 index 0000000..509569e --- /dev/null +++ b/arch/arm/boards/phytec-phycore-pxa270/board.c @@ -0,0 +1,188 @@ +/* + * (C) 2009 Pengutronix, Sascha Hauer + * 2010 by Marc Kleine-Budde + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define PCM990_CTRL_PHYS (void *)PXA_CS1_PHYS + +#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ +#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ +#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ +#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ +#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ + +static void lcd_power(int on) +{ + void __iomem *ctrl3 = PCM990_CTRL_PHYS + PCM990_CTRL_REG3; + + if (on) + writeb(PCM990_CTRL_LCDPWR | PCM990_CTRL_LCDON, ctrl3); + else + writeb(0x0, ctrl3); +} + +static void backlight_power(int on) +{ + if (on) { + mdelay(20); + gpio_set_value(16, 1); + } else { + gpio_set_value(16, 0); + } +} + +static struct pxafb_videomode pxafb_mode = { + .mode = { + .pixclock = 28000, + .xres = 640, + .yres = 480, + .hsync_len = 20, + .left_margin = 103, + .right_margin = 47, + .vsync_len = 6, + .upper_margin = 28, + .lower_margin = 5, + .sync = 0, + }, + .bpp = 16, +}; + +static struct pxafb_platform_data fb_pdata = { + .mode = &pxafb_mode, + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, + .lcd_power = lcd_power, + .backlight_power = backlight_power, +}; + +static int pcm027_mem_init(void) +{ + arm_add_mem_device("ram0", 0xa0000000, SZ_64M); + + return 0; +} +mem_initcall(pcm027_mem_init); + +static unsigned long pin_config[] = { + /* Chip Selects */ + GPIO20_nSDCS_2, + GPIO21_nSDCS_3, + GPIO15_nCS_1, + GPIO78_nCS_2, + GPIO80_nCS_4, + + /* Variable Latency I/O Ready Pin */ + GPIO18_RDY, + + /* FFUART */ + GPIO85_nPCE_1, /* enables RX */ + GPIO34_FFUART_RXD, + GPIO35_FFUART_CTS, + GPIO36_FFUART_DCD, + GPIO37_FFUART_DSR, + GPIO38_FFUART_RI, + GPIO39_FFUART_TXD, + GPIO40_FFUART_DTR, + GPIO41_FFUART_RTS, + + /* LCD */ + GPIO58_LCD_LDD_0, + GPIO59_LCD_LDD_1, + GPIO60_LCD_LDD_2, + GPIO61_LCD_LDD_3, + GPIO62_LCD_LDD_4, + GPIO63_LCD_LDD_5, + GPIO64_LCD_LDD_6, + GPIO65_LCD_LDD_7, + GPIO66_LCD_LDD_8, + GPIO67_LCD_LDD_9, + GPIO68_LCD_LDD_10, + GPIO69_LCD_LDD_11, + GPIO70_LCD_LDD_12, + GPIO71_LCD_LDD_13, + GPIO72_LCD_LDD_14, + GPIO73_LCD_LDD_15, + GPIO74_LCD_FCLK, + GPIO75_LCD_LCLK, + GPIO76_LCD_PCLK, + GPIO77_LCD_BIAS, + MFP_CFG_OUT(GPIO16, AF0, DRIVE_LOW), /* backlight */ + + /* NIC */ + GPIO33_nCS_5, + GPIO49_nPWE, +}; + +static int pcm027_devices_init(void) +{ + void *cfi_iospace; + + add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x14000300, 16, + IORESOURCE_MEM, NULL); + + cfi_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_32M); + add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_iospace, SZ_32M, 0); + + pxa_add_fb((void *)0x44000000, &fb_pdata); + + armlinux_set_architecture(MACH_TYPE_PCM027); + + devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env0"); + protect_file("/dev/env0", 1); + + return 0; +} + +device_initcall(pcm027_devices_init); + +static int pcm027_console_init(void) +{ + /* route pins */ + pxa2xx_mfp_config(ARRAY_AND_SIZE(pin_config)); + + /* enable clock */ + CKEN |= CKEN_FFUART; + + barebox_set_model("Phytec phyCORE-PXA270"); + barebox_set_hostname("pcm027"); + + pxa_add_uart((void *)0x40100000, 0); + + return 0; +} + +console_initcall(pcm027_console_init); diff --git a/arch/arm/boards/phytec-phycore-pxa270/config.h b/arch/arm/boards/phytec-phycore-pxa270/config.h new file mode 100644 index 0000000..ca02b11 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-pxa270/config.h @@ -0,0 +1,324 @@ +/* + * Copyright (C) 2005 Phytec Messtechnik GmbH + * Juergen Kilb, H. Klaholz + * + * Copyright (C) 2006 Pengutronix + * Sascha Hauer + * Robert Schwebel + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * phyCORE-PXA270 configuration settings + * Set these to 0/1 to enable or disable the features. + */ + +#define PHYCORE_PXA270_USE_K3FLASH 0 + +/* 260 MHz or 520 MHZ */ +#define PHYCORE_PXA270_SPEED 520 + +/********************************************************************* + * CONFIG PXA270 GPIO settings * + *********************************************************************/ + +/* + * GPIO set "1" + * + *** REG GPSR0 + * GP15 == nCS1 is 1 + * GP20 == nSDCS2 is 1 + * GP21 == nSDCS3 is 1 + *** REG GPSR1 + * GP33 == nCS5 is 1 + *** REG GPSR2 + * GP78 == nCS2 is 1 + * GP80 == nCS4 is 1 + */ +#define GPSR0_DFT 0x00308000 +#define GPSR1_DFT 0x00000002 +#define GPSR2_DFT 0x00014000 + +#define CONFIG_GPSR0_VAL GPSR0_DFT +#define CONFIG_GPSR1_VAL GPSR1_DFT +#define CONFIG_GPSR2_VAL GPSR2_DFT +#define CONFIG_GPSR3_VAL GPSR3_DFT + +/* + * set Direction "1" GPIO == output else input + * + ** REG GPDR0 + * GP03 == PWR_SDA is output + * GP04 == PWR_SCL is output + * GP15 == nCS1 is output + * GP20 == nSDCS2 is output + * GP21 == nSDCS3 is output + ** REG GPDR1 + * GP33 == nCS5 is output + ** REG GPDR2 + * GP78 == nCS2 is output + * GP80 == nCS4 is output + * GP90 == LED0 is output + * GP91 == LED1 is output + */ + +#define GPDR0_DFT 0x00308018 +#define GPDR1_DFT 0x00000002 +#define GPDR2_DFT 0x00014000 + +#define CONFIG_GPDR0_VAL GPDR0_DFT +#define CONFIG_GPDR1_VAL GPDR1_DFT +#define CONFIG_GPDR2_VAL GPDR2_DFT + +/* + * set Alternate Funktions + * + ** REG GAFR0_L + * GP15 == nCS1 is AF10 + ** REG GAFR0_U + * GP18 == RDY is AF01 + * GP20 == nSDCS2 is AF01 + * GP21 == nSDCS3 is AF01 + ** REG GAFR1_L + * GP33 == nCS5 is AF10 + ** REG GAFR2_L + * GP78 == nCS2 is AF10 + ** REG GAFR2_U + * GP80 == nCS4 is AF10 + */ + +#define GAFR0_L_DFT 0x80000000 +#define GAFR0_U_DFT 0x00000510 +#define GAFR1_L_DFT 0x00000008 +#define GAFR1_U_DFT 0x00000000 +#define GAFR2_L_DFT 0x20000000 +#define GAFR2_U_DFT 0x00000002 + +#define CONFIG_GAFR0_L_VAL GAFR0_L_DFT +#define CONFIG_GAFR0_U_VAL GAFR0_U_DFT +#define CONFIG_GAFR1_L_VAL GAFR1_L_DFT +#define CONFIG_GAFR1_U_VAL GAFR1_U_DFT +#define CONFIG_GAFR2_L_VAL GAFR2_L_DFT +#define CONFIG_GAFR2_U_VAL GAFR2_U_DFT + + +/* + * Power Manager Sleep Status Register (PSSR) + * + * [6] = 0 OTG pad is not holding it's state + * [5] = 1 Read Disable Hold: receivers of all gpio pins are disabled + * [4] = 1 gpio pins are held in their sleep mode state + * [3] = 0 The processor has not been placed in standby mode by + * configuring the PWRMODE register since STS was cleared + * by a reset or by software. + * [2] = 1 nVDD_FAULT has been asserted and caused the processor to + * enter deep-sleep mode. + * [1] = 1 nBATT_FAULT has been asserted and caused the processor to + * enter deep-sleep mode. + * [0] = 1 The processor was placed in sleep mode by configuring the + * PWRMODE register. + */ + +#define CONFIG_PSSR_VAL 0x37 + + +/********************************************************************* + * CONFIG PXA270 Chipselect settings * + *********************************************************************/ + +/* + * Memory settings + * + * This is the configuration for nCS1/0 -> PLD / flash + * configuration for nCS1: + * [31] 0 - Slower Device + * [30:28] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [19] 1 - 16 Bit bus width + * [18:16] 011 - burst RAM or FLASH + * configuration for nCS0 (J3 Flash): + * [15] 0 - Slower Device + * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [03] 0 - 32 Bit bus width + * [02:00] 011 - burst RAM or FLASH + */ +#if PHYCORE_PXA270_USE_K3FLASH == 0 +#define CONFIG_MSC0_VAL 0x128C1262 +#else +/* configuration for nCS0 (K3 Flash): + * [15] 0 - Slower Device + * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [03] 0 - 32 Bit bus width + * [02:00] 011 - burst RAM or FLASH + */ +#define CONFIG_MSC0_VAL 0x128C12B3 +#endif + +/* + * This is the configuration for nCS3/2 + * configuration for nCS3: POWER + * + * [31] 0 - Slower Device + * [30:28] 111 - RRR3: CS deselect to CS time: 7*(2*MemClk) = 140 ns + * [27:24] 1111 - RDN3: Address to data valid in bursts: (15+1)*MemClk = 160 ns + * [23:20] 1111 - RDF3: Address for first access: (23+1)*MemClk = 240 ns + * [19] 0 - 32 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS2: PLD + * [15] 0 - Slower Device + * [14:12] 111 - RRR2: CS deselect to CS time: 7*(2*MemClk) = 140 ns + * [11:08] 1111 - RDN2: Address to data valid in bursts: (15+1)*MemClk = 160 ns + * [07:04] 1111 - RDF2: Address for first access: (23+1)*MemClk = 240 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CONFIG_MSC1_VAL 0x128c128c + +/* + * This is the configuration for nCS5/4 + * + * configuration for nCS5: LAN Controller + * [31] 0 - Slower Device + * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns + * [19] 0 - 32 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS4: USB + * [15] 0 - Slower Device + * [14:12] 111 - RRR4: CS deselect to CS time: 7*(2*MemClk) = 140 ns + * [11:08] 1111 - RDN4: Address to data valid in bursts: (15+1)*MemClk = 160 ns + * [07:04] 1111 - RDF4: Address for first access: (23+1)*MemClk = 240 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CONFIG_MSC2_VAL 0x1234128C + +/********************************************************************* + * CONFIG PXA270 SDRAM settings * + *********************************************************************/ + +#define CONFIG_DRAM_BASE 0xa0000000 + + +/* MDCNFG: SDRAM Configuration Register + * + * [31] 0 - Stack1 + * [30] 0 - dcacx2 + * [20] 0 - reserved + * [31:29] 000 - reserved + * [28] 1 - SA1111 compatiblity mode + * [27] 1 - latch return data with return clock + * [26] 0 - alternate addressing for pair 2/3 + * [25:24] 10 - timings + * [23] 1 - internal banks in lower partition 2/3 (not used) + * [22:21] 10 - row address bits for partition 2/3 (not used) + * [20:19] 01 - column address bits for partition 2/3 (not used) + * [18] 0 - SDRAM partition 2/3 width is 32 bit + * [17] 0 - SDRAM partition 3 disabled + * [16] 0 - SDRAM partition 2 disabled + * [15] 0 - Stack1 + * [14] 0 - dcacx0 + * [13] 0 - Stack0 + * [12] 0 - SA1110 compatiblity mode + * [11] 1 - always 1 + * [10] 0 - no alternate addressing for pair 0/1 + * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk + * [7] 1 - 4 internal banks in lower partition pair + * [06:05] 10 - 13 row address bits for partition 0/1 + * [04:03] 01 - 9 column address bits for partition 0/1 + * [02] 0 - SDRAM partition 0/1 width is 32 bit + * [01] 0 - disable SDRAM partition 1 + * [00] 1 - enable SDRAM partition 0 + */ + +/* K4S561633*/ +#define CONFIG_MDCNFG_VAL 0x0AC90AC9 + +/* MDREFR: SDRAM Refresh Control Register + * + * [31] 0 - ALTREFA + * [30] 0 - ALTREFB + * [29] 1 - K0DB4 + * [28] 0 - reserved + * [27] 0 - reserved + * [26] 0 - reserved + * [25] 1 - K2FREE: not free running + * [24] 0 - K1FREE: not free running + * [23] 1 - K0FREE: not free running + * [22] 0 - SLFRSH: self refresh disabled + * [21] 0 - reserved + * [20] 0 - APD: no auto power down + * [19] 0 - K2DB2: SDCLK2 is MemClk + * [18] 0 - K2RUN: disable SDCLK2 + * [17] 0 - K1DB2: SDCLK1 is MemClk + * [16] 1 - K1RUN: enable SDCLK1 + * [15] 1 - E1PIN: SDRAM clock enable + * [14] 1 - K0DB2: SDCLK0 is MemClk + * [13] 0 - K0RUN: disable SDCLK0 + * [12] 0 - RESERVED + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 + */ +#define CONFIG_MDREFR_VAL 0x2281C018 + +/* MDMRS: Mode Register Set Configuration Register + * + * [31] 0 - reserved + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) + * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) + * [15] 0 - reserved + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. + * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. + */ +#define CONFIG_MDMRS_VAL 0x00020022 + +/********************************************************************* + * CONFIG PXA270 Clock generation * + *********************************************************************/ +#define CONFIG_FLYCNFG_VAL 0x00010001 +#define CONFIG_SXCNFG_VAL 0x40044004 +#define CONFIG_CKEN (CKEN_MEMC | CKEN_OSTIMER) + +#if PHYCORE_PXA270_SPEED == 520 +#define CONFIG_CCCR 0x00000290 /* Memory Clock is f. Table; N=2.5, L=16 => 16x13=208, 208x2,5=520 MHz */ +#elif PHYCORE_PXA270_SPEED == 260 +#define CONFIG_CCCR 0x02000288 /* Memory Clock is System-Bus Freq., N=2.5, L=8 => 8x13=104, 104x2,5=260 MHz */ +#else +#error You have specified an illegal speed. +#endif + +/********************************************************************* + * CONFIG PXA270 CF interface * + *********************************************************************/ +#define CONFIG_MECR_VAL 0x00000003 +#define CONFIG_MCMEM0_VAL 0x00010504 +#define CONFIG_MCMEM1_VAL 0x00010504 +#define CONFIG_MCATT0_VAL 0x00010504 +#define CONFIG_MCATT1_VAL 0x00010504 +#define CONFIG_MCIO0_VAL 0x00004715 +#define CONFIG_MCIO1_VAL 0x00004715 + +#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/phytec-phycore-pxa270/env/config b/arch/arm/boards/phytec-phycore-pxa270/env/config new file mode 100644 index 0000000..d427800 --- /dev/null +++ b/arch/arm/boards/phytec-phycore-pxa270/env/config @@ -0,0 +1,45 @@ +#!/bin/sh + +eth0.serverip= +user= + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=dhcp + +# or set your networking parameters here +#eth0.ipaddr=a.b.c.d +#eth0.netmask=a.b.c.d +#eth0.gateway=a.b.c.d +#eth0.serverip=a.b.c.d + +# can be either 'nfs', 'tftp', 'nor' or 'nand' +kernel_loc=tftp +# can be either 'net', 'nor', 'nand' or 'initrd' +rootfs_loc=net + +# can be either 'jffs2' or 'ubifs' +rootfs_type=ubifs +rootfsimage=root-${global.hostname}.$rootfs_type + +kernelimage=zImage-${global.hostname} +#kernelimage=uImage-${global.hostname} +#kernelimage=Image-${global.hostname} +#kernelimage=Image-${global.hostname}.lzo + +if [ -n $user ]; then + kernelimage="$user"-"$kernelimage" + nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" + rootfsimage="$user"-"$rootfsimage" +else + nfsroot="$eth0.serverip:/path/to/nfs/root" +fi + +autoboot_timeout=3 + +bootargs="console=ttyS0,115200" + +nor_parts="512k(barebox)ro,256k(bareboxenv),4M(kernel),-(root)" +rootfs_mtdblock_nor=3 + +PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S new file mode 100644 index 0000000..c7dacce --- /dev/null +++ b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S @@ -0,0 +1,459 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO <31:00> */ +#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO <63:32> */ +#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO <80:64> */ + +#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO <31:00> */ +#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ +#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ + +#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO <31:0o> */ +#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO <63:32> */ +#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO <80:64> */ + +#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO <15:00> */ +#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO <31:16> */ +#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO <47:32> */ +#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO <63:48> */ +#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO <79:64> */ +#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO <95:80> */ + +/* + * Memory setup + */ +.globl barebox_arm_reset_vector +barebox_arm_reset_vector: + bl arm_cpu_lowlevel_init + + @ Preserve r8/r7 i.e. kernel entry values + + @ Data cache might be active. + @ Be sure to flush kernel binary out of the cache, + @ whatever state it is, before it is turned off. + @ This is done by fetching through currently executed + @ memory to be sure we hit the same cache. + bic r2, pc, #0x1f + add r3, r2, #0x10000 @ 64 kb is quite enough... +1: ldr r0, [r2], #32 + teq r2, r3 + bne 1b + mcr p15, 0, r0, c7, c10, 4 @ drain WB + mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches + + @ disabling MMU and caches + mrc p15, 0, r0, c1, c0, 0 @ read control reg + bic r0, r0, #0x05 @ clear DC, MMU + bic r0, r0, #0x1000 @ clear Icache + mcr p15, 0, r0, c1, c0, 0 + /* set output */ + ldr r0, =GPSR0 + ldr r1, =CONFIG_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CONFIG_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CONFIG_GPSR2_VAL + str r1, [r0] + + /* set direction */ + ldr r0, =GPDR0 + ldr r1, =CONFIG_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CONFIG_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CONFIG_GPDR2_VAL + str r1, [r0] + + /* alternate function */ + ldr r0, =GAFR0_L + ldr r1, =CONFIG_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CONFIG_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CONFIG_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CONFIG_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CONFIG_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CONFIG_GAFR2_U_VAL + str r1, [r0] + + /* enable GPIO pins */ + ldr r0, =PSSR + ldr r1, =CONFIG_PSSR_VAL + str r1, [r0] + + /* -------------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* -------------------------------------------------------------------- */ + + /* -------------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* -------------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + cmp pc, #0xa0000000 + bls mem_init + cmp pc, #0xb0000000 + bhi mem_init + b skip_mem_init + +mem_init: + ldr r1, =MDCNFG /* get memory controller base addr. */ + + /* -------------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* -------------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CONFIG_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CONFIG_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CONFIG_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* -------------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* -------------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CONFIG_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CONFIG_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CONFIG_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CONFIG_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CONFIG_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CONFIG_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CONFIG_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* -------------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* -------------------------------------------------------------------- */ + ldr r2, =CONFIG_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* -------------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* -------------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CONFIG_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K2FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* -------------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* -------------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* + * Write SXMRS to cause an MRS command to all enabled banks of + * synchronous static memory. Note that SXLCR need not be + * written at this time. + */ + ldr r2, =CONFIG_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* -------------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* -------------------------------------------------------------------- */ + bic r4, r4, #(MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + orr r4, r4, #MDREFR_K2FREE + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* + * Step 4d: write MDCNFG with MDCNFG:DEx deasserted + * (set to 0), to configure but not enable each SDRAM + * partition pair. + */ + ldr r4, =CONFIG_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* + * Step 4e: Wait for the clock to the SDRAMs to stabilize, + * 100..200 usec. + */ + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200 usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + ldr r3, =CONFIG_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* + * Step 4g: Write MDCNFG with enable bits asserted + * (MDCNFG:DEx set to 1) + */ + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + ldr r2, =CONFIG_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ +skip_mem_init: + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* -------------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* -------------------------------------------------------------------- */ + +initirqs: + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* -------------------------------------------------------------------- */ + /* Clock initialisation */ + /* -------------------------------------------------------------------- */ + +initclks: + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CONFIG_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CONFIG_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change */ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MDCNFG + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] + + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /* Disable software and data breakpoints */ + mov r0, #0 + mcr p15, 0, r0, c14, c8, 0 /* ibcr0 */ + mcr p15, 0, r0, c14, c9, 0 /* ibcr1 */ + mcr p15, 0, r0, c14, c4, 0 /* dbcon */ + + /* Enable all debug functionality */ + mov r0, #0x80000000 + mcr p14, 0, r0, c10, c0, 0 /* dcsr */ +#endif + + /* -------------------------------------------------------------------- */ + /* End lowlevel_init */ + /* -------------------------------------------------------------------- */ + +endlowlevel_init: + mov r0, #0xa0000000 + mov r1, #SZ_64M + mov r2, #0 + b barebox_arm_entry diff --git a/arch/arm/boards/phytec-phyflex-imx6/Makefile b/arch/arm/boards/phytec-phyflex-imx6/Makefile new file mode 100644 index 0000000..93e7308 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/Makefile @@ -0,0 +1,5 @@ +obj-y += board.o +obj-y += flash-header-phytec-pfla02-1gib.dcd.o flash-header-phytec-pfla02-2gib.dcd.o +extra-y += flash-header-phytec-pfla02-1gib.dcd.S flash-header-phytec-pfla02-2gib.dcd.S +extra-y += flash-header-phytec-pfla02-1gib.dcd flash-header-phytec-pfla02-2gib.dcd +lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c new file mode 100644 index 0000000..e9bd168 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include +#include +#include +#include + +#include + +#define ETH_PHY_RST IMX_GPIO_NR(3, 23) + +static int eth_phy_reset(void) +{ + gpio_request(ETH_PHY_RST, "phy reset"); + gpio_direction_output(ETH_PHY_RST, 0); + mdelay(1); + gpio_set_value(ETH_PHY_RST, 1); + + return 0; +} + +static int phytec_pfla02_init(void) +{ + if (!of_machine_is_compatible("phytec,imx6q-pfla02")) + return 0; + + eth_phy_reset(); + + return 0; +} +device_initcall(phytec_pfla02_init); + +static int phytec_pfla02_core_init(void) +{ + if (!of_machine_is_compatible("phytec,imx6q-pfla02")) + return 0; + + imx6_init_lowlevel(); + + return 0; +} +postcore_initcall(phytec_pfla02_core_init); diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg new file mode 100644 index 0000000..524ebca --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg @@ -0,0 +1,6 @@ + +#define SETUP_1GIB_2GIB \ + wm 32 0x021b0040 0x00000017; \ + wm 32 0x021b0000 0xc21a0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg new file mode 100644 index 0000000..bf6e0ab --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg @@ -0,0 +1,6 @@ + +#define SETUP_1GIB_2GIB \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0xC31A0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h new file mode 100644 index 0000000..b90f7cb --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h @@ -0,0 +1,99 @@ +soc imx6 +loadaddr 0x20000000 +dcdofs 0x400 + +wm 32 0x020e05a8 0x00000030 +wm 32 0x020e05b0 0x00000030 +wm 32 0x020e0524 0x00000030 +wm 32 0x020e051c 0x00000030 +wm 32 0x020e0518 0x00000030 +wm 32 0x020e050c 0x00000030 +wm 32 0x020e05b8 0x00000030 +wm 32 0x020e05c0 0x00000030 +wm 32 0x020e05ac 0x00020030 +wm 32 0x020e05b4 0x00020030 +wm 32 0x020e0528 0x00020030 +wm 32 0x020e0520 0x00020030 +wm 32 0x020e0514 0x00020030 +wm 32 0x020e0510 0x00020030 +wm 32 0x020e05bc 0x00020030 +wm 32 0x020e05c4 0x00020030 +wm 32 0x020e056c 0x00020030 +wm 32 0x020e0578 0x00020030 +wm 32 0x020e0588 0x00020030 +wm 32 0x020e0594 0x00020030 +wm 32 0x020e057c 0x00020030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00003030 +wm 32 0x020e05a0 0x00003030 +wm 32 0x020e0784 0x00000030 +wm 32 0x020e0788 0x00000030 +wm 32 0x020e0794 0x00000030 +wm 32 0x020e079c 0x00000030 +wm 32 0x020e07a0 0x00000030 +wm 32 0x020e07a4 0x00000030 +wm 32 0x020e07a8 0x00000030 +wm 32 0x020e0748 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0798 0x000c0000 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b0018 0x00081740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b000c 0x555a7975 +wm 32 0x021b0010 0xff538e64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x005b0e21 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b0004 0x00025576 + +SETUP_1GIB_2GIB + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00428031 +wm 32 0x021b001c 0x00428039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0800 0xa1380003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b0020 0x00005800 +wm 32 0x021b0818 0x00022227 +wm 32 0x021b4818 0x00022227 +wm 32 0x021b083c 0x433c033f +wm 32 0x021b0840 0x033e033d +wm 32 0x021b483c 0x43490351 +wm 32 0x021b4840 0x0344032f +wm 32 0x021b0848 0x4a434146 +wm 32 0x021b4848 0x4745434b +wm 32 0x021b0850 0x3d3d433a +wm 32 0x021b4850 0x48334b3e +wm 32 0x021b080c 0x000f0011 +wm 32 0x021b0810 0x00200022 +wm 32 0x021b480c 0x0033002e +wm 32 0x021b4810 0x003e003b +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b001c 0x00000000 +wm 32 0x021b0404 0x00011006 +wm 32 0x020e0010 0xf00000ff +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f +wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c new file mode 100644 index 0000000..6422bc4 --- /dev/null +++ b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2013 Sascha Hauer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static inline void setup_uart(void) +{ + void __iomem *ccmbase = (void *)MX6_CCM_BASE_ADDR; + void __iomem *uartbase = (void *)MX6_UART4_BASE_ADDR; + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + writel(0x4, iomuxbase + 0x01f8); + + writel(0xffffffff, ccmbase + 0x68); + writel(0xffffffff, ccmbase + 0x6c); + writel(0xffffffff, ccmbase + 0x70); + writel(0xffffffff, ccmbase + 0x74); + writel(0xffffffff, ccmbase + 0x78); + writel(0xffffffff, ccmbase + 0x7c); + writel(0xffffffff, ccmbase + 0x80); + + writel(0x00000000, uartbase + 0x80); + writel(0x00004027, uartbase + 0x84); + writel(0x00000704, uartbase + 0x88); + writel(0x00000a81, uartbase + 0x90); + writel(0x0000002b, uartbase + 0x9c); + writel(0x00013880, uartbase + 0xb0); + writel(0x0000047f, uartbase + 0xa4); + writel(0x0000c34f, uartbase + 0xa8); + writel(0x00000001, uartbase + 0x80); + + putc_ll('>'); +} + +extern char __dtb_imx6q_phytec_pbab01_start[]; + +ENTRY_FUNCTION(start_phytec_pbab01_1gib, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00920000 - 8); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} + +ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2) +{ + uint32_t fdt; + + arm_cpu_lowlevel_init(); + + arm_setup_stack(0x00920000 - 8); + + if (IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset(); + + barebox_arm_entry(0x10000000, SZ_2G, fdt); +} diff --git a/arch/arm/configs/datamodul-edm-qmx6_defconfig b/arch/arm/configs/datamodul-edm-qmx6_defconfig new file mode 100644 index 0000000..30e5a53 --- /dev/null +++ b/arch/arm/configs/datamodul-edm-qmx6_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARCH_IMX=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x31000 +CONFIG_IMX_MULTI_BOARDS=y +CONFIG_MACH_REALQ7=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x0 +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_RELOCATABLE=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/datamodul-edm-qmx6/env" +CONFIG_RESET_SOURCE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_LN=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_WD=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_RESOLV=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_DISK_AHCI=y +CONFIG_DISK_AHCI_IMX=y +CONFIG_MCI=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_MFD_STMPE=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_IMX=y +CONFIG_GPIO_STMPE=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/dmo-realq7_defconfig b/arch/arm/configs/dmo-realq7_defconfig deleted file mode 100644 index 131eddf..0000000 --- a/arch/arm/configs/dmo-realq7_defconfig +++ /dev/null @@ -1,93 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x31000 -CONFIG_IMX_MULTI_BOARDS=y -CONFIG_MACH_REALQ7=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_THUMB2_BAREBOX=y -CONFIG_CMD_ARM_MMUINFO=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_RELOCATABLE=y -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_CONSOLE_ACTIVATE_NONE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/dmo-mx6-realq7/env" -CONFIG_RESET_SOURCE=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_LN=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_WD=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_RESOLV=y -CONFIG_OFDEVICE=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_DRIVER_NET_FEC_IMX=y -CONFIG_DRIVER_SPI_IMX=y -CONFIG_I2C=y -CONFIG_I2C_IMX=y -CONFIG_MTD=y -CONFIG_MTD_M25P80=y -CONFIG_DISK_AHCI=y -CONFIG_DISK_AHCI_IMX=y -CONFIG_MCI=y -CONFIG_MCI_IMX_ESDHC=y -CONFIG_MFD_STMPE=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_IMX=y -CONFIG_GPIO_STMPE=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/freescale-mx21-ads_defconfig b/arch/arm/configs/freescale-mx21-ads_defconfig new file mode 100644 index 0000000..530f483 --- /dev/null +++ b/arch/arm/configs/freescale-mx21-ads_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX21=y +CONFIG_MACH_IMX21ADS=y +CONFIG_IMX_CLKO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_TEXT_BASE=0xc3000000 +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_LONGHELP=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx21-ads/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CRC=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_DRIVER_NET_CS8900=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_DRIVER_CFI=y +# CONFIG_DRIVER_CFI_INTEL is not set +CONFIG_CFI_BUFFER_WRITE=y diff --git a/arch/arm/configs/freescale-mx23-evk_defconfig b/arch/arm/configs/freescale-mx23-evk_defconfig new file mode 100644 index 0000000..1502d22 --- /dev/null +++ b/arch/arm/configs/freescale-mx23-evk_defconfig @@ -0,0 +1,33 @@ +CONFIG_ARCH_MXS=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_BROKEN=y +CONFIG_LONGHELP=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_RESET=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +# CONFIG_SPI is not set +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DFU=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_MXS=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/freescale-mx25-3ds_defconfig b/arch/arm/configs/freescale-mx25-3ds_defconfig new file mode 100644 index 0000000..57d3465 --- /dev/null +++ b/arch/arm/configs/freescale-mx25-3ds_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX25=y +CONFIG_MACH_FREESCALE_MX25_3STACK=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x87F00000 +CONFIG_MALLOC_SIZE=0x01000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_ERRNO_MESSAGES is not set +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx25-3ds/env/" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_DRIVER_NET_FEC_IMX=y +# CONFIG_SPI is not set +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale-mx27-ads_defconfig b/arch/arm/configs/freescale-mx27-ads_defconfig new file mode 100644 index 0000000..d374582 --- /dev/null +++ b/arch/arm/configs/freescale-mx27-ads_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX27=y +CONFIG_MACH_IMX27ADS=y +CONFIG_IMX_CLKO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_TEXT_BASE=0xa7f00000 +CONFIG_LONGHELP=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx27-ads/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CRC=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_MTD=y +CONFIG_DRIVER_CFI=y +# CONFIG_DRIVER_CFI_INTEL is not set +CONFIG_CFI_BUFFER_WRITE=y diff --git a/arch/arm/configs/freescale-mx28-evk_defconfig b/arch/arm/configs/freescale-mx28-evk_defconfig new file mode 100644 index 0000000..d06bac8 --- /dev/null +++ b/arch/arm/configs/freescale-mx28-evk_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARCH_MXS=y +CONFIG_ARCH_IMX28=y +CONFIG_MACH_MX28EVK=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x43000000 +CONFIG_MALLOC_SIZE=0x800000 +CONFIG_BROKEN=y +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx28-evk/env" +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_SERIAL_AUART=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_DRIVER_SPI_MXS=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_STM=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_MXS=y +CONFIG_MXS_APBH_DMA=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/freescale-mx35-3ds_defconfig b/arch/arm/configs/freescale-mx35-3ds_defconfig new file mode 100644 index 0000000..e3f3262 --- /dev/null +++ b/arch/arm/configs/freescale-mx35-3ds_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX35=y +CONFIG_MACH_FREESCALE_MX35_3STACK=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_TEXT_BASE=0x87F00000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx35-3ds/env/" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_DRIVER_NET_SMC911X=y +CONFIG_DRIVER_NET_FEC_IMX=y +# CONFIG_SPI is not set +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_IMX=y +CONFIG_UBI=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_IMX_IPU=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale-mx51-babbage_defconfig b/arch/arm/configs/freescale-mx51-babbage_defconfig new file mode 100644 index 0000000..3d1ad31 --- /dev/null +++ b/arch/arm/configs/freescale-mx51-babbage_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARCH_IMX=y +CONFIG_IMX_MULTI_BOARDS=y +CONFIG_MACH_FREESCALE_MX51_PDK=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx51-babbage/env/" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_SPI=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_RESOLV=y +CONFIG_OFDEVICE=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_DRIVER_SPI_IMX=y +CONFIG_MTD=y +CONFIG_MTD_DATAFLASH=y +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_MFD_MC13XXX=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale-mx53-qsb_defconfig b/arch/arm/configs/freescale-mx53-qsb_defconfig new file mode 100644 index 0000000..afe8b72 --- /dev/null +++ b/arch/arm/configs/freescale-mx53-qsb_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARCH_IMX=y +CONFIG_IMX_MULTI_BOARDS=y +CONFIG_MACH_FREESCALE_MX53_LOCO=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx53-qsb/env/" +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_LN=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_WD=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_SMSC_PHY=y +CONFIG_DRIVER_NET_FEC_IMX=y +# CONFIG_SPI is not set +CONFIG_I2C=y +CONFIG_I2C_IMX=y +CONFIG_DISK_ATA=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_STORAGE=y +CONFIG_MCI=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_MFD_MC13XXX=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_IMX=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale-mx53-smd_defconfig b/arch/arm/configs/freescale-mx53-smd_defconfig new file mode 100644 index 0000000..f18c436 --- /dev/null +++ b/arch/arm/configs/freescale-mx53-smd_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX53=y +CONFIG_MACH_FREESCALE_MX53_SMD=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x7ff00000 +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx53-smd/env/" +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_NET_NETCONSOLE=y +CONFIG_DRIVER_NET_FEC_IMX=y +# CONFIG_SPI is not set +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_IMX_ESDHC=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale_mx25_3stack_defconfig b/arch/arm/configs/freescale_mx25_3stack_defconfig deleted file mode 100644 index 888736a..0000000 --- a/arch/arm/configs/freescale_mx25_3stack_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX25=y -CONFIG_MACH_FREESCALE_MX25_3STACK=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x87F00000 -CONFIG_MALLOC_SIZE=0x01000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -# CONFIG_ERRNO_MESSAGES is not set -CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx25-3-stack/env/" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_DRIVER_NET_FEC_IMX=y -# CONFIG_SPI is not set -CONFIG_USB=y -CONFIG_USB_EHCI=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale_mx35_3stack_defconfig b/arch/arm/configs/freescale_mx35_3stack_defconfig deleted file mode 100644 index 2f45764..0000000 --- a/arch/arm/configs/freescale_mx35_3stack_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX35=y -CONFIG_MACH_FREESCALE_MX35_3STACK=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_TEXT_BASE=0x87F00000 -CONFIG_MALLOC_SIZE=0x1000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx35-3-stack/env/" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_I2C=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_DRIVER_NET_SMC911X=y -CONFIG_DRIVER_NET_FEC_IMX=y -# CONFIG_SPI is not set -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_IMX=y -CONFIG_UBI=y -CONFIG_VIDEO=y -CONFIG_DRIVER_VIDEO_IMX_IPU=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale_mx51_babbage_defconfig b/arch/arm/configs/freescale_mx51_babbage_defconfig deleted file mode 100644 index b45b897..0000000 --- a/arch/arm/configs/freescale_mx51_babbage_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_IMX_MULTI_BOARDS=y -CONFIG_MACH_FREESCALE_MX51_PDK=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_THUMB2_BAREBOX=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_CONSOLE_ACTIVATE_NONE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx51-pdk/env/" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_MM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_SPI=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_CLK=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_RESOLV=y -CONFIG_OFDEVICE=y -CONFIG_DRIVER_NET_FEC_IMX=y -CONFIG_DRIVER_SPI_IMX=y -CONFIG_MTD=y -CONFIG_MTD_DATAFLASH=y -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_IMX_ESDHC=y -CONFIG_MFD_MC13XXX=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale_mx53_loco_defconfig b/arch/arm/configs/freescale_mx53_loco_defconfig deleted file mode 100644 index 8863944..0000000 --- a/arch/arm/configs/freescale_mx53_loco_defconfig +++ /dev/null @@ -1,90 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_IMX_MULTI_BOARDS=y -CONFIG_MACH_FREESCALE_MX53_LOCO=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_THUMB2_BAREBOX=y -CONFIG_CMD_ARM_MMUINFO=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_CONSOLE_ACTIVATE_NONE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx53-loco/env/" -CONFIG_RESET_SOURCE=y -CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_LN=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_CMD_WD=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_NETCONSOLE=y -CONFIG_OFDEVICE=y -CONFIG_SMSC_PHY=y -CONFIG_DRIVER_NET_FEC_IMX=y -# CONFIG_SPI is not set -CONFIG_I2C=y -CONFIG_I2C_IMX=y -CONFIG_DISK_ATA=y -CONFIG_USB=y -CONFIG_USB_EHCI=y -CONFIG_USB_STORAGE=y -CONFIG_MCI=y -CONFIG_MCI_IMX_ESDHC=y -CONFIG_MFD_MC13XXX=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_IMX=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/freescale_mx53_smd_defconfig b/arch/arm/configs/freescale_mx53_smd_defconfig deleted file mode 100644 index f18c436..0000000 --- a/arch/arm/configs/freescale_mx53_smd_defconfig +++ /dev/null @@ -1,66 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX53=y -CONFIG_MACH_FREESCALE_MX53_SMD=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x7ff00000 -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx53-smd/env/" -CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_NET_NETCONSOLE=y -CONFIG_DRIVER_NET_FEC_IMX=y -# CONFIG_SPI is not set -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_IMX_ESDHC=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/imx23evk_defconfig b/arch/arm/configs/imx23evk_defconfig deleted file mode 100644 index 1502d22..0000000 --- a/arch/arm/configs/imx23evk_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -CONFIG_ARCH_MXS=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_BROKEN=y -CONFIG_LONGHELP=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_RESET_SOURCE=y -CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_RESET=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -# CONFIG_SPI is not set -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DFU=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_MXS=y -CONFIG_FS_EXT4=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/imx28evk_defconfig b/arch/arm/configs/imx28evk_defconfig deleted file mode 100644 index d06bac8..0000000 --- a/arch/arm/configs/imx28evk_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_ARCH_MXS=y -CONFIG_ARCH_IMX28=y -CONFIG_MACH_MX28EVK=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x43000000 -CONFIG_MALLOC_SIZE=0x800000 -CONFIG_BROKEN=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx28-evk/env" -CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_GPIO=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_RESOLV=y -CONFIG_DRIVER_SERIAL_AUART=y -CONFIG_DRIVER_NET_FEC_IMX=y -CONFIG_DRIVER_SPI_MXS=y -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_MXS=y -CONFIG_VIDEO=y -CONFIG_DRIVER_VIDEO_STM=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_MXS=y -CONFIG_MXS_APBH_DMA=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/mx21ads_defconfig b/arch/arm/configs/mx21ads_defconfig deleted file mode 100644 index 13c005b..0000000 --- a/arch/arm/configs/mx21ads_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX21=y -CONFIG_MACH_IMX21ADS=y -CONFIG_IMX_CLKO=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_TEXT_BASE=0xc3000000 -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_LONGHELP=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/imx21ads/env" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_CRC=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_GPIO=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_DRIVER_NET_CS8900=y -# CONFIG_SPI is not set -CONFIG_MTD=y -CONFIG_DRIVER_CFI=y -# CONFIG_DRIVER_CFI_INTEL is not set -CONFIG_CFI_BUFFER_WRITE=y diff --git a/arch/arm/configs/mx27ads_defconfig b/arch/arm/configs/mx27ads_defconfig deleted file mode 100644 index b3fdf84..0000000 --- a/arch/arm/configs/mx27ads_defconfig +++ /dev/null @@ -1,39 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX27=y -CONFIG_MACH_IMX27ADS=y -CONFIG_IMX_CLKO=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_TEXT_BASE=0xa7f00000 -CONFIG_LONGHELP=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/imx27ads/env" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_CRC=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_GPIO=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_DRIVER_SPI_IMX=y -CONFIG_MTD=y -CONFIG_DRIVER_CFI=y -# CONFIG_DRIVER_CFI_INTEL is not set -CONFIG_CFI_BUFFER_WRITE=y diff --git a/arch/arm/configs/pca100_defconfig b/arch/arm/configs/pca100_defconfig deleted file mode 100644 index 6e3a3ad..0000000 --- a/arch/arm/configs/pca100_defconfig +++ /dev/null @@ -1,91 +0,0 @@ -CONFIG_BUILTIN_DTB=y -CONFIG_BUILTIN_DTB_NAME="imx27-phytec-phycard-s-rdk" -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y -CONFIG_MACH_PCA100=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_PBL_IMAGE=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x01000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_BLSPEC=y -CONFIG_CONSOLE_ACTIVATE_NONE=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="" -CONFIG_RESET_SOURCE=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_CLK=y -CONFIG_CMD_DETECT=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_NETCONSOLE=y -CONFIG_OFDEVICE=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_DRIVER_NET_FEC_IMX=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -# CONFIG_SPI is not set -CONFIG_MTD=y -CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -CONFIG_NAND_IMX=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_USB=y -CONFIG_USB_EHCI=y -CONFIG_USB_ULPI=y -CONFIG_MCI=y -CONFIG_MCI_IMX=y -CONFIG_IMX_WEIM=y -CONFIG_FS_EXT4=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_FS_UBIFS=y -CONFIG_FS_UBIFS_COMPRESSION_LZO=y diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig deleted file mode 100644 index f911951..0000000 --- a/arch/arm/configs/pcm027_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_ARCH_PXA=y -CONFIG_MACH_PCM027=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x1000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm027/env" -CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_AUTOMOUNT=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTZ is not set -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_DRIVER_SERIAL_PXA=y -CONFIG_DRIVER_NET_SMC91111=y -# CONFIG_SPI is not set -CONFIG_MTD=y -CONFIG_DRIVER_CFI=y -CONFIG_VIDEO=y -CONFIG_DRIVER_VIDEO_PXA=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig deleted file mode 100644 index 1a75701..0000000 --- a/arch/arm/configs/pcm037_defconfig +++ /dev/null @@ -1,88 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_CACHE_L2X0=y -CONFIG_ARCH_IMX31=y -CONFIG_MACH_PCM037=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_MALLOC_SIZE=0x01000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_PARTITION=y -CONFIG_PARTITION_DISK=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm037/env" -CONFIG_RESET_SOURCE=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_DIRNAME=y -CONFIG_CMD_LN=y -CONFIG_CMD_READLINK=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_SPI=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_CLK=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_NETCONSOLE=y -CONFIG_NET_RESOLV=y -CONFIG_DRIVER_NET_SMC911X=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_IMX=y -CONFIG_UBI=y -CONFIG_USB=y -CONFIG_USB_EHCI=y -CONFIG_FS_EXT4=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig deleted file mode 100644 index e2f5388..0000000 --- a/arch/arm/configs/pcm038_defconfig +++ /dev/null @@ -1,77 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y -CONFIG_ARCH_IMX27=y -CONFIG_MACH_PCM038=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0xa7f00000 -CONFIG_MALLOC_SIZE=0x1000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm038/env" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_NETCONSOLE=y -CONFIG_NET_RESOLV=y -CONFIG_DRIVER_NET_FEC_IMX=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_MTD=y -CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -CONFIG_NAND_IMX=y -CONFIG_USB=y -CONFIG_USB_IMX_CHIPIDEA=y -CONFIG_USB_EHCI=y -CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO=y -CONFIG_DRIVER_VIDEO_IMX=y -CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm043_defconfig b/arch/arm/configs/pcm043_defconfig deleted file mode 100644 index 5447777..0000000 --- a/arch/arm/configs/pcm043_defconfig +++ /dev/null @@ -1,89 +0,0 @@ -CONFIG_ARCH_IMX=y -CONFIG_CACHE_L2X0=y -CONFIG_ARCH_IMX_EXTERNAL_BOOT=y -CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y -CONFIG_ARCH_IMX35=y -CONFIG_MACH_PCM043=y -CONFIG_IMX_IIM=y -CONFIG_IMX_IIM_FUSE_BLOW=y -CONFIG_AEABI=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x87E00000 -CONFIG_MALLOC_SIZE=0x1000000 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_PARTITION=y -CONFIG_PARTITION_DISK=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm043/env" -CONFIG_RESET_SOURCE=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_MSLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_LET=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_DIRNAME=y -CONFIG_CMD_LN=y -CONFIG_CMD_READLINK=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_FILETYPE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_OFTREE_PROBE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_CLK=y -CONFIG_CMD_WD=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y -CONFIG_NET_PING=y -CONFIG_NET_NETCONSOLE=y -CONFIG_DRIVER_NET_FEC_IMX=y -# CONFIG_SPI is not set -CONFIG_DRIVER_CFI=y -CONFIG_CFI_BUFFER_WRITE=y -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_IMX=y -CONFIG_UBI=y -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_IMX=y -CONFIG_FS_TFTP=y -CONFIG_ZLIB=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm049_defconfig b/arch/arm/configs/pcm049_defconfig deleted file mode 100644 index 35b4052..0000000 --- a/arch/arm/configs/pcm049_defconfig +++ /dev/null @@ -1,77 +0,0 @@ -CONFIG_ARCH_OMAP=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x80000 -CONFIG_ARCH_OMAP4=y -CONFIG_MACH_PCM049=y -CONFIG_AEABI=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x8f000000 -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_KALLSYMS=y -CONFIG_PROMPT="barebox> " -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -# CONFIG_TIMESTAMP is not set -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm049/env" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TIME=y -CONFIG_CMD_AUTOMOUNT=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_BOOTM_VERBOSE=y -CONFIG_CMD_BOOTM_INITRD=y -CONFIG_CMD_BOOTM_OFTREE=y -CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y -CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_SPLASH=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y -CONFIG_NET_PING=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y -CONFIG_SMSC_PHY=y -CONFIG_DRIVER_NET_SMC911X=y -# CONFIG_SPI is not set -CONFIG_I2C=y -CONFIG_I2C_OMAP=y -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_OMAP_GPMC=y -CONFIG_UBI=y -CONFIG_USB=y -CONFIG_VIDEO=y -CONFIG_DRIVER_VIDEO_OMAP=y -CONFIG_IMAGE_RENDERER=y -CONFIG_BMP=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_OMAP_HSMMC=y -CONFIG_MFD_TWL6030=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/pcm049_xload_defconfig b/arch/arm/configs/pcm049_xload_defconfig deleted file mode 100644 index 6bbc2e4..0000000 --- a/arch/arm/configs/pcm049_xload_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_ARCH_OMAP=y -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000 -CONFIG_ARCH_OMAP4=y -CONFIG_OMAP_BUILD_IFT=y -CONFIG_MACH_PCM049=y -CONFIG_THUMB2_BAREBOX=y -# CONFIG_CMD_ARM_CPUINFO is not set -# CONFIG_ARM_EXCEPTIONS is not set -# CONFIG_MEMINFO is not set -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x40300000 -CONFIG_MEMORY_LAYOUT_FIXED=y -CONFIG_STACK_BASE=0x8f000000 -CONFIG_MALLOC_BASE=0x84000000 -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_MALLOC_DUMMY=y -CONFIG_PROMPT="barebox> " -CONFIG_SHELL_NONE=y -# CONFIG_ERRNO_MESSAGES is not set -# CONFIG_TIMESTAMP is not set -CONFIG_CONSOLE_SIMPLE=y -# CONFIG_DEFAULT_ENVIRONMENT is not set -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y -# CONFIG_SPI is not set -CONFIG_MTD=y -# CONFIG_MTD_WRITE is not set -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set -# CONFIG_NAND_INFO is not set -# CONFIG_NAND_BBT is not set -CONFIG_NAND_OMAP_GPMC=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -# CONFIG_MCI_WRITE is not set -CONFIG_MCI_OMAP_HSMMC=y -# CONFIG_FS_RAMFS is not set -# CONFIG_FS_DEVFS is not set -CONFIG_FS_FAT=y diff --git a/arch/arm/configs/pcm051_defconfig b/arch/arm/configs/pcm051_defconfig deleted file mode 100644 index d7e510b..0000000 --- a/arch/arm/configs/pcm051_defconfig +++ /dev/null @@ -1,97 +0,0 @@ -CONFIG_ARCH_OMAP=y -CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y -CONFIG_OMAP_MULTI_BOARDS=y -CONFIG_MACH_PCM051=y -CONFIG_THUMB2_BAREBOX=y -CONFIG_ARM_BOARD_APPEND_ATAG=y -CONFIG_CMD_ARM_MMUINFO=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x0 -CONFIG_MALLOC_SIZE=0x0 -CONFIG_MALLOC_TLSF=y -CONFIG_KALLSYMS=y -CONFIG_RELOCATABLE=y -CONFIG_PROMPT="barebox@pcm051>" -CONFIG_LONGHELP=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -# CONFIG_TIMESTAMP is not set -CONFIG_BLSPEC=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm051/env" -CONFIG_DEBUG_INFO=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TFTP=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_UBIFORMAT=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_UIMAGE=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_BOOTU is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_BAREBOX_UPDATE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_SPI=y -CONFIG_CMD_LED=y -CONFIG_CMD_LED_TRIGGER=y -CONFIG_CMD_MIITOOL=y -CONFIG_CMD_DETECT=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y -CONFIG_NET_PING=y -CONFIG_OFDEVICE=y -CONFIG_OF_BAREBOX_DRIVERS=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y -CONFIG_DRIVER_NET_CPSW=y -CONFIG_DRIVER_SPI_OMAP3=y -CONFIG_I2C=y -CONFIG_I2C_OMAP=y -CONFIG_MTD=y -CONFIG_MTD_M25P80=y -CONFIG_NAND=y -CONFIG_NAND_OMAP_GPMC=y -CONFIG_MTD_UBI=y -CONFIG_USB=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -CONFIG_MCI_OMAP_HSMMC=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_LED_GPIO_OF=y -CONFIG_LED_TRIGGERS=y -CONFIG_EEPROM_AT24=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_SINGLE=y -CONFIG_BUS_OMAP_GPMC=y -CONFIG_FS_TFTP=y -CONFIG_FS_NFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/phycard_a_l1_defconfig b/arch/arm/configs/phycard_a_l1_defconfig deleted file mode 100644 index cdf292c..0000000 --- a/arch/arm/configs/phycard_a_l1_defconfig +++ /dev/null @@ -1,178 +0,0 @@ -CONFIG_GENERIC_LINKER_SCRIPT=y -CONFIG_ARM=y -CONFIG_ARM_LINUX=y -CONFIG_ARCH_OMAP=y -CONFIG_CPU_32=y -CONFIG_CPU_V7=y -CONFIG_CPU_32v7=y -CONFIG_ARCH_OMAP3=y -CONFIG_OMAP_CLOCK_SOURCE_S32K=y -CONFIG_OMAP3_CLOCK_CONFIG=y -CONFIG_OMAP3_COPY_CLOCK_SRAM=n -CONFIG_OMAP_GPMC=y -CONFIG_MACH_PCAAL1=y -CONFIG_AEABI=y -CONFIG_CMD_ARM_CPUINFO=y -CONFIG_ARM_EXCEPTIONS=y -CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" -CONFIG_GREGORIAN_CALENDER=y -CONFIG_HAS_KALLSYMS=y -CONFIG_HAS_MODULES=y -CONFIG_CMD_MEMORY=y -CONFIG_ENV_HANDLING=y -CONFIG_GENERIC_GPIO=y -CONFIG_BLOCK=y -CONFIG_BLOCK_WRITE=y -CONFIG_LOCALVERSION="" -CONFIG_LOCALVERSION_AUTO=y -CONFIG_ENVIRONMENT_VARIABLES=y -CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y -CONFIG_TEXT_BASE=0x85000000 -CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y -CONFIG_MEMORY_LAYOUT_DEFAULT=y -CONFIG_STACK_SIZE=0x8000 -CONFIG_MALLOC_SIZE=0x1000000 -CONFIG_EXPERIMENTAL=y -CONFIG_MALLOC_DLMALLOC=y -CONFIG_ARCH_HAS_LOWLEVEL_INIT=y -CONFIG_PROMPT="phyCARD-A-L1 >" -CONFIG_BAUDRATE=115200 -CONFIG_LONGHELP=y -CONFIG_CBSIZE=1024 -CONFIG_MAXARGS=16 -CONFIG_SHELL_HUSH=y -CONFIG_GLOB=y -CONFIG_PROMPT_HUSH_PS2="> " -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_HUSH_GETOPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_MENU=y -CONFIG_PASSWORD=y -CONFIG_PASSWD_SUM_MD5=y -CONFIG_DYNAMIC_CRC_TABLE=y -CONFIG_ERRNO_MESSAGES=y -CONFIG_TIMESTAMP=y -CONFIG_CONSOLE_FULL=y -CONFIG_CONSOLE_ACTIVATE_FIRST=y -CONFIG_PARTITION=y -CONFIG_PARTITION_DISK=y -CONFIG_PARTITION_DISK_DOS=y -CONFIG_DEFAULT_ENVIRONMENT=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phycard-a-l1/env" -CONFIG_COMMAND_SUPPORT=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_TRUE=y -CONFIG_CMD_FALSE=y -CONFIG_CMD_MENU=y -CONFIG_CMD_MENU_MANAGEMENT=y -CONFIG_CMD_LOGIN=y -CONFIG_CMD_PASSWD=y -CONFIG_PASSWD_MODE_STAR=y -CONFIG_CMD_TIME=y -CONFIG_CMD_LS=y -CONFIG_CMD_RM=y -CONFIG_CMD_CAT=y -CONFIG_CMD_MKDIR=y -CONFIG_CMD_RMDIR=y -CONFIG_CMD_CP=y -CONFIG_CMD_PWD=y -CONFIG_CMD_CD=y -CONFIG_CMD_MOUNT=y -CONFIG_CMD_UMOUNT=y -CONFIG_CMD_NAND=y -CONFIG_CMD_CLEAR=y -CONFIG_CMD_ECHO=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_CRC=y -CONFIG_CMD_CRC_CMP=y -CONFIG_CMD_DIGEST=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_SHA256SUM=y -CONFIG_CMD_SHA224SUM=y -CONFIG_CMD_MTEST=y -CONFIG_CMD_MTEST_ALTERNATIVE=y -CONFIG_CMD_FLASH=y -CONFIG_CMD_UBI=y -CONFIG_CMD_BOOTM=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_IMINFO=y -CONFIG_CMD_BOOTZ=n -CONFIG_CMD_BOOTU=n -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_TEST=y -CONFIG_CMD_VERSION=y -CONFIG_CMD_HELP=y -CONFIG_CMD_MAGICVAR=y -CONFIG_CMD_MAGICVAR_HELP=y -CONFIG_CMD_DEVINFO=y -CONFIG_CMD_UNCOMPRESS=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_NET_NETCONSOLE=y -CONFIG_NET_RESOLV=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y -CONFIG_PHYLIB=y -CONFIG_DRIVER_NET_SMC911X=y -CONFIG_DRIVER_NET_SMC911X_ADDRESS_SHIFT=0 -CONFIG_SPI=n -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_WRITE=y -CONFIG_NAND_ECC_SOFT=y -CONFIG_NAND_ECC_HW=y -CONFIG_NAND_ECC_HW_SYNDROME=y -CONFIG_NAND_ECC_HW_NONE=y -CONFIG_NAND_INFO=y -CONFIG_NAND_READ_OOB=y -CONFIG_NAND_BBT=y -CONFIG_NAND_OOB_DEVICE=y -CONFIG_NAND_OMAP_GPMC=y -CONFIG_MTD_NAND_IDS=y -CONFIG_UBI=y -CONFIG_DISK=y -CONFIG_DISK_WRITE=y -CONFIG_DISK_ATA=y -CONFIG_DISK_INTF_PLATFORM_IDE=y -CONFIG_MCI=y -CONFIG_MCI_INFO=y -CONFIG_MCI_WRITE=y -CONFIG_MCI_OMAP_HSMMC=y -CONFIG_FS_CRAMFS=y -CONFIG_FS_RAMFS=y -CONFIG_FS_DEVFS=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y -CONFIG_PARTITION_NEED_MTD=y -CONFIG_ZLIB=y -CONFIG_BZLIB=y -CONFIG_PROCESS_ESCAPE_SEQUENCE=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_FDT=y -CONFIG_OFTREE=y -CONFIG_CRC32=y -CONFIG_CRC16=y -CONFIG_DIGEST=y -CONFIG_MD5=y -CONFIG_SHA1=y -CONFIG_SHA224=y -CONFIG_SHA256=y diff --git a/arch/arm/configs/phycard_a_l1_xload_defconfig b/arch/arm/configs/phycard_a_l1_xload_defconfig deleted file mode 100644 index 5901ed1..0000000 --- a/arch/arm/configs/phycard_a_l1_xload_defconfig +++ /dev/null @@ -1,43 +0,0 @@ -CONFIG_ARCH_OMAP=y -CONFIG_OMAP_BUILD_IFT=y -CONFIG_MACH_PCAAL1=y -CONFIG_AEABI=y -CONFIG_THUMB2_BAREBOX=y -# CONFIG_CMD_ARM_CPUINFO is not set -# CONFIG_ARM_EXCEPTIONS is not set -CONFIG_ENVIRONMENT_VARIABLES=y -CONFIG_TEXT_BASE=0x40200000 -CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x0000f000 -CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x0000f000 -CONFIG_MEMORY_LAYOUT_FIXED=y -CONFIG_STACK_BASE=0x4020F000 -CONFIG_STACK_SIZE=0xc00 -CONFIG_MALLOC_BASE=0x84000000 -CONFIG_MALLOC_SIZE=0x1000000 -CONFIG_MALLOC_DUMMY=y -CONFIG_PROMPT="X-load pca-a-l1>" -CONFIG_CBSIZE=128 -CONFIG_SHELL_NONE=y -# CONFIG_ERRNO_MESSAGES is not set -# CONFIG_TIMESTAMP is not set -CONFIG_CONSOLE_SIMPLE=y -# CONFIG_DEFAULT_ENVIRONMENT is not set -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y -# CONFIG_SPI is not set -CONFIG_MTD=y -# CONFIG_MTD_WRITE is not set -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set -# CONFIG_NAND_BBT is not set -CONFIG_NAND_OMAP_GPMC=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -# CONFIG_MCI_WRITE is not set -CONFIG_MCI_OMAP_HSMMC=y -# CONFIG_FS_RAMFS is not set -# CONFIG_FS_DEVFS is not set -CONFIG_FS_FAT=y diff --git a/arch/arm/configs/phycard_a_xl2_defconfig b/arch/arm/configs/phycard_a_xl2_defconfig deleted file mode 100644 index f091b82..0000000 --- a/arch/arm/configs/phycard_a_xl2_defconfig +++ /dev/null @@ -1,56 +0,0 @@ -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP4=y -CONFIG_MACH_PCAAXL2=y -CONFIG_AEABI=y -CONFIG_ARM_UNWIND=y -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x8f000000 -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_KALLSYMS=y -CONFIG_PROMPT="barebox> " -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_HUSH_GETOPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -# CONFIG_TIMESTAMP is not set -CONFIG_PARTITION=y -CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y -CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phycard-a-xl2/env/" -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_SAVEENV=y -CONFIG_CMD_LOADENV=y -CONFIG_CMD_EXPORT=y -CONFIG_CMD_PRINTENV=y -CONFIG_CMD_READLINE=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_FLASH=y -# CONFIG_CMD_BOOTM is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_UNLZO=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_NFS=y -CONFIG_NET_PING=y -CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y -CONFIG_DRIVER_NET_KS8851_MLL=y -# CONFIG_SPI is not set -CONFIG_MTD=y -CONFIG_NAND=y -CONFIG_NAND_OMAP_GPMC=y -CONFIG_UBI=y -CONFIG_MCI=y -CONFIG_MCI_OMAP_HSMMC=y -CONFIG_FS_FAT=y -CONFIG_FS_FAT_WRITE=y -CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/phycard_a_xl2_xload_defconfig b/arch/arm/configs/phycard_a_xl2_xload_defconfig deleted file mode 100644 index 84160e3..0000000 --- a/arch/arm/configs/phycard_a_xl2_xload_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARCH_OMAP=y -CONFIG_ARCH_OMAP4=y -CONFIG_OMAP_BUILD_IFT=y -CONFIG_MACH_PCAAXL2=y -CONFIG_AEABI=y -CONFIG_THUMB2_BAREBOX=y -# CONFIG_CMD_ARM_CPUINFO is not set -# CONFIG_ARM_EXCEPTIONS is not set -CONFIG_MMU=y -CONFIG_TEXT_BASE=0x40300000 -CONFIG_MEMORY_LAYOUT_FIXED=y -CONFIG_STACK_BASE=0x8f000000 -CONFIG_MALLOC_BASE=0x84000000 -CONFIG_MALLOC_SIZE=0x2000000 -CONFIG_MALLOC_DUMMY=y -CONFIG_PROMPT="barebox> " -CONFIG_SHELL_NONE=y -# CONFIG_ERRNO_MESSAGES is not set -# CONFIG_TIMESTAMP is not set -CONFIG_CONSOLE_SIMPLE=y -# CONFIG_DEFAULT_ENVIRONMENT is not set -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y -# CONFIG_SPI is not set -CONFIG_MTD=y -# CONFIG_MTD_WRITE is not set -# CONFIG_MTD_OOB_DEVICE is not set -CONFIG_NAND=y -# CONFIG_NAND_ECC_SOFT is not set -# CONFIG_NAND_ECC_HW_SYNDROME is not set -# CONFIG_NAND_ECC_HW_NONE is not set -# CONFIG_NAND_INFO is not set -# CONFIG_NAND_BBT is not set -CONFIG_NAND_OMAP_GPMC=y -CONFIG_MCI=y -CONFIG_MCI_STARTUP=y -# CONFIG_MCI_WRITE is not set -CONFIG_MCI_OMAP_HSMMC=y -# CONFIG_FS_RAMFS is not set -# CONFIG_FS_DEVFS is not set -CONFIG_FS_FAT=y diff --git a/arch/arm/configs/phytec-phycard-imx27_defconfig b/arch/arm/configs/phytec-phycard-imx27_defconfig new file mode 100644 index 0000000..6e3a3ad --- /dev/null +++ b/arch/arm/configs/phytec-phycard-imx27_defconfig @@ -0,0 +1,91 @@ +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="imx27-phytec-phycard-s-rdk" +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y +CONFIG_MACH_PCA100=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_PBL_IMAGE=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x01000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="" +CONFIG_RESET_SOURCE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +CONFIG_NAND_IMX=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_ULPI=y +CONFIG_MCI=y +CONFIG_MCI_IMX=y +CONFIG_IMX_WEIM=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_UBIFS=y +CONFIG_FS_UBIFS_COMPRESSION_LZO=y diff --git a/arch/arm/configs/phytec-phycard-omap3-xload_defconfig b/arch/arm/configs/phytec-phycard-omap3-xload_defconfig new file mode 100644 index 0000000..5901ed1 --- /dev/null +++ b/arch/arm/configs/phytec-phycard-omap3-xload_defconfig @@ -0,0 +1,43 @@ +CONFIG_ARCH_OMAP=y +CONFIG_OMAP_BUILD_IFT=y +CONFIG_MACH_PCAAL1=y +CONFIG_AEABI=y +CONFIG_THUMB2_BAREBOX=y +# CONFIG_CMD_ARM_CPUINFO is not set +# CONFIG_ARM_EXCEPTIONS is not set +CONFIG_ENVIRONMENT_VARIABLES=y +CONFIG_TEXT_BASE=0x40200000 +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x0000f000 +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0x0000f000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x4020F000 +CONFIG_STACK_SIZE=0xc00 +CONFIG_MALLOC_BASE=0x84000000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_MALLOC_DUMMY=y +CONFIG_PROMPT="X-load pca-a-l1>" +CONFIG_CBSIZE=128 +CONFIG_SHELL_NONE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_SIMPLE=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +# CONFIG_NAND_BBT is not set +CONFIG_NAND_OMAP_GPMC=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +# CONFIG_MCI_WRITE is not set +CONFIG_MCI_OMAP_HSMMC=y +# CONFIG_FS_RAMFS is not set +# CONFIG_FS_DEVFS is not set +CONFIG_FS_FAT=y diff --git a/arch/arm/configs/phytec-phycard-omap3_defconfig b/arch/arm/configs/phytec-phycard-omap3_defconfig new file mode 100644 index 0000000..b901658 --- /dev/null +++ b/arch/arm/configs/phytec-phycard-omap3_defconfig @@ -0,0 +1,178 @@ +CONFIG_GENERIC_LINKER_SCRIPT=y +CONFIG_ARM=y +CONFIG_ARM_LINUX=y +CONFIG_ARCH_OMAP=y +CONFIG_CPU_32=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_ARCH_OMAP3=y +CONFIG_OMAP_CLOCK_SOURCE_S32K=y +CONFIG_OMAP3_CLOCK_CONFIG=y +CONFIG_OMAP3_COPY_CLOCK_SRAM=n +CONFIG_OMAP_GPMC=y +CONFIG_MACH_PCAAL1=y +CONFIG_AEABI=y +CONFIG_CMD_ARM_CPUINFO=y +CONFIG_ARM_EXCEPTIONS=y +CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" +CONFIG_GREGORIAN_CALENDER=y +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +CONFIG_CMD_MEMORY=y +CONFIG_ENV_HANDLING=y +CONFIG_GENERIC_GPIO=y +CONFIG_BLOCK=y +CONFIG_BLOCK_WRITE=y +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_ENVIRONMENT_VARIABLES=y +CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y +CONFIG_TEXT_BASE=0x85000000 +CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y +CONFIG_MEMORY_LAYOUT_DEFAULT=y +CONFIG_STACK_SIZE=0x8000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_DLMALLOC=y +CONFIG_ARCH_HAS_LOWLEVEL_INIT=y +CONFIG_PROMPT="phyCARD-A-L1 >" +CONFIG_BAUDRATE=115200 +CONFIG_LONGHELP=y +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +CONFIG_SHELL_HUSH=y +CONFIG_GLOB=y +CONFIG_PROMPT_HUSH_PS2="> " +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_HUSH_GETOPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PASSWORD=y +CONFIG_PASSWD_SUM_MD5=y +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_ERRNO_MESSAGES=y +CONFIG_TIMESTAMP=y +CONFIG_CONSOLE_FULL=y +CONFIG_CONSOLE_ACTIVATE_FIRST=y +CONFIG_PARTITION=y +CONFIG_PARTITION_DISK=y +CONFIG_PARTITION_DISK_DOS=y +CONFIG_DEFAULT_ENVIRONMENT=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycard-omap3/env" +CONFIG_COMMAND_SUPPORT=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TRUE=y +CONFIG_CMD_FALSE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_LOGIN=y +CONFIG_CMD_PASSWD=y +CONFIG_PASSWD_MODE_STAR=y +CONFIG_CMD_TIME=y +CONFIG_CMD_LS=y +CONFIG_CMD_RM=y +CONFIG_CMD_CAT=y +CONFIG_CMD_MKDIR=y +CONFIG_CMD_RMDIR=y +CONFIG_CMD_CP=y +CONFIG_CMD_PWD=y +CONFIG_CMD_CD=y +CONFIG_CMD_MOUNT=y +CONFIG_CMD_UMOUNT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_CLEAR=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_DIGEST=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_SHA224SUM=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_UBI=y +CONFIG_CMD_BOOTM=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_IMINFO=y +CONFIG_CMD_BOOTZ=n +CONFIG_CMD_BOOTU=n +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_TEST=y +CONFIG_CMD_VERSION=y +CONFIG_CMD_HELP=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_DEVINFO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +CONFIG_PHYLIB=y +CONFIG_DRIVER_NET_SMC911X=y +CONFIG_DRIVER_NET_SMC911X_ADDRESS_SHIFT=0 +CONFIG_SPI=n +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_WRITE=y +CONFIG_NAND_ECC_SOFT=y +CONFIG_NAND_ECC_HW=y +CONFIG_NAND_ECC_HW_SYNDROME=y +CONFIG_NAND_ECC_HW_NONE=y +CONFIG_NAND_INFO=y +CONFIG_NAND_READ_OOB=y +CONFIG_NAND_BBT=y +CONFIG_NAND_OOB_DEVICE=y +CONFIG_NAND_OMAP_GPMC=y +CONFIG_MTD_NAND_IDS=y +CONFIG_UBI=y +CONFIG_DISK=y +CONFIG_DISK_WRITE=y +CONFIG_DISK_ATA=y +CONFIG_DISK_INTF_PLATFORM_IDE=y +CONFIG_MCI=y +CONFIG_MCI_INFO=y +CONFIG_MCI_WRITE=y +CONFIG_MCI_OMAP_HSMMC=y +CONFIG_FS_CRAMFS=y +CONFIG_FS_RAMFS=y +CONFIG_FS_DEVFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_PARTITION_NEED_MTD=y +CONFIG_ZLIB=y +CONFIG_BZLIB=y +CONFIG_PROCESS_ESCAPE_SEQUENCE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_FDT=y +CONFIG_OFTREE=y +CONFIG_CRC32=y +CONFIG_CRC16=y +CONFIG_DIGEST=y +CONFIG_MD5=y +CONFIG_SHA1=y +CONFIG_SHA224=y +CONFIG_SHA256=y diff --git a/arch/arm/configs/phytec-phycard-omap4-xload_defconfig b/arch/arm/configs/phytec-phycard-omap4-xload_defconfig new file mode 100644 index 0000000..84160e3 --- /dev/null +++ b/arch/arm/configs/phytec-phycard-omap4-xload_defconfig @@ -0,0 +1,41 @@ +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP4=y +CONFIG_OMAP_BUILD_IFT=y +CONFIG_MACH_PCAAXL2=y +CONFIG_AEABI=y +CONFIG_THUMB2_BAREBOX=y +# CONFIG_CMD_ARM_CPUINFO is not set +# CONFIG_ARM_EXCEPTIONS is not set +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x40300000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x8f000000 +CONFIG_MALLOC_BASE=0x84000000 +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_MALLOC_DUMMY=y +CONFIG_PROMPT="barebox> " +CONFIG_SHELL_NONE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_SIMPLE=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +# CONFIG_NAND_INFO is not set +# CONFIG_NAND_BBT is not set +CONFIG_NAND_OMAP_GPMC=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +# CONFIG_MCI_WRITE is not set +CONFIG_MCI_OMAP_HSMMC=y +# CONFIG_FS_RAMFS is not set +# CONFIG_FS_DEVFS is not set +CONFIG_FS_FAT=y diff --git a/arch/arm/configs/phytec-phycard-omap4_defconfig b/arch/arm/configs/phytec-phycard-omap4_defconfig new file mode 100644 index 0000000..2b7548b --- /dev/null +++ b/arch/arm/configs/phytec-phycard-omap4_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARCH_OMAP=y +CONFIG_ARCH_OMAP4=y +CONFIG_MACH_PCAAXL2=y +CONFIG_AEABI=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x8f000000 +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_KALLSYMS=y +CONFIG_PROMPT="barebox> " +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_HUSH_GETOPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_TIMESTAMP is not set +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycard-omap4/env/" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_FLASH=y +# CONFIG_CMD_BOOTM is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNLZO=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +CONFIG_DRIVER_NET_KS8851_MLL=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_OMAP_GPMC=y +CONFIG_UBI=y +CONFIG_MCI=y +CONFIG_MCI_OMAP_HSMMC=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/phytec-phycore-am335x_defconfig b/arch/arm/configs/phytec-phycore-am335x_defconfig new file mode 100644 index 0000000..c74116b --- /dev/null +++ b/arch/arm/configs/phytec-phycore-am335x_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARCH_OMAP=y +CONFIG_BAREBOX_UPDATE_AM33XX_SPI_NOR_MLO=y +CONFIG_OMAP_MULTI_BOARDS=y +CONFIG_MACH_PCM051=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_ARM_BOARD_APPEND_ATAG=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x0 +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_PROMPT="barebox@pcm051>" +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +# CONFIG_TIMESTAMP is not set +CONFIG_BLSPEC=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-am335x/env" +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_UBIFORMAT=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_DETECT=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +CONFIG_DRIVER_NET_CPSW=y +CONFIG_DRIVER_SPI_OMAP3=y +CONFIG_I2C=y +CONFIG_I2C_OMAP=y +CONFIG_MTD=y +CONFIG_MTD_M25P80=y +CONFIG_NAND=y +CONFIG_NAND_OMAP_GPMC=y +CONFIG_MTD_UBI=y +CONFIG_USB=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_OMAP_HSMMC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y +CONFIG_EEPROM_AT24=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_BUS_OMAP_GPMC=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y diff --git a/arch/arm/configs/phytec-phycore-imx27_defconfig b/arch/arm/configs/phytec-phycore-imx27_defconfig new file mode 100644 index 0000000..07751ea --- /dev/null +++ b/arch/arm/configs/phytec-phycore-imx27_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARCH_IMX=y +CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y +CONFIG_ARCH_IMX27=y +CONFIG_MACH_PCM038=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0xa7f00000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-imx27/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_MTEST=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +CONFIG_NAND_IMX=y +CONFIG_USB=y +CONFIG_USB_IMX_CHIPIDEA=y +CONFIG_USB_EHCI=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_IMX=y +CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/phytec-phycore-imx31_defconfig b/arch/arm/configs/phytec-phycore-imx31_defconfig new file mode 100644 index 0000000..2aa87fe --- /dev/null +++ b/arch/arm/configs/phytec-phycore-imx31_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARCH_IMX=y +CONFIG_CACHE_L2X0=y +CONFIG_ARCH_IMX31=y +CONFIG_MACH_PCM037=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x01000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PARTITION=y +CONFIG_PARTITION_DISK=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-imx31/env" +CONFIG_RESET_SOURCE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_SPI=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y +CONFIG_DRIVER_NET_SMC911X=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_IMX=y +CONFIG_UBI=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_FS_EXT4=y +CONFIG_FS_TFTP=y +CONFIG_FS_NFS=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/phytec-phycore-imx35_defconfig b/arch/arm/configs/phytec-phycore-imx35_defconfig new file mode 100644 index 0000000..59c1b82 --- /dev/null +++ b/arch/arm/configs/phytec-phycore-imx35_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARCH_IMX=y +CONFIG_CACHE_L2X0=y +CONFIG_ARCH_IMX_EXTERNAL_BOOT=y +CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y +CONFIG_ARCH_IMX35=y +CONFIG_MACH_PCM043=y +CONFIG_IMX_IIM=y +CONFIG_IMX_IIM_FUSE_BLOW=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x87E00000 +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PARTITION=y +CONFIG_PARTITION_DISK=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-imx35/env" +CONFIG_RESET_SOURCE=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_LET=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_DIRNAME=y +CONFIG_CMD_LN=y +CONFIG_CMD_READLINK=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_OFTREE_PROBE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_CLK=y +CONFIG_CMD_WD=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_NET_NETCONSOLE=y +CONFIG_DRIVER_NET_FEC_IMX=y +# CONFIG_SPI is not set +CONFIG_DRIVER_CFI=y +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_IMX=y +CONFIG_UBI=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_IMX=y +CONFIG_FS_TFTP=y +CONFIG_ZLIB=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/phytec-phycore-omap4460-xload_defconfig b/arch/arm/configs/phytec-phycore-omap4460-xload_defconfig new file mode 100644 index 0000000..6bbc2e4 --- /dev/null +++ b/arch/arm/configs/phytec-phycore-omap4460-xload_defconfig @@ -0,0 +1,42 @@ +CONFIG_ARCH_OMAP=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xC000 +CONFIG_ARCH_OMAP4=y +CONFIG_OMAP_BUILD_IFT=y +CONFIG_MACH_PCM049=y +CONFIG_THUMB2_BAREBOX=y +# CONFIG_CMD_ARM_CPUINFO is not set +# CONFIG_ARM_EXCEPTIONS is not set +# CONFIG_MEMINFO is not set +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x40300000 +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x8f000000 +CONFIG_MALLOC_BASE=0x84000000 +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_MALLOC_DUMMY=y +CONFIG_PROMPT="barebox> " +CONFIG_SHELL_NONE=y +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_SIMPLE=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +# CONFIG_SPI is not set +CONFIG_MTD=y +# CONFIG_MTD_WRITE is not set +# CONFIG_MTD_OOB_DEVICE is not set +CONFIG_NAND=y +# CONFIG_NAND_ECC_SOFT is not set +# CONFIG_NAND_ECC_HW_SYNDROME is not set +# CONFIG_NAND_ECC_HW_NONE is not set +# CONFIG_NAND_INFO is not set +# CONFIG_NAND_BBT is not set +CONFIG_NAND_OMAP_GPMC=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +# CONFIG_MCI_WRITE is not set +CONFIG_MCI_OMAP_HSMMC=y +# CONFIG_FS_RAMFS is not set +# CONFIG_FS_DEVFS is not set +CONFIG_FS_FAT=y diff --git a/arch/arm/configs/phytec-phycore-omap4460_defconfig b/arch/arm/configs/phytec-phycore-omap4460_defconfig new file mode 100644 index 0000000..906dfea --- /dev/null +++ b/arch/arm/configs/phytec-phycore-omap4460_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARCH_OMAP=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x80000 +CONFIG_ARCH_OMAP4=y +CONFIG_MACH_PCM049=y +CONFIG_AEABI=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_TEXT_BASE=0x8f000000 +CONFIG_MALLOC_SIZE=0x2000000 +CONFIG_KALLSYMS=y +CONFIG_PROMPT="barebox> " +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_TIMESTAMP is not set +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-omap4460/env" +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y +CONFIG_NET_PING=y +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +CONFIG_SMSC_PHY=y +CONFIG_DRIVER_NET_SMC911X=y +# CONFIG_SPI is not set +CONFIG_I2C=y +CONFIG_I2C_OMAP=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_OMAP_GPMC=y +CONFIG_UBI=y +CONFIG_USB=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_OMAP=y +CONFIG_IMAGE_RENDERER=y +CONFIG_BMP=y +CONFIG_MCI=y +CONFIG_MCI_STARTUP=y +CONFIG_MCI_OMAP_HSMMC=y +CONFIG_MFD_TWL6030=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_LZO_DECOMPRESS=y diff --git a/arch/arm/configs/phytec-phycore-pxa270_defconfig b/arch/arm/configs/phytec-phycore-pxa270_defconfig new file mode 100644 index 0000000..0e8d1b3 --- /dev/null +++ b/arch/arm/configs/phytec-phycore-pxa270_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARCH_PXA=y +CONFIG_MACH_PCM027=y +CONFIG_AEABI=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x1000000 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_LONGHELP=y +CONFIG_GLOB=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-pxa270/env" +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_UIMAGE=y +# CONFIG_CMD_BOOTZ is not set +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SPLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_NET=y +CONFIG_NET_DHCP=y +CONFIG_NET_PING=y +CONFIG_CMD_TFTP=y +CONFIG_FS_TFTP=y +CONFIG_DRIVER_SERIAL_PXA=y +CONFIG_DRIVER_NET_SMC91111=y +# CONFIG_SPI is not set +CONFIG_MTD=y +CONFIG_DRIVER_CFI=y +CONFIG_VIDEO=y +CONFIG_DRIVER_VIDEO_PXA=y +CONFIG_LZO_DECOMPRESS=y diff --git a/images/Makefile.imx b/images/Makefile.imx index dd12242..9aca871 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -16,7 +16,7 @@ # ----------------------- i.MX51 based boards --------------------------- pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage -CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-pdk/flash-header-imx51-babbage.imxcfg +CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg FILE_barebox-freescale-imx51-babbage.img = start_imx51_babbage.pblx.imximg image-$(CONFIG_MACH_FREESCALE_MX51_PDK) += barebox-freescale-imx51-babbage.img @@ -27,12 +27,12 @@ # ----------------------- i.MX53 based boards --------------------------- pblx-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += start_imx53_loco -CFG_start_imx53_loco.pblx.imximg = $(board)/freescale-mx53-loco/flash-header-imx53-loco.imxcfg +CFG_start_imx53_loco.pblx.imximg = $(board)/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg FILE_barebox-freescale-imx53-loco.img = start_imx53_loco.pblx.imximg image-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += barebox-freescale-imx53-loco.img pblx-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += start_imx53_loco_r -CFG_start_imx53_loco_r.pblx.imximg = $(board)/freescale-mx53-loco/flash-header-imx53-loco.imxcfg +CFG_start_imx53_loco_r.pblx.imximg = $(board)/freescale-mx53-qsb/flash-header-imx53-loco.imxcfg FILE_barebox-freescale-imx53-loco-r.img = start_imx53_loco_r.pblx.imximg image-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += barebox-freescale-imx53-loco-r.img @@ -53,7 +53,7 @@ # ----------------------- i.MX6 based boards --------------------------- pblx-$(CONFIG_MACH_REALQ7) += start_imx6_realq7 -CFG_start_imx6_realq7.pblx.imximg = $(board)/dmo-mx6-realq7/flash-header.imxcfg +CFG_start_imx6_realq7.pblx.imximg = $(board)/datamodul-edm-qmx6/flash-header.imxcfg FILE_barebox-datamodul-edm-qmx6.img = start_imx6_realq7.pblx.imximg image-$(CONFIG_MACH_REALQ7) += barebox-datamodul-edm-qmx6.img @@ -73,12 +73,12 @@ image-$(CONFIG_MACH_TQMA6X) += barebox-tq-tqma6q-mba6x.img pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_2gib -CFG_start_phytec_pbab01_2gib.pblx.imximg = $(board)/phytec-pfla02/flash-header-phytec-pfla02-2gib.imxcfg +CFG_start_phytec_pbab01_2gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg FILE_barebox-phytec-pbab01-2gib.img = start_phytec_pbab01_2gib.pblx.imximg image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-2gib.img pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_1gib -CFG_start_phytec_pbab01_1gib.pblx.imximg = $(board)/phytec-pfla02/flash-header-phytec-pfla02-1gib.imxcfg +CFG_start_phytec_pbab01_1gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg FILE_barebox-phytec-pbab01-1gib.img = start_phytec_pbab01_1gib.pblx.imximg image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-1gib.img