diff --git a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h index bcd9789..5c15372 100644 --- a/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h +++ b/arch/mips/boards/qemu-malta/include/board/board_pbl_start.h @@ -20,15 +20,80 @@ #include #include +#include +#include +#include + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define GT_CPU_TO_LE32(x) (x) +#elif defined CONFIG_CPU_BIG_ENDIAN +#define GT_CPU_TO_LE32(x) ( \ + (((x) & 0x000000ff) << 24) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0xff000000) >> 24)) +#else +#error "could not determine byte order" +#endif + +#define GT_LD(x) (GT_CPU_TO_LE32(((x) >> 21) & 0x7fff)) +#define GT_HD(x) (GT_CPU_TO_LE32(((x) >> 21) & 0x7f)) + .macro board_pbl_start .set push .set noreorder + b __start + nop + + /* + On MIPS Technologies boards + 0x1fc00010 address is reserved for BoardID + */ + .org 0x10 + .word 0xffffffff + .word 0xffffffff + +__start: mips_disable_interrupts /* cpu specific setup ... */ /* ... absent */ + /* + * Load BAR registers of GT64120 as done by YAMON + * + * based on write_bootloader() in qemu.git/hw/mips/mips_malta.c + * see GT64120 manual and qemu.git/hw/mips/gt64xxx_pci.c for details + */ + + /* move GT64120 registers to 0x1be00000 */ + li t1, KSEG1ADDR(GT_DEF_BASE) + li t0, GT_LD(MIPS_GT_BASE) + sw t0, GT_ISD_OFS(t1) + + /* + * setup MEM-to-PCI0 mapping + */ + li t1, KSEG1ADDR(MIPS_GT_BASE) + + /* setup PCI0 io window */ + li t0, GT_LD(0x18000000) + sw t0, GT_PCI0IOLD_OFS(t1) + li t0, GT_HD(0x181fffff) + sw t0, GT_PCI0IOHD_OFS(t1) + + /* setup PCI0 mem windows */ + li t0, GT_LD(0x10000000) + sw t0, GT_PCI0M0LD_OFS(t1) + li t0, GT_HD(0x17efffff) + sw t0, GT_PCI0M0HD_OFS(t1) + + li t0, GT_LD(0x18200000) + sw t0, GT_PCI0M1LD_OFS(t1) + li t0, GT_LD(0x1bdfffff) + sw t0, GT_PCI0M1HD_OFS(t1) + mips_nmon copy_to_link_location pbl_start diff --git a/arch/mips/boards/qemu-malta/qemu-malta.dox b/arch/mips/boards/qemu-malta/qemu-malta.dox index 2e03636..bf10244 100644 --- a/arch/mips/boards/qemu-malta/qemu-malta.dox +++ b/arch/mips/boards/qemu-malta/qemu-malta.dox @@ -4,12 +4,17 @@ Emulator run string: @verbatim -qemu-system-mips -nodefaults -M malta -m 256 -nographic -serial stdio -monitor null -bios barebox.bin +qemu-system-mips -nodefaults -M malta -m 256 -nographic -serial stdio -monitor null -bios barebox-flash-image +@endverbatim + +Also you can use GXemul: +@verbatim +gxemul -Q -x -e maltabe -M 256 0xbfc00000:barebox-flash-image @endverbatim Links: -@li http://www.mips.com/products/development-kits/malta/ @li http://www.linux-mips.org/wiki/Mips_Malta @li http://www.qemu.org/ +@li http://gxemul.sourceforge.net/ */ diff --git a/arch/mips/dts/qemu-malta.dts b/arch/mips/dts/qemu-malta.dts index 4057729..b6b69c4 100644 --- a/arch/mips/dts/qemu-malta.dts +++ b/arch/mips/dts/qemu-malta.dts @@ -17,9 +17,9 @@ reg = <0x00000000 0x10000000>; }; - uart0: serial@b00003f8 { + uart0: serial@b80003f8 { compatible = "ns16550a"; - reg = <0xb00003f8 0x08>; + reg = <0xb80003f8 0x08>; reg-shift = <0>; /* no matter for emulated port */ clock-frequency = <1843200>; diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h new file mode 100644 index 0000000..6b2ad0f --- /dev/null +++ b/arch/mips/include/asm/gt64120.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ +#ifndef _ASM_GT64120_H +#define _ASM_GT64120_H + +#define GT_DEF_BASE 0x14000000 + +/* + * Register offset addresses + */ + +/* CPU Address Decode. */ +#define GT_PCI0IOLD_OFS 0x048 +#define GT_PCI0IOHD_OFS 0x050 +#define GT_PCI0M0LD_OFS 0x058 +#define GT_PCI0M0HD_OFS 0x060 +#define GT_ISD_OFS 0x068 + +#define GT_PCI0M1LD_OFS 0x080 +#define GT_PCI0M1HD_OFS 0x088 + +#endif /* _ASM_GT64120_H */ diff --git a/arch/mips/mach-malta/include/mach/hardware.h b/arch/mips/mach-malta/include/mach/hardware.h index affb4ea..9345a67 100644 --- a/arch/mips/mach-malta/include/mach/hardware.h +++ b/arch/mips/mach-malta/include/mach/hardware.h @@ -18,7 +18,7 @@ #ifndef __INCLUDE_ARCH_HARDWARE_H__ #define __INCLUDE_ARCH_HARDWARE_H__ -#define MALTA_PIIX4_UART0 0xb00003f8 +#define MALTA_PIIX4_UART0 0xb80003f8 /* * Reset register. diff --git a/arch/mips/mach-malta/include/mach/mach-gt64120.h b/arch/mips/mach-malta/include/mach/mach-gt64120.h new file mode 100644 index 0000000..ed1e23e --- /dev/null +++ b/arch/mips/mach-malta/include/mach/mach-gt64120.h @@ -0,0 +1,13 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H +#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H + +#define MIPS_GT_BASE 0x1be00000 + +#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */