diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c index 030c3db..b132ccc 100644 --- a/arch/arm/boards/at91rm9200ek/lowlevel.c +++ b/arch/arm/boards/at91rm9200ek/lowlevel.c @@ -33,28 +33,28 @@ /* * PMC Check if the PLL is already initialized */ - r = __raw_readl(pmc + AT91_PMC_MCKR); + r = readl(pmc + AT91_PMC_MCKR); if (r & AT91_PMC_CSS) goto end; /* * Enable the Main Oscillator */ - __raw_writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR); + writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR); do { - r = __raw_readl(pmc + AT91_PMC_SR); + r = readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_MOSCS)); /* * EBI_CFGR */ - __raw_writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR); + writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR); /* * SMC2_CSR[0]: 16bit, 2 TDF, 4 WS */ - __raw_writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0)); + writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0)); /* * Init Clocks @@ -63,24 +63,24 @@ /* * PLLAR: x MHz for PCK */ - __raw_writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR); + writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR); do { - r = __raw_readl(pmc + AT91_PMC_SR); + r = readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_LOCKA)); /* * PCK/x = MCK Master Clock from SLOW */ - __raw_writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR); + writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR); /* * PCK/x = MCK Master Clock from PLLA */ - __raw_writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR); + writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR); do { - r = __raw_readl(pmc + AT91_PMC_SR); + r = readl(pmc + AT91_PMC_SR); } while (!(r & AT91_PMC_MCKRDY)); /* @@ -88,38 +88,38 @@ */ /* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */ - __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR); + writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR); /* PIOC_BSR */ - __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR); + writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR); /* PIOC_PDR */ - __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR); + writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR); /* EBI_CSA : CS1=SDRAM */ - __raw_writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91RM9200_EBI_CSA); + writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91RM9200_EBI_CSA); /* SDRC_CR */ - __raw_writel(CONFIG_SYS_SDRC_CR_VAL, mc + AT91RM9200_SDRAMC_CR); + writel(CONFIG_SYS_SDRC_CR_VAL, mc + AT91RM9200_SDRAMC_CR); /* SDRC_MR : Precharge All */ - __raw_writel(AT91RM9200_SDRAMC_MODE_PRECHARGE, mc + AT91RM9200_SDRAMC_MR); + writel(AT91RM9200_SDRAMC_MODE_PRECHARGE, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM */ access_sdram(); /* SDRC_MR : refresh */ - __raw_writel(AT91RM9200_SDRAMC_MODE_REFRESH, mc + AT91RM9200_SDRAMC_MR); + writel(AT91RM9200_SDRAMC_MODE_REFRESH, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM 8 times */ for (i = 0; i < 8; i++) access_sdram(); /* SDRC_MR : Load Mode Register */ - __raw_writel(AT91RM9200_SDRAMC_MODE_LMR, mc + AT91RM9200_SDRAMC_MR); + writel(AT91RM9200_SDRAMC_MODE_LMR, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM */ access_sdram(); /* SDRC_TR : Write refresh rate */ - __raw_writel(CONFIG_SYS_SDRC_TR_VAL, mc + AT91RM9200_SDRAMC_TR); + writel(CONFIG_SYS_SDRC_TR_VAL, mc + AT91RM9200_SDRAMC_TR); /* access SDRAM */ access_sdram(); /* SDRC_MR : Normal Mode */ - __raw_writel(AT91RM9200_SDRAMC_MODE_NORMAL, mc + AT91RM9200_SDRAMC_MR); + writel(AT91RM9200_SDRAMC_MODE_NORMAL, mc + AT91RM9200_SDRAMC_MR); /* access SDRAM */ access_sdram(); diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c index 9aa0e8b..5011910 100644 --- a/arch/arm/boards/at91sam9x5ek/lowlevel.c +++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c index 0e25270..8492ae9 100644 --- a/arch/arm/boards/sama5d3_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c @@ -19,5 +19,5 @@ arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); - barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL); + barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL); } diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c index 0e25270..8492ae9 100644 --- a/arch/arm/boards/sama5d3xek/lowlevel.c +++ b/arch/arm/boards/sama5d3xek/lowlevel.c @@ -19,5 +19,5 @@ arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); - barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL); + barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL); } diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c index 0e25270..9021ef5 100644 --- a/arch/arm/boards/sama5d4_xplained/lowlevel.c +++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c @@ -17,7 +17,7 @@ { arm_cpu_lowlevel_init(); - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); + arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16); - barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL); + barebox_arm_entry(SAMA5_DDRCS, at91sama5d4_get_ddram_size(), NULL); } diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c index 0e25270..9021ef5 100644 --- a/arch/arm/boards/sama5d4ek/lowlevel.c +++ b/arch/arm/boards/sama5d4ek/lowlevel.c @@ -17,7 +17,7 @@ { arm_cpu_lowlevel_init(); - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16); + arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE - 16); - barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), NULL); + barebox_arm_entry(SAMA5_DDRCS, at91sama5d4_get_ddram_size(), NULL); } diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index efed738..8e1bf06 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,14 +1,5 @@ if ARCH_AT91 -config HAVE_AT91_DBGU0 - bool - -config HAVE_AT91_DBGU1 - bool - -config HAVE_AT91_DBGU2 - bool - config HAVE_AT91_UTMI bool @@ -115,7 +106,6 @@ config SOC_AT91SAM9260 bool select SOC_AT91SAM9 - select HAVE_AT91_DBGU0 select HAS_MACB help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE @@ -124,21 +114,18 @@ config SOC_AT91SAM9261 bool select SOC_AT91SAM9 - select HAVE_AT91_DBGU0 help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. config SOC_AT91SAM9263 bool select SOC_AT91SAM9 - select HAVE_AT91_DBGU1 select HAS_MACB select HAVE_AT91_LOAD_BAREBOX_SRAM config SOC_AT91SAM9G45 bool select SOC_AT91SAM9 - select HAVE_AT91_DBGU1 select HAS_MACB help Select this if you are using one of Atmel's AT91SAM9G45 family SoC. @@ -147,7 +134,6 @@ config SOC_AT91SAM9X5 bool select SOC_AT91SAM9 - select HAVE_AT91_DBGU0 select HAS_MACB select COMMON_CLK_OF_PROVIDER help @@ -160,7 +146,6 @@ config SOC_AT91SAM9N12 bool select SOC_AT91SAM9 - select HAVE_AT91_DBGU0 help Select this if you are using Atmel's AT91SAM9N12 SoC. @@ -213,14 +198,12 @@ config ARCH_SAMA5D3 bool "SAMA5D3x" select SOC_SAMA5D3 - select HAVE_AT91_DBGU1 select HAS_MACB select HAVE_MACH_ARM_HEAD config ARCH_SAMA5D4 bool "SAMA5D4" select SOC_SAMA5D4 - select HAVE_AT91_DBGU2 select HAS_MACB select HAVE_MACH_ARM_HEAD diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h index 3b59485..e33a358 100644 --- a/arch/arm/mach-at91/include/mach/at91_dbgu.h +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h @@ -16,7 +16,6 @@ #ifndef AT91_DBGU_H #define AT91_DBGU_H -#if !defined(CONFIG_ARCH_AT91X40) #define AT91_DBGU_CR (0x00) /* Control Register */ #define AT91_DBGU_MR (0x04) /* Mode Register */ #define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */ @@ -34,7 +33,6 @@ #define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */ #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ -#endif /* AT91_DBGU */ /* * Some AT91 parts that don't have full DEBUG units still support the ID diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h index 9ab0eef..d52a29e 100644 --- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h +++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h @@ -78,43 +78,43 @@ int in_sram = running_in_sram(); /* SDRAMC Check if Refresh Timer Counter is already initialized */ - r = __raw_readl(cfg->sdramc + AT91_SDRAMC_TR); + r = readl(cfg->sdramc + AT91_SDRAMC_TR); if (r && !in_sram) return; /* SDRAMC_MR : Normal Mode */ - __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); + writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); /* SDRAMC_TR - Refresh Timer register */ - __raw_writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR); + writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR); /* SDRAMC_CR - Configuration register*/ - __raw_writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR); + writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR); /* Memory Device Type */ - __raw_writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR); + writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR); /* SDRAMC_MR : Precharge All */ - __raw_writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR); + writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR); access_sdram(); /* SDRAMC_MR : refresh */ - __raw_writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR); + writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR); /* access SDRAM 8 times */ for (i = 0; i < 8; i++) access_sdram(); /* SDRAMC_MR : Load Mode Register */ - __raw_writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR); + writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR); access_sdram(); /* SDRAMC_MR : Normal Mode */ - __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); + writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR); access_sdram(); /* SDRAMC_TR : Refresh Timer Counter */ - __raw_writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR); + writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR); access_sdram(); } @@ -127,7 +127,7 @@ if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT)) return; - __raw_writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR); + writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR); /* configure PIOx as EBI0 D[16-31] */ at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr); diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h index 1c4d313..496cf70 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h @@ -137,17 +137,19 @@ #ifndef __ASSEMBLY__ #include +#include -static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb) +static inline u32 at91_get_ddram_size(void __iomem *base, bool is_nb) { u32 cr; u32 mdr; u32 size; bool is_sdram; - cr = __raw_readl(base + AT91_DDRSDRC_CR); - mdr = __raw_readl(base + AT91_DDRSDRC_MDR); + cr = readl(base + AT91_DDRSDRC_CR); + mdr = readl(base + AT91_DDRSDRC_MDR); + /* will always be false for sama5d2, sama5d3 or sama5d4 */ is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR; /* Formula: @@ -175,8 +177,6 @@ return size; } -#ifdef CONFIG_SOC_AT91SAM9G45 -#include static inline u32 at91sam9g45_get_ddram_size(int bank) { switch (bank) { @@ -188,76 +188,26 @@ return 0; } } -#else -static inline u32 at91sam9g45_get_ddram_size(int bank) -{ - return 0; -} -#endif -#ifdef CONFIG_SOC_AT91SAM9X5 -#include static inline u32 at91sam9x5_get_ddram_size(void) { return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true); } -#else -static inline u32 at91sam9x5_get_ddram_size(void) -{ - return 0; -} -#endif -#ifdef CONFIG_SOC_AT91SAM9N12 -#include static inline u32 at91sam9n12_get_ddram_size(void) { return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true); } -#else -static inline u32 at91sam9n12_get_ddram_size(void) + +static inline u32 at91sama5d3_get_ddram_size(void) { - return 0; + return at91_get_ddram_size(IOMEM(SAMA5D3_BASE_MPDDRC), true); } -#endif -#ifdef CONFIG_SOC_SAMA5 -#include -static inline u32 at91sama5_get_ddram_size(void) +static inline u32 at91sama5d4_get_ddram_size(void) { - u32 cr; - u32 mdr; - u32 size; - void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC); - - cr = __raw_readl(base + AT91_DDRSDRC_CR); - mdr = __raw_readl(base + AT91_DDRSDRC_MDR); - - /* Formula: - * size = bank << (col + row + 1); - * if (bandwidth == 32 bits) - * size <<= 1; - */ - size = 1; - /* COL */ - size += (cr & AT91_DDRSDRC_NC) + 9; - /* ROW */ - size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11; - /* BANK */ - size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size; - - /* bandwidth */ - if (!(mdr & AT91_DDRSDRC_DBW)) - size <<= 1; - - return size; + return at91_get_ddram_size(IOMEM(SAMA5D4_BASE_MPDDRC), true); } -#else -static inline u32 at91sama5_get_ddram_size(void) -{ - return 0; -} -#endif #endif diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h index 8595f9c..7bd887c 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h @@ -90,7 +90,7 @@ u32 val; u32 size; - val = __raw_readl(base + AT91_SDRAMC_CR); + val = readl(base + AT91_SDRAMC_CR); /* Formula: * size = bank << (col + row + 1); @@ -114,7 +114,7 @@ static inline bool at91_is_low_power_sdram(void *base) { - return __raw_readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM; + return readl(base + AT91_SDRAMC_MDR) & AT91_SDRAMC_MD_LOW_POWER_SDRAM; } #ifdef CONFIG_SOC_AT91SAM9260 diff --git a/arch/arm/mach-at91/include/mach/debug_ll.h b/arch/arm/mach-at91/include/mach/debug_ll.h index 42728a4..b713930 100644 --- a/arch/arm/mach-at91/include/mach/debug_ll.h +++ b/arch/arm/mach-at91/include/mach/debug_ll.h @@ -9,13 +9,6 @@ #define __MACH_DEBUG_LL_H__ #include -#include - -#ifdef CONFIG_HAVE_AT91_DBGU0 -#define UART_BASE AT91_BASE_DBGU0 -#else -#define UART_BASE AT91_BASE_DBGU1 -#endif #define ATMEL_US_CSR 0x0014 #define ATMEL_US_THR 0x001c @@ -31,11 +24,11 @@ */ static inline void PUTC_LL(char c) { - while (!(__raw_readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY)) + while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXRDY)) barrier(); - __raw_writel(c, UART_BASE + ATMEL_US_THR); + writel(c, CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_THR); - while (!(__raw_readl(UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) + while (!(readl(CONFIG_DEBUG_AT91_UART_BASE + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) barrier(); } #endif diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index bdc0cb6..f5ab47c 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h @@ -26,67 +26,62 @@ static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) { - __raw_writel(mask, pio + PIO_IDR); + writel(mask, pio + PIO_IDR); } static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) { - __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR)); + writel(mask, pio + (on ? PIO_PUER : PIO_PUDR)); } static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) { - __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR)); + writel(mask, pio + (on ? PIO_MDER : PIO_MDDR)); } static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) { - __raw_writel(mask, pio + PIO_ASR); + writel(mask, pio + PIO_ASR); } static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) { - __raw_writel(mask, pio + PIO_BSR); + writel(mask, pio + PIO_BSR); } static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) { - - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, - pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, - pio + PIO_ABCDSR2); + writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); + writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2); } static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) { - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, - pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, - pio + PIO_ABCDSR2); + writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); + writel(readl(pio + PIO_ABCDSR2) & ~mask, pio + PIO_ABCDSR2); } static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) { - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); + writel(readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); + writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); } static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) { - __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); - __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); + writel(readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); + writel(readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); } static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) { - __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); + writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); } static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) { if (is_on) - __raw_writel(mask, pio + PIO_IFSCDR); + writel(mask, pio + PIO_IFSCDR); at91_mux_set_deglitch(pio, mask, is_on); } @@ -94,50 +89,50 @@ bool is_on, u32 div) { if (is_on) { - __raw_writel(mask, pio + PIO_IFSCER); - __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); - __raw_writel(mask, pio + PIO_IFER); + writel(mask, pio + PIO_IFSCER); + writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); + writel(mask, pio + PIO_IFER); } else { - __raw_writel(mask, pio + PIO_IFDR); + writel(mask, pio + PIO_IFDR); } } static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) { - __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); + writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); } static inline void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) { - __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); + writel(readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); } static inline void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) { - __raw_writel(mask, pio + PIO_PDR); + writel(mask, pio + PIO_PDR); } static inline void at91_mux_gpio_enable(void __iomem *pio, unsigned mask) { - __raw_writel(mask, pio + PIO_PER); + writel(mask, pio + PIO_PER); } static inline void at91_mux_gpio_input(void __iomem *pio, unsigned mask, bool input) { - __raw_writel(mask, pio + (input ? PIO_ODR : PIO_OER)); + writel(mask, pio + (input ? PIO_ODR : PIO_OER)); } static inline void at91_mux_gpio_set(void __iomem *pio, unsigned mask, int value) { - __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); + writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); } static inline int at91_mux_gpio_get(void __iomem *pio, unsigned mask) { u32 pdsr; - pdsr = __raw_readl(pio + PIO_PDSR); + pdsr = readl(pio + PIO_PDSR); return (pdsr & mask) != 0; } diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index e2e0134..2146203 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -22,33 +22,15 @@ /* sama5d4 */ #define AT91_BASE_DBGU2 0xfc069000 -#if defined(CONFIG_ARCH_AT91RM9200) #include -#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) #include -#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) #include -#elif defined(CONFIG_ARCH_AT91SAM9263) #include -#elif defined(CONFIG_ARCH_AT91SAM9RL) -#include -#elif defined(CONFIG_ARCH_AT91SAM9G45) #include -#elif defined(CONFIG_ARCH_AT91SAM9N12) #include -#elif defined(CONFIG_ARCH_AT91SAM9X5) #include -#elif defined(CONFIG_ARCH_SAMA5D3) #include -#elif defined(CONFIG_ARCH_SAMA5D4) #include -#elif defined(CONFIG_ARCH_AT91CAP9) -#include -#elif defined(CONFIG_ARCH_AT91X40) -#include -#else -#error "Unsupported AT91 processor" -#endif /* External Memory Map */ #define AT91_CHIPSELECT_0 0x10000000 diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index dc1f2ed..a4d441f 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -41,23 +41,23 @@ break; } - __raw_writel(config->mode - | AT91_SMC_TDF_(config->tdf_cycles), - mode_reg); + writel(config->mode + | AT91_SMC_TDF_(config->tdf_cycles), + mode_reg); } static void sam9_smc_cs_write_timings(void __iomem *base, struct sam9_smc_config *config) { - __raw_writel(AT91_SMC_TCLR_(config->tclr) - | AT91_SMC_TADL_(config->tadl) - | AT91_SMC_TAR_(config->tar) - | AT91_SMC_OCMS_(config->ocms) - | AT91_SMC_TRR_(config->trr) - | AT91_SMC_TWB_(config->twb) - | AT91_SMC_RBNSEL_(config->rbnsel) - | AT91_SMC_NFSEL_(config->nfsel), - base + AT91_SAMA5_SMC_TIMINGS); + writel(AT91_SMC_TCLR_(config->tclr) + | AT91_SMC_TADL_(config->tadl) + | AT91_SMC_TAR_(config->tar) + | AT91_SMC_OCMS_(config->ocms) + | AT91_SMC_TRR_(config->trr) + | AT91_SMC_TWB_(config->twb) + | AT91_SMC_RBNSEL_(config->rbnsel) + | AT91_SMC_NFSEL_(config->nfsel), + base + AT91_SAMA5_SMC_TIMINGS); } void sam9_smc_write_mode(int id, int cs, @@ -71,23 +71,23 @@ { /* Setup register */ - __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup) - | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) - | AT91_SMC_NRDSETUP_(config->nrd_setup) - | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup), - base + AT91_SMC_SETUP); + writel(AT91_SMC_NWESETUP_(config->nwe_setup) + | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup) + | AT91_SMC_NRDSETUP_(config->nrd_setup) + | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup), + base + AT91_SMC_SETUP); /* Pulse register */ - __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse) - | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) - | AT91_SMC_NRDPULSE_(config->nrd_pulse) - | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse), - base + AT91_SMC_PULSE); + writel(AT91_SMC_NWEPULSE_(config->nwe_pulse) + | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse) + | AT91_SMC_NRDPULSE_(config->nrd_pulse) + | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse), + base + AT91_SMC_PULSE); /* Cycle register */ - __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle) - | AT91_SMC_NRDCYCLE_(config->read_cycle), - base + AT91_SMC_CYCLE); + writel(AT91_SMC_NWECYCLE_(config->write_cycle) + | AT91_SMC_NRDCYCLE_(config->read_cycle), + base + AT91_SMC_CYCLE); /* Mode register */ sam9_smc_cs_write_mode(base, config); @@ -115,7 +115,7 @@ break; } - val = __raw_readl(mode_reg); + val = readl(mode_reg); config->mode = (val & ~AT91_SMC_NWECYCLE); config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; @@ -133,7 +133,7 @@ u32 val; /* Setup register */ - val = __raw_readl(base + AT91_SMC_SETUP); + val = readl(base + AT91_SMC_SETUP); config->nwe_setup = val & AT91_SMC_NWESETUP; config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; @@ -141,7 +141,7 @@ config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; /* Pulse register */ - val = __raw_readl(base + AT91_SMC_PULSE); + val = readl(base + AT91_SMC_PULSE); config->nwe_setup = val & AT91_SMC_NWEPULSE; config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; @@ -149,7 +149,7 @@ config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; /* Cycle register */ - val = __raw_readl(base + AT91_SMC_CYCLE); + val = readl(base + AT91_SMC_CYCLE); config->write_cycle = val & AT91_SMC_NWECYCLE; config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c index f5075b3..bf4a03d 100644 --- a/arch/arm/mach-at91/sama5d3_devices.c +++ b/arch/arm/mach-at91/sama5d3_devices.c @@ -28,7 +28,7 @@ void at91_add_device_sdram(u32 size) { if (!size) - size = at91sama5_get_ddram_size(); + size = at91sama5d3_get_ddram_size(); arm_add_mem_device("ram0", SAMA5_DDRCS, size); add_mem_device("sram0", SAMA5D3_SRAM_BASE, diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c index 4064e44..5a1109d 100644 --- a/arch/arm/mach-at91/sama5d4_devices.c +++ b/arch/arm/mach-at91/sama5d4_devices.c @@ -29,7 +29,7 @@ void at91_add_device_sdram(u32 size) { if (!size) - size = at91sama5_get_ddram_size(); + size = at91sama5d4_get_ddram_size(); arm_add_mem_device("ram0", SAMA5_DDRCS, size); add_mem_device("sram0", SAMA5D4_SRAM_BASE, diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index cb79eb2..4e30c78 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -29,11 +29,11 @@ { u32 cidr, socid; - cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR); + cidr = readl(dbgu_base + AT91_DBGU_CIDR); socid = cidr & ~AT91_CIDR_VERSION; /* sub version of soc */ - at91_soc_initdata.exid = __raw_readl(dbgu_base + AT91_DBGU_EXID); + at91_soc_initdata.exid = readl(dbgu_base + AT91_DBGU_EXID); switch (socid) { case ARCH_ID_AT91RM9200: diff --git a/common/Kconfig b/common/Kconfig index 899d224..cac1113 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1189,6 +1189,13 @@ Say Y here if you want low-level debugging support on RaspberryPi 1 boards. +config DEBUG_AT91_UART + bool "AT91 Debug UART" + depends on ARCH_AT91 + help + Say Y here if you want barebox low-level debugging support + on AT91 based platforms. + config DEBUG_RPI2_3_UART bool "RaspberryPi 2/3 PL011 UART" depends on ARCH_BCM283X @@ -1259,6 +1266,7 @@ help Choose UART root clock. + config DEBUG_LAYERSCAPE_UART_PORT int "Layerscape UART port selection" depends on ARCH_LAYERSCAPE @@ -1267,6 +1275,19 @@ Select the UART port number used for early debugging here. Port numbers start counting from 1. +config DEBUG_AT91_UART_BASE + hex "AT91 Debug UART Port Selection" if DEBUG_AT91_UART + default 0xfffff200 if SOC_AT91RM9200 || SOC_AT91SAM9260 \ + || SOC_AT91SAM9261 || SOC_AT91SAM9X5 \ + || SOC_AT91SAM9N12 + default 0xffffee00 if SOC_AT91SAM9263 || SOC_AT91SAM9G45 || ARCH_SAMA5D3 + default 0xfc069000 if ARCH_SAMA5D4 + default 0xfffff200 + depends on ARCH_AT91 + help + Specify UART port base address on which barebox low-level + debug messages should be output. + config DEBUG_INITCALLS bool "Trace initcalls" help diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c index 60516ca..396c35f 100644 --- a/drivers/clk/at91/clk-generated.c +++ b/drivers/clk/at91/clk-generated.c @@ -181,8 +181,7 @@ gck->hw.ops = &generated_ops; parents_array_size = num_parents * sizeof(gck->hw.parent_names[0]); - gck->hw.parent_names = xzalloc(parents_array_size); - memcpy(gck->hw.parent_names, parent_names, parents_array_size); + gck->hw.parent_names = xmemdup(parent_names, parents_array_size); gck->hw.num_parents = num_parents; /* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; */ diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c index 4d4127d..abae355 100644 --- a/drivers/clk/at91/clk-main.c +++ b/drivers/clk/at91/clk-main.c @@ -455,8 +455,7 @@ clkmain->clk.name = name; clkmain->clk.ops = &sam9x5_main_ops; parents_array_size = num_parents * sizeof (clkmain->clk.parent_names[0]); - clkmain->clk.parent_names = xzalloc(parents_array_size); - memcpy(clkmain->clk.parent_names, parent_names, parents_array_size); + clkmain->clk.parent_names = xmemdup(parent_names, parents_array_size); clkmain->clk.num_parents = num_parents; /* init.flags = CLK_SET_PARENT_GATE; */ diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index bbd6706..beb8623 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -23,77 +23,6 @@ #define SYSTEM_MAX_ID 31 -#ifdef CONFIG_HAVE_AT91_AUDIO_PLL -static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) -{ - struct clk *hw; - const char *name = np->name; - const char *parent_name; - struct regmap *regmap; - - regmap = syscon_node_to_regmap(of_get_parent(np)); - if (IS_ERR(regmap)) - return; - - parent_name = of_clk_get_parent_name(np, 0); - - hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name); - if (IS_ERR(hw)) - return; - - of_clk_add_provider(np, of_clk_src_simple_get, hw); -} -CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup, - "atmel,sama5d2-clk-audio-pll-frac", - of_sama5d2_clk_audio_pll_frac_setup); - -static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) -{ - struct clk *hw; - const char *name = np->name; - const char *parent_name; - struct regmap *regmap; - - regmap = syscon_node_to_regmap(of_get_parent(np)); - if (IS_ERR(regmap)) - return; - - parent_name = of_clk_get_parent_name(np, 0); - - hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name); - if (IS_ERR(hw)) - return; - - of_clk_add_provider(np, of_clk_src_simple_get, hw); -} -CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup, - "atmel,sama5d2-clk-audio-pll-pad", - of_sama5d2_clk_audio_pll_pad_setup); - -static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) -{ - struct clk *hw; - const char *name = np->name; - const char *parent_name; - struct regmap *regmap; - - regmap = syscon_node_to_regmap(of_get_parent(np)); - if (IS_ERR(regmap)) - return; - - parent_name = of_clk_get_parent_name(np, 0); - - hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name); - if (IS_ERR(hw)) - return; - - of_clk_add_provider(np, of_clk_src_simple_get, hw); -} -CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup, - "atmel,sama5d2-clk-audio-pll-pmc", - of_sama5d2_clk_audio_pll_pmc_setup); -#endif /* CONFIG_HAVE_AT91_AUDIO_PLL */ - #ifdef CONFIG_HAVE_AT91_GENERATED_CLK #define GENERATED_SOURCE_MAX 6 @@ -184,45 +113,6 @@ of_sama5d4_clk_h32mx_setup); #endif /* CONFIG_HAVE_AT91_H32MX */ -#ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK -#define I2S_BUS_NR 2 - -static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np) -{ - struct regmap *regmap_sfr; - u8 bus_id; - const char *parent_names[2]; - struct device_node *i2s_mux_np; - struct clk *hw; - int ret; - - regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); - if (IS_ERR(regmap_sfr)) - return; - - for_each_child_of_node(np, i2s_mux_np) { - if (of_property_read_u8(i2s_mux_np, "reg", &bus_id)) - continue; - - if (bus_id > I2S_BUS_NR) - continue; - - ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2); - if (ret != 2) - continue; - - hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, - parent_names, 2, bus_id); - if (IS_ERR(hw)) - continue; - - of_clk_add_provider(i2s_mux_np, of_clk_src_simple_get, hw); - } -} -CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux", - of_sama5d2_clk_i2s_mux_setup); -#endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */ - static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np) { struct clk *hw; diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c index aa73d61..86a50b6 100644 --- a/drivers/clk/at91/pmc.c +++ b/drivers/clk/at91/pmc.c @@ -140,8 +140,6 @@ u32 imr; u32 pcsr1; u32 pcr[PMC_MAX_IDS]; - u32 audio_pll0; - u32 audio_pll1; u32 pckr[PMC_MAX_PCKS]; } pmc_cache; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 5294983..b553ea2 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -89,18 +89,6 @@ struct clk *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data); struct clk * -at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name, - const char *parent_name); - -struct clk * -at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name, - const char *parent_name); - -struct clk * -at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name, - const char *parent_name); - -struct clk * at91_clk_register_generated(struct regmap *regmap, const char *name, const char **parent_names, u8 num_parents, u8 id, bool pll_audio, @@ -111,11 +99,6 @@ const char *parent_name); struct clk * -at91_clk_i2s_mux_register(struct regmap *regmap, const char *name, - const char * const *parent_names, - unsigned int num_parents, u8 bus_id); - -struct clk * at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name, u32 frequency, u32 accuracy); struct clk * diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index dc15f7d..7627c58 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -84,8 +84,6 @@ { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, }, { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, }, { .n = "securam_clk", .id = 51, }, - { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, }, - { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, }, { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, }, { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, }, { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, }, @@ -123,8 +121,6 @@ { .n = "pwm_gclk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, { .n = "isc_gclk", .id = 46, }, { .n = "pdmic_gclk", .id = 48, }, - { .n = "i2s0_gclk", .id = 54, .pll = true }, - { .n = "i2s1_gclk", .id = 55, .pll = true }, { .n = "can0_gclk", .id = 56, .r = { .min = 0, .max = 80000000 }, }, { .n = "can1_gclk", .id = 57, .r = { .min = 0, .max = 80000000 }, }, { .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 100000000 }, @@ -136,7 +132,7 @@ struct clk_range range = CLK_RANGE(0, 0); const char *slck_name, *mainxtal_name; struct pmc_data *sama5d2_pmc; - const char *parent_names[6]; + const char *parent_names[5]; struct regmap *regmap, *regmap_sfr; struct clk *hw; int i; @@ -157,7 +153,7 @@ if (IS_ERR(regmap)) return; - sama5d2_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1, + sama5d2_pmc = pmc_data_allocate(PMC_MCK2 + 1, nck(sama5d2_systemck), nck(sama5d2_periph32ck), nck(sama5d2_gck)); @@ -193,21 +189,6 @@ if (IS_ERR(hw)) goto err_free; - hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck", - "mainck"); - if (IS_ERR(hw)) - goto err_free; - - hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck", - "audiopll_fracck"); - if (IS_ERR(hw)) - goto err_free; - - hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck", - "audiopll_fracck"); - if (IS_ERR(hw)) - goto err_free; - regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); if (IS_ERR(regmap_sfr)) regmap_sfr = NULL; @@ -270,7 +251,7 @@ } for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) { - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + hw = at91_clk_register_sam9x5_peripheral(regmap, sama5d2_periphck[i].n, "masterck", sama5d2_periphck[i].id, @@ -282,7 +263,7 @@ } for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) { - hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + hw = at91_clk_register_sam9x5_peripheral(regmap, sama5d2_periph32ck[i].n, "h32mxck", sama5d2_periph32ck[i].id, @@ -298,11 +279,10 @@ parent_names[2] = "plladivck"; parent_names[3] = "utmick"; parent_names[4] = "mck"; - parent_names[5] = "audiopll_pmcck"; for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) { - hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, + hw = at91_clk_register_generated(regmap, sama5d2_gck[i].n, - parent_names, 6, + parent_names, 5, sama5d2_gck[i].id, sama5d2_gck[i].pll, &sama5d2_gck[i].r); @@ -312,26 +292,6 @@ sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw; } - if (regmap_sfr) { - parent_names[0] = "i2s0_clk"; - parent_names[1] = "i2s0_gclk"; - hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk", - parent_names, 2, 0); - if (IS_ERR(hw)) - goto err_free; - - sama5d2_pmc->chws[PMC_I2S0_MUX] = hw; - - parent_names[0] = "i2s1_clk"; - parent_names[1] = "i2s1_gclk"; - hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk", - parent_names, 2, 1); - if (IS_ERR(hw)) - goto err_free; - - sama5d2_pmc->chws[PMC_I2S1_MUX] = hw; - } - of_clk_add_provider(np, of_clk_hw_pmc_get, sama5d2_pmc); return; diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c index e23f1e5..6e86653 100644 --- a/drivers/clocksource/timer-atmel-pit.c +++ b/drivers/clocksource/timer-atmel-pit.c @@ -35,8 +35,8 @@ #include #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) -#define pit_write(reg, val) __raw_writel(val, pit_base + reg) -#define pit_read(reg) __raw_readl(pit_base + reg) +#define pit_write(reg, val) writel(val, pit_base + reg) +#define pit_read(reg) readl(pit_base + reg) static __iomem void *pit_base; diff --git a/drivers/mci/atmel-mci-regs.h b/drivers/mci/atmel-mci-regs.h index af1dba0..2866e3e 100644 --- a/drivers/mci/atmel-mci-regs.h +++ b/drivers/mci/atmel-mci-regs.h @@ -138,9 +138,9 @@ /* Register access macros */ #define atmci_readl(port,reg) \ - __raw_readl((port)->regs + reg) + readl((port)->regs + reg) #define atmci_writel(port,reg,value) \ - __raw_writel((value), (port)->regs + reg) + writel((value), (port)->regs + reg) /* On AVR chips the Peripheral DMA Controller is not connected to MCI. */ #ifdef CONFIG_AVR32 diff --git a/drivers/net/at91_ether.h b/drivers/net/at91_ether.h index 08df6f1..21c2ae9 100644 --- a/drivers/net/at91_ether.h +++ b/drivers/net/at91_ether.h @@ -33,7 +33,7 @@ */ static inline unsigned long at91_emac_read(unsigned int reg) { - return __raw_readl(AT91_VA_BASE_EMAC + reg); + return readl(AT91_VA_BASE_EMAC + reg); } /* @@ -41,6 +41,6 @@ */ static inline void at91_emac_write(unsigned int reg, unsigned long value) { - __raw_writel(value, AT91_VA_BASE_EMAC + reg); + writel(value, AT91_VA_BASE_EMAC + reg); } #endif diff --git a/drivers/net/macb.h b/drivers/net/macb.h index 979f53c..fda4d08 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -334,13 +334,13 @@ /* Register access macros */ #define macb_readl(port,reg) \ - __raw_readl((port)->regs + MACB_##reg) + readl((port)->regs + MACB_##reg) #define macb_writel(port,reg,value) \ - __raw_writel((value), (port)->regs + MACB_##reg) + writel((value), (port)->regs + MACB_##reg) #define gem_readl(port, reg) \ - __raw_readl((port)->regs + GEM_##reg) + readl((port)->regs + GEM_##reg) #define gem_writel(port, reg, value) \ - __raw_writel((value), (port)->regs + GEM_##reg) + writel((value), (port)->regs + GEM_##reg) /* * Conditional GEM/MACB macros. These perform the operation to the correct diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index 11e0083..9b366e4 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -303,11 +303,11 @@ { unsigned select; - if (__raw_readl(pio + PIO_PSR) & mask) + if (readl(pio + PIO_PSR) & mask) return AT91_MUX_GPIO; - select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask); - select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1); + select = !!(readl(pio + PIO_ABCDSR1) & mask); + select |= (!!(readl(pio + PIO_ABCDSR2) & mask) << 1); return select + 1; } @@ -316,34 +316,34 @@ { unsigned select; - if (__raw_readl(pio + PIO_PSR) & mask) + if (readl(pio + PIO_PSR) & mask) return AT91_MUX_GPIO; - select = __raw_readl(pio + PIO_ABSR) & mask; + select = readl(pio + PIO_ABSR) & mask; return select + 1; } static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) { - return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; + return (readl(pio + PIO_IFSR) >> pin) & 0x1; } static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) { - *div = __raw_readl(pio + PIO_SCDR); + *div = readl(pio + PIO_SCDR); - return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; + return (readl(pio + PIO_IFSCSR) >> pin) & 0x1; } static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) { - return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1; + return (readl(pio + PIO_PPDSR) >> pin) & 0x1; } static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) { - return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; + return (readl(pio + PIO_SCHMITT) >> pin) & 0x1; } static struct at91_pinctrl_mux_ops at91rm9200_ops = { @@ -559,7 +559,7 @@ unsigned mask = 1 << offset; at91_mux_gpio_set(pio, mask, value); - __raw_writel(mask, pio + PIO_OER); + writel(mask, pio + PIO_OER); return 0; } @@ -571,8 +571,8 @@ unsigned mask = 1 << offset; u32 osr; - if (mask & __raw_readl(pio + PIO_PSR)) { - osr = __raw_readl(pio + PIO_OSR); + if (mask & readl(pio + PIO_PSR)) { + osr = readl(pio + PIO_OSR); return !(osr & mask); } else { return -EBUSY; @@ -585,7 +585,7 @@ void __iomem *pio = at91_gpio->regbase; unsigned mask = 1 << offset; - __raw_writel(mask, pio + PIO_ODR); + writel(mask, pio + PIO_ODR); return 0; } diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index 3f4d7ba..7c48069 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -161,8 +161,8 @@ /* Register access macros */ #define spi_readl(port, reg) \ - __raw_readl((port)->regs + SPI_##reg) + readl((port)->regs + SPI_##reg) #define spi_writel(port, reg, value) \ - __raw_writel((value), (port)->regs + SPI_##reg) + writel((value), (port)->regs + SPI_##reg) #endif /* __ATMEL_SPI_H__ */ diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index 243656d..efbc574 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c @@ -65,9 +65,9 @@ static const char ep0name[] = "ep0"; #define at91_udp_read(udc, reg) \ - __raw_readl((udc)->udp_baseaddr + (reg)) + readl((udc)->udp_baseaddr + (reg)) #define at91_udp_write(udc, reg, val) \ - __raw_writel((val), (udc)->udp_baseaddr + (reg)) + writel((val), (udc)->udp_baseaddr + (reg)) /*-------------------------------------------------------------------------*/ @@ -136,7 +136,7 @@ * or if we already emptied both pingpong buffers */ rescan: - csr = __raw_readl(creg); + csr = readl(creg); if ((csr & RX_DATA_READY) == 0) return 0; @@ -162,7 +162,7 @@ } } else csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); - __raw_writel(csr, creg); + writel(csr, creg); req->req.actual += count; is_done = (count < ep->ep.maxpacket); @@ -184,7 +184,7 @@ * CSR returns bad RXCOUNT when read too soon after updating * RX_DATA_BK flags. */ - csr = __raw_readl(creg); + csr = readl(creg); bufferspace -= count; buf += count; @@ -198,7 +198,7 @@ static int write_fifo(struct at91_ep *ep, struct at91_request *req) { u32 __iomem *creg = ep->creg; - u32 csr = __raw_readl(creg); + u32 csr = readl(creg); u8 __iomem *dreg = ep->creg + (AT91_UDP_FDR(0) - AT91_UDP_CSR(0)); unsigned total, count, is_last; u8 *buf; @@ -219,8 +219,8 @@ if (csr & AT91_UDP_TXCOMP) { csr |= CLR_FX; csr &= ~(SET_FX | AT91_UDP_TXCOMP); - __raw_writel(csr, creg); - csr = __raw_readl(creg); + writel(csr, creg); + csr = readl(creg); } if (csr & AT91_UDP_TXPKTRDY) return 0; @@ -340,7 +340,7 @@ tmp |= 0x04; tmp <<= 8; tmp |= AT91_UDP_EPEDS; - __raw_writel(tmp, ep->creg); + writel(tmp, ep->creg); ep->desc = desc; ep->ep.maxpacket = maxpacket; @@ -373,7 +373,7 @@ if (ep->udc->clocked) { at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); at91_udp_write(udc, AT91_UDP_RST_EP, 0); - __raw_writel(0, ep->creg); + writel(0, ep->creg); } return 0; @@ -471,10 +471,10 @@ ep0_in_status: PACKET("ep0 in/status\n"); status = 0; - tmp = __raw_readl(ep->creg); + tmp = readl(ep->creg); tmp &= ~SET_FX; tmp |= CLR_FX | AT91_UDP_TXPKTRDY; - __raw_writel(tmp, ep->creg); + writel(tmp, ep->creg); udc->req_pending = 0; goto done; } @@ -534,7 +534,7 @@ creg = ep->creg; - csr = __raw_readl(creg); + csr = readl(creg); /* * fail with still-busy IN endpoints, ensuring correct sequencing @@ -554,7 +554,7 @@ at91_udp_write(udc, AT91_UDP_RST_EP, 0); csr &= ~AT91_UDP_FORCESTALL; } - __raw_writel(csr, creg); + writel(csr, creg); } return status; @@ -760,7 +760,7 @@ { struct at91_request *req; u32 __iomem *creg = ep->creg; - u32 csr = __raw_readl(creg); + u32 csr = readl(creg); if (!list_empty(&ep->queue)) req = list_entry(ep->queue.next, @@ -772,7 +772,7 @@ if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { csr |= CLR_FX; csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); - __raw_writel(csr, creg); + writel(csr, creg); } if (req) return write_fifo(ep, req); @@ -784,8 +784,8 @@ req->req.status = -EILSEQ; csr |= CLR_FX; csr &= ~(SET_FX | AT91_UDP_STALLSENT); - __raw_writel(csr, creg); - csr = __raw_readl(creg); + writel(csr, creg); + csr = readl(creg); } if (req && (csr & RX_DATA_READY)) return read_fifo(ep, req); @@ -811,7 +811,7 @@ rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; if (likely(rxcount == 8)) { while (rxcount--) - pkt.raw[i++] = __raw_readb(dreg); + pkt.raw[i++] = readb(dreg); if (pkt.r.bRequestType & USB_DIR_IN) { csr |= AT91_UDP_DIR; ep->is_in = 1; @@ -826,7 +826,7 @@ } csr |= CLR_FX; csr &= ~(SET_FX | AT91_UDP_RXSETUP); - __raw_writel(csr, creg); + writel(csr, creg); udc->wait_for_addr_ack = 0; udc->wait_for_config_ack = 0; ep->stopped = 0; @@ -846,14 +846,14 @@ * hardware ... notably for device and endpoint features. */ udc->req_pending = 1; - csr = __raw_readl(creg); + csr = readl(creg); csr |= CLR_FX; csr &= ~SET_FX; switch ((pkt.r.bRequestType << 8) | pkt.r.bRequest) { case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) | USB_REQ_SET_ADDRESS: - __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); + writel(csr | AT91_UDP_TXPKTRDY, creg); udc->addr = w_value; udc->wait_for_addr_ack = 1; udc->req_pending = 0; @@ -882,8 +882,8 @@ if (at91_udp_read(udc, AT91_UDP_GLB_STAT) & AT91_UDP_ESR) tmp |= (1 << USB_DEVICE_REMOTE_WAKEUP); PACKET("get device status\n"); - __raw_writeb(tmp, dreg); - __raw_writeb(0, dreg); + writeb(tmp, dreg); + writeb(0, dreg); goto write_in; /* then STATUS starts later, automatically */ case ((USB_TYPE_STANDARD|USB_RECIP_DEVICE) << 8) @@ -910,8 +910,8 @@ case ((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) | USB_REQ_GET_STATUS: PACKET("get interface status\n"); - __raw_writeb(0, dreg); - __raw_writeb(0, dreg); + writeb(0, dreg); + writeb(0, dreg); goto write_in; /* then STATUS starts later, automatically */ case ((USB_TYPE_STANDARD|USB_RECIP_INTERFACE) << 8) @@ -939,12 +939,12 @@ goto stall; } PACKET("get %s status\n", ep->ep.name); - if (__raw_readl(ep->creg) & AT91_UDP_FORCESTALL) + if (readl(ep->creg) & AT91_UDP_FORCESTALL) tmp = (1 << USB_ENDPOINT_HALT); else tmp = 0; - __raw_writeb(tmp, dreg); - __raw_writeb(0, dreg); + writeb(tmp, dreg); + writeb(0, dreg); goto write_in; /* then STATUS starts later, automatically */ case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) @@ -961,10 +961,10 @@ } else if (ep->is_in) goto stall; - tmp = __raw_readl(ep->creg); + tmp = readl(ep->creg); tmp &= ~SET_FX; tmp |= CLR_FX | AT91_UDP_FORCESTALL; - __raw_writel(tmp, ep->creg); + writel(tmp, ep->creg); goto succeed; case ((USB_TYPE_STANDARD|USB_RECIP_ENDPOINT) << 8) | USB_REQ_CLEAR_FEATURE: @@ -984,10 +984,10 @@ at91_udp_write(udc, AT91_UDP_RST_EP, ep->int_mask); at91_udp_write(udc, AT91_UDP_RST_EP, 0); - tmp = __raw_readl(ep->creg); + tmp = readl(ep->creg); tmp |= CLR_FX; tmp &= ~(SET_FX | AT91_UDP_FORCESTALL); - __raw_writel(tmp, ep->creg); + writel(tmp, ep->creg); if (!list_empty(&ep->queue)) handle_ep(ep); goto succeed; @@ -1008,7 +1008,7 @@ VDBG(udc, "req %02x.%02x protocol STALL; stat %d\n", pkt.r.bRequestType, pkt.r.bRequest, status); csr |= AT91_UDP_FORCESTALL; - __raw_writel(csr, creg); + writel(csr, creg); udc->req_pending = 0; } return; @@ -1018,7 +1018,7 @@ PACKET("ep0 in/status\n"); write_in: csr |= AT91_UDP_TXPKTRDY; - __raw_writel(csr, creg); + writel(csr, creg); udc->req_pending = 0; } @@ -1026,7 +1026,7 @@ { struct at91_ep *ep0 = &udc->ep[0]; u32 __iomem *creg = ep0->creg; - u32 csr = __raw_readl(creg); + u32 csr = readl(creg); struct at91_request *req; if (unlikely(csr & AT91_UDP_STALLSENT)) { @@ -1034,9 +1034,9 @@ udc->req_pending = 0; csr |= CLR_FX; csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); - __raw_writel(csr, creg); + writel(csr, creg); VDBG(udc, "ep0 stalled\n"); - csr = __raw_readl(creg); + csr = readl(creg); } if (csr & AT91_UDP_RXSETUP) { nuke(ep0, 0); @@ -1070,7 +1070,7 @@ */ } else { udc->req_pending = 0; - __raw_writel(csr, creg); + writel(csr, creg); /* * SET_ADDRESS takes effect only after the STATUS @@ -1104,10 +1104,10 @@ if (handle_ep(ep0)) { /* send IN/STATUS */ PACKET("ep0 in/status\n"); - csr = __raw_readl(creg); + csr = readl(creg); csr &= ~SET_FX; csr |= CLR_FX | AT91_UDP_TXPKTRDY; - __raw_writel(csr, creg); + writel(csr, creg); udc->req_pending = 0; } } else if (udc->req_pending) { @@ -1129,14 +1129,14 @@ * that gadget drivers not use this mode. */ DBG(udc, "no control-OUT deferred responses!\n"); - __raw_writel(csr | AT91_UDP_FORCESTALL, creg); + writel(csr | AT91_UDP_FORCESTALL, creg); udc->req_pending = 0; } /* STATUS stage for control-IN; ack. */ } else { PACKET("ep0 out/status ACK\n"); - __raw_writel(csr, creg); + writel(csr, creg); /* "early" status stage */ if (req) diff --git a/drivers/video/atmel_lcdfb.h b/drivers/video/atmel_lcdfb.h index b845892..76c0e73 100644 --- a/drivers/video/atmel_lcdfb.h +++ b/drivers/video/atmel_lcdfb.h @@ -43,8 +43,8 @@ void *dma_desc; }; -#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg)) -#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg)) +#define lcdc_readl(sinfo, reg) readl((sinfo)->mmio+(reg)) +#define lcdc_writel(sinfo, reg, val) writel((val), (sinfo)->mmio+(reg)) #define ATMEL_LCDC_STOP_NOWAIT (1 << 0)