diff --git a/include/asm-arm/arch-imx/esdctl.h b/include/asm-arm/arch-imx/esdctl.h
new file mode 100644
index 0000000..7f3c66f
--- /dev/null
+++ b/include/asm-arm/arch-imx/esdctl.h
@@ -0,0 +1,34 @@
+
+/* SDRAM Controller registers */
+#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0       */
+#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
+#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1       */
+#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
+#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register   */
+
+#define ESDCTL0_SDE				(1 << 31)
+#define ESDCTL0_SMODE_NORMAL			(0 << 28)
+#define ESDCTL0_SMODE_PRECHARGE			(1 << 28)
+#define ESDCTL0_SMODE_AUTO_REFRESH		(2 << 28)
+#define ESDCTL0_SMODE_LOAD_MODE			(3 << 28)
+#define ESDCTL0_SMODE_MANUAL_SELF_REFRESH	(4 << 28)
+#define ESDCTL0_SP				(1 << 27)
+#define ESDCTL0_ROW11				(0 << 24)
+#define ESDCTL0_ROW12				(1 << 24)
+#define ESDCTL0_ROW13				(2 << 24)
+#define ESDCTL0_ROW14				(3 << 24)
+#define ESDCTL0_ROW15				(4 << 24)
+#define ESDCTL0_COL8				(0 << 20)
+#define ESDCTL0_COL9				(1 << 20)
+#define ESDCTL0_COL10				(2 << 20)
+#define ESDCTL0_DSIZ_31_16			(0 << 16)
+#define ESDCTL0_DSIZ_15_0			(1 << 16)
+#define ESDCTL0_DSIZ_31_0			(2 << 16)
+#define ESDCTL0_REF1				(1 << 13)
+#define ESDCTL0_REF2				(2 << 13)
+#define ESDCTL0_REF4				(3 << 13)
+#define ESDCTL0_REF8				(4 << 13)
+#define ESDCTL0_REF16				(5 << 13)
+#define ESDCTL0_FP				(1 << 8)
+#define ESDCTL0_BL				(1 << 7)
+
diff --git a/include/asm-arm/arch-imx/imx27-regs.h b/include/asm-arm/arch-imx/imx27-regs.h
index 8b93bd9..6722751 100644
--- a/include/asm-arm/arch-imx/imx27-regs.h
+++ b/include/asm-arm/arch-imx/imx27-regs.h
@@ -74,38 +74,7 @@
 #define CS5A __REG(IMX_WEIM_BASE + 0x58) /* Chip Select 5 Addition Register */
 #define EIM  __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register     */
 
-/* SDRAM Controller registers */
-#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0       */
-#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
-#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1       */
-#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
-#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register   */
-
-#define ESDCTL0_SDE				(1 << 31)
-#define ESDCTL0_SMODE_NORMAL			(0 << 28)
-#define ESDCTL0_SMODE_PRECHARGE			(1 << 28)
-#define ESDCTL0_SMODE_AUTO_REFRESH		(2 << 28)
-#define ESDCTL0_SMODE_LOAD_MODE			(3 << 28)
-#define ESDCTL0_SMODE_MANUAL_SELF_REFRESH	(4 << 28)
-#define ESDCTL0_SP				(1 << 27)
-#define ESDCTL0_ROW11				(0 << 24)
-#define ESDCTL0_ROW12				(1 << 24)
-#define ESDCTL0_ROW13				(2 << 24)
-#define ESDCTL0_ROW14				(3 << 24)
-#define ESDCTL0_ROW15				(4 << 24)
-#define ESDCTL0_COL8				(0 << 20)
-#define ESDCTL0_COL9				(1 << 20)
-#define ESDCTL0_COL10				(2 << 20)
-#define ESDCTL0_DSIZ_31_16			(0 << 16)
-#define ESDCTL0_DSIZ_15_0			(1 << 16)
-#define ESDCTL0_DSIZ_31_0			(2 << 16)
-#define ESDCTL0_REF1				(1 << 13)
-#define ESDCTL0_REF2				(2 << 13)
-#define ESDCTL0_REF4				(3 << 13)
-#define ESDCTL0_REF8				(4 << 13)
-#define ESDCTL0_REF16				(5 << 13)
-#define ESDCTL0_FP				(1 << 8)
-#define ESDCTL0_BL				(1 << 7)
+#include "esdctl.h"
 
 /* Watchdog Registers*/
 #define WCR  __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
diff --git a/include/asm-arm/arch-imx/imx31-regs.h b/include/asm-arm/arch-imx/imx31-regs.h
index 06bda54..5bbff16 100644
--- a/include/asm-arm/arch-imx/imx31-regs.h
+++ b/include/asm-arm/arch-imx/imx31-regs.h
@@ -166,6 +166,9 @@
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 
+#define IMX_ESD_BASE	0xb8001000
+#include "esdctl.h"
+
 /*
  * Chip Select Registers
  */