diff --git a/Documentation/boards/openrisc.rst b/Documentation/boards/openrisc.rst new file mode 100644 index 0000000..cc00a5d --- /dev/null +++ b/Documentation/boards/openrisc.rst @@ -0,0 +1,51 @@ +OpenRISC +======== + +or1ksim +------- + +Compile or1ksim emulator:: + + $ cd ~/ + $ git clone https://github.com/openrisc/or1ksim + $ cd or1ksim + $ ./configure + $ make + +Create minimal or1ksim.cfg file:: + + section cpu + ver = 0x12 + cfgr = 0x20 + rev = 0x0001 + end + + section memory + name = "RAM" + type = unknown + baseaddr = 0x00000000 + size = 0x02000000 + delayr = 1 + delayw = 2 + end + + section uart + enabled = 1 + baseaddr = 0x90000000 + irq = 2 + 16550 = 1 + /* channel = "tcp:10084" */ + channel = "xterm:" + end + + section ethernet + enabled = 1 + baseaddr = 0x92000000 + irq = 4 + rtx_type = "tap" + tap_dev = "tap0" + end + +Run or1ksim:: + + $ ~/or1ksim/sim -f or1ksim.cfg barebox diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index 23c6a71..483ae6d 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -1,5 +1,6 @@ config OPENRISC bool + select OFTREE select HAS_CACHE select HAVE_CONFIGURABLE_MEMORY_LAYOUT select HAVE_DEFAULT_ENVIRONMENT_NEW @@ -11,6 +12,14 @@ hex default 0x00000000 +config BUILTIN_DTB + bool "link a DTB into the barebox image" + depends on OFTREE + +config BUILTIN_DTB_NAME + string "DTB to build into the barebox image" + depends on BUILTIN_DTB + choice prompt "Select your board" diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile index fd8bbbf..b0c8566 100644 --- a/arch/openrisc/Makefile +++ b/arch/openrisc/Makefile @@ -19,3 +19,10 @@ common-y += arch/openrisc/cpu/ lds-y += arch/openrisc/cpu/barebox.lds + +common-$(CONFIG_BUILTIN_DTB) += arch/openrisc/dts/ + +dts := arch/openrisc/dts + +%.dtb: scripts + $(Q)$(MAKE) $(build)=$(dts) $(dts)/$@ diff --git a/arch/openrisc/boards/generic/config.h b/arch/openrisc/boards/generic/config.h index 6ebab42..f6a054b 100644 --- a/arch/openrisc/boards/generic/config.h +++ b/arch/openrisc/boards/generic/config.h @@ -8,13 +8,8 @@ #define OPENRISC_SOPC_MEMORY_BASE 0x00000000 #define OPENRISC_SOPC_MEMORY_SIZE 0x02000000 -#define OPENRISC_SOPC_UART_FREQ CONFIG_SYS_CLK_FREQ -#define OPENRISC_SOPC_UART_BASE 0x90000000 - -#define OPENRISC_SOPC_ETHOC_BASE 0x92000000 - -/* We reserve 256K for barebox */ -#define BAREBOX_RESERVED_SIZE 0x40000 +/* We reserve 512K for barebox */ +#define BAREBOX_RESERVED_SIZE 0x80000 /* Barebox will be at top of main memory */ #define OPENRISC_SOPC_TEXT_BASE (OPENRISC_SOPC_MEMORY_BASE + OPENRISC_SOPC_MEMORY_SIZE - BAREBOX_RESERVED_SIZE) diff --git a/arch/openrisc/boards/generic/generic.c b/arch/openrisc/boards/generic/generic.c index 9f68007..ff6f9f4 100644 --- a/arch/openrisc/boards/generic/generic.c +++ b/arch/openrisc/boards/generic/generic.c @@ -1,30 +1,10 @@ #include #include -#include -#include -#include -static struct NS16550_plat serial_plat = { - .clock = OPENRISC_SOPC_UART_FREQ, - .shift = 0, -}; - -static int openrisc_console_init(void) +static int openrisc_core_init(void) { - barebox_set_model("OpenRISC or1k"); barebox_set_hostname("or1k"); - /* Register the serial port */ - add_ns16550_device(DEVICE_ID_DYNAMIC, OPENRISC_SOPC_UART_BASE, 1024, - IORESOURCE_MEM | IORESOURCE_MEM_8BIT, &serial_plat); - -#ifdef CONFIG_DRIVER_NET_ETHOC - add_generic_device("ethoc", DEVICE_ID_DYNAMIC, NULL, - OPENRISC_SOPC_ETHOC_BASE, 0x1000, - IORESOURCE_MEM, NULL); -#endif - return 0; } - -console_initcall(openrisc_console_init); +core_initcall(openrisc_core_init); diff --git a/arch/openrisc/configs/generic_defconfig b/arch/openrisc/configs/generic_defconfig index deaef2a..1f2d40e 100644 --- a/arch/openrisc/configs/generic_defconfig +++ b/arch/openrisc/configs/generic_defconfig @@ -1,26 +1,35 @@ -CONFIG_LONGHELP=y +CONFIG_BUILTIN_DTB=y +CONFIG_BUILTIN_DTB_NAME="or1ksim" CONFIG_HUSH_FANCY_PROMPT=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_PARTITION=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SAVEENV=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_BOOTM is not set +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_PARTITION=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y -CONFIG_CMD_TIME=y -CONFIG_CMD_ECHO_E=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_FLASH=y -# CONFIG_CMD_BOOTM is not set -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_PARTITION=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_NET=y +CONFIG_CMD_SAVEENV=y CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y CONFIG_CMD_PING=y CONFIG_CMD_TFTP=y -CONFIG_FS_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_NET_ETHOC=y +CONFIG_FS_TFTP=y diff --git a/arch/openrisc/cpu/barebox.lds.S b/arch/openrisc/cpu/barebox.lds.S index add9181..dbecdbf 100644 --- a/arch/openrisc/cpu/barebox.lds.S +++ b/arch/openrisc/cpu/barebox.lds.S @@ -69,6 +69,8 @@ __usymtab : { BAREBOX_SYMS } > ram ___usymtab_end = .; + .dtb : { BAREBOX_DTB() } > ram + __etext = .; /* End of text and rodata section */ . = ALIGN(4); diff --git a/arch/openrisc/dts/Makefile b/arch/openrisc/dts/Makefile new file mode 100644 index 0000000..6d6c9a3 --- /dev/null +++ b/arch/openrisc/dts/Makefile @@ -0,0 +1,5 @@ + +BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) +obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o + +clean-files := *.dtb *.dtb.S diff --git a/arch/openrisc/dts/or1ksim.dts b/arch/openrisc/dts/or1ksim.dts new file mode 100644 index 0000000..7316cc6 --- /dev/null +++ b/arch/openrisc/dts/or1ksim.dts @@ -0,0 +1,51 @@ +/dts-v1/; +/ { + model = "or1ksim"; + compatible = "opencores,or1ksim"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "console=uart,mmio,0x90000000,115200"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x02000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "opencores,or1200-rtlsvn481"; + reg = <0>; + clock-frequency = <20000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible = "opencores,or1k-pic"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible = "ns16550a"; + reg = <0x90000000 0x100>; + interrupts = <2>; + clock-frequency = <50000000>; + }; + + enet0: ethoc@92000000 { + compatible = "opencores,ethoc"; + reg = <0x92000000 0x100>; + interrupts = <4>; + }; +}; diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile index 0b3cc50..62082fe 100644 --- a/arch/openrisc/lib/Makefile +++ b/arch/openrisc/lib/Makefile @@ -5,3 +5,4 @@ obj-y += lshrdi3.o obj-y += ashldi3.o obj-y += ashrdi3.o +obj-$(CONFIG_BUILTIN_DTB) += dtb.o diff --git a/arch/openrisc/lib/dtb.c b/arch/openrisc/lib/dtb.c new file mode 100644 index 0000000..4f63a77 --- /dev/null +++ b/arch/openrisc/lib/dtb.c @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2014 Antony Pavlov + * + * Based on arch/arm/cpu/dtb.c: + * Copyright (C) 2013 Sascha Hauer , Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include + +extern char __dtb_start[]; + +static int of_openrisc_init(void) +{ + struct device_node *root; + + root = of_get_root_node(); + if (root) + return 0; + + root = of_unflatten_dtb(__dtb_start); + if (root) { + pr_debug("using internal DTB\n"); + of_set_root_node(root); + if (IS_ENABLED(CONFIG_OFDEVICE)) + of_probe(); + } + + return 0; +} +core_initcall(of_openrisc_init); diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index 679e1e5..35d7d46 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -565,8 +565,14 @@ return 0; } +static struct of_device_id ethoc_dt_ids[] = { + { .compatible = "opencores,ethoc", }, + { } +}; + static struct driver_d ethoc_driver = { .name = "ethoc", .probe = ethoc_probe, + .of_compatible = DRV_OF_COMPAT(ethoc_dt_ids), }; device_platform_driver(ethoc_driver); diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index 8195506..97a1d93 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -4,7 +4,7 @@ config OFTREE_MEM_GENERIC depends on OFTREE - depends on PPC || ARM || ARCH_EFI + depends on PPC || ARM || ARCH_EFI || OPENRISC def_bool y config DTC