diff --git a/Makefile b/Makefile
index 3923fec..61d1e57 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
 VERSION = 2013
 PATCHLEVEL = 05
-SUBLEVEL = 0
+SUBLEVEL = 1
 EXTRAVERSION =
 NAME = Amissive Actinocutious Kiwi
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d506b12..de4d2c7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,11 +190,8 @@
 
 ifdef CONFIG_IMAGE_COMPRESSION
 KBUILD_BINARY := arch/arm/pbl/zbarebox.bin
-KBUILD_TARGET := zbarebox.bin
-$(KBUILD_BINARY): $(KBUILD_TARGET)
 else
 KBUILD_BINARY := barebox.bin
-KBUILD_TARGET := barebox.bin
 endif
 
 barebox.netx: $(KBUILD_BINARY)
@@ -206,7 +203,6 @@
 		--cookie=$(CONFIG_NETX_COOKIE);
 
 ifeq ($(machine-y),netx)
-KBUILD_TARGET := barebox.netx
 KBUILD_IMAGE := barebox.netx
 endif
 
@@ -214,7 +210,6 @@
 	$(Q)scripts/s5p_cksum $< barebox.s5p
 
 ifeq ($(CONFIG_ARCH_S5PCxx),y)
-KBUILD_TARGET := barebox.s5p
 KBUILD_IMAGE := barebox.s5p
 endif
 
@@ -226,7 +221,6 @@
 	$(call if_changed,mlo)
 
 ifeq ($(CONFIG_OMAP_BUILD_IFT),y)
-KBUILD_TARGET := MLO
 KBUILD_IMAGE := MLO
 endif
 
@@ -239,7 +233,6 @@
 	$(call if_changed,davinci_ubl_image)
 
 ifeq ($(CONFIG_ARCH_DAVINCI),y)
-KBUILD_TARGET := barebox.ubl
 KBUILD_IMAGE := barebox.ubl
 endif
 
@@ -250,7 +243,6 @@
 	$(call if_changed,am35xx_spi_image)
 
 ifeq ($(CONFIG_OMAP_BUILD_SPI),y)
-KBUILD_TARGET := barebox.spi
 KBUILD_IMAGE := barebox.spi
 endif
 
@@ -258,13 +250,12 @@
 	$(Q)scripts/zynq_mkimage $< $@
 
 ifeq ($(machine-y),zynq)
-KBUILD_TARGET := barebox.zynq
 KBUILD_IMAGE := barebox.zynq
 endif
 
 pbl := arch/arm/pbl
-zbarebox.S zbarebox.bin zbarebox: barebox.bin
-	$(Q)$(MAKE) $(build)=$(pbl) $(pbl)/$@
+$(pbl)/zbarebox.S $(pbl)/zbarebox.bin $(pbl)/zbarebox: barebox.bin FORCE
+	$(Q)$(MAKE) $(build)=$(pbl) $@
 
 archclean:
 	$(MAKE) $(clean)=$(pbl)
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c
index df565d9..7f92043 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.c
+++ b/arch/arm/boards/ccxmx51/ccxmx51.c
@@ -46,30 +46,31 @@
 #include <mach/clock-imx51_53.h>
 #include <mach/imx5.h>
 #include <mach/revision.h>
+#include <mach/esdctl.h>
 
 #include "ccxmx51.h"
 
 static struct ccxmx51_ident ccxmx51_ids[] = {
-/* 0x00 */	{ "Unknown",						0, 0, 0, 0 },
-/* 0x01 */	{ "Not supported",					0, 0, 0, 0 },
-/* 0x02 */	{ "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel",	0, 1, 1, 1 },
-/* 0x03 */	{ "i.MX515@800MHz, PHY, Ext. Eth, Accel",		0, 1, 1, 0 },
-/* 0x04 */	{ "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel",	1, 1, 1, 1 },
-/* 0x05 */	{ "i.MX515@600MHz, PHY, Ext. Eth, Accel",		1, 1, 1, 0 },
-/* 0x06 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x07 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
-/* 0x08 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x09 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
-/* 0x0a */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		1, 1, 0, 1 },
-/* 0x0b */	{ "i.MX515@600MHz, PHY, Accel",				1, 1, 0, 0 },
-/* 0x0c */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x0d */	{ "i.MX512@800MHz",					0, 0, 0, 0 },
-/* 0x0e */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		0, 1, 0, 1 },
-/* 0x0f */	{ "i.MX515@600MHz, PHY, Accel",				1, 1, 0, 0 },
-/* 0x10 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		1, 1, 0, 1 },
-/* 0x11 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
-/* 0x12 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		1, 1, 0, 1 },
-/* 0x13 */	{ "i.MX515@800MHz, PHY, Accel",				0, 1, 0, 0 },
+/* 0x00 */	{ "Unknown",						0,       0, 0, 0, 0 },
+/* 0x01 */	{ "Not supported",					0,       0, 0, 0, 0 },
+/* 0x02 */	{ "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel",	SZ_512M, 0, 1, 1, 1 },
+/* 0x03 */	{ "i.MX515@800MHz, PHY, Ext. Eth, Accel",		SZ_512M, 0, 1, 1, 0 },
+/* 0x04 */	{ "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel",	SZ_512M, 1, 1, 1, 1 },
+/* 0x05 */	{ "i.MX515@600MHz, PHY, Ext. Eth, Accel",		SZ_512M, 1, 1, 1, 0 },
+/* 0x06 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_512M, 0, 1, 0, 1 },
+/* 0x07 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_512M, 0, 1, 0, 0 },
+/* 0x08 */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_256M, 0, 1, 0, 1 },
+/* 0x09 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_256M, 0, 1, 0, 0 },
+/* 0x0a */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		SZ_256M, 1, 1, 0, 1 },
+/* 0x0b */	{ "i.MX515@600MHz, PHY, Accel",				SZ_256M, 1, 1, 0, 0 },
+/* 0x0c */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_128M, 0, 1, 0, 1 },
+/* 0x0d */	{ "i.MX512@800MHz",					SZ_128M, 0, 0, 0, 0 },
+/* 0x0e */	{ "i.MX515@800MHz, Wireless, PHY, Accel",		SZ_512M, 0, 1, 0, 1 },
+/* 0x0f */	{ "i.MX515@600MHz, PHY, Accel",				SZ_128M, 1, 1, 0, 0 },
+/* 0x10 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		SZ_128M, 1, 1, 0, 1 },
+/* 0x11 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_128M, 0, 1, 0, 0 },
+/* 0x12 */	{ "i.MX515@600MHz, Wireless, PHY, Accel",		SZ_512M, 1, 1, 0, 1 },
+/* 0x13 */	{ "i.MX515@800MHz, PHY, Accel",				SZ_512M, 0, 1, 0, 0 },
 };
 
 struct ccxmx51_ident *ccxmx51_id;
@@ -339,6 +340,26 @@
 	return 0;
 }
 
+/*
+ * On this board the SDRAM is always configured for 512Mib. The real
+ * size is determined by the board id read from the IIM module.
+ */
+static int ccxmx51_sdram_fixup(void)
+{
+	imx_esdctl_disable();
+
+	return 0;
+}
+postcore_initcall(ccxmx51_sdram_fixup);
+
+static int ccxmx51_memory_init(void)
+{
+	arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, SZ_128M);
+
+	return 0;
+}
+mem_initcall(ccxmx51_memory_init);
+
 static int ccxmx51_devices_init(void)
 {
 	u8 hwid[6];
@@ -368,6 +389,8 @@
 			break;
 		}
 		printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]);
+		if ((ccxmx51_id->mem_sz - SZ_128M) > 0)
+			arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M);
 	}
 
 	imx51_add_uart1();
diff --git a/arch/arm/boards/ccxmx51/ccxmx51.h b/arch/arm/boards/ccxmx51/ccxmx51.h
index ef40b7f..3feacac 100644
--- a/arch/arm/boards/ccxmx51/ccxmx51.h
+++ b/arch/arm/boards/ccxmx51/ccxmx51.h
@@ -23,6 +23,7 @@
 
 struct ccxmx51_ident {
 	const char	*id_string;
+	const int	mem_sz;
 	const char	industrial;
 	const char	eth0;
 	const char	eth1;
diff --git a/arch/arm/boards/ccxmx51/lowlevel.c b/arch/arm/boards/ccxmx51/lowlevel.c
index 3e6a0ee..9519b77 100644
--- a/arch/arm/boards/ccxmx51/lowlevel.c
+++ b/arch/arm/boards/ccxmx51/lowlevel.c
@@ -1,9 +1,11 @@
 #include <common.h>
 #include <mach/esdctl.h>
+#include <asm/barebox-arm.h>
 #include <asm/barebox-arm-head.h>
+#include <mach/imx51-regs.h>
 
 void __naked barebox_arm_reset_vector(void)
 {
 	arm_cpu_lowlevel_init();
-	imx51_barebox_entry(0);
+	barebox_arm_entry(MX51_CSD0_BASE_ADDR, SZ_128M, 0);
 }
diff --git a/arch/arm/boards/guf-vincell/lowlevel.c b/arch/arm/boards/guf-vincell/lowlevel.c
index ee7aafd..534e506 100644
--- a/arch/arm/boards/guf-vincell/lowlevel.c
+++ b/arch/arm/boards/guf-vincell/lowlevel.c
@@ -132,7 +132,7 @@
 	/* Skip SDRAM initialization if we run from RAM */
 	r = get_pc();
 	if (r > 0x70000000 && r < 0xf0000000)
-		imx51_barebox_entry(0);
+		imx53_barebox_entry(0);
 
 	/* Setup a preliminary stack */
 	r = 0xf8000000 + 0x60000 - 16;
@@ -146,5 +146,5 @@
 
 	imx_esdctlv4_init();
 
-	imx51_barebox_entry(0);
+	imx53_barebox_entry(0);
 }
diff --git a/arch/arm/boards/sama5d3xek/env/config b/arch/arm/boards/sama5d3xek/env/config
index 375e90d..a7fd930 100644
--- a/arch/arm/boards/sama5d3xek/env/config
+++ b/arch/arm/boards/sama5d3xek/env/config
@@ -32,7 +32,7 @@
 
 nand_device=atmel_nand
 nand_parts="256k(at91bootstrap),384k(barebox)ro,256k@768k(bareboxenv),256k(bareboxenv2),128k@1536k(oftree),5M@2M(kernel),-@8M(rootfs)"
-rootfs_mtdblock_nand=7
+rootfs_mtdblock_nand=6
 
 m25p80_parts="64k(bootstrap),384k(barebox),256k(bareboxenv),256k(bareboxenv2),128k(oftree),-(updater)"
 
diff --git a/arch/arm/boards/tqma53/env/config-board b/arch/arm/boards/tqma53/env/config-board
index 4776438..28d015e 100644
--- a/arch/arm/boards/tqma53/env/config-board
+++ b/arch/arm/boards/tqma53/env/config-board
@@ -4,4 +4,4 @@
 # instead
 
 global.hostname=tqma53
-global.linux.bootargs.base="console=ttymxc0,115200"
+global.linux.bootargs.base="console=ttymxc1,115200"
diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 13542d9..c19618b 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -34,7 +34,10 @@
 
 .section .text.v7_mmu_cache_off
 ENTRY(v7_mmu_cache_off)
-		stmfd	sp!, {r0-r7, r9-r11}
+		/* although 'r12' is an eabi scratch register which does
+		   not need to be restored, save it to ensure an 8-byte
+	           stack alignment */
+		stmfd	sp!, {r4-r12, lr}
 		mrc	p15, 0, r0, c1, c0
 #ifdef CONFIG_MMU
 		bic	r0, r0, #0x000d
@@ -42,7 +45,6 @@
 		bic	r0, r0, #0x000c
 #endif
 		mcr	p15, 0, r0, c1, c0	@ turn MMU and cache off
-		mov	r12, lr
 		bl	v7_mmu_cache_flush
 		mov	r0, #0
 #ifdef CONFIG_MMU
@@ -51,35 +53,44 @@
 		mcr	p15, 0, r0, c7, c5, 6	@ invalidate BTC
 		mcr	p15, 0, r0, c7, c10, 4	@ DSB
 		mcr	p15, 0, r0, c7, c5, 4	@ ISB
-		ldmfd	sp!, {r0-r7, r9-r11}
-		mov	pc, r12
+		ldmfd	sp!, {r4-r12, pc}
 ENDPROC(v7_mmu_cache_off)
 
-.section .text.v7_mmu_cache_flush
+.section .text.v7_mmu_cache_flush_invalidate
+ENTRY(v7_mmu_cache_invalidate)
+		mov	r0, #1
+		b	__v7_mmu_cache_flush_invalidate
+ENDPROC(v7_mmu_cache_invalidate)
+
 ENTRY(v7_mmu_cache_flush)
-		stmfd	sp!, {r10, lr}
-		mrc	p15, 0, r10, c0, c1, 5	@ read ID_MMFR1
-		tst	r10, #0xf << 16		@ hierarchical cache (ARMv7)
-		mov	r10, #0
+		mov	r0, #0
+		b	__v7_mmu_cache_flush_invalidate
+ENDPROC(v7_mmu_cache_flush)
+
+ENTRY(__v7_mmu_cache_flush_invalidate)
+		mrc	p15, 0, r12, c0, c1, 5	@ read ID_MMFR1
+		tst	r12, #0xf << 16		@ hierarchical cache (ARMv7)
+		mov	r12, #0
 		beq	hierarchical
-		mcr	p15, 0, r10, c7, c14, 0	@ clean+invalidate D
+		mcr	p15, 0, r12, c7, c14, 0	@ clean+invalidate D
 		b	iflush
 hierarchical:
-		mcr	p15, 0, r10, c7, c10, 5	@ DMB
-		stmfd	sp!, {r0-r7, r9-r11}
+		stmfd	sp!, {r4-r11}
+		mov	r8, r0
+		mcr	p15, 0, r12, c7, c10, 5	@ DMB
 		mrc	p15, 1, r0, c0, c0, 1	@ read clidr
 		ands	r3, r0, #0x7000000	@ extract loc from clidr
 		mov	r3, r3, lsr #23		@ left align loc bit field
 		beq	finished		@ if loc is 0, then no need to clean
-		mov	r10, #0			@ start clean at cache level 0
+		mov	r12, #0			@ start clean at cache level 0
 loop1:
-		add	r2, r10, r10, lsr #1	@ work out 3x current cache level
+		add	r2, r12, r12, lsr #1	@ work out 3x current cache level
 		mov	r1, r0, lsr r2		@ extract cache type bits from clidr
 		and	r1, r1, #7		@ mask of the bits for current cache only
 		cmp	r1, #2			@ see what cache we have at this level
 		blt	skip			@ skip if no cache, or just i-cache
-		mcr	p15, 2, r10, c0, c0, 0	@ select current cache level in cssr
-		mcr	p15, 0, r10, c7, c5, 4	@ isb to sych the new cssr&csidr
+		mcr	p15, 2, r12, c0, c0, 0	@ select current cache level in cssr
+		mcr	p15, 0, r12, c7, c5, 4	@ isb to sych the new cssr&csidr
 		mrc	p15, 1, r1, c0, c0, 0	@ read the new csidr
 		and	r2, r1, #7		@ extract the length of the cache lines
 		add	r2, r2, #4		@ add 4 (line length offset)
@@ -91,32 +102,35 @@
 loop2:
 		mov	r9, r4			@ create working copy of max way size
 loop3:
-ARM(		orr	r11, r10, r9, lsl r5	) @ factor way and cache number into r11
+ARM(		orr	r11, r12, r9, lsl r5	) @ factor way and cache number into r11
 ARM(		orr	r11, r11, r7, lsl r2	) @ factor index number into r11
 THUMB(		lsl	r6, r9, r5		)
-THUMB(		orr	r11, r10, r6		) @ factor way and cache number into r11
+THUMB(		orr	r11, r12, r6		) @ factor way and cache number into r11
 THUMB(		lsl	r6, r7, r2		)
 THUMB(		orr	r11, r11, r6		) @ factor index number into r11
-		mcr	p15, 0, r11, c7, c14, 2	@ clean & invalidate by set/way
+		cmp	r8, #0
+THUMB(		ite	eq			)
+		mcreq	p15, 0, r11, c7, c14, 2	@ clean & invalidate by set/way
+		mcrne	p15, 0, r11, c7, c6, 2	@ invalidate by set/way
 		subs	r9, r9, #1		@ decrement the way
 		bge	loop3
 		subs	r7, r7, #1		@ decrement the index
 		bge	loop2
 skip:
-		add	r10, r10, #2		@ increment cache number
-		cmp	r3, r10
+		add	r12, r12, #2		@ increment cache number
+		cmp	r3, r12
 		bgt	loop1
 finished:
-		ldmfd	sp!, {r0-r7, r9-r11}
-		mov	r10, #0			@ switch back to cache level 0
-		mcr	p15, 2, r10, c0, c0, 0	@ select current cache level in cssr
+		ldmfd	sp!, {r4-r11}
+		mov	r12, #0			@ switch back to cache level 0
+		mcr	p15, 2, r12, c0, c0, 0	@ select current cache level in cssr
 iflush:
-		mcr	p15, 0, r10, c7, c10, 4	@ DSB
-		mcr	p15, 0, r10, c7, c5, 0	@ invalidate I+BTB
-		mcr	p15, 0, r10, c7, c10, 4	@ DSB
-		mcr	p15, 0, r10, c7, c5, 4	@ ISB
-		ldmfd	sp!, {r10, pc}
-ENDPROC(v7_mmu_cache_flush)
+		mcr	p15, 0, r12, c7, c10, 4	@ DSB
+		mcr	p15, 0, r12, c7, c5, 0	@ invalidate I+BTB
+		mcr	p15, 0, r12, c7, c10, 4	@ DSB
+		mcr	p15, 0, r12, c7, c5, 4	@ ISB
+		mov	pc, lr
+ENDPROC(__v7_mmu_cache_flush_invalidate)
 
 /*
  * cache_line_size - get the cache line size from the CSIDR register
diff --git a/arch/arm/cpu/cache.c b/arch/arm/cpu/cache.c
index 95c8338..7aab55b 100644
--- a/arch/arm/cpu/cache.c
+++ b/arch/arm/cpu/cache.c
@@ -134,3 +134,24 @@
 #endif
 	}
 }
+
+void v7_mmu_cache_invalidate(void);
+
+void arm_early_mmu_cache_invalidate(void)
+{
+	switch (arm_early_get_cpu_architecture()) {
+	case CPU_ARCH_ARMv4T:
+	case CPU_ARCH_ARMv5:
+	case CPU_ARCH_ARMv5T:
+	case CPU_ARCH_ARMv5TE:
+	case CPU_ARCH_ARMv5TEJ:
+	case CPU_ARCH_ARMv6:
+		asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
+		return;
+#ifdef CONFIG_CPU_32v7
+	case CPU_ARCH_ARMv7:
+		v7_mmu_cache_invalidate();
+		return;
+#endif
+	}
+}
diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c
index 6f03c4a..3ef0118 100644
--- a/arch/arm/cpu/start-pbl.c
+++ b/arch/arm/cpu/start-pbl.c
@@ -59,6 +59,8 @@
 
 	endmem -= STACK_SIZE; /* stack */
 
+	arm_early_mmu_cache_invalidate();
+
 	if (IS_ENABLED(CONFIG_PBL_RELOCATABLE))
 		relocate_to_current_adr();
 
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 580c1fe..5a3c629 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -124,6 +124,8 @@
 {
 	arm_setup_stack(membase + memsize - 16);
 
+	arm_early_mmu_cache_invalidate();
+
 	__start(membase, memsize, boarddata);
 }
 #else
diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h
index 9385415..9a8cc87 100644
--- a/arch/arm/include/asm/barebox-arm-head.h
+++ b/arch/arm/include/asm/barebox-arm-head.h
@@ -22,7 +22,7 @@
 
 #if __LINUX_ARM_ARCH__ >= 6
 	r |= CR_U;
-	r &= CR_A;
+	r &= ~CR_A;
 #else
 	r |= CR_A;
 #endif
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index e5621eb..f5f8bf3 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -10,10 +10,15 @@
 
 #ifdef CONFIG_MMU
 void arm_early_mmu_cache_flush(void);
+void arm_early_mmu_cache_invalidate(void);
 #else
 static inline void arm_early_mmu_cache_flush(void)
 {
 }
+
+static inline void arm_early_mmu_cache_invalidate(void)
+{
+}
 #endif
 
 #endif
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 5e35d7f..c4d2672 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -14,31 +14,15 @@
 
 	.text
 	.align	5
-	.word	0
-
-1:	subs	r2, r2, #4		@ 1 do we have enough
-	blt	5f			@ 1 bytes to align with?
-	cmp	r3, #2			@ 1
-	strltb	r1, [ip], #1		@ 1
-	strleb	r1, [ip], #1		@ 1
-	strb	r1, [ip], #1		@ 1
-	add	r2, r2, r3		@ 1 (r2 = r2 - (4 - r3))
-/*
- * The pointer is now aligned and the length is adjusted.  Try doing the
- * memset again.
- */
 
 ENTRY(memset)
-/*
- * Preserve the contents of r0 for the return value.
- */
-	mov	ip, r0
-	ands	r3, ip, #3		@ 1 unaligned?
-	bne	1b			@ 1
+	ands	r3, r0, #3		@ 1 unaligned?
+	mov	ip, r0			@ preserve r0 as return value
+	bne	6f			@ 1
 /*
  * we know that the pointer in ip is aligned to a word boundary.
  */
-	orr	r1, r1, r1, lsl #8
+1:	orr	r1, r1, r1, lsl #8
 	orr	r1, r1, r1, lsl #16
 	mov	r3, r1
 	cmp	r2, #16
@@ -127,5 +111,14 @@
 	tst	r2, #1
 	strneb	r1, [ip], #1
 	mov	pc, lr
+
+6:	subs	r2, r2, #4		@ 1 do we have enough
+	blt	5b			@ 1 bytes to align with?
+	cmp	r3, #2			@ 1
+	strltb	r1, [ip], #1		@ 1
+	strleb	r1, [ip], #1		@ 1
+	strb	r1, [ip], #1		@ 1
+	add	r2, r2, r3		@ 1 (r2 = r2 - (4 - r3))
+	b	1b
 ENDPROC(memset)
 
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index cb57d45..e2025b3 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -39,6 +39,17 @@
 	void (*add_mem)(void *esdctlbase, struct imx_esdctl_data *);
 };
 
+static int imx_esdctl_disabled;
+
+/*
+ * Boards can disable SDRAM detection if it doesn't work for them. In
+ * this case arm_add_mem_device has to be called by board code.
+ */
+void imx_esdctl_disable(void)
+{
+	imx_esdctl_disabled = 1;
+}
+
 /*
  * v1 - found on i.MX1
  */
@@ -239,6 +250,9 @@
 	if (!base)
 		return -ENOMEM;
 
+	if (imx_esdctl_disabled)
+		return 0;
+
 	data->add_mem(base, data);
 
 	return 0;
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 26436d9..b7219d9 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -136,6 +136,7 @@
 void __naked __noreturn imx51_barebox_entry(uint32_t boarddata);
 void __naked __noreturn imx53_barebox_entry(uint32_t boarddata);
 void __naked __noreturn imx6_barebox_entry(uint32_t boarddata);
+void imx_esdctl_disable(void);
 #endif
 
 #endif /* __MACH_ESDCTL_V2_H */
diff --git a/arch/arm/mach-mxs/imx.c b/arch/arm/mach-mxs/imx.c
index cdf9275..fcb26f7 100644
--- a/arch/arm/mach-mxs/imx.c
+++ b/arch/arm/mach-mxs/imx.c
@@ -101,6 +101,7 @@
 		case 0x3: revision = SILICON_REVISION_1_3; break;
 		case 0x4: revision = SILICON_REVISION_1_4; break;
 		}
+		break;
 	case HW_DIGCTL_CHIPID_MX28:
 		product = "i.MX28";
 		switch (rev) {
diff --git a/common/Makefile b/common/Makefile
index dcb07c2..83c29d0 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -101,6 +101,8 @@
 $(obj)/barebox_default_env.lzo: $(obj)/barebox_default_env FORCE
 	$(call if_changed,lzo)
 
+targets += barebox_default_env.lzo barebox_default_env.bz2 barebox_default_env.gz
+
 quiet_cmd_env_h = ENVH    $@
 cmd_env_h = cat $< | (cd $(obj) && $(objtree)/scripts/bin2c default_environment) > $@; \
 	echo "const int default_environment_uncompress_size=`stat -c%s $(obj)/barebox_default_env`;" >> $@
diff --git a/defaultenv-2/menu/menu/settings b/defaultenv-2/menu/menu/settings
index 3b95d4c..db619af 100644
--- a/defaultenv-2/menu/menu/settings
+++ b/defaultenv-2/menu/menu/settings
@@ -7,7 +7,7 @@
 
 	menu -e -a -R -m settings -c "$global.editcmd /env/network/eth0" -d "Network settings"
 	menu -e -a -R -m settings -c "$global.editcmd /env/config" -d "Config settings"
-	menu -e -a -m settings -c "settings-entries-edit" -d "Edit settings entries"
+	menu -e -a -m settings -c "boot-entries-edit" -d "Edit boot entries"
 	menu -e -a -m settings -c "init-entries-edit" -d "Edit init entries"
 	menu -e -a -R -m settings -c "saveenv || echo \"failed to save environment\" && sleep 2" -d "Save settings"
 	menu -e -a -m settings -c "menu_exit=true" -d "back"
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index db422a4..a3ec576 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -489,8 +489,7 @@
 	}
 
 	of_write_number(&fdt_res->address, (unsigned long)__fdt, 2);
-	of_write_number(&fdt_res->size, (unsigned long)__fdt +
-			be32_to_cpu(fdt->totalsize), 2);
+	of_write_number(&fdt_res->size, be32_to_cpu(fdt->totalsize), 2);
 	fdt_res++;
 
 	of_write_number(&fdt_res->address, 0, 2);
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index a95bbe4..4ef2c56 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -233,7 +233,7 @@
 	$(call echo-cmd,checksrc) $(cmd_checksrc)			  \
 	$(call echo-cmd,pbl_cc_o_c) $(cmd_pbl_cc_o_c);			  \
 	$(cmd_modversions)						  \
-	scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,pbl_cc__o_c)' >    \
+	scripts/basic/fixdep $(depfile) $@ '$(call make-cmd,pbl_cc_o_c)' >    \
 	                                              $(dot-target).tmp;  \
 	rm -f $(depfile);						  \
 	mv -f $(dot-target).tmp $(dot-target).cmd