diff --git a/drivers/hab/habv3.c b/drivers/hab/habv3.c index 82ae245..47d3caf 100644 --- a/drivers/hab/habv3.c +++ b/drivers/hab/habv3.c @@ -78,5 +78,9 @@ int imx25_hab_get_status(void) { + if (!cpu_is_mx25()) + return 0; + return imx_habv3_get_status(readl(IOMEM(0x780018d4))); } +postmmu_initcall(imx25_hab_get_status); diff --git a/drivers/hab/habv4.c b/drivers/hab/habv4.c index aa9506c..ca95c01 100644 --- a/drivers/hab/habv4.c +++ b/drivers/hab/habv4.c @@ -20,6 +20,7 @@ #include #include +#include #include #include @@ -501,9 +502,54 @@ return -EINVAL; } +static int init_imx6_hab_get_status(void) +{ + int ret = 0; + + if (!cpu_is_mx6()) + /* can happen in multi-image builds and is not an error */ + return 0; + + ret = imx6_hab_get_status(); + + /* + * Nobody will check the return value if there were HAB errors, but the + * initcall will fail spectaculously with a strange error message. + */ + if (ret == -EPERM) + return 0; + return ret; +} + +/* + * Need to run before MMU setup because i.MX6 ROM code is mapped near 0x0, + * which will no longer be accessible when the MMU sets the zero page to + * faulting. + */ +postconsole_initcall(init_imx6_hab_get_status); + int imx28_hab_get_status(void) { const struct habv4_rvt *rvt = (void *)HABV4_RVT_IMX28; return habv4_get_status(rvt); } + +static int init_imx28_hab_get_status(void) +{ + int ret = 0; + + if (!cpu_is_mx28()) + /* can happen in multi-image builds and is not an error */ + return 0; + + ret = imx28_hab_get_status(); + + /* nobody will check the return value if there were HAB errors, but the + * initcall will fail spectaculously with a strange error message. */ + if (ret == -EPERM) + return 0; + return ret; +} +/* i.MX28 ROM code can be run after MMU setup to make use of caching */ +postmmu_initcall(init_imx28_hab_get_status);