diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index d6011ad..456e6fe 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/ obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/ obj-$(CONFIG_MACH_NXDB500) += netx/ +obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += nxp-imx6ull-evk/ obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/ obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/ obj-$(CONFIG_MACH_PANDA) += panda/ diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c index f75c9d1..0b1c927 100644 --- a/arch/arm/boards/freescale-mx53-qsb/board.c +++ b/arch/arm/boards/freescale-mx53-qsb/board.c @@ -64,15 +64,6 @@ loco_system_rev = (loco_system_rev & ~(0xF << 8)) | (rev & 0xF) << 8; } -#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) - -static void loco_fec_reset(void) -{ - gpio_direction_output(LOCO_FEC_PHY_RST, 0); - mdelay(1); - gpio_set_value(LOCO_FEC_PHY_RST, 1); -} - #define MX53_LOCO_USB_PWREN IMX_GPIO_NR(7, 8) static int loco_late_init(void) @@ -148,8 +139,6 @@ gpio_direction_output(MX53_LOCO_USB_PWREN, 0); gpio_set_value(MX53_LOCO_USB_PWREN, 1); - loco_fec_reset(); - set_silicon_rev(imx_silicon_revision()); armlinux_set_architecture(MACH_TYPE_MX53_LOCO); diff --git a/arch/arm/boards/nxp-imx6ull-evk/Makefile b/arch/arm/boards/nxp-imx6ull-evk/Makefile new file mode 100644 index 0000000..01c7a25 --- /dev/null +++ b/arch/arm/boards/nxp-imx6ull-evk/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/nxp-imx6ull-evk/board.c b/arch/arm/boards/nxp-imx6ull-evk/board.c new file mode 100644 index 0000000..a0ca268 --- /dev/null +++ b/arch/arm/boards/nxp-imx6ull-evk/board.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#include +#include +#include +#include + +#include + +static int ksz8081_phy_fixup(struct phy_device *dev) +{ + phy_write(dev, 0x1f, 0x8190); + phy_write(dev, 0x16, 0x202); + + return 0; +} + +static int nxp_imx6ull_evk_init(void) +{ + if (!of_machine_is_compatible("fsl,imx6ull-14x14-evk")) + return 0; + + phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK, + ksz8081_phy_fixup); + + imx6_bbu_internal_mmc_register_handler("mmc", "/dev/mmc1.barebox", + BBU_HANDLER_FLAG_DEFAULT); + + barebox_set_hostname("imx6ull-evk"); + + return 0; +} +device_initcall(nxp_imx6ull_evk_init); diff --git a/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg new file mode 100644 index 0000000..a507ab3 --- /dev/null +++ b/arch/arm/boards/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Values taken from U-Boot-2017.07-rc1 + * + */ + +loadaddr 0x80000000 +soc imx6 +dcdofs 0x400 + +/* Enable all clocks */ +wm 32 0x020c4068 0xffffffff +wm 32 0x020c406c 0xffffffff +wm 32 0x020c4070 0xffffffff +wm 32 0x020c4074 0xffffffff +wm 32 0x020c4078 0xffffffff +wm 32 0x020c407c 0xffffffff +wm 32 0x020c4080 0xffffffff + +wm 32 0x020e04b4 0x000c0000 +wm 32 0x020e04ac 0x00000000 +wm 32 0x020e027c 0x00000030 +wm 32 0x020e0250 0x00000030 +wm 32 0x020e024c 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e0288 0x000c0030 +wm 32 0x020e0270 0x00000000 +wm 32 0x020e0260 0x00000030 +wm 32 0x020e0264 0x00000030 +wm 32 0x020e04a0 0x00000030 +wm 32 0x020e0494 0x00020000 +wm 32 0x020e0280 0x00000030 +wm 32 0x020e0284 0x00000030 +wm 32 0x020e04b0 0x00020000 +wm 32 0x020e0498 0x00000030 +wm 32 0x020e04a4 0x00000030 +wm 32 0x020e0244 0x00000030 +wm 32 0x020e0248 0x00000030 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b080c 0x00000004 +wm 32 0x021b083c 0x41640158 +wm 32 0x021b0848 0x40403237 +wm 32 0x021b0850 0x40403c33 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b082c 0xf3333333 +wm 32 0x021b0830 0xf3333333 +wm 32 0x021b08c0 0x00944009 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b0004 0x0002002d +wm 32 0x021b0008 0x1b333030 +wm 32 0x021b000c 0x676b52f3 +wm 32 0x021b0010 0xb66d0b63 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b0018 0x00201740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x006b1023 +wm 32 0x021b0040 0x0000004f +wm 32 0x021b0000 0x84180000 +wm 32 0x021b0890 0x00400000 +wm 32 0x021b001c 0x02008032 +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x15208030 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b0020 0x00000800 +wm 32 0x021b0818 0x00000227 +wm 32 0x021b0004 0x0002552d +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c new file mode 100644 index 0000000..bb2e362 --- /dev/null +++ b/arch/arm/boards/nxp-imx6ull-evk/lowlevel.c @@ -0,0 +1,74 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); + void __iomem *uart = IOMEM(MX6_UART1_BASE_ADDR); + + imx6_ungate_all_peripherals(); + + writel(0x0, iomuxbase + 0x84); + writel(0x1b0b1, iomuxbase + 0x0310); + + writel(0x0, iomuxbase + 0x88); + writel(0x1b0b0, iomuxbase + 0x0314); + + writel(0x3, iomuxbase + 0x624); + + imx6_uart_setup(uart); + + pbl_set_putc(imx_uart_putc, uart); + + putc_ll('>'); +} + +extern char __dtb_imx6ull_14x14_evk_start[]; + +static noinline void nxp_imx6_ull(void) +{ + imx6ul_barebox_entry(__dtb_imx6ull_14x14_evk_start); +} + +ENTRY_FUNCTION(start_nxp_imx6ull_evk, r0, r1, r2) +{ + + imx6ul_cpu_lowlevel_init(); + + arm_setup_stack(0x00910000 - 8); + + arm_early_mmu_cache_invalidate(); + + relocate_to_current_adr(); + setup_c(); + + setup_uart(); + + /* disable all watchdog powerdown counters */ + writew(0x0, IOMEM(MX6_WDOG1_BASE_ADDR + 0x8)); + writew(0x0, IOMEM(MX6_WDOG2_BASE_ADDR + 0x8)); + writew(0x0, IOMEM(MX6ULL_WDOG3_BASE_ADDR + 0x8)); + + nxp_imx6_ull(); +} diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c index 07ac443..29811d3 100644 --- a/arch/arm/boards/phytec-som-imx6/lowlevel.c +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -56,7 +56,7 @@ if (cpu_type == IMX6_CPUTYPE_IMX6UL || cpu_type == IMX6_CPUTYPE_IMX6ULL) { - arm_cpu_lowlevel_init(); + imx6ul_cpu_lowlevel_init(); /* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */ arm_setup_stack(0x00910000 - 8); } else { diff --git a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c index aad5512..f351e67 100644 --- a/arch/arm/boards/technexion-pico-hobbit/lowlevel.c +++ b/arch/arm/boards/technexion-pico-hobbit/lowlevel.c @@ -37,7 +37,7 @@ { void *fdt; - arm_cpu_lowlevel_init(); + imx6ul_cpu_lowlevel_init(); arm_setup_stack(0x00910000 - 8); diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S index aaa8bf8..7a1c5c0 100644 --- a/arch/arm/cpu/cache-armv7.S +++ b/arch/arm/cpu/cache-armv7.S @@ -9,7 +9,7 @@ mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 tst r11, #0xf @ VMSA mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + dsb @ drain write buffer tst r11, #0xf @ VMSA mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs #endif @@ -24,11 +24,11 @@ movne r1, #-1 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control #endif - mcr p15, 0, r0, c7, c5, 4 @ ISB + isb mcr p15, 0, r0, c1, c0, 0 @ load control register mrc p15, 0, r0, c1, c0, 0 @ and read it back mov r0, #0 - mcr p15, 0, r0, c7, c5, 4 @ ISB + isb ldmfd sp!, {r11, pc} ENDPROC(v7_mmu_cache_on) @@ -51,8 +51,8 @@ mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB #endif mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c5, 4 @ ISB + dsb + isb ldmfd sp!, {r4-r12, pc} ENDPROC(v7_mmu_cache_off) @@ -68,7 +68,7 @@ ENDPROC(v7_mmu_cache_flush) ENTRY(__v7_mmu_cache_flush_invalidate) - mcr p15, 0, r12, c7, c10, 5 @ DMB + dmb mrc p15, 0, r12, c0, c1, 5 @ read ID_MMFR1 tst r12, #0xf << 16 @ hierarchical cache (ARMv7) mov r12, #0 @@ -78,7 +78,7 @@ hierarchical: stmfd sp!, {r4-r11} mov r8, r0 - mcr p15, 0, r12, c7, c10, 5 @ DMB + dmb mrc p15, 1, r0, c0, c0, 1 @ read clidr ands r3, r0, #0x7000000 @ extract loc from clidr mov r3, r3, lsr #23 @ left align loc bit field @@ -91,7 +91,7 @@ cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache mcr p15, 2, r12, c0, c0, 0 @ select current cache level in cssr - mcr p15, 0, r12, c7, c5, 4 @ isb to sych the new cssr&csidr + isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) @@ -126,10 +126,10 @@ mov r12, #0 @ switch back to cache level 0 mcr p15, 2, r12, c0, c0, 0 @ select current cache level in cssr iflush: - mcr p15, 0, r12, c7, c10, 4 @ DSB + dsb mcr p15, 0, r12, c7, c5, 0 @ invalidate I+BTB - mcr p15, 0, r12, c7, c10, 4 @ DSB - mcr p15, 0, r12, c7, c5, 4 @ ISB + dsb + isb mov pc, lr ENDPROC(__v7_mmu_cache_flush_invalidate) diff --git a/arch/arm/cpu/common.c b/arch/arm/cpu/common.c index dcd8f0b..7d74996 100644 --- a/arch/arm/cpu/common.c +++ b/arch/arm/cpu/common.c @@ -63,7 +63,7 @@ memset(dynsym, 0, (unsigned long)dynend - (unsigned long)dynsym); arm_early_mmu_cache_flush(); - flush_icache(); + icache_invalidate(); } #ifdef ARM_MULTIARCH diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c index b480463..bf604fd 100644 --- a/arch/arm/cpu/cpu.c +++ b/arch/arm/cpu/cpu.c @@ -103,7 +103,7 @@ #ifdef CONFIG_MMU mmu_disable(); #endif - flush_icache(); + icache_invalidate(); #if __LINUX_ARM_ARCH__ <= 7 /* diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S index e5baa12..7696a19 100644 --- a/arch/arm/cpu/lowlevel.S +++ b/arch/arm/cpu/lowlevel.S @@ -58,3 +58,10 @@ mov pc, r2 ENDPROC(arm_cpu_lowlevel_init) + +ENTRY(cortex_a7_lowlevel_init) + mrc p15, 0, r12, c1, c0, 1 + orr r12, r12, #(1 << 6) /* Enable SMP for cortex-a7 to make caches work */ + mcr p15, 0, r12, c1, c0, 1 + mov pc, lr +ENDPROC(cortex_a7_lowlevel_init) diff --git a/arch/arm/cpu/start-pbl.c b/arch/arm/cpu/start-pbl.c index 5f1469b..e851b4a 100644 --- a/arch/arm/cpu/start-pbl.c +++ b/arch/arm/cpu/start-pbl.c @@ -93,7 +93,7 @@ pbl_barebox_uncompress((void*)barebox_base, (void *)pg_start, pg_len); arm_early_mmu_cache_flush(); - flush_icache(); + icache_invalidate(); if (IS_ENABLED(CONFIG_THUMB2_BAREBOX)) barebox = (void *)(barebox_base + 1); diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c index eeb5a65..9d7fe0e 100644 --- a/arch/arm/cpu/uncompress.c +++ b/arch/arm/cpu/uncompress.c @@ -100,7 +100,7 @@ pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len); arm_early_mmu_cache_flush(); - flush_icache(); + icache_invalidate(); if (IS_ENABLED(CONFIG_THUMB2_BAREBOX)) barebox = (void *)(barebox_base + 1); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b5601a6..4f13d4e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -80,6 +80,7 @@ imx6q-h100.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += imx6ul-pico-hobbit.dtb.o +pbl-dtb-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += imx6ull-14x14-evk.dtb.o pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-dtb-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts new file mode 100644 index 0000000..9afe640 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -0,0 +1,29 @@ +#include + +/{ + chosen { + environment@0 { + compatible = "barebox,environment"; + device-path = &environment_usdhc2; + }; + }; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0xc0000>; + }; + + environment_usdhc2: partition@c0000 { + label = "barebox-environment"; + reg = <0xc0000 0x40000>; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec1 0x620 &fec2 0x632>; +}; diff --git a/arch/arm/include/asm/barebox-arm-head.h b/arch/arm/include/asm/barebox-arm-head.h index 0a2eb6b..bd9c9b1 100644 --- a/arch/arm/include/asm/barebox-arm-head.h +++ b/arch/arm/include/asm/barebox-arm-head.h @@ -6,6 +6,7 @@ #ifndef __ASSEMBLY__ void arm_cpu_lowlevel_init(void); +void cortex_a7_lowlevel_init(void); /* * 32 bytes at this offset is reserved in the barebox head for board/SoC diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 8fcdb64..b5460a7 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -6,7 +6,7 @@ extern void v8_dcache_all(void); #endif -static inline void flush_icache(void) +static inline void icache_invalidate(void) { #if __LINUX_ARM_ARCH__ <= 7 asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 92440e3..1578875 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -414,6 +414,10 @@ https://goo.gl/6EKGdk +config MACH_NXP_IMX6ULL_EVK + bool "NXP i.MX6ull EVK Board" + select ARCH_IMX6UL + endif # ---------------------------------------------------------- diff --git a/arch/arm/mach-imx/cpu_init.c b/arch/arm/mach-imx/cpu_init.c index 2b388ca..6a6c4c5 100644 --- a/arch/arm/mach-imx/cpu_init.c +++ b/arch/arm/mach-imx/cpu_init.c @@ -14,6 +14,7 @@ #include #include +#include void imx5_cpu_lowlevel_init(void) { @@ -34,6 +35,12 @@ enable_arm_errata_845369_war(); } +void imx6ul_cpu_lowlevel_init(void) +{ + cortex_a7_lowlevel_init(); + arm_cpu_lowlevel_init(); +} + void imx7_cpu_lowlevel_init(void) { arm_cpu_lowlevel_init(); diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h index 73be9ce..f68dc87 100644 --- a/arch/arm/mach-imx/include/mach/generic.h +++ b/arch/arm/mach-imx/include/mach/generic.h @@ -48,6 +48,7 @@ void imx5_cpu_lowlevel_init(void); void imx6_cpu_lowlevel_init(void); +void imx6ul_cpu_lowlevel_init(void); void imx7_cpu_lowlevel_init(void); void vf610_cpu_lowlevel_init(void); diff --git a/arch/arm/mach-imx/include/mach/imx6-regs.h b/arch/arm/mach-imx/include/mach/imx6-regs.h index e661c4e..ac2aa21 100644 --- a/arch/arm/mach-imx/include/mach/imx6-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-regs.h @@ -107,6 +107,7 @@ #define MX6_MIPI_CSI2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x5C000) #define MX6_MIPI_DSI_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x60000) #define MX6_VDOA_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x64000) +#define MX6ULL_WDOG3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x64000) #define MX6_UART2_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x68000) #define MX6_UART3_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x6C000) #define MX6_UART4_BASE_ADDR (MX6_AIPS2_OFF_BASE_ADDR + 0x70000) diff --git a/images/Makefile.imx b/images/Makefile.imx index e917602..76e91eb 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -325,6 +325,11 @@ FILE_barebox-imx6ul-pico-hobbit-512mb.img = start_imx6ul_pico_hobbit_512mb.pblx.imximg image-$(CONFIG_MACH_TECHNEXION_PICO_HOBBIT) += barebox-imx6ul-pico-hobbit-512mb.img +pblx-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += start_nxp_imx6ull_evk +CFG_start_nxp_imx6ull_evk.pblx.imximg = $(board)/nxp-imx6ull-evk/flash-header-nxp-imx6ull-evk.imxcfg +FILE_barebox-nxp-imx6ull-evk.img = start_nxp_imx6ull_evk.pblx.imximg +image-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += barebox-nxp-imx6ull-evk.img + pblx-$(CONFIG_MACH_NITROGEN6) += start_imx6q_nitrogen6x_1g CFG_start_imx6q_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6/flash-header-nitrogen6q-1g.imxcfg FILE_barebox-boundarydevices-imx6q-nitrogen6x-1g.img = start_imx6q_nitrogen6x_1g.pblx.imximg diff --git a/scripts/imx/imx-usb-loader.c b/scripts/imx/imx-usb-loader.c index 1119e61..6052343 100644 --- a/scripts/imx/imx-usb-loader.c +++ b/scripts/imx/imx-usb-loader.c @@ -171,6 +171,13 @@ .max_transfer = 1024, }, { .vid = 0x15a2, + .pid = 0x0080, + .name = "i.MX6ull", + .header_type = HDR_MX53, + .mode = MODE_HID, + .max_transfer = 1024, + }, { + .vid = 0x15a2, .pid = 0x0076, .name = "i.MX7S", .header_type = HDR_MX53, @@ -628,7 +635,7 @@ break; } if ((last_trans > rem) || (last_trans > 64)) { - if ((last_trans == 64) && (cnt == rem)) { + if ((last_trans == 64) && (rem < 64)) { /* Last transfer is expected to be too large for HID */ } else { printf("err: %02x %02x %02x %02x cnt=%u rem=%d last_trans=%i\n",