diff --git a/arch/arm/boards/freescale-mx53-qsb/board.c b/arch/arm/boards/freescale-mx53-qsb/board.c index 11b4a42..38d1ee6 100644 --- a/arch/arm/boards/freescale-mx53-qsb/board.c +++ b/arch/arm/boards/freescale-mx53-qsb/board.c @@ -99,6 +99,7 @@ rev = readl(MX53_IIM_BASE_ADDR + 0x878); set_board_rev(rev); printf("MCIMX53-START-R board 1.0 rev %c\n", (rev == 1) ? 'A' : 'B' ); + barebox_set_hostname("loco-r"); armlinux_set_revision(loco_system_rev); /* Set VDDGP to 1.25V for 1GHz on SW1 */ mc13xxx_reg_read(mc34708, MC13892_REG_SW_0, &val); @@ -146,6 +147,7 @@ } else { /* so we have a DA9053 based board */ printf("MCIMX53-START board 1.0\n"); + barebox_set_hostname("loco"); armlinux_set_revision(loco_system_rev); } diff --git a/arch/arm/boards/freescale-mx53-qsb/env/config-board b/arch/arm/boards/freescale-mx53-qsb/env/config-board index a6cf69d..e8e8378 100644 --- a/arch/arm/boards/freescale-mx53-qsb/env/config-board +++ b/arch/arm/boards/freescale-mx53-qsb/env/config-board @@ -3,5 +3,4 @@ # board defaults, do not change in running system. Change /env/config # instead -global.hostname=loco global.linux.bootargs.base="console=ttymxc0,115200" diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c index e9bd168..c90f378 100644 --- a/arch/arm/boards/phytec-phyflex-imx6/board.c +++ b/arch/arm/boards/phytec-phyflex-imx6/board.c @@ -21,6 +21,7 @@ #include #include #include +#include #include @@ -43,6 +44,8 @@ eth_phy_reset(); + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + return 0; } device_initcall(phytec_pfla02_init); diff --git a/arch/arm/configs/freescale-mx53-qsb_defconfig b/arch/arm/configs/freescale-mx53-qsb_defconfig index afe8b72..8365234 100644 --- a/arch/arm/configs/freescale-mx53-qsb_defconfig +++ b/arch/arm/configs/freescale-mx53-qsb_defconfig @@ -16,6 +16,7 @@ CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y +CONFIG_BLSPEC=y CONFIG_CONSOLE_ACTIVATE_NONE=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx53-qsb/env/" @@ -25,31 +26,44 @@ CONFIG_CMD_SLEEP=y CONFIG_CMD_MSLEEP=y CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y +CONFIG_CMD_LET=y CONFIG_CMD_MENU=y CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_PASSWD_MODE_STAR=y CONFIG_CMD_TIME=y CONFIG_CMD_LN=y CONFIG_CMD_TFTP=y CONFIG_CMD_FILETYPE=y CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_MM=y CONFIG_CMD_CRC=y CONFIG_CMD_CRC_CMP=y CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_SHA224SUM=y CONFIG_CMD_BOOTM_SHOW_TYPE=y CONFIG_CMD_BOOTM_VERBOSE=y CONFIG_CMD_BOOTM_INITRD=y CONFIG_CMD_BOOTM_OFTREE=y CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +CONFIG_CMD_BOOTM_AIMAGE=y CONFIG_CMD_UIMAGE=y -# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_BOOTZ=y CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y @@ -64,23 +78,36 @@ CONFIG_CMD_WD=y CONFIG_NET=y CONFIG_NET_DHCP=y +CONFIG_NET_NFS=y CONFIG_NET_PING=y CONFIG_NET_NETCONSOLE=y +CONFIG_NET_RESOLV=y CONFIG_OFDEVICE=y CONFIG_SMSC_PHY=y CONFIG_DRIVER_NET_FEC_IMX=y +CONFIG_NET_USB=y +CONFIG_NET_USB_ASIX=y +CONFIG_NET_USB_SMSC95XX=y # CONFIG_SPI is not set CONFIG_I2C=y CONFIG_I2C_IMX=y -CONFIG_DISK_ATA=y +CONFIG_DISK_AHCI=y +CONFIG_DISK_AHCI_IMX=y CONFIG_USB=y +CONFIG_USB_IMX_CHIPIDEA=y CONFIG_USB_EHCI=y +CONFIG_USB_ULPI=y CONFIG_USB_STORAGE=y CONFIG_MCI=y CONFIG_MCI_IMX_ESDHC=y CONFIG_MFD_MC13XXX=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_IMX=y +CONFIG_FS_EXT4=y CONFIG_FS_TFTP=y CONFIG_FS_NFS=y CONFIG_FS_FAT=y diff --git a/arch/arm/configs/phytec-phycore-imx35_defconfig b/arch/arm/configs/phytec-phycore-imx35_defconfig index 59c1b82..6674015 100644 --- a/arch/arm/configs/phytec-phycore-imx35_defconfig +++ b/arch/arm/configs/phytec-phycore-imx35_defconfig @@ -1,8 +1,6 @@ CONFIG_ARCH_IMX=y CONFIG_CACHE_L2X0=y -CONFIG_ARCH_IMX_EXTERNAL_BOOT=y CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y -CONFIG_ARCH_IMX35=y CONFIG_MACH_PCM043=y CONFIG_IMX_IIM=y CONFIG_IMX_IIM_FUSE_BLOW=y @@ -20,7 +18,6 @@ CONFIG_AUTO_COMPLETE=y CONFIG_MENU=y CONFIG_PARTITION=y -CONFIG_PARTITION_DISK=y CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-imx35/env" CONFIG_RESET_SOURCE=y @@ -28,16 +25,16 @@ CONFIG_CMD_SLEEP=y CONFIG_CMD_MSLEEP=y CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y CONFIG_CMD_EXPORT=y CONFIG_CMD_PRINTENV=y CONFIG_CMD_READLINE=y +CONFIG_CMD_READF=y CONFIG_CMD_LET=y CONFIG_CMD_MENU=y CONFIG_CMD_MENU_MANAGEMENT=y CONFIG_CMD_TIME=y -CONFIG_CMD_DIRNAME=y CONFIG_CMD_LN=y -CONFIG_CMD_READLINK=y CONFIG_CMD_TFTP=y CONFIG_CMD_FILETYPE=y CONFIG_CMD_ECHO_E=y @@ -57,9 +54,9 @@ CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y -CONFIG_CMD_OFTREE_PROBE=y CONFIG_CMD_OF_PROPERTY=y CONFIG_CMD_OF_NODE=y +CONFIG_CMD_BAREBOX_UPDATE=y CONFIG_CMD_TIMEOUT=y CONFIG_CMD_PARTITION=y CONFIG_CMD_MAGICVAR=y @@ -68,6 +65,7 @@ CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_MIITOOL=y CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y CONFIG_CMD_WD=y CONFIG_NET=y CONFIG_NET_DHCP=y @@ -76,12 +74,11 @@ CONFIG_NET_NETCONSOLE=y CONFIG_DRIVER_NET_FEC_IMX=y # CONFIG_SPI is not set +CONFIG_MTD=y CONFIG_DRIVER_CFI=y CONFIG_CFI_BUFFER_WRITE=y -CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_IMX=y -CONFIG_UBI=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_IMX=y CONFIG_FS_TFTP=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d42fde9..46b6f4f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -3,8 +3,7 @@ am335x-boneblack.dtb \ am335x-phytec-phycore.dtb dtb-$(CONFIG_ARCH_IMX25) += imx25-karo-tx25.dtb -dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk.dtb \ - imx27-phytec-phycard-s-som.dtb +dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk-bb.dtb dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \ imx51-genesi-efika-sb.dtb dtb-$(CONFIG_ARCH_IMX53) += imx53-mba53.dtb \ diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts new file mode 100644 index 0000000..cecfc5a --- /dev/null +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts @@ -0,0 +1,38 @@ +/* + * Barebox specific DT overlay for Phytec PCA100 RDK + */ + +#include "imx27-phytec-phycard-s-rdk.dts" + +/ { + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &nfc, "partname:environment"; + }; + }; +}; + +&nfc { + partition@0 { + label = "boot"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "environment"; + reg = <0x80000 0x80000>; + }; + + partition@2 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + partition@3 { + label = "root"; + reg = <0x500000 0x7b00000>; + }; +}; diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts index fb2b874..3c3964a 100644 --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts @@ -9,7 +9,7 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include "imx27-phytec-phycard-s-som.dts" +#include "imx27-phytec-phycard-s-som.dtsi" / { model = "Phytec pca100 rapid development kit"; @@ -76,35 +76,54 @@ &iomuxc { imx27-phycard-s-rdk { pinctrl_i2c1: i2c1grp { - fsl,pins = ; + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; }; pinctrl_owire1: owire1grp { - fsl,pins = ; + fsl,pins = < + MX27_PAD_RTCK__OWIRE 0x0 + >; }; pinctrl_sdhc2: sdhc2grp { - fsl,pins = ; + fsl,pins = < + MX27_PAD_SD2_CLK__SD2_CLK 0x0 + MX27_PAD_SD2_CMD__SD2_CMD 0x0 + MX27_PAD_SD2_D0__SD2_D0 0x0 + MX27_PAD_SD2_D1__SD2_D1 0x0 + MX27_PAD_SD2_D2__SD2_D2 0x0 + MX27_PAD_SD2_D3__SD2_D3 0x0 + MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ + >; }; pinctrl_uart1: uart1grp { fsl,pins = < - MX27_UART1_PINGRP1 - MX27_UART1_RTSCTS_PINGRP1 + MX27_PAD_UART1_TXD__UART1_TXD 0x0 + MX27_PAD_UART1_RXD__UART1_RXD 0x0 + MX27_PAD_UART1_CTS__UART1_CTS 0x0 + MX27_PAD_UART1_RTS__UART1_RTS 0x0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX27_UART2_PINGRP1 - MX27_UART2_RTSCTS_PINGRP1 + MX27_PAD_UART2_TXD__UART2_TXD 0x0 + MX27_PAD_UART2_RXD__UART2_RXD 0x0 + MX27_PAD_UART2_CTS__UART2_CTS 0x0 + MX27_PAD_UART2_RTS__UART2_RTS 0x0 >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX27_UART3_PINGRP1 - MX27_UART3_RTSCTS_PINGRP1 + MX27_PAD_UART3_TXD__UART3_TXD 0x0 + MX27_PAD_UART3_RXD__UART3_RXD 0x0 + MX27_PAD_UART3_CTS__UART3_CTS 0x0 + MX27_PAD_UART3_RTS__UART3_RTS 0x0 >; }; }; diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/dts/imx27-phytec-phycard-s-som.dts deleted file mode 100644 index a48d4e1..0000000 --- a/arch/arm/dts/imx27-phytec-phycard-s-som.dts +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar - * and Markus Pargmann, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pca100"; - compatible = "phytec,imx27-pca100", "fsl,imx27"; - - chosen { - linux,stdout-path = &uart1; - - environment@0 { - compatible = "barebox,environment"; - device-path = &nfc, "partname:environment"; - }; - }; - - memory { - reg = <0xa0000000 0x08000000>; /* 128MB */ - }; -}; - -&cspi1 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&iomuxc { - imx27-phycard-s-som { - pinctrl_fec1: fec1grp { - fsl,pins = ; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = ; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = ; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; - - partition@0 { - label = "boot"; - reg = <0x0 0x80000>; - }; - - partition@1 { - label = "environment"; - reg = <0x80000 0x80000>; - }; - - partition@2 { - label = "kernel"; - reg = <0x100000 0x400000>; - }; - - partition@3 { - label = "root"; - reg = <0x500000 0x7b00000>; - }; -}; diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi new file mode 100644 index 0000000..1b62480 --- /dev/null +++ b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi @@ -0,0 +1,103 @@ +/* + * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar + * and Markus Pargmann, Pengutronix + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx27.dtsi" + +/ { + model = "Phytec pca100"; + compatible = "phytec,imx27-pca100", "fsl,imx27"; + + memory { + reg = <0xa0000000 0x08000000>; /* 128MB */ + }; +}; + +&cspi1 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, + <&gpio4 27 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + at24@52 { + compatible = "at,24c32"; + pagesize = <32>; + reg = <0x52>; + }; +}; + +&iomuxc { + imx27-phycard-s-som { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX27_PAD_SD3_CMD__FEC_TXD0 0x0 + MX27_PAD_SD3_CLK__FEC_TXD1 0x0 + MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 + MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 + MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 + MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 + MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 + MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 + MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 + MX27_PAD_ATA_DATA7__FEC_MDC 0x0 + MX27_PAD_ATA_DATA8__FEC_CRS 0x0 + MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 + MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 + MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 + MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 + MX27_PAD_ATA_DATA13__FEC_COL 0x0 + MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 + MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 + MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 + >; + }; + + pinctrl_nfc: nfcgrp { + fsl,pins = < + MX27_PAD_NFRB__NFRB 0x0 + MX27_PAD_NFCLE__NFCLE 0x0 + MX27_PAD_NFWP_B__NFWP_B 0x0 + MX27_PAD_NFCE_B__NFCE_B 0x0 + MX27_PAD_NFALE__NFALE 0x0 + MX27_PAD_NFRE_B__NFRE_B 0x0 + MX27_PAD_NFWE_B__NFWE_B 0x0 + >; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; diff --git a/arch/arm/dts/imx27-pingrp.h b/arch/arm/dts/imx27-pingrp.h deleted file mode 100644 index 57ca02f..0000000 --- a/arch/arm/dts/imx27-pingrp.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2013 Markus Pargmann , Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#ifndef __DTS_IMX27_PINGRP_H -#define __DTS_IMX27_PINGRP_H - -#include "imx27-pinfunc.h" - -#define MX27_CSPI1_PINGRP1 \ - MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 \ - MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 \ - MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 - -#define MX27_CSPI2_PINGRP1 \ - MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 \ - MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 \ - MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 - -#define MX27_CSPI3_PINGRP1 \ - MX27_PAD_SD1_CLK__CSPI3_SCLK 0x0 \ - MX27_PAD_SD1_D0__CSPI3_MISO 0x0 \ - MX27_PAD_SD1_CMD__CSPI3_MOSI 0x0 - -#define MX27_FB_PINGRP1 \ - MX27_PAD_CLS__CLS 0x0 \ - MX27_PAD_CONTRAST__CONTRAST 0x0 \ - MX27_PAD_LD0__LD0 0x0 \ - MX27_PAD_LD1__LD1 0x0 \ - MX27_PAD_LD2__LD2 0x0 \ - MX27_PAD_LD3__LD3 0x0 \ - MX27_PAD_LD4__LD4 0x0 \ - MX27_PAD_LD5__LD5 0x0 \ - MX27_PAD_LD6__LD6 0x0 \ - MX27_PAD_LD7__LD7 0x0 \ - MX27_PAD_LD8__LD8 0x0 \ - MX27_PAD_LD9__LD9 0x0 \ - MX27_PAD_LD10__LD10 0x0 \ - MX27_PAD_LD11__LD11 0x0 \ - MX27_PAD_LD12__LD12 0x0 \ - MX27_PAD_LD13__LD13 0x0 \ - MX27_PAD_LD14__LD14 0x0 \ - MX27_PAD_LD15__LD15 0x0 \ - MX27_PAD_LD16__LD16 0x0 \ - MX27_PAD_LD17__LD17 0x0 \ - MX27_PAD_LSCLK__LSCLK 0x0 \ - MX27_PAD_OE_ACD__OE_ACD 0x0 \ - MX27_PAD_PS__PS 0x0 \ - MX27_PAD_REV__REV 0x0 \ - MX27_PAD_SPL_SPR__SPL_SPR 0x0 \ - MX27_PAD_HSYNC__HSYNC 0x0 \ - MX27_PAD_VSYNC__VSYNC 0x0 - -#define MX27_FEC1_PINGRP1 \ - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 \ - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 \ - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 \ - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 \ - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 \ - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 \ - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 \ - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 \ - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 \ - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 \ - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 \ - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 \ - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 \ - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 \ - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 \ - MX27_PAD_ATA_DATA13__FEC_COL 0x0 \ - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 \ - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - -#define MX27_I2C1_PINGRP1 \ - MX27_PAD_I2C_DATA__I2C_DATA 0x0 \ - MX27_PAD_I2C_CLK__I2C_CLK 0x0 - -#define MX27_I2C2_PINGRP1 \ - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 \ - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - -#define MX27_NFC_PINGRP1 \ - MX27_PAD_NFRB__NFRB 0x0 \ - MX27_PAD_NFCLE__NFCLE 0x0 \ - MX27_PAD_NFWP_B__NFWP_B 0x0 \ - MX27_PAD_NFCE_B__NFCE_B 0x0 \ - MX27_PAD_NFALE__NFALE 0x0 \ - MX27_PAD_NFRE_B__NFRE_B 0x0 \ - MX27_PAD_NFWE_B__NFWE_B 0x0 - -#define MX27_OWIRE1_PINGRP1 \ - MX27_PAD_RTCK__OWIRE 0x0 - -#define MX27_PWM_PINGRP1 \ - MX27_PAD_PWMO__PWMO 0x0 - -#define MX27_SDHC1_PINGRP1 \ - MX27_PAD_SD1_CLK__SD1_CLK 0x0 \ - MX27_PAD_SD1_CMD__SD1_CMD 0x0 \ - MX27_PAD_SD1_D0__SD1_D0 0x0 \ - MX27_PAD_SD1_D1__SD1_D1 0x0 \ - MX27_PAD_SD1_D2__SD1_D2 0x0 \ - MX27_PAD_SD1_D3__SD1_D3 0x0 - -#define MX27_SDHC2_PINGRP1 \ - MX27_PAD_SD2_CLK__SD2_CLK 0x0 \ - MX27_PAD_SD2_CMD__SD2_CMD 0x0 \ - MX27_PAD_SD2_D0__SD2_D0 0x0 \ - MX27_PAD_SD2_D1__SD2_D1 0x0 \ - MX27_PAD_SD2_D2__SD2_D2 0x0 \ - MX27_PAD_SD2_D3__SD2_D3 0x0 - -#define MX27_SDHC3_PINGRP1 \ - MX27_PAD_SD3_CLK__SD3_CLK 0x0 \ - MX27_PAD_SD3_CMD__SD3_CMD 0x0 \ - MX27_PAD_SD3_D0__SD3_D0 0x0 \ - MX27_PAD_SD3_D1__SD3_D1 0x0 \ - MX27_PAD_SD3_D2__SD3_D2 0x0 \ - MX27_PAD_SD3_D3__SD3_D3 0x0 - -#define MX27_UART1_PINGRP1 \ - MX27_PAD_UART1_TXD__UART1_TXD 0x0 \ - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - -#define MX27_UART1_RTSCTS_PINGRP1 \ - MX27_PAD_UART1_CTS__UART1_CTS 0x0 \ - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - -#define MX27_UART2_PINGRP1 \ - MX27_PAD_UART2_TXD__UART2_TXD 0x0 \ - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - -#define MX27_UART2_RTSCTS_PINGRP1 \ - MX27_PAD_UART2_CTS__UART2_CTS 0x0 \ - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - -#define MX27_UART3_PINGRP1 \ - MX27_PAD_UART3_TXD__UART3_TXD 0x0 \ - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - -#define MX27_UART3_RTSCTS_PINGRP1 \ - MX27_PAD_UART3_CTS__UART3_CTS 0x0 \ - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - -#endif /* __DTS_IMX27_PINGRP_H */ diff --git a/arch/arm/dts/imx27.dtsi b/arch/arm/dts/imx27.dtsi index 7e98966..83a8247 100644 --- a/arch/arm/dts/imx27.dtsi +++ b/arch/arm/dts/imx27.dtsi @@ -10,12 +10,13 @@ */ #include "skeleton.dtsi" -#include "imx27-pingrp.h" +#include "imx27-pinfunc.h" #include #include / { aliases { + ethernet0 = &fec; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -70,6 +71,26 @@ }; }; + usbphy { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + usbphy0: usbphy@0 { + compatible = "usb-nop-xceiv"; + reg = <0>; + clocks = <&clks 75>; + clock-names = "main_clk"; + }; + + usbphy2: usbphy@2 { + compatible = "usb-nop-xceiv"; + reg = <2>; + clocks = <&clks 75>; + clock-names = "main_clk"; + }; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -439,6 +460,42 @@ iram = <&iram>; }; + usbotg: usb@10024000 { + compatible = "fsl,imx27-usb"; + reg = <0x10024000 0x200>; + interrupts = <56>; + clocks = <&clks 15>; + fsl,usbmisc = <&usbmisc 0>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usbh1: usb@10024200 { + compatible = "fsl,imx27-usb"; + reg = <0x10024200 0x200>; + interrupts = <54>; + clocks = <&clks 15>; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbh2: usb@10024400 { + compatible = "fsl,imx27-usb"; + reg = <0x10024400 0x200>; + interrupts = <55>; + clocks = <&clks 15>; + fsl,usbmisc = <&usbmisc 2>; + fsl,usbphy = <&usbphy2>; + status = "disabled"; + }; + + usbmisc: usbmisc@10024600 { + #index-cells = <1>; + compatible = "fsl,imx27-usbmisc"; + reg = <0x10024600 0x200>; + clocks = <&clks 62>; + }; + sahara2: sahara@10025000 { compatible = "fsl,imx27-sahara"; reg = <0x10025000 0x1000>; diff --git a/arch/arm/dts/imx53-qsb-common.dtsi b/arch/arm/dts/imx53-qsb-common.dtsi index 571da92..9aa0f08 100644 --- a/arch/arm/dts/imx53-qsb-common.dtsi +++ b/arch/arm/dts/imx53-qsb-common.dtsi @@ -230,3 +230,7 @@ &sata { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi index c3fac43..d6cdcaf 100644 --- a/arch/arm/dts/imx53.dtsi +++ b/arch/arm/dts/imx53.dtsi @@ -79,8 +79,8 @@ compatible = "fsl,imx53-ahci"; reg = <0x10000000 0x1000>; interrupts = <28>; - clocks = <&clks 173>, <&clks 5>, <&clks 188>; - clock-names = "sata", "ahb", "per"; + clocks = <&clks 173>, <&clks 188>, <&clks 5>; + clock-names = "sata_gate", "sata_ref", "ahb"; status = "disabled"; }; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index b242716..034a2cd 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -110,6 +110,12 @@ depends on BAREBOX_UPDATE default y +config BAREBOX_UPDATE_IMX6_NAND + bool + depends on ARCH_IMX6 + depends on BAREBOX_UPDATE + default y + comment "Freescale i.MX System-on-Chip" config ARCH_IMX1 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index b3f00f9..03e5b10 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -20,4 +20,5 @@ obj-y += boot.o obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o +obj-$(CONFIG_BAREBOX_UPDATE_IMX6_NAND) += imx6-bbu-nand.o pbl-y += esdctl.o diff --git a/arch/arm/mach-imx/imx6-bbu-nand.c b/arch/arm/mach-imx/imx6-bbu-nand.c new file mode 100644 index 0000000..2d07059 --- /dev/null +++ b/arch/arm/mach-imx/imx6-bbu-nand.c @@ -0,0 +1,497 @@ +/* + * Copyright (C) 2014 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ + +#define pr_fmt(fmt) "imx6-bbu-nand: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct dbbt_block { + uint32_t Checksum; + uint32_t FingerPrint; + uint32_t Version; + uint32_t reserved; + uint32_t DBBTNumOfPages; +}; + +struct fcb_block { + uint32_t Checksum; /* First fingerprint in first byte */ + uint32_t FingerPrint; /* 2nd fingerprint at byte 4 */ + uint32_t Version; /* 3rd fingerprint at byte 8 */ + uint8_t DataSetup; + uint8_t DataHold; + uint8_t AddressSetup; + uint8_t DSAMPLE_TIME; + /* These are for application use only and not for ROM. */ + uint8_t NandTimingState; + uint8_t REA; + uint8_t RLOH; + uint8_t RHOH; + uint32_t PageDataSize; /* 2048 for 2K pages, 4096 for 4K pages */ + uint32_t TotalPageSize; /* 2112 for 2K pages, 4314 for 4K pages */ + uint32_t SectorsPerBlock; /* Number of 2K sections per block */ + uint32_t NumberOfNANDs; /* Total Number of NANDs - not used by ROM */ + uint32_t TotalInternalDie; /* Number of separate chips in this NAND */ + uint32_t CellType; /* MLC or SLC */ + uint32_t EccBlockNEccType; /* Type of ECC, can be one of BCH-0-20 */ + uint32_t EccBlock0Size; /* Number of bytes for Block0 - BCH */ + uint32_t EccBlockNSize; /* Block size in bytes for all blocks other than Block0 - BCH */ + uint32_t EccBlock0EccType; /* Ecc level for Block 0 - BCH */ + uint32_t MetadataBytes; /* Metadata size - BCH */ + uint32_t NumEccBlocksPerPage; /* Number of blocks per page for ROM use - BCH */ + uint32_t EccBlockNEccLevelSDK; /* Type of ECC, can be one of BCH-0-20 */ + uint32_t EccBlock0SizeSDK; /* Number of bytes for Block0 - BCH */ + uint32_t EccBlockNSizeSDK; /* Block size in bytes for all blocks other than Block0 - BCH */ + uint32_t EccBlock0EccLevelSDK; /* Ecc level for Block 0 - BCH */ + uint32_t NumEccBlocksPerPageSDK;/* Number of blocks per page for SDK use - BCH */ + uint32_t MetadataBytesSDK; /* Metadata size - BCH */ + uint32_t EraseThreshold; /* To set into BCH_MODE register */ + uint32_t BootPatch; /* 0 for normal boot and 1 to load patch starting next to FCB */ + uint32_t PatchSectors; /* Size of patch in sectors */ + uint32_t Firmware1_startingPage;/* Firmware image starts on this sector */ + uint32_t Firmware2_startingPage;/* Secondary FW Image starting Sector */ + uint32_t PagesInFirmware1; /* Number of sectors in firmware image */ + uint32_t PagesInFirmware2; /* Number of sector in secondary FW image */ + uint32_t DBBTSearchAreaStartAddress; /* Page address where dbbt search area begins */ + uint32_t BadBlockMarkerByte; /* Byte in page data that have manufacturer marked bad block marker, */ + /* this will be swapped with metadata[0] to complete page data. */ + uint32_t BadBlockMarkerStartBit;/* For BCH ECC sizes other than 8 and 16 the bad block marker does not */ + /* start at 0th bit of BadBlockMarkerByte. This field is used to get to */ + /* the start bit of bad block marker byte with in BadBlockMarkerByte */ + uint32_t BBMarkerPhysicalOffset;/* FCB value that gives byte offset for bad block marker on physical NAND page */ + uint32_t BCHType; + + uint32_t TMTiming2_ReadLatency; + uint32_t TMTiming2_PreambleDelay; + uint32_t TMTiming2_CEDelay; + uint32_t TMTiming2_PostambleDelay; + uint32_t TMTiming2_CmdAddPause; + uint32_t TMTiming2_DataPause; + uint32_t TMSpeed; + uint32_t TMTiming1_BusyTimeout; + + uint32_t DISBBM; /* the flag to enable (1)/disable(0) bi swap */ + uint32_t BBMarkerPhysicalOffsetInSpareData; /* The swap position of main area in spare area */ +}; + +#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) +#define GETBIT(v,n) (((v) >> (n)) & 0x1) + +static uint8_t calculate_parity_13_8(uint8_t d) +{ + uint8_t p = 0; + + p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 3) ^ GETBIT(d, 2)) << 0; + p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^ GETBIT(d, 4) ^ GETBIT(d, 2) ^ GETBIT(d, 1)) << 1; + p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 2; + p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 0)) << 3; + p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 2) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 4; + return p; +} + +static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) +{ + int i; + uint8_t *src = _src; + uint8_t *ecc = _ecc; + + for (i = 0; i < size; i++) + ecc[i] = calculate_parity_13_8(src[i]); +} + +static uint32_t calc_chksum(void *buf, size_t size) +{ + u32 chksum = 0; + u8 *bp = buf; + size_t i; + + for (i = 0; i < size; i++) + chksum += bp[i]; + + return ~chksum; +} + +static __maybe_unused void dump_fcb(void *buf) +{ + struct fcb_block *fcb = buf; + + pr_debug("Checksum: 0x%08x\n", fcb->Checksum); + pr_debug("FingerPrint: 0x%08x\n", fcb->FingerPrint); + pr_debug("Version: 0x%08x\n", fcb->Version); + pr_debug("DataSetup: 0x%02x\n", fcb->DataSetup); + pr_debug("DataHold: 0x%02x\n", fcb->DataHold); + pr_debug("AddressSetup: 0x%02x\n", fcb->AddressSetup); + pr_debug("DSAMPLE_TIME: 0x%02x\n", fcb->DSAMPLE_TIME); + pr_debug("NandTimingState: 0x%02x\n", fcb->NandTimingState); + pr_debug("REA: 0x%02x\n", fcb->REA); + pr_debug("RLOH: 0x%02x\n", fcb->RLOH); + pr_debug("RHOH: 0x%02x\n", fcb->RHOH); + pr_debug("PageDataSize: 0x%08x\n", fcb->PageDataSize); + pr_debug("TotalPageSize: 0x%08x\n", fcb->TotalPageSize); + pr_debug("SectorsPerBlock: 0x%08x\n", fcb->SectorsPerBlock); + pr_debug("NumberOfNANDs: 0x%08x\n", fcb->NumberOfNANDs); + pr_debug("TotalInternalDie: 0x%08x\n", fcb->TotalInternalDie); + pr_debug("CellType: 0x%08x\n", fcb->CellType); + pr_debug("EccBlockNEccType: 0x%08x\n", fcb->EccBlockNEccType); + pr_debug("EccBlock0Size: 0x%08x\n", fcb->EccBlock0Size); + pr_debug("EccBlockNSize: 0x%08x\n", fcb->EccBlockNSize); + pr_debug("EccBlock0EccType: 0x%08x\n", fcb->EccBlock0EccType); + pr_debug("MetadataBytes: 0x%08x\n", fcb->MetadataBytes); + pr_debug("NumEccBlocksPerPage: 0x%08x\n", fcb->NumEccBlocksPerPage); + pr_debug("EccBlockNEccLevelSDK: 0x%08x\n", fcb->EccBlockNEccLevelSDK); + pr_debug("EccBlock0SizeSDK: 0x%08x\n", fcb->EccBlock0SizeSDK); + pr_debug("EccBlockNSizeSDK: 0x%08x\n", fcb->EccBlockNSizeSDK); + pr_debug("EccBlock0EccLevelSDK: 0x%08x\n", fcb->EccBlock0EccLevelSDK); + pr_debug("NumEccBlocksPerPageSDK: 0x%08x\n", fcb->NumEccBlocksPerPageSDK); + pr_debug("MetadataBytesSDK: 0x%08x\n", fcb->MetadataBytesSDK); + pr_debug("EraseThreshold: 0x%08x\n", fcb->EraseThreshold); + pr_debug("BootPatch: 0x%08x\n", fcb->BootPatch); + pr_debug("PatchSectors: 0x%08x\n", fcb->PatchSectors); + pr_debug("Firmware1_startingPage: 0x%08x\n", fcb->Firmware1_startingPage); + pr_debug("Firmware2_startingPage: 0x%08x\n", fcb->Firmware2_startingPage); + pr_debug("PagesInFirmware1: 0x%08x\n", fcb->PagesInFirmware1); + pr_debug("PagesInFirmware2: 0x%08x\n", fcb->PagesInFirmware2); + pr_debug("DBBTSearchAreaStartAddress: 0x%08x\n", fcb->DBBTSearchAreaStartAddress); + pr_debug("BadBlockMarkerByte: 0x%08x\n", fcb->BadBlockMarkerByte); + pr_debug("BadBlockMarkerStartBit: 0x%08x\n", fcb->BadBlockMarkerStartBit); + pr_debug("BBMarkerPhysicalOffset: 0x%08x\n", fcb->BBMarkerPhysicalOffset); + pr_debug("BCHType: 0x%08x\n", fcb->BCHType); + pr_debug("TMTiming2_ReadLatency: 0x%08x\n", fcb->TMTiming2_ReadLatency); + pr_debug("TMTiming2_PreambleDelay: 0x%08x\n", fcb->TMTiming2_PreambleDelay); + pr_debug("TMTiming2_CEDelay: 0x%08x\n", fcb->TMTiming2_CEDelay); + pr_debug("TMTiming2_PostambleDelay: 0x%08x\n", fcb->TMTiming2_PostambleDelay); + pr_debug("TMTiming2_CmdAddPause: 0x%08x\n", fcb->TMTiming2_CmdAddPause); + pr_debug("TMTiming2_DataPause: 0x%08x\n", fcb->TMTiming2_DataPause); + pr_debug("TMSpeed: 0x%08x\n", fcb->TMSpeed); + pr_debug("TMTiming1_BusyTimeout: 0x%08x\n", fcb->TMTiming1_BusyTimeout); + pr_debug("DISBBM: 0x%08x\n", fcb->DISBBM); + pr_debug("BBMarkerPhysOfsInSpareData: 0x%08x\n", fcb->BBMarkerPhysicalOffsetInSpareData); +} + +static __maybe_unused ssize_t raw_read_page(struct mtd_info *mtd, void *dst, loff_t offset) +{ + struct mtd_oob_ops ops; + ssize_t ret; + + ops.mode = MTD_OPS_RAW; + ops.ooboffs = 0; + ops.datbuf = dst; + ops.len = mtd->writesize; + ops.oobbuf = dst + mtd->writesize; + ops.ooblen = mtd->oobsize; + ret = mtd_read_oob(mtd, offset, &ops); + + return ret; +} + +static ssize_t raw_write_page(struct mtd_info *mtd, void *buf, loff_t offset) +{ + struct mtd_oob_ops ops; + ssize_t ret; + + ops.mode = MTD_OPS_RAW; + ops.ooboffs = 0; + ops.datbuf = buf; + ops.len = mtd->writesize; + ops.oobbuf = buf + mtd->writesize; + ops.ooblen = mtd->oobsize; + ret = mtd_write_oob(mtd, offset, &ops); + + return ret; +} + +static int fcb_create(struct fcb_block *fcb, struct mtd_info *mtd) +{ + fcb->FingerPrint = 0x20424346; + fcb->Version = 0x01000000; + fcb->PageDataSize = mtd->writesize; + fcb->TotalPageSize = mtd->writesize + mtd->oobsize; + fcb->SectorsPerBlock = mtd->erasesize / mtd->writesize; + + if (mtd->writesize == 2048) { + fcb->EccBlock0EccType = 4; + } else if (mtd->writesize == 4096) { + if (mtd->oobsize == 218) { + fcb->EccBlock0EccType = 8; + } else if (mtd->oobsize == 128) { + fcb->EccBlock0EccType = 4; + } else { + pr_err("Illegal oobsize %d\n", mtd->oobsize); + return -EINVAL; + } + } else { + pr_err("Illegal writesize %d\n", mtd->writesize); + return -EINVAL; + } + + fcb->EccBlockNEccType = fcb->EccBlock0EccType; + + /* Also hardcoded in kobs-ng */ + fcb->DataSetup = 80; + fcb->DataHold = 60; + fcb->AddressSetup = 25; + fcb->DSAMPLE_TIME = 6; + fcb->MetadataBytes = 0x0000000a; + fcb->EccBlock0Size = 0x00000200; + fcb->EccBlockNSize = 0x00000200; + + fcb->NumEccBlocksPerPage = mtd->writesize / fcb->EccBlock0Size - 1; + + /* DBBT search area starts at third block */ + fcb->DBBTSearchAreaStartAddress = mtd->erasesize / mtd->writesize * 2; + + if (mtd->writesize == 2048) { + fcb->BadBlockMarkerByte = 0x000007cf; + } else { + pr_err("BadBlockMarkerByte unknown for writesize %d\n", mtd->writesize); + return -EINVAL; + } + + fcb->BBMarkerPhysicalOffset = mtd->writesize; + + fcb->Checksum = calc_chksum((void *)fcb + 4, sizeof(*fcb) - 4); + + return 0; +} + +static int imx6_bbu_erase(struct mtd_info *mtd) +{ + uint64_t offset = 0; + int len = SZ_2M; + struct erase_info erase; + int ret; + + while (len > 0) { + pr_debug("erasing at 0x%08llx\n", offset); + if (mtd_block_isbad(mtd, offset)) { + offset += mtd->erasesize; + pr_debug("erase skip block @ 0x%08llx\n", offset); + continue; + } + + memset(&erase, 0, sizeof(erase)); + erase.addr = offset; + erase.len = mtd->erasesize; + + ret = mtd_erase(mtd, &erase); + if (ret) + return ret; + + offset += mtd->erasesize; + len -= mtd->erasesize; + } + + return 0; +} + +static int imx6_bbu_write_firmware(struct mtd_info *mtd, int block, void *buf, size_t len) +{ + uint64_t offset = block * mtd->erasesize; + int ret; + size_t written; + + while (len > 0) { + int now = min(len, mtd->erasesize); + + pr_debug("writing %p at 0x%08llx, left 0x%08x\n", + buf, offset, len); + + if (mtd_block_isbad(mtd, offset)) { + offset += mtd->erasesize; + block++; + pr_debug("write skip block @ 0x%08llx\n", offset); + continue; + } + + ret = mtd_write(mtd, offset, now, &written, buf); + if (ret) + return ret; + + offset += now; + len -= now; + buf += now; + block++; + } + + return block; +} + +static int dbbt_data_create(struct mtd_info *mtd, void *buf, int block_last) +{ + int n; + int n_bad_blocks = 0; + uint32_t *bb = buf + 0x8; + uint32_t *n_bad_blocksp = buf + 0x4; + + for (n = 0; n <= block_last; n++) { + loff_t offset = n * mtd->erasesize; + if (mtd_block_isbad(mtd, offset)) { + n_bad_blocks++; + *bb = n; + bb++; + } + } + + *n_bad_blocksp = n_bad_blocks; + + return n_bad_blocks; +} + +static int imx6_bbu_nand_update(struct bbu_handler *handler, struct bbu_data *data) +{ + struct cdev *bcb_cdev; + struct mtd_info *mtd; + int ret, block_fw1, block_fw2, block_last; + struct fcb_block *fcb; + struct dbbt_block *dbbt; + void *fcb_raw_page, *dbbt_page, *dbbt_data_page; + void *ecc; + int written; + void *fw; + unsigned fw_size; + int i; + + if (file_detect_type(data->image, data->len) != filetype_arm_barebox && + !bbu_force(data, "Not an ARM barebox image")) + return -EINVAL; + + ret = bbu_confirm(data); + if (ret) + return ret; + + bcb_cdev = cdev_by_name("nand0"); + if (!bcb_cdev) { + pr_err("%s: No FCB device!\n", __func__); + return -ENODEV; + } + + mtd = bcb_cdev->mtd; + + fcb_raw_page = xzalloc(mtd->writesize + mtd->oobsize); + + fcb = fcb_raw_page + 12; + ecc = fcb_raw_page + 512 + 12; + + dbbt_page = xzalloc(mtd->writesize); + dbbt_data_page = xzalloc(mtd->writesize); + dbbt = dbbt_page; + + /* + * We have to write one additional page to make the ROM happy. + * Maybe the PagesInFirmwarex fields are really the number of pages - 1. + * kobs-ng has the same. + */ + fw_size = ALIGN(data->len + mtd->writesize, mtd->writesize); + fw = xzalloc(fw_size); + memcpy(fw, data->image, data->len); + + block_fw1 = 4; + + ret = imx6_bbu_erase(mtd); + if (ret) + goto out; + + ret = imx6_bbu_write_firmware(mtd, block_fw1, fw, fw_size); + if (ret < 0) + goto out; + + block_fw2 = ret; + + ret = imx6_bbu_write_firmware(mtd, block_fw2, fw, fw_size); + if (ret < 0) + goto out; + + block_last = ret; + + fcb->Firmware1_startingPage = block_fw1 * mtd->erasesize / mtd->writesize; + fcb->Firmware2_startingPage = block_fw2 * mtd->erasesize / mtd->writesize; + fcb->PagesInFirmware1 = ALIGN(data->len, mtd->writesize) / mtd->writesize; + fcb->PagesInFirmware2 = fcb->PagesInFirmware1; + + fcb_create(fcb, mtd); + encode_hamming_13_8(fcb, ecc, 512); + ret = raw_write_page(mtd, fcb_raw_page, 0); + if (ret) + goto out; + + ret = raw_write_page(mtd, fcb_raw_page, mtd->erasesize); + if (ret) + goto out; + + dbbt->Checksum = 0; + dbbt->FingerPrint = 0x54424244; + dbbt->Version = 0x01000000; + + ret = dbbt_data_create(mtd, dbbt_data_page, block_last); + if (ret < 0) + goto out; + + if (ret > 0) + dbbt->DBBTNumOfPages = 1; + + for (i = 2; i < 4; i++) { + ret = mtd_write(mtd, mtd->erasesize * i, 2048, &written, dbbt_page); + if (ret) + goto out; + + if (dbbt->DBBTNumOfPages > 0) { + ret = mtd_write(mtd, mtd->erasesize * i + mtd->writesize * 4, + 2048, &written, dbbt_data_page); + if (ret) + goto out; + } + } + +out: + free(dbbt_page); + free(dbbt_data_page); + free(fcb_raw_page); + free(fw); + + return ret; +} + +int imx6_bbu_nand_register_handler(const char *name, unsigned long flags) +{ + struct bbu_handler *handler; + int ret; + + handler = xzalloc(sizeof(*handler)); + handler->devicefile = "/dev/nand0"; + handler->name = name; + handler->flags = flags; + handler->handler = imx6_bbu_nand_update; + + ret = bbu_register_handler(handler); + if (ret) + free(handler); + + return ret; +} diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h index 3cd3b1e..1644d85 100644 --- a/arch/arm/mach-imx/include/mach/bbu.h +++ b/arch/arm/mach-imx/include/mach/bbu.h @@ -33,6 +33,8 @@ unsigned long flags, struct imx_dcd_v2_entry *dcd, int dcdsize, unsigned long app_dest); +int imx6_bbu_nand_register_handler(const char *name, unsigned long flags); + #else static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile, @@ -77,6 +79,10 @@ return -ENOSYS; } +static inline int imx6_bbu_nand_register_handler(const char *name, unsigned long flags) +{ + return -ENOSYS; +} #endif #if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)