diff --git a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
index b1608dd..6c256e8 100644
--- a/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
+++ b/arch/arm/boards/phytec-phycore-imx7/flash-header-phytec-phycore-imx7.imxcfg
@@ -13,64 +13,66 @@
 loadaddr 0x80000000
 dcdofs 0x400
 
+#include <mach/imx7-ddr-regs.h>
+
 wm 32 0x30340004 0x4F400005
 /* Clear then set bit30 to ensure exit from DDR retention */
 wm 32 0x30360388 0x40000000
 wm 32 0x30360384 0x40000000
 
 wm 32 0x30391000 0x00000002
-wm 32 0x307a0000 0x01040001
-wm 32 0x307a01a0 0x80400003
-wm 32 0x307a01a4 0x00100020
-wm 32 0x307a01a8 0x80100004
-wm 32 0x307a0064 0x00400046
-wm 32 0x307a0490 0x00000001
-wm 32 0x307a00d0 0x00020083
-wm 32 0x307a00d4 0x00690000
-wm 32 0x307a00dc 0x09300004
-wm 32 0x307a00e0 0x04080000
-wm 32 0x307a00e4 0x00100004
-wm 32 0x307a00f4 0x0000033f
-wm 32 0x307a0100 0x09081109
-wm 32 0x307a0104 0x0007020d
-wm 32 0x307a0108 0x03040407
-wm 32 0x307a010c 0x00002006
-wm 32 0x307a0110 0x04020205
-wm 32 0x307a0114 0x03030202
-wm 32 0x307a0120 0x00000803
-wm 32 0x307a0180 0x00800020
-wm 32 0x307a0184 0x02000100
-wm 32 0x307a0190 0x02098204
-wm 32 0x307a0194 0x00030303
-wm 32 0x307a0200 0x00000016
-wm 32 0x307a0204 0x00171717
-wm 32 0x307a0214 0x04040404
-wm 32 0x307a0218 0x0f040404
-wm 32 0x307a0240 0x06000604
-wm 32 0x307a0244 0x00000001
+wm 32 MX7_DDRC_MSTR 0x01040001
+wm 32 MX7_DDRC_DFIUPD0 0x80400003
+wm 32 MX7_DDRC_DFIUPD1 0x00100020
+wm 32 MX7_DDRC_DFIUPD2 0x80100004
+wm 32 MX7_DDRC_RFSHTMG 0x00400046
+wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001
+wm 32 MX7_DDRC_INIT0 0x00020083
+wm 32 MX7_DDRC_INIT1 0x00690000
+wm 32 MX7_DDRC_INIT3 0x09300004
+wm 32 MX7_DDRC_INIT4 0x04080000
+wm 32 MX7_DDRC_INIT5 0x00100004
+wm 32 MX7_DDRC_RANKCTL 0x0000033f
+wm 32 MX7_DDRC_DRAMTMG0 0x09081109
+wm 32 MX7_DDRC_DRAMTMG1 0x0007020d
+wm 32 MX7_DDRC_DRAMTMG2 0x03040407
+wm 32 MX7_DDRC_DRAMTMG3 0x00002006
+wm 32 MX7_DDRC_DRAMTMG4 0x04020205
+wm 32 MX7_DDRC_DRAMTMG5 0x03030202
+wm 32 MX7_DDRC_DRAMTMG8 0x00000803
+wm 32 MX7_DDRC_ZQCTL0 0x00800020
+wm 32 MX7_DDRC_ZQCTL1 0x02000100
+wm 32 MX7_DDRC_DFITMG0 0x02098204
+wm 32 MX7_DDRC_DFITMG1 0x00030303
+wm 32 MX7_DDRC_ADDRMAP0 0x00000016
+wm 32 MX7_DDRC_ADDRMAP1 0x00171717
+wm 32 MX7_DDRC_ADDRMAP5 0x04040404
+wm 32 MX7_DDRC_ADDRMAP6 0x0f040404
+wm 32 MX7_DDRC_ODTCFG 0x06000604
+wm 32 MX7_DDRC_ODTMAP 0x00000001
 wm 32 0x30391000 0x00000000
-wm 32 0x30790000 0x17420f40
-wm 32 0x30790004 0x10210100
-wm 32 0x30790010 0x00060807
-wm 32 0x307900b0 0x1010007e
-wm 32 0x3079009c 0x00000d6e
-wm 32 0x30790020 0x08080808
-wm 32 0x30790030 0x08080808
-wm 32 0x30790050 0x01000010
-wm 32 0x30790050 0x00000010
+wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40
+wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100
+wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807
+wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e
+wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e
+wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808
+wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808
+wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010
+wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010
 
-wm 32 0x307900c0 0x0e407304
-wm 32 0x307900c0 0x0e447304
-wm 32 0x307900c0 0x0e447306
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306
 
-check 32 while_any_bit_clear 0x307900c4 0x1
+check 32 while_any_bit_clear MX7_DDR_PHY_ZQ_CON1 0x1
 
-wm 32 0x307900c0 0x0e447304
-wm 32 0x307900c0 0x0e407304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
 
 wm 32 0x30384130 0x00000000
 wm 32 0x30340020 0x00000178
 wm 32 0x30384130 0x00000002
-wm 32 0x30790018 0x0000000f
+wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f
 
-check 32 while_any_bit_clear 0x307a0004 0x1
+check 32 while_any_bit_clear MX7_DDRC_STAT 0x1
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 96beef4..8cec129 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -176,3 +176,7 @@
 		};
 	};
 };
+
+&ocotp {
+	barebox,provide-mac-address = <&fec1 0x620 &fec2 0x632>;
+};
diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c
index bd1749f..5ac0ed1 100644
--- a/drivers/clk/imx/clk-cpu.c
+++ b/drivers/clk/imx/clk-cpu.c
@@ -82,14 +82,22 @@
 	.set_rate	= clk_cpu_set_rate,
 };
 
+struct imx_clk_cpu {
+	struct clk_cpu cpu;
+	const char *parent_name;
+};
+
 struct clk *imx_clk_cpu(const char *name, const char *parent_name,
 		struct clk *div, struct clk *mux, struct clk *pll,
 		struct clk *step)
 {
+	struct imx_clk_cpu *icpu;
 	struct clk_cpu *cpu;
 	int ret;
 
-	cpu = xzalloc(sizeof(*cpu));
+	icpu = xzalloc(sizeof(*icpu));
+	icpu->parent_name = parent_name;
+	cpu = &icpu->cpu;
 
 	cpu->div = div;
 	cpu->mux = mux;
@@ -99,7 +107,7 @@
 	cpu->clk.name = name;
 	cpu->clk.ops = &clk_cpu_ops;
 	cpu->clk.flags = 0;
-	cpu->clk.parent_names = &parent_name;
+	cpu->clk.parent_names = &icpu->parent_name;
 	cpu->clk.num_parents = 1;
 
 	ret = clk_register(&cpu->clk);
diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c
index 876699a..7819879 100644
--- a/drivers/spi/imx_spi.c
+++ b/drivers/spi/imx_spi.c
@@ -32,14 +32,17 @@
 #include <linux/err.h>
 #include <clock.h>
 
+/* time to wait for STAT_RR getting set */
+#define IMX_SPI_RR_TIMEOUT	10000 /* ns */
+
 struct imx_spi {
 	struct spi_master	master;
 	int			*cs_array;
 	void __iomem		*regs;
 	struct clk		*clk;
 
-	unsigned int		(*xchg_single)(struct imx_spi *imx, u32 data);
-	void			(*do_transfer)(struct spi_device *spi);
+	int			(*xchg_single)(struct imx_spi *imx, u32 txdata, u32 *rxdata);
+	int			(*do_transfer)(struct spi_device *spi);
 	void			(*chipselect)(struct spi_device *spi, int active);
 
 	const void *tx_buf;
@@ -49,8 +52,8 @@
 };
 
 struct spi_imx_devtype_data {
-	unsigned int		(*xchg_single)(struct imx_spi *imx, u32 data);
-	void			(*do_transfer)(struct spi_device *spi);
+	int			(*xchg_single)(struct imx_spi *imx, u32 txdata, u32 *rxdata);
+	int			(*do_transfer)(struct spi_device *spi);
 	void			(*chipselect)(struct spi_device *spi, int active);
 	void			(*init)(struct imx_spi *imx);
 };
@@ -86,21 +89,29 @@
 	return result;
 }
 
-static unsigned int cspi_0_0_xchg_single(struct imx_spi *imx, unsigned int data)
+static int cspi_0_0_xchg_single(struct imx_spi *imx, u32 txdata, u32 *rxdata)
 {
 	void __iomem *base = imx->regs;
+	int ret;
 
 	unsigned int cfg_reg = readl(base + CSPI_0_0_CTRL);
 
-	writel(data, base + CSPI_0_0_TXDATA);
+	writel(txdata, base + CSPI_0_0_TXDATA);
 
 	cfg_reg |= CSPI_0_0_CTRL_XCH;
 
 	writel(cfg_reg, base + CSPI_0_0_CTRL);
 
-	while (!(readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR));
+	ret = wait_on_timeout(IMX_SPI_RR_TIMEOUT,
+			      readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR);
+	if (ret) {
+		dev_err(imx->master.dev, "Timeout waiting for received data\n");
+		return ret;
+	}
 
-	return readl(base + CSPI_0_0_RXDATA);
+	*rxdata = readl(base + CSPI_0_0_RXDATA);
+
+	return 0;
 }
 
 static void cspi_0_0_chipselect(struct spi_device *spi, int is_active)
@@ -152,22 +163,28 @@
 	} while (readl(base + CSPI_0_0_RESET) & CSPI_0_0_RESET_START);
 }
 
-static unsigned int cspi_0_7_xchg_single(struct imx_spi *imx, unsigned int data)
+static int cspi_0_7_xchg_single(struct imx_spi *imx, u32 txdata, u32 *rxdata)
 {
 	void __iomem *base = imx->regs;
+	int ret;
 
 	unsigned int cfg_reg = readl(base + CSPI_0_7_CTRL);
 
-	writel(data, base + CSPI_0_7_TXDATA);
+	writel(txdata, base + CSPI_0_7_TXDATA);
 
 	cfg_reg |= CSPI_0_7_CTRL_XCH;
 
 	writel(cfg_reg, base + CSPI_0_7_CTRL);
 
-	while (!(readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR))
-		;
+	ret = wait_on_timeout(IMX_SPI_RR_TIMEOUT,
+			      readl(base + CSPI_0_7_STAT) & CSPI_0_7_STAT_RR);
+	if (ret) {
+		dev_err(imx->master.dev, "Timeout waiting for received data\n");
+		return ret;
+	}
 
-	return readl(base + CSPI_0_7_RXDATA);
+	*rxdata = readl(base + CSPI_0_7_RXDATA);
+	return 0;
 }
 
 /* MX1, MX31, MX35, MX51 CSPI */
@@ -242,15 +259,23 @@
 		readl(base + CSPI_0_7_RXDATA);
 }
 
-static unsigned int cspi_2_3_xchg_single(struct imx_spi *imx, unsigned int data)
+static int cspi_2_3_xchg_single(struct imx_spi *imx, u32 txdata, u32 *rxdata)
 {
 	void __iomem *base = imx->regs;
+	int ret;
 
-	writel(data, base + CSPI_2_3_TXDATA);
+	writel(txdata, base + CSPI_2_3_TXDATA);
 
-	while (!(readl(base + CSPI_2_3_STAT) & CSPI_2_3_STAT_RR));
+	ret = wait_on_timeout(IMX_SPI_RR_TIMEOUT,
+			      readl(base + CSPI_2_3_STAT) & CSPI_2_3_STAT_RR);
+	if (ret) {
+		dev_err(imx->master.dev, "Timeout waiting for received data\n");
+		return ret;
+	}
 
-	return readl(base + CSPI_2_3_RXDATA);
+	*rxdata = readl(base + CSPI_2_3_RXDATA);
+
+	return 0;
 }
 
 static unsigned int cspi_2_3_clkdiv(unsigned int fin, unsigned int fspi)
@@ -336,16 +361,20 @@
 		gpio_set_value(gpio, gpio_cs);
 }
 
-static u32 imx_xchg_single(struct spi_device *spi, u32 tx_val)
+static int imx_xchg_single(struct spi_device *spi, u32 tx_val, u32* rx_val)
 {
-	u32 rx_val;
 	struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
-
+	u32 local_rx_val;
+	int ret;
 
 	tx_val = imx_spi_maybe_reverse_bits(spi, tx_val);
-	rx_val = imx->xchg_single(imx, tx_val);
+	ret = imx->xchg_single(imx, tx_val, &local_rx_val);
+	if (ret)
+		return ret;
 
-	return imx_spi_maybe_reverse_bits(spi, rx_val);
+	*rx_val = imx_spi_maybe_reverse_bits(spi, local_rx_val);
+
+	return 0;
 }
 
 static void cspi_2_3_init(struct imx_spi *imx)
@@ -355,18 +384,21 @@
 	writel(0, base + CSPI_2_3_CTRL);
 }
 
-static void imx_spi_do_transfer(struct spi_device *spi)
+static int imx_spi_do_transfer(struct spi_device *spi)
 {
 	struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
 	unsigned i;
+	u32 rx_val;
+	int ret;
 
 	if (imx->bits_per_word <= 8) {
 		const u8	*tx_buf = imx->tx_buf;
 		u8		*rx_buf = imx->rx_buf;
-		u8		rx_val;
 
 		for (i = 0; i < imx->xfer_len; i++) {
-			rx_val = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0);
+			ret = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0, &rx_val);
+			if (ret)
+				return ret;
 
 			if (rx_buf)
 				rx_buf[i] = rx_val;
@@ -374,10 +406,11 @@
 	} else if (imx->bits_per_word <= 16) {
 		const u16	*tx_buf = imx->tx_buf;
 		u16		*rx_buf = imx->rx_buf;
-		u16		rx_val;
 
 		for (i = 0; i < imx->xfer_len >> 1; i++) {
-			rx_val = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0);
+			ret = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0, &rx_val);
+			if (ret)
+				return ret;
 
 			if (rx_buf)
 				rx_buf[i] = rx_val;
@@ -385,15 +418,18 @@
 	} else if (imx->bits_per_word <= 32) {
 		const u32	*tx_buf = imx->tx_buf;
 		u32		*rx_buf = imx->rx_buf;
-		u32		rx_val;
 
 		for (i = 0; i < imx->xfer_len >> 2; i++) {
-			rx_val = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0);
+			ret = imx_xchg_single(spi, tx_buf ? tx_buf[i] : 0, &rx_val);
+			if (ret)
+				return ret;
 
 			if (rx_buf)
 				rx_buf[i] = rx_val;
 		}
 	}
+
+	return 0;
 }
 
 static int cspi_2_3_xchg_burst(struct spi_device *spi)
@@ -448,7 +484,7 @@
 	return now;
 }
 
-static void cspi_2_3_do_transfer(struct spi_device *spi)
+static int cspi_2_3_do_transfer(struct spi_device *spi)
 {
 	struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
 	u32 ctrl;
@@ -457,14 +493,14 @@
 		while (cspi_2_3_xchg_burst(spi) > 0);
 
 	if (!imx->xfer_len)
-		return;
+		return 0;
 
 	ctrl = readl(imx->regs + CSPI_2_3_CTRL);
 	ctrl &= ~(0xfff << CSPI_2_3_CTRL_BL_OFFSET);
 	ctrl |= (spi->bits_per_word - 1) << CSPI_2_3_CTRL_BL_OFFSET;
 	writel(ctrl, imx->regs + CSPI_2_3_CTRL);
 
-	imx_spi_do_transfer(spi);
+	return imx_spi_do_transfer(spi);
 }
 
 static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
@@ -473,6 +509,7 @@
 	struct spi_transfer *t;
 	unsigned int cs_change;
 	const int nsecs = 50;
+	int ret;
 
 	imx->chipselect(spi, 1);
 
@@ -494,7 +531,9 @@
 		imx->rx_buf = t->rx_buf;
 		imx->xfer_len = t->len;
 		imx->bits_per_word = spi->bits_per_word;
-		imx->do_transfer(spi);
+		ret = imx->do_transfer(spi);
+		if (ret)
+			return ret;
 
 		mesg->actual_length += t->len;
 
diff --git a/scripts/imx/imx-image.c b/scripts/imx/imx-image.c
index dd5799c..b241e8c 100644
--- a/scripts/imx/imx-image.c
+++ b/scripts/imx/imx-image.c
@@ -762,10 +762,6 @@
 		create_usb_image = 0;
 	}
 
-	buf = calloc(1, HEADER_LEN);
-	if (!buf)
-		exit(1);
-
 	if (data.image_dcd_offset == 0xffffffff) {
 		if (create_usb_image)
 			data.image_dcd_offset = 0x0;
@@ -790,6 +786,10 @@
 
 	switch (data.header_version) {
 	case 1:
+		buf = calloc(1, HEADER_LEN);
+		if (!buf)
+			exit(1);
+
 		add_header_v1(&data, buf);
 		if (data.srkfile) {
 			ret = add_srk(buf, data.image_dcd_offset, data.image_load_addr,
@@ -799,6 +799,10 @@
 		}
 		break;
 	case 2:
+		buf = calloc(1, data.image_dcd_offset + sizeof(struct imx_flash_header_v2) + MAX_DCD * sizeof(u32));
+		if (!buf)
+			exit(1);
+
 		add_header_v2(&data, buf);
 		break;
 	default: