diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index aeb5c04..a2d443f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -68,6 +68,7 @@ select COMMON_CLK_OF_PROVIDER select CLKDEV_LOOKUP select OFTREE + select GPIOLIB config MACH_MIPS_BCM47XX bool "Broadcom BCM47xx-based boards" diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S index 7e2ae5e..1ddce95 100644 --- a/arch/mips/boot/start.S +++ b/arch/mips/boot/start.S @@ -1,8 +1,7 @@ /* * Startup Code for MIPS CPU * - * Copyright (C) 2011 Antony Pavlov - * Used code copyrighted (C) 2009 by Shinya Kuribayashi + * Copyright (C) 2011, 2015 Antony Pavlov * * This file is part of barebox. * See file CREDITS for list of people who contributed to this project. @@ -18,32 +17,7 @@ * */ -#include -#include -#include -#include -#include -#include - - /* - * ADR macro instruction (inspired by ARM) - * - * ARM architecture doesn't have PC-relative jump instruction - * like MIPS' B/BAL insns. When ARM makes PC-relative jumps, - * it uses ADR insn. ADR is used to get a destination address - * of 'label' against current PC. With this, ARM can safely - * make PC-relative jumps. - */ - .macro ADR rd label temp - .set push - .set noreorder - move \temp, ra # preserve ra beforehand - bal _pc - nop -_pc: addiu \rd, ra, \label - _pc # label is assumed to be - move ra, \temp # within pc +/- 32KB - .set pop - .endm +#include .set noreorder .text @@ -52,91 +26,23 @@ EXPORT(_start) - b __start - nop + mips_barebox_10h - .org 0x10 - .ascii "barebox " UTS_RELEASE " " UTS_VERSION - .byte 0 - - .align 4 -__start: /* disable watchpoints */ mtc0 zero, CP0_WATCHLO mtc0 zero, CP0_WATCHHI - /* disable interrupts */ - mfc0 k0, CP0_STATUS - li k1, ~ST0_IE - and k0, k1 - mtc0 k0, CP0_STATUS + mips_disable_interrupts - /* copy barebox to link location */ - ADR a0, _start, t1 /* a0 <- pc-relative position of _start */ + copy_to_link_location _start - la a1, _start /* link (RAM) _start address */ - - beq a0, a1, stack_setup - nop - - la t0, _start - la t1, __bss_start - subu t2, t1, t0 /* t2 <- size of barebox */ - addu a2, a0, t2 /* a2 <- source end address */ - -#define LONGSIZE 4 - -copy_loop: - /* copy from source address [a0] */ - lw t4, LONGSIZE * 0(a0) - lw t5, LONGSIZE * 1(a0) - lw t6, LONGSIZE * 2(a0) - lw t7, LONGSIZE * 3(a0) - /* copy fo target address [a1] */ - sw t4, LONGSIZE * 0(a1) - sw t5, LONGSIZE * 1(a1) - sw t6, LONGSIZE * 2(a1) - sw t7, LONGSIZE * 3(a1) - addi a0, LONGSIZE * 4 - subu t3, a0, a2 - blez t3, copy_loop - addi a1, LONGSIZE * 4 - - /* - * Dominic Sweetman, See MIPS Run, Morgan Kaufmann, 2nd edition, 2006 - * - * 11.2.2 Stack Argument Structure in o32 - * ... - * At the point where a function is called, sp must be - * eight-byte-aligned, matching the alignment of the largest - * basic types -- a long long integer or a floating-point double. - * The eight-byte alignment is not required by 32-bit MIPS integer - * hardware, but it's essential for compatibility with CPUs with - * 64-bit registers, and thus part of the rules. Subroutines fit - * in with this by always adjusting the stack pointer by a multiple - * of eight. - * ... - * SGI's n32 and n64 standards call for the stack to be maintained - * with 16-byte alignment. - * - */ - -#if (STACK_BASE + STACK_SIZE) % 16 != 0 -#error stack pointer must be 16-byte-aligned -#endif - -stack_setup: - la sp, STACK_BASE + STACK_SIZE - - /* reserve four 32-bit argument slots */ - addiu sp, -16 + stack_setup la v0, main_entry - jal v0 + jal v0 nop /* No return */ - __error: b __error nop diff --git a/arch/mips/configs/tplink-mr3020_defconfig b/arch/mips/configs/tplink-mr3020_defconfig index 9f81ce3..b675993 100644 --- a/arch/mips/configs/tplink-mr3020_defconfig +++ b/arch/mips/configs/tplink-mr3020_defconfig @@ -1,34 +1,40 @@ CONFIG_BUILTIN_DTB=y CONFIG_BUILTIN_DTB_NAME="tplink-mr3020" CONFIG_MACH_MIPS_ATH79=y -CONFIG_LONGHELP=y CONFIG_CMDLINE_EDITING=y CONFIG_AUTO_COMPLETE=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_SLEEP=y -CONFIG_CMD_LET=y -CONFIG_CMD_GLOBAL=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_BOOTM is not set +CONFIG_CMD_GO=y CONFIG_CMD_LOADB=y CONFIG_CMD_LOADY=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_MM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_FLASH=y -# CONFIG_CMD_BOOTM is not set CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_OF_PROPERTY=y -CONFIG_CMD_OF_NODE=y -CONFIG_CMD_SPI=y +CONFIG_CMD_GLOBAL=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_LET=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MM=y CONFIG_CMD_CLK=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_LED=y +CONFIG_CMD_SPI=y +CONFIG_CMD_LED_TRIGGER=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y CONFIG_OFDEVICE=y CONFIG_DRIVER_SERIAL_AR933X=y CONFIG_DRIVER_SPI_ATH79=y CONFIG_MTD=y # CONFIG_MTD_OOB_DEVICE is not set CONFIG_MTD_M25P80=y -CONFIG_MD5=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y CONFIG_DIGEST_SHA224_GENERIC=y CONFIG_DIGEST_SHA256_GENERIC=y diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi index 8e7afcd..99ede9e 100644 --- a/arch/mips/dts/ar9331.dtsi +++ b/arch/mips/dts/ar9331.dtsi @@ -17,6 +17,16 @@ status = "disabled"; }; + gpio: gpio@18040000 { + compatible = "qca,ar7100-gpio"; + gpio-controller; + reg = <0x18040000 0x100>; + #gpio-cells = <2>; + + ngpios = <30>; + status = "disabled"; + }; + ar9331_clk: clock { compatible = "qca,ar933x-clk"; reg = <0x18050000 0x48>; diff --git a/arch/mips/dts/tplink-mr3020.dts b/arch/mips/dts/tplink-mr3020.dts index 41be352..804d290 100644 --- a/arch/mips/dts/tplink-mr3020.dts +++ b/arch/mips/dts/tplink-mr3020.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "ar9331.dtsi" +#include / { model = "TP-LINK MR3020"; @@ -9,12 +10,48 @@ memory { reg = <0x00000000 0x2000000>; }; + + aliases { + spiflash = &spiflash; + }; + + leds { + compatible = "gpio-leds"; + + wlan { + label = "tp-link:green:wlan"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + lan { + label = "tp-link:green:lan"; + gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + wps { + label = "tp-link:green:wps"; + gpios = <&gpio 26 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led3g { + label = "tp-link:green:3g"; + gpios = <&gpio 27 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; &serial0 { status = "okay"; }; +&gpio { + status = "okay"; +}; + &spi { num-chipselects = <1>; status = "okay"; @@ -28,9 +65,3 @@ reg = <0>; }; }; - -/ { - aliases { - spiflash = &spiflash; - }; -}; diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile index 71c4f6b..0145f35 100644 --- a/arch/mips/lib/Makefile +++ b/arch/mips/lib/Makefile @@ -12,3 +12,5 @@ obj-$(CONFIG_CMD_MIPS_CPUINFO) += cpuinfo.o obj-$(CONFIG_CMD_BOOTM) += bootm.o + +pbl-y += ashldi3.o diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 0c6ddd6..b82a8c3 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -15,10 +15,16 @@ #ifndef __ASM_MACH_AR71XX_REGS_H #define __ASM_MACH_AR71XX_REGS_H +#ifndef __ASSEMBLER__ #include +#else +#define BIT(nr) (1 << (nr)) +#endif #define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) #define AR71XX_PLL_SIZE 0x100 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) @@ -28,6 +34,21 @@ #define AR933X_UART_SIZE 0x14 /* + * GPIO block + */ +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 + +/* * PLL block */ #define AR933X_PLL_CPU_CONFIG_REG 0x00 diff --git a/arch/mips/mach-ath79/include/mach/debug_ll.h b/arch/mips/mach-ath79/include/mach/debug_ll.h index 64db674..d3813af 100644 --- a/arch/mips/mach-ath79/include/mach/debug_ll.h +++ b/arch/mips/mach-ath79/include/mach/debug_ll.h @@ -19,10 +19,7 @@ #define __AR933X_DEBUG_LL__ #include - -/* Alas! isn't assembly-tolerant */ -#define AR71XX_APB_BASE 0x18000000 -#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) +#include #define DEBUG_LL_UART_ADDR KSEG1ADDR(AR933X_UART_BASE) diff --git a/arch/mips/pbl/.gitignore b/arch/mips/pbl/.gitignore index 1b7f618..be604a8 100644 --- a/arch/mips/pbl/.gitignore +++ b/arch/mips/pbl/.gitignore @@ -1,6 +1,8 @@ piggy.gzip piggy.lzo piggy.lz4 +piggy.xzkern +piggy.shipped zbarebox zbarebox.bin zbarebox.lds diff --git a/arch/mips/pbl/Makefile b/arch/mips/pbl/Makefile index b03bca1..44ce3d1 100644 --- a/arch/mips/pbl/Makefile +++ b/arch/mips/pbl/Makefile @@ -2,6 +2,7 @@ suffix_$(CONFIG_IMAGE_COMPRESSION_GZIP) = gzip suffix_$(CONFIG_IMAGE_COMPRESSION_LZO) = lzo suffix_$(CONFIG_IMAGE_COMPRESSION_LZ4) = lz4 +suffix_$(CONFIG_IMAGE_COMPRESSION_XZKERN) = xzkern suffix_$(CONFIG_IMAGE_COMPRESSION_NONE) = shipped OBJCOPYFLAGS_zbarebox.bin = -O binary diff --git a/arch/mips/pbl/piggy.xzkern.S b/arch/mips/pbl/piggy.xzkern.S new file mode 100644 index 0000000..edfa53b --- /dev/null +++ b/arch/mips/pbl/piggy.xzkern.S @@ -0,0 +1,6 @@ +#include + + .section .data +EXPORT(input_data) + .incbin "arch/mips/pbl/piggy.xzkern" +EXPORT(input_data_end) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 1d94661..f39e8da 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_GPIOLIB) += gpiolib.o obj-$(CONFIG_GPIO_74164) += gpio-74164.o +obj-$(CONFIG_MACH_MIPS_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_BCM2835) += gpio-bcm2835.o obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o diff --git a/drivers/gpio/gpio-ath79.c b/drivers/gpio/gpio-ath79.c new file mode 100644 index 0000000..a1e42c4 --- /dev/null +++ b/drivers/gpio/gpio-ath79.c @@ -0,0 +1,156 @@ +/* + * Atheros AR71XX/AR724X/AR913X GPIO API support + * + * Copyright (C) 2010-2011 Jaiganesh Narayanan + * Copyright (C) 2008-2011 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * Copyright (C) 2015 Antony Pavlov + * + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include +#include + +static void __iomem *ath79_gpio_base; +static u32 ath79_gpio_count; + +static void __ath79_gpio_set_value(unsigned gpio, int value) +{ + void __iomem *base = ath79_gpio_base; + + if (value) + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); +} + +static int __ath79_gpio_get_value(unsigned gpio) +{ + return (__raw_readl(ath79_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1; +} + +static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned offset) +{ + return __ath79_gpio_get_value(offset); +} + +static void ath79_gpio_set_value(struct gpio_chip *chip, + unsigned offset, int value) +{ + __ath79_gpio_set_value(offset, value); +} + +static int ath79_gpio_direction_input(struct gpio_chip *chip, + unsigned offset) +{ + void __iomem *base = ath79_gpio_base; + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), + base + AR71XX_GPIO_REG_OE); + + return 0; +} + +static int ath79_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + void __iomem *base = ath79_gpio_base; + + if (value) + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); + else + __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); + + __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), + base + AR71XX_GPIO_REG_OE); + + return 0; +} + +static int ath79_gpio_get_direction(struct gpio_chip *chip, unsigned offset) +{ + + void __iomem *base = ath79_gpio_base; + uint32_t oe = __raw_readl(base + AR71XX_GPIO_REG_OE); + + return (oe & (1 << offset)) ? GPIOF_DIR_OUT : GPIOF_DIR_IN; +} + +static struct gpio_ops ath79_gpio_ops = { + .get = ath79_gpio_get_value, + .set = ath79_gpio_set_value, + .direction_input = ath79_gpio_direction_input, + .direction_output = ath79_gpio_direction_output, + .get_direction = ath79_gpio_get_direction, +}; + +static struct gpio_chip ath79_gpio_chip = { + .ops = &ath79_gpio_ops, + .base = 0, +}; + +static const struct of_device_id ath79_gpio_of_match[] = { + { .compatible = "qca,ar7100-gpio" }, + {}, +}; + +static int ath79_gpio_probe(struct device_d *dev) +{ + struct device_node *np = dev->device_node; + int err; + + if (!np) { + dev_err(dev, "No DT node or platform data found\n"); + return -EINVAL; + } + + err = of_property_read_u32(np, "ngpios", &ath79_gpio_count); + if (err) { + dev_err(dev, "ngpios property is not valid\n"); + return err; + } + if (ath79_gpio_count >= 32) { + dev_err(dev, "ngpios must be less than 32\n"); + return -EINVAL; + } + + ath79_gpio_base = dev_request_mem_region(dev, 0); + if (IS_ERR(ath79_gpio_base)) { + dev_err(dev, "could not get memory region\n"); + return PTR_ERR(ath79_gpio_base); + } + + ath79_gpio_chip.dev = dev; + ath79_gpio_chip.ngpio = ath79_gpio_count; + + err = gpiochip_add(&ath79_gpio_chip); + if (err) { + dev_err(dev, "cannot add AR71xx GPIO chip, error=%d", err); + return err; + } + + return 0; +} + +static struct driver_d ath79_gpio_driver = { + .name = "ath79-gpio", + .probe = ath79_gpio_probe, + .of_compatible = DRV_OF_COMPAT(ath79_gpio_of_match), +}; + +static int ath79_gpio_init(void) +{ + return platform_driver_register(&ath79_gpio_driver); +} +coredevice_initcall(ath79_gpio_init);