diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 91025d8..93619d5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -165,14 +165,16 @@ bool "NVIDIA Tegra" select CPU_V7 select HAS_DEBUG_LL - select BUILTIN_DTB select COMMON_CLK select COMMON_CLK_OF_PROVIDER select CLKDEV_LOOKUP select GPIOLIB select GPIO_TEGRA + select HAVE_DEFAULT_ENVIRONMENT_NEW + select HAVE_PBL_MULTI_IMAGES select OFDEVICE select OFTREE + select RELOCATABLE config ARCH_ZYNQ bool "Xilinx Zynq-based boards" diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 2210fd4..c273f0c 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/ +obj-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += toradex-colibri-t20-iris/ obj-$(CONFIG_MACH_TOSHIBA_AC100) += toshiba-ac100/ obj-$(CONFIG_MACH_TQMA53) += tqma53/ obj-$(CONFIG_MACH_TQMA6X) += tqma6x/ diff --git a/arch/arm/boards/toradex-colibri-t20-iris/Makefile b/arch/arm/boards/toradex-colibri-t20-iris/Makefile new file mode 100644 index 0000000..5be3dd0 --- /dev/null +++ b/arch/arm/boards/toradex-colibri-t20-iris/Makefile @@ -0,0 +1,2 @@ +CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t +lwl-y += entry.o diff --git a/arch/arm/boards/toradex-colibri-t20-iris/entry.c b/arch/arm/boards/toradex-colibri-t20-iris/entry.c new file mode 100644 index 0000000..30a13e0 --- /dev/null +++ b/arch/arm/boards/toradex-colibri-t20-iris/entry.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013 Lucas Stach + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +extern char __dtb_tegra20_colibri_iris_start[]; + +ENTRY_FUNCTION(start_toradex_colibri_t20_iris)(void) +{ + uint32_t fdt; + + __barebox_arm_head(); + + tegra_cpu_lowlevel_setup(); + + fdt = (uint32_t)__dtb_tegra20_colibri_iris_start - get_runtime_offset(); + + tegra_avp_reset_vector(fdt); +} diff --git a/arch/arm/boards/toshiba-ac100/Kconfig b/arch/arm/boards/toshiba-ac100/Kconfig deleted file mode 100644 index 1cc13f0..0000000 --- a/arch/arm/boards/toshiba-ac100/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -if MACH_TOSHIBA_AC100 - -config ARCH_TEXT_BASE - hex - default 0x01000000 - -endif diff --git a/arch/arm/boards/toshiba-ac100/Makefile b/arch/arm/boards/toshiba-ac100/Makefile index dcfc293..4ef18c0 100644 --- a/arch/arm/boards/toshiba-ac100/Makefile +++ b/arch/arm/boards/toshiba-ac100/Makefile @@ -1 +1,3 @@ +CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t +lwl-y += entry.o obj-y += board.o diff --git a/arch/arm/boards/toshiba-ac100/entry.c b/arch/arm/boards/toshiba-ac100/entry.c new file mode 100644 index 0000000..372d596 --- /dev/null +++ b/arch/arm/boards/toshiba-ac100/entry.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2013 Lucas Stach + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +extern char __dtb_tegra20_paz00_start[]; + +ENTRY_FUNCTION(start_toshiba_ac100)(void) +{ + uint32_t fdt; + + __barebox_arm_head(); + + tegra_cpu_lowlevel_setup(); + + fdt = (uint32_t)__dtb_tegra20_paz00_start - get_runtime_offset(); + + tegra_avp_reset_vector(fdt); +} diff --git a/arch/arm/configs/tegra20_colibri_iris_defconfig b/arch/arm/configs/tegra20_colibri_iris_defconfig deleted file mode 100644 index 37a0e8a..0000000 --- a/arch/arm/configs/tegra20_colibri_iris_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_BUILTIN_DTB_NAME="tegra20-colibri-iris" -CONFIG_ARCH_TEGRA=y -CONFIG_AEABI=y -CONFIG_CMD_ARM_MMUINFO=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_STACK_SIZE=0x10000 -CONFIG_MALLOC_SIZE=0x4000000 -CONFIG_LONGHELP=y -CONFIG_GLOB=y -CONFIG_GLOB_SORT=y -CONFIG_HUSH_FANCY_PROMPT=y -CONFIG_HUSH_GETOPT=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -CONFIG_CMD_EDIT=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_IOMEM=y -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_RESET=y -CONFIG_CMD_OFTREE=y -CONFIG_CMD_TIMEOUT=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_CLK=y -CONFIG_DRIVER_SERIAL_NS16550=y diff --git a/arch/arm/configs/tegra_v7_defconfig b/arch/arm/configs/tegra_v7_defconfig new file mode 100644 index 0000000..677a955 --- /dev/null +++ b/arch/arm/configs/tegra_v7_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARCH_TEGRA=y +CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS=y +CONFIG_MACH_TOSHIBA_AC100=y +CONFIG_AEABI=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_STACK_SIZE=0x10000 +CONFIG_MALLOC_SIZE=0x4000000 +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_RESET=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_CLK=y +CONFIG_DRIVER_SERIAL_NS16550=y diff --git a/arch/arm/configs/toshiba_ac100_defconfig b/arch/arm/configs/toshiba_ac100_defconfig deleted file mode 100644 index 1903910..0000000 --- a/arch/arm/configs/toshiba_ac100_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -CONFIG_BUILTIN_DTB_NAME="tegra20-paz00" -CONFIG_ARCH_TEGRA=y -CONFIG_TEGRA_UART_A=y -CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y -CONFIG_TEXT_BASE=0x01000000 -CONFIG_BROKEN=y -CONFIG_EXPERIMENTAL=y -CONFIG_PROMPT="toshiba ac100> " -CONFIG_LONGHELP=y -CONFIG_CMDLINE_EDITING=y -CONFIG_AUTO_COMPLETE=y -# CONFIG_ERRNO_MESSAGES is not set -# CONFIG_DEFAULT_ENVIRONMENT is not set -CONFIG_POLLER=y -CONFIG_ENABLE_DEVICE_NOISE=y -CONFIG_CMD_SLEEP=y -# CONFIG_CMD_TRUE is not set -# CONFIG_CMD_FALSE is not set -CONFIG_CMD_TFTP=y -CONFIG_CMD_LOADB=y -CONFIG_CMD_LOADY=y -CONFIG_CMD_LOADS=y -CONFIG_CMD_MEMINFO=y -CONFIG_CMD_MD5SUM=y -CONFIG_CMD_SHA1SUM=y -CONFIG_CMD_BOOTM_SHOW_TYPE=y -CONFIG_CMD_RESET=y -CONFIG_CMD_GO=y -CONFIG_CMD_OFTREE=y -CONFIG_NET=y -CONFIG_NET_DHCP=y -CONFIG_NET_PING=y -CONFIG_NET_NETCONSOLE=y -CONFIG_DRIVER_SERIAL_NS16550=y -CONFIG_NET_USB=y -CONFIG_NET_USB_ASIX=y -# CONFIG_SPI is not set -CONFIG_USB=y -CONFIG_USB_EHCI=y -CONFIG_USB_STORAGE=y -CONFIG_FS_TFTP=y -CONFIG_FS_FAT=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7782874..511adf4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -13,6 +13,9 @@ dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb +dtb-$(CONFIG_ARCH_TEGRA) += \ + tegra20-colibri-iris.dtb \ + tegra20-paz00.dtb BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o @@ -25,6 +28,8 @@ pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o +pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += tegra20-colibri-iris.dtb.o +pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index e6d53bc..3becb84 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,13 +1,11 @@ if ARCH_TEGRA -choice - prompt "Tegra processor type" +config ARCH_TEXT_BASE + hex + default 0x0 -config ARCH_TEGRA_2x_SOC - bool "Tegra 20" - select PINCTRL_TEGRA20 - -endchoice +config BOARDINFO + default "" choice prompt "Tegra debug UART" @@ -44,34 +42,21 @@ # --------------------------------------------------------- -if ARCH_TEGRA_2x_SOC +config ARCH_TEGRA_2x_SOC + bool + select PINCTRL_TEGRA20 -config ARCH_TEXT_BASE - hex - default 0x00108000 +menu "select Tegra boards to be built" -choice - prompt "Tegra 20 Board Type" - -config MACH_TEGRA20_GENERIC - bool "Generic DT based board" - help - Say Y here if you are building for a generic DT based board. +config MACH_TORADEX_COLIBRI_T20_IRIS + bool "Toradex Colibri T20 on Iris Carrier" + select ARCH_TEGRA_2x_SOC config MACH_TOSHIBA_AC100 bool "Toshiba AC100" - help - Say Y here if you are using Toshiba AC100 smartbook. + select ARCH_TEGRA_2x_SOC -endchoice - -if MACH_TEGRA20_GENERIC - -endif #MACH_TEGRA20_GENERIC - -source arch/arm/boards/toshiba-ac100/Kconfig - -endif #ARCH_TEGRA_2x_SOC +endmenu # --------------------------------------------------------- diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index fd6a870..0fa8430 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,4 +1,5 @@ CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t +CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t lwl-y += tegra_avp_init.o lwl-y += tegra_maincomplex_init.o obj-y += tegra20.o diff --git a/arch/arm/mach-tegra/include/mach/lowlevel.h b/arch/arm/mach-tegra/include/mach/lowlevel.h index 071416f..472348a 100644 --- a/arch/arm/mach-tegra/include/mach/lowlevel.h +++ b/arch/arm/mach-tegra/include/mach/lowlevel.h @@ -40,7 +40,8 @@ #define T20_ODMDATA_UARTID_SHIFT 15 #define T20_ODMDATA_UARTID_MASK (7 << T20_ODMDATA_UARTID_SHIFT) -static inline u32 tegra_get_odmdata(void) +static inline __attribute__((always_inline)) +u32 tegra_get_odmdata(void) { u32 bctsize, bctptr, odmdata; @@ -62,7 +63,8 @@ TEGRA20 = 0, }; -static inline enum tegra_chiptype tegra_get_chiptype(void) +static inline __attribute__((always_inline)) +enum tegra_chiptype tegra_get_chiptype(void) { u32 hidrev; @@ -76,7 +78,8 @@ } } -static inline int tegra_get_num_cores(void) +static inline __attribute__((always_inline)) +int tegra_get_num_cores(void) { switch (tegra_get_chiptype()) { case TEGRA20: @@ -89,7 +92,8 @@ } /* Runtime data */ -static inline int tegra_cpu_is_maincomplex(void) +static inline __attribute__((always_inline)) +int tegra_cpu_is_maincomplex(void) { u32 tag0; @@ -98,7 +102,8 @@ return (tag0 & 0xff) == 0x55; } -static inline uint32_t tegra20_get_ramsize(void) +static inline __attribute__((always_inline)) +uint32_t tegra20_get_ramsize(void) { switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >> T20_ODMDATA_RAMSIZE_SHIFT) { @@ -120,7 +125,8 @@ TEGRA_UARTE_BASE, }; -static inline long tegra20_get_debuguart_base(void) +static inline __attribute__((always_inline)) +long tegra20_get_debuguart_base(void) { u32 odmdata; int id; @@ -146,7 +152,8 @@ #define CRC_OSC_CTRL_OSC_FREQ_SHIFT 30 #define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT) -static inline unsigned int tegra_get_osc_clock(void) +static inline unsigned __attribute__((always_inline)) +int tegra_get_osc_clock(void) { u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL); @@ -165,5 +172,20 @@ } } +static inline __attribute__((always_inline)) +void tegra_cpu_lowlevel_setup(void) +{ + uint32_t r; + + /* set the cpu to SVC32 mode */ + __asm__ __volatile__("mrs %0, cpsr":"=r"(r)); + r &= ~0x1f; + r |= 0xd3; + __asm__ __volatile__("msr cpsr, %0" : : "r"(r)); +} + +/* reset vector for the AVP, to be called from board reset vector */ +void tegra_avp_reset_vector(uint32_t boarddata); + /* reset vector for the main CPU complex */ void tegra_maincomplex_entry(void); diff --git a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h b/arch/arm/mach-tegra/include/mach/tegra20-pmc.h index d56b845..3a05e0f 100644 --- a/arch/arm/mach-tegra/include/mach/tegra20-pmc.h +++ b/arch/arm/mach-tegra/include/mach/tegra20-pmc.h @@ -65,3 +65,5 @@ #define PMC_PWRGATE_STATUS_VE (1 << 2) #define PMC_PWRGATE_STATUS_TD (1 << 1) #define PMC_PWRGATE_STATUS_CPU (1 << 0) + +#define PMC_SCRATCH(i) (0x050 + 0x4*i) diff --git a/arch/arm/mach-tegra/tegra_avp_init.c b/arch/arm/mach-tegra/tegra_avp_init.c index 5099e91..6cabdb3 100644 --- a/arch/arm/mach-tegra/tegra_avp_init.c +++ b/arch/arm/mach-tegra/tegra_avp_init.c @@ -19,21 +19,11 @@ #include #include +#include #include #include #include -static inline void tegra_cpu_lowlevel_setup(void) -{ - uint32_t r; - - /* set the cpu to SVC32 mode */ - __asm__ __volatile__("mrs %0, cpsr":"=r"(r)); - r &= ~0x1f; - r |= 0xd3; - __asm__ __volatile__("msr cpsr, %0" : : "r"(r)); -} - /* instruct the PMIC to enable the CPU power rail */ static void enable_maincomplex_powerrail(void) { @@ -108,8 +98,6 @@ return; chiptype = tegra_get_chiptype(); - if (chiptype < 0) - BUG(); osc_freq = (readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL) & CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT; @@ -187,24 +175,12 @@ writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD); } } -void barebox_arm_reset_vector(void) +void tegra_avp_reset_vector(uint32_t boarddata) { int num_cores; - /* minimal initialization, OK for both ARMv4 and ARMv7 */ - tegra_cpu_lowlevel_setup(); - - /* - * If we are already running on the main CPU complex jump straight - * to the maincomplex entry point. - */ - if (tegra_cpu_is_maincomplex()) - tegra_maincomplex_entry(); - /* get the number of cores in the main CPU complex of the current SoC */ num_cores = tegra_get_num_cores(); - if (!num_cores) - BUG(); /* bring down main CPU complex (this may be a warm boot) */ enable_maincomplex_powerrail(); @@ -212,7 +188,11 @@ stop_maincomplex_clocks(num_cores); /* set start address for the main CPU complex processors */ - writel(barebox_arm_head, TEGRA_EXCEPTION_VECTORS_BASE + 0x100); + writel(tegra_maincomplex_entry - get_runtime_offset(), + TEGRA_EXCEPTION_VECTORS_BASE + 0x100); + + /* put boarddata in scratch reg, for main CPU to fetch after startup */ + writel(boarddata, TEGRA_PMC_BASE + PMC_SCRATCH(10)); /* bring up main CPU complex */ start_cpu0_clocks(); diff --git a/arch/arm/mach-tegra/tegra_maincomplex_init.c b/arch/arm/mach-tegra/tegra_maincomplex_init.c index dea9c91..b3d59ab 100644 --- a/arch/arm/mach-tegra/tegra_maincomplex_init.c +++ b/arch/arm/mach-tegra/tegra_maincomplex_init.c @@ -19,6 +19,7 @@ #include #include #include +#include void tegra_maincomplex_entry(void) { @@ -33,14 +34,9 @@ break; default: /* If we don't know the chiptype, better bail out */ - BUG(); + unreachable(); } - /* - * The standard load address for Tegra systems is 0x10800 which means - * the barebox binary will always be below the malloc area for all - * reasonable malloc area sizes. We offset the RAM base address by 8MB - * to pretend barebox is in another bank. - */ - barebox_arm_entry(rambase + SZ_8M, ramsize - SZ_8M, 0); + barebox_arm_entry(rambase, ramsize, + readl(TEGRA_PMC_BASE + PMC_SCRATCH(10))); } diff --git a/images/Makefile b/images/Makefile index e6732bf..ec033ab 100644 --- a/images/Makefile +++ b/images/Makefile @@ -109,6 +109,7 @@ include $(srctree)/images/Makefile.imx include $(srctree)/images/Makefile.mvebu include $(srctree)/images/Makefile.socfpga +include $(srctree)/images/Makefile.tegra targets += $(image-y) pbl.lds barebox.x barebox.z targets += $(patsubst %,%.pblx,$(pblx-y)) diff --git a/images/Makefile.tegra b/images/Makefile.tegra new file mode 100644 index 0000000..1cf1432 --- /dev/null +++ b/images/Makefile.tegra @@ -0,0 +1,14 @@ +# +# barebox image generation Makefile for Tegra images +# + +board = $(srctree)/arch/$(ARCH)/boards + +# ----------------------- Tegra20 based boards --------------------------- +pblx-$(CONFIG_MACH_TOSHIBA_AC100) += start_toshiba_ac100 +FILE_barebox-tegra20-toshiba-ac100.img = start_toshiba_ac100.pblx +image-$(CONFIG_MACH_TOSHIBA_AC100) += barebox-tegra20-toshiba-ac100.img + +pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += start_toradex_colibri_t20_iris +FILE_barebox-tegra20-toradex-colibri-t20-iris.img = start_toradex_colibri_t20_iris.pblx +image-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += barebox-tegra20-toradex-colibri-t20-iris.img