diff --git a/Documentation/boards/imx.rst b/Documentation/boards/imx.rst
index 71cc6bb..8fe0a28 100644
--- a/Documentation/boards/imx.rst
+++ b/Documentation/boards/imx.rst
@@ -142,6 +142,79 @@
 
 Analogous to HABv4 options and a template exist for HABv3.
 
+Secure Boot on i.MX6
+~~~~~~~~~~~~~~~~~~~~
+
+For most boards, the secure boot process on i.MX6 consist of the following image
+constellation::
+
+    0x0 +---------------------------------+
+        | Barebox Header                  |
+  0x400 +---------------------------------+       -
+        | i.MX IVT Header                 |       |
+        | Boot Data                       +--+    |
+        | CSF Pointer                     +--|-+  | Signed Area
+        +---------------------------------+  | |  |
+        | Device Configuration Data (DCD) |  | |  |
+ 0x1000 +---------------------------------+  | |  |
+        | Barebox Prebootloader (PBL)     |<-+ |  |
+        +---------------------------------+    |  |
+        | Piggydata (Main Barebox Binary) |    |  |
+        +---------------------------------+    |  -
+        | Command Sequence File (CSF)     |<---+
+        +---------------------------------+
+
+Here the Command Sequence File signs the complete Header, PBL and piggy data
+file. This ensures that the whole barebox binary is authenticated. This is
+possible since the DDR RAM is configured using the DCD and the whole DDR memory
+area can be used to load data onto the device for authentication.
+The boot ROM loads the CSF area and barebox into memory and uses the CSF to
+verify the complete barebox binary.
+
+Boards which do require a boot via SRAM, need changes akin to the implementation
+for i.MX8MQ described in the next chapter.
+
+Secure Boot on i.MX8MQ
+~~~~~~~~~~~~~~~~~~~~~~
+
+For i.MX8MQ the image has the following design::
+
+    0x0 +---------------------------------+
+        | Barebox Header                  |
+        +---------------------------------+
+        | i.MX IVT Header                 |
+        | HDMI Firmware (Signed by NXP)   |
+        +---------------------------------+        -
+        | i.MX IVT Header                 |        |
+        | Boot Data                       +--+     |
+        | CSF Pointer                     +--|-+   |
+        +---------------------------------+  | |   | Signed Area
+        | Device Configuration Data (DCD) |  | |   |
+        +---------------------------------+  | |   |
+        | Barebox Prebootloader (PBL)     |<-+ |   |
+        | Piggydata Hash (SHA256)         +----|-+ |
+        +---------------------------------+    | | -
+        | Command Sequence File (CSF)     |<---+ |
+        +---------------------------------+      | -
+        | Piggydata (Main Barebox Binary) |<-----+ | Hashed Area
+        +---------------------------------+        -
+
+In contrast to i.MX6, for the i.MX8MQ the piggydata can not be signed together
+with the PBL binary. The DDR memory is initialized during the start of the PBL,
+previous to this no access to the DDR memory is possible. Since the Tightly
+Coupled Memory used for early startup on i.MX8MQ has only 256Kib, the whole
+barebox can't be loaded and verified at once, since the complete barebox with
+firmware has a size of ~500Kib.
+
+The bootrom loads the HDMI firmware unconditionally, since it is signed by NXP.
+Afterwards the Prebootloader (PBL) is loaded into SRAM and the bootrom proceeds
+to verify the PBL according to the Command Sequence File (CSF). The verified
+PBL initializes the ARM Trusted Firmware (TF-A) and DDR RAM. It subsequently
+loads the piggydata from the boot media and calculates the sha256sum of the
+piggydata. This is compared to the sha256sum built into the PBL during compile
+time, the PBL will only continue to boot if the sha256sum matches the builtin
+sha256sum.
+
 Using GPT on i.MX
 ^^^^^^^^^^^^^^^^^
 
diff --git a/Documentation/boards/imx/embest-marsboard.rst b/Documentation/boards/imx/embest-marsboard.rst
new file mode 100644
index 0000000..bdaa088
--- /dev/null
+++ b/Documentation/boards/imx/embest-marsboard.rst
@@ -0,0 +1,82 @@
+Embest MarS Board
+=================
+
+Board comes with:
+
+* 1G DDR3 SDRAM
+* 4G eMMC
+* 2M SPI-NOR Flash
+
+Layout::
+
+  .-----------------------------------------------------.
+  |O                                    OTG-->| V |    O|
+  |                              SW1    USB   '---'  .--|
+  |             .-----------.    v.---.           .->| <|
+  |             |           |    1|o--| O         |  `--|
+  |             | i.MX6Dual |    2|--o| N        Debug  |
+  |             |    SoC    |     `---'          USB    |
+  |             |           |                           |
+  |             `-----------'                           |
+  |                                                     |
+  |                                                     |
+  |                                                     |
+  |                                                     |
+  |O                                                   O|
+  `-----------------------------------------------------'
+
+Boot Configuration
+==================
+
+DIP Switch ``SW1`` on the board can be used to set ``BOOT_MODE1`` and
+``BOOT_MODE0`` going to the i.MX6:
+
+Set ``SW1 = 01`` for serial boot::
+
+        SW1
+        v.---.
+        1|o--| O
+        2|--o| N
+         `---'
+
+Set ``SW1 = 10`` for internal (SPI-NOR Flash) boot::
+
+        SW1
+        v.---.
+        1|--o| O
+        2|o--| N
+         `---'
+
+Set ``SW1 = 00`` for boot from eFuses::
+
+        SW1
+        v.---.
+        1|o--| O
+        2|o--| N
+         `---'
+
+Flashing barebox
+----------------
+
+  1. Connect to the board's Debug Mini-USB (115200 8N1)
+
+  2. Set ``SW1 = 01`` for serial boot mode (see above)
+
+  3. Turn board's power on
+
+  4. Upload barebox image to the board via imx-usb-loader
+
+.. code-block:: none
+
+  host$ imx-usb-loader images/barebox-embest-imx6q-marsboard.img
+..
+
+  4. Flash barebox to SPI-NOR Flash via Android Fastboot
+
+.. code-block:: none
+
+  host$ fastboot flash bbu-spiflash images/barebox-embest-imx6q-marsboard.img
+
+..
+
+  5. Restore ``SW1 = 10`` for internal (SPI-NOR) boot (see above)
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index e862db4..6cb40d0 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -36,6 +36,7 @@
 obj-$(CONFIG_MACH_EDB9315)			+= edb93xx/
 obj-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK)		+= efika-mx-smartbook/
 obj-$(CONFIG_MACH_EMBEDSKY_E9)			+= embedsky-e9/
+obj-$(CONFIG_MACH_EMBEST_MARSBOARD)		+= embest-marsboard/
 obj-$(CONFIG_MACH_EMBEST_RIOTBOARD)		+= embest-riotboard/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX25)		+= eukrea_cpuimx25/
 obj-$(CONFIG_MACH_EUKREA_CPUIMX27)		+= eukrea_cpuimx27/
diff --git a/arch/arm/boards/embest-marsboard/Makefile b/arch/arm/boards/embest-marsboard/Makefile
new file mode 100644
index 0000000..ef52194
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/Makefile
@@ -0,0 +1,3 @@
+obj-y += board.o
+lwl-y += lowlevel.o
+bbenv-y += defaultenv-mars
diff --git a/arch/arm/boards/embest-marsboard/board.c b/arch/arm/boards/embest-marsboard/board.c
new file mode 100644
index 0000000..6689343
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/board.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
+ * Copyright (C) 2014 Eric Bénard <eric@eukrea.com>
+ * Copyright (C) 2019 Ahmad Fatoum <a.fatoum@pengutronix.de>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <envfs.h>
+#include <mach/bbu.h>
+#include <linux/phy.h>
+
+static int ar8035_phy_fixup(struct phy_device *dev)
+{
+	u16 val;
+
+	/* Ar803x phy SmartEEE feature cause link status generates glitch,
+	 * which cause ethernet link down/up issue, so disable SmartEEE
+	 */
+	phy_write(dev, 0xd, 0x3);
+	phy_write(dev, 0xe, 0x805d);
+	phy_write(dev, 0xd, 0x4003);
+
+	val = phy_read(dev, 0xe);
+	phy_write(dev, 0xe, val & ~(1 << 8));
+
+	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+	phy_write(dev, 0xd, 0x7);
+	phy_write(dev, 0xe, 0x8016);
+	phy_write(dev, 0xd, 0x4007);
+
+	val = phy_read(dev, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(dev, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(dev, 0x1d, 0x5);
+	val = phy_read(dev, 0x1e);
+	val |= 0x0100;
+	phy_write(dev, 0x1e, val);
+
+	return 0;
+}
+
+static int marsboard_device_init(void)
+{
+	if (!of_machine_is_compatible("embest,imx6q-marsboard"))
+		return 0;
+
+	barebox_set_hostname("marsboard");
+
+	phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
+
+	imx6_bbu_internal_spi_i2c_register_handler("spiflash",
+		"/dev/m25p0.barebox", BBU_HANDLER_FLAG_DEFAULT);
+
+	defaultenv_append_directory(defaultenv_mars);
+
+	return 0;
+}
+device_initcall(marsboard_device_init);
diff --git a/arch/arm/boards/embest-marsboard/defaultenv-mars/init/fastboot b/arch/arm/boards/embest-marsboard/defaultenv-mars/init/fastboot
new file mode 100644
index 0000000..9c784fb
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/defaultenv-mars/init/fastboot
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+if [ "$bootsource" != "serial" ]; then
+    exit 0
+fi
+
+usbgadget -a -A "" -b
diff --git a/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
new file mode 100644
index 0000000..bdaf60c
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/flash-header-embest-marsboard.imxcfg
@@ -0,0 +1,99 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+wm 32 0x020e05a8 0x00000030
+wm 32 0x020e05b0 0x00000030
+wm 32 0x020e0524 0x00000030
+wm 32 0x020e051c 0x00000030
+wm 32 0x020e0518 0x00000030
+wm 32 0x020e050c 0x00000030
+wm 32 0x020e05b8 0x00000030
+wm 32 0x020e05c0 0x00000030
+wm 32 0x020e05ac 0x00020030
+wm 32 0x020e05b4 0x00020030
+wm 32 0x020e0528 0x00020030
+wm 32 0x020e0520 0x00020030
+wm 32 0x020e0514 0x00020030
+wm 32 0x020e0510 0x00020030
+wm 32 0x020e05bc 0x00020030
+wm 32 0x020e05c4 0x00020030
+wm 32 0x020e056c 0x00020030
+wm 32 0x020e0578 0x00020030
+wm 32 0x020e0588 0x00020030
+wm 32 0x020e0594 0x00020030
+wm 32 0x020e057c 0x00020030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00003030
+wm 32 0x020e05a0 0x00003030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e0788 0x00000030
+wm 32 0x020e0794 0x00000030
+wm 32 0x020e079c 0x00000030
+wm 32 0x020e07a0 0x00000030
+wm 32 0x020e07a4 0x00000030
+wm 32 0x020e07a8 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0798 0x000c0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00081740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b000c 0x555a7975
+wm 32 0x021b0010 0xff538e64
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x005b0e21
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x831a0000
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0800 0xa1380003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00022227
+wm 32 0x021b4818 0x00022227
+wm 32 0x021b083c 0x434b0350
+wm 32 0x021b0840 0x034c0359
+wm 32 0x021b483c 0x434b0350
+wm 32 0x021b4840 0x03650348
+wm 32 0x021b0848 0x4436383b
+wm 32 0x021b4848 0x39393341
+wm 32 0x021b0850 0x35373933
+wm 32 0x021b4850 0x48254A36
+wm 32 0x021b080c 0x001f001f
+wm 32 0x021b0810 0x001f001f
+wm 32 0x021b480c 0x00440044
+wm 32 0x021b4810 0x00440044
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+wm 32 0x020c4068 0x00c03f3f
+wm 32 0x020c406c 0x0030fc03
+wm 32 0x020c4070 0x0fffc000
+wm 32 0x020c4074 0x3ff00000
+wm 32 0x020c4078 0x00fff300
diff --git a/arch/arm/boards/embest-marsboard/lowlevel.c b/arch/arm/boards/embest-marsboard/lowlevel.c
new file mode 100644
index 0000000..9e20a2e
--- /dev/null
+++ b/arch/arm/boards/embest-marsboard/lowlevel.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Ahmad Fatoum - Pengutronix
+ */
+
+#include <common.h>
+#include <io.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx6.h>
+#include <mach/esdctl.h>
+#include <mach/iomux-mx6.h>
+#include <debug_ll.h>
+
+static inline void setup_uart(void)
+{
+	void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+
+	imx6_ungate_all_peripherals();
+
+	imx_setup_pad(iomuxbase, MX6Q_PAD_EIM_D26__UART2_TXD);
+
+	imx6_uart_setup_ll();
+
+	putc_ll('>');
+}
+
+extern char __dtb_z_imx6q_marsboard_start[];
+
+ENTRY_FUNCTION(start_imx6q_marsboard, r0, r1, r2)
+{
+	void *fdt;
+
+	imx6_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	fdt = __dtb_z_imx6q_marsboard_start + get_runtime_offset();
+
+	imx6q_barebox_entry(fdt);
+}
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 25bf40c..76d6f5b 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -56,22 +56,18 @@
 	.hw_ecc	= 1,
 };
 
-static struct imx_fb_videomode imxfb_mode = {
-	.mode = {
-		.name		= "CMO-QVGA",
-		.refresh	= 60,
-		.xres		= 320,
-		.yres		= 240,
-		.pixclock	= KHZ2PICOS(6500),
-		.hsync_len	= 30,
-		.left_margin	= 38,
-		.right_margin	= 20,
-		.vsync_len	= 3,
-		.upper_margin	= 15,
-		.lower_margin	= 4,
-	},
-	.pcr		= 0xCAD08B80,
-	.bpp		= 16,
+static struct fb_videomode imxfb_mode = {
+	.name		= "CMO-QVGA",
+	.refresh	= 60,
+	.xres		= 320,
+	.yres		= 240,
+	.pixclock	= KHZ2PICOS(6500),
+	.hsync_len	= 30,
+	.left_margin	= 38,
+	.right_margin	= 20,
+	.vsync_len	= 3,
+	.upper_margin	= 15,
+	.lower_margin	= 4,
 };
 
 static struct imx_fb_platform_data eukrea_cpuimx25_fb_data = {
@@ -80,6 +76,8 @@
 	.pwmr		= 0x00A903FF,
 	.lscr1		= 0x00120300,
 	.dmacr		= 0x80040060,
+	.pcr		= 0xCAD08B80,
+	.bpp		= 16,
 };
 
 struct gpio_led led0 = {
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 63034e2..52971ed 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -80,22 +80,19 @@
 };
 
 #ifdef CONFIG_DRIVER_VIDEO_IMX
-static struct imx_fb_videomode imxfb_mode = {
-	.mode = {
-		.name		= "CMO-QVGA",
-		.refresh	= 60,
-		.xres		= 320,
-		.yres		= 240,
-		.pixclock	= 156000,
-		.hsync_len	= 30,
-		.left_margin	= 38,
-		.right_margin	= 20,
-		.vsync_len	= 3,
-		.upper_margin	= 15,
-		.lower_margin	= 4,
-	},
-	.pcr		= 0xFAD08B80,
-	.bpp		= 16,};
+static struct fb_videomode imxfb_mode = {
+	.name		= "CMO-QVGA",
+	.refresh	= 60,
+	.xres		= 320,
+	.yres		= 240,
+	.pixclock	= 156000,
+	.hsync_len	= 30,
+	.left_margin	= 38,
+	.right_margin	= 20,
+	.vsync_len	= 3,
+	.upper_margin	= 15,
+	.lower_margin	= 4,
+};
 
 static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = {
 	.mode	= &imxfb_mode,
@@ -103,6 +100,8 @@
 	.pwmr	= 0x00A903FF,
 	.lscr1	= 0x00120300,
 	.dmacr	= 0x00020010,
+	.pcr	= 0xFAD08B80,
+	.bpp	= 16,
 };
 #endif
 
diff --git a/arch/arm/boards/freescale-mx21-ads/imx21ads.c b/arch/arm/boards/freescale-mx21-ads/imx21ads.c
index aa654da..2c54cd7 100644
--- a/arch/arm/boards/freescale-mx21-ads/imx21ads.c
+++ b/arch/arm/boards/freescale-mx21-ads/imx21ads.c
@@ -47,24 +47,20 @@
 };
 
 /* Sharp LQ035Q7DB02 QVGA display */
-static struct imx_fb_videomode imx_fb_modedata = {
-        .mode = {
-		.name           = "Sharp-LQ035Q7",
-		.refresh        = 60,
-		.xres           = 240,
-		.yres           = 320,
-		.pixclock       = 188679,
-		.left_margin    = 6,
-		.right_margin   = 16,
-		.upper_margin   = 8,
-		.lower_margin   = 10,
-		.hsync_len      = 2,
-		.vsync_len      = 1,
-		.sync           = 0,
-		.vmode          = FB_VMODE_NONINTERLACED,
-	},
-        .pcr            = 0xfb108bc7,
-        .bpp            = 16,
+static struct fb_videomode imx_fb_modedata = {
+	.name           = "Sharp-LQ035Q7",
+	.refresh        = 60,
+	.xres           = 240,
+	.yres           = 320,
+	.pixclock       = 188679,
+	.left_margin    = 6,
+	.right_margin   = 16,
+	.upper_margin   = 8,
+	.lower_margin   = 10,
+	.hsync_len      = 2,
+	.vsync_len      = 1,
+	.sync           = 0,
+	.vmode          = FB_VMODE_NONINTERLACED,
 };
 
 static struct imx_fb_platform_data imx_fb_data = {
@@ -76,6 +72,8 @@
 	.pwmr           = 0x00a903ff,
 	.lscr1          = 0x00120300,
 	.dmacr          = 0x00020008,
+	.pcr            = 0xfb108bc7,
+	.bpp            = 16,
 };
 
 static int imx21ads_timing_init(void)
diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c
index 2a64bc1..6846ba5 100644
--- a/arch/arm/boards/guf-neso/board.c
+++ b/arch/arm/boards/guf-neso/board.c
@@ -62,36 +62,18 @@
 	.flash_bbt	= 1,
 };
 
-static struct imx_fb_videomode imxfb_mode = {
-	.mode = {
-		.name		= "CPT CLAA070LC0JCT",
-		.refresh	= 60,
-		.xres		= 800,
-		.yres		= 480,
-		.pixclock	= KHZ2PICOS(27000),
-		.hsync_len	= 1,	/* DE only sync */
-		.left_margin	= 50,
-		.right_margin	= 50,
-		.vsync_len	= 1,	/* DE only sync */
-		.upper_margin	= 10,
-		.lower_margin	= 10,
-	},
-	/*
-	 * - TFT style panel
-	 * - clk enabled while idle
-	 * - clock inverted
-	 * - data not inverted
-	 * - data enable high active
-	 */
-	.pcr = PCR_TFT |
-		PCR_COLOR |
-		PCR_PBSIZ_8 |
-		PCR_BPIX_16 |
-		PCR_CLKPOL |
-		PCR_SCLK_SEL |
-		PCR_LPPOL |
-		PCR_FLMPOL,
-	.bpp = 16,	/* TODO 32 bit does not work: The 'green' component is lacking in this mode */
+static struct fb_videomode imxfb_mode = {
+	.name		= "CPT CLAA070LC0JCT",
+	.refresh	= 60,
+	.xres		= 800,
+	.yres		= 480,
+	.pixclock	= KHZ2PICOS(27000),
+	.hsync_len	= 1,	/* DE only sync */
+	.left_margin	= 50,
+	.right_margin	= 50,
+	.vsync_len	= 1,	/* DE only sync */
+	.upper_margin	= 10,
+	.lower_margin	= 10,
 };
 
 static void neso_fb_enable(int enable)
@@ -109,6 +91,22 @@
 	.dmacr	= (0 << 31) | (4 << 16) | 96,
 	.enable	= neso_fb_enable,
 	.framebuffer_ovl = (void *)0xa7f00000,
+	/*
+	 * - TFT style panel
+	 * - clk enabled while idle
+	 * - clock inverted
+	 * - data not inverted
+	 * - data enable high active
+	 */
+	.pcr = PCR_TFT |
+		PCR_COLOR |
+		PCR_PBSIZ_8 |
+		PCR_BPIX_16 |
+		PCR_CLKPOL |
+		PCR_SCLK_SEL |
+		PCR_LPPOL |
+		PCR_FLMPOL,
+	.bpp = 16,	/* TODO 32 bit does not work: The 'green' component is lacking in this mode */
 };
 
 #if defined(CONFIG_USB) && defined(CONFIG_USB_ULPI)
diff --git a/arch/arm/boards/karo-tx25/board.c b/arch/arm/boards/karo-tx25/board.c
index ebebd58..a4d4af5 100644
--- a/arch/arm/boards/karo-tx25/board.c
+++ b/arch/arm/boards/karo-tx25/board.c
@@ -125,24 +125,20 @@
 	MX25_PAD_OE_ACD__OE_ACD,
 };
 
-static struct imx_fb_videomode stk5_fb_mode = {
-	.bpp	= 16,
-	.mode = {
-		.name = "G-ETV570G0DMU",
-		.pixclock	= 33333,
+static struct fb_videomode stk5_fb_mode = {
+	.name = "G-ETV570G0DMU",
+	.pixclock	= 33333,
 
-		.xres		= 640,
-		.yres		= 480,
+	.xres		= 640,
+	.yres		= 480,
 
-		.hsync_len	= 64,
-		.left_margin	= 96,
-		.right_margin	= 80,
+	.hsync_len	= 64,
+	.left_margin	= 96,
+	.right_margin	= 80,
 
-		.vsync_len	= 3,
-		.upper_margin	= 46,
-		.lower_margin	= 39,
-	},
-	.pcr	= PCR_TFT | PCR_COLOR | PCR_FLMPOL | PCR_LPPOL | PCR_SCLK_SEL,
+	.vsync_len	= 3,
+	.upper_margin	= 46,
+	.lower_margin	= 39,
 };
 
 #define STK5_LCD_BACKLIGHT_GPIO		IMX_GPIO_NR(1, 26)
@@ -168,6 +164,8 @@
 	.num_modes	= 1,
 	.dmacr		= 0x80040060,
 	.enable		= tx25_fb_enable,
+	.bpp		= 16,
+	.pcr		= PCR_TFT | PCR_COLOR | PCR_FLMPOL | PCR_LPPOL | PCR_SCLK_SEL,
 };
 
 static int tx25_init_fb(void)
diff --git a/arch/arm/boards/phytec-phycore-imx27/pcm038.c b/arch/arm/boards/phytec-phycore-imx27/pcm038.c
index 5ebef51..008346f 100644
--- a/arch/arm/boards/phytec-phycore-imx27/pcm038.c
+++ b/arch/arm/boards/phytec-phycore-imx27/pcm038.c
@@ -34,20 +34,26 @@
 
 #define PCM038_GPIO_OTG_STP	(GPIO_PORTE + 1)
 
-static struct imx_fb_videomode imxfb_mode = {
-	.mode = {
-		.name		= "Sharp-LQ035Q7",
-		.refresh	= 60,
-		.xres		= 240,
-		.yres		= 320,
-		.pixclock	= 188679, /* in ps (5.3MHz) */
-		.hsync_len	= 7,
-		.left_margin	= 5,
-		.right_margin	= 16,
-		.vsync_len	= 1,
-		.upper_margin	= 7,
-		.lower_margin	= 9,
-	},
+static struct fb_videomode imxfb_mode = {
+	.name		= "Sharp-LQ035Q7",
+	.refresh	= 60,
+	.xres		= 240,
+	.yres		= 320,
+	.pixclock	= 188679, /* in ps (5.3MHz) */
+	.hsync_len	= 7,
+	.left_margin	= 5,
+	.right_margin	= 16,
+	.vsync_len	= 1,
+	.upper_margin	= 7,
+	.lower_margin	= 9,
+};
+
+static struct imx_fb_platform_data pcm038_fb_data = {
+	.mode	= &imxfb_mode,
+	.num_modes = 1,
+	.pwmr	= 0x00a903ff,
+	.lscr1	= 0x00120300,
+	.dmacr	= 0x00020010,
 	/*
 	 * - HSYNC active high
 	 * - VSYNC active high
@@ -57,16 +63,8 @@
 	 * - data enable low active
 	 * - enable sharp mode
 	 */
-	.pcr		= 0xf00080c0,
-	.bpp		= 16,
-};
-
-static struct imx_fb_platform_data pcm038_fb_data = {
-	.mode	= &imxfb_mode,
-	.num_modes = 1,
-	.pwmr	= 0x00a903ff,
-	.lscr1	= 0x00120300,
-	.dmacr	= 0x00020010,
+	.pcr	= 0xf00080c0,
+	.bpp	= 16,
 };
 
 static const unsigned int pcm038_pins[] = {
diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c
index 7301157..27a1ad4 100644
--- a/arch/arm/boards/phytec-som-imx6/board.c
+++ b/arch/arm/boards/phytec-som-imx6/board.c
@@ -115,12 +115,16 @@
 static int phycore_da9062_setup_buck_mode(void)
 {
 	struct i2c_adapter *adapter = NULL;
+	struct device_node *pmic_np = NULL;
 	struct i2c_client client;
 	unsigned char value;
-	int bus = 0;
 	int ret;
 
-	adapter = i2c_get_adapter(bus);
+	pmic_np = of_find_node_by_name(NULL, "pmic@58");
+	if (!pmic_np)
+		return -ENODEV;
+
+	adapter = of_find_i2c_adapter_by_node(pmic_np->parent);
 	if (!adapter)
 		return -ENODEV;
 
diff --git a/arch/arm/boards/zii-common/board.c b/arch/arm/boards/zii-common/board.c
index 20ec64d..9a9564e 100644
--- a/arch/arm/boards/zii-common/board.c
+++ b/arch/arm/boards/zii-common/board.c
@@ -16,6 +16,64 @@
 #include <globalvar.h>
 #include <init.h>
 #include <fs.h>
+#include <net.h>
+#include <linux/nvmem-consumer.h>
+
+static int rdu_eth_register_ethaddr(struct device_node *np)
+{
+	u8 mac[ETH_ALEN];
+	u8 *data;
+	int i;
+
+	data = nvmem_cell_get_and_read(np, "mac-address", ETH_ALEN);
+	if (IS_ERR(data))
+		return PTR_ERR(data);
+	/*
+	 * EEPROM stores MAC address in reverse (to what we expect it
+	 * to be) byte order.
+	 */
+	for (i = 0; i < ETH_ALEN; i++)
+		mac[i] = data[ETH_ALEN - i - 1];
+
+	free(data);
+
+	of_eth_register_ethaddr(np, mac);
+
+	return 0;
+}
+
+static int rdu_ethernet_init(void)
+{
+	static const char * const aliases[] = { "ethernet0", "ethernet1" };
+	struct device_node *np, *root;
+	int i, ret;
+
+	if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
+	    !of_machine_is_compatible("zii,imx6qp-zii-rdu2") &&
+	    !of_machine_is_compatible("zii,imx8mq-ultra"))
+		return 0;
+
+	root = of_get_root_node();
+
+	for (i = 0; i < ARRAY_SIZE(aliases); i++) {
+		const char *alias = aliases[i];
+
+		np = of_find_node_by_alias(root, alias);
+		if (!np) {
+			pr_warn("Failed to find %s\n", alias);
+			continue;
+		}
+
+		ret = rdu_eth_register_ethaddr(np);
+		if (ret) {
+			pr_warn("Failed to register MAC for %s\n", alias);
+			continue;
+		}
+	}
+
+	return 0;
+}
+late_initcall(rdu_ethernet_init);
 
 static int rdu_networkconfig(void)
 {
diff --git a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c
index da05b05..c7bb044 100644
--- a/arch/arm/boards/zii-imx51-rdu1/lowlevel.c
+++ b/arch/arm/boards/zii-imx51-rdu1/lowlevel.c
@@ -68,9 +68,9 @@
 	return FIELD_GET(SYSTEM_TYPE, dr);
 }
 
-extern char __dtb_imx51_zii_rdu1_start[];
-extern char __dtb_imx51_zii_scu2_mezz_start[];
-extern char __dtb_imx51_zii_scu3_esb_start[];
+extern char __dtb_z_imx51_zii_rdu1_start[];
+extern char __dtb_z_imx51_zii_scu2_mezz_start[];
+extern char __dtb_z_imx51_zii_scu3_esb_start[];
 
 ENTRY_FUNCTION(start_imx51_zii_rdu1, r0, r1, r2)
 {
@@ -96,13 +96,13 @@
 		/* FALLTHROUGH */
 	case ZII_PLATFORM_IMX51_RDU_REV_B:
 	case ZII_PLATFORM_IMX51_RDU_REV_C:
-		fdt = __dtb_imx51_zii_rdu1_start;
+		fdt = __dtb_z_imx51_zii_rdu1_start;
 		break;
 	case ZII_PLATFORM_IMX51_SCU2_MEZZ:
-		fdt = __dtb_imx51_zii_scu2_mezz_start;
+		fdt = __dtb_z_imx51_zii_scu2_mezz_start;
 		break;
 	case ZII_PLATFORM_IMX51_SCU3_ESB:
-		fdt = __dtb_imx51_zii_scu3_esb_start;
+		fdt = __dtb_z_imx51_zii_scu3_esb_start;
 		break;
 	}
 
diff --git a/arch/arm/boards/zii-imx6q-rdu2/board.c b/arch/arm/boards/zii-imx6q-rdu2/board.c
index 6adb0b1..63367a4 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/board.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/board.c
@@ -159,61 +159,6 @@
 }
 device_initcall(rdu2_devices_init);
 
-static int rdu2_eth_register_ethaddr(struct device_node *np)
-{
-	u8 mac[ETH_ALEN];
-	u8 *data;
-	int i;
-
-	data = nvmem_cell_get_and_read(np, "mac-address", ETH_ALEN);
-	if (IS_ERR(data))
-		return PTR_ERR(data);
-	/*
-	 * EEPROM stores MAC address in reverse (to what we expect it
-	 * to be) byte order.
-	 */
-	for (i = 0; i < ETH_ALEN; i++)
-		mac[i] = data[ETH_ALEN - i - 1];
-
-	free(data);
-
-	of_eth_register_ethaddr(np, mac);
-
-	return 0;
-}
-
-static int rdu2_ethernet_init(void)
-{
-	const char *aliases[] = { "ethernet0", "ethernet1" };
-	struct device_node *np, *root;
-	int i, ret;
-
-	if (!of_machine_is_compatible("zii,imx6q-zii-rdu2") &&
-	    !of_machine_is_compatible("zii,imx6qp-zii-rdu2"))
-		return 0;
-
-	root = of_get_root_node();
-
-	for (i = 0; i < ARRAY_SIZE(aliases); i++) {
-		const char *alias = aliases[i];
-
-		np = of_find_node_by_alias(root, alias);
-		if (!np) {
-			pr_warn("Failed to find %s\n", alias);
-			continue;
-		}
-
-		ret = rdu2_eth_register_ethaddr(np);
-		if (ret) {
-			pr_warn("Failed to register MAC for %s\n", alias);
-			continue;
-		}
-	}
-
-	return 0;
-}
-late_initcall(rdu2_ethernet_init);
-
 static int rdu2_fixup_egalax_ts(struct device_node *root, void *context)
 {
 	struct device_node *np;
diff --git a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
index 3f5d90b..87e6345 100644
--- a/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
+++ b/arch/arm/boards/zii-imx6q-rdu2/lowlevel.c
@@ -263,8 +263,8 @@
 	putc_ll('>');
 }
 
-extern char __dtb_imx6q_zii_rdu2_start[];
-extern char __dtb_imx6qp_zii_rdu2_start[];
+extern char __dtb_z_imx6q_zii_rdu2_start[];
+extern char __dtb_z_imx6qp_zii_rdu2_start[];
 
 static noinline void rdu2_sram_setup(void)
 {
@@ -304,9 +304,9 @@
 		rdu2_sram_setup();
 
 	if (__imx6_cpu_type() == IMX6_CPUTYPE_IMX6QP)
-		imx6q_barebox_entry(__dtb_imx6qp_zii_rdu2_start +
+		imx6q_barebox_entry(__dtb_z_imx6qp_zii_rdu2_start +
 				    get_runtime_offset());
 	else
-		imx6q_barebox_entry(__dtb_imx6q_zii_rdu2_start +
+		imx6q_barebox_entry(__dtb_z_imx6q_zii_rdu2_start +
 				    get_runtime_offset());
 }
diff --git a/arch/arm/boards/zii-imx7d-dev/lowlevel.c b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
index 3ad4940..3bacfd0 100644
--- a/arch/arm/boards/zii-imx7d-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx7d-dev/lowlevel.c
@@ -18,8 +18,8 @@
 #include <asm/cache.h>
 #include <mach/esdctl.h>
 
-extern char __dtb_imx7d_zii_rpu2_start[];
-extern char __dtb_imx7d_zii_rmu2_start[];
+extern char __dtb_z_imx7d_zii_rpu2_start[];
+extern char __dtb_z_imx7d_zii_rmu2_start[];
 
 static inline void setup_uart(void)
 {
@@ -97,10 +97,10 @@
 		}
 		/* FALLTHROUGH */
 	case ZII_PLATFORM_IMX7D_RPU2:
-		fdt = __dtb_imx7d_zii_rpu2_start;
+		fdt = __dtb_z_imx7d_zii_rpu2_start;
 		break;
 	case ZII_PLATFORM_IMX7D_RMU2:
-		fdt = __dtb_imx7d_zii_rmu2_start;
+		fdt = __dtb_z_imx7d_zii_rmu2_start;
 		break;
 	}
 
diff --git a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
index 7eb8b68..795c98c 100644
--- a/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
+++ b/arch/arm/boards/zii-imx8mq-dev/lowlevel.c
@@ -117,8 +117,8 @@
 	return FIELD_GET(SYSTEM_TYPE, dr);
 }
 
-extern char __dtb_imx8mq_zii_ultra_rmb3_start[];
-extern char __dtb_imx8mq_zii_ultra_zest_start[];
+extern char __dtb_z_imx8mq_zii_ultra_rmb3_start[];
+extern char __dtb_z_imx8mq_zii_ultra_zest_start[];
 
 static __noreturn noinline void zii_imx8mq_dev_start(void)
 {
@@ -155,8 +155,6 @@
 	switch (system_type) {
 	default:
 		if (IS_ENABLED(CONFIG_DEBUG_LL)) {
-			relocate_to_current_adr();
-			setup_c();
 			puts_ll("\n*********************************\n");
 			puts_ll("* Unknown system type: ");
 			puthex_ll(system_type);
@@ -165,10 +163,10 @@
 		}
 		/* FALLTHROUGH */
 	case ZII_PLATFORM_IMX8MQ_ULTRA_RMB3:
-		fdt = __dtb_imx8mq_zii_ultra_rmb3_start;
+		fdt = __dtb_z_imx8mq_zii_ultra_rmb3_start;
 		break;
 	case ZII_PLATFORM_IMX8MQ_ULTRA_ZEST:
-		fdt = __dtb_imx8mq_zii_ultra_zest_start;
+		fdt = __dtb_z_imx8mq_zii_ultra_zest_start;
 		break;
 	}
 
diff --git a/arch/arm/boards/zii-vf610-dev/lowlevel.c b/arch/arm/boards/zii-vf610-dev/lowlevel.c
index b320fbc..9b57581 100644
--- a/arch/arm/boards/zii-vf610-dev/lowlevel.c
+++ b/arch/arm/boards/zii-vf610-dev/lowlevel.c
@@ -75,13 +75,13 @@
 	return pdir;
 }
 
-extern char __dtb_vf610_zii_dev_rev_b_start[];
-extern char __dtb_vf610_zii_dev_rev_c_start[];
-extern char __dtb_vf610_zii_cfu1_start[];
-extern char __dtb_vf610_zii_ssmb_spu3_start[];
-extern char __dtb_vf610_zii_scu4_aib_start[];
-extern char __dtb_vf610_zii_ssmb_dtu_start[];
-extern char __dtb_vf610_zii_spb4_start[];
+extern char __dtb_z_vf610_zii_dev_rev_b_start[];
+extern char __dtb_z_vf610_zii_dev_rev_c_start[];
+extern char __dtb_z_vf610_zii_cfu1_start[];
+extern char __dtb_z_vf610_zii_ssmb_spu3_start[];
+extern char __dtb_z_vf610_zii_scu4_aib_start[];
+extern char __dtb_z_vf610_zii_ssmb_dtu_start[];
+extern char __dtb_z_vf610_zii_spb4_start[];
 
 ENTRY_FUNCTION(start_zii_vf610_dev, r0, r1, r2)
 {
@@ -105,25 +105,25 @@
 			puts_ll("*********************************\n");
 		}
 	case ZII_PLATFORM_VF610_DEV_REV_B: /* FALLTHROUGH */
-		fdt = __dtb_vf610_zii_dev_rev_b_start;
+		fdt = __dtb_z_vf610_zii_dev_rev_b_start;
 		break;
 	case ZII_PLATFORM_VF610_SCU4_AIB:
-		fdt = __dtb_vf610_zii_scu4_aib_start;
+		fdt = __dtb_z_vf610_zii_scu4_aib_start;
 		break;
 	case ZII_PLATFORM_VF610_DEV_REV_C:
-		fdt = __dtb_vf610_zii_dev_rev_c_start;
+		fdt = __dtb_z_vf610_zii_dev_rev_c_start;
 		break;
 	case ZII_PLATFORM_VF610_CFU1:
-		fdt = __dtb_vf610_zii_cfu1_start;
+		fdt = __dtb_z_vf610_zii_cfu1_start;
 		break;
 	case ZII_PLATFORM_VF610_SSMB_SPU3:
-		fdt = __dtb_vf610_zii_ssmb_spu3_start;
+		fdt = __dtb_z_vf610_zii_ssmb_spu3_start;
 		break;
 	case ZII_PLATFORM_VF610_SPB4:
-		fdt = __dtb_vf610_zii_spb4_start;
+		fdt = __dtb_z_vf610_zii_spb4_start;
 		break;
 	case ZII_PLATFORM_VF610_SSMB_DTU:
-		fdt = __dtb_vf610_zii_ssmb_dtu_start;
+		fdt = __dtb_z_vf610_zii_ssmb_dtu_start;
 		break;
 	}
 
diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
index 18c2775..8b8178a 100644
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@@ -27,6 +27,7 @@
 CONFIG_MACH_SOLIDRUN_MICROSOM=y
 CONFIG_MACH_TECHNEXION_PICO_HOBBIT=y
 CONFIG_MACH_TECHNEXION_WANDBOARD=y
+CONFIG_MACH_EMBEST_MARSBOARD=y
 CONFIG_MACH_EMBEST_RIOTBOARD=y
 CONFIG_MACH_UDOO=y
 CONFIG_MACH_VARISCITE_MX6=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bffcfad..294a0bf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,6 +12,7 @@
 lwl-dtb-$(CONFIG_MACH_KINDLE_MX50) += imx50-kindle-d01100.dtb.o imx50-kindle-d01200.dtb.o imx50-kindle-ey21.dtb.o
 lwl-dtb-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
 lwl-dtb-$(CONFIG_MACH_ELTEC_HIPERCAM) += imx6dl-eltec-hipercam.dtb.o
+lwl-dtb-$(CONFIG_MACH_EMBEST_MARSBOARD) += imx6q-marsboard.dtb.o
 lwl-dtb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o
 lwl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o
 lwl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
diff --git a/arch/arm/dts/canon-a1100.dts b/arch/arm/dts/canon-a1100.dts
index a88eacf..18ba495 100644
--- a/arch/arm/dts/canon-a1100.dts
+++ b/arch/arm/dts/canon-a1100.dts
@@ -7,6 +7,7 @@
 	compatible = "canon,a1100";
 
 	memory {
+		device_type = "memory";
 		reg = <0x00000000 0x04000000>;
 	};
 
diff --git a/arch/arm/dts/digic4.dtsi b/arch/arm/dts/digic4.dtsi
index 21b004d..2db9393 100644
--- a/arch/arm/dts/digic4.dtsi
+++ b/arch/arm/dts/digic4.dtsi
@@ -1,8 +1,11 @@
-/include/ "skeleton.dtsi"
-
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
 	compatible = "canon,digic4";
 
+	chosen { };
+
 	timer0: timer@c0210000 {
 		compatible = "canon,digic-timer";
 		reg = <0xc0210000 0x1c>;
diff --git a/arch/arm/dts/dm365.dtsi b/arch/arm/dts/dm365.dtsi
index ea69007..b03cc3e 100644
--- a/arch/arm/dts/dm365.dtsi
+++ b/arch/arm/dts/dm365.dtsi
@@ -1,6 +1,9 @@
-#include "skeleton.dtsi"
-
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+
 	soc {
 		compatible = "simple-bus";
 		model = "TI TMS320DM365";
diff --git a/arch/arm/dts/imx25-karo-tx25.dts b/arch/arm/dts/imx25-karo-tx25.dts
index 9296e90..2785a3c 100644
--- a/arch/arm/dts/imx25-karo-tx25.dts
+++ b/arch/arm/dts/imx25-karo-tx25.dts
@@ -9,102 +9,16 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/dts-v1/;
+#include <arm/imx25-karo-tx25.dts>
 #include "imx25.dtsi"
 
 / {
-	model = "Ka-Ro TX25";
-	compatible = "karo,imx25-tx25", "fsl,imx25";
-
 	chosen {
-		stdout-path = &uart1;
-
 		environment {
 			compatible = "barebox,environment";
 			device-path = &nfc, "partname:environment";
 		};
 	};
-
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		reg_fec_phy: regulator@0 {
-			compatible = "regulator-fixed";
-			reg = <0>;
-			regulator-name = "fec-phy";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-			gpio = <&gpio4 9 0>;
-		};
-	};
-
-	memory {
-		reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
-	};
-};
-
-&iomuxc {
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
-			MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
-			MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
-			MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
-		>;
-	};
-
-	pinctrl_fec: fecgrp {
-		fsl,pins = <
-			MX25_PAD_D11__GPIO_4_9		0x80000000 /* FEC PHY power on pin */
-			MX25_PAD_D13__GPIO_4_7		0x80000000 /* FEC reset */
-			MX25_PAD_FEC_MDC__FEC_MDC	0x80000000
-			MX25_PAD_FEC_MDIO__FEC_MDIO	0x80000000
-			MX25_PAD_FEC_TDATA0__FEC_TDATA0	0x80000000
-			MX25_PAD_FEC_TDATA1__FEC_TDATA1	0x80000000
-			MX25_PAD_FEC_TX_EN__FEC_TX_EN	0x80000000
-			MX25_PAD_FEC_RDATA0__FEC_RDATA0	0x80000000
-			MX25_PAD_FEC_RDATA1__FEC_RDATA1	0x80000000
-			MX25_PAD_FEC_RX_DV__FEC_RX_DV	0x80000000
-			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK	0x80000000
-		>;
-	};
-
-	pinctrl_nfc: nfcgrp {
-		fsl,pins = <
-			MX25_PAD_NF_CE0__NF_CE0		0x80000000
-			MX25_PAD_NFWE_B__NFWE_B		0x80000000
-			MX25_PAD_NFRE_B__NFRE_B		0x80000000
-			MX25_PAD_NFALE__NFALE		0x80000000
-			MX25_PAD_NFCLE__NFCLE		0x80000000
-			MX25_PAD_NFWP_B__NFWP_B		0x80000000
-			MX25_PAD_NFRB__NFRB		0x80000000
-			MX25_PAD_D7__D7			0x80000000
-			MX25_PAD_D6__D6			0x80000000
-			MX25_PAD_D5__D5			0x80000000
-			MX25_PAD_D4__D4			0x80000000
-			MX25_PAD_D3__D3			0x80000000
-			MX25_PAD_D2__D2			0x80000000
-			MX25_PAD_D1__D1			0x80000000
-			MX25_PAD_D0__D0			0x80000000
-		>;
-	};
-};
-
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	status = "okay";
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec>;
-	phy-reset-gpios = <&gpio4 7 0>;
-	phy-mode = "rmii";
-	phy-supply = <&reg_fec_phy>;
-	status = "okay";
 };
 
 &iim {
@@ -112,14 +26,8 @@
 };
 
 &nfc {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_nfc>;
 	#address-cells = <1>;
 	#size-cells = <1>;
-	nand-on-flash-bbt;
-	nand-ecc-mode = "hw";
-	nand-bus-width = <8>;
-	status = "okay";
 
 	partition@0 {
 		label = "boot";
diff --git a/arch/arm/dts/imx25.dtsi b/arch/arm/dts/imx25.dtsi
index eb30461..e72dbd5 100644
--- a/arch/arm/dts/imx25.dtsi
+++ b/arch/arm/dts/imx25.dtsi
@@ -9,10 +9,12 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include "skeleton.dtsi"
-#include <arm/imx25.dtsi>
-
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+
 	aliases {
 		mmc0 = &esdhc1;
 		mmc2 = &esdhc2;
diff --git a/arch/arm/dts/imx6q-marsboard.dts b/arch/arm/dts/imx6q-marsboard.dts
new file mode 100644
index 0000000..1d9f8f0
--- /dev/null
+++ b/arch/arm/dts/imx6q-marsboard.dts
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright (C) 2019 Ahmad Fatoum - Pengutronix
+ */
+
+#include <arm/imx6q-marsboard.dts>
+#include "imx6q.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+
+		environment {
+			compatible = "barebox,environment";
+			device-path = &environment_spinor;
+		};
+	};
+};
+
+&ecspi1 {
+	m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x000000 0x100000>;
+		};
+
+		environment_spinor: partition@100000 {
+			label = "barebox-environment";
+			reg = <0x100000 0x80000>;
+		};
+	};
+};
+
+&fec {
+	phy-reset-duration = <2>;
+};
+
+&ocotp {
+	barebox,provide-mac-address = <&fec 0x620>;
+};
diff --git a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
index f0bba2e..846ebbe 100644
--- a/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
@@ -86,6 +86,10 @@
 	};
 };
 
+&fec {
+	/delete-property/ phy-supply;
+};
+
 &gpmi {
 	partitions {
 		compatible = "fixed-partitions";
diff --git a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
index dd4379b..414497b 100644
--- a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
+++ b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
@@ -3,41 +3,5 @@
  * Copyright (C) 2019 Zodiac Inflight Innovations
  */
 
-/dts-v1/;
-
+#include <arm64/freescale/imx8mq-zii-ultra-rmb3.dts>
 #include "imx8mq-zii-ultra.dtsi"
-
-/ {
-	model = "ZII i.MX8MQ Ultra RMB3 Board";
-	compatible = "zii,imx8mq-ultra-rmb3", "zii,imx8mq-ultra", "fsl,imx8mq";
-};
-
-&ecspi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	nor_flash: flash@0 {
-		compatible = "st,m25p128", "jedec,spi-nor";
-		spi-max-frequency = <20000000>;
-		reg = <0>;
-	};
-};
-
-&iomuxc {
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9	0x19
-			MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
-			MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
-			MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
-		>;
-	};
-};
-
-&usb_hub {
-	swap-dx-lanes = <0>;
-};
diff --git a/arch/arm/dts/imx8mq-zii-ultra-zest.dts b/arch/arm/dts/imx8mq-zii-ultra-zest.dts
index c2ac05d..491e669 100644
--- a/arch/arm/dts/imx8mq-zii-ultra-zest.dts
+++ b/arch/arm/dts/imx8mq-zii-ultra-zest.dts
@@ -3,11 +3,5 @@
  * Copyright (C) 2019 Zodiac Inflight Innovations
  */
 
-/dts-v1/;
-
+#include <arm64/freescale/imx8mq-zii-ultra-zest.dts>
 #include "imx8mq-zii-ultra.dtsi"
-
-/ {
-	model = "ZII i.MX8MQ Ultra Zest Board";
-	compatible = "zii,imx8mq-ultra-zest", "zii,imx8mq-ultra", "fsl,imx8mq";
-};
diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
index 6e41e82..6180f21 100644
--- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
+++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
@@ -3,7 +3,6 @@
  * Copyright (C) 2019 Zodiac Inflight Innovations
  */
 
-#include <arm64/freescale/imx8mq.dtsi>
 #include "imx8mq.dtsi"
 #include "imx8mq-ddrc.dtsi"
 
@@ -24,6 +23,8 @@
 	};
 
 	aliases {
+		ethernet0 = &fec1;
+		ethernet1 = &i210;
 		/*
 		 * NVMEM device corresponding to EEPROM attached to
 		 * the switch shared DT node with it, so we use that
@@ -31,265 +32,18 @@
 		 */
 		switch-eeprom = &switch;
 	};
-
-	mdio0: bitbang-mdio {
-		compatible = "virtual,mdio-gpio";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>;
-		gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>, /* MDC */
-			<&gpio1 14 GPIO_ACTIVE_HIGH>; /* MDIO */
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		phy0: ethernet-phy@0 {
-			reg = <0>;
-			reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
-		};
-	};
-
-	reg_usdhc2_vmmc: regulator-vsd-3v3 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usdhc2>;
-		compatible = "regulator-fixed";
-		regulator-name = "VSD_3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	pcie0_refclk: pcie0-refclk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
-
-	pcie1_refclk: pcie0-refclk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <100000000>;
-	};
 };
 
 &fec1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec1>;
-
-	phy-handle = <&phy0>;
-	phy-mode = "rmii";
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "okay";
-
-		switch: switch@0 {
-			compatible = "marvell,mv88e6085";
-			reg = <0>;
-			dsa,member = <0 0>;
-			eeprom-length = <512>;
-
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
-					label = "gigabit_proc";
-				};
-
-				port@1 {
-					reg = <1>;
-					label = "netaux";
-				};
-
-				port@2 {
-					reg = <2>;
-					label = "cpu";
-
-					fixed-link {
-						speed = <100>;
-						full-duplex;
-					};
-				};
-
-				port@3 {
-					reg = <3>;
-					label = "netright";
-				};
-
-				port@4 {
-					reg = <4>;
-					label = "netleft";
-				};
-			};
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-};
-
-&i2c2 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	status = "okay";
-
-	pmic@8 {
-		compatible = "fsl,pfuze100";
-		reg = <0x8>;
-
-		regulators {
-			sw1a_reg: sw1ab {
-				regulator-min-microvolt = <825000>;
-				regulator-max-microvolt = <1100000>;
-			};
-
-			sw1c_reg: sw1c {
-				regulator-min-microvolt = <825000>;
-				regulator-max-microvolt = <1100000>;
-			};
-
-			sw2_reg: sw2 {
-				regulator-min-microvolt = <1100000>;
-				regulator-max-microvolt = <1100000>;
-				regulator-always-on;
-			};
-
-			sw3a_reg: sw3ab {
-				regulator-min-microvolt = <825000>;
-				regulator-max-microvolt = <1100000>;
-				regulator-always-on;
-			};
-
-			sw4_reg: sw4 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-always-on;
-			};
-
-			swbst_reg: swbst {
-				regulator-min-microvolt = <5000000>;
-				regulator-max-microvolt = <5150000>;
-			};
-
-			snvs_reg: vsnvs {
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <3000000>;
-				regulator-always-on;
-			};
-
-			vref_reg: vrefddr {
-				regulator-always-on;
-			};
-
-			vgen1_reg: vgen1 {
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1550000>;
-			};
-
-			vgen2_reg: vgen2 {
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <975000>;
-				regulator-always-on;
-			};
-
-			vgen3_reg: vgen3 {
-				regulator-min-microvolt = <1675000>;
-				regulator-max-microvolt = <1975000>;
-				regulator-always-on;
-			};
-
-			vgen4_reg: vgen4 {
-				regulator-min-microvolt = <1625000>;
-				regulator-max-microvolt = <1875000>;
-				regulator-always-on;
-			};
-
-			vgen5_reg: vgen5 {
-				regulator-min-microvolt = <3075000>;
-				regulator-max-microvolt = <3625000>;
-				regulator-always-on;
-			};
-
-			vgen6_reg: vgen6 {
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-			};
-		};
-	};
-
-	temp-sense@48 {
-		compatible = "national,lm75";
-		reg = <0x48>;
-	};
-
-	eeprom@54 {
-		compatible = "atmel,24c128";
-		reg = <0x54>;
-	};
-
-	ds1341: rtc@68 {
-		compatible = "dallas,ds1341";
-		reg = <0x68>;
-	};
-};
-
-&i2c3 {
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	status = "okay";
-
-	usb_hub: usb2513b@2c {
-		compatible = "microchip,usb2513b";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb2513b>;
-		reg = <0x2c>;
-		reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
-	};
-};
-
-&i2c4 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c4>;
-	status = "okay";
+	nvmem-cells = <&mac_address_0>;
+	nvmem-cell-names = "mac-address";
 };
 
 &ocotp {
 	barebox,provide-mac-address = <&fec1 0x640>;
 };
 
-&pcie0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcie0>;
-	reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
-		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
-		 <&pcie0_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
-	status = "okay";
-};
-
 &pcie1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcie1>;
-	reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
-	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
-		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
-		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
-		 <&pcie1_refclk>;
-	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
-	status = "okay";
-
 	host@0 {
 		reg = <0 0 0 0 0>;
 
@@ -302,73 +56,26 @@
 	};
 };
 
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	status = "okay";
+&i210 {
+	nvmem-cells = <&mac_address_1>;
+	nvmem-cell-names = "mac-address";
 };
 
 &uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	status = "okay";
-
 	rave-sp {
-		compatible = "zii,rave-sp-rdu2";
-		current-speed = <1000000>;
-		#address-cells = <1>;
-		#size-cells = <1>;
+		eeprom@a4 {
+			mac_address_0: mac-address@180 {
+				reg = <0x180 6>;
+			};
 
-		watchdog {
-			compatible = "zii,rave-sp-watchdog";
-		};
-
-		main_eeprom: eeprom@a4 {
-			compatible = "zii,rave-sp-eeprom";
-			reg = <0xa4 0x4000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			zii,eeprom-name = "main-eeprom";
-		};
-
-		eeprom@a3 {
-			compatible = "zii,rave-sp-eeprom";
-			reg = <0xa3 0x4000>;
-			zii,eeprom-name = "dds-eeprom";
+			mac_address_1: mac-address@190 {
+				reg = <0x190 6>;
+			};
 		};
 	};
 };
 
-&usb_dwc3_0 {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&usb3_phy0 {
-	status = "okay";
-};
-
-&usb_dwc3_1 {
-	status = "okay";
-	dr_mode = "host";
-};
-
-&usb3_phy1 {
-	status = "okay";
-};
-
 &usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	vqmmc-supply = <&sw4_reg>;
-	bus-width = <8>;
-	non-removable;
-	no-sd;
-	no-sdio;
-	status = "okay";
-
 	#address-cells = <1>;
 	#size-cells = <1>;
 
@@ -384,14 +91,6 @@
 };
 
 &usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	status = "okay";
-
 	#address-cells = <1>;
 	#size-cells = <1>;
 
@@ -406,187 +105,3 @@
 	};
 };
 
-&iomuxc {
-	pinctrl_mdio_bitbang: bitbangmdiogrp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x44
-			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14	0x64
-		>;
-	};
-
-	pinctrl_fec1: fec1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23
-			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
-			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
-			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK		0x1f
-			MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER		0x91
-			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-		>;
-	};
-
-	pinctrl_fec1_phy_reset: fec1phyresetgrp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29		0x11
-		>;
-	};
-
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
-			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
-		>;
-	};
-
-	pinctrl_i2c2: i2c2grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
-			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
-		>;
-	};
-
-	pinctrl_i2c3: i2c3grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
-			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
-		>;
-	};
-
-	pinctrl_i2c4: i2c4grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000007f
-			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000007f
-		>;
-	};
-
-	pinctrl_pcie0: pcie0grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B	0x76
-			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x16
-		>;
-	};
-
-	pinctrl_pcie1: pcie1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B	0x76
-			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x16
-		>;
-	};
-
-	pinctrl_reg_usdhc2: regusdhc2grpgpio {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
-		>;
-	};
-
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
-			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
-		>;
-	};
-
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
-			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
-		>;
-	};
-
-	pinctrl_usb2513b: usb2513bgrp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25    0x41
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
-			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
-			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
-			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
-			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
-			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
-			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
-			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
-			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
-			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
-			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
-			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
-			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
-			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
-			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
-			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
-			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
-			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
-			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
-			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
-			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
-			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x85
-			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
-			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
-			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
-			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
-			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
-			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
-			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
-			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
-			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
-			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
-			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x87
-			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
-			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
-			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
-			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
-			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
-			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
-			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
-			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
-			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
-			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
-			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
-			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
-			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200grp {
-		fsl,pins = <
-			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
-			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
-			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
-			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
-			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
-			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
-			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
-		>;
-	};
-};
\ No newline at end of file
diff --git a/arch/arm/dts/k1879hb1ya.dtsi b/arch/arm/dts/k1879hb1ya.dtsi
index 83ba7fb..7bbc31e 100644
--- a/arch/arm/dts/k1879hb1ya.dtsi
+++ b/arch/arm/dts/k1879hb1ya.dtsi
@@ -1,6 +1,13 @@
-#include "skeleton.dtsi"
-
 / {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen { };
+
+	memory {
+		device_type = "memory";
+	};
+
 	soc {
 		compatible = "simple-bus";
 		model = "RC Module K1879HB1YA";
diff --git a/arch/arm/dts/skeleton.dtsi b/arch/arm/dts/skeleton.dtsi
deleted file mode 100644
index b41d241..0000000
--- a/arch/arm/dts/skeleton.dtsi
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Skeleton device tree; the bare minimum needed to boot; just include and
- * add a compatible value.  The bootloader will typically populate the memory
- * node.
- */
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	chosen { };
-	aliases { };
-	memory { device_type = "memory"; reg = <0 0>; };
-};
diff --git a/arch/arm/dts/vf610-zii-scu4-aib.dts b/arch/arm/dts/vf610-zii-scu4-aib.dts
index 43a13e2..1e6a549 100644
--- a/arch/arm/dts/vf610-zii-scu4-aib.dts
+++ b/arch/arm/dts/vf610-zii-scu4-aib.dts
@@ -109,3 +109,11 @@
 		label = "fiber9";
 	};
 };
+
+/*
+ * FIXME: Remove once this code appears in kernel DTS
+*/
+&i2c2 {
+	tca9548@70 { i2c-mux-idle-disconnect; };
+	tca9548@71 { i2c-mux-idle-disconnect; };
+};
diff --git a/arch/arm/dts/virt2real.dts b/arch/arm/dts/virt2real.dts
index 09aec1f..8f8c65b 100644
--- a/arch/arm/dts/virt2real.dts
+++ b/arch/arm/dts/virt2real.dts
@@ -6,6 +6,7 @@
 	model = "virt2real";
 
 	memory {
+		device_type = "memory";
 		reg = <0x82000000 0x01000000>;
 	};
 
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index e772162..6e98e95 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -397,6 +397,11 @@
 	select ARM_USE_COMPRESSED_DTB
 	select MCI_IMX_ESDHC_PBL
 
+config MACH_EMBEST_MARSBOARD
+	bool "Embest MarSboard"
+	select ARCH_IMX6
+	select ARM_USE_COMPRESSED_DTB
+
 config MACH_EMBEST_RIOTBOARD
 	bool "Embest RIoTboard"
 	select ARCH_IMX6
@@ -447,12 +452,14 @@
 	select MACH_FREESCALE_MX51_PDK_POWER
 	select CRC8
 	select MACH_ZII_COMMON
+	select ARM_USE_COMPRESSED_DTB
 
 config MACH_ZII_RDU2
 	bool "ZII i.MX6Q(+) RDU2"
 	select ARCH_IMX6
 	select MCI_IMX_ESDHC_PBL
 	select MACH_ZII_COMMON
+	select ARM_USE_COMPRESSED_DTB
 
 config MACH_ZII_IMX8MQ_DEV
 	bool "ZII i.MX8MQ based devices"
@@ -462,15 +469,18 @@
 	select ARM_SMCCC
 	select MCI_IMX_ESDHC_PBL
 	select MACH_ZII_COMMON
+	select ARM_USE_COMPRESSED_DTB
 
 config MACH_ZII_VF610_DEV
 	bool "ZII VF610 Dev Family"
 	select ARCH_VF610
 	select CLKDEV_LOOKUP
+	select ARM_USE_COMPRESSED_DTB
 
 config MACH_ZII_IMX7D_DEV
 	bool "ZII i.MX7D based devices"
 	select ARCH_IMX7
+	select ARM_USE_COMPRESSED_DTB
 
 config MACH_PHYTEC_PHYCORE_IMX7
 	bool "Phytec phyCORE i.MX7"
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 0fdd9f0..41e0066 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -192,13 +192,7 @@
 
 u64 imx6_uid(void)
 {
-	void __iomem *ocotpbase = IOMEM(MX6_OCOTP_BASE_ADDR);
-	u64 uid;
-
-	uid = ((u64)readl(ocotpbase + MX6_OCOTP_CFG0) << 32);
-	uid |= (u64)readl(ocotpbase + MX6_OCOTP_CFG1);
-
-	return uid;
+	return imx_ocotp_read_uid(IOMEM(MX6_OCOTP_BASE_ADDR));
 }
 
 int imx6_init(void)
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index 0893445..d06ba09 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -20,6 +20,7 @@
 #include <mach/revision.h>
 #include <mach/imx8mq.h>
 #include <mach/reset-reason.h>
+#include <mach/ocotp.h>
 
 #include <linux/iopoll.h>
 #include <linux/arm-smccc.h>
@@ -27,6 +28,11 @@
 #define FSL_SIP_BUILDINFO			0xC2000003
 #define FSL_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
+u64 imx8mq_uid(void)
+{
+	return imx_ocotp_read_uid(IOMEM(MX8MQ_OCOTP_BASE_ADDR));
+}
+
 int imx8mq_init(void)
 {
 	void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
@@ -52,6 +58,7 @@
 	 * Reset reasons seem to be identical to that of i.MX7
 	 */
 	imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
+	pr_info("%s unique ID: %llx\n", cputypestr, imx8mq_uid());
 
 	if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
 	    IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h
index 08dc06f..c085894 100644
--- a/arch/arm/mach-imx/include/mach/imx8mq.h
+++ b/arch/arm/mach-imx/include/mach/imx8mq.h
@@ -49,4 +49,6 @@
 	return revision;
 }
 
+u64 imx8mq_uid(void);
+
 #endif /* __MACH_IMX8_H */
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h
index ea39e31..6df7a14 100644
--- a/arch/arm/mach-imx/include/mach/imxfb.h
+++ b/arch/arm/mach-imx/include/mach/imxfb.h
@@ -52,17 +52,11 @@
 #define DMACR_HM(x)	(((x) & 0xf) << 16)
 #define DMACR_TM(x)	((x) & 0xf)
 
-struct imx_fb_videomode {
-	struct fb_videomode mode;
-	u32 pcr;
-	unsigned char	bpp;
-};
-
 /**
  * Define relevant framebuffer information
  */
 struct imx_fb_platform_data {
-	struct imx_fb_videomode *mode;
+	struct fb_videomode *mode;
 	u_int			num_modes;
 
 	u_int		cmap_greyscale:1,
@@ -73,6 +67,8 @@
 	u_int		pwmr;
 	u_int		lscr1;
 	u_int		dmacr;
+	u32 pcr;
+	unsigned char	bpp;
 
 	/** force a memory area to be used, else NULL for dynamic allocation */
 	void		*framebuffer;
diff --git a/arch/arm/mach-imx/include/mach/ocotp.h b/arch/arm/mach-imx/include/mach/ocotp.h
index e758238..7ba5da1 100644
--- a/arch/arm/mach-imx/include/mach/ocotp.h
+++ b/arch/arm/mach-imx/include/mach/ocotp.h
@@ -26,10 +26,24 @@
 #define OCOTP_BIT(n)		FIELD_PREP(OCOTP_BIT_MASK, n)
 #define OCOTP_WIDTH(n)		FIELD_PREP(OCOTP_WIDTH_MASK, (n) - 1)
 
+#define OCOTP_OFFSET_CFG0	0x410
+#define OCOTP_OFFSET_CFG1	0x420
+
 
 int imx_ocotp_read_field(uint32_t field, unsigned *value);
 int imx_ocotp_write_field(uint32_t field, unsigned value);
 int imx_ocotp_permanent_write(int enable);
 bool imx_ocotp_sense_enable(bool enable);
 
+static inline u64 imx_ocotp_read_uid(void __iomem *ocotp)
+{
+	u64 uid;
+
+	uid  = readl(ocotp + OCOTP_OFFSET_CFG0);
+	uid <<= 32;
+	uid |= readl(ocotp + OCOTP_OFFSET_CFG1);
+
+	return uid;
+}
+
 #endif /* __MACH_IMX_OCOTP_H */
diff --git a/common/imx-bbu-nand-fcb.c b/common/imx-bbu-nand-fcb.c
index bb6dd1d..aa3f733 100644
--- a/common/imx-bbu-nand-fcb.c
+++ b/common/imx-bbu-nand-fcb.c
@@ -626,8 +626,15 @@
 			continue;
 
 		ret = mtd_peb_erase(mtd, block + i);
-		if (ret && ret != -EIO)
+		if (ret == -EIO) {
+			newbadblock = 1;
+
+			ret = mtd_peb_mark_bad(mtd, block + i);
+			if (ret)
+				return ret;
+		} else if (ret) {
 			return ret;
+		}
 	}
 
 	while (len > 0) {
diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index 42bde5e..aa7dcb8 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -170,6 +170,16 @@
 	return ret;
 }
 
+static int pca954x_deselect_chan(struct i2c_adapter *adap,
+				 void *client, u32 chan)
+{
+	struct pca954x *data = i2c_get_clientdata(client);
+
+	/* Deselect active channel */
+	data->last_chan = 0;
+	return pca954x_reg_write(adap, client, data->last_chan);
+}
+
 /*
  * I2C init/probing/exit functions
  */
@@ -182,6 +192,7 @@
 	uintptr_t tmp;
 	int ret = -ENODEV;
 	int gpio;
+	bool idle_disconnect;
 
 	data = kzalloc(sizeof(struct pca954x), GFP_KERNEL);
 	if (!data) {
@@ -209,6 +220,9 @@
 	if (ret)
 		goto exit_free;
 
+	idle_disconnect = of_property_read_bool(dev->device_node,
+						"i2c-mux-idle-disconnect");
+
 	data->last_chan = 0;		   /* force the first selection */
 
 	/* Now create an adapter for each channel */
@@ -216,7 +230,10 @@
 
 		data->virt_adaps[num] =
 			i2c_add_mux_adapter(adap, &client->dev, client,
-				0, num, pca954x_select_chan, NULL);
+					    0, num, pca954x_select_chan,
+					    idle_disconnect ?
+					    pca954x_deselect_chan :
+					    NULL);
 
 		if (data->virt_adaps[num] == NULL) {
 			ret = -ENODEV;
diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c
index 31c9102..5ef1d43 100644
--- a/drivers/net/fec_imx.c
+++ b/drivers/net/fec_imx.c
@@ -781,7 +781,8 @@
 	if (IS_ERR(fec->reg_phy)) {
 		if (PTR_ERR(fec->reg_phy) == -EPROBE_DEFER) {
 			ret = -EPROBE_DEFER;
-			goto disable_clk;
+			fec->reg_phy = NULL;
+			goto release_res;
 		}
 		fec->reg_phy = NULL;
 	}
@@ -789,7 +790,7 @@
 	ret = regulator_enable(fec->reg_phy);
 	if (ret) {
 		dev_err(dev, "Failed to enable phy regulator: %d\n", ret);
-		goto disable_clk;
+		goto release_res;
 	}
 
 	phy_reset = of_get_named_gpio(dev->device_node, "phy-reset-gpios", 0);
diff --git a/drivers/video/imx.c b/drivers/video/imx.c
index 947f8d5..d15c2d8 100644
--- a/drivers/video/imx.c
+++ b/drivers/video/imx.c
@@ -152,8 +152,6 @@
 				cmap_static:1,
 				unused:30;
 
-	struct imx_fb_videomode *mode;
-
 	struct fb_info		info;
 	struct device_d		*dev;
 
@@ -293,14 +291,6 @@
 	unsigned long long tmp;
 	struct imxfb_info *fbi = info->priv;
 	u32 pcr;
-	int i;
-
-	for (i = 0; i < info->modes.num_modes; i++) {
-		if (!strcmp(fbi->mode[i].mode.name, mode->name)) {
-			fbi->pcr = fbi->mode[i].pcr;
-			break;
-		}
-	}
 
 	/* physical screen start address	    */
 	writel(VPW_VPW(mode->xres * info->bits_per_pixel / 8 / 4),
@@ -556,7 +546,7 @@
 
 	mode_list = xzalloc(sizeof(*mode_list) * pdata->num_modes);
 	for (i = 0; i < pdata->num_modes; i++)
-		mode_list[i] = pdata->mode[i].mode;
+		mode_list[i] = pdata->mode[i];
 
 	fbi = xzalloc(sizeof(*fbi));
 	info = &fbi->info;
@@ -573,13 +563,12 @@
 	if (IS_ERR(fbi->ipg_clk))
 		return PTR_ERR(fbi->ipg_clk);
 
-	fbi->mode = pdata->mode;
 	iores = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(iores))
 		return PTR_ERR(iores);
 	fbi->regs = IOMEM(iores->start);
 
-	fbi->pcr = pdata->mode->pcr;
+	fbi->pcr = pdata->pcr;
 	fbi->pwmr = pdata->pwmr;
 	fbi->lscr1 = pdata->lscr1;
 	fbi->dmacr = pdata->dmacr;
@@ -588,10 +577,10 @@
 	info->priv = fbi;
 	info->modes.modes = mode_list;
 	info->modes.num_modes = pdata->num_modes;
-	info->mode = &pdata->mode->mode;
-	info->xres = pdata->mode->mode.xres;
-	info->yres = pdata->mode->mode.yres;
-	info->bits_per_pixel = pdata->mode->bpp;
+	info->mode = pdata->mode;
+	info->xres = pdata->mode->xres;
+	info->yres = pdata->mode->yres;
+	info->bits_per_pixel = pdata->bpp;
 	info->fbops = &imxfb_ops;
 
 	dev_info(dev, "i.MX Framebuffer driver\n");
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 84c4071..a8f8a9b 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -406,6 +406,11 @@
 FILE_barebox-embedsky-imx6q-e9.img = start_imx6q_embedsky_e9.pblb.imximg
 image-$(CONFIG_MACH_EMBEDSKY_E9) += barebox-embedsky-imx6q-e9.img
 
+pblb-$(CONFIG_MACH_EMBEST_MARSBOARD) += start_imx6q_marsboard
+CFG_start_imx6q_marsboard.pblb.imximg = $(board)/embest-marsboard/flash-header-embest-marsboard.imxcfg
+FILE_barebox-embest-imx6q-marsboard.img = start_imx6q_marsboard.pblb.imximg
+image-$(CONFIG_MACH_EMBEST_MARSBOARD) += barebox-embest-imx6q-marsboard.img
+
 pblb-$(CONFIG_MACH_EMBEST_RIOTBOARD) += start_imx6s_riotboard
 CFG_start_imx6s_riotboard.pblb.imximg = $(board)/embest-riotboard/flash-header-embest-riotboard.imxcfg
 FILE_barebox-embest-imx6s-riotboard.img = start_imx6s_riotboard.pblb.imximg