diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c index ae18863..ae84209 100644 --- a/arch/arm/boards/sama5d3_xplained/init.c +++ b/arch/arm/boards/sama5d3_xplained/init.c @@ -57,21 +57,30 @@ }; static struct sam9_smc_config sama5d3_xplained_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, + .ncs_read_setup = 1, + .nrd_setup = 2, + .ncs_write_setup = 1, + .nwe_setup = 2, - .ncs_read_pulse = 6, - .nrd_pulse = 4, + .ncs_read_pulse = 5, + .nrd_pulse = 3, .ncs_write_pulse = 5, .nwe_pulse = 3, - .read_cycle = 6, - .write_cycle = 5, + .read_cycle = 8, + .write_cycle = 8, .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 1, + .tdf_cycles = 3, + + .tclr = 3, + .tadl = 10, + .tar = 3, + .ocms = 0, + .trr = 4, + .twb = 5, + .rbnsel = 3, + .nfsel = 1 }; static void ek_add_device_nand(void) @@ -87,7 +96,7 @@ sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config); + sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config); at91_add_device_nand(&nand_pdata); } diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c index e078642..743197f 100644 --- a/arch/arm/boards/sama5d3xek/init.c +++ b/arch/arm/boards/sama5d3xek/init.c @@ -72,21 +72,30 @@ }; static struct sam9_smc_config cm_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, + .ncs_read_setup = 1, + .nrd_setup = 2, + .ncs_write_setup = 1, + .nwe_setup = 2, - .ncs_read_pulse = 6, - .nrd_pulse = 4, + .ncs_read_pulse = 5, + .nrd_pulse = 3, .ncs_write_pulse = 5, .nwe_pulse = 3, - .read_cycle = 6, - .write_cycle = 5, + .read_cycle = 8, + .write_cycle = 8, .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 1, + .tdf_cycles = 3, + + .tclr = 3, + .tadl = 10, + .tar = 3, + .ocms = 0, + .trr = 4, + .twb = 5, + .rbnsel = 3, + .nfsel = 1 }; static void ek_add_device_nand(void) @@ -102,7 +111,7 @@ cm_nand_smc_config.mode |= AT91_SMC_DBW_8; /* configure chip-select 3 (NAND) */ - sam9_smc_configure(0, 3, &cm_nand_smc_config); + sama5_smc_configure(0, 3, &cm_nand_smc_config); at91_add_device_nand(&nand_pdata); } diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c index 961873d..264420d 100644 --- a/arch/arm/cpu/start.c +++ b/arch/arm/cpu/start.c @@ -103,7 +103,7 @@ /* * Maximum malloc space is the Kconfig value if given - * or 64MB. + * or 1GB. */ if (MALLOC_SIZE > 0) { malloc_start = malloc_end - MALLOC_SIZE; @@ -111,8 +111,8 @@ malloc_start = membase; } else { malloc_start = malloc_end - (malloc_end - membase) / 2; - if (malloc_end - malloc_start > SZ_64M) - malloc_start = malloc_end - SZ_64M; + if (malloc_end - malloc_start > SZ_1G) + malloc_start = malloc_end - SZ_1G; } mem_malloc_init((void *)malloc_start, (void *)malloc_end - 1); diff --git a/arch/arm/dts/am335x-phytec-phycore.dts b/arch/arm/dts/am335x-phytec-phycore.dts index 8966b32..5678138 100644 --- a/arch/arm/dts/am335x-phytec-phycore.dts +++ b/arch/arm/dts/am335x-phytec-phycore.dts @@ -209,6 +209,7 @@ &davinci_mdio { pinctrl-names = "default"; pinctrl-0 = <&davinci_mdio_default>; + status = "okay"; }; &phy_sel { @@ -231,6 +232,7 @@ pinctrl-names = "default"; pinctrl-0 = <&emac_rmii1_pins>; dual_emac = <1>; + status = "okay"; }; &gpmc { diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index d9b9111..ffd56ed 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -414,6 +414,11 @@ int to_read; struct android_header_comp *cmp; unsigned long mem_free; + unsigned long mem_start, mem_size; + + ret = sdram_start_and_size(&mem_start, &mem_size); + if (ret) + return ret; fd = open(data->os_file, O_RDONLY); if (fd < 0) { @@ -447,8 +452,17 @@ cmp = &header->kernel; data->os_res = request_sdram_region("akernel", cmp->load_addr, cmp->size); if (!data->os_res) { - ret = -ENOMEM; - goto err_out; + pr_err("Cannot request region 0x%08x - 0x%08x, using default load address\n", + cmp->load_addr, cmp->size); + + data->os_address = mem_start + PAGE_ALIGN(cmp->size * 4); + data->os_res = request_sdram_region("akernel", data->os_address, cmp->size); + if (!data->os_res) { + pr_err("Cannot request region 0x%08x - 0x%08x\n", + cmp->load_addr, cmp->size); + ret = -ENOMEM; + goto err_out; + } } ret = aimage_load_resource(fd, data->os_res, buf, header->page_size); diff --git a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c index 985203a..e69e4a8 100644 --- a/arch/arm/mach-at91/at91sam926x_lowlevel_init.c +++ b/arch/arm/mach-at91/at91sam926x_lowlevel_init.c @@ -130,7 +130,7 @@ at91_sys_write(cfg->matrix_csa, cfg->ebi_csa); /* flash */ - at91_smc_write(cfg->smc_cs, AT91_SMC_MODE, cfg->smc_mode); + at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode); at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle); diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h index d5cf5f7..d19cf82 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -43,12 +43,24 @@ /* Mode register */ u32 mode; u8 tdf_cycles:4; + + /* Timings register */ + u8 tclr; + u8 tadl; + u8 tar; + u8 ocms; + u8 trr; + u8 twb; + u8 rbnsel; + u8 nfsel; }; extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); + +extern void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config); #endif #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ @@ -77,7 +89,26 @@ #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) -#define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ +#define AT91_SAMA5_SMC_TIMINGS 0x0c /* Timings register for CS n */ +#define AT91_SMC_TCLR (0x0f << 0) /* CLE to REN Low Delay */ +#define AT91_SMC_TCLR_(x) ((x) << 0) +#define AT91_SMC_TADL (0x0f << 4) /* ALE to Data Start */ +#define AT91_SMC_TADL_(x) ((x) << 4) +#define AT91_SMC_TAR (0x0f << 8) /* ALE to REN Low Delay */ +#define AT91_SMC_TAR_(x) ((x) << 8) +#define AT91_SMC_OCMS (0x1 << 12) /* Off Chip Memory Scrambling Enable */ +#define AT91_SMC_OCMS_(x) ((x) << 12) +#define AT91_SMC_TRR (0x0f << 16) /* Ready to REN Low Delay */ +#define AT91_SMC_TRR_(x) ((x) << 16) +#define AT91_SMC_TWB (0x0f << 24) /* WEN High to REN to Busy */ +#define AT91_SMC_TWB_(x) ((x) << 24) +#define AT91_SMC_RBNSEL (0x07 << 28) /* Ready/Busy Line Selection */ +#define AT91_SMC_RBNSEL_(x) ((x) << 28) +#define AT91_SMC_NFSEL (0x01 << 31) /* Nand Flash Selection */ +#define AT91_SMC_NFSEL_(x) ((x) << 31) + +#define AT91_SAM9_SMC_MODE 0xc +#define AT91_SAMA5_SMC_MODE 0x10 #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c index c7bfdfd..9f02807 100644 --- a/arch/arm/mach-at91/sam9_smc.c +++ b/arch/arm/mach-at91/sam9_smc.c @@ -17,7 +17,9 @@ #include -#define AT91_SMC_CS_STRIDE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? 0x14 : 0x10) +#define AT91_SAM9_SMC_CS_STRIDE 0x10 +#define AT91_SAMA5_SMC_CS_STRIDE 0x14 +#define AT91_SMC_CS_STRIDE ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_CS_STRIDE : AT91_SAM9_SMC_CS_STRIDE) #define AT91_SMC_CS(id, n) (smc_base_addr[id] + ((n) * AT91_SMC_CS_STRIDE)) static void __iomem *smc_base_addr[2]; @@ -25,9 +27,27 @@ static void sam9_smc_cs_write_mode(void __iomem *base, struct sam9_smc_config *config) { + void __iomem *mode_reg; + + mode_reg = base + ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_MODE : AT91_SAM9_SMC_MODE); + __raw_writel(config->mode | AT91_SMC_TDF_(config->tdf_cycles), - base + AT91_SMC_MODE); + mode_reg); +} + +static void sam9_smc_cs_write_timings(void __iomem *base, + struct sam9_smc_config *config) +{ + __raw_writel(AT91_SMC_TCLR_(config->tclr) + | AT91_SMC_TADL_(config->tadl) + | AT91_SMC_TAR_(config->tar) + | AT91_SMC_OCMS_(config->ocms) + | AT91_SMC_TRR_(config->trr) + | AT91_SMC_TWB_(config->twb) + | AT91_SMC_RBNSEL_(config->rbnsel) + | AT91_SMC_NFSEL_(config->nfsel), + base + AT91_SAMA5_SMC_TIMINGS); } void sam9_smc_write_mode(int id, int cs, @@ -72,7 +92,12 @@ static void sam9_smc_cs_read_mode(void __iomem *base, struct sam9_smc_config *config) { - u32 val = __raw_readl(base + AT91_SMC_MODE); + u32 val; + void __iomem *mode_reg; + + mode_reg = base + ((at91_soc_initdata.type == AT91_SOC_SAMA5D3) ? AT91_SAMA5_SMC_MODE : AT91_SAM9_SMC_MODE); + + val = __raw_readl(mode_reg); config->mode = (val & ~AT91_SMC_NWECYCLE); config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; @@ -120,6 +145,13 @@ sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); } +void sama5_smc_configure(int id, int cs, struct sam9_smc_config *config) +{ + sam9_smc_configure(id, cs, config); + + sam9_smc_cs_write_timings(AT91_SMC_CS(id, cs), config); +} + static int at91sam9_smc_probe(struct device_d *dev) { int id = dev->id;