diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 2229817..2e58f15 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_MACH_CM_FX6) += cm-fx6/ obj-$(CONFIG_MACH_NITROGEN6X) += boundarydevices-nitrogen6x/ obj-$(CONFIG_MACH_CCMX51) += ccxmx51/ +obj-$(CONFIG_MACH_CCMX53) += ccxmx53/ obj-$(CONFIG_MACH_CFA10036) += crystalfontz-cfa10036/ obj-$(CONFIG_MACH_CHUMBY) += chumby_falconwing/ obj-$(CONFIG_MACH_CLEP7212) += clep7212/ @@ -79,13 +80,12 @@ obj-$(CONFIG_MACH_PCA100) += phytec-phycard-imx27/ obj-$(CONFIG_MACH_PCAAL1) += phytec-phycard-omap3/ obj-$(CONFIG_MACH_PCAAXL2) += phytec-phycard-omap4/ -obj-$(CONFIG_MACH_PCAAXL3) += phytec-phycard-imx6/ obj-$(CONFIG_MACH_PCM037) += phytec-phycore-imx31/ obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/ obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/ -obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-phyflex-imx6/ +obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/ obj-$(CONFIG_MACH_PM9261) += pm9261/ diff --git a/arch/arm/boards/ccxmx53/Makefile b/arch/arm/boards/ccxmx53/Makefile new file mode 100644 index 0000000..01c7a25 --- /dev/null +++ b/arch/arm/boards/ccxmx53/Makefile @@ -0,0 +1,2 @@ +obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/ccxmx53/board.c b/arch/arm/boards/ccxmx53/board.c new file mode 100644 index 0000000..0031aed --- /dev/null +++ b/arch/arm/boards/ccxmx53/board.c @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2015 Jason Cobham + * + * Board specific file for the Digi ConnectCore ccxmx53 SoM + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +struct ccwmx53_ident { + const char *id_string; + const int mem_sz; + const char industrial; + const char eth0; + const char eth1; + const char wless; +}; + +static struct ccwmx53_ident ccwmx53_ids[] = { + /* 0x00 - 5500xxxx-xx */ + { "Unknown", 0, 0, 0, 0, 0}, + /* 0x01 - 5500xxxx-xx */ + { "Not supported", 0, 0, 0, 0, 0}, + /* 0x02 - 55001604-01 */ + { "i.MX535@1000MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 1}, + /* 0x03 - 55001605-01 */ + { "i.MX535@1000MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0}, + /* 0x04 - 55001604-02 */ + { "i.MX535@1000MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 1}, + /* 0x05 - 5500xxxx-xx */ + { "i.MX535@1000MHz, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 0}, + /* 0x06 - 55001604-03 */ + { "i.MX535@1000MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1}, + /* 0x07 - 5500xxxx-xx */ + { "i.MX535@1000MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0}, + /* 0x08 - 55001604-04 */ + { "i.MX537@800MHz, Wireless, PHY, Accel", SZ_512M, 1, 1, 0, 1}, + /* 0x09 - 55001605-02 */ + { "i.MX537@800MHz, PHY, Accel", SZ_512M, 1, 1, 0, 0}, + /* 0x0a - 5500xxxx-xx */ + { "i.MX537@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 1}, + /* 0x0b - 55001605-03 */ + { "i.MX537@800MHz, PHY, Ext. Eth, Accel", SZ_1G, 1, 1, 1, 0}, + /* 0x0c - 5500xxxx-xx */ + { "Reserved for future use", 0, 0, 0, 0, 0}, + /* 0x0d - 55001605-05 */ + { "i.MX537@800MHz, PHY, Accel", SZ_1G, 1, 1, 0, 0}, + /* 0x0e - 5500xxxx-xx */ + { "Reserved for future use", 0, 0, 0, 0, 0}, + /* 0x0f - 5500xxxx-xx */ + { "Reserved for future use", 0, 0, 0, 0, 0}, +}; + +static struct ccwmx53_ident *ccwmx53_id; + +/* On these boards, memory information is encoded in the MAC address. + * Print device memory, and option info from lookup table. + * */ +static int ccwmx53_devices_init(void) +{ + u8 hwid[6] = {0}; + char manloc = 0; + + if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || + (hwid[0] < 0x02) || + (hwid[0] >= ARRAY_SIZE(ccwmx53_ids))) { + printf("Module Variant: Unknown (0x%02x) (0x%02x) (0x%02x) (0x%02x) (0x%02x) (0x%02x)\n", + hwid[0], hwid[1], hwid[2], hwid[3], hwid[4], hwid[5]); + memset(hwid, 0x00, sizeof(hwid)); + } + + ccwmx53_id = &ccwmx53_ids[hwid[0]]; + printf("Module Variant: %s (0x%02x)\n", ccwmx53_id->id_string, hwid[0]); + + if (hwid[0]) { + printf("Module HW Rev : %02x\n", hwid[1] + 1); + switch (hwid[2] & 0xc0) { + case 0x00: + manloc = 'B'; + break; + case 0x40: + manloc = 'W'; + break; + case 0x80: + manloc = 'S'; + break; + default: + manloc = 'N'; + break; + } + + printf("Module Serial : %c%d\n", manloc, + ((hwid[2] & 0x3f) << 24) | + (hwid[3] << 16) | + (hwid[4] << 8) | + hwid[5]); + + printf("Module RAM : %dK\n", (ccwmx53_id->mem_sz) / 1024); + + } else { + return -ENOSYS; + } + + armlinux_set_architecture(MACH_TYPE_CCWMX53); + + return 0; +} +device_initcall(ccwmx53_devices_init); + +static int ccxmx53_init(void) +{ + unsigned char value = 0; + struct i2c_adapter *adapter = NULL; + struct i2c_client client; + int addr = 0x68; /* da9053 device address is 0x68 */ + int bus = 0; /* I2C0 bus */ + + if (!of_machine_is_compatible("digi,imx53-ccxmx53")) + return 0; + + adapter = i2c_get_adapter(bus); + if (adapter) { + client.adapter = adapter; + client.addr = addr; + /* Enable 3.3V ext regulator. */ + value = 0xfa; + if (i2c_write_reg(&client, 0x19, &value, 1) < 0) { + printf("Can't set regulator. I2C write failed\n"); + return -ENOSYS; + } + } else { + printf("Can't set regulator. No I2C Adapter\n"); + return -ENOSYS; + } + + armlinux_set_architecture(MACH_TYPE_CCMX53); + + barebox_set_model("Digi CCMX53"); + barebox_set_hostname("ccxmx53"); + + imx53_bbu_internal_nand_register_handler("nand", + BBU_HANDLER_FLAG_DEFAULT, SZ_512K); + + return 0; +} +late_initcall(ccxmx53_init); + +static int ccxmx53_postcore_init(void) +{ + if (!of_machine_is_compatible("digi,imx53-ccxmx53")) + return 0; + + imx53_init_lowlevel(800); + + return 0; +} +postcore_initcall(ccxmx53_postcore_init); diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg new file mode 100644 index 0000000..6f1cab6 --- /dev/null +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg @@ -0,0 +1,67 @@ +loadaddr 0x70000000 +soc imx53 +dcdofs 0x400 +wm 32 0x53fa8554 0x00200000 +wm 32 0x53fa8558 0x00200040 +wm 32 0x53fa8560 0x00200000 +wm 32 0x53fa8564 0x00200040 +wm 32 0x53fa8568 0x00200040 +wm 32 0x53fa8570 0x00200000 +wm 32 0x53fa8574 0x00200000 +wm 32 0x53fa8578 0x00200000 +wm 32 0x53fa857c 0x00200040 +wm 32 0x53fa8580 0x00200040 +wm 32 0x53fa8584 0x00200000 +wm 32 0x53fa8588 0x00200000 +wm 32 0x53fa8590 0x00200040 +wm 32 0x53fa8594 0x00200000 +wm 32 0x53fa86f0 0x00200000 +wm 32 0x53fa86f4 0x00000200 +wm 32 0x53fa86fc 0x00000000 +wm 32 0x53fa8714 0x00000000 +wm 32 0x53fa8718 0x00200000 +wm 32 0x53fa871c 0x00200000 +wm 32 0x53fa8720 0x00200000 +wm 32 0x53fa8724 0x06000000 +wm 32 0x53fa8728 0x00200000 +wm 32 0x53fa872c 0x00200000 +wm 32 0x63fd9088 0x2d313331 +wm 32 0x63fd9090 0x393b3836 +wm 32 0x63fd90f8 0x00000800 +wm 32 0x63fd907c 0x020c0211 +wm 32 0x63fd9080 0x014c0155 +wm 32 0x63fd9018 0x000016d0 +wm 32 0x63fd9000 0xc4110000 +wm 32 0x63fd900c 0x4d5122d2 +wm 32 0x63fd9010 0x92d18a22 +wm 32 0x63fd9014 0x00c70092 +wm 32 0x63fd902c 0x000026d2 +wm 32 0x63fd9030 0x009f000e +wm 32 0x63fd9008 0x12272000 +wm 32 0x63fd9004 0x00030012 +wm 32 0x63fd901c 0x04008010 +wm 32 0x63fd901c 0x00008032 +wm 32 0x63fd901c 0x00008033 +wm 32 0x63fd901c 0x00008031 +wm 32 0x63fd901c 0x0b5280b0 +wm 32 0x63fd901c 0x04008010 +wm 32 0x63fd901c 0x00008020 +wm 32 0x63fd901c 0x00008020 +wm 32 0x63fd901c 0x0a528030 +wm 32 0x63fd901c 0x03c68031 +wm 32 0x63fd901c 0x00448031 +wm 32 0x63fd901c 0x04008018 +wm 32 0x63fd901c 0x0000803a +wm 32 0x63fd901c 0x0000803b +wm 32 0x63fd901c 0x00008039 +wm 32 0x63fd901c 0x0b528138 +wm 32 0x63fd901c 0x04008018 +wm 32 0x63fd901c 0x00008028 +wm 32 0x63fd901c 0x00008028 +wm 32 0x63fd901c 0x0a528038 +wm 32 0x63fd901c 0x03c68039 +wm 32 0x63fd901c 0x00448039 +wm 32 0x63fd9020 0x00005800 +wm 32 0x63fd9058 0x00022225 +wm 32 0x63fd901c 0x00000000 +wm 32 0x63fd9040 0x04b80003 diff --git a/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg new file mode 100644 index 0000000..b707dd6 --- /dev/null +++ b/arch/arm/boards/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg @@ -0,0 +1,67 @@ +loadaddr 0x70000000 +soc imx53 +dcdofs 0x400 +wm 32 0x53fa8554 0x00200000 +wm 32 0x53fa8558 0x00200040 +wm 32 0x53fa8560 0x00200000 +wm 32 0x53fa8564 0x00200040 +wm 32 0x53fa8568 0x00200040 +wm 32 0x53fa8570 0x00200000 +wm 32 0x53fa8574 0x00200000 +wm 32 0x53fa8578 0x00200000 +wm 32 0x53fa857c 0x00200040 +wm 32 0x53fa8580 0x00200040 +wm 32 0x53fa8584 0x00200000 +wm 32 0x53fa8588 0x00200000 +wm 32 0x53fa8590 0x00200040 +wm 32 0x53fa8594 0x00200000 +wm 32 0x53fa86f0 0x00200000 +wm 32 0x53fa86f4 0x00000200 +wm 32 0x53fa86fc 0x00000000 +wm 32 0x53fa8714 0x00000000 +wm 32 0x53fa8718 0x00200000 +wm 32 0x53fa871c 0x00200000 +wm 32 0x53fa8720 0x00200000 +wm 32 0x53fa8724 0x06000000 +wm 32 0x53fa8728 0x00200000 +wm 32 0x53fa872c 0x00200000 +wm 32 0x63fd9088 0x2d313331 +wm 32 0x63fd9090 0x393b3836 +wm 32 0x63fd90f8 0x00000800 +wm 32 0x63fd907c 0x020c0211 +wm 32 0x63fd9080 0x014c0155 +wm 32 0x63fd9018 0x000016d0 +wm 32 0x63fd9000 0xc2110000 +wm 32 0x63fd900c 0x4d5122d2 +wm 32 0x63fd9010 0x92d18a22 +wm 32 0x63fd9014 0x00c70092 +wm 32 0x63fd902c 0x000026d2 +wm 32 0x63fd9030 0x009f000e +wm 32 0x63fd9008 0x12272000 +wm 32 0x63fd9004 0x00030012 +wm 32 0x63fd901c 0x04008010 +wm 32 0x63fd901c 0x00008032 +wm 32 0x63fd901c 0x00008033 +wm 32 0x63fd901c 0x00008031 +wm 32 0x63fd901c 0x0b5280b0 +wm 32 0x63fd901c 0x04008010 +wm 32 0x63fd901c 0x00008020 +wm 32 0x63fd901c 0x00008020 +wm 32 0x63fd901c 0x0a528030 +wm 32 0x63fd901c 0x03c68031 +wm 32 0x63fd901c 0x00448031 +wm 32 0x63fd901c 0x04008018 +wm 32 0x63fd901c 0x0000803a +wm 32 0x63fd901c 0x0000803b +wm 32 0x63fd901c 0x00008039 +wm 32 0x63fd901c 0x0b528138 +wm 32 0x63fd901c 0x04008018 +wm 32 0x63fd901c 0x00008028 +wm 32 0x63fd901c 0x00008028 +wm 32 0x63fd901c 0x0a528038 +wm 32 0x63fd901c 0x03c68039 +wm 32 0x63fd901c 0x00448039 +wm 32 0x63fd9020 0x00005800 +wm 32 0x63fd9058 0x00022225 +wm 32 0x63fd901c 0x00000000 +wm 32 0x63fd9040 0x04b80003 diff --git a/arch/arm/boards/ccxmx53/lowlevel.c b/arch/arm/boards/ccxmx53/lowlevel.c new file mode 100644 index 0000000..b321811 --- /dev/null +++ b/arch/arm/boards/ccxmx53/lowlevel.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2013 Sascha Hauer + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +BAREBOX_IMD_TAG_STRING(ccxmx53_memsize_SZ_512M, IMD_TYPE_PARAMETER, "memsize=512", 0); +BAREBOX_IMD_TAG_STRING(ccxmx53_memsize_SZ_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0); + +static void __noreturn start_imx53_ccxmx53_common(uint32_t size, + void *fdt_blob_fixed_offset) +{ + void *fdt; + + imx5_cpu_lowlevel_init(); + arm_setup_stack(0xf8020000 - 8); + + fdt = fdt_blob_fixed_offset - get_runtime_offset(); + barebox_arm_entry(0x70000000, size, fdt); +} + +#define CCMX53_ENTRY(name, fdt_name, memory_size) \ + ENTRY_FUNCTION(name, r0, r1, r2) \ + { \ + extern char __dtb_##fdt_name##_start[]; \ + \ + IMD_USED(ccxmx53_memsize_##memory_size); \ + \ + start_imx53_ccxmx53_common(memory_size, \ + __dtb_##fdt_name##_start); \ + } + +CCMX53_ENTRY(start_ccxmx53_512mb, imx53_ccxmx53, SZ_512M); +CCMX53_ENTRY(start_ccxmx53_1gib, imx53_ccxmx53, SZ_1G); diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c index 378f4e8..7b3993d 100644 --- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c @@ -91,27 +91,18 @@ }; #ifdef CONFIG_USB -static void imx35_usb_init(void) -{ - unsigned int tmp; +#ifndef CONFIG_USB_GADGET +struct imxusb_platformdata otg_pdata = { + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, + .mode = IMX_USB_MODE_HOST, + .phymode = USBPHY_INTERFACE_MODE_UTMI, +}; +#endif - /* Host 1 */ - tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x600); - tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | - MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); - tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; - tmp |= MX35_H1_USBTE_BIT | MX35_H1_PM_BIT | MX35_H1_TLL_BIT ; - tmp |= MX35_H1_IPPUE_DOWN_BIT; - writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x600); - - tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x584); - tmp |= 3 << 30; - writel(tmp, MX35_USB_OTG_BASE_ADDR + 0x584); - - /* Set to Host mode */ - tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x5a8); - writel(tmp | 0x3, MX35_USB_OTG_BASE_ADDR + 0x5a8); -} +struct imxusb_platformdata hs_pdata = { + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN, + .mode = IMX_USB_MODE_HOST, +}; #endif #ifdef CONFIG_USB_GADGET @@ -206,9 +197,12 @@ gpio_direction_output(1, 0); #ifdef CONFIG_USB - imx35_usb_init(); - add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX35_USB_HS_BASE_ADDR, NULL); +#ifndef CONFIG_USB_GADGET + imx_add_usb((void *)MX35_USB_OTG_BASE_ADDR, 0, &otg_pdata); #endif + imx_add_usb((void *)MX35_USB_HS_BASE_ADDR, 1, &hs_pdata); +#endif + #ifdef CONFIG_USB_GADGET /* Workaround ENGcm09152 */ tmp = readl(MX35_USB_OTG_BASE_ADDR + 0x608); diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile b/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile index cc4078f..01c7a25 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-mx6sx-sabresdb.dcd.o -extra-y += flash-header-mx6sx-sabresdb.dcd.S flash-header-mx6sx-sabresdb.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c index 353b460..ca22eba 100644 --- a/arch/arm/boards/freescale-mx6sx-sabresdb/board.c +++ b/arch/arm/boards/freescale-mx6sx-sabresdb/board.c @@ -241,9 +241,11 @@ imx6sx_sdb_setup_fec(); + barebox_set_hostname("mx6sx-sabresdb"); + imx6_bbu_internal_mmc_register_handler("sd", "/dev/mmc3", BBU_HANDLER_FLAG_DEFAULT); return 0; } -console_initcall(imx6sx_sdb_coredevices_init); +coredevice_initcall(imx6sx_sdb_coredevices_init); diff --git a/arch/arm/boards/gateworks-ventana/clocks.imxcfg b/arch/arm/boards/gateworks-ventana/clocks.imxcfg deleted file mode 100644 index bfd5331..0000000 --- a/arch/arm/boards/gateworks-ventana/clocks.imxcfg +++ /dev/null @@ -1,8 +0,0 @@ -wm 32 MX6_CCM_CCGR0 0x00C03F3F -wm 32 MX6_CCM_CCGR1 0x0030FC03 -wm 32 MX6_CCM_CCGR2 0x0FFFC000 -wm 32 MX6_CCM_CCGR3 0x3FF00000 -wm 32 MX6_CCM_CCGR4 0xFFFFF300 -wm 32 MX6_CCM_CCGR5 0x0F0000C3 -wm 32 MX6_CCM_CCGR6 0x000003FF -wm 32 MX6_CCM_CCOSR 0x000000FB diff --git a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg index 75271e4..f4506f1 100644 --- a/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg +++ b/arch/arm/boards/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg @@ -8,4 +8,3 @@ #include "ram-base.imxcfg" #include "quad_128x64.imxcfg" -#include "clocks.imxcfg" diff --git a/arch/arm/boards/phytec-phycard-imx6/Makefile b/arch/arm/boards/phytec-phycard-imx6/Makefile deleted file mode 100644 index de67f04..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += board.o -lwl-y += lowlevel.o -bbenv-y += defaultenv-phycard-imx6 diff --git a/arch/arm/boards/phytec-phycard-imx6/board.c b/arch/arm/boards/phytec-phycard-imx6/board.c deleted file mode 100644 index 27b84aa..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/board.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2014 Christian Hemp, Phytec Messtechnik GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -static int phytec_pcaaxl3_init(void) -{ - if (!of_machine_is_compatible("phytec,imx6q-pcaaxl3")) - return 0; - - switch (bootsource_get()) { - case BOOTSOURCE_MMC: - of_device_enable_path("/chosen/environment-sd"); - break; - default: - case BOOTSOURCE_NAND: - of_device_enable_path("/chosen/environment-nand"); - break; - } - - imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); - - defaultenv_append_directory(defaultenv_phycard_imx6); - - return 0; -} -device_initcall(phytec_pcaaxl3_init); diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/nand b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/nand deleted file mode 100644 index 3f3a9aa..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/nand +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -global.bootm.oftree="/dev/nand0.oftree.bb" -bootargs-ip -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" - diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/sd-ext3 b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/sd-ext3 deleted file mode 100644 index fd35fe0..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/boot/sd-ext3 +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -global.bootm.image="/mnt/mmc/linuximage" -global.bootm.oftree="/mnt/mmc/oftree" -bootargs-ip -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait rw" diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/init/automount b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/init/automount deleted file mode 100644 index 49d99bd..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/init/automount +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - -# automount tftp server based on $eth0.serverip - -mkdir -p /mnt/tftp -automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' - -mkdir -p /mnt/mmc -automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc' diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/boot.default b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/boot.default deleted file mode 100644 index 026a25c..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/boot.default +++ /dev/null @@ -1 +0,0 @@ -nand diff --git a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/hostname b/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/hostname deleted file mode 100644 index 47b16cc..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/defaultenv-phycard-imx6/nv/hostname +++ /dev/null @@ -1 +0,0 @@ -phyCARD-i.MX6 diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg deleted file mode 100644 index 62a24ed..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg +++ /dev/null @@ -1,9 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x54597955; \ - -#define SETUP_MDOR_MDASP_MDCTL \ - wm 32 0x021b0030 0x00591023; \ - wm 32 0x021b0040 0x00000027; \ - wm 32 0x021b0000 0x831a0000 - -#include "flash-header-phytec-pcaaxl3.h" diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg deleted file mode 100644 index bab726d..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg +++ /dev/null @@ -1,9 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3a3f7975; \ - -#define SETUP_MDOR_MDASP_MDCTL \ - wm 32 0x021b0030 0x003f1023; \ - wm 32 0x021b0040 0x00000017; \ - wm 32 0x021b0000 0xc21a0000 - -#include "flash-header-phytec-pcaaxl3.h" diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg deleted file mode 100644 index 512f6cb..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg +++ /dev/null @@ -1,9 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x54597955; \ - -#define SETUP_MDOR_MDASP_MDCTL \ - wm 32 0x021b0030 0x00591023; \ - wm 32 0x021b0040 0x00000027; \ - wm 32 0x021b0000 0xc31a0000 - -#include "flash-header-phytec-pcaaxl3.h" diff --git a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h deleted file mode 100644 index a03b8dc..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/flash-header-phytec-pcaaxl3.h +++ /dev/null @@ -1,98 +0,0 @@ -soc imx6 -loadaddr 0x20000000 -dcdofs 0x400 - -wm 32 0x020e05a8 0x00000028 -wm 32 0x020e05b0 0x00000028 -wm 32 0x020e0524 0x00000028 -wm 32 0x020e051c 0x00000028 -wm 32 0x020e0518 0x00000028 -wm 32 0x020e050c 0x00000028 -wm 32 0x020e05b8 0x00000028 -wm 32 0x020e05c0 0x00000028 -wm 32 0x020e05ac 0x00000028 -wm 32 0x020e05b4 0x00000028 -wm 32 0x020e0528 0x00000028 -wm 32 0x020e0520 0x00000028 -wm 32 0x020e0514 0x00000028 -wm 32 0x020e0510 0x00000028 -wm 32 0x020e05bc 0x00000028 -wm 32 0x020e05c4 0x00000028 -wm 32 0x020e056c 0x00000028 -wm 32 0x020e0578 0x00000028 -wm 32 0x020e0588 0x00000028 -wm 32 0x020e0594 0x00000028 -wm 32 0x020e057c 0x00000028 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000028 -wm 32 0x020e05a0 0x00000028 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e0788 0x00000028 -wm 32 0x020e0794 0x00000028 -wm 32 0x020e079c 0x00000028 -wm 32 0x020e07a0 0x00000028 -wm 32 0x020e07a4 0x00000028 -wm 32 0x020e07a8 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e074c 0x00000028 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e078c 0x00000028 -wm 32 0x020e0798 0x000c0000 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b0018 0x00091740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b0010 0xff328f64 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0008 0x09444040 -wm 32 0x021b0004 0x00025576 - -SETUP_MDCFG0 -SETUP_MDOR_MDASP_MDCTL - -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00048039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b083c 0x4350035e -wm 32 0x021b0840 0x035c0358 -wm 32 0x021b483c 0x436e0376 -wm 32 0x021b4840 0x03770352 -wm 32 0x021b0848 0x3c333436 -wm 32 0x021b4848 0x35332f3b -wm 32 0x021b0850 0x37363e39 -wm 32 0x021b4850 0x432f433d -wm 32 0x021b080c 0x0013001b -wm 32 0x021b0810 0x003b0034 -wm 32 0x021b480c 0x0037004b -wm 32 0x021b4810 0x004b0055 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b001c 0x00000000 -wm 32 0x021b0404 0x00011006 -wm 32 0x020e0010 0xf00000ff -wm 32 0x020e0018 0x007f007f -wm 32 0x020e001c 0x007f007f -wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c b/arch/arm/boards/phytec-phycard-imx6/lowlevel.c deleted file mode 100644 index 09ab645..0000000 --- a/arch/arm/boards/phytec-phycard-imx6/lowlevel.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2014 Christian Hemp - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline void setup_uart(void) -{ - void __iomem *iomuxbase = IOMEM(MX6_IOMUXC_BASE_ADDR); - - writel(0x4, iomuxbase + 0x01f8); - - imx6_ungate_all_peripherals(); - imx6_uart_setup_ll(); - - putc_ll('>'); -} - -extern char __dtb_imx6q_phytec_pbaa03_start[]; - -static void __noreturn start_imx6q_phytec_pbaa03_common(uint32_t size) -{ - void *fdt; - - imx6_cpu_lowlevel_init(); - - arm_setup_stack(0x00920000 - 8); - - if (IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - - fdt = __dtb_imx6q_phytec_pbaa03_start - get_runtime_offset(); - - barebox_arm_entry(0x10000000, size, fdt); -} - -ENTRY_FUNCTION(start_phytec_pbaa03_1gib, r0, r1, r2) -{ - start_imx6q_phytec_pbaa03_common(SZ_1G); -} - -ENTRY_FUNCTION(start_phytec_pbaa03_1gib_1bank, r0, r1, r2) -{ - start_imx6q_phytec_pbaa03_common(SZ_1G); -} - -ENTRY_FUNCTION(start_phytec_pbaa03_2gib, r0, r1, r2) -{ - start_imx6q_phytec_pbaa03_common(SZ_2G); -} diff --git a/arch/arm/boards/phytec-phyflex-imx6/Makefile b/arch/arm/boards/phytec-phyflex-imx6/Makefile deleted file mode 100644 index 11e1c7d..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-y += board.o -lwl-y += lowlevel.o -bbenv-y += defaultenv-phyflex-imx6 diff --git a/arch/arm/boards/phytec-phyflex-imx6/board.c b/arch/arm/boards/phytec-phyflex-imx6/board.c deleted file mode 100644 index d3100c8..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/board.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) 2013 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation. - * - */ -#define pr_fmt(fmt) "phyFLEX-i.MX6: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#define PHYFLEX_MODULE_REV_1 0x1 -#define PHYFLEX_MODULE_REV_2 0x2 - -#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \ - MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS - -#define MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(GPIO_2_11_PD_CTL)) -#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, GPIO_2_11_PD_CTL) - -#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) - -static void phyflex_err006282_workaround(void) -{ - /* - * Boards beginning with 1362.2 have the SD4_DAT3 pin connected - * to the CMIC. If this pin isn't toggled within 10s the boards - * reset. The pin is unconnected on older boards, so we do not - * need a check for older boards before applying this fixup. - */ - - gpio_direction_output(MX6_PHYFLEX_ERR006282, 0); - mdelay(2); - gpio_direction_output(MX6_PHYFLEX_ERR006282, 1); - mdelay(2); - gpio_set_value(MX6_PHYFLEX_ERR006282, 0); - - if (cpu_is_mx6q()) - mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD); - else if (cpu_is_mx6dl()) - mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11); - - gpio_direction_input(MX6_PHYFLEX_ERR006282); -} - -static unsigned int pfla02_module_revision; - -static unsigned int get_module_rev(void) -{ - unsigned int val = 0; - - val = gpio_get_value(IMX_GPIO_NR(2, 12)); - val |= (gpio_get_value(IMX_GPIO_NR(2, 13)) << 1); - val |= (gpio_get_value(IMX_GPIO_NR(2, 14)) << 2); - val |= (gpio_get_value(IMX_GPIO_NR(2, 15)) << 3); - - return 16 - val; -} - -static int phytec_pfla02_init(void) -{ - int ret; - char *environment_path, *envdev; - - if (!of_machine_is_compatible("phytec,imx6q-pfla02") && - !of_machine_is_compatible("phytec,imx6dl-pfla02") && - !of_machine_is_compatible("phytec,imx6s-pfla02")) - return 0; - - phyflex_err006282_workaround(); - - imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); - - pfla02_module_revision = get_module_rev(); - globalvar_add_simple_int("board.revision", &pfla02_module_revision, "%u"); - - pr_info("Module Revision: %u\n", pfla02_module_revision); - - switch (bootsource_get()) { - case BOOTSOURCE_MMC: - environment_path = asprintf("/chosen/environment-sd%d", - bootsource_get_instance() + 1); - envdev = "MMC"; - break; - case BOOTSOURCE_NAND: - environment_path = asprintf("/chosen/environment-nand"); - envdev = "NAND flash"; - break; - default: - case BOOTSOURCE_SPI: - environment_path = asprintf("/chosen/environment-spinor"); - envdev = "SPI NOR flash"; - break; - } - - ret = of_device_enable_path(environment_path); - if (ret < 0) - pr_warn("Failed to enable environment partition '%s' (%d)\n", - environment_path, ret); - - free(environment_path); - - pr_notice("Using environment in %s\n", envdev); - - return 0; -} -device_initcall(phytec_pfla02_init); - -static int phytec_pbab0x_init(void) -{ - if (!of_machine_is_compatible("phytec,imx6x-pbab01") && - !of_machine_is_compatible("phytec,imx6dl-pbab05") && - !of_machine_is_compatible("phytec,imx6q-pbab02")) - return 0; - - defaultenv_append_directory(defaultenv_phyflex_imx6); - - return 0; -} -device_initcall(phytec_pbab0x_init); diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/nand b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/nand deleted file mode 100644 index 79dc03c..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -global.bootm.oftree="/dev/nand0.oftree.bb" -bootargs-ip -global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/sd-ext3 b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/sd-ext3 deleted file mode 100644 index fd35fe0..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/boot/sd-ext3 +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -global.bootm.image="/mnt/mmc/linuximage" -global.bootm.oftree="/mnt/mmc/oftree" -bootargs-ip -global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait rw" diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/init/automount b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/init/automount deleted file mode 100644 index 49d99bd..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/init/automount +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/sh - -if [ "$1" = menu ]; then - init-menu-add-entry "$0" "Automountpoints" - exit -fi - -# automount tftp server based on $eth0.serverip - -mkdir -p /mnt/tftp -automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' - -mkdir -p /mnt/mmc -automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc' diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/boot.default b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/boot.default deleted file mode 100644 index 026a25c..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/boot.default +++ /dev/null @@ -1 +0,0 @@ -nand diff --git a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/hostname b/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/hostname deleted file mode 100644 index 192f6b4..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/defaultenv-phyflex-imx6/nv/hostname +++ /dev/null @@ -1 +0,0 @@ -phyFLEX-i.MX6 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg deleted file mode 100644 index 75dc982..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg +++ /dev/null @@ -1,8 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 - -#define SETUP_MDASP_MDCTL \ - wm 32 0x021b0040 0x00000027; \ - wm 32 0x021b0000 0x831a0000 - -#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg deleted file mode 100644 index 1f1fbe5..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg +++ /dev/null @@ -1,8 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x3c409b85 - -#define SETUP_MDASP_MDCTL \ - wm 32 0x021b0040 0x00000017; \ - wm 32 0x021b0000 0xc21a0000 - -#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg deleted file mode 100644 index aa01c05..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg +++ /dev/null @@ -1,8 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 - -#define SETUP_MDASP_MDCTL \ - wm 32 0x021b0040 0x00000027; \ - wm 32 0x021b0000 0xC31A0000 - -#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg deleted file mode 100644 index c8d33cf..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg +++ /dev/null @@ -1,8 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x8c929b85 - -#define SETUP_MDASP_MDCTL \ - wm 32 0x021b0040 0x00000047; \ - wm 32 0x021b0000 0xC41A0000 - -#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h deleted file mode 100644 index 93291e9..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02.h +++ /dev/null @@ -1,102 +0,0 @@ -soc imx6 -loadaddr 0x20000000 -dcdofs 0x400 - -wm 32 0x020e0798 0x000C0000 -wm 32 0x020e0758 0x00000000 -wm 32 0x020e0588 0x00000030 -wm 32 0x020e0594 0x00000030 -wm 32 0x020e056c 0x00000030 -wm 32 0x020e0578 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e057c 0x00000030 -wm 32 0x020e058c 0x00000000 -wm 32 0x020e059c 0x00000030 -wm 32 0x020e05a0 0x00000030 -wm 32 0x020e0590 0x00003000 -wm 32 0x020e0598 0x00003000 -wm 32 0x020e078c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e05a8 0x00000028 -wm 32 0x020e05b0 0x00000028 -wm 32 0x020e0524 0x00000028 -wm 32 0x020e051c 0x00000028 -wm 32 0x020e0518 0x00000028 -wm 32 0x020e050c 0x00000028 -wm 32 0x020e05b8 0x00000028 -wm 32 0x020e05c0 0x00000028 -wm 32 0x020e0774 0x00020000 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e0788 0x00000028 -wm 32 0x020e0794 0x00000028 -wm 32 0x020e079c 0x00000028 -wm 32 0x020e07a0 0x00000028 -wm 32 0x020e07a4 0x00000028 -wm 32 0x020e07a8 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e05ac 0x00000028 -wm 32 0x020e05b4 0x00000028 -wm 32 0x020e0528 0x00000028 -wm 32 0x020e0520 0x00000028 -wm 32 0x020e0514 0x00000028 -wm 32 0x020e0510 0x00000028 -wm 32 0x020e05bc 0x00000028 -wm 32 0x020e05c4 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b080c 0x00110011 -wm 32 0x021b0810 0x00240024 -wm 32 0x021b480c 0x00260038 -wm 32 0x021b4810 0x002C0038 -wm 32 0x021b083c 0x03400350 -wm 32 0x021b0840 0x03440340 -wm 32 0x021b483c 0x034C0354 -wm 32 0x021b4840 0x035C033C -wm 32 0x021b0848 0x322A2A2A -wm 32 0x021b4848 0x302C2834 -wm 32 0x021b0850 0x34303834 -wm 32 0x021b4850 0x422A3E36 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0008 0x09444040 - -SETUP_MDCFG0 - -wm 32 0x021b0010 0xff538f64 -wm 32 0x021b0014 0x01ff0124 -wm 32 0x021b0018 0x00091740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x003F1023 - -SETUP_MDASP_MDCTL - -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00048031 -wm 32 0x021b001c 0x00048039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 -wm 32 0x020e0010 0xf00000ff -wm 32 0x020e0018 0x007F007F -wm 32 0x020e001c 0x007F007F -wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg deleted file mode 100644 index e768670..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +++ /dev/null @@ -1,8 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x8c929b85 - -#define SETUP_MDASP_MDCTL \ - wm 32 0x021b0040 0x00000017; \ - wm 32 0x021b0000 0xc21a0000 - -#include "flash-header-phytec-pfla02dl.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h deleted file mode 100644 index 337488b..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02dl.h +++ /dev/null @@ -1,98 +0,0 @@ -soc imx6 -loadaddr 0x20000000 -dcdofs 0x400 - -wm 32 0x020e0774 0x000C0000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04ac 0x00000030 -wm 32 0x020e04b0 0x00000030 -wm 32 0x020e0464 0x00000030 -wm 32 0x020e0490 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0494 0x00000030 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00000030 -wm 32 0x020e04b8 0x00000030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0750 0x00020000 -wm 32 0x020e04bc 0x00000028 -wm 32 0x020e04c0 0x00000028 -wm 32 0x020e04c4 0x00000028 -wm 32 0x020e04c8 0x00000028 -wm 32 0x020e04cc 0x00000028 -wm 32 0x020e04d0 0x00000028 -wm 32 0x020e04d4 0x00000028 -wm 32 0x020e04d8 0x00000028 -wm 32 0x020e0760 0x00020000 -wm 32 0x020e0764 0x00000028 -wm 32 0x020e0770 0x00000028 -wm 32 0x020e0778 0x00000028 -wm 32 0x020e077c 0x00000028 -wm 32 0x020e0780 0x00000028 -wm 32 0x020e0784 0x00000028 -wm 32 0x020e078c 0x00000028 -wm 32 0x020e0748 0x00000028 -wm 32 0x020e0470 0x00000028 -wm 32 0x020e0474 0x00000028 -wm 32 0x020e0478 0x00000028 -wm 32 0x020e047c 0x00000028 -wm 32 0x020e0480 0x00000028 -wm 32 0x020e0484 0x00000028 -wm 32 0x020e0488 0x00000028 -wm 32 0x020e048c 0x00000028 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1380003 -wm 32 0x021b080c 0x00110011 -wm 32 0x021b0810 0x00240024 -wm 32 0x021b480c 0x00260038 -wm 32 0x021b4810 0x002C0038 -wm 32 0x021b083c 0x02480248 -wm 32 0x021b0840 0x022f022d -wm 32 0x021b483c 0x02540258 -wm 32 0x021b4840 0x0236021e -wm 32 0x021b0848 0x332f3033 -wm 32 0x021b4848 0x302d2c35 -wm 32 0x021b0850 0x3030362a -wm 32 0x021b4850 0x3423372d -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b481c 0x33333333 -wm 32 0x021b4820 0x33333333 -wm 32 0x021b4824 0x33333333 -wm 32 0x021b4828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0008 0x09444040 - -SETUP_MDCFG0 - -wm 32 0x021b0010 0xff538f64 -wm 32 0x021b0014 0x01ff0124 -wm 32 0x021b0018 0x00091740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x003F1023 - -SETUP_MDASP_MDCTL - -wm 32 0x021b001c 0x04088032 -wm 32 0x021b001c 0x0408803a -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x0000803b -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x00428039 -wm 32 0x021b001c 0x09408030 -wm 32 0x021b001c 0x09408038 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b001c 0x04008048 -wm 32 0x021b0020 0x00007800 -wm 32 0x021b0818 0x00011117 -wm 32 0x021b4818 0x00011117 -wm 32 0x021b0004 0x00025576 -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg b/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg deleted file mode 100644 index 6a46cd9..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg +++ /dev/null @@ -1,8 +0,0 @@ -#define SETUP_MDCFG0 \ - wm 32 0x021b000c 0x565c9b85 - -#define SETUP_MDASP_MDCTL \ - wm 32 0x021b0040 0x00000017; \ - wm 32 0x021b0000 0x83190000 - -#include "flash-header-phytec-pfla02dl.h" diff --git a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c b/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c deleted file mode 100644 index 82c0244..0000000 --- a/arch/arm/boards/phytec-phyflex-imx6/lowlevel.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2013 Sascha Hauer - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static inline void setup_uart(void) -{ - void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; - - writel(0x4, iomuxbase + 0x01f8); - - imx6_ungate_all_peripherals(); - imx6_uart_setup_ll(); - - putc_ll('>'); -} - -#define SZ_4G 0xEFFFFFF8 - -BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_SZ_512M, IMD_TYPE_PARAMETER, "memsize=512", 0); -BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_SZ_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0); -BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_SZ_2G, IMD_TYPE_PARAMETER, "memsize=2048", 0); -BAREBOX_IMD_TAG_STRING(phyflex_mx6_memsize_SZ_4G, IMD_TYPE_PARAMETER, "memsize=4096", 0); - -static void __noreturn start_imx6_phytec_common(uint32_t size, - bool do_early_uart_config, - void *fdt_blob_fixed_offset) -{ - void *fdt; - - imx6_cpu_lowlevel_init(); - - arm_setup_stack(0x00920000 - 8); - - if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL)) - setup_uart(); - - fdt = fdt_blob_fixed_offset - get_runtime_offset(); - barebox_arm_entry(0x10000000, size, fdt); -} - -#define PHYTEC_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \ - ENTRY_FUNCTION(name, r0, r1, r2) \ - { \ - extern char __dtb_##fdt_name##_start[]; \ - \ - IMD_USED(phyflex_mx6_memsize_##memory_size); \ - \ - start_imx6_phytec_common(memory_size, do_early_uart_config, \ - __dtb_##fdt_name##_start); \ - } - -PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true); -PHYTEC_ENTRY(start_phytec_pbab01_1gib_1bank, imx6q_phytec_pbab01, SZ_1G, true); -PHYTEC_ENTRY(start_phytec_pbab01_2gib, imx6q_phytec_pbab01, SZ_2G, true); -PHYTEC_ENTRY(start_phytec_pbab01_4gib, imx6q_phytec_pbab01, SZ_4G, true); -PHYTEC_ENTRY(start_phytec_pbab01dl_1gib, imx6dl_phytec_pbab01, SZ_1G, false); -PHYTEC_ENTRY(start_phytec_pbab01s_512mb, imx6s_phytec_pbab01, SZ_512M, false); -PHYTEC_ENTRY(start_phytec_phyboard_alcor_1gib, imx6q_phytec_phyboard_alcor, SZ_1G, false); -PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb, imx6dl_phytec_phyboard_subra, SZ_512M, false); diff --git a/arch/arm/boards/phytec-som-imx6/Makefile b/arch/arm/boards/phytec-som-imx6/Makefile new file mode 100644 index 0000000..c61e9cd --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/Makefile @@ -0,0 +1,4 @@ +obj-y += board.o +lwl-y += lowlevel.o +bbenv-y += defaultenv-physom-imx6 +bbenv-y += defaultenv-physom-imx6-mira diff --git a/arch/arm/boards/phytec-som-imx6/board.c b/arch/arm/boards/phytec-som-imx6/board.c new file mode 100644 index 0000000..9aefa55 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/board.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2013 Sascha Hauer, Pengutronix + * Copyright (C) 2015 PHYTEC Messtechnik GmbH, + * Author: Stefan Christ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation. + * + */ +#define pr_fmt(fmt) "phySOM-i.MX6: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#define PHYFLEX_MODULE_REV_1 0x1 +#define PHYFLEX_MODULE_REV_2 0x2 + +#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \ + MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS + +#define MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD (_MX6Q_PAD_SD4_DAT3__GPIO_2_11 | MUX_PAD_CTRL(GPIO_2_11_PD_CTL)) +#define MX6DL_PAD_SD4_DAT3__GPIO_2_11 IOMUX_PAD(0x0734, 0x034C, 5, 0x0000, 0, GPIO_2_11_PD_CTL) + +#define MX6_PHYFLEX_ERR006282 IMX_GPIO_NR(2, 11) + +static void phyflex_err006282_workaround(void) +{ + /* + * Boards beginning with 1362.2 have the SD4_DAT3 pin connected + * to the CMIC. If this pin isn't toggled within 10s the boards + * reset. The pin is unconnected on older boards, so we do not + * need a check for older boards before applying this fixup. + */ + + gpio_direction_output(MX6_PHYFLEX_ERR006282, 0); + mdelay(2); + gpio_direction_output(MX6_PHYFLEX_ERR006282, 1); + mdelay(2); + gpio_set_value(MX6_PHYFLEX_ERR006282, 0); + + if (cpu_is_mx6q()) + mxc_iomux_v3_setup_pad(MX6Q_PAD_SD4_DAT3__GPIO_2_11_PD); + else if (cpu_is_mx6dl()) + mxc_iomux_v3_setup_pad(MX6DL_PAD_SD4_DAT3__GPIO_2_11); + + gpio_direction_input(MX6_PHYFLEX_ERR006282); +} + +static unsigned int pfla02_module_revision; + +static unsigned int get_module_rev(void) +{ + unsigned int val = 0; + + val = gpio_get_value(IMX_GPIO_NR(2, 12)); + val |= (gpio_get_value(IMX_GPIO_NR(2, 13)) << 1); + val |= (gpio_get_value(IMX_GPIO_NR(2, 14)) << 2); + val |= (gpio_get_value(IMX_GPIO_NR(2, 15)) << 3); + + return 16 - val; +} + +static int physom_imx6_devices_init(void) +{ + int ret; + char *environment_path, *default_environment_path; + char *envdev, *default_envdev; + + if (of_machine_is_compatible("phytec,imx6q-pfla02") + || of_machine_is_compatible("phytec,imx6dl-pfla02") + || of_machine_is_compatible("phytec,imx6s-pfla02")) { + + phyflex_err006282_workaround(); + + pfla02_module_revision = get_module_rev(); + globalvar_add_simple_int("board.revision", &pfla02_module_revision, "%u"); + pr_info("Module Revision: %u\n", pfla02_module_revision); + + barebox_set_hostname("phyFLEX-i.MX6"); + default_environment_path = "/chosen/environment-spinor"; + default_envdev = "SPI NOR flash"; + + } else if (of_machine_is_compatible("phytec,imx6q-pcaaxl3")) { + + barebox_set_hostname("phyCARD-i.MX6"); + default_environment_path = "/chosen/environment-nand"; + default_envdev = "NAND flash"; + + } else if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") + || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") + || of_machine_is_compatible("phytec,imx6dl-pcm058-nand")) { + + barebox_set_hostname("phyCORE-i.MX6"); + default_environment_path = "/chosen/environment-spinor"; + default_envdev = "SPI NOR flash"; + + } else + return 0; + + switch (bootsource_get()) { + case BOOTSOURCE_MMC: + environment_path = asprintf("/chosen/environment-sd%d", + bootsource_get_instance() + 1); + envdev = "MMC"; + break; + case BOOTSOURCE_NAND: + environment_path = asprintf("/chosen/environment-nand"); + envdev = "NAND flash"; + break; + case BOOTSOURCE_SPI: + environment_path = asprintf("/chosen/environment-spinor"); + envdev = "SPI NOR flash"; + break; + default: + environment_path = asprintf(default_environment_path); + envdev = default_envdev; + break; + } + + if (environment_path) { + ret = of_device_enable_path(environment_path); + if (ret < 0) + pr_warn("Failed to enable environment partition '%s' (%d)\n", + environment_path, ret); + free(environment_path); + } + + pr_notice("Using environment in %s\n", envdev); + + imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); + + defaultenv_append_directory(defaultenv_physom_imx6); + + /* Overwrite file /env/init/automount */ + if (of_machine_is_compatible("phytec,imx6q-pcm058-nand") + || of_machine_is_compatible("phytec,imx6q-pcm058-emmc") + || of_machine_is_compatible("phytec,imx6dl-pcm058-nand")) { + defaultenv_append_directory(defaultenv_physom_imx6_mira); + } + + return 0; +} +device_initcall(physom_imx6_devices_init); diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-mira/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-mira/init/automount new file mode 100644 index 0000000..3659cf7 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6-mira/init/automount @@ -0,0 +1,14 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mmc0.probe=1 && [ -e /dev/mmc0.0 ] && mount /dev/mmc0.0 /mnt/mmc' diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc new file mode 100644 index 0000000..332fc26 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/mmc @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/mnt/mmc/linuximage" +global.bootm.oftree="/mnt/mmc/oftree" +global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootwait rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand new file mode 100644 index 0000000..a23aa21 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/nand @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/dev/nand0.kernel.bb" +global.bootm.oftree="/dev/nand0.oftree.bb" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi new file mode 100644 index 0000000..2000a16 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/boot/spi @@ -0,0 +1,5 @@ +#!/bin/sh + +global.bootm.image="/dev/m25p0.kernel" +global.bootm.oftree="/dev/m25p0.oftree" +global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw" diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount new file mode 100644 index 0000000..49d99bd --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/automount @@ -0,0 +1,14 @@ +#!/bin/sh + +if [ "$1" = menu ]; then + init-menu-add-entry "$0" "Automountpoints" + exit +fi + +# automount tftp server based on $eth0.serverip + +mkdir -p /mnt/tftp +automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp' + +mkdir -p /mnt/mmc +automount -d /mnt/mmc 'mmc2.probe=1 && [ -e /dev/mmc2.0 ] && mount /dev/mmc2.0 /mnt/mmc' diff --git a/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource new file mode 100644 index 0000000..3f2ff4b --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6/init/bootsource @@ -0,0 +1,15 @@ +#!/bin/sh + +if [ -n "$nv.boot.default" ]; then + exit +fi + +if [ $bootsource = mmc ]; then + global.boot.default="mmc nand spi net" +elif [ $bootsource = nand ]; then + global.boot.default="nand spi mmc net" +elif [ $bootsource = spi ]; then + global.boot.default="spi nand mmc net" +elif [ $bootsource = net ]; then + global.boot.default="net nand spi mmc" +fi diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg new file mode 100644 index 0000000..62a24ed --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg @@ -0,0 +1,9 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x54597955; \ + +#define SETUP_MDOR_MDASP_MDCTL \ + wm 32 0x021b0030 0x00591023; \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831a0000 + +#include "flash-header-phytec-pcaaxl3.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg new file mode 100644 index 0000000..bab726d --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg @@ -0,0 +1,9 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x3a3f7975; \ + +#define SETUP_MDOR_MDASP_MDCTL \ + wm 32 0x021b0030 0x003f1023; \ + wm 32 0x021b0040 0x00000017; \ + wm 32 0x021b0000 0xc21a0000 + +#include "flash-header-phytec-pcaaxl3.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg new file mode 100644 index 0000000..512f6cb --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg @@ -0,0 +1,9 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x54597955; \ + +#define SETUP_MDOR_MDASP_MDCTL \ + wm 32 0x021b0030 0x00591023; \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0xc31a0000 + +#include "flash-header-phytec-pcaaxl3.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h new file mode 100644 index 0000000..ebcc1dd --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcaaxl3.h @@ -0,0 +1,98 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e05a8 0x00000028 +wm 32 0x020e05b0 0x00000028 +wm 32 0x020e0524 0x00000028 +wm 32 0x020e051c 0x00000028 +wm 32 0x020e0518 0x00000028 +wm 32 0x020e050c 0x00000028 +wm 32 0x020e05b8 0x00000028 +wm 32 0x020e05c0 0x00000028 +wm 32 0x020e05ac 0x00000028 +wm 32 0x020e05b4 0x00000028 +wm 32 0x020e0528 0x00000028 +wm 32 0x020e0520 0x00000028 +wm 32 0x020e0514 0x00000028 +wm 32 0x020e0510 0x00000028 +wm 32 0x020e05bc 0x00000028 +wm 32 0x020e05c4 0x00000028 +wm 32 0x020e056c 0x00000028 +wm 32 0x020e0578 0x00000028 +wm 32 0x020e0588 0x00000028 +wm 32 0x020e0594 0x00000028 +wm 32 0x020e057c 0x00000028 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000028 +wm 32 0x020e05a0 0x00000028 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e0788 0x00000028 +wm 32 0x020e0794 0x00000028 +wm 32 0x020e079c 0x00000028 +wm 32 0x020e07a0 0x00000028 +wm 32 0x020e07a4 0x00000028 +wm 32 0x020e07a8 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e074c 0x00000028 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e078c 0x00000028 +wm 32 0x020e0798 0x000c0000 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b0018 0x00091740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b0010 0xff328f64 +wm 32 0x021b0014 0x01ff00db +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0008 0x09444040 +wm 32 0x021b0004 0x00025576 + +SETUP_MDCFG0 +SETUP_MDOR_MDASP_MDCTL + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00048039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b083c 0x4350035e +wm 32 0x021b0840 0x035c0358 +wm 32 0x021b483c 0x436e0376 +wm 32 0x021b4840 0x03770352 +wm 32 0x021b0848 0x3c333436 +wm 32 0x021b4848 0x35332f3b +wm 32 0x021b0850 0x37363e39 +wm 32 0x021b4850 0x432f433d +wm 32 0x021b080c 0x0013001b +wm 32 0x021b0810 0x003b0034 +wm 32 0x021b480c 0x0037004b +wm 32 0x021b4810 0x004b0055 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b001c 0x00000000 +wm 32 0x021b0404 0x00011006 +wm 32 0x020e0010 0xf00000ff +wm 32 0x020e0018 0x007f007f +wm 32 0x020e001c 0x007f007f +wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg new file mode 100644 index 0000000..5df46b9 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x555A7955 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831A0000 + +#include "flash-header-phytec-pcm058.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h new file mode 100644 index 0000000..7cdf45c --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058.h @@ -0,0 +1,102 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e0798 0x000C0000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00000028 +wm 32 0x020e05b0 0x00000028 +wm 32 0x020e0524 0x00000028 +wm 32 0x020e051c 0x00000028 +wm 32 0x020e0518 0x00000028 +wm 32 0x020e050c 0x00000028 +wm 32 0x020e05b8 0x00000028 +wm 32 0x020e05c0 0x00000028 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e0788 0x00000028 +wm 32 0x020e0794 0x00000028 +wm 32 0x020e079c 0x00000028 +wm 32 0x020e07a0 0x00000028 +wm 32 0x020e07a4 0x00000028 +wm 32 0x020e07a8 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e05ac 0x00000028 +wm 32 0x020e05b4 0x00000028 +wm 32 0x020e0528 0x00000028 +wm 32 0x020e0520 0x00000028 +wm 32 0x020e0514 0x00000028 +wm 32 0x020e0510 0x00000028 +wm 32 0x020e05bc 0x00000028 +wm 32 0x020e05c4 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x00140014 +wm 32 0x021b0810 0x00230018 +wm 32 0x021b480c 0x000A001E +wm 32 0x021b4810 0x000A0015 +wm 32 0x021b083c 0x43080314 +wm 32 0x021b0840 0x02680300 +wm 32 0x021b483c 0x430C0318 +wm 32 0x021b4840 0x03000254 +wm 32 0x021b0848 0x3A323234 +wm 32 0x021b4848 0x3E3C3242 +wm 32 0x021b0850 0x2A2E3632 +wm 32 0x021b4850 0x3C323E34 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00020036 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xFF328F64 +wm 32 0x021b0014 0x01FF00DB +wm 32 0x021b0018 0x00011740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x003F1023 + +SETUP_MDASP_MDCTL + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00048039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 +wm 32 0x020e0010 0xf00000ff +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F +wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg new file mode 100644 index 0000000..bf50190 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x3c409b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x0000000F; \ + wm 32 0x021b0000 0x82190000 + +#include "flash-header-phytec-pcm058dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h new file mode 100644 index 0000000..c7df790 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcm058dl.h @@ -0,0 +1,98 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e0774 0x000C0000 +wm 32 0x020e0754 0x00000000 +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0494 0x00000030 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00000030 +wm 32 0x020e04b8 0x00000030 +wm 32 0x020e04a4 0x00003000 +wm 32 0x020e04a8 0x00003000 +wm 32 0x020e076c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e04bc 0x00000028 +wm 32 0x020e04c0 0x00000028 +wm 32 0x020e04c4 0x00000028 +wm 32 0x020e04c8 0x00000028 +wm 32 0x020e04cc 0x00000028 +wm 32 0x020e04d0 0x00000028 +wm 32 0x020e04d4 0x00000028 +wm 32 0x020e04d8 0x00000028 +wm 32 0x020e0760 0x00020000 +wm 32 0x020e0764 0x00000028 +wm 32 0x020e0770 0x00000028 +wm 32 0x020e0778 0x00000028 +wm 32 0x020e077c 0x00000028 +wm 32 0x020e0780 0x00000028 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e078c 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e0470 0x00000028 +wm 32 0x020e0474 0x00000028 +wm 32 0x020e0478 0x00000028 +wm 32 0x020e047c 0x00000028 +wm 32 0x020e0480 0x00000028 +wm 32 0x020e0484 0x00000028 +wm 32 0x020e0488 0x00000028 +wm 32 0x020e048c 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x0032003A +wm 32 0x021b0810 0x00350037 +wm 32 0x021b480c 0x00260038 +wm 32 0x021b4810 0x002C0038 +wm 32 0x021b083c 0x42630244 +wm 32 0x021b0840 0x02300238 +wm 32 0x021b483c 0x02540258 +wm 32 0x021b4840 0x0236021e +wm 32 0x021b0848 0x46484446 +wm 32 0x021b4848 0x302d2c35 +wm 32 0x021b0850 0x36342630 +wm 32 0x021b4850 0x3423372d +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xff538f64 +wm 32 0x021b0014 0x01ff0124 +wm 32 0x021b0018 0x00091740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x003F1023 + +SETUP_MDASP_MDCTL + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00428031 +wm 32 0x021b001c 0x00428039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg new file mode 100644 index 0000000..75dc982 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x565c9b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831a0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg new file mode 100644 index 0000000..1f1fbe5 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x3c409b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000017; \ + wm 32 0x021b0000 0xc21a0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg new file mode 100644 index 0000000..aa01c05 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x565c9b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0xC31A0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg new file mode 100644 index 0000000..c8d33cf --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x8c929b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000047; \ + wm 32 0x021b0000 0xC41A0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg new file mode 100644 index 0000000..d6bbe1f --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x555a7975 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000017; \ + wm 32 0x021b0000 0x821a0000 + +#include "flash-header-phytec-pfla02.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h new file mode 100644 index 0000000..507b9c6 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02.h @@ -0,0 +1,102 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e0798 0x000C0000 +wm 32 0x020e0758 0x00000000 +wm 32 0x020e0588 0x00000030 +wm 32 0x020e0594 0x00000030 +wm 32 0x020e056c 0x00000030 +wm 32 0x020e0578 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e057c 0x00000030 +wm 32 0x020e058c 0x00000000 +wm 32 0x020e059c 0x00000030 +wm 32 0x020e05a0 0x00000030 +wm 32 0x020e0590 0x00003000 +wm 32 0x020e0598 0x00003000 +wm 32 0x020e078c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e05a8 0x00000028 +wm 32 0x020e05b0 0x00000028 +wm 32 0x020e0524 0x00000028 +wm 32 0x020e051c 0x00000028 +wm 32 0x020e0518 0x00000028 +wm 32 0x020e050c 0x00000028 +wm 32 0x020e05b8 0x00000028 +wm 32 0x020e05c0 0x00000028 +wm 32 0x020e0774 0x00020000 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e0788 0x00000028 +wm 32 0x020e0794 0x00000028 +wm 32 0x020e079c 0x00000028 +wm 32 0x020e07a0 0x00000028 +wm 32 0x020e07a4 0x00000028 +wm 32 0x020e07a8 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e05ac 0x00000028 +wm 32 0x020e05b4 0x00000028 +wm 32 0x020e0528 0x00000028 +wm 32 0x020e0520 0x00000028 +wm 32 0x020e0514 0x00000028 +wm 32 0x020e0510 0x00000028 +wm 32 0x020e05bc 0x00000028 +wm 32 0x020e05c4 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x00110011 +wm 32 0x021b0810 0x00240024 +wm 32 0x021b480c 0x00260038 +wm 32 0x021b4810 0x002C0038 +wm 32 0x021b083c 0x03400350 +wm 32 0x021b0840 0x03440340 +wm 32 0x021b483c 0x034C0354 +wm 32 0x021b4840 0x035C033C +wm 32 0x021b0848 0x322A2A2A +wm 32 0x021b4848 0x302C2834 +wm 32 0x021b0850 0x34303834 +wm 32 0x021b4850 0x422A3E36 +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xff538f64 +wm 32 0x021b0014 0x01ff0124 +wm 32 0x021b0018 0x00091740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x003F1023 + +SETUP_MDASP_MDCTL + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00048031 +wm 32 0x021b001c 0x00048039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 +wm 32 0x020e0010 0xf00000ff +wm 32 0x020e0018 0x007F007F +wm 32 0x020e001c 0x007F007F +wm 32 0x020c8000 0x80002021 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg new file mode 100644 index 0000000..156eea9 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x565c9b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000027; \ + wm 32 0x021b0000 0x831a0000 + +#include "flash-header-phytec-pfla02dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg new file mode 100644 index 0000000..e768670 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x8c929b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000017; \ + wm 32 0x021b0000 0xc21a0000 + +#include "flash-header-phytec-pfla02dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h new file mode 100644 index 0000000..6cdf429 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02dl.h @@ -0,0 +1,98 @@ +soc imx6 +loadaddr 0x10000000 +dcdofs 0x400 + +wm 32 0x020e0774 0x000C0000 +wm 32 0x020e0754 0x00000000 +wm 32 0x020e04ac 0x00000030 +wm 32 0x020e04b0 0x00000030 +wm 32 0x020e0464 0x00000030 +wm 32 0x020e0490 0x00000030 +wm 32 0x020e074c 0x00000030 +wm 32 0x020e0494 0x00000030 +wm 32 0x020e04a0 0x00000000 +wm 32 0x020e04b4 0x00000030 +wm 32 0x020e04b8 0x00000030 +wm 32 0x020e04a4 0x00003000 +wm 32 0x020e04a8 0x00003000 +wm 32 0x020e076c 0x00000030 +wm 32 0x020e0750 0x00020000 +wm 32 0x020e04bc 0x00000028 +wm 32 0x020e04c0 0x00000028 +wm 32 0x020e04c4 0x00000028 +wm 32 0x020e04c8 0x00000028 +wm 32 0x020e04cc 0x00000028 +wm 32 0x020e04d0 0x00000028 +wm 32 0x020e04d4 0x00000028 +wm 32 0x020e04d8 0x00000028 +wm 32 0x020e0760 0x00020000 +wm 32 0x020e0764 0x00000028 +wm 32 0x020e0770 0x00000028 +wm 32 0x020e0778 0x00000028 +wm 32 0x020e077c 0x00000028 +wm 32 0x020e0780 0x00000028 +wm 32 0x020e0784 0x00000028 +wm 32 0x020e078c 0x00000028 +wm 32 0x020e0748 0x00000028 +wm 32 0x020e0470 0x00000028 +wm 32 0x020e0474 0x00000028 +wm 32 0x020e0478 0x00000028 +wm 32 0x020e047c 0x00000028 +wm 32 0x020e0480 0x00000028 +wm 32 0x020e0484 0x00000028 +wm 32 0x020e0488 0x00000028 +wm 32 0x020e048c 0x00000028 +wm 32 0x021b0800 0xa1390003 +wm 32 0x021b4800 0xa1380003 +wm 32 0x021b080c 0x00110011 +wm 32 0x021b0810 0x00240024 +wm 32 0x021b480c 0x00260038 +wm 32 0x021b4810 0x002C0038 +wm 32 0x021b083c 0x02480248 +wm 32 0x021b0840 0x022f022d +wm 32 0x021b483c 0x02540258 +wm 32 0x021b4840 0x0236021e +wm 32 0x021b0848 0x332f3033 +wm 32 0x021b4848 0x302d2c35 +wm 32 0x021b0850 0x3030362a +wm 32 0x021b4850 0x3423372d +wm 32 0x021b081c 0x33333333 +wm 32 0x021b0820 0x33333333 +wm 32 0x021b0824 0x33333333 +wm 32 0x021b0828 0x33333333 +wm 32 0x021b481c 0x33333333 +wm 32 0x021b4820 0x33333333 +wm 32 0x021b4824 0x33333333 +wm 32 0x021b4828 0x33333333 +wm 32 0x021b08b8 0x00000800 +wm 32 0x021b48b8 0x00000800 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0008 0x09444040 + +SETUP_MDCFG0 + +wm 32 0x021b0010 0xff538f64 +wm 32 0x021b0014 0x01ff0124 +wm 32 0x021b0018 0x00091740 +wm 32 0x021b001c 0x00008000 +wm 32 0x021b002c 0x000026d2 +wm 32 0x021b0030 0x003F1023 + +SETUP_MDASP_MDCTL + +wm 32 0x021b001c 0x04088032 +wm 32 0x021b001c 0x0408803a +wm 32 0x021b001c 0x00008033 +wm 32 0x021b001c 0x0000803b +wm 32 0x021b001c 0x00428031 +wm 32 0x021b001c 0x00428039 +wm 32 0x021b001c 0x09408030 +wm 32 0x021b001c 0x09408038 +wm 32 0x021b001c 0x04008040 +wm 32 0x021b001c 0x04008048 +wm 32 0x021b0020 0x00007800 +wm 32 0x021b0818 0x00011117 +wm 32 0x021b4818 0x00011117 +wm 32 0x021b0004 0x00025576 +wm 32 0x021b0404 0x00011006 +wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg new file mode 100644 index 0000000..26fe2b2 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x3c409b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x0000000B; \ + wm 32 0x021b0000 0x82180000 + +#include "flash-header-phytec-pfla02dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg new file mode 100644 index 0000000..babb0df --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x3c409b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x0000000F; \ + wm 32 0x021b0000 0x82190000 + +#include "flash-header-phytec-pfla02dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg new file mode 100644 index 0000000..6a46cd9 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg @@ -0,0 +1,8 @@ +#define SETUP_MDCFG0 \ + wm 32 0x021b000c 0x565c9b85 + +#define SETUP_MDASP_MDCTL \ + wm 32 0x021b0040 0x00000017; \ + wm 32 0x021b0000 0x83190000 + +#include "flash-header-phytec-pfla02dl.h" diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c new file mode 100644 index 0000000..eb796e7 --- /dev/null +++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Sascha Hauer + * Copyright (C) 2015 PHYTEC Messtechnik GmbH, + * Author: Stefan Christ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static inline void setup_uart(void) +{ + void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR; + + writel(0x4, iomuxbase + 0x01f8); + + imx6_ungate_all_peripherals(); + imx6_uart_setup_ll(); + + putc_ll('>'); +} + +#define SZ_4G 0xEFFFFFF8 + +BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_128M, IMD_TYPE_PARAMETER, "memsize=128", 0); +BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_256M, IMD_TYPE_PARAMETER, "memsize=256", 0); +BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_512M, IMD_TYPE_PARAMETER, "memsize=512", 0); +BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_1G, IMD_TYPE_PARAMETER, "memsize=1024", 0); +BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_2G, IMD_TYPE_PARAMETER, "memsize=2048", 0); +BAREBOX_IMD_TAG_STRING(physom_mx6_memsize_SZ_4G, IMD_TYPE_PARAMETER, "memsize=4096", 0); + +static void __noreturn start_imx6_phytec_common(uint32_t size, + bool do_early_uart_config, + void *fdt_blob_fixed_offset) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + arm_setup_stack(0x00920000 - 8); + + if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL)) + setup_uart(); + + fdt = fdt_blob_fixed_offset - get_runtime_offset(); + barebox_arm_entry(0x10000000, size, fdt); +} + +#define PHYTEC_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \ + ENTRY_FUNCTION(name, r0, r1, r2) \ + { \ + extern char __dtb_##fdt_name##_start[]; \ + \ + IMD_USED(physom_mx6_memsize_##memory_size); \ + \ + start_imx6_phytec_common(memory_size, do_early_uart_config, \ + __dtb_##fdt_name##_start); \ + } + +PHYTEC_ENTRY(start_phytec_pbaa03_1gib, imx6q_phytec_pbaa03, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_pbaa03_1gib_1bank, imx6q_phytec_pbaa03, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_pbaa03_2gib, imx6q_phytec_pbaa03, SZ_2G, true); + +PHYTEC_ENTRY(start_phytec_pbab01_512mb_1bank, imx6q_phytec_pbab01, SZ_512M, true); +PHYTEC_ENTRY(start_phytec_pbab01_1gib, imx6q_phytec_pbab01, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_pbab01_1gib_1bank, imx6q_phytec_pbab01, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_pbab01_2gib, imx6q_phytec_pbab01, SZ_2G, true); +PHYTEC_ENTRY(start_phytec_pbab01_4gib, imx6q_phytec_pbab01, SZ_4G, true); +PHYTEC_ENTRY(start_phytec_pbab01dl_1gib, imx6dl_phytec_pbab01, SZ_1G, false); +PHYTEC_ENTRY(start_phytec_pbab01dl_1gib_1bank, imx6dl_phytec_pbab01, SZ_1G, false); +PHYTEC_ENTRY(start_phytec_pbab01s_128mb_1bank, imx6s_phytec_pbab01, SZ_128M, false); +PHYTEC_ENTRY(start_phytec_pbab01s_256mb_1bank, imx6s_phytec_pbab01, SZ_256M, false); +PHYTEC_ENTRY(start_phytec_pbab01s_512mb_1bank, imx6s_phytec_pbab01, SZ_512M, false); +PHYTEC_ENTRY(start_phytec_phyboard_alcor_1gib, imx6q_phytec_phyboard_alcor, SZ_1G, false); +PHYTEC_ENTRY(start_phytec_phyboard_subra_512mb_1bank, imx6dl_phytec_phyboard_subra, SZ_512M, false); + +PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_nand_256mb, imx6dl_phytec_phycore_som_nand, SZ_256M, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true); +PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true); diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg new file mode 100644 index 0000000..6902fe1 --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/1066mhz-4x128mx16.imxcfg @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00000000 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00000000 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00000000 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00000000 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x0314031c +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x023e0304 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x03240330 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03180260 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x3630323c +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x3436283a +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x36344038 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x422a423c +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x54597955 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDMISC 0x00011740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005B0E21 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MAARCR 0x11420000 +wm 32 MX6_MMDC_P0_MDCTL 0x831A0000 +wm 32 MX6_MMDC_P0_MDSCR 0x02088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0208803A +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803B +wm 32 MX6_MMDC_P0_MDSCR 0x00408031 +wm 32 MX6_MMDC_P0_MDSCR 0x00408039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg new file mode 100644 index 0000000..ac336e5 --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/1066mhz-4x256mx16.imxcfg @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x00000000 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x00000000 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x00000000 +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00000000 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x0314031c +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x023e0304 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x03240330 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x03180260 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x3630323c +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x3436283a +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x36344038 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x422a423c +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x00025576 +wm 32 MX6_MMDC_P0_MDOTC 0x09444040 +wm 32 MX6_MMDC_P0_MDCFG0 0x898E7975 +wm 32 MX6_MMDC_P0_MDCFG1 0xFF328F64 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDMISC 0x00011740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x005B0E21 +wm 32 MX6_MMDC_P0_MDASP 0x00000047 +wm 32 MX6_MMDC_P0_MAARCR 0x11420000 +wm 32 MX6_MMDC_P0_MDCTL 0x841A0000 +wm 32 MX6_MMDC_P0_MDSCR 0x02088032 +wm 32 MX6_MMDC_P0_MDSCR 0x0208803A +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x0000803B +wm 32 MX6_MMDC_P0_MDSCR 0x00408031 +wm 32 MX6_MMDC_P0_MDSCR 0x00408039 +wm 32 MX6_MMDC_P0_MDSCR 0x09408030 +wm 32 MX6_MMDC_P0_MDSCR 0x09408038 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDSCR 0x04008048 +wm 32 MX6_MMDC_P0_MDREF 0x00005800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 diff --git a/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg b/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg new file mode 100644 index 0000000..c8e5a0c --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/1066mhz-64b.imxcfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000C0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00020030 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00020030 +wm 32 MX6_IOM_DRAM_CAS 0x00020030 +wm 32 MX6_IOM_DRAM_RAS 0x00020030 +wm 32 MX6_IOM_GRP_ADDDS 0x00000030 +wm 32 MX6_IOM_DRAM_RESET 0x00020030 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00003030 +wm 32 MX6_IOM_DRAM_SDODT1 0x00003030 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000030 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000030 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000030 +wm 32 MX6_IOM_GRP_B1DS 0x00000030 +wm 32 MX6_IOM_GRP_B2DS 0x00000030 +wm 32 MX6_IOM_GRP_B3DS 0x00000030 +wm 32 MX6_IOM_GRP_B4DS 0x00000030 +wm 32 MX6_IOM_GRP_B5DS 0x00000030 +wm 32 MX6_IOM_GRP_B6DS 0x00000030 +wm 32 MX6_IOM_GRP_B7DS 0x00000030 +wm 32 MX6_IOM_DRAM_DQM0 0x00020030 +wm 32 MX6_IOM_DRAM_DQM1 0x00020030 +wm 32 MX6_IOM_DRAM_DQM2 0x00020030 +wm 32 MX6_IOM_DRAM_DQM3 0x00020030 +wm 32 MX6_IOM_DRAM_DQM4 0x00020030 +wm 32 MX6_IOM_DRAM_DQM5 0x00020030 +wm 32 MX6_IOM_DRAM_DQM6 0x00020030 +wm 32 MX6_IOM_DRAM_DQM7 0x00020030 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg new file mode 100644 index 0000000..affb011 --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/800mhz-2x128mx16.imxcfg @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P1_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x005a0057 +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x004a0052 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x02480240 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x02340230 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x40404440 +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x38343034 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x0002002d +wm 32 MX6_MMDC_P0_MDOTC 0x00333040 +wm 32 MX6_MMDC_P0_MDCFG0 0x3f435313 +wm 32 MX6_MMDC_P0_MDCFG1 0xb66e8b63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01ff00db +wm 32 MX6_MMDC_P0_MDMISC 0x00011740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x00431023 +wm 32 MX6_MMDC_P0_MDASP 0x00000017 +wm 32 MX6_MMDC_P0_MAARCR 0x11420000 +wm 32 MX6_MMDC_P0_MDCTL 0x83190000 +wm 32 MX6_MMDC_P0_MDSCR 0x00008032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x00008031 +wm 32 MX6_MMDC_P0_MDSCR 0x05208030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P0_MDPDC 0x0002556d +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg new file mode 100644 index 0000000..91322f4 --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/800mhz-32b.imxcfg @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000028 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000028 +wm 32 MX6_IOM_DRAM_CAS 0x00000010 +wm 32 MX6_IOM_DRAM_RAS 0x00000010 +wm 32 MX6_IOM_GRP_ADDDS 0x00000010 +wm 32 MX6_IOM_DRAM_RESET 0x00000010 +wm 32 MX6_IOM_DRAM_SDCKE0 0x00003000 +wm 32 MX6_IOM_DRAM_SDCKE1 0x00003000 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000010 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000010 +wm 32 MX6_IOM_GRP_CTLDS 0x00000010 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000000 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000000 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000000 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000000 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000000 +wm 32 MX6_IOM_GRP_B5DS 0x00000000 +wm 32 MX6_IOM_GRP_B6DS 0x00000000 +wm 32 MX6_IOM_GRP_B7DS 0x00000000 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000000 +wm 32 MX6_IOM_DRAM_DQM5 0x00000000 +wm 32 MX6_IOM_DRAM_DQM6 0x00000000 +wm 32 MX6_IOM_DRAM_DQM7 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg new file mode 100644 index 0000000..384e6fd --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/800mhz-4x128mx16.imxcfg @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +wm 32 MX6_MMDC_P0_MPZQHWCTRL 0xa1390003 +wm 32 MX6_MMDC_P0_MPWLDECTRL0 0x0045004D +wm 32 MX6_MMDC_P0_MPWLDECTRL1 0x003A0047 +wm 32 MX6_MMDC_P1_MPWLDECTRL0 0x001F001F +wm 32 MX6_MMDC_P1_MPWLDECTRL1 0x00210035 +wm 32 MX6_MMDC_P0_MPDGCTRL0 0x023C0224 +wm 32 MX6_MMDC_P0_MPDGCTRL1 0x02000220 +wm 32 MX6_MMDC_P1_MPDGCTRL0 0x02200220 +wm 32 MX6_MMDC_P1_MPDGCTRL1 0x02040208 +wm 32 MX6_MMDC_P0_MPRDDLCTL 0x44444846 +wm 32 MX6_MMDC_P1_MPRDDLCTL 0x4042463C +wm 32 MX6_MMDC_P0_MPWRDLCTL 0x32343032 +wm 32 MX6_MMDC_P1_MPWRDLCTL 0x36363430 +wm 32 MX6_MMDC_P0_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY0DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY1DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY2DL 0x33333333 +wm 32 MX6_MMDC_P1_MPRDDQBY3DL 0x33333333 +wm 32 MX6_MMDC_P0_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P1_MPMUR0 0x00000800 +wm 32 MX6_MMDC_P0_MDPDC 0x0002002d +wm 32 MX6_MMDC_P0_MDOTC 0x00333040 +wm 32 MX6_MMDC_P0_MDCFG0 0x3F4352F3 +wm 32 MX6_MMDC_P0_MDCFG1 0xB66D8B63 +wm 32 MX6_MMDC_P0_MDCFG2 0x01FF00DB +wm 32 MX6_MMDC_P0_MDMISC 0x00011740 +wm 32 MX6_MMDC_P0_MDSCR 0x00008000 +wm 32 MX6_MMDC_P0_MDRWD 0x000026d2 +wm 32 MX6_MMDC_P0_MDOR 0x00431023 +wm 32 MX6_MMDC_P0_MDASP 0x00000027 +wm 32 MX6_MMDC_P0_MDCTL 0x831A0000 +wm 32 MX6_MMDC_P0_MDSCR 0x02008032 +wm 32 MX6_MMDC_P0_MDSCR 0x00008033 +wm 32 MX6_MMDC_P0_MDSCR 0x04008031 +wm 32 MX6_MMDC_P0_MDSCR 0x05208030 +wm 32 MX6_MMDC_P0_MDSCR 0x04008040 +wm 32 MX6_MMDC_P0_MDREF 0x00007800 +wm 32 MX6_MMDC_P0_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P1_MPODTCTRL 0x00000007 +wm 32 MX6_MMDC_P0_MDPDC 0x0002556d +wm 32 MX6_MMDC_P0_MAPSR 0x00011006 +wm 32 MX6_MMDC_P0_MDSCR 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg b/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg new file mode 100644 index 0000000..021b40b --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/800mhz-64b.imxcfg @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2013 Boundary Devices + * Copyright (C) 2013 SolidRun ltd. + * Copyright (C) 2013 Jon Nettleton + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +wm 32 MX6_IOM_GRP_DDR_TYPE 0x000c0000 +wm 32 MX6_IOM_GRP_DDRPKE 0x00000000 +wm 32 MX6_IOM_DRAM_SDCLK_0 0x00000028 +wm 32 MX6_IOM_DRAM_SDCLK_1 0x00000028 +wm 32 MX6_IOM_DRAM_CAS 0x00000028 +wm 32 MX6_IOM_DRAM_RAS 0x00000028 +wm 32 MX6_IOM_GRP_ADDDS 0x00000028 +wm 32 MX6_IOM_DRAM_RESET 0x00000028 +wm 32 MX6_IOM_DRAM_SDBA2 0x00000000 +wm 32 MX6_IOM_DRAM_SDODT0 0x00000028 +wm 32 MX6_IOM_DRAM_SDODT1 0x00000028 +wm 32 MX6_IOM_GRP_CTLDS 0x00000028 +wm 32 MX6_IOM_DDRMODE_CTL 0x00020000 +wm 32 MX6_IOM_DRAM_SDQS0 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS1 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS2 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS3 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS4 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS5 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS6 0x00000028 +wm 32 MX6_IOM_DRAM_SDQS7 0x00000028 +wm 32 MX6_IOM_GRP_DDRMODE 0x00020000 +wm 32 MX6_IOM_GRP_B0DS 0x00000028 +wm 32 MX6_IOM_GRP_B1DS 0x00000028 +wm 32 MX6_IOM_GRP_B2DS 0x00000028 +wm 32 MX6_IOM_GRP_B3DS 0x00000028 +wm 32 MX6_IOM_GRP_B4DS 0x00000028 +wm 32 MX6_IOM_GRP_B5DS 0x00000028 +wm 32 MX6_IOM_GRP_B6DS 0x00000028 +wm 32 MX6_IOM_GRP_B7DS 0x00000028 +wm 32 MX6_IOM_DRAM_DQM0 0x00000028 +wm 32 MX6_IOM_DRAM_DQM1 0x00000028 +wm 32 MX6_IOM_DRAM_DQM2 0x00000028 +wm 32 MX6_IOM_DRAM_DQM3 0x00000028 +wm 32 MX6_IOM_DRAM_DQM4 0x00000028 +wm 32 MX6_IOM_DRAM_DQM5 0x00000028 +wm 32 MX6_IOM_DRAM_DQM6 0x00000028 +wm 32 MX6_IOM_DRAM_DQM7 0x00000028 diff --git a/arch/arm/boards/solidrun-microsom/Makefile b/arch/arm/boards/solidrun-microsom/Makefile index 8b4754e..01c7a25 100644 --- a/arch/arm/boards/solidrun-microsom/Makefile +++ b/arch/arm/boards/solidrun-microsom/Makefile @@ -1,3 +1,2 @@ -obj-y += board.o flash-header-solidrun-hummingboard.dcd.o -extra-y += flash-header-solidrun-hummingboard.dcd.S flash-header-solidrun-hummingboard.dcd +obj-y += board.o lwl-y += lowlevel.o diff --git a/arch/arm/boards/solidrun-microsom/board.c b/arch/arm/boards/solidrun-microsom/board.c index c231c17..28a60b9 100644 --- a/arch/arm/boards/solidrun-microsom/board.c +++ b/arch/arm/boards/solidrun-microsom/board.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -61,12 +62,26 @@ return 0; } -static int hummingboard_device_init(void) +static void microsom_eth_init(void) { - if (!of_machine_is_compatible("solidrun,hummingboard/dl")) - return 0; + void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR; + u32 val; + + clk_set_rate(clk_lookup("enet_ref"), 25000000); + + val = readl(iomux + IOMUXC_GPR1); + val |= IMX6Q_GPR1_ENET_CLK_SEL_ANATOP; + writel(val, iomux + IOMUXC_GPR1); phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup); +} +static int hummingboard_device_init(void) +{ + if (!of_machine_is_compatible("solidrun,hummingboard/dl") && + !of_machine_is_compatible("solidrun,hummingboard/q")) + return 0; + + microsom_eth_init(); /* enable USB VBUS */ gpio_direction_output(IMX_GPIO_NR(3, 22), 1); @@ -80,7 +95,8 @@ static int hummingboard_late_init(void) { - if (!of_machine_is_compatible("solidrun,hummingboard/dl")) + if (!of_machine_is_compatible("solidrun,hummingboard/dl") && + !of_machine_is_compatible("solidrun,hummingboard/q")) return 0; imx6_bbu_internal_mmc_register_handler("sdcard", "/dev/mmc1.barebox", diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg new file mode 100644 index 0000000..eb7bc84 --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i1.imxcfg @@ -0,0 +1,9 @@ +loadaddr 0x10000000 +soc imx6 +dcdofs 0x400 + +#include +#include + +#include "800mhz-32b.imxcfg" +#include "800mhz-2x128mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg new file mode 100644 index 0000000..8930012 --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2.imxcfg @@ -0,0 +1,9 @@ +loadaddr 0x10000000 +soc imx6 +dcdofs 0x400 + +#include +#include + +#include "800mhz-64b.imxcfg" +#include "800mhz-4x128mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg new file mode 100644 index 0000000..4eb937a --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i2eX.imxcfg @@ -0,0 +1,9 @@ +loadaddr 0x10000000 +soc imx6 +dcdofs 0x400 + +#include +#include + +#include "1066mhz-64b.imxcfg" +#include "1066mhz-4x128mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg new file mode 100644 index 0000000..438bd8e --- /dev/null +++ b/arch/arm/boards/solidrun-microsom/flash-header-microsom-i4.imxcfg @@ -0,0 +1,9 @@ +loadaddr 0x10000000 +soc imx6 +dcdofs 0x400 + +#include +#include + +#include "1066mhz-64b.imxcfg" +#include "1066mhz-4x256mx16.imxcfg" diff --git a/arch/arm/boards/solidrun-microsom/flash-header-solidrun-hummingboard.imxcfg b/arch/arm/boards/solidrun-microsom/flash-header-solidrun-hummingboard.imxcfg deleted file mode 100644 index b1856b4..0000000 --- a/arch/arm/boards/solidrun-microsom/flash-header-solidrun-hummingboard.imxcfg +++ /dev/null @@ -1,79 +0,0 @@ -loadaddr 0x10000000 -soc imx6 -dcdofs 0x400 -wm 32 0x020e0774 0x000c0000 -wm 32 0x020e0754 0x00000000 -wm 32 0x020e04ac 0x00000030 -wm 32 0x020e04b0 0x00000030 -wm 32 0x020e0464 0x00000030 -wm 32 0x020e0490 0x00000030 -wm 32 0x020e074c 0x00000030 -wm 32 0x020e0494 0x00000030 -wm 32 0x020e04a4 0x00003000 -wm 32 0x020e04a8 0x00003000 -wm 32 0x020e04a0 0x00000000 -wm 32 0x020e04b4 0x00003030 -wm 32 0x020e04b8 0x00003030 -wm 32 0x020e076c 0x00000030 -wm 32 0x020e0750 0x00000000 -wm 32 0x020e04bc 0x00000030 -wm 32 0x020e04c0 0x00000030 -wm 32 0x020e04c4 0x00000030 -wm 32 0x020e04c8 0x00000030 -wm 32 0x020e04cc 0x00000000 -wm 32 0x020e04d0 0x00000000 -wm 32 0x020e04d4 0x00000000 -wm 32 0x020e04d8 0x00000000 -wm 32 0x020e0760 0x00000000 -wm 32 0x020e0764 0x00000030 -wm 32 0x020e0770 0x00000030 -wm 32 0x020e0778 0x00000030 -wm 32 0x020e077c 0x00000030 -wm 32 0x020e0780 0x00000000 -wm 32 0x020e0784 0x00000000 -wm 32 0x020e078c 0x00000000 -wm 32 0x020e0748 0x00000000 -wm 32 0x020e0470 0x00000030 -wm 32 0x020e0474 0x00000030 -wm 32 0x020e0478 0x00000030 -wm 32 0x020e047c 0x00000030 -wm 32 0x020e0480 0x00000000 -wm 32 0x020e0484 0x00000000 -wm 32 0x020e0488 0x00000000 -wm 32 0x020e048c 0x00000000 -wm 32 0x021b0800 0xa1390003 -wm 32 0x021b4800 0xa1390003 -wm 32 0x021b080c 0x000F0011 -wm 32 0x021b0810 0x000E000F -wm 32 0x021b083c 0x42240229 -wm 32 0x021b0840 0x021a0219 -wm 32 0x021b0848 0x4e4f5150 -wm 32 0x021b0850 0x35363136 -wm 32 0x021b081c 0x33333333 -wm 32 0x021b0820 0x33333333 -wm 32 0x021b0824 0x33333333 -wm 32 0x021b0828 0x33333333 -wm 32 0x021b08b8 0x00000800 -wm 32 0x021b48b8 0x00000800 -wm 32 0x021b0004 0x0002002d -wm 32 0x021b0008 0x00333030 -wm 32 0x021b000c 0x40445323 -wm 32 0x021b0010 0xb68e8c63 -wm 32 0x021b0014 0x01ff00db -wm 32 0x021b0018 0x00001740 -wm 32 0x021b001c 0x00008000 -wm 32 0x021b002c 0x000026d2 -wm 32 0x021b0030 0x00440e21 -wm 32 0x021b0040 0x00000017 -wm 32 0x021b0400 0x11420000 -wm 32 0x021b0000 0x83190000 -wm 32 0x021b001c 0x04008032 -wm 32 0x021b001c 0x00008033 -wm 32 0x021b001c 0x00428031 -wm 32 0x021b001c 0x07208030 -wm 32 0x021b001c 0x04008040 -wm 32 0x021b0020 0x00005800 -wm 32 0x021b0818 0x00000007 -wm 32 0x021b0004 0x0002556d -wm 32 0x021b0404 0x00011006 -wm 32 0x021b001c 0x00000000 diff --git a/arch/arm/boards/solidrun-microsom/lowlevel.c b/arch/arm/boards/solidrun-microsom/lowlevel.c index 30f4a3f..54f1cdf 100644 --- a/arch/arm/boards/solidrun-microsom/lowlevel.c +++ b/arch/arm/boards/solidrun-microsom/lowlevel.c @@ -5,8 +5,9 @@ #include extern char __dtb_imx6dl_hummingboard_start[]; +extern char __dtb_imx6q_hummingboard_start[]; -ENTRY_FUNCTION(start_imx6dl_hummingboard, r0, r1, r2) +ENTRY_FUNCTION(start_hummingboard_microsom_i1, r0, r1, r2) { void *fdt; @@ -15,3 +16,33 @@ fdt = __dtb_imx6dl_hummingboard_start - get_runtime_offset(); barebox_arm_entry(0x10000000, SZ_512M, fdt); } + +ENTRY_FUNCTION(start_hummingboard_microsom_i2, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6dl_hummingboard_start - get_runtime_offset(); + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} + +ENTRY_FUNCTION(start_hummingboard_microsom_i2ex, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6q_hummingboard_start - get_runtime_offset(); + barebox_arm_entry(0x10000000, SZ_1G, fdt); +} + +ENTRY_FUNCTION(start_hummingboard_microsom_i4, r0, r1, r2) +{ + void *fdt; + + imx6_cpu_lowlevel_init(); + + fdt = __dtb_imx6q_hummingboard_start - get_runtime_offset(); + barebox_arm_entry(0x10000000, SZ_2G, fdt); +} diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig index 4c83102..c163827 100644 --- a/arch/arm/configs/eukrea_cpuimx35_defconfig +++ b/arch/arm/configs/eukrea_cpuimx35_defconfig @@ -77,6 +77,7 @@ CONFIG_NAND_IMX=y CONFIG_NAND_IMX_BBM=y CONFIG_USB_HOST=y +CONFIG_USB_IMX_CHIPIDEA=y CONFIG_USB_EHCI=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig index 0f38125..82b3821 100644 --- a/arch/arm/configs/imx_v7_defconfig +++ b/arch/arm/configs/imx_v7_defconfig @@ -4,10 +4,10 @@ CONFIG_MACH_EMBEDSKY_E9=y CONFIG_MACH_FREESCALE_MX51_PDK=y CONFIG_MACH_FREESCALE_MX53_LOCO=y +CONFIG_MACH_CCMX53=y CONFIG_MACH_TQMA53=y CONFIG_MACH_FREESCALE_MX53_VMX53=y -CONFIG_MACH_PCAAXL3=y -CONFIG_MACH_PHYTEC_PFLA02=y +CONFIG_MACH_PHYTEC_SOM_IMX6=y CONFIG_MACH_DFI_FS700_M60=y CONFIG_MACH_GUF_SANTARO=y CONFIG_MACH_REALQ7=y diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c87bd93..49a2f99 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -18,6 +18,7 @@ pbl-dtb-$(CONFIG_MACH_EMBEDSKY_E9) += imx6q-embedsky-e9.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o +pbl-dtb-$(CONFIG_MACH_CCMX53) += imx53-ccxmx53.dtb.o pbl-dtb-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o pbl-dtb-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o pbl-dtb-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o @@ -31,7 +32,6 @@ pbl-dtb-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o pbl-dtb-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o pbl-dtb-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o -pbl-dtb-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o pbl-dtb-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += am335x-phytec-phyflex-som.dtb.o am335x-phytec-phyflex-som-mlo.dtb.o \ am335x-phytec-phyflex-som-no-spi.dtb.o am335x-phytec-phyflex-som-no-eeprom.dtb.o \ @@ -39,7 +39,15 @@ am335x-phytec-phycore-som.dtb.o am335x-phytec-phycore-som-no-spi.dtb.o am335x-phytec-phycore-som-mlo.dtb.o \ am335x-phytec-phycore-som-no-eeprom.dtb.o am335x-phytec-phycore-som-no-spi-no-eeprom.dtb.o \ am335x-phytec-phycard-som.dtb.o am335x-phytec-phycard-som-mlo.dtb.o -pbl-dtb-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o imx6q-phytec-phyboard-alcor.dtb.o imx6dl-phytec-phyboard-subra.dtb.o +pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \ + imx6s-phytec-pbab01.dtb.o \ + imx6dl-phytec-pbab01.dtb.o \ + imx6q-phytec-pbab01.dtb.o \ + imx6q-phytec-phyboard-alcor.dtb.o \ + imx6dl-phytec-phyboard-subra.dtb.o \ + imx6q-phytec-phycore-som-nand.dtb.o \ + imx6q-phytec-phycore-som-emmc.dtb.o \ + imx6dl-phytec-phycore-som-nand.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o @@ -51,7 +59,7 @@ pbl-dtb-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o pbl-dtb-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-dtb-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o -pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o +pbl-dtb-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o imx6q-hummingboard.dtb.o pbl-dtb-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += imx6q-wandboard.dtb.o imx6dl-wandboard.dtb.o pbl-dtb-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o pbl-dtb-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o diff --git a/arch/arm/dts/imx53-ccxmx53.dts b/arch/arm/dts/imx53-ccxmx53.dts new file mode 100644 index 0000000..ac6103a --- /dev/null +++ b/arch/arm/dts/imx53-ccxmx53.dts @@ -0,0 +1,15 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include +#include "imx53-ccxmx53.dtsi" +#include "imx53.dtsi" diff --git a/arch/arm/dts/imx53-ccxmx53.dtsi b/arch/arm/dts/imx53-ccxmx53.dtsi new file mode 100644 index 0000000..6f76d28 --- /dev/null +++ b/arch/arm/dts/imx53-ccxmx53.dtsi @@ -0,0 +1,35 @@ +/ { + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &nfc, "partname:environment"; + }; + }; +}; + +&nfc { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "environment"; + reg = <0x80000 0x80000>; + }; + + partition@2 { + label = "kernel"; + reg = <0x100000 0x400000>; + }; + + partition@3 { + label = "rootfs"; + reg = <0x500000 0x07B00000>; + }; +}; diff --git a/arch/arm/dts/imx6dl-hummingboard.dts b/arch/arm/dts/imx6dl-hummingboard.dts index 24f6bfa..2314965 100644 --- a/arch/arm/dts/imx6dl-hummingboard.dts +++ b/arch/arm/dts/imx6dl-hummingboard.dts @@ -17,10 +17,10 @@ device-path = &usdhc2, "partname:barebox-environment"; }; }; +}; - memory { - reg = <0x10000000 0x20000000>; - }; +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; }; &usdhc2 { diff --git a/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts new file mode 100644 index 0000000..2324f3a --- /dev/null +++ b/arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts @@ -0,0 +1,63 @@ +/* + * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6dl.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 Duallite/SOLO with NAND"; + compatible = "phytec,imx6dl-pcm058-nand", "fsl,imx6dl"; +}; + +&eeprom { + status = "okay"; +}; + +&fec { + status = "okay"; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 14 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + reg = <3>; + max-speed = <100>; + }; + }; +}; + +&gpmi { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/dts/imx6q-hummingboard.dts b/arch/arm/dts/imx6q-hummingboard.dts new file mode 100644 index 0000000..e1d2fa8 --- /dev/null +++ b/arch/arm/dts/imx6q-hummingboard.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2013 Russell King + * + * The code contained herein is licensed under the GNU General Public + * License version 2. + */ + +#include +#include "imx6qdl.dtsi" + +/ { + chosen { + linux,stdout-path = &uart1; + + environment@0 { + compatible = "barebox,environment"; + device-path = &usdhc2, "partname:barebox-environment"; + }; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; +}; + +&usdhc2 { + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi index 97cf78a..0522465 100644 --- a/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi +++ b/arch/arm/dts/imx6q-phytec-pcaaxl3.dtsi @@ -17,7 +17,7 @@ compatible = "phytec,imx6q-pcaaxl3", "fsl,imx6q"; chosen { - environment-sd { + environment-sd3 { compatible = "barebox,environment"; device-path = &environment_usdhc3; status = "disabled"; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts new file mode 100644 index 0000000..6e19ab5 --- /dev/null +++ b/arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts @@ -0,0 +1,50 @@ +/* + * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 Quad with eMMC"; + compatible = "phytec,imx6q-pcm058-emmc", "fsl,imx6q"; +}; + +&eeprom { + status = "okay"; +}; + +&fec { + status = "okay"; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 14 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + reg = <3>; + max-speed = <1000>; + }; + }; +}; + +&usdhc1 { + status = "okay"; +}; + +&usdhc4 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts new file mode 100644 index 0000000..06f2f71 --- /dev/null +++ b/arch/arm/dts/imx6q-phytec-phycore-som-nand.dts @@ -0,0 +1,72 @@ +/* + * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include +#include "imx6q.dtsi" +#include "imx6qdl-phytec-phycore-som.dtsi" + +/ { + model = "Phytec phyCORE-i.MX6 Quad with NAND"; + compatible = "phytec,imx6q-pcm058-nand", "fsl,imx6q"; + +}; + +&ecspi1 { + status = "okay"; +}; + +&eeprom { + status = "okay"; +}; + +&fec { + status = "okay"; + phy-handle = <ðphy>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 14 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { + reg = <3>; + max-speed = <1000>; + }; + }; +}; + +&flash { + status = "okay"; +}; + +&gpmi { + status = "okay"; +}; + +&usdhc1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi new file mode 100644 index 0000000..2a975d1 --- /dev/null +++ b/arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi @@ -0,0 +1,266 @@ +/* + * Copyright 2015 Christian Hemp, Phytec Messtechnik GmbH + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx6qdl.dtsi" + +/ { + chosen { + linux,stdout-path = &uart2; + + environment-sd1 { + compatible = "barebox,environment"; + device-path = &usdhc1, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-sd4 { + compatible = "barebox,environment"; + device-path = &usdhc4, "partname:barebox-environment"; + status = "disabled"; + }; + + environment-nand { + compatible = "barebox,environment"; + device-path = &gpmi, "partname:barebox-environment"; + status = "disabled"; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 0>; + status = "disabled"; + + flash: m25p80@0 { + compatible = "m25p80"; + spi-max-frequency = <20000000>; + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x100000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x100000 0x20000>; + }; + + partition@2 { + label = "oftree"; + reg = <0x120000 0x20000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x140000 0x0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x400000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x400000 0x100000>; + }; + + partition@2 { + label = "oftree"; + reg = <0x500000 0x100000>; + }; + + partition@3 { + label = "kernel"; + reg = <0x600000 0x800000>; + }; + + partition@4 { + label = "root"; + reg = <0xe00000 0x0>; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; + + eeprom: 24c32@50 { + status = "disabled"; + compatible = "st,24c32"; + reg = <0x50>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx6qdl-phytec-phycore-som { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x80000000 + >; + }; + + pinctrl_gpmi_nand: gpmigrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1 + MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 /* CD */ + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&ocotp { + barebox,provide-mac-address = <&fec 0x620>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio6 31 0>; + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "barebox"; + reg = <0x0 0x80000>; + }; + + partition@1 { + label = "barebox-environment"; + reg = <0x80000 0x80000>; + }; +}; diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 0a7b517..3f6dd77 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -34,11 +34,10 @@ default 0x4fc00000 if MACH_REALQ7 default 0x4fc00000 if MACH_GK802 default 0x2fc00000 if MACH_TQMA6X - default 0x4fc00000 if MACH_PHYTEC_PFLA02 default 0x4fc00000 if MACH_DFI_FS700_M60 default 0x4fc00000 if MACH_UDOO default 0x4fc00000 if MACH_VARISCITE_MX6 - default 0x4fc00000 if MACH_PCAAXL3 + default 0x4fc00000 if MACH_PHYTEC_SOM_IMX6 config ARCH_IMX_INTERNAL_BOOT bool "support internal boot mode" @@ -246,6 +245,13 @@ select DRIVER_SPI_IMX select MFD_MC13XXX +config MACH_CCMX53 + bool "Digi ConnectCore i.MX53" + select ARCH_IMX53 + help + Say Y here if you are using the Digi ConnectCore ccxmx53 + series SoM + config MACH_FREESCALE_MX53_LOCO bool "Freescale i.MX53 LOCO" select ARCH_IMX53 @@ -268,14 +274,10 @@ Say Y here if you are using the Voipac Technologies X53-DMM-668 module equipped with a Freescale i.MX53 Processor -config MACH_PCAAXL3 - bool "Phytec phyCARD-i.MX6 Quad" +config MACH_PHYTEC_SOM_IMX6 + bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6" select ARCH_IMX6 -config MACH_PHYTEC_PFLA02 - bool "Phytec phyFLEX-i.MX6" - select ARCH_IMX6 - config MACH_DFI_FS700_M60 bool "DFI i.MX6 FS700 M60 Q7 Board" select ARCH_IMX6 diff --git a/arch/arm/mach-imx/clk-imx5.c b/arch/arm/mach-imx/clk-imx5.c index 6dc3c80..70db31c 100644 --- a/arch/arm/mach-imx/clk-imx5.c +++ b/arch/arm/mach-imx/clk-imx5.c @@ -332,7 +332,7 @@ static void mx53_clocks_ipu_init(void __iomem *regs) { clks[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1); + clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_np("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1); clks[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", regs + CCM_CSCMR2, 9, 1, mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel)); clks[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", regs + CCM_CDCDR, 16, 3); diff --git a/arch/arm/mach-imx/clk-imx6.c b/arch/arm/mach-imx/clk-imx6.c index f18ad40..597e502 100644 --- a/arch/arm/mach-imx/clk-imx6.c +++ b/arch/arm/mach-imx/clk-imx6.c @@ -300,9 +300,9 @@ clks[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3); clks[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3); clks[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clks[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1); + clks[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_np("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1); clks[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clks[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1); + clks[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_np("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1); clks[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3); clks[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3); clks[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3); diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h index c8da2fa..c5913e1 100644 --- a/arch/arm/mach-imx/clk.h +++ b/arch/arm/mach-imx/clk.h @@ -10,6 +10,12 @@ return clk_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT); } +static inline struct clk *imx_clk_divider_np(const char *name, const char *parent, + void __iomem *reg, u8 shift, u8 width) +{ + return clk_divider(name, parent, reg, shift, width, 0); +} + static inline struct clk *imx_clk_divider_table(const char *name, const char *parent, void __iomem *reg, u8 shift, u8 width, const struct clk_div_table *table) diff --git a/arch/arm/mach-imx/imx35.c b/arch/arm/mach-imx/imx35.c index 69d45eb..3e1aa97 100644 --- a/arch/arm/mach-imx/imx35.c +++ b/arch/arm/mach-imx/imx35.c @@ -73,6 +73,7 @@ add_generic_device("imx31-gpio", 1, NULL, MX35_GPIO2_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx31-gpio", 2, NULL, MX35_GPIO3_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL); add_generic_device("imx21-wdt", 0, NULL, MX35_WDOG_BASE_ADDR, 0x4000, IORESOURCE_MEM, NULL); + add_generic_device("imx35-usb-misc", 0, NULL, MX35_USB_OTG_BASE_ADDR + 0x600, 0x100, IORESOURCE_MEM, NULL); return 0; } diff --git a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h index ac2764f..fd1de8e 100644 --- a/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h +++ b/arch/arm/mach-imx/include/mach/imx6-ddr-regs.h @@ -24,6 +24,7 @@ #define MX6_MMDC_P0_MDRWD 0x021b002c #define MX6_MMDC_P0_MDOR 0x021b0030 #define MX6_MMDC_P0_MDASP 0x021b0040 +#define MX6_MMDC_P0_MAARCR 0x021b0400 #define MX6_MMDC_P0_MAPSR 0x021b0404 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c diff --git a/arch/arm/mach-imx/ocotp.c b/arch/arm/mach-imx/ocotp.c index c99a003..6ff5ee4 100644 --- a/arch/arm/mach-imx/ocotp.c +++ b/arch/arm/mach-imx/ocotp.c @@ -426,6 +426,7 @@ cdev->priv = priv; cdev->size = 192; cdev->name = "imx-ocotp"; + cdev->device_node = dev->device_node; ret = devfs_create(cdev); diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c index 9a3f05c..2e48967 100644 --- a/drivers/spi/imx_spi.c +++ b/drivers/spi/imx_spi.c @@ -380,6 +380,77 @@ } } +static int cspi_2_3_xchg_burst(struct spi_device *spi) +{ + struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); + int now, txlen, rxlen; + u32 ctrl; + void __iomem *base = imx->regs; + + now = min(imx->xfer_len, 512); + now >>= 2; + + if (!now) + return 0; + + txlen = rxlen = now; + + ctrl = readl(base + CSPI_2_3_CTRL); + ctrl &= ~(0xfff << CSPI_2_3_CTRL_BL_OFFSET); + ctrl |= ((txlen * 32) - 1) << CSPI_2_3_CTRL_BL_OFFSET; + ctrl |= 1 << 3; + writel(ctrl, base + CSPI_2_3_CTRL); + + while (txlen || rxlen) { + u32 status = readl(base + CSPI_2_3_STAT); + + if (txlen && !(status & CSPI_2_3_STAT_TF)) { + if (imx->tx_buf) { + u32 data = swab32(*(u32 *)imx->tx_buf); + writel(data, base + CSPI_2_3_TXDATA); + imx->tx_buf += sizeof(u32); + } else { + writel(0, base + CSPI_2_3_TXDATA); + } + txlen--; + } + + if (rxlen && (status & CSPI_2_3_STAT_RR)) { + u32 data = readl(base + CSPI_2_3_RXDATA); + + if (imx->rx_buf) { + *(u32 *)imx->rx_buf = swab32(data); + imx->rx_buf += sizeof(u32); + } + + rxlen--; + } + } + + imx->xfer_len -= now * 4; + + return now; +} + +static void cspi_2_3_do_transfer(struct spi_device *spi) +{ + struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); + u32 ctrl; + + if (imx->bits_per_word == 8 && !(spi->mode & SPI_LSB_FIRST)) + while (cspi_2_3_xchg_burst(spi) > 0); + + if (!imx->xfer_len) + return; + + ctrl = readl(imx->regs + CSPI_2_3_CTRL); + ctrl &= ~(0xfff << CSPI_2_3_CTRL_BL_OFFSET); + ctrl |= (spi->bits_per_word - 1) << CSPI_2_3_CTRL_BL_OFFSET; + writel(ctrl, imx->regs + CSPI_2_3_CTRL); + + imx_spi_do_transfer(spi); +} + static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) { struct imx_spi *imx = container_of(spi->master, struct imx_spi, master); @@ -437,7 +508,7 @@ static __maybe_unused struct spi_imx_devtype_data spi_imx_devtype_data_2_3 = { .chipselect = cspi_2_3_chipselect, - .do_transfer = imx_spi_do_transfer, + .do_transfer = cspi_2_3_do_transfer, .xchg_single = cspi_2_3_xchg_single, }; diff --git a/drivers/video/imx-ipu-v3/imx-ldb.c b/drivers/video/imx-ipu-v3/imx-ldb.c index a41eb1a..2340b9b 100644 --- a/drivers/video/imx-ipu-v3/imx-ldb.c +++ b/drivers/video/imx-ipu-v3/imx-ldb.c @@ -68,7 +68,7 @@ struct imx_ldb_data { void __iomem *base; - int (*prepare)(struct imx_ldb_channel *imx_ldb_ch, int di); + int (*prepare)(struct imx_ldb_channel *imx_ldb_ch, int di, unsigned long clkrate); unsigned ipu_mask; int have_mux; }; @@ -114,7 +114,7 @@ { struct imx_ldb *ldb = imx_ldb_ch->ldb; - ldb->soc_data->prepare(imx_ldb_ch, di); + ldb->soc_data->prepare(imx_ldb_ch, di, PICOS2KHZ(mode->pixclock) * 1000UL); /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ if (imx_ldb_ch == &ldb->channel[0]) { @@ -146,7 +146,8 @@ return 0; } -static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di) +static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di, + unsigned long pixclk) { struct clk *diclk, *ldbclk; struct imx_ldb *ldb = imx_ldb_ch->ldb; @@ -155,6 +156,7 @@ void __iomem *gpr3 = (void *)MX6_IOMUXC_BASE_ADDR + 0xc; uint32_t val; int shift; + int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; ipuno = ((di >> 1) & 1) + 1; dino = di & 0x1; @@ -181,6 +183,11 @@ return ret; } + if (!dual) + pixclk *= 2; + + clk_set_rate(clk_get_parent(ldbclk), pixclk); + val = readl(gpr3); shift = (imx_ldb_ch->chno == 0) ? 6 : 8; val &= ~(3 << shift); @@ -190,12 +197,14 @@ return 0; } -static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di) +static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di, + unsigned long pixclk) { struct clk *diclk, *ldbclk; struct imx_ldb *ldb = imx_ldb_ch->ldb; int ret, dino; char *clkname; + int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; dino = di & 0x1; @@ -221,6 +230,11 @@ return ret; } + if (!dual) + pixclk *= 2; + + clk_set_rate(clk_get_parent(ldbclk), pixclk); + return 0; } @@ -299,6 +313,10 @@ imx_ldb->base = devtype->base; imx_ldb->soc_data = devtype; + dual = of_property_read_bool(np, "fsl,dual-channel"); + if (dual) + imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; + for_each_child_of_node(np, child) { struct imx_ldb_channel *channel; struct device_node *port; diff --git a/drivers/watchdog/imxwd.c b/drivers/watchdog/imxwd.c index dd11a62..1952548 100644 --- a/drivers/watchdog/imxwd.c +++ b/drivers/watchdog/imxwd.c @@ -97,9 +97,12 @@ dev_dbg(priv->dev, "%s: %d\n", __func__, timeout); - if (!timeout || timeout > 128) + if (timeout < -1 || timeout > 128) return -EINVAL; + if (timeout == 0) /* bit 2 (WDE) cannot be set to 0 again */ + return -ENOSYS; + if (timeout > 0) val = ((timeout * 2 - 1) << 8) | IMX21_WDOG_WCR_SRS | IMX21_WDOG_WCR_WDA; diff --git a/dts/src/arm/imx53-ccxmx53.dts b/dts/src/arm/imx53-ccxmx53.dts new file mode 100644 index 0000000..85d20c3 --- /dev/null +++ b/dts/src/arm/imx53-ccxmx53.dts @@ -0,0 +1,104 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx53-ccxmx53.dtsi" + +/ { + model = "Digi ConnectCore ccxmx53"; + compatible = "digi,imx53-ccxmx53", "fsl,imx53"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-ccxmx53 { + pinctrl_hog: hoggrp { + + }; + + pinctrl_esdhc2: esdhc2grp { + fsl,pins = < + MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 + MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 + /* SD2_CD */ + MX53_PAD_GPIO_4__GPIO1_4 0x1d5 + /* SD2_WP */ + MX53_PAD_GPIO_2__GPIO1_2 0x1d5 + >; + }; + + pinctrl_esdhc3: esdhc3grp { + fsl,pins = < + MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 + MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 + MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 + MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 + MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 + MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 + >; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc2>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc3>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + phy-reset-duration = <10>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&iim { + barebox,provide-mac-address = <&fec 1 9>; +}; diff --git a/dts/src/arm/imx53-ccxmx53.dtsi b/dts/src/arm/imx53-ccxmx53.dtsi new file mode 100644 index 0000000..7632167 --- /dev/null +++ b/dts/src/arm/imx53-ccxmx53.dtsi @@ -0,0 +1,223 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "imx53.dtsi" + +/ { + memory { + reg = <0x70000000 0x40000000>; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-ccxmx53 { + pinctrl_hog: hoggrp { + + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 + MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 + MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 + MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4 + MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4 + MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4 + MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4 + MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4 + MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4 + MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4 + MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4 + >; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pmic: dialog@68 { + compatible = "dlg,da9053-aa"; + reg = <0x68>; + interrupt-parent = <&gpio7>; + interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */ + + regulators { + buck1_reg: buck1 { + regulator-name = "BUCKCORE"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "BUCKPRO"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "BUCKMEM"; + regulator-min-microvolt = <1420000>; + regulator-max-microvolt = <1580000>; + regulator-always-on; + }; + + buck4_reg: buck4 { + regulator-name = "BUCKPERI"; + regulator-min-microvolt = <2370000>; + regulator-max-microvolt = <2630000>; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "ldo1_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "ldo2_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "ldo3_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "ldo4_2v775"; + regulator-min-microvolt = <2770000>; + regulator-max-microvolt = <2780000>; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + regulator-name = "ldo5_3v3"; + regulator-min-microvolt = <3250000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + }; + + ldo6_reg: ldo6 { + regulator-name = "ldo6_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + ldo7_reg: ldo7 { + regulator-name = "ldo7_2v75"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo8_reg: ldo8 { + regulator-name = "ldo8_1v8"; + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1850000>; + regulator-always-on; + }; + + ldo9_reg: ldo9 { + regulator-name = "ldo9_1v5"; + regulator-min-microvolt = <1450000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + ldo10_reg: ldo10 { + regulator-name = "ldo10_1v3"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; diff --git a/images/Makefile.imx b/images/Makefile.imx index a09afd6..ea9346a 100644 --- a/images/Makefile.imx +++ b/images/Makefile.imx @@ -76,6 +76,16 @@ FILE_barebox-freescale-imx53-loco-r.img = start_imx53_loco_r.pblx.imximg image-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += barebox-freescale-imx53-loco-r.img +pblx-$(CONFIG_MACH_CCMX53) += start_ccxmx53_512mb +CFG_start_ccxmx53_512mb.pblx.imximg = $(board)/ccxmx53/flash-header-imx53-ccxmx53_512mb.imxcfg +FILE_barebox-imx53-ccxmx53_512mb.img = start_ccxmx53_512mb.pblx.imximg +image-$(CONFIG_MACH_CCMX53) += barebox-imx53-ccxmx53_512mb.img + +pblx-$(CONFIG_MACH_CCMX53) += start_ccxmx53_1gib +CFG_start_ccxmx53_1gib.pblx.imximg = $(board)/ccxmx53/flash-header-imx53-ccxmx53_1gib.imxcfg +FILE_barebox-imx53-ccxmx53_1gib.img = start_ccxmx53_1gib.pblx.imximg +image-$(CONFIG_MACH_CCMX53) += barebox-imx53-ccxmx53_1gib.img + pblx-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += start_imx53_vmx53 CFG_start_imx53_vmx53.pblx.imximg = $(board)/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg FILE_barebox-freescale-imx53-vmx53.img = start_imx53_vmx53.pblx.imximg @@ -127,45 +137,65 @@ FILE_barebox-tq-tqma6q-mba6x.img = start_imx6q_mba6x.pblx.imximg image-$(CONFIG_MACH_TQMA6X) += barebox-tq-tqma6q-mba6x.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_4gib -CFG_start_phytec_pbab01_4gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-4gib.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01_4gib +CFG_start_phytec_pbab01_4gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02-4gib.imxcfg FILE_barebox-phytec-pbab01-4gib.img = start_phytec_pbab01_4gib.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-4gib.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01-4gib.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_2gib -CFG_start_phytec_pbab01_2gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-2gib.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01_2gib +CFG_start_phytec_pbab01_2gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02-2gib.imxcfg FILE_barebox-phytec-pbab01-2gib.img = start_phytec_pbab01_2gib.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-2gib.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01-2gib.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_1gib -CFG_start_phytec_pbab01_1gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01_1gib +CFG_start_phytec_pbab01_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg FILE_barebox-phytec-pbab01-1gib.img = start_phytec_pbab01_1gib.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-1gib.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01-1gib.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_1gib_1bank -CFG_start_phytec_pbab01_1gib_1bank.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01_1gib_1bank +CFG_start_phytec_pbab01_1gib_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02-1gib-1bank.imxcfg FILE_barebox-phytec-pbab01-1gib-1bank.img = start_phytec_pbab01_1gib_1bank.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-1gib-1bank.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01-1gib-1bank.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01dl_1gib -CFG_start_phytec_pbab01dl_1gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01_512mb_1bank +CFG_start_phytec_pbab01_512mb_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02-512mb-1bank.imxcfg +FILE_barebox-phytec-pbab01-512mb-1bank.img = start_phytec_pbab01_512mb_1bank.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01-512mb-1bank.img + +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01dl_1gib +CFG_start_phytec_pbab01dl_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib.imxcfg FILE_barebox-phytec-pbab01dl-1gib.img = start_phytec_pbab01dl_1gib.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01dl-1gib.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01dl-1gib.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01s_512mb -CFG_start_phytec_pbab01s_512mb.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg -FILE_barebox-phytec-pbab01s-512mb.img = start_phytec_pbab01s_512mb.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01s-512mb.img +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01dl_1gib_1bank +CFG_start_phytec_pbab01dl_1gib_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02dl-1gib-1bank.imxcfg +FILE_barebox-phytec-pbab01dl-1gib-1bank.img = start_phytec_pbab01dl_1gib_1bank.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01dl-1gib-1bank.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_phyboard_alcor_1gib -CFG_start_phytec_phyboard_alcor_1gib.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02-1gib.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01s_512mb_1bank +CFG_start_phytec_pbab01s_512mb_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg +FILE_barebox-phytec-pbab01s-512mb-1bank.img = start_phytec_pbab01s_512mb_1bank.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01s-512mb-1bank.img + +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01s_256mb_1bank +CFG_start_phytec_pbab01s_256mb_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02s-256mb-1bank.imxcfg +FILE_barebox-phytec-pbab01s-256mb-1bank.img = start_phytec_pbab01s_256mb_1bank.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01s-256mb-1bank.img + +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbab01s_128mb_1bank +CFG_start_phytec_pbab01s_128mb_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02s-128mb-1bank.imxcfg +FILE_barebox-phytec-pbab01s-128mb-1bank.img = start_phytec_pbab01s_128mb_1bank.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbab01s-128mb-1bank.img + +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phyboard_alcor_1gib +CFG_start_phytec_phyboard_alcor_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02-1gib.imxcfg FILE_barebox-phytec-phyboard-alcor-1gib.img = start_phytec_phyboard_alcor_1gib.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-phyboard-alcor-1gib.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phyboard-alcor-1gib.img -pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_phyboard_subra_512mb -CFG_start_phytec_phyboard_subra_512mb.pblx.imximg = $(board)/phytec-phyflex-imx6/flash-header-phytec-pfla02s-512mb.imxcfg -FILE_barebox-phytec-phyboard-subra-512mb.img = start_phytec_phyboard_subra_512mb.pblx.imximg -image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-phyboard-subra-512mb.img +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phyboard_subra_512mb_1bank +CFG_start_phytec_phyboard_subra_512mb_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pfla02s-512mb-1bank.imxcfg +FILE_barebox-phytec-phyboard-subra-512mb-1bank.img = start_phytec_phyboard_subra_512mb_1bank.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phyboard-subra-512mb-1bank.img pblx-$(CONFIG_MACH_DFI_FS700_M60) += start_imx6dl_dfi_fs700_m60_6s CFG_start_imx6dl_dfi_fs700_m60_6s.pblx.imximg = $(board)/dfi-fs700-m60/flash-header-fs700-m60-6s.imxcfg @@ -202,16 +232,31 @@ FILE_barebox-freescale-imx6sx-sabresdb.img = start_imx6sx_sabresdb.pblx.imximg image-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += barebox-freescale-imx6sx-sabresdb.img -pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_imx6dl_hummingboard -CFG_start_imx6dl_hummingboard.pblx.imximg = $(board)/solidrun-microsom/flash-header-solidrun-hummingboard.imxcfg -FILE_barebox-solidrun-imx6dl-hummingboard.img = start_imx6dl_hummingboard.pblx.imximg -image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-imx6dl-hummingboard.img +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard_microsom_i1 +CFG_start_hummingboard_microsom_i1.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i1.imxcfg +FILE_barebox-solidrun-hummingboard-microsom-i1.img = start_hummingboard_microsom_i1.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard-microsom-i1.img pblx-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += start_imx6_wandboard CFG_start_imx6_wandboard.imx-sram-img = $(board)/technexion-wandboard/flash-header-technexion-wandboard.imxcfg FILE_barebox-imx6-wandboard.img = start_imx6_wandboard.imx-sram-img image-$(CONFIG_MACH_TECHNEXION_WANDBOARD) += barebox-imx6-wandboard.img +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard_microsom_i2 +CFG_start_hummingboard_microsom_i2.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i2.imxcfg +FILE_barebox-solidrun-hummingboard-microsom-i2.img = start_hummingboard_microsom_i2.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard-microsom-i2.img + +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard_microsom_i2ex +CFG_start_hummingboard_microsom_i2ex.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i2eX.imxcfg +FILE_barebox-solidrun-hummingboard-microsom-i2eX.img = start_hummingboard_microsom_i2ex.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard-microsom-i2eX.img + +pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_hummingboard_microsom_i4 +CFG_start_hummingboard_microsom_i4.pblx.imximg = $(board)/solidrun-microsom/flash-header-microsom-i4.imxcfg +FILE_barebox-solidrun-hummingboard-microsom-i4.img = start_hummingboard_microsom_i4.pblx.imximg +image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-hummingboard-microsom-i4.img + pblx-$(CONFIG_MACH_NITROGEN6X) += start_imx6q_nitrogen6x_1g CFG_start_imx6q_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6x/flash-header-nitrogen6q-1g.imxcfg FILE_barebox-boundarydevices-imx6q-nitrogen6x-1g.img = start_imx6q_nitrogen6x_1g.pblx.imximg @@ -267,20 +312,35 @@ FILE_barebox-embest-imx6s-riotboard.img = start_imx6s_riotboard.pblx.imximg image-$(CONFIG_MACH_EMBEST_RIOTBOARD) += barebox-embest-imx6s-riotboard.img -pblx-$(CONFIG_MACH_PCAAXL3) += start_phytec_pbaa03_1gib -CFG_start_phytec_pbaa03_1gib.pblx.imximg = $(board)/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_1gib +CFG_start_phytec_pbaa03_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib.imxcfg FILE_barebox-phytec-pbaa03-1gib.img = start_phytec_pbaa03_1gib.pblx.imximg -image-$(CONFIG_MACH_PCAAXL3) += barebox-phytec-pbaa03-1gib.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbaa03-1gib.img -pblx-$(CONFIG_MACH_PCAAXL3) += start_phytec_pbaa03_1gib_1bank -CFG_start_phytec_pbaa03_1gib_1bank.pblx.imximg = $(board)/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_1gib_1bank +CFG_start_phytec_pbaa03_1gib_1bank.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-1gib-1bank.imxcfg FILE_barebox-phytec-pbaa03-1gib-1bank.img = start_phytec_pbaa03_1gib_1bank.pblx.imximg -image-$(CONFIG_MACH_PCAAXL3) += barebox-phytec-pbaa03-1gib-1bank.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbaa03-1gib-1bank.img -pblx-$(CONFIG_MACH_PCAAXL3) += start_phytec_pbaa03_2gib -CFG_start_phytec_pbaa03_2gib.pblx.imximg = $(board)/phytec-phycard-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_pbaa03_2gib +CFG_start_phytec_pbaa03_2gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcaaxl3-2gib.imxcfg FILE_barebox-phytec-pbaa03-2gib.img = start_phytec_pbaa03_2gib.pblx.imximg -image-$(CONFIG_MACH_PCAAXL3) += barebox-phytec-pbaa03-2gib.img +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-pbaa03-2gib.img + +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6q_som_nand_1gib +CFG_start_phytec_phycore_imx6q_som_nand_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg +FILE_barebox-phytec-phycore-imx6q-som-nand-1gib.img = start_phytec_phycore_imx6q_som_nand_1gib.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6q-som-nand-1gib.img + +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6q_som_emmc_1gib +CFG_start_phytec_phycore_imx6q_som_emmc_1gib.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcm058-1gib.imxcfg +FILE_barebox-phytec-phycore-imx6q-som-emmc-1gib.img = start_phytec_phycore_imx6q_som_emmc_1gib.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6q-som-emmc-1gib.img + +pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6dl_som_nand_256mb +CFG_start_phytec_phycore_imx6dl_som_nand_256mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcm058dl-256mb.imxcfg +FILE_barebox-phytec-phycore-imx6dl-som-nand-256mb.img = start_phytec_phycore_imx6dl_som_nand_256mb.pblx.imximg +image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6dl-som-nand-256mb.img pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64 CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg diff --git a/include/spi/imx-spi.h b/include/spi/imx-spi.h index 5c89634..221c665 100644 --- a/include/spi/imx-spi.h +++ b/include/spi/imx-spi.h @@ -79,6 +79,7 @@ #define CSPI_2_3_INT_RREN (1 << 3) #define CSPI_2_3_STAT 0x18 -#define CSPI_2_3_STAT_RR (1 << 3) +#define CSPI_2_3_STAT_TF (1 << 2) +#define CSPI_2_3_STAT_RR (1 << 3) #endif /* __SPI_IMX_SPI_H */ diff --git a/lib/gui/graphic_utils.c b/lib/gui/graphic_utils.c index 4c1885d..2fe9fa3 100644 --- a/lib/gui/graphic_utils.c +++ b/lib/gui/graphic_utils.c @@ -249,6 +249,10 @@ { struct screen *sc; + if (!info->xres || !info->yres || !info->line_length || + !info->screen_base) + return ERR_PTR(-EINVAL); + sc = xzalloc(sizeof(*sc)); sc->s.x = 0;