diff --git a/Documentation/barebox-main.dox b/Documentation/barebox-main.dox
index fb780e6..90fce8e 100644
--- a/Documentation/barebox-main.dox
+++ b/Documentation/barebox-main.dox
@@ -1,166 +1,74 @@
-/** @mainpage Universal Bootloader
+/** @mainpage Barebox
-@section barebox_intro Introduction
+Barebox is a bootloader that initializes a hardware and boots Linux and
+maybe other operating systems or bare metal code on a variety of
+processors. It was initialy derived from U-Boot and captures up with
+several of it's ideas, so users being familiar with U-Boot should come
+into production quickly with Barebox.
-@a Barebox is a bootloader which follows the tradition of U-Boot. U-Boot
-offers an excellent choice as a bootloader for today's embedded systems,
-seen from a user's point of view. Nevertheless, there are quite some
-design flaws which turned out over the last years and we think that they
-cannot be solved in a production tree. So this tree tries to do several
-things right - without caring about losing support for old boards.
+However, as the Barebox developers are highly addicted to the Linux
+kernel, it's coding style and code quality, we try to stick as closely
+as possible to the methodologies and techniques developed in Linux. In
+addition we have a strong background in POSIX, so you'll find several
+good old Unix traditions realized in Barebox as well.
-@par General features include:
+@par Highlights:
-- A posix based file API
- - inside @a barebox the usual open/close/read/write/lseek functions are used.
- This makes it familiar to everyone who has programmed under unix systems.
+- POSIX File API:
+ @a Barebox uses the the well known open/close/read/write/lseek access
+ functions, together with a model of representing devices by files. This
+ makes the APIs familiar to everyone who has experience with Unix
+ systems.
-- usual shell commands like ls/cd/mkdir/echo/cat,...
+- Shell:
+ We have the standard shell commands like ls/cd/mkdir/echo/cat,...
-- The environment is not a variable store anymore, but a file store. It has
- currently some limitations, of course. The environment is not a real
- read/write filesystem, it is more like a tar archive, or even more like
- an ar archive, because it cannot handle directories. The saveenv command
- saves the files under a certain directory (by default /env) in persistent
- storage (by default /dev/env0). There is a counterpart called loadenv, too.
+- Environment Filesystem:
+ In contrast to U-Boot, Barebox doesn't misuse the environment for
+ scripting. If you start the bootloader, it gives you a shell and
+ something that looks like a filesystem. In fact it isn't: it is a very
+ simple ar archive being extracted from flash into a ramdisk with 'loadenv'
+ and stored back with 'saveenv'.
-- Real filesystem support
- - The loader starts up with mounting a ramdisk on /. Then a devfs is mounted
- on /dev allowing the user (or shell commands) to access devices. Apart from
- these two filesystems there is currently one filesystem ported: cramfs. One
- can mount it with the usual mount command.
+- Filesystem Support:
+ When starting up, the environment is mounted to /, followed by a
+ device filesytem being mounted to /dev in order to make it possible to
+ access devices. Other filesystems can be mounted on demand.
-- device/driver model
- - Devices are no longer described by defines in the config file. Instead
- there are devices which can be registered in the board .c file or
- dynamically allocated. Drivers will match upon the devices automatically.
+- Driver Model (borrowed from Linux):
+ Barebox follows the Linux driver model: devices can be specified in a
+ hardware specific file, and drivers feel responsible for these devices
+ if they have the same name.
-- clocksource support
- - Timekeeping has been simplified by the use of the Linux clocksource API.
- Only one function is needed for a new board, no [gs]et_timer[masked]() or
- reset_timer[masked]() functions.
+- Clocksource:
+ We use the clocksource API knwon from Linux.
-- Kconfig and Kernel build system
- - Only targets which are really needed get recompiled. Parallel builds are
- no problem anymore. This also removes the need for many many ifdefs in
- the code.
+- Kconfig/Kbuild:
+ This gives us parallel builds and removes the need for lots of ifdefs.
-- simulation target
- - @a barebox can be compiled to run under Linux. While this is rather useless
- in real world this is a great debugging and development aid. New features
- can be easily developed and tested on long train journeys and started
- under gdb. There is a console driver for linux which emulates a serial
- device and a tap based ethernet driver. Linux files can be mapped to
- devices under @a barebox to emulate storage devices.
+- Sandbox:
+ If you develop features for @a Barebox, you can use the 'sandbox'
+ target which compiles @a Barebox as a POSIX application in the Linux
+ userspace: it can be started like a normal command and even has
+ network access (tun/tap). Files from the local filesytem can be used
+ to simulate devices.
-- device parameter support
- - Each device can have a unlimited number of parameters. They can be accessed
- on the command line with \.\="...", for example
- 'eth0.ip=192.168.0.7' or 'echo $eth0.ip'
+- Device Parameters:
+ There is a parameter model in @a Barebox: each device can specify it's
+ own parameters, which do exist for every instance. Parameters can be
+ changed on the command line with \.\="...". For
+ example, if you want to access the IPv4 address for eth0, this is done
+ with 'eth0.ip=192.168.0.7' and 'echo $eth0.ip'.
-- initcalls
- - hooks in the startup process can be achieved with *_initcall() directives
- in each file.
+- Getopt:
+ @a Barebox has a lightweight getopt() implementation. This makes it
+ unnecessary to use positional parameters, which can be hard to read.
-- getopt
- - There is a small getopt implementation. Some commands got really
- complicated (both in code and in usage) due to the fact that @a U-Boot only
- allowed positional parameters.
+- Integrated Editor:
+ Scripts can be edited with a small integrated fullscreen editor.
+ This editor has no features except the ones really needed: moving
+ the cursor around, typing characters, exiting and saving.
-- editor
- - Scripts can be edited with a small editor. This editor has no features
- except the ones really needed: moving the cursor and typing characters.
-
-@par Building barebox
-
-@a Barebox uses the Linux kernel's build system. It consists of two parts:
-the makefile infrastructure (kbuild), plus a configuration system
-(kconfig). So building @a barebox is very similar to building the Linux
-kernel.
-
-For the examples below, we use the User Mode @a barebox implementation, which
-is a port of @a barebox to the Linux userspace. This makes it possible to
-test drive the code without having real hardware. So for this test
-scenario, @p ARCH=sandbox is the valid architecture selection. This currently
-only works on ia32 hosts and partly on x86-64.
-
-Selection of the architecture and the cross compiler can be done in two
-ways. You can either specify it using the environment variables @p ARCH
-and @p CROSS_COMPILE, or you can create the soft links cross_arch and
-cross_compile pointing to your architecture and compiler. For @p ARCH=sandbox
-we do not need a cross compiler so it is sufficient to specify the
-architecture:
-
-@code # ln -s arch/sandbox cross_arch @endcode
-
-In order to configure the various aspects of @a barebox, start the @a barebox
-configuration system:
-
-@code # make menuconfig @endcode
-
-This command starts a menu box and lets you select all the different
-options available for your architecture. Once the configuration was
-finished (you can simulate this by using the standard demo config file
-with 'make sandbox_defconfig'), there is a .config file in the toplevel
-directory of the sourcecode.
-
-Once @a barebox is configured, we can start the compilation
-
-@code # make @endcode
-
-If everything goes well, the result is a file called @p barebox:
-
-@code
- # ls -l barebox
- -rwxr-xr-x 1 rsc ptx 114073 Jun 26 22:34 barebox
-@endcode
-
-@a barebox usually needs an environment for storing the configuration data.
-You can generate an environment using the example environment contained
-in arch/sanbox/board/env:
-
-@code # ./scripts/bareboxenv -s -p 0x10000 arch/sanbox/board/env/ env.bin @endcode
-
-To get some files to play with you can generate a cramfs image:
-
-@code # mkcramfs somedir/ cramfs.bin @endcode
-
-The @a barebox image is a normal Linux executable, so it can be started
-just like every other program:
-
-@code
- # ./barebox -e env.bin -i cramfs.bin
-
- barebox 2.0.0-trunk (Jun 26 2007 - 22:34:38)
-
- loading environment from /dev/env0
- barebox\> /
-@endcode
-
-Specifying -[ie] \ tells @a barebox to map the file as a device
-under @p /dev. Files given with '-e' will appear as @p /dev/env[n]. Files
-given with '-i' will appear as @p /dev/fd[n].
-If @a barebox finds a valid configuration sector on @p /dev/env0 it will
-load it to @p /env. It then executes @p /env/init if it exists. If you have
-loaded the example environment @a barebox will show you a menu asking for
-your settings.
-
-If you have started @a barebox as root you will find a new tap device on your
-host which you can configure using ifconfig. Once you configured the
-network settings accordingly you can do a ping or tftpboot.
-
-If you have mapped a cramfs image try mounting it with
-
-@code
- # mkdir /cram
- # mount /dev/fd0 cramfs /cram
-@endcode
-
-Memory can be examined as usual using @p md/mw commands. They both understand
-the -f \ option to tell the commands that they should work on the
-specified files instead of @p /dev/mem which holds the complete address space.
-Note that if you call 'md /dev/fd0' (without -f) @a barebox will segfault on
-the host, because it will interpret @p /dev/fd0 as a number.
@par Directory layout
diff --git a/Documentation/boards.dox b/Documentation/boards.dox
index 3eb79b2..fa0f284 100644
--- a/Documentation/boards.dox
+++ b/Documentation/boards.dox
@@ -8,18 +8,23 @@
ARM type:
+
@li @subpage pcm037
@li @subpage pcm038
@li @subpage pcm043
@li @subpage imx21ads
@li @subpage imx27ads
@li @subpage the3stack
+@li @subpage mx23_evk
+@li @subpage board_babage
+@li @subpage chumbyone
@li @subpage scb9328
@li @subpage netx
@li @subpage dev_omap_arch
@li @subpage a9m2440
@li @subpage a9m2410
@li @subpage eukrea_cpuimx27
+@li @subpage eukrea_cpuimx35
@li @subpage edb9301
@li @subpage edb9302
@li @subpage edb9302a
@@ -28,6 +33,7 @@
@li @subpage edb9312
@li @subpage edb9315
@li @subpage edb9315a
+@li @subpage board_cupid
Blackfin type:
diff --git a/Documentation/building.dox b/Documentation/building.dox
new file mode 100644
index 0000000..527ca45
--- /dev/null
+++ b/Documentation/building.dox
@@ -0,0 +1,60 @@
+/** @page building Building
+
+This section describes how to build the Barebox bootloader.
+
+@a Barebox uses Kconfig/Kbuild from the Linux kernel to build it's
+sources. It consists of two parts: the makefile infrastructure (kbuild)
+and a configuration system (kconfig). So building @a barebox is very
+similar to building the Linux kernel.
+
+In the examples below we use the "sandbox" configuration, which is a
+port of @a Barebox to the Linux userspace. This makes it possible to
+test the code without having real hardware or even qemu. Note that the
+sandbox architecture does only work well on x86 and has some issues on
+x86_64.
+
+\todo Find out about issues on x86_64.
+
+Selecting the architecture and the corresponding cross compiler is done
+by setting the following environment variables:
+
+- ARCH=\
+- CROSS_COMPILE=\
+
+For @p ARCH=sandbox we do not need a cross compiler, so it is sufficient
+to specify the architecture:
+
+@code
+# export ARCH=sandbox
+@endcode
+
+In order to configure the various aspects of @a barebox, start the
+@a barebox configuration system:
+
+@code
+# make menuconfig
+@endcode
+
+This command starts a menu box and lets you select all the different
+options available for the selected architecture. Once the configuration
+is finished (you can simulate this by using the default config file with
+'make sandbox_defconfig'), there is a .config file in the toplevel
+directory of the sourcecode.
+
+After @a barebox is configured, we can start the compilation:
+
+@code
+# make
+@endcode
+
+You can use '-j \' in order to do a parallel build if you have more
+than one cpus.
+
+If everything goes well, the result is a file called @p barebox:
+
+@code
+# ls -l barebox
+-rwxr-xr-x 1 rsc ptx 114073 Jun 26 22:34 barebox
+@endcode
+
+*/
diff --git a/Documentation/commands.dox b/Documentation/commands.dox
index a8850b1..27eb511 100644
--- a/Documentation/commands.dox
+++ b/Documentation/commands.dox
@@ -1,24 +1,48 @@
/**
- * @page command_reference Supported Shell Commands
+ * @page command_reference Shell Commands
+
+This section describes the commands which are available on the @a
+Barebox shell.
+
+@a Barebox, as a bootloader, usually shall start the Linux kernel right
+away. However, there are several use cases around which make it
+necessary to have some (customizable) logic and interactive scripting
+possibilities. In order to achieve this, @a Barebox offers several
+commands on it's integrated commandline shell.
+
+The following alphabetically sorted list documents all commands
+available in @a Barebox:
+
+\todo Sort this by functionality?
@li @subpage addpart_command
+@li @subpage bmp_command
+@li @subpage bootm_command
@li @subpage cat_command
@li @subpage cd_command
+@li @subpage clear_command
@li @subpage cp_command
+@li @subpage crc_command
@li @subpage delpart_command
@li @subpage devinfo_command
+@li @subpage dfu_command
+@li @subpage echo_command
@li @subpage edit_command
@li @subpage erase_command
@li @subpage export_command
+@li @subpage gpio_get_value_command
+@li @subpage gpio_set_value_command
+@li @subpage gpio_direction_input_command
+@li @subpage gpio_direction_output_command
@li @subpage tftp_command
@li @subpage loadenv_command
+@li @subpage ls_command
@li @subpage mount_command
@li @subpage printenv_command
@li @subpage protect_command
-@li @subpage rarp_command
@li @subpage saveenv_command
@li @subpage setenv_command
-@li @subpage sh_command
@li @subpage unprotect_command
@li @subpage linux16_command
+
*/
diff --git a/Documentation/developers_manual.dox b/Documentation/developers_manual.dox
index 620905e..2f7d360 100644
--- a/Documentation/developers_manual.dox
+++ b/Documentation/developers_manual.dox
@@ -20,6 +20,5 @@
@li @subpage barebox_simul
@li @subpage io_access_functions
@li @subpage mcfv4e_MCDlib
-@li @subpage x86_runtime
*/
diff --git a/Documentation/first_steps.dox b/Documentation/first_steps.dox
new file mode 100644
index 0000000..edc612f
--- /dev/null
+++ b/Documentation/first_steps.dox
@@ -0,0 +1,61 @@
+/** @page first_steps First Steps
+
+This section demonstrates the first steps with the 'sandbox'
+platform.
+
+@a barebox usually needs an environment for storing it's configuration.
+You can generate an environment using the example-environment contained
+in arch/sanbox/board/env:
+
+@code
+# ./scripts/bareboxenv -s -p 0x10000 arch/sanbox/board/env/ env.bin
+@endcode
+
+To get some files to play with you can generate a cramfs image:
+
+@code
+# mkcramfs somedir/ cramfs.bin
+@endcode
+
+The @a barebox image is a normal Linux executable, so it can be started
+just like every other program:
+
+@code
+# ./barebox -e env.bin -i cramfs.bin
+
+barebox 2010.10.0 (Oct 29 2010 - 13:47:17)
+
+loading environment from /dev/env0
+barebox\> /
+@endcode
+
+Specifying -[ie] \ tells @a barebox to map the file as a device
+under @p /dev. Files given with '-e' will appear as @p /dev/env[n]. Files
+given with '-i' will appear as @p /dev/fd[n].
+
+If @a barebox finds a valid configuration sector on @p /dev/env0, it
+will be loaded into @p /env and executes @p /env/init if existing.
+The default environment from the example above will show up a menu
+asking for the relevant settings.
+
+If you have started @a barebox as root you will find a new tap device on
+your host which you can configure using ifconfig. Once configured with
+valid network addresses, barebox can be used to ping the host machine or
+to fetch files with tftp.
+
+\todo Add more about tun/tap configuration
+
+If you have mapped a cramfs image, try mounting it with
+
+@code
+# mkdir /cram
+# mount /dev/fd0 cramfs /cram
+@endcode
+
+Memory can be examined using @p md/mw commands. They both understand the
+-f \ option to tell the commands that they should work on the
+specified files instead of @p /dev/mem (which holds the complete address
+space). Note that if you call 'md /dev/fd0' (without -f), @a barebox will
+segfault on the host, because it will interpret @p /dev/fd0 as a number.
+
+*/
diff --git a/Documentation/users_manual.dox b/Documentation/users_manual.dox
index cd2b99c..ea47b18 100644
--- a/Documentation/users_manual.dox
+++ b/Documentation/users_manual.dox
@@ -1,15 +1,17 @@
/** @page users_manual User's Manual
-Who should read this part?
+This manual provides help for working with @a Barebox from the user's
+point of view. So if you want to use @a Barebox for booting your target,
+you find a lot of nice tricks on these pages to make your life easier.
-Mostly everyone. The user needs it to find help for his daily work to manage
-his targets. The developer to find out all the new features that make his
-work easier.
+@li @subpage building
+@li @subpage first_steps
+@li @subpage command_reference
+@li @subpage gpio_for_users
+\todo Rework the following sections
@li @subpage shell_notes
@li @subpage readline_parser
-@li @subpage command_reference
-@li @subpage partitions
@li @subpage x86_bootloader
@li @subpage net_netconsole
diff --git a/Doxyfile b/Doxyfile
index 40bcb2f..d9ce22c 100644
--- a/Doxyfile
+++ b/Doxyfile
@@ -424,7 +424,7 @@
# The QUIET tag can be used to turn on/off the messages that are generated
# by doxygen. Possible values are YES and NO. If left blank NO is used.
-QUIET = NO
+QUIET = YES
# The WARNINGS tag can be used to turn on/off the warning messages that are
# generated by doxygen. Possible values are YES and NO. If left blank
@@ -483,7 +483,6 @@
drivers \
commands \
common \
- board \
lib \
scripts/setupmbr \
net
@@ -504,6 +503,7 @@
FILE_PATTERNS = *.c \
*.h \
+ *.S \
*.dox
# The RECURSIVE tag can be used to turn specify whether or not subdirectories
@@ -516,7 +516,9 @@
# excluded from the INPUT source files. This way you can easily exclude a
# subdirectory from a directory tree whose root is specified with the INPUT tag.
-EXCLUDE =
+EXCLUDE = drivers/mtd/ubi \
+ include/mtd \
+ include/linux/mtd
# The EXCLUDE_SYMLINKS tag can be used select whether or not files or
# directories that are symbolic links (a Unix filesystem feature) are excluded
@@ -543,7 +545,7 @@
# directories that contain example code fragments that are included (see
# the \include command).
-EXAMPLE_PATH = Documentation/examples/
+EXAMPLE_PATH =
# If the value of the EXAMPLE_PATH tag contains directories, you can use the
# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
@@ -563,7 +565,7 @@
# directories that contain image that are included in the documentation (see
# the \image command).
-IMAGE_PATH = Documentation/images/
+IMAGE_PATH =
# The INPUT_FILTER tag can be used to specify a program that doxygen should
# invoke to filter for each input file. Doxygen will invoke the filter program
@@ -573,7 +575,7 @@
# to standard output. If FILTER_PATTERNS is specified, this tag will be
# ignored.
-INPUT_FILTER =
+INPUT_FILTER = "awk -f scripts/doxy_filter.awk"
# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
# basis. Doxygen will compare the file name with each pattern and apply the
@@ -1065,7 +1067,10 @@
# undefined via #undef or recursively expanded use the := operator
# instead of the = operator.
-PREDEFINED = DOXYGEN_SHOULD_SKIP_THIS
+PREDEFINED = \
+ DOXYGEN_SHOULD_SKIP_THIS \
+ CONFIG_CMD_DEVINFO \
+ CONFIG_NET_TFTP_PUSH
# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
# this tag can be used to specify a list of macro names that should be expanded.
@@ -1209,7 +1214,7 @@
# So in most cases it will be better to enable call graphs for selected
# functions only using the \callgraph command.
-CALL_GRAPH = YES
+CALL_GRAPH = NO
# If the CALLER_GRAPH, SOURCE_BROWSER and HAVE_DOT tags are set to YES then doxygen will
# generate a caller dependency graph for every global function or class method.
@@ -1217,19 +1222,19 @@
# So in most cases it will be better to enable caller graphs for selected
# functions only using the \callergraph command.
-CALLER_GRAPH = YES
+CALLER_GRAPH = NO
# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
# will graphical hierarchy of all classes instead of a textual one.
-GRAPHICAL_HIERARCHY = YES
+GRAPHICAL_HIERARCHY = NO
# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES
# then doxygen will show the dependencies a directory has on other directories
# in a graphical way. The dependency relations are determined by the #include
# relations between the files in the directories.
-DIRECTORY_GRAPH = YES
+DIRECTORY_GRAPH = NO
# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
# generated by dot. Possible values are png, jpg, or gif
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fa37036..8cb86cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -39,6 +39,10 @@
bool "Freescale iMX-based"
select GENERIC_GPIO
+config ARCH_STM
+ bool "SigmaTel/FSL iMX-based"
+ select GENERIC_GPIO
+
config ARCH_NETX
bool "Hilscher NetX based"
select CPU_ARM926T
@@ -55,6 +59,7 @@
config ARCH_S3C24xx
bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
select CPU_ARM920T
+ select GENERIC_GPIO
endchoice
@@ -62,6 +67,7 @@
source arch/arm/mach-at91/Kconfig
source arch/arm/mach-ep93xx/Kconfig
source arch/arm/mach-imx/Kconfig
+source arch/arm/mach-stm/Kconfig
source arch/arm/mach-netx/Kconfig
source arch/arm/mach-nomadik/Kconfig
source arch/arm/mach-omap/Kconfig
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 77b6cf4..cdb0185 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -41,6 +41,7 @@
machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_IMX) := imx
+machine-$(CONFIG_ARCH_STM) := stm
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_OMAP) := omap
@@ -80,6 +81,10 @@
board-$(CONFIG_MACH_PM9263) := pm9263
board-$(CONFIG_MACH_SCB9328) := scb9328
board-$(CONFIG_MACH_NESO) := guf-neso
+board-$(CONFIG_MACH_MX23EVK) := freescale-mx23-evk
+board-$(CONFIG_MACH_CHUMBY) := chumby_falconwing
+board-$(CONFIG_MACH_FREESCALE_MX51_PDK) := freescale-mx51-pdk
+board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
diff --git a/arch/arm/boards/chumby_falconwing/Makefile b/arch/arm/boards/chumby_falconwing/Makefile
new file mode 100644
index 0000000..0bc79d9
--- /dev/null
+++ b/arch/arm/boards/chumby_falconwing/Makefile
@@ -0,0 +1 @@
+obj-y = falconwing.o
diff --git a/arch/arm/boards/chumby_falconwing/config.h b/arch/arm/boards/chumby_falconwing/config.h
new file mode 100644
index 0000000..87d9e2f
--- /dev/null
+++ b/arch/arm/boards/chumby_falconwing/config.h
@@ -0,0 +1,21 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CONFIG_H_
+# define _CONFIG_H_
+
+#endif /* _CONFIG_H_ */
diff --git a/arch/arm/boards/chumby_falconwing/env/bin/boot b/arch/arm/boards/chumby_falconwing/env/bin/boot
new file mode 100644
index 0000000..981a387
--- /dev/null
+++ b/arch/arm/boards/chumby_falconwing/env/bin/boot
@@ -0,0 +1,38 @@
+#!/bin/sh
+
+. /env/config
+
+if [ x$1 = xdisk ]; then
+ rootfs_loc=disk
+ kernel_loc=disk
+elif [ x$1 = xnet ]; then
+ rootfs_loc=net
+ kernel_loc=net
+fi
+
+if [ x$ip = xdhcp ]; then
+ bootargs="$bootargs ip=dhcp"
+elif [ x$ip = xnone ]; then
+ bootargs="$bootargs ip=none"
+else
+ bootargs="$bootargs ip=$eth0.ipaddr::$eth0.gateway:$eth0.netmask:::"
+fi
+
+if [ x$rootfs_loc = xdisk ]; then
+ bootargs="$bootargs noinitrd rootfstype=$rootfs_type root=/dev/$rootfs_part"
+elif [ x$rootfs_loc = xnet ]; then
+ bootargs="$bootargs root=/dev/nfs nfsroot=$nfsroot,v3,tcp noinitrd"
+elif [ x$rootfs_loc = xinitrd ]; then
+ bootargs="$bootargs root=/dev/ram0 rdinit=/sbin/init"
+fi
+
+if [ x$kernelimage_type = xuimage ]; then
+ bootm /dev/$kernel_part
+elif [ x$kernelimage_type = xzimage ]; then
+ bootz /dev/$kernel_part
+else
+ echo "Booting failed. Correct setup of 'kernelimage_type'?"
+ exit
+fi
+
+echo "Booting failed. Correct setup of 'kernel_part'?"
diff --git a/arch/arm/boards/chumby_falconwing/env/bin/init b/arch/arm/boards/chumby_falconwing/env/bin/init
new file mode 100644
index 0000000..3ed68f7
--- /dev/null
+++ b/arch/arm/boards/chumby_falconwing/env/bin/init
@@ -0,0 +1,15 @@
+#!/bin/sh
+
+PATH=/env/bin
+export PATH
+
+. /env/config
+
+echo
+echo -n "Hit any key to stop autoboot: "
+timeout -a $autoboot_timeout
+if [ $? != 0 ]; then
+ exit
+fi
+
+boot
diff --git a/arch/arm/boards/chumby_falconwing/env/config b/arch/arm/boards/chumby_falconwing/env/config
new file mode 100644
index 0000000..1e61dce
--- /dev/null
+++ b/arch/arm/boards/chumby_falconwing/env/config
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+machine=falconwing
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=none
+
+# or set your networking parameters here (if a USB network adapter is attached)
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'net' or 'disk'
+kernel_loc=disk
+# can be either 'net', or 'disk' or 'initrd'
+rootfs_loc=disk
+
+# can be any regular filesystem like ext2, ext3, reiserfs in case of 'rootfs_loc=disk'
+rootfs_type=ext2
+# Where is the rootfs in case of 'rootfs_loc=disk'
+rootfs_part=mmcblk0p4
+
+# Where is the rootfs in case of 'rootfs_loc=net'
+nfsroot=FIXME
+
+# The image type of the kernel. Can be uimage, zimage
+kernelimage_type=uimage
+# Where to get the kernel image in case of 'kernel_loc=disk'
+kernel_part=disk0.2
+
+# base kernel parameter
+bootargs="console=ttyAM0,115200 debug ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1"
+
+autoboot_timeout=2
diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c
new file mode 100644
index 0000000..952a384
--- /dev/null
+++ b/arch/arm/boards/chumby_falconwing/falconwing.c
@@ -0,0 +1,350 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct memory_platform_data ram_pdata = {
+ .name = "ram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+ .name = "mem",
+ .map_base = IMX_MEMORY_BASE,
+ .size = 64 * 1024 * 1024,
+ .platform_data = &ram_pdata,
+};
+
+static struct stm_mci_platform_data mci_pdata = {
+ .caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz,
+ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, /* fixed to 3.3 V */
+};
+
+static struct device_d mci_dev = {
+ .name = "stm_mci",
+ .map_base = IMX_SSP1_BASE,
+ .platform_data = &mci_pdata,
+};
+
+static const uint32_t pad_setup[] = {
+ /* may be not required as already done by the bootlet code */
+#if 0
+ /* SDRAM data signals */
+ EMI_D15 | STRENGTH(0) | VE_2_5V,
+ EMI_D14 | STRENGTH(0) | VE_2_5V,
+ EMI_D13 | STRENGTH(0) | VE_2_5V,
+ EMI_D12 | STRENGTH(0) | VE_2_5V,
+ EMI_D11 | STRENGTH(0) | VE_2_5V,
+ EMI_D10 | STRENGTH(0) | VE_2_5V,
+ EMI_D9 | STRENGTH(0) | VE_2_5V,
+ EMI_D8 | STRENGTH(0) | VE_2_5V,
+ EMI_D7 | STRENGTH(0) | VE_2_5V,
+ EMI_D6 | STRENGTH(0) | VE_2_5V,
+ EMI_D5 | STRENGTH(0) | VE_2_5V,
+ EMI_D4 | STRENGTH(0) | VE_2_5V,
+ EMI_D3 | STRENGTH(0) | VE_2_5V,
+ EMI_D2 | STRENGTH(0) | VE_2_5V,
+ EMI_D1 | STRENGTH(0) | VE_2_5V,
+ EMI_D0 | STRENGTH(0) | VE_2_5V,
+
+ /* SDRAM data control signals */
+ EMI_DQM0 | STRENGTH(0) | VE_2_5V, /* LDM */
+ EMI_DQM1 | STRENGTH(0) | VE_2_5V, /* UDM */
+
+ /* SDRAM address signals */
+ EMI_A0 | STRENGTH(0) | VE_2_5V,
+ EMI_A1 | STRENGTH(0) | VE_2_5V,
+ EMI_A2 | STRENGTH(0) | VE_2_5V,
+ EMI_A3 | STRENGTH(0) | VE_2_5V,
+ EMI_A4 | STRENGTH(0) | VE_2_5V,
+ EMI_A5 | STRENGTH(0) | VE_2_5V,
+ EMI_A6 | STRENGTH(0) | VE_2_5V,
+ EMI_A7 | STRENGTH(0) | VE_2_5V,
+ EMI_A8 | STRENGTH(0) | VE_2_5V,
+ EMI_A9 | STRENGTH(0) | VE_2_5V,
+ EMI_A10 | STRENGTH(0) | VE_2_5V,
+ EMI_A11 | STRENGTH(0) | VE_2_5V,
+ EMI_A12 | STRENGTH(0) | VE_2_5V,
+
+ /* SDRAM address control signals */
+ EMI_RASN | STRENGTH(0) | VE_2_5V,
+ EMI_CASN | STRENGTH(0) | VE_2_5V,
+
+ /* SDRAM control signals */
+ EMI_CE0N | STRENGTH(0) | VE_2_5V,
+ EMI_CLK | STRENGTH(0) | VE_2_5V,
+ EMI_CLKN | STRENGTH(0) | VE_2_5V,
+ EMI_CKE | STRENGTH(0) | VE_2_5V,
+ EMI_WEN | STRENGTH(0) | VE_2_5V,
+ EMI_BA0 | STRENGTH(0) | VE_2_5V,
+ EMI_BA1 | STRENGTH(0) | VE_2_5V,
+ EMI_DQS0 | STRENGTH(0) | VE_2_5V,
+ EMI_DQS1 | STRENGTH(0) | VE_2_5V,
+#endif
+ /* debug port */
+ PWM1_DUART_TX | STRENGTH(S4MA), /* strength is TBD */
+ PWM0_DUART_RX | STRENGTH(S4MA), /* strength is TBD */
+
+ /* lcd */
+ LCD_VSYNC, /* kernel tries with 12 mA for all LCD related pins */
+ LCD_HSYNC,
+ LCD_ENABE,
+ LCD_DOTCLOCK,
+ LCD_D17,
+ LCD_D16,
+ LCD_D15,
+ LCD_D14,
+ LCD_D13,
+ LCD_D12,
+ LCD_D11,
+ LCD_D10,
+ LCD_D9,
+ LCD_D8,
+ LCD_D7,
+ LCD_D6,
+ LCD_D5,
+ LCD_D4,
+ LCD_D3,
+ LCD_D2,
+ LCD_D1,
+ LCD_D0,
+
+ /* LCD usage currently unknown */
+ LCD_CS, /* used as SPI SS */
+ LCD_RS, /* used as SPI CLK */
+ LCD_RESET,
+ LCD_WR, /* used as SPI MOSI */
+
+ /* I2C to the MMA7455L, KXTE9, AT24C08 (DCID), AT24C128B (ID EEPROM) and QN8005B */
+ I2C_SDA,
+ I2C_CLK,
+
+ /* Rotary decoder (external pull ups) */
+ ROTARYA,
+ ROTARYB,
+
+ /* the chumby bend (external pull up) */
+ PWM4_GPIO | GPIO_IN,
+
+ /* backlight control, to be controled by PWM, here we only want to disable it */
+ PWM2_GPIO | GPIO_OUT | GPIO_VALUE(0), /* 1 enables, 0 disables the backlight */
+
+ /* send a reset signal to the USB hub */
+ AUART1_TX_GPIO | GPIO_OUT | GPIO_VALUE(0),
+
+ /* USB power disable (FIXME what level to be switched off) */
+ AUART1_CTS_GPIO | GPIO_OUT | GPIO_VALUE(0),
+
+ /* Detecting if a display is connected (0 = display attached) (external pull up) */
+ AUART1_RTS_GPIO | GPIO_IN,
+
+ /* disable the audio amplifier */
+ GPMI_D08_GPIO | GPIO_OUT | GPIO_VALUE(0),
+
+ /* Head Phone detection (FIXME what level when plugged in) (external pull up) */
+ GPMI_D11_GPIO | GPIO_IN,
+
+#if 0
+ /* Enable the local 5V (FIXME what to do when the bootloader runs) */
+ GPMI_D12_GPIO | GPIO_OUT | GPIO_VALUE(1),
+#endif
+
+ /* not used pins */
+ GPMI_D09_GPIO | GPIO_IN | PULLUP(1),
+ GPMI_D10_GPIO | GPIO_IN | PULLUP(1),
+ GPMI_D13_GPIO | GPIO_IN | PULLUP(1),
+
+ /* unknown. Not connected to anything than test pin J113 */
+ GPMI_D14_GPIO | GPIO_IN | PULLUP(1),
+
+ /* unknown. Not connected to anything than test pin J114 */
+ GPMI_D15_GPIO | GPIO_IN | PULLUP(1),
+
+ /* NAND controller (Note: There is no NAND device on the board) */
+ GPMI_D00 | PULLUP(1),
+ GPMI_D01 | PULLUP(1),
+ GPMI_D02 | PULLUP(1),
+ GPMI_D03 | PULLUP(1),
+ GPMI_D04 | PULLUP(1),
+ GPMI_D05 | PULLUP(1),
+ GPMI_D06 | PULLUP(1),
+ GPMI_D07 | PULLUP(1),
+ GPMI_CE0N,
+ GPMI_RDY0 | PULLUP(1),
+ GPMI_WRN, /* kernel tries here with 12 mA */
+ GPMI_RDN, /* kernel tries here with 12 mA */
+ GPMI_WPM, /* kernel tries here with 12 mA */
+ GPMI_CLE,
+ GPMI_ALE,
+
+ /* SD card interface */
+ SSP1_DATA0 | PULLUP(1), /* available at J201 */
+ SSP1_DATA1 | PULLUP(1), /* available at J200 */
+ SSP1_DATA2 | PULLUP(1), /* available at J205 */
+ SSP1_DATA3 | PULLUP(1), /* available at J204 */
+ SSP1_SCK, /* available at J202 */
+ SSP1_CMD | PULLUP(1), /* available at J203 */
+ SSP1_DETECT | PULLUP(1), /* only connected to test pin J115 */
+
+ /* other not used pins */
+ GPMI_CE1N_GPIO | GPIO_IN | PULLUP(1),
+ GPMI_CE2N_GPIO | GPIO_IN | PULLUP(1),
+ GPMI_RDY1_GPIO | GPIO_IN | PULLUP(1),
+ GPMI_RDY2_GPIO | GPIO_IN | PULLUP(1),
+ GPMI_RDY3_GPIO | GPIO_IN | PULLUP(1),
+};
+
+/**
+ * Try to register an environment storage on the attached MCI card
+ * @return 0 on success
+ *
+ * We relay on the existance of a useable SD card, already attached to
+ * our system, to get someting like a persistant memory for our environment.
+ * If this SD card is also the boot media, we can use the second partition
+ * for our environment purpose (if present!).
+ */
+static int register_persistant_environment(void)
+{
+ struct cdev *cdev;
+
+ /*
+ * The chumby one only has one MCI card socket.
+ * So, we expect its name as "disk0".
+ */
+ cdev = cdev_by_name("disk0");
+ if (cdev == NULL) {
+ pr_err("No MCI card preset\n");
+ return -ENODEV;
+ }
+
+ /* MCI card is present, also a useable partition on it? */
+ cdev = cdev_by_name("disk0.1");
+ if (cdev == NULL) {
+ pr_err("No second partition available\n");
+ pr_info("Please create at least a second partition with"
+ " 256 kiB...512 kiB in size (your choice)\n");
+ return -ENODEV;
+ }
+
+ /* use the full partition as our persistant environment storage */
+ return devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0");
+}
+
+static int falconwing_devices_init(void)
+{
+ int i, rc;
+
+ /* initizalize gpios */
+ for (i = 0; i < ARRAY_SIZE(pad_setup); i++)
+ imx_gpio_mode(pad_setup[i]);
+
+ register_device(&sdram_dev);
+ imx_set_ioclk(480U * 1000U); /* enable IOCLK to run at the PLL frequency */
+ /* run the SSP unit clock at 100,000 kHz */
+ imx_set_sspclk(0, 100U * 1000U, 1);
+ register_device(&mci_dev);
+
+ armlinux_add_dram(&sdram_dev);
+ armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100));
+ armlinux_set_architecture(MACH_TYPE_CHUMBY);
+
+ rc = register_persistant_environment();
+ if (rc != 0)
+ printf("Cannot create the 'env0' persistant environment storage (%d)\n", rc);
+
+ return 0;
+}
+
+device_initcall(falconwing_devices_init);
+
+static struct device_d falconwing_serial_device = {
+ .name = "stm_serial",
+ .map_base = IMX_DBGUART_BASE,
+ .size = 8192,
+};
+
+static int falconwing_console_init(void)
+{
+ return register_device(&falconwing_serial_device);
+}
+
+console_initcall(falconwing_console_init);
+
+/** @page chumbyone Chumby Industrie's Falconwing
+
+This device is also known as "chumby one" (http://www.chumby.com/)
+
+This CPU card is based on a Freescale i.MX23 CPU. The card is shipped with:
+
+- 64 MiB synchronous dynamic RAM (DDR type)
+
+Memory layout when @b barebox is running:
+
+- 0x40000000 start of SDRAM
+- 0x40000100 start of kernel's boot parameters
+ - below malloc area: stack area
+ - below barebox: malloc area
+- 0x42000000 start of @b barebox
+
+@section get_falconwing_binary How to get the bootloader binary image:
+
+Using the default configuration:
+
+@verbatim
+make ARCH=arm chumbyone_defconfig
+@endverbatim
+
+Build the bootloader binary image:
+
+@verbatim
+make ARCH=arm CROSS_COMPILE=armv5compiler
+@endverbatim
+
+@note replace the armv5compiler with your ARM v5 cross compiler.
+
+@section setup_falconwing How to prepare an MCI card to boot the "chumby one" with barebox
+
+- Create four primary partitions on the MCI card
+ - the first one for the bootlets (about 256 kiB)
+ - the second one for the persistant environment (size is up to you, at least 256k)
+ - the third one for the kernel (2 MiB ... 4 MiB in size)
+ - the 4th one for the root filesystem which can fill the rest of the available space
+
+- Mark the first partition with the partition ID "53" and copy the bootlets
+ into this partition (currently not part of @b barebox!).
+
+- Copy the default @b barebox environment into the second partition (no filesystem required).
+
+- Copy the kernel into the third partition (no filesystem required).
+
+- Create the root filesystem in the 4th partition. You may copy an image into this
+ partition or you can do it in the classic way: mkfs on it, mount it and copy
+ all required data and programs into it.
+
+*/
diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/init b/arch/arm/boards/eukrea_cpuimx25/env/bin/init
index 335d7ae..4732875 100644
--- a/arch/arm/boards/eukrea_cpuimx25/env/bin/init
+++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/init
@@ -14,9 +14,11 @@
if [ -f /env/logo.bmp ]; then
bmp /env/logo.bmp
+ fb0.enable=1
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
bmp /logo.bmp
+ fb0.enable=1
fi
if [ -z $eth0.ethaddr ]; then
diff --git a/arch/arm/boards/eukrea_cpuimx25/env/config b/arch/arm/boards/eukrea_cpuimx25/env/config
index 9217ca1..3e41ec8 100644
--- a/arch/arm/boards/eukrea_cpuimx25/env/config
+++ b/arch/arm/boards/eukrea_cpuimx25/env/config
@@ -13,7 +13,7 @@
nfsroot=""
bootargs="console=ttymxc0,115200"
-nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)"
+nand_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)"
rootpartnum_nand=3
ubiroot="eukrea-cpuimx25-rootfs"
diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
index 7fd1031..805ffe2 100644
--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
+++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c
@@ -40,6 +40,9 @@
#include
#include
#include
+#include
+#include
+#include
extern unsigned long _stext;
extern void exception_vectors(void);
@@ -151,6 +154,60 @@
.platform_data = &eukrea_cpuimx25_fb_data,
};
+static struct device_d i2c_dev = {
+ .id = -1,
+ .name = "i2c-imx",
+ .map_base = IMX_I2C1_BASE,
+};
+
+static struct device_d esdhc_dev = {
+ .name = "imx-esdhc",
+ .map_base = 0x53fb4000,
+};
+
+#ifdef CONFIG_USB
+static void imx25_usb_init(void)
+{
+ unsigned int tmp;
+
+ /* Host 1 */
+ tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+ tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
+ tmp |= MX35_H1_USBTE_BIT;
+ tmp |= MX35_H1_IPPUE_DOWN_BIT;
+ writel(tmp, IMX_OTG_BASE + 0x600);
+
+ tmp = readl(IMX_OTG_BASE + 0x584);
+ tmp |= 3 << 30;
+ writel(tmp, IMX_OTG_BASE + 0x584);
+
+ /* Set to Host mode */
+ tmp = readl(IMX_OTG_BASE + 0x5a8);
+ writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+}
+
+static struct device_d usbh2_dev = {
+ .id = -1,
+ .name = "ehci",
+ .map_base = IMX_OTG_BASE + 0x400,
+ .size = 0x200,
+};
+#endif
+
+static struct fsl_usb2_platform_data usb_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
+static struct device_d usbotg_dev = {
+ .name = "fsl-udc",
+ .map_base = IMX_OTG_BASE,
+ .size = 0x200,
+ .platform_data = &usb_pdata,
+};
+
#ifdef CONFIG_MMU
static void eukrea_cpuimx25_mmu_init(void)
{
@@ -209,6 +266,16 @@
MX25_PAD_HSYNC__LCDC_HSYN,
/* BACKLIGHT CONTROL */
MX25_PAD_PWM__GPIO26,
+ /* I2C */
+ MX25_PAD_I2C1_CLK__SCL,
+ MX25_PAD_I2C1_DAT__SDA,
+ /* SDCard */
+ MX25_PAD_SD1_CLK__CLK,
+ MX25_PAD_SD1_CMD__CMD,
+ MX25_PAD_SD1_DATA0__DAT0,
+ MX25_PAD_SD1_DATA1__DAT1,
+ MX25_PAD_SD1_DATA2__DAT2,
+ MX25_PAD_SD1_DATA3__DAT3,
};
static int eukrea_cpuimx25_devices_init(void)
@@ -217,6 +284,7 @@
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
ARRAY_SIZE(eukrea_cpuimx25_pads));
+
register_device(&fec_dev);
nand_info.width = 1;
@@ -238,6 +306,15 @@
register_device(&imxfb_dev);
+ register_device(&i2c_dev);
+ register_device(&esdhc_dev);
+
+#ifdef CONFIG_USB
+ imx25_usb_init();
+ register_device(&usbh2_dev);
+#endif
+ register_device(&usbotg_dev);
+
armlinux_add_dram(&sdram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25);
@@ -256,7 +333,6 @@
static int eukrea_cpuimx25_console_init(void)
{
- writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3);
register_device(&eukrea_cpuimx25_serial_device);
return 0;
}
@@ -270,10 +346,17 @@
}
#endif
-static int eukrea_cpuimx25_core_setup(void)
-{
- writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2);
- return 0;
+static int eukrea_cpuimx25_core_init(void) {
+ /* enable UART1, FEC, SDHC, USB & I2C clock */
+ writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 6) | (1 << 23)
+ | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28),
+ IMX_CCM_BASE + CCM_CGCR0);
+ writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 23) | (1 << 15)
+ | (1 << 13), IMX_CCM_BASE + CCM_CGCR1);
+ writel(readl(IMX_CCM_BASE + CCM_CGCR2) | (1 << 14),
+ IMX_CCM_BASE + CCM_CGCR2);
+ return 0;
}
-core_initcall(eukrea_cpuimx25_core_setup);
+
+core_initcall(eukrea_cpuimx25_core_init);
diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
index b9d3ce5..4ebf247 100644
--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c
@@ -26,13 +26,13 @@
#include
#include
#include
-#include
#include
#include
#include
#include
#include
+#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
uint32_t r;
@@ -45,17 +45,32 @@
board_init_lowlevel_return();
}
-
-#define MX25_CCM_MCR 0x64
-#define MX25_CCM_CGR0 0x0c
-#define MX25_CCM_CGR1 0x10
-#define MX25_CCM_CGR2 0x14
+#endif
void __bare_init __naked board_init_lowlevel(void)
{
uint32_t r;
+#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
+#endif
+ register uint32_t loops = 0x20000;
+
+ /* restart the MPLL and wait until it's stable */
+ writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),
+ IMX_CCM_BASE + CCM_CCTL);
+ while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};
+
+ /* Configure dividers and ARM clock source
+ * ARM @ 400 MHz
+ * AHB @ 133 MHz
+ */
+ writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);
+
+ /* Enable UART1 / FEC / */
+/* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0);
+ writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1);
+ writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -102,23 +117,46 @@
*/
writel(0x1, 0xb8003000);
- /* enable all the clocks */
- writel(0x038A81A2, IMX_CCM_BASE + MX25_CCM_CGR0);
- writel(0x24788F00, IMX_CCM_BASE + MX25_CCM_CGR1);
- writel(0x00004438, IMX_CCM_BASE + MX25_CCM_CGR2);
- writel(0x00, IMX_CCM_BASE + MX25_CCM_MCR);
+ /* Speed up NAND controller by adjusting the NFC divider */
+ r = readl(IMX_CCM_BASE + CCM_PCDR2);
+ r &= ~0xf;
+ r |= 0x1;
+ writel(r, IMX_CCM_BASE + CCM_PCDR2);
+
+ /* Skip SDRAM initialization if we run from RAM */
+ r = get_pc();
+ if (r > 0x80000000 && r < 0x90000000)
+ board_init_lowlevel_return();
+
+ /* Init Mobile DDR */
+ writel(0x0000000E, ESDMISC);
+ writel(0x00000004, ESDMISC);
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+
+ writel(0x0029572B, ESDCFG0);
+ writel(0x92210000, ESDCTL0);
+ writeb(0xda, IMX_SDRAM_CS0 + 0x400);
+ writel(0xA2210000, ESDCTL0);
+ writeb(0xda, IMX_SDRAM_CS0);
+ writeb(0xda, IMX_SDRAM_CS0);
+ writel(0xB2210000, ESDCTL0);
+ writeb(0xda, IMX_SDRAM_CS0 + 0x33);
+ writeb(0xda, IMX_SDRAM_CS0 + 0x1000000);
+ writel(0x82216080, ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000)
+ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
/* Move ourselves out of NFC SRAM */
- for (i = 0; i < 0x1000 / sizeof(int); i++)
+ for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot
index 7272e56..0e1c80a 100644
--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot
+++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot
@@ -27,12 +27,14 @@
bootargs="$bootargs ip=off"
fi
-if [ x$root = xnand ]; then
- bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
-elif [ x$root = xnor ]; then
- bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+if [ x$rootfstype = xubifs ]; then
+ bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum rootfstype=ubifs"
else
- bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+ if [ x$root = xnand ]; then
+ bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
+ elif [ x$root = xnor ]; then
+ bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
+ fi
fi
bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts"
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/init b/arch/arm/boards/eukrea_cpuimx27/env/bin/init
index 3bfd194..aefd67c 100644
--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/init
+++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/init
@@ -16,11 +16,21 @@
source /env/bin/hush_hack
fi
+if [ -f /env/logo.bmp ]; then
+ bmp /env/logo.bmp
+ fb0.enable=1
+elif [ -f /env/logo.bmp.lzo ]; then
+ unlzo /env/logo.bmp.lzo /logo.bmp
+ bmp /logo.bmp
+ fb0.enable=1
+fi
+
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
done
echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+ saveenv
fi
echo
diff --git a/arch/arm/boards/eukrea_cpuimx27/env/config b/arch/arm/boards/eukrea_cpuimx27/env/config
index 505ada3..7f56003 100644
--- a/arch/arm/boards/eukrea_cpuimx27/env/config
+++ b/arch/arm/boards/eukrea_cpuimx27/env/config
@@ -3,9 +3,11 @@
# can be either 'net', 'nor' or 'nand''
kernel=nor
root=nor
+rootfstype=ubifs
-uimage=mx27/uImage
-jffs2=mx27/rootfs.jffs2
+basedir=cpuimx27
+uimage=$basedir/uImage
+rootfs=$basedir/rootfs
autoboot_timeout=1
@@ -13,12 +15,15 @@
video="CMO-QVGA"
bootargs="console=ttymxc0,115200 fec_mac=$eth0.ethaddr video=mxcfb:$video"
-nor_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)"
+nor_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)"
rootpart_nor="/dev/mtdblock3"
nand_parts="-(nand)"
rootpart_nand=""
+rootpartnum=3
+ubiroot="eukrea-cpuimx27-rootfs"
+
nfsroot=""
# use 'dhcp' to do dhcp in barebox and in kernel
diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
index 4d1797b..62fc14e 100644
--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
+++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c
@@ -44,7 +44,7 @@
#include
#include
#include
-#include
+#include
#include
static struct device_d cfi_dev = {
@@ -275,6 +275,7 @@
PA29_PF_VSYNC,
PA31_PF_OE_ACD,
GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT,
+ GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT,
#endif
};
@@ -311,6 +312,8 @@
register_device(&imxfb_dev);
gpio_direction_output(GPIO_PORTE | 5, 0);
gpio_set_value(GPIO_PORTE | 5, 1);
+ gpio_direction_output(GPIO_PORTA | 25, 0);
+ gpio_set_value(GPIO_PORTA | 25, 1);
#endif
armlinux_add_dram(&sdram_dev);
diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/init b/arch/arm/boards/eukrea_cpuimx35/env/bin/init
index 90007cd..b56d7b5 100644
--- a/arch/arm/boards/eukrea_cpuimx35/env/bin/init
+++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/init
@@ -15,12 +15,12 @@
if [ -f /env/logo.bmp ]; then
fb0.enable=1
bmp /env/logo.bmp
- gpio_direction_out 1 1
+ gpio_set_value 1 1
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
fb0.enable=1
bmp /logo.bmp
- gpio_direction_out 1 1
+ gpio_set_value 1 1
fi
if [ -z $eth0.ethaddr ]; then
diff --git a/arch/arm/boards/eukrea_cpuimx35/env/config b/arch/arm/boards/eukrea_cpuimx35/env/config
index df2079f..fc99e51 100644
--- a/arch/arm/boards/eukrea_cpuimx35/env/config
+++ b/arch/arm/boards/eukrea_cpuimx35/env/config
@@ -13,7 +13,7 @@
nfsroot=""
bootargs="console=ttymxc0,115200"
-nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)"
+nand_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)"
rootpartnum_nand=3
ubiroot="eukrea-cpuimx35-rootfs"
diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
index 63d019a..dfe64d0 100644
--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
+++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c
@@ -51,6 +51,9 @@
#include
#include
#include
+#include
+#include
+#include
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
@@ -126,6 +129,60 @@
.platform_data = &ipu_fb_data,
};
+static struct device_d i2c_dev = {
+ .id = -1,
+ .name = "i2c-imx",
+ .map_base = IMX_I2C1_BASE,
+};
+
+static struct device_d esdhc_dev = {
+ .name = "imx-esdhc",
+ .map_base = IMX_SDHC1_BASE,
+};
+
+#ifdef CONFIG_USB
+static void imx35_usb_init(void)
+{
+ unsigned int tmp;
+
+ /* Host 1 */
+ tmp = readl(IMX_OTG_BASE + 0x600);
+ tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+ tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
+ tmp |= MX35_H1_USBTE_BIT;
+ tmp |= MX35_H1_IPPUE_DOWN_BIT;
+ writel(tmp, IMX_OTG_BASE + 0x600);
+
+ tmp = readl(IMX_OTG_BASE + 0x584);
+ tmp |= 3 << 30;
+ writel(tmp, IMX_OTG_BASE + 0x584);
+
+ /* Set to Host mode */
+ tmp = readl(IMX_OTG_BASE + 0x5a8);
+ writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
+}
+
+static struct device_d usbh2_dev = {
+ .id = -1,
+ .name = "ehci",
+ .map_base = IMX_OTG_BASE + 0x400,
+ .size = 0x200,
+};
+#endif
+
+static struct fsl_usb2_platform_data usb_pdata = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
+static struct device_d usbotg_dev = {
+ .name = "fsl-udc",
+ .map_base = IMX_OTG_BASE,
+ .size = 0x200,
+ .platform_data = &usb_pdata,
+};
+
#ifdef CONFIG_MMU
static int eukrea_cpuimx35_mmu_init(void)
{
@@ -153,6 +210,8 @@
static int eukrea_cpuimx35_devices_init(void)
{
+ unsigned int tmp;
+
register_device(&nand_dev);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
@@ -165,6 +224,18 @@
register_device(&sdram_dev);
register_device(&imxfb_dev);
+ register_device(&i2c_dev);
+ register_device(&esdhc_dev);
+
+#ifdef CONFIG_USB
+ imx35_usb_init();
+ register_device(&usbh2_dev);
+#endif
+ /* Workaround ENGcm09152 */
+ tmp = readl(IMX_OTG_BASE + 0x608);
+ writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608);
+ register_device(&usbotg_dev);
+
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
@@ -211,6 +282,16 @@
MX35_PAD_LD23__GPIO3_29,
MX35_PAD_CONTRAST__GPIO1_1,
MX35_PAD_D3_CLS__GPIO1_4,
+
+ MX35_PAD_I2C1_CLK__I2C1_SCL,
+ MX35_PAD_I2C1_DAT__I2C1_SDA,
+
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
};
static int eukrea_cpuimx35_console_init(void)
@@ -219,7 +300,7 @@
ARRAY_SIZE(eukrea_cpuimx35_pads));
/* screen default on to prevent flicker */
- gpio_direction_output(4, 1);
+ gpio_direction_output(4, 0);
/* backlight default off */
gpio_direction_output(1, 0);
/* led default off */
@@ -235,10 +316,15 @@
{
u32 reg;
- /* enable clock for I2C1 and FEC */
+ /* enable clock for I2C1, SDHC1, USB and FEC */
reg = readl(IMX_CCM_BASE + CCM_CGR1);
reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
+ reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT;
+ reg |= 0x3 << CCM_CGR1_I2C1_SHIFT,
reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
+ reg = readl(IMX_CCM_BASE + CCM_CGR2);
+ reg |= 0x3 << CCM_CGR2_USB_SHIFT;
+ reg = writel(reg, IMX_CCM_BASE + CCM_CGR2);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
index 285a2d4..5a77c3a 100644
--- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c
+++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c
@@ -12,30 +12,30 @@
struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
{ .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, },
- { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, },
- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x0009572B, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
+ { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0009572B, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92220000, },
{ .ptr_type = 1, .addr = 0x80000400, .val = 0xda, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
- { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
- { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2220000, },
+ { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
+ { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2220000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
- { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82224080, },
- { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82224080, },
+ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, },
};
-
+#define CPUIMX35_DEST_BASE 0x80000000
struct imx_flash_header __flash_header_section flash_header = {
- .app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE),
+ .app_code_jump_vector = CPUIMX35_DEST_BASE + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker),
- .app_dest = DEST_BASE,
+ .app_dest = CPUIMX35_DEST_BASE,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof(dcd_entry),
};
diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
index aad334d..6c0e106 100644
--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
+++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c
@@ -66,6 +66,7 @@
unsigned int *trg, *src;
int i;
#endif
+ register uint32_t loops = 0x20000;
r = get_cr();
r |= CR_Z; /* Flow prediction (Z) */
@@ -118,7 +119,7 @@
writel(r, ccm_base + CCM_CGR0);
r = readl(ccm_base + CCM_CGR1);
- r |= 0x00000C00;
+ r |= 0x00030C00;
r |= 0x00000003;
writel(r, ccm_base + CCM_CGR1);
@@ -132,31 +133,34 @@
board_init_lowlevel_return();
/* Init Mobile DDR */
+ writel(0x0000000E, ESDMISC);
writel(0x00000004, ESDMISC);
- writel(0x0000000C, ESDMISC);
+ __asm__ volatile ("1:\n"
+ "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0" (loops));
+
writel(0x0009572B, ESDCFG0);
writel(0x92220000, ESDCTL0);
writeb(0xda, IMX_SDRAM_CS0 + 0x400);
writel(0xA2220000, ESDCTL0);
- writel(0x87654321, IMX_SDRAM_CS0);
- writel(0x87654321, IMX_SDRAM_CS0);
+ writeb(0xda, IMX_SDRAM_CS0);
+ writeb(0xda, IMX_SDRAM_CS0);
writel(0xB2220000, ESDCTL0);
writeb(0xda, IMX_SDRAM_CS0 + 0x33);
writeb(0xda, IMX_SDRAM_CS0 + 0x2000000);
- writel(0x82224080, ESDCTL0);
- writel(0x00000004, ESDMISC);
+ writel(0x82228080, ESDCTL0);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000)
+ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
/* Move ourselves out of NFC SRAM */
- for (i = 0; i < 0x1000 / sizeof(int); i++)
+ for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
diff --git a/arch/arm/boards/freescale-mx23-evk/Makefile b/arch/arm/boards/freescale-mx23-evk/Makefile
new file mode 100644
index 0000000..cffb561
--- /dev/null
+++ b/arch/arm/boards/freescale-mx23-evk/Makefile
@@ -0,0 +1,2 @@
+#
+obj-y := mx23-evk.o
diff --git a/arch/arm/boards/freescale-mx23-evk/config.h b/arch/arm/boards/freescale-mx23-evk/config.h
new file mode 100644
index 0000000..4b3da8f
--- /dev/null
+++ b/arch/arm/boards/freescale-mx23-evk/config.h
@@ -0,0 +1,16 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
new file mode 100644
index 0000000..1ce72be
--- /dev/null
+++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct memory_platform_data ram_pdata = {
+ .name = "ram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+ .name = "mem",
+ .map_base = IMX_MEMORY_BASE,
+ .size = 32 * 1024 * 1024,
+ .platform_data = &ram_pdata,
+};
+
+static int mx23_evk_devices_init(void)
+{
+ register_device(&sdram_dev);
+
+ armlinux_add_dram(&sdram_dev);
+ armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100));
+ armlinux_set_architecture(MACH_TYPE_MX23EVK);
+
+ return 0;
+}
+
+device_initcall(mx23_evk_devices_init);
+
+static struct device_d mx23_evk_serial_device = {
+ .name = "stm_serial",
+ .map_base = IMX_DBGUART_BASE,
+ .size = 8192,
+};
+
+static int mx23_evk_console_init(void)
+{
+ return register_device(&mx23_evk_serial_device);
+}
+
+console_initcall(mx23_evk_console_init);
+
+/** @page mx23_evk Freescale's i.MX23 evaluation kit
+
+This CPU card is based on an i.MX23 CPU. The card is shipped with:
+
+- 32 MiB synchronous dynamic RAM (mobile DDR type)
+- ENC28j60 based network (over SPI)
+
+Memory layout when @b barebox is running:
+
+- 0x40000000 start of SDRAM
+- 0x40000100 start of kernel's boot parameters
+ - below malloc area: stack area
+ - below barebox: malloc area
+- 0x41000000 start of @b barebox
+
+@section get_imx23evk_binary How to get the bootloader binary image:
+
+Using the default configuration:
+
+@verbatim
+make ARCH=arm imx23evk_defconfig
+@endverbatim
+
+Build the bootloader binary image:
+
+@verbatim
+make ARCH=arm CROSS_COMPILE=armv5compiler
+@endverbatim
+
+@note replace the armv5compiler with your ARM v5 cross compiler.
+*/
diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
index 70de7958..25945f1 100644
--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c
@@ -39,7 +39,7 @@
#include
#include
#include
-#include
+#include
extern unsigned long _stext;
extern void exception_vectors(void);
diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
index 71aaa92..d6699cd 100644
--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c
+++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c
@@ -50,8 +50,8 @@
#include
#include
-#include
-#include
+#include
+#include
/* Board rev for the PDK 3stack */
@@ -111,7 +111,7 @@
static struct i2c_board_info i2c_devices[] = {
{
- I2C_BOARD_INFO("mc13892", 0x08),
+ I2C_BOARD_INFO("mc13892-i2c", 0x08),
}, {
I2C_BOARD_INFO("mc9sdz60", 0x69),
},
diff --git a/arch/arm/boards/freescale-mx51-pdk/Makefile b/arch/arm/boards/freescale-mx51-pdk/Makefile
new file mode 100644
index 0000000..8e0c87c
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/Makefile
@@ -0,0 +1,3 @@
+obj-y += lowlevel_init.o
+obj-y += board.o
+obj-y += flash_header.o
diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c
new file mode 100644
index 0000000..5197c55
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/board.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct memory_platform_data ram_pdata = {
+ .name = "ram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+ .id = -1,
+ .name = "mem",
+ .map_base = 0x90000000,
+ .size = 512 * 1024 * 1024,
+ .platform_data = &ram_pdata,
+};
+
+static struct fec_platform_data fec_info = {
+ .xcv_type = MII100,
+};
+
+static struct device_d fec_dev = {
+ .name = "fec_imx",
+ .map_base = 0x83fec000,
+ .platform_data = &fec_info,
+};
+
+static struct device_d esdhc_dev = {
+ .name = "imx-esdhc",
+ .map_base = 0x70004000,
+};
+
+static struct pad_desc f3s_pads[] = {
+ MX51_PAD_EIM_EB2__FEC_MDIO,
+ MX51_PAD_EIM_EB3__FEC_RDATA1,
+ MX51_PAD_EIM_CS2__FEC_RDATA2,
+ MX51_PAD_EIM_CS3__FEC_RDATA3,
+ MX51_PAD_EIM_CS4__FEC_RX_ER,
+ MX51_PAD_EIM_CS5__FEC_CRS,
+ MX51_PAD_NANDF_RB2__FEC_COL,
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK,
+ MX51_PAD_NANDF_RB7__FEC_TX_ER,
+ MX51_PAD_NANDF_CS3__FEC_MDC,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3,
+ MX51_PAD_NANDF_CS7__FEC_TX_EN,
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
+ MX51_PAD_NANDF_D11__FEC_RX_DV,
+ MX51_PAD_NANDF_RB6__FEC_RDATA0,
+ MX51_PAD_NANDF_D8__FEC_TDATA0,
+ MX51_PAD_CSPI1_SS0__CSPI1_SS0,
+ MX51_PAD_CSPI1_MOSI__CSPI1_MOSI,
+ MX51_PAD_CSPI1_MISO__CSPI1_MISO,
+ MX51_PAD_CSPI1_RDY__CSPI1_RDY,
+ MX51_PAD_CSPI1_SCLK__CSPI1_SCLK,
+ MX51_PAD_EIM_A20__GPIO2_14, /* LAN8700 reset pin */
+ IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, 0x85), /* FIXME: needed? */
+};
+
+#ifdef CONFIG_MMU
+static void babbage_mmu_init(void)
+{
+ mmu_init();
+
+ arm_create_section(0x90000000, 0x90000000, 512, PMD_SECT_DEF_CACHED);
+ arm_create_section(0xb0000000, 0x90000000, 512, PMD_SECT_DEF_UNCACHED);
+
+ setup_dma_coherent(0x20000000);
+
+#if TEXT_BASE & (0x100000 - 1)
+#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
+#else
+ arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
+#endif
+
+ mmu_enable();
+}
+#else
+static void babbage_mmu_init(void)
+{
+}
+#endif
+
+//extern int babbage_power_init(void);
+
+#define BABBAGE_ECSPI1_CS0 (3 * 32 + 24)
+static int spi_0_cs[] = {BABBAGE_ECSPI1_CS0};
+
+static struct spi_imx_master spi_0_data = {
+ .chipselect = spi_0_cs,
+ .num_chipselect = ARRAY_SIZE(spi_0_cs),
+};
+
+static struct device_d spi_dev = {
+ .id = -1,
+ .name = "imx_spi",
+ .map_base = MX51_CSPI1_BASE_ADDR,
+ .platform_data = &spi_0_data,
+};
+
+static const struct spi_board_info mx51_babbage_spi_board_info[] = {
+ {
+ .name = "mc13892-spi",
+ .max_speed_hz = 300000,
+ .bus_num = 0,
+ .chip_select = 0,
+ },
+};
+
+#define MX51_CCM_CACRR 0x10
+
+static void babbage_power_init(void)
+{
+ struct mc13892 *mc13892;
+ u32 val;
+
+ mc13892 = mc13892_get();
+ if (!mc13892) {
+ printf("could not get mc13892\n");
+ return;
+ }
+
+ /* Write needed to Power Gate 2 register */
+ mc13892_reg_read(mc13892, 34, &val);
+ val &= ~0x10000;
+ mc13892_reg_write(mc13892, 34, val);
+
+ /* Write needed to update Charger 0 */
+ mc13892_reg_write(mc13892, 48, 0x0023807F);
+
+ /* power up the system first */
+ mc13892_reg_write(mc13892, 34, 0x00200000);
+
+ if (imx_silicon_revision() < MX51_CHIP_REV_3_0) {
+ /* Set core voltage to 1.1V */
+ mc13892_reg_read(mc13892, 24, &val);
+ val &= ~0x1f;
+ val |= 0x14;
+ mc13892_reg_write(mc13892, 24, val);
+
+ /* Setup VCC (SW2) to 1.25 */
+ mc13892_reg_read(mc13892, 25, &val);
+ val &= ~0x1f;
+ val |= 0x1a;
+ mc13892_reg_write(mc13892, 25, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ mc13892_reg_read(mc13892, 26, &val);
+ val &= ~0x1f;
+ val |= 0x1a;
+ mc13892_reg_write(mc13892, 26, val);
+ udelay(50);
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, MX51_CCM_BASE_ADDR + MX51_CCM_CACRR);
+ } else {
+ /* Setup VCC (SW2) to 1.225 */
+ mc13892_reg_read(mc13892, 25, &val);
+ val &= ~0x1f;
+ val |= 0x19;
+ mc13892_reg_write(mc13892, 25, val);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.2 */
+ mc13892_reg_read(mc13892, 26, &val);
+ val &= ~0x1f;
+ val |= 0x18;
+ mc13892_reg_write(mc13892, 26, val);
+ }
+
+ if (mc13892_get_revision(mc13892) < MC13892_REVISION_2_0) {
+ /* Set switchers in PWM mode for Atlas 2.0 and lower */
+ /* Setup the switcher mode for SW1 & SW2*/
+ mc13892_reg_read(mc13892, 28, &val);
+ val &= ~0x3c0f;
+ val |= 0x1405;
+ mc13892_reg_write(mc13892, 28, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ mc13892_reg_read(mc13892, 29, &val);
+ val &= ~0xf0f;
+ val |= 0x505;
+ mc13892_reg_write(mc13892, 29, val);
+ } else {
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+ /* Setup the switcher mode for SW1 & SW2*/
+ mc13892_reg_read(mc13892, 28, &val);
+ val &= ~0x3c0f;
+ val |= 0x2008;
+ mc13892_reg_write(mc13892, 28, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ mc13892_reg_read(mc13892, 29, &val);
+ val &= ~0xf0f;
+ val |= 0x808;
+ mc13892_reg_write(mc13892, 29, val);
+ }
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
+ mc13892_reg_read(mc13892, 30, &val);
+ val &= ~0x34030;
+ val |= 0x10020;
+ mc13892_reg_write(mc13892, 30, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ mc13892_reg_read(mc13892, 31, &val);
+ val &= ~0x1FC;
+ val |= 0x1F4;
+ mc13892_reg_write(mc13892, 31, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = 0x208;
+ mc13892_reg_write(mc13892, 33, val);
+ udelay(200);
+#define GPIO_LAN8700_RESET (1 * 32 + 14)
+
+ /* Reset the ethernet controller over GPIO */
+ gpio_direction_output(GPIO_LAN8700_RESET, 0);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = 0x49249;
+ mc13892_reg_write(mc13892, 33, val);
+
+ udelay(500);
+
+ gpio_set_value(GPIO_LAN8700_RESET, 1);
+}
+
+static int f3s_devices_init(void)
+{
+ babbage_mmu_init();
+
+ register_device(&sdram_dev);
+ register_device(&fec_dev);
+ register_device(&esdhc_dev);
+
+ spi_register_board_info(mx51_babbage_spi_board_info,
+ ARRAY_SIZE(mx51_babbage_spi_board_info));
+ register_device(&spi_dev);
+
+ babbage_power_init();
+
+ armlinux_add_dram(&sdram_dev);
+ armlinux_set_bootparams((void *)0x90000100);
+ armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
+
+ return 0;
+}
+
+device_initcall(f3s_devices_init);
+
+static int f3s_part_init(void)
+{
+ devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
+ devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
+
+ return 0;
+}
+late_initcall(f3s_part_init);
+
+static struct device_d f3s_serial_device = {
+ .name = "imx_serial",
+ .map_base = 0x73fbc000,
+ .size = 4096,
+};
+
+static int f3s_console_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
+
+ writel(0, 0x73fa8228);
+ writel(0, 0x73fa822c);
+ writel(0, 0x73fa8230);
+ writel(0, 0x73fa8234);
+
+ register_device(&f3s_serial_device);
+ return 0;
+}
+
+console_initcall(f3s_console_init);
+
diff --git a/arch/arm/boards/freescale-mx51-pdk/config.h b/arch/arm/boards/freescale-mx51-pdk/config.h
new file mode 100644
index 0000000..b7effe5
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/config.h
@@ -0,0 +1,24 @@
+/**
+ * @file
+ * @brief Global defintions for the ARM i.MX51 based babbage board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif /* __CONFIG_H */
diff --git a/arch/arm/boards/freescale-mx51-pdk/env/config b/arch/arm/boards/freescale-mx51-pdk/env/config
new file mode 100644
index 0000000..d9b8407
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/env/config
@@ -0,0 +1,52 @@
+#!/bin/sh
+
+machine=babbage
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'net', 'nor' or 'nand'
+kernel_loc=net
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$machine.$rootfs_type
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-$machine
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+ kernelimage="$user"-"$kernelimage"
+ nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+ rootfsimage="$user"-"$rootfsimage"
+else
+ nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttymxc0,115200"
+
+disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)"
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/freescale-mx51-pdk/flash_header.c b/arch/arm/boards/freescale-mx51-pdk/flash_header.c
new file mode 100644
index 0000000..5f94506
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/flash_header.c
@@ -0,0 +1,85 @@
+#include
+#include
+
+extern unsigned long _stext;
+
+void __naked __flash_header_start go(void)
+{
+ __asm__ __volatile__("b exception_vectors\n");
+}
+
+struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
+ { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, },
+ { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, },
+ { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, },
+ { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, },
+ { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, },
+ { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, },
+ { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, },
+ { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, },
+ { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, },
+ { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, },
+ { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, },
+ { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, },
+ { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, },
+ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, },
+ { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, },
+ { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, },
+ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, },
+ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, },
+ { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, },
+ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
+};
+
+#define APP_DEST 0x90000000
+
+struct imx_flash_header __flash_header_section flash_header = {
+ .app_code_jump_vector = APP_DEST + 0x1000,
+ .app_code_barker = APP_CODE_BARKER,
+ .app_code_csf = 0,
+ .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
+ .super_root_key = 0,
+ .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
+ .app_dest = APP_DEST,
+ .dcd_barker = DCD_BARKER,
+ .dcd_block_len = sizeof (dcd_entry),
+};
+
+unsigned long __image_len_section barebox_len = 0x40000;
+
diff --git a/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S b/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
new file mode 100644
index 0000000..793104c
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S
@@ -0,0 +1,216 @@
+/*
+ * This code is based on the ecos babbage startup code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+
+#define ROM_SI_REV_OFFSET 0x48
+
+.macro setup_pll pll, freq
+ ldr r2, =\pll
+ ldr r1, =0x00001232
+ str r1, [r2, #MX51_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r2, #MX51_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ str r3, [r2, #MX51_PLL_DP_OP]
+ str r3, [r2, #MX51_PLL_DP_HFS_OP]
+
+ str r4, [r2, #MX51_PLL_DP_MFD]
+ str r4, [r2, #MX51_PLL_DP_HFS_MFD]
+
+ str r5, [r2, #MX51_PLL_DP_MFN]
+ str r5, [r2, #MX51_PLL_DP_HFS_MFN]
+
+ ldr r1, =0x00001232
+ str r1, [r2, #MX51_PLL_DP_CTL]
+1: ldr r1, [r2, #MX51_PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+.endm
+
+#define writel(val, reg) \
+ ldr r0, =reg; \
+ ldr r1, =val; \
+ str r1, [r0];
+
+#define IMX51_TO_2
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+ mov r10, lr
+
+ /* explicitly disable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ /* reconfigure L2 cache aux control reg */
+ mov r0, #0xC0 /* tag RAM */
+ add r0, r0, #0x4 /* data RAM */
+ orr r0, r0, #(1 << 24) /* disable write allocate delay */
+ orr r0, r0, #(1 << 23) /* disable write allocate combine */
+ orr r0, r0, #(1 << 22) /* disable write allocate */
+
+ ldr r1, =MX51_IROM_BASE_ADDR
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x10
+ orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */
+
+ mcr 15, 1, r0, c9, c0, 2
+
+ ldr r0, =MX51_CCM_BASE_ADDR
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #MX51_CCM_CCGR0]
+ ldr r1, =0x0
+ str r1, [r0, #MX51_CCM_CCGR1]
+ str r1, [r0, #MX51_CCM_CCGR2]
+ str r1, [r0, #MX51_CCM_CCGR3]
+
+ ldr r1, =0x00030000
+ str r1, [r0, #MX51_CCM_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #MX51_CCM_CCGR5]
+ ldr r1, =0x00000300
+ str r1, [r0, #MX51_CCM_CCGR6]
+
+ /* Disable IPU and HSC dividers */
+ mov r1, #0x60000
+ str r1, [r0, #MX51_CCM_CCDR]
+
+#ifdef IMX51_TO_2
+ /* Make sure to switch the DDR away from PLL 1 */
+ ldr r1, =0x19239145
+ str r1, [r0, #MX51_CCM_CBCDR]
+ /* make sure divider effective */
+1: ldr r1, [r0, #MX51_CCM_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+#endif
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #MX51_CCM_CCSR]
+
+ mov r3, #MX51_PLL_DP_OP_800
+ mov r4, #MX51_PLL_DP_MFD_800
+ mov r5, #MX51_PLL_DP_MFN_800
+ setup_pll MX51_PLL1_BASE_ADDR
+
+ mov r3, #MX51_PLL_DP_OP_665
+ mov r4, #MX51_PLL_DP_MFD_665
+ mov r5, #MX51_PLL_DP_MFN_665
+ setup_pll MX51_PLL3_BASE_ADDR
+
+ /* Switch peripheral to PLL 3 */
+ ldr r1, =0x000010C0
+ str r1, [r0, #MX51_CCM_CBCMR]
+ ldr r1, =0x13239145
+ str r1, [r0, #MX51_CCM_CBCDR]
+
+ mov r3, #MX51_PLL_DP_OP_665
+ mov r4, #MX51_PLL_DP_MFD_665
+ mov r5, #MX51_PLL_DP_MFN_665
+ setup_pll MX51_PLL2_BASE_ADDR
+
+ /* Switch peripheral to PLL2 */
+ ldr r1, =0x19239145
+ str r1, [r0, #MX51_CCM_CBCDR]
+ ldr r1, =0x000020C0
+ str r1, [r0, #MX51_CCM_CBCMR]
+
+ mov r3, #MX51_PLL_DP_OP_216
+ mov r4, #MX51_PLL_DP_MFD_216
+ mov r5, #MX51_PLL_DP_MFN_216
+ setup_pll MX51_PLL3_BASE_ADDR
+
+ /* Set the platform clock dividers */
+ ldr r2, =MX51_ARM_BASE_ADDR
+ ldr r1, =0x00000124
+ str r1, [r2, #0x14]
+
+ /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+ ldr r1, =MX51_IROM_BASE_ADDR
+ ldr r3, [r1, #ROM_SI_REV_OFFSET]
+ cmp r3, #0x10
+ movls r1, #0x1
+ movhi r1, #0
+ str r1, [r0, #MX51_CCM_CACRR]
+
+ /* Switch ARM back to PLL 1 */
+ mov r1, #0
+ str r1, [r0, #MX51_CCM_CCSR]
+
+ /* setup the rest */
+ /* Use lp_apm (24MHz) source for perclk */
+#ifdef IMX51_TO_2
+ ldr r1, =0x000020C2
+ str r1, [r0, #MX51_CCM_CBCMR]
+ // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
+ ldr r1, =0x59239100
+ str r1, [r0, #MX51_CCM_CBCDR]
+#else
+ ldr r1, =0x0000E3C2
+ str r1, [r0, #MX51_CCM_CBCMR]
+ // emi=ahb, all perclk dividers are 1 since using 24MHz
+ // DDR divider=6 to have 665/6=110MHz
+ ldr r1, =0x013B9100
+ str r1, [r0, #MX51_CCM_CBCDR]
+#endif
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #MX51_CCM_CCGR0]
+ str r1, [r0, #MX51_CCM_CCGR1]
+ str r1, [r0, #MX51_CCM_CCGR2]
+ str r1, [r0, #MX51_CCM_CCGR3]
+ str r1, [r0, #MX51_CCM_CCGR4]
+ str r1, [r0, #MX51_CCM_CCGR5]
+ str r1, [r0, #MX51_CCM_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, =0xA5A2A020
+ str r1, [r0, #MX51_CCM_CSCMR1]
+ ldr r1, =0x00C30321
+ str r1, [r0, #MX51_CCM_CSCDR1]
+
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #MX51_CCM_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r1, #0x0
+ str r1, [r0, #MX51_CCM_CCDR]
+
+ writel(0x1, 0x73fa8074)
+ ldr r0, =0x73f88000
+ ldr r1, [r0]
+ orr r1, #0x40
+ str r1, [r0]
+
+ ldr r0, =0x73f88004
+ ldr r1, [r0]
+ orr r1, #0x40
+ str r1, [r0]
+
+ mov pc, r10
+
diff --git a/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox b/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox
new file mode 100644
index 0000000..d9ea823
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox
@@ -0,0 +1,4 @@
+/** @page board_babage Freescale i.MX51 PDK (Babbage) Board
+
+
+*/
diff --git a/arch/arm/boards/freescale-mx51-pdk/spi.c b/arch/arm/boards/freescale-mx51-pdk/spi.c
new file mode 100644
index 0000000..8eabe81
--- /dev/null
+++ b/arch/arm/boards/freescale-mx51-pdk/spi.c
@@ -0,0 +1,340 @@
+#include
+#include
+#include
+#include
+#include
+
+#define IMX_SPI_ACTIVE_HIGH 1
+#define SPI_RETRY_TIMES 100
+#define CLKCTL_CACRR 0x10
+#define REV_ATLAS_LITE_2_0 0x10
+
+/* Only for SPI master support */
+struct imx_spi_dev {
+ unsigned int base; // base address of SPI module the device is connected to
+ unsigned int freq; // desired clock freq in Hz for this device
+ unsigned int ss_pol; // ss polarity: 1=active high; 0=active low
+ unsigned int ss; // slave select
+ unsigned int in_sctl; // inactive sclk ctl: 1=stay low; 0=stay high
+ unsigned int in_dctl; // inactive data ctl: 1=stay low; 0=stay high
+ unsigned int ssctl; // single burst mode vs multiple: 0=single; 1=multi
+ unsigned int sclkpol; // sclk polarity: active high=0; active low=1
+ unsigned int sclkpha; // sclk phase: 0=phase 0; 1=phase1
+ unsigned int fifo_sz; // fifo size in bytes for either tx or rx. Don't add them up!
+ unsigned int ctrl_reg;
+ unsigned int cfg_reg;
+};
+
+struct imx_spi_dev imx_spi_pmic = {
+ .base = MX51_CSPI1_BASE_ADDR,
+ .freq = 25000000,
+ .ss_pol = IMX_SPI_ACTIVE_HIGH,
+ .ss = 0, /* slave select 0 */
+ .fifo_sz = 32,
+};
+
+/*
+ * Initialization function for a spi slave device. It must be called BEFORE
+ * any spi operations. The SPI module will be -disabled- after this call.
+ */
+static int imx_spi_init(struct imx_spi_dev *dev)
+{
+ unsigned int clk_src = 66500000;
+ unsigned int pre_div = 0, post_div = 0, i, reg_ctrl = 0, reg_config = 0;
+
+ if (dev->freq == 0) {
+ printf("Error: desired clock is 0\n");
+ return -1;
+ }
+
+ /* control register setup */
+ if (clk_src > dev->freq) {
+ pre_div = clk_src / dev->freq;
+ if (pre_div > 16) {
+ post_div = pre_div / 16;
+ pre_div = 15;
+ }
+ if (post_div != 0) {
+ for (i = 0; i < 16; i++) {
+ if ((1 << i) >= post_div)
+ break;
+ }
+ if (i == 16) {
+ printf
+ ("Error: no divider can meet the freq: %d\n",
+ dev->freq);
+ return -1;
+ }
+ post_div = i;
+ }
+ }
+ debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
+ reg_ctrl |= pre_div << 12;
+ reg_ctrl |= post_div << 8;
+ reg_ctrl |= 1 << (dev->ss + 4); /* always set to master mode */
+
+ /* configuration register setup */
+ reg_config |= dev->ss_pol << (dev->ss + 12);
+ reg_config |= dev->in_sctl << (dev->ss + 20);
+ reg_config |= dev->in_dctl << (dev->ss + 16);
+ reg_config |= dev->ssctl << (dev->ss + 8);
+ reg_config |= dev->sclkpol << (dev->ss + 4);
+ reg_config |= dev->sclkpha << (dev->ss + 0);
+
+ debug("reg_ctrl = 0x%x\n", reg_ctrl);
+ /* reset the spi */
+ writel(0, dev->base + 0x8);
+ writel(reg_ctrl, dev->base + 0x8);
+ debug("reg_config = 0x%x\n", reg_config);
+ writel(reg_config, dev->base + 0xC);
+ /* save control register */
+ dev->cfg_reg = reg_config;
+ dev->ctrl_reg = reg_ctrl;
+
+ /* clear interrupt reg */
+ writel(0, dev->base + 0x10);
+ writel(3 << 6, dev->base + 0x18);
+
+ return 0;
+}
+
+static int imx_spi_xfer(struct imx_spi_dev *dev, /* spi device pointer */
+ void *tx_buf, /* tx buffer (has to be 4-byte aligned) */
+ void *rx_buf, /* rx buffer (has to be 4-byte aligned) */
+ int burst_bits /* total number of bits in one burst (or xfer) */
+ )
+{
+ int val = SPI_RETRY_TIMES;
+ unsigned int *p_buf;
+ unsigned int reg;
+ int len, ret_val = 0;
+ int burst_bytes = burst_bits / 8;
+
+ /* Account for rounding of non-byte aligned burst sizes */
+ if ((burst_bits % 8) != 0)
+ burst_bytes++;
+
+ if (burst_bytes > dev->fifo_sz) {
+ printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n",
+ dev->fifo_sz, burst_bytes);
+ return -1;
+ }
+
+ dev->ctrl_reg = (dev->ctrl_reg & ~0xFFF00000) | ((burst_bits - 1) << 20);
+ writel(dev->ctrl_reg | 0x1, dev->base + 0x8);
+ writel(dev->cfg_reg, dev->base + 0xC);
+ debug("ctrl_reg=0x%x, cfg_reg=0x%x\n",
+ readl(dev->base + 0x8), readl(dev->base + 0xC));
+
+ /* move data to the tx fifo */
+ len = burst_bytes;
+ for (p_buf = tx_buf; len > 0; p_buf++, len -= 4)
+ writel(*p_buf, dev->base + 0x4);
+
+ reg = readl(dev->base + 0x8);
+ reg |= (1 << 2); /* set xch bit */
+ writel(reg, dev->base + 0x8);
+
+ /* poll on the TC bit (transfer complete) */
+ while ((val-- > 0) && (readl(dev->base + 0x18) & (1 << 7)) == 0);
+
+ /* clear the TC bit */
+ writel(3 << 6, dev->base + 0x18);
+
+ if (val == 0) {
+ printf("Error: re-tried %d times without response. Give up\n",
+ SPI_RETRY_TIMES);
+ ret_val = -1;
+ goto error;
+ }
+
+ /* move data in the rx buf */
+ len = burst_bytes;
+ for (p_buf = rx_buf; len > 0; p_buf++, len -= 4)
+ *p_buf = readl(dev->base + 0x0);
+
+error:
+ writel(0, dev->base + 0x8);
+ return ret_val;
+}
+
+/*
+ * To read/write to a PMIC register. For write, it does another read for the
+ * actual register value.
+ *
+ * @param reg register number inside the PMIC
+ * @param val data to be written to the register; don't care for read
+ * @param write 0 for read; 1 for write
+ *
+ * @return the actual data in the PMIC register
+ */
+static unsigned int
+pmic_reg(unsigned int reg, unsigned int val, unsigned int write)
+{
+ static unsigned int pmic_tx, pmic_rx;
+
+ if (reg > 63 || write > 1) {
+ printf(" = %d is invalid. Should be less then 63\n",
+ reg);
+ return 0;
+ }
+ pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
+ debug("reg=0x%x, val=0x%08x\n", reg, pmic_tx);
+
+ imx_spi_xfer(&imx_spi_pmic, (unsigned char *) &pmic_tx,
+ (unsigned char *) &pmic_rx, (4 * 8));
+
+ if (write) {
+ pmic_tx &= ~(1 << 31);
+ imx_spi_xfer(&imx_spi_pmic, (unsigned char *) &pmic_tx,
+ (unsigned char *) &pmic_rx, (4 * 8));
+ }
+
+ return pmic_rx;
+}
+
+static void show_pmic_info(void)
+{
+ unsigned int rev_id;
+ char *rev;
+
+ rev_id = pmic_reg(7, 0, 0);
+
+ switch (rev_id & 0x1F) {
+ case 0x1: rev = "1.0"; break;
+ case 0x9: rev = "1.1"; break;
+ case 0xa: rev = "1.2"; break;
+ case 0x10:
+ if (((rev_id >> 9) & 0x3) == 0)
+ rev = "2.0";
+ else
+ rev = "2.0a";
+ break;
+ case 0x11: rev = "2.1"; break;
+ case 0x18: rev = "3.0"; break;
+ case 0x19: rev = "3.1"; break;
+ case 0x1a: rev = "3.2"; break;
+ case 0x2: rev = "3.2a"; break;
+ case 0x1b: rev = "3.3"; break;
+ case 0x1d: rev = "3.5"; break;
+ default: rev = "unknown"; break;
+ }
+
+ printf("PMIC ID: 0x%08x [Rev: %s]\n", rev_id, rev);
+}
+
+int babbage_power_init(void)
+{
+ unsigned int val;
+ unsigned int reg;
+
+ imx_spi_init(&imx_spi_pmic);
+
+ show_pmic_info();
+
+ /* Write needed to Power Gate 2 register */
+ val = pmic_reg(34, 0, 0);
+ val &= ~0x10000;
+ pmic_reg(34, val, 1);
+
+ /* Write needed to update Charger 0 */
+ pmic_reg(48, 0x0023807F, 1);
+
+ /* power up the system first */
+ pmic_reg(34, 0x00200000, 1);
+
+ if (1) {
+ /* Set core voltage to 1.1V */
+ val = pmic_reg(24, 0, 0);
+ val &= ~0x1f;
+ val |= 0x14;
+ pmic_reg(24, val, 1);
+
+ /* Setup VCC (SW2) to 1.25 */
+ val = pmic_reg(25, 0, 0);
+ val &= ~0x1f;
+ val |= 0x1a;
+ pmic_reg(25, val, 1);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.25 */
+ val = pmic_reg(26, 0, 0);
+ val &= ~0x1f;
+ val |= 0x1a;
+ pmic_reg(26, val, 1);
+ udelay(50);
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, MX51_CCM_BASE_ADDR + CLKCTL_CACRR);
+ } else {
+ /* TO 3.0 */
+ /* Setup VCC (SW2) to 1.225 */
+ val = pmic_reg(25, 0, 0);
+ val &= ~0x1f;
+ val |= 0x19;
+ pmic_reg(25, val, 1);
+
+ /* Setup 1V2_DIG1 (SW3) to 1.2 */
+ val = pmic_reg(26, 0, 0);
+ val &= ~0x1f;
+ val |= 0x18;
+ pmic_reg(26, val, 1);
+ }
+
+ if (((pmic_reg(7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0)
+ || (((pmic_reg(7, 0, 0) >> 9) & 0x3) == 0)) {
+ /* Set switchers in PWM mode for Atlas 2.0 and lower */
+ /* Setup the switcher mode for SW1 & SW2 */
+ val = pmic_reg(28, 0, 0);
+ val &= ~0x3c0f;
+ val |= 0x1405;
+ pmic_reg(28, val, 1);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg(29, 0, 0);
+ val &= ~0xf0f;
+ val |= 0x505;
+ pmic_reg(29, val, 1);
+ } else {
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+ /* Setup the switcher mode for SW1 & SW2 */
+ val = pmic_reg(28, 0, 0);
+ val &= ~0x3c0f;
+ val |= 0x2008;
+ pmic_reg(28, val, 1);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ val = pmic_reg(29, 0, 0);
+ val &= ~0xf0f;
+ val |= 0x808;
+ pmic_reg(29, val, 1);
+ }
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
+ val = pmic_reg(30, 0, 0);
+ val &= ~0x34030;
+ val |= 0x10020;
+ pmic_reg(30, val, 1);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ val = pmic_reg(31, 0, 0);
+ val &= ~0x1FC;
+ val |= 0x1F4;
+ pmic_reg(31, val, 1);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = 0x208;
+ pmic_reg(33, val, 1);
+ udelay(200);
+
+ gpio_direction_output(32 + 14, 0); /* Lower reset line */
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = 0x49249;
+ pmic_reg(33, val, 1);
+
+ udelay(500);
+
+ gpio_set_value(32 + 14, 1);
+
+ return 0;
+}
+
diff --git a/arch/arm/boards/guf-cupid/Makefile b/arch/arm/boards/guf-cupid/Makefile
new file mode 100644
index 0000000..3a06cf4
--- /dev/null
+++ b/arch/arm/boards/guf-cupid/Makefile
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2007 Juergen Beisert
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+obj-y += lowlevel.o
+obj-y += board.o
diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c
new file mode 100644
index 0000000..6d7a99b
--- /dev/null
+++ b/arch/arm/boards/guf-cupid/board.c
@@ -0,0 +1,426 @@
+/*
+ * (C) 2007 Pengutronix, Sascha Hauer
+ * (C) 2009 Pengutronix, Juergen Beisert
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Board support for the Garz+Fricke Cupid board
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct fec_platform_data fec_info = {
+ .xcv_type = MII100,
+};
+
+static struct device_d fec_dev = {
+ .id = -1,
+ .name = "fec_imx",
+ .map_base = IMX_FEC_BASE,
+ .platform_data = &fec_info,
+};
+
+static struct memory_platform_data ram_pdata = {
+ .name = "ram0",
+ .flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram0_dev = {
+ .id = -1,
+ .name = "mem",
+ .map_base = IMX_SDRAM_CS0,
+ .size = 128 * 1024 * 1024,
+ .platform_data = &ram_pdata,
+};
+
+struct imx_nand_platform_data nand_info = {
+ .width = 1,
+ .hw_ecc = 1,
+ .flash_bbt = 1,
+};
+
+static struct device_d nand_dev = {
+ .id = -1,
+ .name = "imx_nand",
+ .map_base = IMX_NFC_BASE,
+ .platform_data = &nand_info,
+};
+
+static struct fb_videomode guf_cupid_fb_mode = {
+ /* 800x480 @ 70 Hz */
+ .name = "CPT CLAA070LC0JCT",
+ .refresh = 70,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 30761,
+ .left_margin = 24,
+ .right_margin = 47,
+ .upper_margin = 5,
+ .lower_margin = 3,
+ .hsync_len = 24,
+ .vsync_len = 3,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_CLK_INVERT |
+ FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+};
+
+#define GPIO_LCD_ENABLE (2 * 32 + 24)
+#define GPIO_LCD_BACKLIGHT (0 * 32 + 19)
+
+static void cupid_fb_enable(int enable)
+{
+ if (enable) {
+ gpio_direction_output(GPIO_LCD_ENABLE, 1);
+ mdelay(100);
+ gpio_direction_output(GPIO_LCD_BACKLIGHT, 1);
+ } else {
+ gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
+ mdelay(100);
+ gpio_direction_output(GPIO_LCD_ENABLE, 0);
+ }
+}
+
+static struct imx_ipu_fb_platform_data ipu_fb_data = {
+ .mode = &guf_cupid_fb_mode,
+ .bpp = 16,
+ .enable = cupid_fb_enable,
+};
+
+static struct device_d imx_ipu_fb_dev = {
+ .id = -1,
+ .name = "imx-ipu-fb",
+ .map_base = 0x53fc0000,
+ .size = 0x1000,
+ .platform_data = &ipu_fb_data,
+};
+
+static struct device_d esdhc_dev = {
+ .name = "imx-esdhc",
+ .map_base = IMX_SDHC1_BASE,
+};
+
+#ifdef CONFIG_MMU
+static int cupid_mmu_init(void)
+{
+ mmu_init();
+
+ arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
+ arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
+
+ setup_dma_coherent(0x10000000);
+
+#if TEXT_BASE & (0x100000 - 1)
+#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
+#else
+ arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
+#endif
+
+ mmu_enable();
+
+#ifdef CONFIG_CACHE_L2X0
+ l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
+#endif
+ return 0;
+}
+postcore_initcall(cupid_mmu_init);
+#endif
+
+static int cupid_devices_init(void)
+{
+ uint32_t reg;
+
+ gpio_direction_output(GPIO_LCD_ENABLE, 0);
+ gpio_direction_output(GPIO_LCD_BACKLIGHT, 0);
+
+ reg = readl(IMX_CCM_BASE + CCM_RCSR);
+ /* some fuses provide us vital information about connected hardware */
+ if (reg & 0x20000000)
+ nand_info.width = 2; /* 16 bit */
+ else
+ nand_info.width = 1; /* 8 bit */
+
+ register_device(&fec_dev);
+ register_device(&nand_dev);
+
+ devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+ dev_add_bb_dev("self_raw", "self0");
+ devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
+ dev_add_bb_dev("env_raw", "env0");
+
+ register_device(&sdram0_dev);
+ register_device(&imx_ipu_fb_dev);
+ register_device(&esdhc_dev);
+
+ armlinux_add_dram(&sdram0_dev);
+ armlinux_set_bootparams((void *)0x80000100);
+ armlinux_set_architecture(MACH_TYPE_GUF_CUPID);
+
+ return 0;
+}
+
+device_initcall(cupid_devices_init);
+
+static struct device_d cupid_serial_device = {
+ .id = -1,
+ .name = "imx_serial",
+ .map_base = IMX_UART1_BASE,
+ .size = 16 * 1024,
+};
+
+static struct pad_desc cupid_pads[] = {
+ /* UART1 */
+ MX35_PAD_CTS1__UART1_CTS,
+ MX35_PAD_RTS1__UART1_RTS,
+ MX35_PAD_TXD1__UART1_TXD_MUX,
+ MX35_PAD_RXD1__UART1_RXD_MUX,
+ /* UART2 */
+ MX35_PAD_CTS2__UART2_CTS,
+ MX35_PAD_RTS2__UART2_RTS,
+ MX35_PAD_TXD2__UART2_TXD_MUX,
+ MX35_PAD_RXD2__UART2_RXD_MUX,
+ /* FEC */
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* I2C1 */
+ MX35_PAD_I2C1_CLK__I2C1_SCL,
+ MX35_PAD_I2C1_DAT__I2C1_SDA,
+ /* Display */
+ MX35_PAD_LD0__IPU_DISPB_DAT_0,
+ MX35_PAD_LD1__IPU_DISPB_DAT_1,
+ MX35_PAD_LD2__IPU_DISPB_DAT_2,
+ MX35_PAD_LD3__IPU_DISPB_DAT_3,
+ MX35_PAD_LD4__IPU_DISPB_DAT_4,
+ MX35_PAD_LD5__IPU_DISPB_DAT_5,
+ MX35_PAD_LD6__IPU_DISPB_DAT_6,
+ MX35_PAD_LD7__IPU_DISPB_DAT_7,
+ MX35_PAD_LD8__IPU_DISPB_DAT_8,
+ MX35_PAD_LD9__IPU_DISPB_DAT_9,
+ MX35_PAD_LD10__IPU_DISPB_DAT_10,
+ MX35_PAD_LD11__IPU_DISPB_DAT_11,
+ MX35_PAD_LD12__IPU_DISPB_DAT_12,
+ MX35_PAD_LD13__IPU_DISPB_DAT_13,
+ MX35_PAD_LD14__IPU_DISPB_DAT_14,
+ MX35_PAD_LD15__IPU_DISPB_DAT_15,
+ MX35_PAD_LD16__IPU_DISPB_DAT_16,
+ MX35_PAD_LD17__IPU_DISPB_DAT_17,
+ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+ MX35_PAD_LD18__GPIO3_24, /* LCD enable */
+ MX35_PAD_CSPI1_SS1__GPIO1_19, /* LCD backligtht PWM */
+ /* USB Host*/
+ MX35_PAD_MLB_CLK__GPIO3_3, /* USB Host PWR */
+ MX35_PAD_MLB_DAT__GPIO3_4, /* USB Host Overcurrent */
+ /* USB OTG */
+ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+ MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+ /* SSI */
+ MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+ MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+ MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+ MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+ /* UCB1400 IRQ */
+ MX35_PAD_ATA_INTRQ__GPIO2_29,
+ /* Speaker On */
+ MX35_PAD_LD20__GPIO3_26,
+ /* LEDs */
+ MX35_PAD_TX1__GPIO1_14,
+ /* ESDHC1 */
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ /* ESDHC1 CD */
+ MX35_PAD_ATA_DATA5__GPIO2_18,
+ /* ESDHC1 WP */
+ MX35_PAD_ATA_DATA6__GPIO2_19,
+};
+
+static int cupid_console_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(cupid_pads, ARRAY_SIZE(cupid_pads));
+
+ register_device(&cupid_serial_device);
+ return 0;
+}
+
+console_initcall(cupid_console_init);
+
+static int cupid_core_setup(void)
+{
+ u32 tmp;
+
+ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, IMX_AIPS1_BASE);
+ writel(0x77777777, IMX_AIPS1_BASE + 0x4);
+ writel(0x77777777, IMX_AIPS2_BASE);
+ writel(0x77777777, IMX_AIPS2_BASE + 0x4);
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ writel(0x0, IMX_AIPS1_BASE + 0x40);
+ writel(0x0, IMX_AIPS1_BASE + 0x44);
+ writel(0x0, IMX_AIPS1_BASE + 0x48);
+ writel(0x0, IMX_AIPS1_BASE + 0x4C);
+ tmp = readl(IMX_AIPS1_BASE + 0x50);
+ tmp &= 0x00FFFFFF;
+ writel(tmp, IMX_AIPS1_BASE + 0x50);
+
+ writel(0x0, IMX_AIPS2_BASE + 0x40);
+ writel(0x0, IMX_AIPS2_BASE + 0x44);
+ writel(0x0, IMX_AIPS2_BASE + 0x48);
+ writel(0x0, IMX_AIPS2_BASE + 0x4C);
+ tmp = readl(IMX_AIPS2_BASE + 0x50);
+ tmp &= 0x00FFFFFF;
+ writel(tmp, IMX_AIPS2_BASE + 0x50);
+
+ /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_PARAM1 0x00302154
+ writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */
+ writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
+ writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
+ writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
+ writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
+
+ /* SGPCR - always park on last master */
+ writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
+ writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
+ writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
+ writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
+ writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
+
+ /* MGPCR - restore default values */
+ writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
+ writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
+ writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
+ writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
+ writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
+ writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
+
+ writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */
+ writel(0x444A4541, CSCR_L(0));
+ writel(0x44443302, CSCR_A(0));
+
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ writel(0x40, IMX_M3IF_BASE);
+
+ return 0;
+}
+
+core_initcall(cupid_core_setup);
+
+#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+
+static int do_cpufreq(struct command *cmdtp, int argc, char *argv[])
+{
+ unsigned long freq;
+
+ if (argc != 2)
+ return COMMAND_ERROR_USAGE;
+
+ freq = simple_strtoul(argv[1], NULL, 0);
+
+ switch (freq) {
+ case 399:
+ writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
+ break;
+ case 532:
+ writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+ break;
+ default:
+ return COMMAND_ERROR_USAGE;
+ }
+
+ printf("Switched CPU frequency to %dMHz\n", freq);
+
+ return 0;
+}
+
+static const __maybe_unused char cmd_cpufreq_help[] =
+"Usage: cpufreq 399|532\n"
+"\n"
+"Set CPU frequency to MHz\n";
+
+BAREBOX_CMD_START(cpufreq)
+ .cmd = do_cpufreq,
+ .usage = "adjust CPU frequency",
+ BAREBOX_CMD_HELP(cmd_cpufreq_help)
+BAREBOX_CMD_END
+
diff --git a/arch/arm/boards/guf-cupid/config.h b/arch/arm/boards/guf-cupid/config.h
new file mode 100644
index 0000000..0e3b175
--- /dev/null
+++ b/arch/arm/boards/guf-cupid/config.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Definitions related to passing arguments to kernel.
+ */
+
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#endif
+
+/* nothing to do here yet */
diff --git a/arch/arm/boards/guf-cupid/cupid.dox b/arch/arm/boards/guf-cupid/cupid.dox
new file mode 100644
index 0000000..45f0e0c
--- /dev/null
+++ b/arch/arm/boards/guf-cupid/cupid.dox
@@ -0,0 +1,9 @@
+/** @page board_cupid Garz+Fricke Cupid
+
+This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with:
+
+- 256MiB Nand flash
+- 128MiB synchronous dynamic RAM
+
+
+*/
diff --git a/arch/arm/boards/guf-cupid/env/config b/arch/arm/boards/guf-cupid/env/config
new file mode 100644
index 0000000..4db05b6
--- /dev/null
+++ b/arch/arm/boards/guf-cupid/env/config
@@ -0,0 +1,56 @@
+#!/bin/sh
+
+machine=cupid
+eth0.serverip=
+user=
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=dhcp
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'net', 'nor' or 'nand'
+kernel_loc=net
+# can be either 'net', 'nor', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root-$machine.$rootfs_type
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+kernelimage_type=zimage
+kernelimage=zImage-$machine
+#kernelimage_type=uimage
+#kernelimage=uImage-$machine
+#kernelimage_type=raw
+#kernelimage=Image-$machine
+#kernelimage_type=raw_lzo
+#kernelimage=Image-$machine.lzo
+
+if [ -n $user ]; then
+ kernelimage="$user"-"$kernelimage"
+ nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
+ rootfsimage="$user"-"$rootfsimage"
+else
+ nfsroot="$eth0.serverip:/path/to/nfs/root"
+fi
+
+autoboot_timeout=3
+
+bootargs="console=ttymxc0,115200"
+
+bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW"
+
+nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
+nand_device=mxc_nand
+rootfs_mtdblock_nand=3
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c
new file mode 100644
index 0000000..8d403ee
--- /dev/null
+++ b/arch/arm/boards/guf-cupid/lowlevel.c
@@ -0,0 +1,349 @@
+/*
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Assuming 24MHz input clock */
+#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
+#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
+#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
+
+#define SDRAM_MODE_BL_8 0x0003
+#define SDRAM_MODE_BSEQ 0x0000
+#define SDRAM_MODE_CL_3 0x0030
+#define MDDR_DS_HALF 0x20
+#define SDRAM_COMPARE_CONST1 0x55555555
+#define SDRAM_COMPARE_CONST2 0xaaaaaaaa
+
+#ifdef CONFIG_NAND_IMX_BOOT
+static void __bare_init __naked insdram(void)
+{
+ uint32_t r;
+
+ /* Speed up NAND controller by adjusting the NFC divider */
+ r = readl(IMX_CCM_BASE + CCM_PDR4);
+ r &= ~(0xf << 28);
+ r |= 0x1 << 28;
+ writel(r, IMX_CCM_BASE + CCM_PDR4);
+
+ /* setup a stack to be able to call imx_nand_load_image() */
+ r = STACK_BASE + STACK_SIZE - 12;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r));
+
+ imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
+
+ board_init_lowlevel_return();
+}
+#endif
+
+static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr)
+{
+ volatile int loop;
+ void *r9 = (void *)IMX_SDRAM_CS0;
+ u32 r11 = 0xda; /* dummy constant */
+ u32 r1, r0;
+
+ /* disable second SDRAM region to save power */
+ r1 = readl(ESDCTL1);
+ r1 &= ~ESDCTL0_SDE;
+ writel(r1, ESDCTL1);
+
+ mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST;
+ writel(mode, ESDMISC);
+
+ mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST);
+ writel(mode, ESDMISC);
+
+ /* wait for esdctl reset */
+ for (loop = 0; loop < 0x20000; loop++);
+
+ r1 = ESDCFGx_tXP_4 | ESDCFGx_tWTR_1 |
+ ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 |
+ ESDCFGx_tWR_1_2 | ESDCFGx_tRAS_6 |
+ ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 |
+ ESDCFGx_tRCD_3 | ESDCFGx_tRC_20;
+
+ writel(r1, ESDCFG0);
+
+ /* enable SDRAM controller */
+ writel(memsize | ESDCTL0_SMODE_NORMAL, ESDCTL0);
+
+ /* Micron Datasheet Initialization Step 3: Wait 200us before first command */
+ for (loop = 0; loop < 1000; loop++);
+
+ /* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */
+ writel(memsize | ESDCTL0_SMODE_PRECHARGE, ESDCTL0);
+ writeb(r11, sdram_addr);
+
+ /* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns)
+ * The CPU is not fast enough to cause a problem here
+ */
+
+ /* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP
+ * (at least 140ns)
+ */
+ writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
+ writeb(r11, r9); /* AUTO REFRESH #1 */
+
+ for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
+
+ writeb(r11, r9); /* AUTO REFRESH #2 */
+
+ for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */
+
+ /* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */
+ writel(memsize | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
+ writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3));
+
+ /* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP
+ * (The memory controller will take care of this delay)
+ */
+
+ /* Micron Datasheet Initialization Step 9: LOAD MODE REGISTER EXTENDED */
+ writeb(r11, 0x84000000 | MDDR_DS_HALF); /*we assume 14 Rows / 10 Cols here */
+
+ /* Micron Datasheet Initialization Step 9: tMRD = 2 tCK NOP
+ * (The memory controller will take care of this delay)
+ */
+
+ /* Now configure SDRAM-Controller and check that it works */
+ writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, ESDCTL0);
+
+ /* Freescale asks for first access to be a write to properly
+ * initialize DQS pin-state and keepers
+ */
+ writel(0xdeadbeef, r9);
+
+ /* test that the RAM is in fact working */
+ writel(SDRAM_COMPARE_CONST1, r9);
+ writel(SDRAM_COMPARE_CONST2, r9 + 0x4);
+
+ if (readl(r9) != SDRAM_COMPARE_CONST1)
+ while (1);
+
+ /* Verify that the correct row and coloumn is selected */
+
+ /* So far we asssumed that we have 14 rows, verify this */
+ writel(SDRAM_COMPARE_CONST1, r9);
+ writel(SDRAM_COMPARE_CONST2, r9 + (1 << 25));
+
+ /* if both value are identical, we don't have 14 rows. assume 13 instead */
+ if (readl(r9) == readl(r9 + (1 << 25))) {
+ r0 = readl(ESDCTL0);
+ r0 &= ~ESDCTL0_ROW_MASK;
+ r0 |= ESDCTL0_ROW13;
+ writel(r0, ESDCTL0);
+ }
+
+ /* So far we asssumed that we have 10 columns, verify this */
+ writel(SDRAM_COMPARE_CONST1, r9);
+ writel(SDRAM_COMPARE_CONST2, r9 + (1 << 11));
+
+ /* if both value are identical, we don't have 10 cols. assume 9 instead */
+ if (readl(r9) == readl(r9 + (1 << 11))) {
+ r0 = readl(ESDCTL0);
+ r0 &= ~ESDCTL0_COL_MASK;
+ r0 |= ESDCTL0_COL9;
+ writel(r0, ESDCTL0);
+ }
+}
+
+#define BRANCH_PREDICTION_ENABLE
+#define UNALIGNED_ACCESS_ENABLE
+#define LOW_INT_LATENCY_ENABLE
+
+void __bare_init __naked board_init_lowlevel(void)
+{
+ u32 r0, r1;
+ void *iomuxc_base = (void *)IMX_IOMUXC_BASE;
+ int i;
+#ifdef CONFIG_NAND_IMX_BOOT
+ unsigned int *trg, *src;
+#endif
+
+ r0 = 0x10000000 + 128 * 1024 - 16;
+ __asm__ __volatile__("mov sp, %0" : : "r"(r0));
+
+ /*
+ * ARM1136 init
+ * - invalidate I/D cache/TLB and drain write buffer;
+ * - invalidate L2 cache
+ * - unaligned access
+ * - branch predictions
+ */
+#ifdef TURN_OFF_IMPRECISE_ABORT
+ __asm__ __volatile__("mrs %0, cpsr":"=r"(r0));
+ r0 &= ~0x100;
+ __asm__ __volatile__("msr cpsr, %0" : : "r"(r0));
+#endif
+ /* ensure L1 caches and MMU are turned-off for now */
+ r1 = get_cr();
+ r1 &= ~(CR_I | CR_M | CR_C);
+
+ /* setup core features */
+ __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1":"=r"(r0));
+#ifdef BRANCH_PREDICTION_ENABLE
+ r0 |= 7;
+ r1 |= CR_Z;
+#else
+ r0 &= ~7;
+ r1 &= ~CR_Z;
+#endif
+ __asm__ __volatile__("mcr p15, 0, r0, c1, c0, 1" : : "r"(r0));
+
+#ifdef UNALIGNED_ACCESS_ENABLE
+ r1 |= CR_U;
+#else
+ r1 &= ~CR_U;
+#endif
+
+#ifdef LOW_INT_LATENCY_ENABLE
+ r1 |= CR_FI;
+#else
+ r1 &= ~CR_FI;
+#endif
+ set_cr(r1);
+
+ r0 = 0;
+ __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r0));
+
+ /* invalidate I cache and D cache */
+ __asm__ __volatile__("mcr p15, 0, r0, c7, c7, 0" : : "r"(r0));
+ /* invalidate TLBs */
+ __asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0" : : "r"(r0));
+ /* Drain the write buffer */
+ __asm__ __volatile__("mcr p15, 0, r0, c7, c10, 4" : : "r"(r0));
+
+ /* Also setup the Peripheral Port Remap register inside the core */
+ r0 = 0x40000015; /* start from AIPS 2GB region */
+ __asm__ __volatile__("mcr p15, 0, r0, c15, c2, 4" : : "r"(r0));
+
+#define WDOG_WMCR 0x8
+ /* silence reset WDOG */
+ writew(0, IMX_WDOG_BASE + WDOG_WMCR);
+
+ /* Skip SDRAM initialization if we run from RAM */
+ r0 = get_pc();
+ if (r0 > 0x80000000 && r0 < 0x90000000)
+ board_init_lowlevel_return();
+
+ /* Configure drive strength */
+
+ /* Configure DDR-pins to correct mode */
+ r0 = 0x00001800;
+ writel(r0, iomuxc_base + 0x794);
+ writel(r0, iomuxc_base + 0x798);
+ writel(r0, iomuxc_base + 0x79c);
+ writel(r0, iomuxc_base + 0x7a0);
+ writel(r0, iomuxc_base + 0x7a4);
+
+ /* Set drive strength for DDR-pins */
+ for (i = 0x368; i <= 0x4c8; i += 4) {
+ r0 = readl(iomuxc_base + i);
+ r0 &= ~0x6;
+ r0 |= 0x2;
+ writel(r0, iomuxc_base + i);
+ if (i == 0x468)
+ i = 0x4a4;
+ }
+
+ r0 = readl(iomuxc_base + 0x480);
+ r0 &= ~0x6;
+ r0 |= 0x2;
+ writel(r0, iomuxc_base + 0x480);
+
+ r0 = readl(iomuxc_base + 0x4b8);
+ r0 &= ~0x6;
+ r0 |= 0x2;
+ writel(r0, iomuxc_base + 0x4b8);
+
+ /* Configure static chip-selects */
+ r0 = readl(iomuxc_base + 0x000);
+ r0 &= ~1; /* configure CS2/CSD0 for SDRAM */
+ writel(r0, iomuxc_base + 0x000);
+
+ /* start-up code doesn't need any static chip-select.
+ * Leave their initialization to high-level code that
+ * can initialize them depending on the baseboard.
+ */
+
+ /* Configure clocks */
+
+ /* setup cpu/bus clocks */
+ writel(0x003f4208, IMX_CCM_BASE + CCM_CCMR);
+
+ /* configure MPLL */
+ writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
+
+ /* configure PPLL */
+ writel(PPCTL_PARAM_300, IMX_CCM_BASE + CCM_PPCTL);
+
+ /* configure core dividers */
+ r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2);
+
+ writel(r0, IMX_CCM_BASE + CCM_PDR0);
+
+ /* configure clock-gates */
+ r0 = readl(IMX_CCM_BASE + CCM_CGR0);
+ r0 |= 0x00300000;
+ writel(r0, IMX_CCM_BASE + CCM_CGR0);
+
+ r0 = readl(IMX_CCM_BASE + CCM_CGR1);
+ r0 |= 0x00000c03;
+ writel(r0, IMX_CCM_BASE + CCM_CGR1);
+
+ /* Configure SDRAM */
+ /* Try 32-Bit 256 MB DDR memory */
+ r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */
+ setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00);
+
+#ifdef CONFIG_NAND_IMX_BOOT
+ /* skip NAND boot if not running from NFC space */
+ r0 = get_pc();
+ if (r0 < IMX_NFC_BASE || r0 > IMX_NFC_BASE + 0x800)
+ board_init_lowlevel_return();
+
+ src = (unsigned int *)IMX_NFC_BASE;
+ trg = (unsigned int *)TEXT_BASE;
+
+ /* Move ourselves out of NFC SRAM */
+ for (i = 0; i < 0x800 / sizeof(int); i++)
+ *trg++ = *src++;
+
+ /* Jump to SDRAM */
+ r0 = (unsigned int)&insdram;
+ __asm__ __volatile__("mov pc, %0" : : "r"(r0));
+#else
+ board_init_lowlevel_return();
+#endif
+}
+
diff --git a/arch/arm/boards/nhk8815/env/bin/_update b/arch/arm/boards/nhk8815/env/bin/_update
deleted file mode 100644
index fb7cbe8..0000000
--- a/arch/arm/boards/nhk8815/env/bin/_update
+++ /dev/null
@@ -1,36 +0,0 @@
-#!/bin/sh
-
-if [ -z "$part" -o -z "$image" ]; then
- echo "define \$part and \$image"
- exit 1
-fi
-
-if [ \! -e "$part" ]; then
- echo "Partition $part does not exist"
- exit 1
-fi
-
-if [ $# = 1 ]; then
- image=$1
-fi
-
-if [ x$ip = xdhcp ]; then
- dhcp
-fi
-
-ping $eth0.serverip
-if [ $? -ne 0 ] ; then
- echo "update aborted"
- exit 1
-fi
-
-unprotect $part
-
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing $image to $part"
-echo
-tftp $image $part
diff --git a/arch/arm/boards/nhk8815/env/bin/boot b/arch/arm/boards/nhk8815/env/bin/boot
deleted file mode 100644
index fd8d957..0000000
--- a/arch/arm/boards/nhk8815/env/bin/boot
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-if [ x$1 = xflash ]; then
- root=flash
- kernel=flash
-fi
-
-if [ x$1 = xnet ]; then
- root=net
- kernel=net
-fi
-
-if [ x$ip = xdhcp ]; then
- bootargs="$bootargs ip=dhcp"
-else
- bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
-fi
-
-if [ x$root = xflash ]; then
- bootargs="$bootargs root=$rootpart rootfstype=jffs2"
-else
- bootargs="$bootargs root=/dev/nfs nfsroot=192.168.23.111:$nfsroot"
-fi
-
-bootargs="$bootargs"
-
-if [ $kernel = net ]; then
- if [ x$ip = xdhcp ]; then
- dhcp
- fi
- tftp $uimage uImage
- bootm uImage
-else
- bootm /dev/nor0.kernel
-fi
-
diff --git a/arch/arm/boards/nhk8815/env/bin/init b/arch/arm/boards/nhk8815/env/bin/init
deleted file mode 100644
index 5b45a70..0000000
--- a/arch/arm/boards/nhk8815/env/bin/init
+++ /dev/null
@@ -1,28 +0,0 @@
-#!/bin/sh
-
-PATH=/env/bin
-export PATH
-
-. /env/config
-
-if [ -e /dev/nand0 ]; then
- addpart /dev/nand0 $nand_parts
-
- # Uh, oh, hush first expands wildcards and then starts executing
- # commands. What a bug!
- source /env/bin/hush_hack
-fi
-
-echo
-echo -n "Hit any key to stop autoboot: "
-timeout -a $autoboot_timeout
-if [ $? != 0 ]; then
- echo
- echo "type update_kernel [] to update kernel into flash"
- echo "type udate_root [] to update rootfs into flash"
- echo "type update_barebox_xmodem nor to update barebox into flash"
- echo
- exit
-fi
-
-boot
diff --git a/arch/arm/boards/nhk8815/env/bin/update_barebox_xmodem b/arch/arm/boards/nhk8815/env/bin/update_barebox_xmodem
deleted file mode 100644
index 40f4ad3d..0000000
--- a/arch/arm/boards/nhk8815/env/bin/update_barebox_xmodem
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-part=/dev/nand0.barebox
-
-loadb -f barebox.bin -c
-
-unprotect $part
-echo
-echo "erasing partition $part"
-erase $part
-
-echo
-echo "flashing barebox.bin to $part"
-echo
-cp barebox.bin $part
-crc32 -f barebox.bin
-crc32 -f $part
diff --git a/arch/arm/boards/nhk8815/env/bin/update_kernel b/arch/arm/boards/nhk8815/env/bin/update_kernel
deleted file mode 100644
index db0f4c2..0000000
--- a/arch/arm/boards/nhk8815/env/bin/update_kernel
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$uimage
-part=/dev/nand0.kernel
-
-. /env/bin/_update $1
diff --git a/arch/arm/boards/nhk8815/env/bin/update_root b/arch/arm/boards/nhk8815/env/bin/update_root
deleted file mode 100644
index 9530e84..0000000
--- a/arch/arm/boards/nhk8815/env/bin/update_root
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-. /env/config
-
-image=$jffs2
-part=/dev/nand0.rootfs
-
-. /env/bin/_update $1
diff --git a/arch/arm/boards/nhk8815/env/config b/arch/arm/boards/nhk8815/env/config
index 7e7fc45..e657a76 100644
--- a/arch/arm/boards/nhk8815/env/config
+++ b/arch/arm/boards/nhk8815/env/config
@@ -1,16 +1,33 @@
#!/bin/sh
-# can be either 'net' or 'flash'
-kernel=net
-root=net
-
-# use 'dhcp' todo dhcp in uboot and in kernel
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
-#
-# setup default ethernet address
-#
-#eth0.serverip=192.168.23.108
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'net' or 'nand'
+kernel_loc=net
+# can be either 'net', 'nand' or 'initrd'
+rootfs_loc=net
+
+# can be either 'jffs2' or 'ubifs'
+rootfs_type=ubifs
+rootfsimage=root.$rootfs_type
+
+# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
+#kernelimage_type=zimage
+#kernelimage=zImage
+kernelimage_type=uimage
+kernelimage=uImage
+#kernelimage_type=raw
+#kernelimage=Image
+#kernelimage_type=raw_lzo
+#kernelimage=Image.lzo
# Partition Size Start
# XloaderTOC + X-Loader 256KB 0x00000000
@@ -22,11 +39,10 @@
nand_parts="256k(xloader)ro,256k(meminit),2M(barebox),3M(kernel),22M(rootfs),100M(userfs),384k(free),128k(bareboxenv)"
-uimage=uImage-nhk15
-
-# use 'dhcp' to do dhcp in uboot and in kernel
-ip=dhcp
-
autoboot_timeout=3
bootargs="root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc"
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
+
diff --git a/arch/arm/boards/pcm038/Makefile b/arch/arm/boards/pcm038/Makefile
index a681dda..970804e 100644
--- a/arch/arm/boards/pcm038/Makefile
+++ b/arch/arm/boards/pcm038/Makefile
@@ -1,3 +1,3 @@
-obj-y += lowlevel.o pll_init.o
+obj-y += lowlevel.o
obj-y += pcm038.o
diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c
index eb85e8f..b50e1c8 100644
--- a/arch/arm/boards/pcm038/lowlevel.c
+++ b/arch/arm/boards/pcm038/lowlevel.c
@@ -31,6 +31,8 @@
#include
#include
+#include "pll.h"
+
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
@@ -68,6 +70,11 @@
if (r > 0xa0000000 && r < 0xb0000000)
board_init_lowlevel_return();
+ /* re-program the PLL prior(!) starting the SDRAM controller */
+ MPCTL0 = MPCTL0_VAL;
+ SPCTL0 = SPCTL0_VAL;
+ CSCR = CSCR_VAL | CSCR_UPDATE_DIS | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
+
/*
* DDR on CSD0
*/
diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c
index fda3262..3a9b413 100644
--- a/arch/arm/boards/pcm038/pcm038.c
+++ b/arch/arm/boards/pcm038/pcm038.c
@@ -44,6 +44,8 @@
#include
#include
+#include "pll.h"
+
static struct device_d cfi_dev = {
.id = -1,
.name = "cfi_flash",
@@ -379,11 +381,6 @@
static int pcm038_console_init(void)
{
- /* bring PLLs to reset default */
- MPCTL0 = 0x00211803;
- SPCTL0 = 0x1002700c;
- CSCR = 0x33fc1307;
-
register_device(&pcm038_serial_device);
return 0;
@@ -391,40 +388,50 @@
console_initcall(pcm038_console_init);
-extern void *pcm038_pll_init, *pcm038_pll_init_end;
+/**
+ * The spctl0 register is a beast: Seems you can read it
+ * only one times without writing it again.
+ */
+static inline uint32_t get_pll_spctl10(void)
+{
+ uint32_t reg;
+ reg = SPCTL0;
+ SPCTL0 = reg;
+
+ return reg;
+}
+
+/**
+ * If the PLL settings are in place switch the CPU core frequency to the max. value
+ */
static int pcm038_power_init(void)
{
+ uint32_t spctl0;
int ret;
- void *vram = (void*)0xffff4c00;
- void (*pllfunc)(void) = vram;
- printf("initialising PLLs: 0x%p 0x%p\n", &pcm038_pll_init);
+ spctl0 = get_pll_spctl10();
- memcpy(vram, &pcm038_pll_init, 0x100);
-
- console_flush();
-
- ret = pmic_power();
- if (ret) {
- printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
- return 0;
+ /* PLL registers already set to their final values? */
+ if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) {
+ console_flush();
+ ret = pmic_power();
+ if (ret == 0) {
+ /* wait for required power level to run the CPU at 400 MHz */
+ udelay(100000);
+ CSCR = CSCR_VAL_FINAL;
+ PCDR0 = 0x130410c3;
+ PCDR1 = 0x09030911;
+ /* Clocks have changed. Notify clients */
+ clock_notifier_call_chain();
+ } else {
+ printf("Failed to initialize PMIC. Will continue with low CPU speed\n");
+ }
}
- /* wait for good power level */
- udelay(100000);
-
- pllfunc();
-
/* clock gating enable */
GPCR = 0x00050f08;
- PCDR0 = 0x130410c3;
- PCDR1 = 0x09030911;
-
- /* Clocks have changed. Notify clients */
- clock_notifier_call_chain();
-
return 0;
}
diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h
new file mode 100644
index 0000000..13a7989
--- /dev/null
+++ b/arch/arm/boards/pcm038/pll.h
@@ -0,0 +1,70 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**
+ * @file
+ * @brief phyCORE-i.MX27 specific PLL setup
+ */
+
+#ifndef __PCM038_PLL_H
+#define __PCM038_PLL_H
+
+/* define the PLL setting we want to run the system */
+
+/* main clock divider settings immediately after reset (at 1.25 V core supply) */
+#define CSCR_VAL (CSCR_USB_DIV(3) | \
+ CSCR_SD_CNT(3) | \
+ CSCR_MSHC_SEL | \
+ CSCR_H264_SEL | \
+ CSCR_SSI1_SEL | \
+ CSCR_SSI2_SEL | \
+ CSCR_SP_SEL | /* 26 MHz reference */ \
+ CSCR_MCU_SEL | /* 26 MHz reference */ \
+ CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \
+ CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
+ CSCR_SPEN | \
+ CSCR_MPEN)
+
+/* main clock divider settings after core voltage increases to 1.45 V */
+#define CSCR_VAL_FINAL (CSCR_USB_DIV(3) | \
+ CSCR_SD_CNT(3) | \
+ CSCR_MSHC_SEL | \
+ CSCR_H264_SEL | \
+ CSCR_SSI1_SEL | \
+ CSCR_SSI2_SEL | \
+ CSCR_SP_SEL | /* 26 MHz reference */ \
+ CSCR_MCU_SEL | /* 26 MHz reference */ \
+ CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \
+ CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \
+ CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \
+ CSCR_SPEN | \
+ CSCR_MPEN)
+
+/* MPLL should provide a 399 MHz clock from the 26 MHz reference */
+#define MPCTL0_VAL (IMX_PLL_PD(0) | \
+ IMX_PLL_MFD(51) | \
+ IMX_PLL_MFI(7) | \
+ IMX_PLL_MFN(35))
+
+/* SPLL should provide a 240 MHz clock from the 26 MHz reference */
+#define SPCTL0_VAL (IMX_PLL_PD(1) | \
+ IMX_PLL_MFD(12) | \
+ IMX_PLL_MFI(9) | \
+ IMX_PLL_MFN(3))
+
+
+#endif /* __PCM038_PLL_H */
diff --git a/arch/arm/boards/pcm038/pll_init.S b/arch/arm/boards/pcm038/pll_init.S
deleted file mode 100644
index 0c1ff13..0000000
--- a/arch/arm/boards/pcm038/pll_init.S
+++ /dev/null
@@ -1,48 +0,0 @@
-#include
-#include
-#include
-#include
-
-#define writel(val, reg) \
- ldr r0, =reg; \
- ldr r1, =val; \
- str r1, [r0];
-
-#define CSCR_VAL CSCR_USB_DIV(3) | \
- CSCR_SD_CNT(3) | \
- CSCR_MSHC_SEL | \
- CSCR_H264_SEL | \
- CSCR_SSI1_SEL | \
- CSCR_SSI2_SEL | \
- CSCR_MCU_SEL | \
- CSCR_ARM_SRC_MPLL | \
- CSCR_SP_SEL | \
- CSCR_ARM_DIV(0) | \
- CSCR_FPM_EN | \
- CSCR_SPEN | \
- CSCR_MPEN | \
- CSCR_AHB_DIV(1)
-
-ENTRY(pcm038_pll_init)
-
- writel(IMX_PLL_PD(0) |
- IMX_PLL_MFD(51) |
- IMX_PLL_MFI(7) |
- IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */
-
- writel(IMX_PLL_PD(1) |
- IMX_PLL_MFD(12) |
- IMX_PLL_MFI(9) |
- IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
-
- writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
-
- ldr r2, =16000
-1:
- subs r2, r2, #1
- nop
- bcs 1b
-
- mov pc, lr
-ENDPROC(pcm038_pll_init)
-
diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c
index 9f98795..5932f95 100644
--- a/arch/arm/boards/pcm043/pcm043.c
+++ b/arch/arm/boards/pcm043/pcm043.c
@@ -93,7 +93,7 @@
};
#ifdef CONFIG_PCM043_DISPLAY_SHARP
-static const struct fb_videomode pcm043_fb_mode = {
+static struct fb_videomode pcm043_fb_mode = {
/* 240x320 @ 60 Hz */
.name = "Sharp-LQ035Q7",
.refresh = 60,
@@ -111,7 +111,7 @@
.flag = 0,
};
#else
-static const struct fb_videomode pcm043_fb_mode = {
+static struct fb_videomode pcm043_fb_mode = {
/* 240x320 @ 60 Hz */
.name = "TX090",
.refresh = 60,
diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c
index 7328a6c..3a96180 100644
--- a/arch/arm/boards/phycard-i.MX27/pca100.c
+++ b/arch/arm/boards/phycard-i.MX27/pca100.c
@@ -68,6 +68,7 @@
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
+ .flash_bbt = 1,
};
static struct device_d nand_dev = {
@@ -109,6 +110,11 @@
}
#endif
+static struct device_d mmc_dev = {
+ .name = "imx-mmc",
+ .map_base = 0x10014000,
+};
+
#ifdef CONFIG_MMU
static void pca100_mmu_init(void)
{
@@ -180,8 +186,17 @@
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
+ /* SDHC */
+ PB4_PF_SD2_D0,
+ PB5_PF_SD2_D1,
+ PB6_PF_SD2_D2,
+ PB7_PF_SD2_D3,
+ PB8_PF_SD2_CMD,
+ PB9_PF_SD2_CLK,
};
+ PCCR0 |= PCCR0_SDHC2_EN;
+
/* disable the usb phys */
imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN);
gpio_direction_output(GPIO_PORTB + 23, 1);
@@ -195,6 +210,7 @@
register_device(&nand_dev);
register_device(&sdram_dev);
register_device(&fec_dev);
+ register_device(&mmc_dev);
PCCR1 |= PCCR1_PERCLK2_EN;
diff --git a/arch/arm/configs/chumbyone_defconfig b/arch/arm/configs/chumbyone_defconfig
new file mode 100644
index 0000000..595b6a9
--- /dev/null
+++ b/arch/arm/configs/chumbyone_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARCH_STM=y
+CONFIG_MACH_CHUMBY=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_BROKEN=y
+CONFIG_PROMPT="chumby:"
+CONFIG_LONGHELP=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/chumby_falconwing/env"
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+# CONFIG_SPI is not set
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_STM378X=y
diff --git a/arch/arm/configs/cupid_defconfig b/arch/arm/configs/cupid_defconfig
new file mode 100644
index 0000000..e24afe1
--- /dev/null
+++ b/arch/arm/configs/cupid_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARCH_IMX=y
+CONFIG_CACHE_L2X0=y
+CONFIG_ARCH_IMX35=y
+CONFIG_MACH_GUF_CUPID=y
+CONFIG_IMX_CLKO=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x87F00000
+CONFIG_MALLOC_SIZE=0x1000000
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/guf-cupid/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_NFS=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_NET_TFTP_PUSH=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_IMX=y
+CONFIG_NAND_IMX_BOOT=y
+CONFIG_NAND_IMX_BOOT_2K=y
+CONFIG_UBI=y
+CONFIG_VIDEO=y
+CONFIG_DRIVER_VIDEO_IMX_IPU=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig
index feb758e..bc68804 100644
--- a/arch/arm/configs/eukrea_cpuimx25_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx25_defconfig
@@ -9,6 +9,7 @@
CONFIG_GLOB=y
CONFIG_PROMPT_HUSH_PS2="cpuimx25>"
CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
@@ -23,6 +24,7 @@
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_ZLIB=y
@@ -35,15 +37,23 @@
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
+CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_GADGET=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MCI_IMX_ESDHC_PIO=y
diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig
index 975d095..af82827 100644
--- a/arch/arm/configs/eukrea_cpuimx35_defconfig
+++ b/arch/arm/configs/eukrea_cpuimx35_defconfig
@@ -8,8 +8,11 @@
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_HUSH_GETOPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
+# CONFIG_CONSOLE_ACTIVATE_FIRST is not set
+CONFIG_CONSOLE_ACTIVATE_ALL=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx35/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
@@ -22,6 +25,7 @@
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_RESET=y
@@ -31,15 +35,23 @@
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
+CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
CONFIG_DRIVER_NET_FEC_IMX=y
# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_IMX=y
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_IMX=y
-CONFIG_NAND_IMX_BOOT=y
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_GADGET=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX_IPU=y
+CONFIG_MCI=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_MCI_IMX_ESDHC_PIO=y
diff --git a/arch/arm/configs/freescale_mx51_babbage_defconfig b/arch/arm/configs/freescale_mx51_babbage_defconfig
new file mode 100644
index 0000000..d99d91a
--- /dev/null
+++ b/arch/arm/configs/freescale_mx51_babbage_defconfig
@@ -0,0 +1,43 @@
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_INTERNAL_BOOT=y
+CONFIG_ARCH_IMX51=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x97f00000
+CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx51-pdk/env/"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+CONFIG_DRIVER_SPI_IMX=y
+CONFIG_DRIVER_CFI=y
+CONFIG_CFI_BUFFER_WRITE=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+CONFIG_MCI_IMX_ESDHC=y
+CONFIG_I2C_MC13892=y
diff --git a/arch/arm/configs/imx23evk_defconfig b/arch/arm/configs/imx23evk_defconfig
new file mode 100644
index 0000000..047a7e1
--- /dev/null
+++ b/arch/arm/configs/imx23evk_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARCH_STM=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_BROKEN=y
+CONFIG_LONGHELP=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_PARTITION=y
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_MTEST_ALTERNATIVE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+# CONFIG_SPI is not set
diff --git a/arch/arm/configs/neso_defconfig b/arch/arm/configs/neso_defconfig
index 9f6e3f4..24125f9 100644
--- a/arch/arm/configs/neso_defconfig
+++ b/arch/arm/configs/neso_defconfig
@@ -12,7 +12,8 @@
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/guf-neso/env"
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/guf-neso/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index e3f4102..b81afe2 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -10,7 +10,8 @@
CONFIG_MENU=y
CONFIG_PASSWD_SUM_SHA1=y
CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/nhk8815/env"
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/nhk8815/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
@@ -22,8 +23,8 @@
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_PASSWD=y
CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_ZLIB=y
diff --git a/arch/arm/configs/pca100_defconfig b/arch/arm/configs/pca100_defconfig
index d1708a6..8c72bdf 100644
--- a/arch/arm/configs/pca100_defconfig
+++ b/arch/arm/configs/pca100_defconfig
@@ -12,7 +12,8 @@
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/phycard-i.MX27/env"
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phycard-i.MX27/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig
index 8e60b0a..e12f690 100644
--- a/arch/arm/configs/pcm037_defconfig
+++ b/arch/arm/configs/pcm037_defconfig
@@ -10,7 +10,8 @@
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm037/env"
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm037/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig
index eacbbc6..2038f14 100644
--- a/arch/arm/configs/pcm038_defconfig
+++ b/arch/arm/configs/pcm038_defconfig
@@ -13,7 +13,8 @@
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm038/env"
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm038/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
diff --git a/arch/arm/configs/pcm043_defconfig b/arch/arm/configs/pcm043_defconfig
index 51ca833..2dd711b 100644
--- a/arch/arm/configs/pcm043_defconfig
+++ b/arch/arm/configs/pcm043_defconfig
@@ -13,7 +13,8 @@
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_PARTITION=y
-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm043/env"
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm043/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c
index 61569d2..1ea7bab 100644
--- a/arch/arm/cpu/cache-l2x0.c
+++ b/arch/arm/cpu/cache-l2x0.c
@@ -127,7 +127,7 @@
cache_sync();
}
-void l2x0_flush_range(unsigned long start, unsigned long end)
+static void l2x0_flush_range(unsigned long start, unsigned long end)
{
start &= ~(CACHE_LINE_SIZE - 1);
while (start < end) {
diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c
index 133d144..346f8dc 100644
--- a/arch/arm/cpu/cpu.c
+++ b/arch/arm/cpu/cpu.c
@@ -27,6 +27,7 @@
#include
#include
+#include
#include
#include
diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c
index 0557172..4a0b3f8 100644
--- a/arch/arm/cpu/interrupts.c
+++ b/arch/arm/cpu/interrupts.c
@@ -28,6 +28,14 @@
#include
#include
+void do_undefined_instruction (struct pt_regs *pt_regs);
+void do_software_interrupt (struct pt_regs *pt_regs);
+void do_prefetch_abort (struct pt_regs *pt_regs);
+void do_data_abort (struct pt_regs *pt_regs);
+void do_not_used (struct pt_regs *pt_regs);
+void do_fiq (struct pt_regs *pt_regs);
+void do_irq (struct pt_regs *pt_regs);
+
#ifdef CONFIG_USE_IRQ
/* enable IRQ interrupts */
void enable_interrupts (void)
@@ -62,7 +70,7 @@
/**
* FIXME
*/
-void bad_mode (void)
+static void bad_mode (void)
{
panic ("Resetting CPU ...\n");
reset_cpu (0);
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 5bf31c0..08a57ce 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -16,12 +16,10 @@
ttb[virt] = (phys << 20) | flags;
asm volatile (
- "mov r0, #0;"
- "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */
- "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */
+ "bl __mmu_cache_flush;"
:
:
- : "r0","memory" /* clobber list */
+ : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory"
);
}
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c1ac1aa..1d7f15a 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -1,7 +1,6 @@
obj-y += armlinux.o
obj-y += _ashldi3.o
obj-y += _ashrdi3.o
-obj-y += cache.o
obj-y += div0.o
obj-y += _divsi3.o
obj-y += _modsi3.o
diff --git a/arch/arm/lib/armlinux.c b/arch/arm/lib/armlinux.c
index 7c2cbf9..f826da6 100644
--- a/arch/arm/lib/armlinux.c
+++ b/arch/arm/lib/armlinux.c
@@ -40,6 +40,7 @@
#include
#include
#include
+#include
static struct tag *params;
static int armlinux_architecture = 0;
@@ -135,8 +136,7 @@
}
}
-#if 0
-static void setup_initrd_tag(ulong initrd_start, ulong initrd_end)
+static void setup_initrd_tag(image_header_t *header)
{
/* an ATAG_INITRD node tells the kernel where the compressed
* ramdisk can be found. ATAG_RDIMG is a better name, actually.
@@ -144,12 +144,11 @@
params->hdr.tag = ATAG_INITRD2;
params->hdr.size = tag_size(tag_initrd);
- params->u.initrd.start = initrd_start;
- params->u.initrd.size = initrd_end - initrd_start;
+ params->u.initrd.start = image_get_load(header);
+ params->u.initrd.size = image_get_data_size(header);
params = tag_next(params);
}
-#endif
static void setup_end_tag (void)
{
@@ -157,17 +156,17 @@
params->hdr.size = 0;
}
-static void setup_tags(void)
+static void setup_tags(struct image_data *data)
{
const char *commandline = getenv("bootargs");
setup_start_tag();
setup_memory_tags();
setup_commandline_tag(commandline);
-#if 0
- if (initrd_start && initrd_end)
- setup_initrd_tag (initrd_start, initrd_end);
-#endif
+
+ if (data && data->initrd)
+ setup_initrd_tag (&data->initrd->header);
+
setup_revision_tag();
setup_serial_tag();
setup_end_tag();
@@ -207,12 +206,12 @@
}
#ifdef CONFIG_CMD_BOOTM
-int do_bootm_linux(struct image_data *data)
+static int do_bootm_linux(struct image_data *data)
{
void (*theKernel)(int zero, int arch, void *params);
image_header_t *os_header = &data->os->header;
- if (image_check_type(os_header, IH_TYPE_MULTI)) {
+ if (image_get_type(os_header) == IH_TYPE_MULTI) {
printf("Multifile images not handled at the moment\n");
return -1;
}
@@ -232,13 +231,17 @@
debug("## Transferring control to Linux (at address 0x%p) ...\n",
theKernel);
- setup_tags();
+ setup_tags(data);
if (relocate_image(data->os, (void *)image_get_load(os_header)))
return -1;
+ if (data->initrd)
+ if (relocate_image(data->initrd, (void *)image_get_load(&data->initrd->header)))
+ return -1;
+
/* we assume that the kernel is in place */
- printf("\nStarting kernel ...\n\n");
+ printf("\nStarting kernel %s...\n\n", data->initrd ? "with initrd " : "");
shutdown_barebox();
theKernel (0, armlinux_architecture, armlinux_bootparams);
@@ -335,7 +338,7 @@
printf("loaded zImage from %s with size %d\n", argv[1], header.end);
- setup_tags();
+ setup_tags(NULL);
shutdown_barebox();
theKernel(0, armlinux_architecture, armlinux_bootparams);
@@ -379,7 +382,7 @@
if (!theKernel)
theKernel = (void *)simple_strtoul(argv[1], NULL, 0);
- setup_tags();
+ setup_tags(NULL);
shutdown_barebox();
theKernel(0, armlinux_architecture, armlinux_bootparams);
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
deleted file mode 100644
index 61ee9d3..0000000
--- a/arch/arm/lib/cache.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* for now: just dummy functions to satisfy the linker */
-
-#include
-
-void flush_cache (unsigned long dummy1, unsigned long dummy2)
-{
-#ifdef CONFIG_OMAP2420
- void arm1136_cache_flush(void);
-
- arm1136_cache_flush();
-#endif
- return;
-}
diff --git a/arch/arm/lib/div0.c b/arch/arm/lib/div0.c
index 6267bf1..99d6b85 100644
--- a/arch/arm/lib/div0.c
+++ b/arch/arm/lib/div0.c
@@ -20,11 +20,12 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include
+
+extern void __div0(void);
/* Replacement (=dummy) for GNU/Linux division-by zero handler */
void __div0 (void)
{
- extern void hang (void);
-
hang();
}
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 84df1a1..c1b42f9 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -73,7 +73,7 @@
/*
* Reset the cpu through the reset controller
*/
-void __noreturn reset_cpu (unsigned long ignored)
+void __noreturn reset_cpu (unsigned long addr)
{
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
diff --git a/arch/arm/mach-ep93xx/clocksource.c b/arch/arm/mach-ep93xx/clocksource.c
index 3aa8e14..a1e315d 100644
--- a/arch/arm/mach-ep93xx/clocksource.c
+++ b/arch/arm/mach-ep93xx/clocksource.c
@@ -72,7 +72,7 @@
/*
* Reset the cpu
*/
-void __noreturn reset_cpu(unsigned long ignored)
+void __noreturn reset_cpu(unsigned long addr)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
uint32_t value;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4f95393..f3506af 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -17,6 +17,8 @@
default 0x87f00000 if MACH_PCM043
default 0x08f80000 if MACH_SCB9328
default 0xa7e00000 if MACH_NESO
+ default 0x97f00000 if MACH_MX51_PDK
+ default 0x87f00000 if MACH_GUF_CUPID
config BOARDINFO
default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
@@ -32,13 +34,15 @@
default "Phytec phyCORE-i.MX35" if MACH_PCM043
default "Synertronixx scb9328" if MACH_SCB9328
default "Garz+Fricke Neso" if MACH_NESO
+ default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK
+ default "Garz+Fricke Cupid" if MACH_GUF_CUPID
config ARCH_HAS_FEC_IMX
bool
config ARCH_IMX_INTERNAL_BOOT
bool "support internal boot mode"
- depends on ARCH_IMX25 || ARCH_IMX35
+ depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51
choice
depends on ARCH_IMX_INTERNAL_BOOT
@@ -94,6 +98,11 @@
select CPU_V6
select ARCH_HAS_FEC_IMX
+config ARCH_IMX51
+ bool "i.MX51"
+ select CPU_V7
+ select ARCH_HAS_FEC_IMX
+
endchoice
# ----------------------------------------------------------
@@ -292,12 +301,36 @@
Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped
with a Freescale i.MX35 Processor
+config MACH_GUF_CUPID
+ bool "Garz+Fricke Cupid"
+ select HAVE_MMU
+ select MACH_HAS_LOWLEVEL_INIT
+ select ARCH_HAS_L2X0
+ help
+ Say Y here if you are using the Garz+Fricke Neso board equipped
+ with a Freescale i.MX35 Processor
+
endchoice
endif
# ----------------------------------------------------------
+if ARCH_IMX51
+
+choice
+
+ prompt "i.MX51 Board Type"
+
+config MACH_FREESCALE_MX51_PDK
+ bool "Freescale i.MX51 PDK"
+ select HAVE_MMU
+ select MACH_HAS_LOWLEVEL_INIT
+
+endchoice
+
+endif
+
menu "Board specific settings "
if MACH_PCM043
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index de62f7e..ce38566 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
+obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o
obj-$(CONFIG_IMX_CLKO) += clko.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c
index a166038..5b1bad5 100644
--- a/arch/arm/mach-imx/clocksource.c
+++ b/arch/arm/mach-imx/clocksource.c
@@ -40,7 +40,7 @@
#define GPT(x) __REG(IMX_TIM1_BASE + (x))
#define timer_base (IMX_TIM1_BASE)
-uint64_t imx_clocksource_read(void)
+static uint64_t imx_clocksource_read(void)
{
return readl(timer_base + GPT_TCN);
}
@@ -76,6 +76,10 @@
PCCR0 |= PCCR0_GPT1_EN;
PCCR1 |= PCCR1_PERCLK1_EN;
#endif
+#ifdef CONFIG_ARCH_IMX25
+ writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 19),
+ IMX_CCM_BASE + CCM_CGCR1);
+#endif
for (i = 0; i < 100; i++)
writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */
@@ -97,19 +101,34 @@
core_initcall(clocksource_init);
/*
+ * Watchdog Registers
+ */
+#ifdef CONFIG_ARCH_IMX1
+#define WDOG_WCR 0x00 /* Watchdog Control Register */
+#define WDOG_WSR 0x04 /* Watchdog Service Register */
+#define WDOG_WSTR 0x08 /* Watchdog Status Register */
+#define WDOG_WCR_WDE (1 << 0)
+#else
+#define WDOG_WCR 0x00 /* Watchdog Control Register */
+#define WDOG_WSR 0x02 /* Watchdog Service Register */
+#define WDOG_WSTR 0x04 /* Watchdog Status Register */
+#define WDOG_WCR_WDE (1 << 2)
+#endif
+
+/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
-void __noreturn reset_cpu (unsigned long ignored)
+void __noreturn reset_cpu (unsigned long addr)
{
/* Disable watchdog and set Time-Out field to 0 */
- WCR = 0x0000;
+ writew(0x0, IMX_WDT_BASE + WDOG_WCR);
/* Write Service Sequence */
- WSR = 0x5555;
- WSR = 0xAAAA;
+ writew(0x5555, IMX_WDT_BASE + WDOG_WSR);
+ writew(0xaaaa, IMX_WDT_BASE + WDOG_WSR);
/* Enable watchdog */
- WCR = WCR_WDE;
+ writew(WDOG_WCR_WDE, IMX_WDT_BASE + WDOG_WCR);
while (1);
/*NOTREACHED*/
diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c
index c6a59a6..0a3e046 100644
--- a/arch/arm/mach-imx/gpio.c
+++ b/arch/arm/mach-imx/gpio.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#if defined CONFIG_ARCH_IMX1 || defined CONFIG_ARCH_IMX21 || defined CONFIG_ARCH_IMX27
#define GPIO_DR 0x1c
@@ -47,20 +48,20 @@
#define GPIO_ISR 0x18
#endif
-extern void *imx_gpio_base[];
+extern void __iomem *imx_gpio_base[];
extern int imx_gpio_count;
-static void *gpio_get_base(unsigned gpio)
+static void __iomem *gpio_get_base(unsigned gpio)
{
if (gpio >= imx_gpio_count)
- return 0;
+ return NULL;
return imx_gpio_base[gpio / 32];
}
void gpio_set_value(unsigned gpio, int value)
{
- void *base = gpio_get_base(gpio);
+ void __iomem *base = gpio_get_base(gpio);
int shift = gpio % 32;
u32 val;
@@ -79,7 +80,7 @@
int gpio_direction_input(unsigned gpio)
{
- void *base = gpio_get_base(gpio);
+ void __iomem *base = gpio_get_base(gpio);
int shift = gpio % 32;
u32 val;
@@ -96,7 +97,7 @@
int gpio_direction_output(unsigned gpio, int value)
{
- void *base = gpio_get_base(gpio);
+ void __iomem *base = gpio_get_base(gpio);
int shift = gpio % 32;
u32 val;
@@ -114,7 +115,7 @@
int gpio_get_value(unsigned gpio)
{
- void *base = gpio_get_base(gpio);
+ void __iomem *base = gpio_get_base(gpio);
int shift = gpio % 32;
u32 val;
diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c
index 8c4fc11..075ed22 100644
--- a/arch/arm/mach-imx/imx51.c
+++ b/arch/arm/mach-imx/imx51.c
@@ -15,7 +15,10 @@
* MA 02111-1307 USA
*/
+#include
#include
+#include
+#include
#include "gpio.h"
@@ -28,3 +31,51 @@
int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
+#define SI_REV 0x48
+
+static u32 mx51_silicon_revision;
+static char *mx51_rev_string = "unknown";
+
+int imx_silicon_revision(void)
+{
+ return mx51_silicon_revision;
+}
+
+static int query_silicon_revision(void)
+{
+ void __iomem *rom = MX51_IROM_BASE_ADDR;
+ u32 rev;
+
+ rev = readl(rom + SI_REV);
+ switch (rev) {
+ case 0x1:
+ mx51_silicon_revision = MX51_CHIP_REV_1_0;
+ mx51_rev_string = "1.0";
+ break;
+ case 0x2:
+ mx51_silicon_revision = MX51_CHIP_REV_1_1;
+ mx51_rev_string = "1.1";
+ break;
+ case 0x10:
+ mx51_silicon_revision = MX51_CHIP_REV_2_0;
+ mx51_rev_string = "2.0";
+ break;
+ case 0x20:
+ mx51_silicon_revision = MX51_CHIP_REV_3_0;
+ mx51_rev_string = "3.0";
+ break;
+ default:
+ mx51_silicon_revision = 0;
+ }
+
+ return 0;
+}
+core_initcall(query_silicon_revision);
+
+static int imx51_print_silicon_rev(void)
+{
+ printf("detected i.MX51 rev %s\n", mx51_rev_string);
+
+ return 0;
+}
+device_initcall(imx51_print_silicon_rev);
diff --git a/arch/arm/mach-imx/include/mach/clock-imx51.h b/arch/arm/mach-imx/include/mach/clock-imx51.h
new file mode 100644
index 0000000..0dee7c3
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/clock-imx51.h
@@ -0,0 +1,696 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+/* PLL Register Offsets */
+#define MX51_PLL_DP_CTL 0x00
+#define MX51_PLL_DP_CONFIG 0x04
+#define MX51_PLL_DP_OP 0x08
+#define MX51_PLL_DP_MFD 0x0C
+#define MX51_PLL_DP_MFN 0x10
+#define MX51_PLL_DP_MFNMINUS 0x14
+#define MX51_PLL_DP_MFNPLUS 0x18
+#define MX51_PLL_DP_HFS_OP 0x1C
+#define MX51_PLL_DP_HFS_MFD 0x20
+#define MX51_PLL_DP_HFS_MFN 0x24
+#define MX51_PLL_DP_MFN_TOGC 0x28
+#define MX51_PLL_DP_DESTAT 0x2c
+
+/* PLL Register Bit definitions */
+#define MX51_PLL_DP_CTL_MUL_CTRL 0x2000
+#define MX51_PLL_DP_CTL_DPDCK0_2_EN 0x1000
+#define MX51_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MX51_PLL_DP_CTL_ADE 0x800
+#define MX51_PLL_DP_CTL_REF_CLK_DIV 0x400
+#define MX51_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
+#define MX51_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
+#define MX51_PLL_DP_CTL_HFSM 0x80
+#define MX51_PLL_DP_CTL_PRE 0x40
+#define MX51_PLL_DP_CTL_UPEN 0x20
+#define MX51_PLL_DP_CTL_RST 0x10
+#define MX51_PLL_DP_CTL_RCP 0x8
+#define MX51_PLL_DP_CTL_PLM 0x4
+#define MX51_PLL_DP_CTL_BRM0 0x2
+#define MX51_PLL_DP_CTL_LRF 0x1
+
+#define MX51_PLL_DP_CONFIG_BIST 0x8
+#define MX51_PLL_DP_CONFIG_SJC_CE 0x4
+#define MX51_PLL_DP_CONFIG_AREN 0x2
+#define MX51_PLL_DP_CONFIG_LDREQ 0x1
+
+#define MX51_PLL_DP_OP_MFI_OFFSET 4
+#define MX51_PLL_DP_OP_MFI_MASK (0xF << 4)
+#define MX51_PLL_DP_OP_PDF_OFFSET 0
+#define MX51_PLL_DP_OP_PDF_MASK 0xF
+
+#define MX51_PLL_DP_MFD_OFFSET 0
+#define MX51_PLL_DP_MFD_MASK 0x07FFFFFF
+
+#define MX51_PLL_DP_MFN_OFFSET 0x0
+#define MX51_PLL_DP_MFN_MASK 0x07FFFFFF
+
+#define MX51_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
+#define MX51_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
+#define MX51_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MX51_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
+
+#define MX51_PLL_DP_DESTAT_TOG_SEL (1 << 31)
+#define MX51_PLL_DP_DESTAT_MFN 0x07FFFFFF
+
+/* Assuming 24MHz input clock with doubler ON */
+/* MFI PDF */
+#define MX51_PLL_DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
+#define MX51_PLL_DP_MFD_850 (48 - 1)
+#define MX51_PLL_DP_MFN_850 41
+
+#define MX51_PLL_DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
+#define MX51_PLL_DP_MFD_800 (3 - 1)
+#define MX51_PLL_DP_MFN_800 1
+
+#define MX51_PLL_DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
+#define MX51_PLL_DP_MFD_700 (24 - 1)
+#define MX51_PLL_DP_MFN_700 7
+
+#define MX51_PLL_DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
+#define MX51_PLL_DP_MFD_665 (96 - 1)
+#define MX51_PLL_DP_MFN_665 89
+
+#define MX51_PLL_DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
+#define MX51_PLL_DP_MFD_532 (24 - 1)
+#define MX51_PLL_DP_MFN_532 13
+
+#define MX51_PLL_DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
+#define MX51_PLL_DP_MFD_400 (3 - 1)
+#define MX51_PLL_DP_MFN_400 1
+
+#define MX51_PLL_DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+#define MX51_PLL_DP_MFD_216 (4 - 1)
+#define MX51_PLL_DP_MFN_216 3
+
+/* Register addresses of CCM*/
+#define MX51_CCM_CCR 0x00
+#define MX51_CCM_CCDR 0x04
+#define MX51_CCM_CSR 0x08
+#define MX51_CCM_CCSR 0x0C
+#define MX51_CCM_CACRR 0x10
+#define MX51_CCM_CBCDR 0x14
+#define MX51_CCM_CBCMR 0x18
+#define MX51_CCM_CSCMR1 0x1C
+#define MX51_CCM_CSCMR2 0x20
+#define MX51_CCM_CSCDR1 0x24
+#define MX51_CCM_CS1CDR 0x28
+#define MX51_CCM_CS2CDR 0x2C
+#define MX51_CCM_CDCDR 0x30
+#define MX51_CCM_CHSCDR 0x34
+#define MX51_CCM_CSCDR2 0x38
+#define MX51_CCM_CSCDR3 0x3C
+#define MX51_CCM_CSCDR4 0x40
+#define MX51_CCM_CWDR 0x44
+#define MX51_CCM_CDHIPR 0x48
+#define MX51_CCM_CDCR 0x4C
+#define MX51_CCM_CTOR 0x50
+#define MX51_CCM_CLPCR 0x54
+#define MX51_CCM_CISR 0x58
+#define MX51_CCM_CIMR 0x5C
+#define MX51_CCM_CCOSR 0x60
+#define MX51_CCM_CGPR 0x64
+#define MX51_CCM_CCGR0 0x68
+#define MX51_CCM_CCGR1 0x6C
+#define MX51_CCM_CCGR2 0x70
+#define MX51_CCM_CCGR3 0x74
+#define MX51_CCM_CCGR4 0x78
+#define MX51_CCM_CCGR5 0x7C
+#define MX51_CCM_CCGR6 0x80
+#define MX51_CCM_CMEOR 0x84
+
+/* Define the bits in register CCR */
+#define MX51_CCM_CCR_COSC_EN (1 << 12)
+#define MX51_CCM_CCR_FPM_MULT_MASK (1 << 11)
+#define MX51_CCM_CCR_CAMP2_EN (1 << 10)
+#define MX51_CCM_CCR_CAMP1_EN (1 << 9)
+#define MX51_CCM_CCR_FPM_EN (1 << 8)
+#define MX51_CCM_CCR_OSCNT_OFFSET (0)
+#define MX51_CCM_CCR_OSCNT_MASK (0xFF)
+
+/* Define the bits in register CCDR */
+#define MX51_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
+#define MX51_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+#define MX51_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MX51_CCM_CSR_COSR_READY (1 << 5)
+#define MX51_CCM_CSR_LVS_VALUE (1 << 4)
+#define MX51_CCM_CSR_CAMP2_READY (1 << 3)
+#define MX51_CCM_CSR_CAMP1_READY (1 << 2)
+#define MX51_CCM_CSR_FPM_READY (1 << 1)
+#define MX51_CCM_CSR_REF_EN_B (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MX51_CCM_CCSR_LP_APM_SEL (0x1 << 9)
+#define MX51_CCM_CCSR_STEP_SEL_OFFSET (7)
+#define MX51_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MX51_CCM_CCSR_PLL2_PODF_OFFSET (5)
+#define MX51_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
+#define MX51_CCM_CCSR_PLL3_PODF_OFFSET (3)
+#define MX51_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
+#define MX51_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
+#define MX51_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
+#define MX51_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MX51_CCM_CACRR_ARM_PODF_OFFSET (0)
+#define MX51_CCM_CACRR_ARM_PODF_MASK (0x7)
+
+/* Define the bits in register CBCDR */
+#define MX51_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
+#define MX51_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+#define MX51_CCM_CBCDR_DDR_HF_SEL_OFFSET (30)
+#define MX51_CCM_CBCDR_DDR_HF_SEL (0x1 << 30)
+#define MX51_CCM_CBCDR_DDR_PODF_OFFSET (27)
+#define MX51_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
+#define MX51_CCM_CBCDR_EMI_PODF_OFFSET (22)
+#define MX51_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MX51_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
+#define MX51_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
+#define MX51_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
+#define MX51_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
+#define MX51_CCM_CBCDR_NFC_PODF_OFFSET (13)
+#define MX51_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MX51_CCM_CBCDR_AHB_PODF_OFFSET (10)
+#define MX51_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MX51_CCM_CBCDR_IPG_PODF_OFFSET (8)
+#define MX51_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MX51_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
+#define MX51_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
+#define MX51_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
+#define MX51_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
+#define MX51_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
+#define MX51_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
+
+/* Define the bits in register CBCMR */
+#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
+#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
+#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MX51_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
+#define MX51_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
+#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
+#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
+#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MX51_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
+#define MX51_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
+#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14)
+#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14)
+#define MX51_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
+#define MX51_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
+#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
+#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
+#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
+#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
+#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
+#define MX51_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
+#define MX51_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
+#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
+#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MX51_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+#define MX51_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
+#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
+#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
+#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
+#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MX51_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
+#define MX51_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
+#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
+#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
+#define MX51_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
+#define MX51_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
+#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
+#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
+#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MX51_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
+#define MX51_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
+
+/* Define the bits in register CSCMR2 */
+#define MX51_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3)
+#define MX51_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3))
+#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
+#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
+#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
+#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
+#define MX51_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
+#define MX51_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
+#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
+#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
+#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
+#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
+#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
+#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
+#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
+#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
+#define MX51_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
+#define MX51_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
+#define MX51_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
+#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
+#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
+#define MX51_CCM_CSCMR2_SPDIF1_COM (1 << 5)
+#define MX51_CCM_CSCMR2_SPDIF0_COM (1 << 4)
+#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
+#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
+#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
+#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
+
+/* Define the bits in register CSCDR1 */
+#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
+#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
+#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
+#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
+#define MX51_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
+#define MX51_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
+#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
+#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
+#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
+#define MX51_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
+#define MX51_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
+#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
+#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
+#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
+#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
+#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
+#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
+
+#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
+#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
+#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
+#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
+#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
+#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
+#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDCDR */
+#define MX51_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
+#define MX51_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
+#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
+#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
+#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
+#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
+#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
+#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
+#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
+#define MX51_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
+#define MX51_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
+#define MX51_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
+#define MX51_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
+#define MX51_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
+#define MX51_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
+
+/* Define the bits in register CHSCCDR */
+#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
+#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
+#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
+#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
+#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
+#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
+#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
+#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CSCDR2 */
+#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
+#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
+#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
+#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+#define MX51_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
+#define MX51_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
+#define MX51_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
+#define MX51_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
+#define MX51_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
+#define MX51_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
+#define MX51_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
+#define MX51_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR3 */
+#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
+#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
+#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
+#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
+#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
+#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
+#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
+#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR4 */
+#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
+#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
+#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
+#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
+#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
+#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
+#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
+#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDHIPR */
+#define MX51_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
+#define MX51_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8)
+#define MX51_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7)
+#define MX51_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
+#define MX51_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
+#define MX51_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
+#define MX51_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
+#define MX51_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
+#define MX51_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
+#define MX51_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
+
+/* Define the bits in register CDCR */
+#define MX51_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
+#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
+#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
+
+/* Define the bits in register CLPCR */
+#define MX51_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
+#define MX51_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
+#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
+#define MX51_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
+#define MX51_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
+#define MX51_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+#define MX51_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
+#define MX51_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
+#define MX51_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+#define MX51_CCM_CLPCR_STBY_COUNT_OFFSET (9)
+#define MX51_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MX51_CCM_CLPCR_VSTBY (0x1 << 8)
+#define MX51_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
+#define MX51_CCM_CLPCR_SBYOS (0x1 << 6)
+#define MX51_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+#define MX51_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
+#define MX51_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MX51_CCM_CLPCR_LPM_OFFSET (0)
+#define MX51_CCM_CLPCR_LPM_MASK (0x3)
+
+/* Define the bits in register CISR */
+#define MX51_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
+#define MX51_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MX51_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
+#define MX51_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
+#define MX51_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
+#define MX51_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
+#define MX51_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
+#define MX51_CCM_CISR_COSC_READY (0x1 << 6)
+#define MX51_CCM_CISR_CKIH2_READY (0x1 << 5)
+#define MX51_CCM_CISR_CKIH_READY (0x1 << 4)
+#define MX51_CCM_CISR_FPM_READY (0x1 << 3)
+#define MX51_CCM_CISR_LRF_PLL3 (0x1 << 2)
+#define MX51_CCM_CISR_LRF_PLL2 (0x1 << 1)
+#define MX51_CCM_CISR_LRF_PLL1 (0x1)
+
+/* Define the bits in register CIMR */
+#define MX51_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
+#define MX51_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MX51_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
+#define MX51_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
+#define MX51_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
+#define MX51_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
+#define MX51_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
+#define MX51_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
+#define MX51_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
+#define MX51_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
+#define MX51_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
+#define MX51_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
+#define MX51_CCM_CIMR_MASK_LRF_PLL1 (0x1)
+
+/* Define the bits in register CCOSR */
+#define MX51_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
+#define MX51_CCM_CCOSR_CKO2_DIV_OFFSET (21)
+#define MX51_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MX51_CCM_CCOSR_CKO2_SEL_OFFSET (16)
+#define MX51_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MX51_CCM_CCOSR_CKOL_EN (0x1 << 7)
+#define MX51_CCM_CCOSR_CKOL_DIV_OFFSET (4)
+#define MX51_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MX51_CCM_CCOSR_CKOL_SEL_OFFSET (0)
+#define MX51_CCM_CCOSR_CKOL_SEL_MASK (0xF)
+
+/* Define the bits in registers CGPR */
+#define MX51_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
+#define MX51_CCM_CGPR_FPM_SEL (0x1 << 3)
+#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
+#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
+
+/* Define the bits in registers CCGRx */
+#define MX51_CCM_CCGR_CG_MASK 0x3
+#define MX51_CCM_CCGR_MOD_OFF 0x0
+#define MX51_CCM_CCGR_MOD_ON 0x3
+#define MX51_CCM_CCGR_MOD_IDLE 0x1
+
+#define MX51_CCM_CCGR0_CG15_OFFSET 30
+#define MX51_CCM_CCGR0_CG15_MASK (0x3 << 30)
+#define MX51_CCM_CCGR0_CG14_OFFSET 28
+#define MX51_CCM_CCGR0_CG14_MASK (0x3 << 28)
+#define MX51_CCM_CCGR0_CG13_OFFSET 26
+#define MX51_CCM_CCGR0_CG13_MASK (0x3 << 26)
+#define MX51_CCM_CCGR0_CG12_OFFSET 24
+#define MX51_CCM_CCGR0_CG12_MASK (0x3 << 24)
+#define MX51_CCM_CCGR0_CG11_OFFSET 22
+#define MX51_CCM_CCGR0_CG11_MASK (0x3 << 22)
+#define MX51_CCM_CCGR0_CG10_OFFSET 20
+#define MX51_CCM_CCGR0_CG10_MASK (0x3 << 20)
+#define MX51_CCM_CCGR0_CG9_OFFSET 18
+#define MX51_CCM_CCGR0_CG9_MASK (0x3 << 18)
+#define MX51_CCM_CCGR0_CG8_OFFSET 16
+#define MX51_CCM_CCGR0_CG8_MASK (0x3 << 16)
+#define MX51_CCM_CCGR0_CG7_OFFSET 14
+#define MX51_CCM_CCGR0_CG6_OFFSET 12
+#define MX51_CCM_CCGR0_CG5_OFFSET 10
+#define MX51_CCM_CCGR0_CG5_MASK (0x3 << 10)
+#define MX51_CCM_CCGR0_CG4_OFFSET 8
+#define MX51_CCM_CCGR0_CG4_MASK (0x3 << 8)
+#define MX51_CCM_CCGR0_CG3_OFFSET 6
+#define MX51_CCM_CCGR0_CG3_MASK (0x3 << 6)
+#define MX51_CCM_CCGR0_CG2_OFFSET 4
+#define MX51_CCM_CCGR0_CG2_MASK (0x3 << 4)
+#define MX51_CCM_CCGR0_CG1_OFFSET 2
+#define MX51_CCM_CCGR0_CG1_MASK (0x3 << 2)
+#define MX51_CCM_CCGR0_CG0_OFFSET 0
+#define MX51_CCM_CCGR0_CG0_MASK 0x3
+
+#define MX51_CCM_CCGR1_CG15_OFFSET 30
+#define MX51_CCM_CCGR1_CG14_OFFSET 28
+#define MX51_CCM_CCGR1_CG13_OFFSET 26
+#define MX51_CCM_CCGR1_CG12_OFFSET 24
+#define MX51_CCM_CCGR1_CG11_OFFSET 22
+#define MX51_CCM_CCGR1_CG10_OFFSET 20
+#define MX51_CCM_CCGR1_CG9_OFFSET 18
+#define MX51_CCM_CCGR1_CG8_OFFSET 16
+#define MX51_CCM_CCGR1_CG7_OFFSET 14
+#define MX51_CCM_CCGR1_CG6_OFFSET 12
+#define MX51_CCM_CCGR1_CG5_OFFSET 10
+#define MX51_CCM_CCGR1_CG4_OFFSET 8
+#define MX51_CCM_CCGR1_CG3_OFFSET 6
+#define MX51_CCM_CCGR1_CG2_OFFSET 4
+#define MX51_CCM_CCGR1_CG1_OFFSET 2
+#define MX51_CCM_CCGR1_CG0_OFFSET 0
+
+#define MX51_CCM_CCGR2_CG15_OFFSET 30
+#define MX51_CCM_CCGR2_CG14_OFFSET 28
+#define MX51_CCM_CCGR2_CG13_OFFSET 26
+#define MX51_CCM_CCGR2_CG12_OFFSET 24
+#define MX51_CCM_CCGR2_CG11_OFFSET 22
+#define MX51_CCM_CCGR2_CG10_OFFSET 20
+#define MX51_CCM_CCGR2_CG9_OFFSET 18
+#define MX51_CCM_CCGR2_CG8_OFFSET 16
+#define MX51_CCM_CCGR2_CG7_OFFSET 14
+#define MX51_CCM_CCGR2_CG6_OFFSET 12
+#define MX51_CCM_CCGR2_CG5_OFFSET 10
+#define MX51_CCM_CCGR2_CG4_OFFSET 8
+#define MX51_CCM_CCGR2_CG3_OFFSET 6
+#define MX51_CCM_CCGR2_CG2_OFFSET 4
+#define MX51_CCM_CCGR2_CG1_OFFSET 2
+#define MX51_CCM_CCGR2_CG0_OFFSET 0
+
+#define MX51_CCM_CCGR3_CG15_OFFSET 30
+#define MX51_CCM_CCGR3_CG14_OFFSET 28
+#define MX51_CCM_CCGR3_CG13_OFFSET 26
+#define MX51_CCM_CCGR3_CG12_OFFSET 24
+#define MX51_CCM_CCGR3_CG11_OFFSET 22
+#define MX51_CCM_CCGR3_CG10_OFFSET 20
+#define MX51_CCM_CCGR3_CG9_OFFSET 18
+#define MX51_CCM_CCGR3_CG8_OFFSET 16
+#define MX51_CCM_CCGR3_CG7_OFFSET 14
+#define MX51_CCM_CCGR3_CG6_OFFSET 12
+#define MX51_CCM_CCGR3_CG5_OFFSET 10
+#define MX51_CCM_CCGR3_CG4_OFFSET 8
+#define MX51_CCM_CCGR3_CG3_OFFSET 6
+#define MX51_CCM_CCGR3_CG2_OFFSET 4
+#define MX51_CCM_CCGR3_CG1_OFFSET 2
+#define MX51_CCM_CCGR3_CG0_OFFSET 0
+
+#define MX51_CCM_CCGR4_CG15_OFFSET 30
+#define MX51_CCM_CCGR4_CG14_OFFSET 28
+#define MX51_CCM_CCGR4_CG13_OFFSET 26
+#define MX51_CCM_CCGR4_CG12_OFFSET 24
+#define MX51_CCM_CCGR4_CG11_OFFSET 22
+#define MX51_CCM_CCGR4_CG10_OFFSET 20
+#define MX51_CCM_CCGR4_CG9_OFFSET 18
+#define MX51_CCM_CCGR4_CG8_OFFSET 16
+#define MX51_CCM_CCGR4_CG7_OFFSET 14
+#define MX51_CCM_CCGR4_CG6_OFFSET 12
+#define MX51_CCM_CCGR4_CG5_OFFSET 10
+#define MX51_CCM_CCGR4_CG4_OFFSET 8
+#define MX51_CCM_CCGR4_CG3_OFFSET 6
+#define MX51_CCM_CCGR4_CG2_OFFSET 4
+#define MX51_CCM_CCGR4_CG1_OFFSET 2
+#define MX51_CCM_CCGR4_CG0_OFFSET 0
+
+#define MX51_CCM_CCGR5_CG15_OFFSET 30
+#define MX51_CCM_CCGR5_CG14_OFFSET 28
+#define MX51_CCM_CCGR5_CG14_MASK (0x3 << 28)
+#define MX51_CCM_CCGR5_CG13_OFFSET 26
+#define MX51_CCM_CCGR5_CG13_MASK (0x3 << 26)
+#define MX51_CCM_CCGR5_CG12_OFFSET 24
+#define MX51_CCM_CCGR5_CG12_MASK (0x3 << 24)
+#define MX51_CCM_CCGR5_CG11_OFFSET 22
+#define MX51_CCM_CCGR5_CG11_MASK (0x3 << 22)
+#define MX51_CCM_CCGR5_CG10_OFFSET 20
+#define MX51_CCM_CCGR5_CG10_MASK (0x3 << 20)
+#define MX51_CCM_CCGR5_CG9_OFFSET 18
+#define MX51_CCM_CCGR5_CG9_MASK (0x3 << 18)
+#define MX51_CCM_CCGR5_CG8_OFFSET 16
+#define MX51_CCM_CCGR5_CG8_MASK (0x3 << 16)
+#define MX51_CCM_CCGR5_CG7_OFFSET 14
+#define MX51_CCM_CCGR5_CG7_MASK (0x3 << 14)
+#define MX51_CCM_CCGR5_CG6_OFFSET 12
+#define MX51_CCM_CCGR5_CG5_OFFSET 10
+#define MX51_CCM_CCGR5_CG4_OFFSET 8
+#define MX51_CCM_CCGR5_CG3_OFFSET 6
+#define MX51_CCM_CCGR5_CG2_OFFSET 4
+#define MX51_CCM_CCGR5_CG2_MASK (0x3 << 4)
+#define MX51_CCM_CCGR5_CG1_OFFSET 2
+#define MX51_CCM_CCGR5_CG0_OFFSET 0
+#define MX51_CCM_CCGR6_CG7_OFFSET 14
+#define MX51_CCM_CCGR6_CG7_MASK (0x3 << 14)
+#define MX51_CCM_CCGR6_CG6_OFFSET 12
+#define MX51_CCM_CCGR6_CG6_MASK (0x3 << 12)
+#define MX51_CCM_CCGR6_CG5_OFFSET 10
+#define MX51_CCM_CCGR6_CG5_MASK (0x3 << 10)
+#define MX51_CCM_CCGR6_CG4_OFFSET 8
+#define MX51_CCM_CCGR6_CG4_MASK (0x3 << 8)
+#define MX51_CCM_CCGR6_CG3_OFFSET 6
+#define MX51_CCM_CCGR6_CG2_OFFSET 4
+#define MX51_CCM_CCGR6_CG1_OFFSET 2
+#define MX51_CCM_CCGR6_CG0_OFFSET 0
+
+/* CORTEXA8 platform */
+#define MX51_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0)
+#define MX51_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4)
+#define MX51_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8)
+#define MX51_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC)
+#define MX51_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10)
+#define MX51_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14)
+#define MX51_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18)
+#define MX51_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20)
+#define MX51_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24)
+
+/* DVFS CORE */
+#define MX51_DVFSTHRS (MX51_DVFS_CORE_BASE + 0x00)
+#define MX51_DVFSCOUN (MX51_DVFS_CORE_BASE + 0x04)
+#define MX51_DVFSSIG1 (MX51_DVFS_CORE_BASE + 0x08)
+#define MX51_DVFSSIG0 (MX51_DVFS_CORE_BASE + 0x0C)
+#define MX51_DVFSGPC0 (MX51_DVFS_CORE_BASE + 0x10)
+#define MX51_DVFSGPC1 (MX51_DVFS_CORE_BASE + 0x14)
+#define MX51_DVFSGPBT (MX51_DVFS_CORE_BASE + 0x18)
+#define MX51_DVFSEMAC (MX51_DVFS_CORE_BASE + 0x1C)
+#define MX51_DVFSCNTR (MX51_DVFS_CORE_BASE + 0x20)
+#define MX51_DVFSLTR0_0 (MX51_DVFS_CORE_BASE + 0x24)
+#define MX51_DVFSLTR0_1 (MX51_DVFS_CORE_BASE + 0x28)
+#define MX51_DVFSLTR1_0 (MX51_DVFS_CORE_BASE + 0x2C)
+#define MX51_DVFSLTR1_1 (MX51_DVFS_CORE_BASE + 0x30)
+#define MX51_DVFSPT0 (MX51_DVFS_CORE_BASE + 0x34)
+#define MX51_DVFSPT1 (MX51_DVFS_CORE_BASE + 0x38)
+#define MX51_DVFSPT2 (MX51_DVFS_CORE_BASE + 0x3C)
+#define MX51_DVFSPT3 (MX51_DVFS_CORE_BASE + 0x40)
+
+/* GPC */
+#define MX51_GPC_CNTR (MX51_GPC_BASE + 0x0)
+#define MX51_GPC_PGR (MX51_GPC_BASE + 0x4)
+#define MX51_GPC_VCR (MX51_GPC_BASE + 0x8)
+#define MX51_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
+#define MX51_GPC_NEON (MX51_GPC_BASE + 0x10)
+#define MX51_GPC_PGR_ARMPG_OFFSET 8
+#define MX51_GPC_PGR_ARMPG_MASK (3 << 8)
+
+/* PGC */
+#define MX51_PGC_IPU_PGCR (MX51_PGC_IPU_BASE + 0x0)
+#define MX51_PGC_IPU_PGSR (MX51_PGC_IPU_BASE + 0xC)
+#define MX51_PGC_VPU_PGCR (MX51_PGC_VPU_BASE + 0x0)
+#define MX51_PGC_VPU_PGSR (MX51_PGC_VPU_BASE + 0xC)
+#define MX51_PGC_GPU_PGCR (MX51_PGC_GPU_BASE + 0x0)
+#define MX51_PGC_GPU_PGSR (MX51_PGC_GPU_BASE + 0xC)
+
+#define MX51_PGCR_PCR 1
+#define MX51_SRPGCR_PCR 1
+#define MX51_EMPGCR_PCR 1
+#define MX51_PGSR_PSR 1
+
+
+#define MX51_CORTEXA8_PLAT_LPC_DSM (1 << 0)
+#define MX51_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
+
+/* SRPG */
+#define MX51_SRPG_NEON_SRPGCR (MX51_SRPG_NEON_BASE + 0x0)
+#define MX51_SRPG_NEON_PUPSCR (MX51_SRPG_NEON_BASE + 0x4)
+#define MX51_SRPG_NEON_PDNSCR (MX51_SRPG_NEON_BASE + 0x8)
+
+#define MX51_SRPG_ARM_SRPGCR (MX51_SRPG_ARM_BASE + 0x0)
+#define MX51_SRPG_ARM_PUPSCR (MX51_SRPG_ARM_BASE + 0x4)
+#define MX51_SRPG_ARM_PDNSCR (MX51_SRPG_ARM_BASE + 0x8)
+
+#define MX51_SRPG_EMPGC0_SRPGCR (MX51_SRPG_EMPGC0_BASE + 0x0)
+#define MX51_SRPG_EMPGC0_PUPSCR (MX51_SRPG_EMPGC0_BASE + 0x4)
+#define MX51_SRPG_EMPGC0_PDNSCR (MX51_SRPG_EMPGC0_BASE + 0x8)
+
+#define MX51_SRPG_EMPGC1_SRPGCR (MX51_SRPG_EMPGC1_BASE + 0x0)
+#define MX51_SRPG_EMPGC1_PUPSCR (MX51_SRPG_EMPGC1_BASE + 0x4)
+#define MX51_SRPG_EMPGC1_PDNSCR (MX51_SRPG_EMPGC1_BASE + 0x8)
+
+#define MX51_SRPG_MEGAMIX_SRPGCR (MX51_SRPG_MEGAMIX_BASE + 0x0)
+#define MX51_SRPG_MEGAMIX_PUPSCR (MX51_SRPG_MEGAMIX_BASE + 0x4)
+#define MX51_SRPG_MEGAMIX_PDNSCR (MX51_SRPG_MEGAMIX_BASE + 0x8)
+
+#define MX51_SRPGC_EMI_SRPGCR (MX51_SRPGC_EMI_BASE + 0x0)
+#define MX51_SRPGC_EMI_PUPSCR (MX51_SRPGC_EMI_BASE + 0x4)
+#define MX51_SRPGC_EMI_PDNSCR (MX51_SRPGC_EMI_BASE + 0x8)
+
+#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
+
+
diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h
index 76ab4a5..5b590a2 100644
--- a/arch/arm/mach-imx/include/mach/clock.h
+++ b/arch/arm/mach-imx/include/mach/clock.h
@@ -28,8 +28,11 @@
ulong imx_get_uartclk(void);
ulong imx_get_lcdclk(void);
ulong imx_get_i2cclk(void);
+ulong imx_get_mmcclk(void);
int imx_clko_set_div(int div);
void imx_clko_set_src(int src);
+void imx_dump_clocks(void);
+
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index d15f52b..fe74cb6 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -18,9 +18,11 @@
#define ESDCTL0_ROW13 (2 << 24)
#define ESDCTL0_ROW14 (3 << 24)
#define ESDCTL0_ROW15 (4 << 24)
+#define ESDCTL0_ROW_MASK (7 << 24)
#define ESDCTL0_COL8 (0 << 20)
#define ESDCTL0_COL9 (1 << 20)
#define ESDCTL0_COL10 (2 << 20)
+#define ESDCTL0_COL_MASK (3 << 20)
#define ESDCTL0_DSIZ_31_16 (0 << 16)
#define ESDCTL0_DSIZ_15_0 (1 << 16)
#define ESDCTL0_DSIZ_31_0 (2 << 16)
@@ -32,3 +34,89 @@
#define ESDCTL0_FP (1 << 8)
#define ESDCTL0_BL (1 << 7)
+#define ESDMISC_RST 0x00000002
+#define ESDMISC_MDDR_EN 0x00000004
+#define ESDMISC_MDDR_DIS 0x00000000
+#define ESDMISC_MDDR_DL_RST 0x00000008
+#define ESDMISC_MDDR_MDIS 0x00000010
+#define ESDMISC_LHD 0x00000020
+#define ESDMISC_SDRAMRDY 0x80000000
+
+#define ESDCFGx_tXP_MASK 0x00600000
+#define ESDCFGx_tXP_1 0x00000000
+#define ESDCFGx_tXP_2 0x00200000
+#define ESDCFGx_tXP_3 0x00400000
+#define ESDCFGx_tXP_4 0x00600000
+
+#define ESDCFGx_tWTR_MASK 0x00100000
+#define ESDCFGx_tWTR_1 0x00000000
+#define ESDCFGx_tWTR_2 0x00100000
+
+#define ESDCFGx_tRP_MASK 0x000c0000
+#define ESDCFGx_tRP_1 0x00000000
+#define ESDCFGx_tRP_2 0x00040000
+#define ESDCFGx_tRP_3 0x00080000
+#define ESDCFGx_tRP_4 0x000c0000
+
+
+#define ESDCFGx_tMRD_MASK 0x00030000
+#define ESDCFGx_tMRD_1 0x00000000
+#define ESDCFGx_tMRD_2 0x00010000
+#define ESDCFGx_tMRD_3 0x00020000
+#define ESDCFGx_tMRD_4 0x00030000
+
+
+#define ESDCFGx_tWR_MASK 0x00008000
+#define ESDCFGx_tWR_1_2 0x00000000
+#define ESDCFGx_tWR_2_3 0x00008000
+
+#define ESDCFGx_tRAS_MASK 0x00007000
+#define ESDCFGx_tRAS_1 0x00000000
+#define ESDCFGx_tRAS_2 0x00001000
+#define ESDCFGx_tRAS_3 0x00002000
+#define ESDCFGx_tRAS_4 0x00003000
+#define ESDCFGx_tRAS_5 0x00004000
+#define ESDCFGx_tRAS_6 0x00005000
+#define ESDCFGx_tRAS_7 0x00006000
+#define ESDCFGx_tRAS_8 0x00007000
+
+
+#define ESDCFGx_tRRD_MASK 0x00000c00
+#define ESDCFGx_tRRD_1 0x00000000
+#define ESDCFGx_tRRD_2 0x00000400
+#define ESDCFGx_tRRD_3 0x00000800
+#define ESDCFGx_tRRD_4 0x00000c00
+
+
+#define ESDCFGx_tCAS_MASK 0x00000300
+#define ESDCFGx_tCAS_2 0x00000200
+#define ESDCFGx_tCAS_3 0x00000300
+
+#define ESDCFGx_tRCD_MASK 0x00000070
+#define ESDCFGx_tRCD_1 0x00000000
+#define ESDCFGx_tRCD_2 0x00000010
+#define ESDCFGx_tRCD_3 0x00000020
+#define ESDCFGx_tRCD_4 0x00000030
+#define ESDCFGx_tRCD_5 0x00000040
+#define ESDCFGx_tRCD_6 0x00000050
+#define ESDCFGx_tRCD_7 0x00000060
+#define ESDCFGx_tRCD_8 0x00000070
+
+#define ESDCFGx_tRC_MASK 0x0000000f
+#define ESDCFGx_tRC_20 0x00000000
+#define ESDCFGx_tRC_2 0x00000001
+#define ESDCFGx_tRC_3 0x00000002
+#define ESDCFGx_tRC_4 0x00000003
+#define ESDCFGx_tRC_5 0x00000004
+#define ESDCFGx_tRC_6 0x00000005
+#define ESDCFGx_tRC_7 0x00000006
+#define ESDCFGx_tRC_8 0x00000007
+#define ESDCFGx_tRC_9 0x00000008
+#define ESDCFGx_tRC_10 0x00000009
+#define ESDCFGx_tRC_11 0x0000000a
+#define ESDCFGx_tRC_12 0x0000000b
+#define ESDCFGx_tRC_13 0x0000000c
+#define ESDCFGx_tRC_14 0x0000000d
+//#define ESDCFGx_tRC_14 0x0000000e // 15 seems to not exist
+#define ESDCFGx_tRC_16 0x0000000f
+
diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h
index 4b89838..9ca838b 100644
--- a/arch/arm/mach-imx/include/mach/generic.h
+++ b/arch/arm/mach-imx/include/mach/generic.h
@@ -45,3 +45,9 @@
#define cpu_is_mx35() (0)
#endif
+#ifdef CONFIG_ARCH_IMX51
+#define cpu_is_mx51() (1)
+#else
+#define cpu_is_mx51() (0)
+#endif
+
diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h
index 06acddb..eb583a2 100644
--- a/arch/arm/mach-imx/include/mach/imx-nand.h
+++ b/arch/arm/mach-imx/include/mach/imx-nand.h
@@ -8,8 +8,8 @@
struct imx_nand_platform_data {
int width;
- int hw_ecc:1;
- int flash_bbt:1;
+ unsigned int hw_ecc:1;
+ unsigned int flash_bbt:1;
};
#endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h
index 2cc49dd..605d320 100644
--- a/arch/arm/mach-imx/include/mach/imx-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx-regs.h
@@ -51,6 +51,8 @@
# include
#elif defined CONFIG_ARCH_IMX25
# include
+#elif defined CONFIG_ARCH_IMX51
+#include
#else
# error "unknown i.MX soc type"
#endif
diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h
index 0d6fd92..f940cdb 100644
--- a/arch/arm/mach-imx/include/mach/imx1-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx1-regs.h
@@ -40,14 +40,6 @@
#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
-/* Watchdog Registers*/
-#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
-#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x01
-
/* SYSCTRL Registers */
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h
index 6d64b81..a2c4d03 100644
--- a/arch/arm/mach-imx/include/mach/imx21-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx21-regs.h
@@ -72,14 +72,6 @@
#define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */
#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
-/* Watchdog Registers*/
-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
-#define WRSR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Reset Status Register */
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x04
-
/* PLL registers */
#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h
index f4354ba..e87d5bf 100644
--- a/arch/arm/mach-imx/include/mach/imx27-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx27-regs.h
@@ -82,14 +82,6 @@
#include "esdctl.h"
-/* Watchdog Registers*/
-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x04
-
/* PLL registers */
#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
@@ -227,14 +219,6 @@
#define ESDCFG_TWTR (1 << 20)
#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
-#define ESDMISC_RST (1 << 1)
-#define ESDMISC_MDDREN (1 << 2)
-#define ESDMISC_MDDR_DL_RST (1 << 3)
-#define ESDMISC_MDDR_MDIS (1 << 4)
-#define ESDMISC_LHD (1 << 5)
-#define ESDMISC_MA10_SHARE (1 << 6)
-#define ESDMISC_SDRAM_RDY (1 << 6)
-
/*
* Definitions for the clocksource driver
*/
diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h
index d2304ec..536bf0d 100644
--- a/arch/arm/mach-imx/include/mach/imx31-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx31-regs.h
@@ -120,16 +120,6 @@
#endif
/*
- * Watchdog Registers
- */
-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x04
-
-/*
* Clock Controller Module (CCM)
*/
#define IMX_CCM_BASE 0x53f80000
diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h
index 5cfb788..89ca7ea 100644
--- a/arch/arm/mach-imx/include/mach/imx35-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx35-regs.h
@@ -51,6 +51,8 @@
#define IMX_SDHC1_BASE 0x53FB4000
#define IMX_SDHC2_BASE 0x53FB8000
#define IMX_SDHC3_BASE 0x53FBC000
+#define IMX_OTG_BASE 0x53FF4000
+#define IMX_WDOG_BASE 0x53fdc000
/*
* Clock Controller Module (CCM)
@@ -73,6 +75,8 @@
#define CCM_CGR1_FEC_SHIFT 0
#define CCM_CGR1_I2C1_SHIFT 10
+#define CCM_CGR1_SDHC1_SHIFT 26
+#define CCM_CGR2_USB_SHIFT 22
#define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
#define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
@@ -132,15 +136,5 @@
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
-/*
- * Watchdog Registers
- */
-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
-
-/* important definition of some bits of WCR */
-#define WCR_WDE 0x04
-
#endif /* __ASM_ARCH_MX35_REGS_H */
diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h
new file mode 100644
index 0000000..1719a78
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx51-regs.h
@@ -0,0 +1,124 @@
+#ifndef __MACH_IMX51_REGS_H
+#define __MACH_IMX51_REGS_H
+
+#define IMX_TIM1_BASE 0x73fa0000
+#define IMX_WDT_BASE 0x73f98000
+#define IMX_IOMUXC_BASE 0x73fa8000
+
+#define GPT_TCTL 0x00
+#define GPT_TPRER 0x04
+#define GPT_TCMP 0x10
+#define GPT_TCR 0x1c
+#define GPT_TCN 0x24
+#define GPT_TSTAT 0x08
+
+/* Part 2: Bitfields */
+#define TCTL_SWR (1<<15) /* Software reset */
+#define TCTL_FRR (1<<9) /* Freerun / restart */
+#define TCTL_CAP (3<<6) /* Capture Edge */
+#define TCTL_OM (1<<5) /* output mode */
+#define TCTL_IRQEN (1<<4) /* interrupt enable */
+#define TCTL_CLKSOURCE (6) /* Clock source bit position */
+#define TCTL_TEN (1) /* Timer enable */
+#define TPRER_PRES (0xff) /* Prescale */
+#define TSTAT_CAPT (1<<1) /* Capture event */
+#define TSTAT_COMP (1) /* Compare event */
+
+#define MX51_IROM_BASE_ADDR 0x0
+
+/*
+ * AIPS 1
+ */
+#define MX51_AIPS1_BASE_ADDR 0x73F00000
+
+#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
+#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
+#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
+#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
+#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
+#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
+#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
+#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
+#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
+#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
+#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
+#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
+#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
+#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
+#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
+#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
+#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
+#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
+#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
+#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
+
+/*
+ * AIPS 2
+ */
+#define MX51_AIPS2_BASE_ADDR 0x83F00000
+
+#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
+#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
+#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
+#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
+#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
+#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
+#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
+#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
+#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
+#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
+#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
+#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
+#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
+#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
+#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
+#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
+#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
+#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
+#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
+#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
+#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
+#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
+#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
+#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
+#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
+#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
+#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
+#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
+#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
+#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
+#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
+#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
+
+#define MX51_SPBA0_BASE_ADDR 0x70000000
+#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000)
+
+/*
+ * Memory regions and CS
+ */
+#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
+#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
+#define MX51_CSD0_BASE_ADDR 0x90000000
+#define MX51_CSD1_BASE_ADDR 0xA0000000
+#define MX51_CS0_BASE_ADDR 0xB0000000
+#define MX51_CS1_BASE_ADDR 0xB8000000
+#define MX51_CS2_BASE_ADDR 0xC0000000
+#define MX51_CS3_BASE_ADDR 0xC8000000
+#define MX51_CS4_BASE_ADDR 0xCC000000
+#define MX51_CS5_BASE_ADDR 0xCE000000
+
+/* silicon revisions specific to i.MX51 */
+#define MX51_CHIP_REV_1_0 0x10
+#define MX51_CHIP_REV_1_1 0x11
+#define MX51_CHIP_REV_1_2 0x12
+#define MX51_CHIP_REV_1_3 0x13
+#define MX51_CHIP_REV_2_0 0x20
+#define MX51_CHIP_REV_2_1 0x21
+#define MX51_CHIP_REV_2_2 0x22
+#define MX51_CHIP_REV_2_3 0x23
+#define MX51_CHIP_REV_3_0 0x30
+#define MX51_CHIP_REV_3_1 0x31
+#define MX51_CHIP_REV_3_2 0x32
+
+#endif /* __MACH_IMX51_REGS_H */
+
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h b/arch/arm/mach-imx/include/mach/iomux-mx25.h
index a290a33..a8ca8f1 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx25.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx25.h
@@ -658,21 +658,21 @@
#define MX25_PAD_RW__EIM_RW IOMUX_PAD(0x278, 0x6c, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x6c, 4, 0x474, 0, NO_PAD_CTRL)
#define MX25_PAD_RW__GPIO25 IOMUX_PAD(0x278, 0x6c, 5, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CLK__CLK IOMUX_PAD(0x38c, 0x194, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_CLK__CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__MISO IOMUX_PAD(0x38c, 0x194, 1, 0x49c, 1, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__RDATA3 IOMUX_PAD(0x38c, 0x194, 2, 0x510, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__SDMA_DBG_STAT_0 IOMUX_PAD(0x38c, 0x194, 4, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__GPIO24 IOMUX_PAD(0x38c, 0x194, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__SLCDC_DATA1 IOMUX_PAD(0x38c, 0x194, 6, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CLK__TRACE11 IOMUX_PAD(0x38c, 0x194, 7, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_CMD__CMD IOMUX_PAD(0x388, 0x190, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_CMD__CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__MOSI IOMUX_PAD(0x388, 0x190, 1, 0x4a0, 1, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__RDATA2 IOMUX_PAD(0x388, 0x190, 2, 0x50c, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__SDMA_DBG_EVT_SEL IOMUX_PAD(0x388, 0x190, 4, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__GPIO23 IOMUX_PAD(0x388, 0x190, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__SLCDC_DATA0 IOMUX_PAD(0x388, 0x190, 6, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_CMD__TRACE10 IOMUX_PAD(0x388, 0x190, 7, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA0__DAT0 IOMUX_PAD(0x390, 0x198, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA0__DAT0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA0__SCLK IOMUX_PAD(0x390, 0x198, 1, 0x494, 1, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA0__TDATA2 IOMUX_PAD(0x390, 0x198, 2, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA0__AUD7_TXFS IOMUX_PAD(0x390, 0x198, 3, 0x47c, 0, NO_PAD_CTRL)
@@ -680,7 +680,7 @@
#define MX25_PAD_SD1_DATA0__GPIO25 IOMUX_PAD(0x390, 0x198, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA0__SLCDC_DATA2 IOMUX_PAD(0x390, 0x198, 6, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA0__TRACE12 IOMUX_PAD(0x390, 0x198, 7, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA1__DAT1 IOMUX_PAD(0x394, 0x19c, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA1__DAT1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__RDY IOMUX_PAD(0x394, 0x19c, 1, 0x498, 1, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__TDATA3 IOMUX_PAD(0x394, 0x19c, 2, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 3, 0x478, 0, NO_PAD_CTRL)
@@ -688,7 +688,7 @@
#define MX25_PAD_SD1_DATA1__GPIO26 IOMUX_PAD(0x394, 0x19c, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__SLCDC_DATA3 IOMUX_PAD(0x394, 0x19c, 6, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA1__TRACE13 IOMUX_PAD(0x394, 0x19c, 7, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA2__DAT2 IOMUX_PAD(0x398, 0x1a0, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA2__DAT2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__SS0 IOMUX_PAD(0x398, 0x1a0, 1, 0x4a4, 1, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__RX_CLK IOMUX_PAD(0x398, 0x1a0, 2, 0x514, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__AUD7_RXC IOMUX_PAD(0x398, 0x1a0, 3, 0, 0, NO_PAD_CTRL)
@@ -696,7 +696,7 @@
#define MX25_PAD_SD1_DATA2__GPIO27 IOMUX_PAD(0x398, 0x1a0, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__SLCDC_DATA4 IOMUX_PAD(0x398, 0x1a0, 6, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA2__TRACE14 IOMUX_PAD(0x398, 0x1a0, 7, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_SD1_DATA3__DAT3 IOMUX_PAD(0x39c, 0x1a4, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA3__DAT3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA3__SS1 IOMUX_PAD(0x39c, 0x1a4, 1, 0x4a8, 1, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA3__CRS IOMUX_PAD(0x39c, 0x1a4, 2, 0x508, 2, NO_PAD_CTRL)
#define MX25_PAD_SD1_DATA3__AUD7_RXFS IOMUX_PAD(0x39c, 0x1a4, 3, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h
index 993b141..23e448b 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx27.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h
@@ -28,6 +28,12 @@
#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
+#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
+#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
+#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
+#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
+#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
+#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h
index 8a56d86..ad7ff56 100644
--- a/arch/arm/mach-imx/include/mach/iomux-mx35.h
+++ b/arch/arm/mach-imx/include/mach/iomux-mx35.h
@@ -815,42 +815,42 @@
#define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0x10, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL)
#define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL)
#define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0x10, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL)
#define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0x10, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0x10, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0x10, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL)
-#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0x10, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
#define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL)
diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h
new file mode 100644
index 0000000..2901ee6
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/iomux-mx51.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option, NO_PAD_CTRL) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_IOMUX_MX51_H__
+#define __MACH_IOMUX_MX51_H__
+
+#include
+
+#define MX51_FEC_PAD_CTRL (PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRIVE_STRENGTH_HIGH)
+
+/*
+ * The naming convention for the pad modes is MX51_PAD___
+ * If or refers to a GPIO, it is named
+ * GPIO__ see also iomux-v3.h
+ */
+
+/* PAD MUX ALT INPSE PATH */
+#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7A8, 0x1C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7A8, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7A8, 0x24, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7A8, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7AC, 0x2C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7AC, 0x30, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7AC, 0x34, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7AC, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7B0, 0x3C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7B0, 0x40, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7B0, 0x44, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7B0, 0x48, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7BC, 0x4C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7BC, 0x50, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7BC, 0x54, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7BC, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3F0, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3F4, 0x60, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3F8, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3FC, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40C, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41C, 0x88, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42C, 0x98, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xA0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xA4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43C, 0xA8, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xAC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xB0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44C, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xC0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45C, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xD0, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46C, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xDC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xE0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xE4, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47C, 0xE8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xEC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xF0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xF4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x52C, 0xF4, 3, 0x950, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48C, 0xF8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xFC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_RB4__NANDF_RB4 IOMUX_PAD(0x514, 0x12C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB5__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB6__FEC_RDATA0 IOMUX_PAD(0x5DC, 0x16C, 2, 0x958, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_RB7__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB7__FEC_TX_ER IOMUX_PAD(0x5E0, 0x138, 2, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0,MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54C, 0x164, 2, 0x96c, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 0, 0x0, 0, NO_PAD_CTRL)
+
+#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0, 0, MX51_FEC_PAD_CTRL)
+
+#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
+#endif /* __MACH_IOMUX_MX51_H__ */
+
diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h
index 1d660a0..198286a 100644
--- a/arch/arm/mach-imx/include/mach/iomux-v3.h
+++ b/arch/arm/mach-imx/include/mach/iomux-v3.h
@@ -84,13 +84,17 @@
#define PAD_CTL_OUTPUT_CMOS (0)
#define PAD_CTL_OUTPUT_OPEN_DRAIN (1 << 3)
-#define PAD_CTL_DRIVE_STRENGTH_NORM (0)
-#define PAD_CTL_DRIVE_STRENGTH_HIGH (1 << 1)
-#define PAD_CTL_DRIVE_STRENGTH_MAX (2 << 1)
+#define PAD_CTL_DRIVE_STRENGTH_LOW (0 << 1)
+#define PAD_CTL_DRIVE_STRENGTH_MED (1 << 1)
+#define PAD_CTL_DRIVE_STRENGTH_HIGH (2 << 1)
+#define PAD_CTL_DRIVE_STRENGTH_MAX (3 << 1)
#define PAD_CTL_SLEW_RATE_SLOW 0
#define PAD_CTL_SLEW_RATE_FAST 1
+#define PAD_CTL_DRV_VOT_LOW (0 << 13)
+#define PAD_CTL_DRV_VOT_HIGH (1 << 13)
+
/*
* setups a single pad:
* - reserves the pad so that it is not claimed by another driver
diff --git a/arch/arm/mach-imx/include/mach/usb.h b/arch/arm/mach-imx/include/mach/usb.h
new file mode 100644
index 0000000..5d6670d
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/usb.h
@@ -0,0 +1,14 @@
+#ifndef __MACH_USB_H_
+#define __MACH_USB_H_
+
+/* configuration bits for i.MX25 and i.MX35 */
+#define MX35_H1_SIC_SHIFT 21
+#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX35_H1_TLL_BIT (1 << 5)
+#define MX35_H1_USBTE_BIT (1 << 4)
+#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
+
+#endif /* __MACH_USB_H_*/
diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c
index 9605674..cb28e9f 100644
--- a/arch/arm/mach-imx/speed-imx25.c
+++ b/arch/arm/mach-imx/speed-imx25.c
@@ -82,7 +82,12 @@
return imx_get_perclk(6);
}
-int imx_dump_clocks(void)
+unsigned long imx_get_mmcclk(void)
+{
+ return imx_get_perclk(3);
+}
+
+void imx_dump_clocks(void)
{
printf("mpll: %10d Hz\n", imx_get_mpllclk());
printf("upll: %10d Hz\n", imx_get_upllclk());
@@ -92,7 +97,8 @@
printf("gpt: %10d Hz\n", imx_get_ipgclk());
printf("nand: %10d Hz\n", imx_get_perclk(8));
printf("lcd: %10d Hz\n", imx_get_perclk(7));
- return 0;
+ printf("i2c: %10d Hz\n", imx_get_perclk(6));
+ printf("sdhc1: %10d Hz\n", imx_get_perclk(3));
}
/*
diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c
index cdcd419..0a92d29 100644
--- a/arch/arm/mach-imx/speed-imx27.c
+++ b/arch/arm/mach-imx/speed-imx27.c
@@ -159,6 +159,11 @@
return imx_get_ipgclk();
}
+ulong imx_get_mmcclk(void)
+{
+ return imx_get_perclk2();
+}
+
void imx_dump_clocks(void)
{
uint32_t cid = CID;
diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c
index c5a31c7..8937ef1 100644
--- a/arch/arm/mach-imx/speed-imx35.c
+++ b/arch/arm/mach-imx/speed-imx35.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include
unsigned long imx_get_mpllclk(void)
@@ -27,7 +28,7 @@
return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ);
}
-unsigned long imx_get_ppllclk(void)
+static unsigned long imx_get_ppllclk(void)
{
ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL);
return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ);
@@ -56,7 +57,7 @@
{ .arm = 0, .ahb = 0, .sel = 0},
};
-unsigned long imx_get_armclk(void)
+static unsigned long imx_get_armclk(void)
{
unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
struct arm_ahb_div *aad;
@@ -83,7 +84,7 @@
return fref / aad->ahb;
}
-unsigned long imx_get_ipgclk(void)
+static unsigned long imx_get_ipgclk(void)
{
ulong clk = imx_get_ahbclk();
@@ -95,7 +96,7 @@
return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
}
-unsigned long imx_get_ipg_perclk(void)
+static unsigned long imx_get_ipg_perclk(void)
{
ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0);
ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4);
@@ -163,6 +164,17 @@
return imx_get_ppllclk() / div;
}
+unsigned long imx_get_mmcclk(void)
+{
+ unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3);
+ unsigned long div = get_3_3_div(pdr3);
+
+ if (pdr3 & (1 << 6))
+ return imx_get_armclk() / div;
+ else
+ return imx_get_ppllclk() / div;
+}
+
ulong imx_get_fecclk(void)
{
return imx_get_ipgclk();
@@ -183,6 +195,7 @@
printf("ipg: %10d Hz\n", imx_get_ipgclk());
printf("ipg_per: %10d Hz\n", imx_get_ipg_perclk());
printf("uart: %10d Hz\n", imx_get_uartclk());
+ printf("sdhc1: %10d Hz\n", imx_get_mmcclk());
}
/*
diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c
new file mode 100644
index 0000000..9983297
--- /dev/null
+++ b/arch/arm/mach-imx/speed-imx51.c
@@ -0,0 +1,190 @@
+#include
+#include
+#include
+#include
+#include "mach/clock-imx51.h"
+
+static u32 ccm_readl(u32 ofs)
+{
+ return readl(MX51_CCM_BASE_ADDR + ofs);
+}
+
+static unsigned long ckil_get_rate(void)
+{
+ return 32768;
+}
+
+static unsigned long osc_get_rate(void)
+{
+ return 24000000;
+}
+
+static unsigned long fpm_get_rate(void)
+{
+ return ckil_get_rate() * 512;
+}
+
+static unsigned long pll_get_rate(void __iomem *pllbase)
+{
+ long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
+ unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
+ u64 temp;
+ unsigned long parent_rate;
+
+ dp_ctl = readl(pllbase + MX51_PLL_DP_CTL);
+
+ if ((dp_ctl & MX51_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0)
+ parent_rate = fpm_get_rate();
+ else
+ parent_rate = osc_get_rate();
+
+ pll_hfsm = dp_ctl & MX51_PLL_DP_CTL_HFSM;
+ dbl = dp_ctl & MX51_PLL_DP_CTL_DPDCK0_2_EN;
+
+ if (pll_hfsm == 0) {
+ dp_op = readl(pllbase + MX51_PLL_DP_OP);
+ dp_mfd = readl(pllbase + MX51_PLL_DP_MFD);
+ dp_mfn = readl(pllbase + MX51_PLL_DP_MFN);
+ } else {
+ dp_op = readl(pllbase + MX51_PLL_DP_HFS_OP);
+ dp_mfd = readl(pllbase + MX51_PLL_DP_HFS_MFD);
+ dp_mfn = readl(pllbase + MX51_PLL_DP_HFS_MFN);
+ }
+ pdf = dp_op & MX51_PLL_DP_OP_PDF_MASK;
+ mfi = (dp_op & MX51_PLL_DP_OP_MFI_MASK) >> MX51_PLL_DP_OP_MFI_OFFSET;
+ mfi = (mfi <= 5) ? 5 : mfi;
+ mfd = dp_mfd & MX51_PLL_DP_MFD_MASK;
+ mfn = mfn_abs = dp_mfn & MX51_PLL_DP_MFN_MASK;
+ /* Sign extend to 32-bits */
+ if (mfn >= 0x04000000) {
+ mfn |= 0xFC000000;
+ mfn_abs = -mfn;
+ }
+
+ ref_clk = 2 * parent_rate;
+ if (dbl != 0)
+ ref_clk *= 2;
+
+ ref_clk /= (pdf + 1);
+ temp = (u64)ref_clk * mfn_abs;
+ do_div(temp, mfd + 1);
+ if (mfn < 0)
+ temp = -temp;
+ temp = (ref_clk * mfi) + temp;
+
+ return temp;
+}
+
+static unsigned long pll1_main_get_rate(void)
+{
+ return pll_get_rate((void __iomem *)MX51_PLL1_BASE_ADDR);
+}
+
+static unsigned long pll2_sw_get_rate(void)
+{
+ return pll_get_rate((void __iomem *)MX51_PLL2_BASE_ADDR);
+}
+
+static unsigned long pll3_sw_get_rate(void)
+{
+ return pll_get_rate((void __iomem *)MX51_PLL3_BASE_ADDR);
+}
+
+static unsigned long get_rate_select(int select,
+ unsigned long (* get_rate1)(void),
+ unsigned long (* get_rate2)(void),
+ unsigned long (* get_rate3)(void),
+ unsigned long (* get_rate4)(void))
+{
+ switch (select) {
+ case 0:
+ return get_rate1() ? get_rate1() : 0;
+ case 1:
+ return get_rate2() ? get_rate2() : 0;
+ case 2:
+ return get_rate3 ? get_rate3() : 0;
+ case 3:
+ return get_rate4 ? get_rate4() : 0;
+ }
+
+ return 0;
+}
+
+unsigned long imx_get_uartclk(void)
+{
+ u32 reg, prediv, podf;
+ unsigned long parent_rate;
+
+ parent_rate = pll2_sw_get_rate();
+
+ reg = ccm_readl(MX51_CCM_CSCDR1);
+ prediv = ((reg & MX51_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+ MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MX51_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+ MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
+
+ return parent_rate / (prediv * podf);
+}
+
+static unsigned long imx_get_ahbclk(void)
+{
+ u32 reg, div;
+
+ reg = ccm_readl(MX51_CCM_CBCDR);
+ div = ((reg >> 10) & 0x7) + 1;
+
+ return pll2_sw_get_rate() / div;
+}
+
+unsigned long imx_get_ipgclk(void)
+{
+ u32 reg, div;
+
+ reg = ccm_readl(MX51_CCM_CBCDR);
+ div = ((reg >> 8) & 0x3) + 1;
+
+ return imx_get_ahbclk() / div;
+}
+
+unsigned long imx_get_gptclk(void)
+{
+ return imx_get_ipgclk();
+}
+
+unsigned long imx_get_fecclk(void)
+{
+ return imx_get_ipgclk();
+}
+
+unsigned long imx_get_mmcclk(void)
+{
+ u32 reg, prediv, podf, rate;
+
+ reg = ccm_readl(MX51_CCM_CSCMR1);
+ reg &= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK;
+ reg >>= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET;
+ rate = get_rate_select(reg,
+ pll1_main_get_rate,
+ pll2_sw_get_rate,
+ pll3_sw_get_rate,
+ NULL);
+
+ reg = ccm_readl(MX51_CCM_CSCDR1);
+ prediv = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >>
+ MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1;
+ podf = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >>
+ MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1;
+
+ return rate / (prediv * podf);
+}
+
+void imx_dump_clocks(void)
+{
+ printf("pll1: %ld\n", pll1_main_get_rate());
+ printf("pll2: %ld\n", pll2_sw_get_rate());
+ printf("pll3: %ld\n", pll3_sw_get_rate());
+ printf("uart: %ld\n", imx_get_uartclk());
+ printf("ipg: %ld\n", imx_get_ipgclk());
+ printf("fec: %ld\n", imx_get_fecclk());
+ printf("gpt: %ld\n", imx_get_gptclk());
+}
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index e024733..750ace0 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -24,6 +24,7 @@
#include
#include
#include
+#include
/*
* get the system pll clock in Hz
diff --git a/arch/arm/mach-omap/arch-omap.dox b/arch/arm/mach-omap/arch-omap.dox
index df16b7b..9c90b4f 100644
--- a/arch/arm/mach-omap/arch-omap.dox
+++ b/arch/arm/mach-omap/arch-omap.dox
@@ -50,7 +50,11 @@
All OMAP common headers are located here. Where we have to incorporate a OMAP variant specific header, add a omapX_function_name.h.
@warning Do not add board specific header files/information here. Put them in mach-omap.
-include/asm-arm/arch-omap/silicon.h contains includes for omapX-silicon.h which defines the base addresses for the peripherals on that platform. the usual convention is to use #define OMAP_SOMETHING_BASE to allow re-use.
+include/asm-arm/arch-omap/silicon.h contains includes for omapX-silicon.h which defines the base addresses for the peripherals on that platform. the usual convention is to use
+@code
+#define OMAP_SOMETHING_BASE
+@endcode
+to allow re-use.
@section board_omap arch/arm/boards/omap directory guidelines
All Board specific files go here. In u-boot, we always had to use common config file which is shared by other drivers to get serial, ethernet baseaddress etc.. we can easily use the device_d structure to handle it with @a barebox. This is more like programming for Linux kernel - it is pretty easy.
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 9893145..f780794 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -52,11 +52,11 @@
*
* In case of crashes, reset the CPU
*
- * @param[in] addr -Cause of crash
+ * @param addr Cause of crash
*
* @return void
*/
-void __noreturn reset_cpu(ulong addr)
+void __noreturn reset_cpu(unsigned long addr)
{
/* FIXME: Enable WDT and cause reset */
hang();
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 1cc8a23..88d45fe 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -1,2 +1,2 @@
-obj-y += generic.o
+obj-y += generic.o gpio-s3c24x0.o
obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o
diff --git a/arch/arm/mach-s3c24xx/gpio-s3c24x0.c b/arch/arm/mach-s3c24xx/gpio-s3c24x0.c
new file mode 100644
index 0000000..3d5e5e5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/gpio-s3c24x0.c
@@ -0,0 +1,169 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static const unsigned char group_offset[] =
+{
+ 0x00, /* GPA */
+ 0x10, /* GPB */
+ 0x20, /* GPC */
+ 0x30, /* GPD */
+ 0x40, /* GPE */
+ 0x50, /* GPF */
+ 0x60, /* GPG */
+ 0x70, /* GPH */
+#ifdef CONFIG_CPU_S3C2440
+ 0xd0, /* GPJ */
+#endif
+};
+
+void gpio_set_value(unsigned gpio, int value)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ offset = group_offset[group];
+
+ reg = readl(GPADAT + offset);
+ reg &= ~(1 << bit);
+ reg |= (!!value) << bit;
+ writel(reg, GPADAT + offset);
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ offset = group_offset[group];
+
+ reg = readl(GPACON + offset);
+ reg &= ~(0x3 << (bit << 1));
+ writel(reg, GPACON + offset);
+
+ return 0;
+}
+
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ offset = group_offset[group];
+
+ /* value */
+ gpio_set_value(gpio,value);
+ /* direction */
+ if (group == 0) { /* GPA is special */
+ reg = readl(GPACON);
+ reg &= ~(1 << bit);
+ writel(reg, GPACON);
+ } else {
+ reg = readl(GPACON + offset);
+ reg &= ~(0x3 << (bit << 1));
+ reg |= 0x1 << (bit << 1);
+ writel(reg, GPACON + offset);
+ }
+
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ unsigned group = gpio >> 5;
+ unsigned bit = gpio % 32;
+ unsigned offset;
+ uint32_t reg;
+
+ if (group == 0) /* GPA is special: no input mode available */
+ return -ENODEV;
+
+ offset = group_offset[group];
+
+ /* value */
+ reg = readl(GPADAT + offset);
+
+ return !!(reg & (1 << bit));
+}
+
+void s3c_gpio_mode(unsigned gpio_mode)
+{
+ unsigned group, func, bit, offset, gpio;
+ uint32_t reg;
+
+ group = GET_GROUP(gpio_mode);
+ func = GET_FUNC(gpio_mode);
+ bit = GET_BIT(gpio_mode);
+ gpio = GET_GPIO_NO(gpio_mode);
+
+ if (group == 0) {
+ /* GPA is special */
+ switch (func) {
+ case 0: /* GPIO input */
+ pr_debug("Cannot set GPA pin to GPIO input\n");
+ break;
+ case 1: /* GPIO output */
+ gpio_direction_output(bit, GET_GPIOVAL(gpio_mode));
+ break;
+ default:
+ reg = readl(GPACON);
+ reg |= 1 << bit;
+ writel(reg, GPACON);
+ break;
+ }
+ return;
+ }
+
+ offset = group_offset[group];
+
+ if (PU_PRESENT(gpio_mode)) {
+ reg = readl(GPACON + offset + 8);
+ if (GET_PU(gpio_mode))
+ reg |= (1 << bit); /* set means _disabled_ */
+ else
+ reg &= ~(1 << bit);
+ writel(reg, GPACON + offset + 8);
+ }
+
+ switch (func) {
+ case 0: /* input */
+ gpio_direction_input(gpio);
+ break;
+ case 1: /* output */
+ gpio_direction_output(gpio, GET_GPIOVAL(gpio_mode));
+ break;
+ case 2: /* function one */
+ case 3: /* function two */
+ reg = readl(GPACON + offset);
+ reg &= ~(0x3 << (bit << 1));
+ reg |= func << (bit << 1);
+ writel(reg, GPACON + offset);
+ break;
+ }
+}
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h
new file mode 100644
index 0000000..37db4f5
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h
@@ -0,0 +1,31 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_MACH_GPIO_H
+#define __ASM_MACH_GPIO_H
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2410)
+# include
+#endif
+
+void gpio_set_value(unsigned, int);
+int gpio_direction_input(unsigned);
+int gpio_direction_output(unsigned, int);
+int gpio_get_value(unsigned);
+void s3c_gpio_mode(unsigned);
+
+#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h b/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h
new file mode 100644
index 0000000..2c64a97
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2010 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_IOMUX_S3C24x0_H
+#define __MACH_IOMUX_S3C24x0_H
+
+/* 3322222222221111111111
+ * 10987654321098765432109876543210
+ * ^^^^^_ Bit offset
+ * ^^^^______ Group Number
+ * ^^____________ Function
+ * ^______________ initial GPIO out value
+ * ^_______________ Pull up feature present
+ * ^________________ initial pull up setting
+ */
+
+
+#define PIN(group,bit) (group * 32 + bit)
+#define FUNC(x) (((x) & 0x3) << 11)
+#define GET_FUNC(x) (((x) >> 11) & 0x3)
+#define GET_GROUP(x) (((x) >> 5) & 0xf)
+#define GET_BIT(x) (((x) & 0x1ff) % 32)
+#define GET_GPIOVAL(x) (((x) >> 13) & 0x1)
+#define GET_GPIO_NO(x) ((x & 0x1ff))
+#define GPIO_OUT FUNC(1)
+#define GPIO_IN FUNC(0)
+#define GPIO_VAL(x) ((!!(x)) << 13)
+#define PU (1 << 14)
+#define PU_PRESENT(x) (!!((x) & (1 << 14)))
+#define ENABLE_PU (0 << 15)
+#define DISABLE_PU (1 << 15)
+#define GET_PU(x) (!!((x) & DISABLE_PU))
+
+/*
+ * Group 0: GPIO 0...31
+ * Used GPIO: 0...22
+ * These pins can also act as GPIO outputs
+ */
+#define GPA0_ADDR0 (PIN(0,0) | FUNC(2))
+#define GPA0_ADDR0_GPIO (PIN(0,0) | FUNC(0))
+#define GPA1_ADDR16 (PIN(0,1) | FUNC(2))
+#define GPA1_ADDR16_GPIO (PIN(0,1) | FUNC(0))
+#define GPA2_ADDR17 (PIN(0,2) | FUNC(2))
+#define GPA2_ADDR17_GPIO (PIN(0,2) | FUNC(0))
+#define GPA3_ADDR18 (PIN(0,3) | FUNC(2))
+#define GPA3_ADDR18_GPIO (PIN(0,3) | FUNC(0))
+#define GPA4_ADDR19 (PIN(0,4) | FUNC(2))
+#define GPA4_ADDR19_GPIO (PIN(0,4) | FUNC(0))
+#define GPA5_ADDR20 (PIN(0,5) | FUNC(2))
+#define GPA5_ADDR20_GPIO (PIN(0,5) | FUNC(0))
+#define GPA6_ADDR21 (PIN(0,6) | FUNC(2))
+#define GPA6_ADDR21_GPIO (PIN(0,6) | FUNC(0))
+#define GPA7_ADDR22 (PIN(0,7) | FUNC(2))
+#define GPA7_ADDR22_GPIO (PIN(0,7) | FUNC(0))
+#define GPA8_ADDR23 (PIN(0,8) | FUNC(2))
+#define GPA8_ADDR23_GPIO (PIN(0,8) | FUNC(0))
+#define GPA9_ADDR24 (PIN(0,9) | FUNC(2))
+#define GPA9_ADDR24_GPIO (PIN(0,9) | FUNC(0))
+#define GPA10_ADDR25 (PIN(0,10) | FUNC(2))
+#define GPA10_ADDR25_GPIO (PIN(0,10) | FUNC(0))
+#define GPA11_ADDR26 (PIN(0,11) | FUNC(2))
+#define GPA11_ADDR26_GPIO (PIN(0,11) | FUNC(0))
+#define GPA12_NGCS1 (PIN(0,12) | FUNC(2))
+#define GPA12_NGCS1_GPIO (PIN(0,12) | FUNC(0))
+#define GPA13_NGCS2 (PIN(0,13) | FUNC(2))
+#define GPA13_NGCS2_GPIO (PIN(0,13) | FUNC(0))
+#define GPA14_NGCS3 (PIN(0,14) | FUNC(2))
+#define GPA14_NGCS3_GPIO (PIN(0,14) | FUNC(0))
+#define GPA15_NGCS4 (PIN(0,15) | FUNC(2))
+#define GPA15_NGCS4_GPIO (PIN(0,15) | FUNC(0))
+#define GPA16_NGCS5 (PIN(0,16) | FUNC(2))
+#define GPA16_NGCS5_GPIO (PIN(0,16) | FUNC(0))
+#define GPA17_CLE (PIN(0,17) | FUNC(2))
+#define GPA17_CLE_GPIO (PIN(0,17) | FUNC(0))
+#define GPA18_ALE (PIN(0,18) | FUNC(2))
+#define GPA18_ALE_GPIO (PIN(0,18) | FUNC(0))
+#define GPA19_NFWE (PIN(0,19) | FUNC(2))
+#define GPA19_NFWE_GPIO (PIN(0,19) | FUNC(0))
+#define GPA20_NFRE (PIN(0,20) | FUNC(2))
+#define GPA20_NFRE_GPIO (PIN(0,20) | FUNC(0))
+#define GPA21_NRSTOUT (PIN(0,21) | FUNC(2))
+#define GPA21_NRSTOUT_GPIO (PIN(0,21) | FUNC(0))
+#define GPA22_NFCE (PIN(0,22) | FUNC(2))
+#define GPA22_NFCE_GPIO (PIN(0,22) | FUNC(0))
+
+/*
+ * Group 1: GPIO 32...63
+ * Used GPIO: 0...10
+ * these pins can also act as GPIO inputs/outputs
+ */
+#define GPB0_TOUT0 (PIN(1,0) | FUNC(2) | PU)
+#define GPB0_GPIO (PIN(1,0) | FUNC(0) | PU)
+#define GPB1_TOUT1 (PIN(1,1) | FUNC(2) | PU)
+#define GPB1_GPIO (PIN(1,1) | FUNC(0) | PU)
+#define GPB2_TOUT2 (PIN(1,2) | FUNC(2) | PU)
+#define GPB2_GPIO (PIN(1,2) | FUNC(0) | PU)
+#define GPB3_TOUT3 (PIN(1,3) | FUNC(2) | PU)
+#define GPB3_GPIO (PIN(1,3) | FUNC(0) | PU)
+#define GPB4_TCLK0 (PIN(1,4) | FUNC(2) | PU)
+#define GPB4_GPIO (PIN(1,4) | FUNC(0) | PU)
+#define GPB5_NXBACK (PIN(1,5) | FUNC(2) | PU)
+#define GPB5_GPIO (PIN(1,5) | FUNC(0) | PU)
+#define GPB6_NXBREQ (PIN(1,6) | FUNC(2) | PU)
+#define GPB6_GPIO (PIN(1,6) | FUNC(0) | PU)
+#define GPB7_NXDACK1 (PIN(1,7) | FUNC(2) | PU)
+#define GPB7_GPIO (PIN(1,7) | FUNC(0) | PU)
+#define GPB8_NXDREQ1 (PIN(1,8) | FUNC(2) | PU)
+#define GPB8_GPIO (PIN(1,8) | FUNC(0) | PU)
+#define GPB9_NXDACK0 (PIN(1,9) | FUNC(2) | PU)
+#define GPB9_GPIO (PIN(1,9) | FUNC(0) | PU)
+#define GPB10_NXDREQ0 (PIN(1,10) | FUNC(2) | PU)
+#define GPB10_GPIO (PIN(1,10) | FUNC(0) | PU)
+
+/*
+ * Group 1: GPIO 64...95
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPC0_LEND (PIN(2,0) | FUNC(2) | PU)
+#define GPC0_GPIO (PIN(2,0) | FUNC(0) | PU)
+#define GPC1_VCLK (PIN(2,1) | FUNC(2) | PU)
+#define GPC1_GPIO (PIN(2,1) | FUNC(0) | PU)
+#define GPC2_VLINE (PIN(2,2) | FUNC(2) | PU)
+#define GPC2_GPIO (PIN(2,2) | FUNC(0) | PU)
+#define GPC3_VFRAME (PIN(2,3) | FUNC(2) | PU)
+#define GPC3_GPIO (PIN(2,3) | FUNC(0) | PU)
+#define GPC4_VM (PIN(2,4) | FUNC(2) | PU)
+#define GPC4_GPIO (PIN(2,4) | FUNC(0) | PU)
+#define GPC5_LPCOE (PIN(2,5) | FUNC(2) | PU)
+#define GPC5_GPIO (PIN(2,5) | FUNC(0) | PU)
+#define GPC6_LPCREV (PIN(2,6) | FUNC(2) | PU)
+#define GPC6_GPIO (PIN(2,6) | FUNC(0) | PU)
+#define GPC7_LPCREVB (PIN(2,7) | FUNC(2) | PU)
+#define GPC7_GPIO (PIN(2,7) | FUNC(0) | PU)
+#define GPC8_VD0 (PIN(2,8) | FUNC(2) | PU)
+#define GPC8_GPIO (PIN(2,8) | FUNC(0) | PU)
+#define GPC9_VD1 (PIN(2,9) | FUNC(2) | PU)
+#define GPC9_GPIO (PIN(2,9) | FUNC(0) | PU)
+#define GPC10_VD2 (PIN(2,10) | FUNC(2) | PU)
+#define GPC10_GPIO (PIN(2,10) | FUNC(0) | PU)
+#define GPC11_VD3 (PIN(2,11) | FUNC(2) | PU)
+#define GPC11_GPIO (PIN(2,11) | FUNC(0) | PU)
+#define GPC12_VD4 (PIN(2,12) | FUNC(2) | PU)
+#define GPC12_GPIO (PIN(2,12) | FUNC(0) | PU)
+#define GPC13_VD5 (PIN(2,13) | FUNC(2) | PU)
+#define GPC13_GPIO (PIN(2,13) | FUNC(0) | PU)
+#define GPC14_VD6 (PIN(2,14) | FUNC(2) | PU)
+#define GPC14_GPIO (PIN(2,14) | FUNC(0) | PU)
+#define GPC15_VD7 (PIN(2,15) | FUNC(2) | PU)
+#define GPC15_GPIO (PIN(2,15) | FUNC(0) | PU)
+
+/*
+ * Group 1: GPIO 96...127
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPD0_VD8 (PIN(3,0) | FUNC(2) | PU)
+#define GPD0_GPIO (PIN(3,0) | FUNC(0) | PU)
+#define GPD1_VD9 (PIN(3,1) | FUNC(2) | PU)
+#define GPD1_GPIO (PIN(3,1) | FUNC(0) | PU)
+#define GPD2_VD10 (PIN(3,2) | FUNC(2) | PU)
+#define GPD2_GPIO (PIN(3,2) | FUNC(0) | PU)
+#define GPD3_VD11 (PIN(3,3) | FUNC(2) | PU)
+#define GPD3_GPIO (PIN(3,3) | FUNC(0) | PU)
+#define GPD4_VD12 (PIN(3,4) | FUNC(2) | PU)
+#define GPD4_GPIO (PIN(3,4) | FUNC(0) | PU)
+#define GPD5_VD13 (PIN(3,5) | FUNC(2) | PU)
+#define GPD5_GPIO (PIN(3,5) | FUNC(0) | PU)
+#define GPD6_VD14 (PIN(3,6) | FUNC(2) | PU)
+#define GPD6_GPIO (PIN(3,6) | FUNC(0) | PU)
+#define GPD7_VD15 (PIN(3,7) | FUNC(2) | PU)
+#define GPD7_GPIO (PIN(3,7) | FUNC(0) | PU)
+#define GPD8_VD16 (PIN(3,8) | FUNC(2) | PU)
+#define GPD8_GPIO (PIN(3,8) | FUNC(0) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPD8_SPIMISO1 (PIN(3,8) | FUNC(3) | PU)
+#endif
+#define GPD9_VD17 (PIN(3,9) | FUNC(2) | PU)
+#define GPD9_GPIO (PIN(3,9) | FUNC(0) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPD9_SPIMOSI1 (PIN(3,9) | FUNC(3) | PU)
+#endif
+#define GPD10_VD18 (PIN(3,10) | FUNC(2) | PU)
+#define GPD10_GPIO (PIN(3,10) | FUNC(0) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPD10_SPICLK (PIN(3,10) | FUNC(3) | PU)
+#endif
+#define GPD11_VD19 (PIN(3,11) | FUNC(2) | PU)
+#define GPD11_GPIO (PIN(3,11) | FUNC(0) | PU)
+#define GPD12_VD20 (PIN(3,12) | FUNC(2) | PU)
+#define GPD12_GPIO (PIN(3,12) | FUNC(0) | PU)
+#define GPD13_VD21 (PIN(3,13) | FUNC(2) | PU)
+#define GPD13_GPIO (PIN(3,13) | FUNC(0) | PU)
+#define GPD14_VD22 (PIN(3,14) | FUNC(2) | PU)
+#define GPD14_GPIO (PIN(3,14) | FUNC(0) | PU)
+#define GPD14_NSS1 (PIN(3,14) | FUNC(3) | PU)
+#define GPD15_VD23 (PIN(3,15) | FUNC(2) | PU)
+#define GPD15_GPIO (PIN(3,15) | FUNC(0) | PU)
+#define GPD15_NSS0 (PIN(3,15) | FUNC(3) | PU)
+
+/*
+ * Group 1: GPIO 128...159
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPE0_I2SLRCK (PIN(4,0) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE0_AC_SYNC (PIN(4,0) | FUNC(3) | PU)
+#endif
+#define GPE0_GPIO (PIN(4,0) | FUNC(0) | PU)
+#define GPE1_I2SSCLK (PIN(4,1) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE1_AC_BIT_CLK (PIN(4,1) | FUNC(3) | PU)
+#endif
+#define GPE1_GPIO (PIN(4,1) | FUNC(0) | PU)
+#define GPE2_CDCLK (PIN(4,2) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE2_AC_NRESET (PIN(4,2) | FUNC(3) | PU)
+#endif
+#define GPE2_GPIO (PIN(4,2) | FUNC(0) | PU)
+#define GPE3_I2SDI (PIN(4,3) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE3_AC_SDATA_IN (PIN(4,3) | FUNC(3) | PU)
+#endif
+#ifdef CONFIG_CPU_S3C2410
+# define GPE_NSS0 (PIN(4,3) | FUNC(3) | PU)
+#endif
+#define GPE3_GPIO (PIN(4,3) | FUNC(0) | PU)
+#define GPE4_I2SDO (PIN(4,4) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPE4_AC_SDATA_OUT (PIN(4,4) | FUNC(3) | PU)
+#endif
+#ifdef CONFIG_CPU_S3C2440
+# define GPE4_I2SSDI (PIN(4,4) | FUNC(3) | PU)
+#endif
+#define GPE4_GPIO (PIN(4,4) | FUNC(0) | PU)
+#define GPE5_SDCLK (PIN(4,5) | FUNC(2) | PU)
+#define GPE5_GPIO (PIN(4,5) | FUNC(0) | PU)
+#define GPE6_SDCMD (PIN(4,6) | FUNC(2) | PU)
+#define GPE6_GPIO (PIN(4,6) | FUNC(0) | PU)
+#define GPE7_SDDAT0 (PIN(4,7) | FUNC(2) | PU)
+#define GPE7_GPIO (PIN(4,7) | FUNC(0) | PU)
+#define GPE8_SDDAT1 (PIN(4,8) | FUNC(2) | PU)
+#define GPE8_GPIO (PIN(4,8) | FUNC(0) | PU)
+#define GPE9_SDDAT2 (PIN(4,9) | FUNC(2) | PU)
+#define GPE9_GPIO (PIN(4,9) | FUNC(0) | PU)
+#define GPE10_SDDAT3 (PIN(4,10) | FUNC(2) | PU)
+#define GPE10_GPIO (PIN(4,10) | FUNC(0) | PU)
+#define GPE11_SPIMISO0 (PIN(4,11) | FUNC(2) | PU)
+#define GPE11_GPIO (PIN(4,11) | FUNC(0) | PU)
+#define GPE12_SPIMOSI0 (PIN(4,12) | FUNC(2) | PU)
+#define GPE12_GPIO (PIN(4,12) | FUNC(0) | PU)
+#define GPE13_SPICLK0 (PIN(4,13) | FUNC(2) | PU)
+#define GPE13_GPIO (PIN(4,13) | FUNC(0) | PU)
+#define GPE14_IICSCL (PIN(4,14) | FUNC(2)) /* no pullup option */
+#define GPE14_GPIO (PIN(4,14) | FUNC(0)) /* no pullup option */
+#define GPE15_IICSDA (PIN(4,15) | FUNC(2)) /* no pullup option */
+#define GPE15_GPIO (PIN(4,15) | FUNC(0)) /* no pullup option */
+
+/*
+ * Group 1: GPIO 160...191
+ * Used GPIO: 0...7
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPF0_EINT0 (PIN(5,0) | FUNC(2) | PU)
+#define GPF0_GPIO (PIN(5,0) | FUNC(0) | PU)
+#define GPF1_EINT1 (PIN(5,1) | FUNC(2) | PU)
+#define GPF1_GPIO (PIN(5,1) | FUNC(0) | PU)
+#define GPF2_EINT2 (PIN(5,2) | FUNC(2) | PU)
+#define GPF2_GPIO (PIN(5,2) | FUNC(0) | PU)
+#define GPF3_EINT3 (PIN(5,3) | FUNC(2) | PU)
+#define GPF3_GPIO (PIN(5,3) | FUNC(0) | PU)
+#define GPF4_EINT4 (PIN(5,4) | FUNC(2) | PU)
+#define GPF4_GPIO (PIN(5,4) | FUNC(0) | PU)
+#define GPF5_EINT5 (PIN(5,5) | FUNC(2) | PU)
+#define GPF5_GPIO (PIN(5,5) | FUNC(0) | PU)
+#define GPF6_EINT6 (PIN(5,6) | FUNC(2) | PU)
+#define GPF6_GPIO (PIN(5,6) | FUNC(0) | PU)
+#define GPF7_EINT7 (PIN(5,7) | FUNC(2) | PU)
+#define GPF7_GPIO (PIN(5,7) | FUNC(0) | PU)
+
+/*
+ * Group 1: GPIO 192..223
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPG0_EINT8 (PIN(6,0) | FUNC(2) | PU)
+#define GPG0_GPIO (PIN(6,0) | FUNC(0) | PU)
+#define GPG1_EINT9 (PIN(6,1) | FUNC(2) | PU)
+#define GPG1_GPIO (PIN(6,1) | FUNC(0) | PU)
+#define GPG2_EINT10 (PIN(6,2) | FUNC(2) | PU)
+#define GPG2_NSS0 (PIN(6,2) | FUNC(3) | PU)
+#define GPG2_GPIO (PIN(6,2) | FUNC(0) | PU)
+#define GPG3_EINT11 (PIN(6,3) | FUNC(2) | PU)
+#define GPG3_NSS1 (PIN(6,3) | FUNC(3) | PU)
+#define GPG3_GPIO (PIN(6,3) | FUNC(0) | PU)
+#define GPG4_EINT12 (PIN(6,4) | FUNC(2) | PU)
+#define GPG4_LCD_PWREN (PIN(6,4) | FUNC(3) | PU)
+#define GPG4_GPIO (PIN(6,4) | FUNC(0) | PU)
+#define GPG5_EINT13 (PIN(6,5) | FUNC(2) | PU)
+#define GPG5_SPIMISO1 (PIN(6,5) | FUNC(3) | PU)
+#define GPG5_GPIO (PIN(6,5) | FUNC(0) | PU)
+#define GPG6_EINT14 (PIN(6,6) | FUNC(2) | PU)
+#define GPG6_SPIMOSI1 (PIN(6,6) | FUNC(3) | PU)
+#define GPG6_GPIO (PIN(6,6) | FUNC(0) | PU)
+#define GPG7_EINT15 (PIN(6,7) | FUNC(2) | PU)
+#define GPG7_SPICLK1 (PIN(6,7) | FUNC(3) | PU)
+#define GPG7_GPIO (PIN(6,7) | FUNC(0) | PU)
+#define GPG8_EINT16 (PIN(6,8) | FUNC(2) | PU)
+#define GPG8_GPIO (PIN(6,8) | FUNC(0) | PU)
+#define GPG9_EINT17 (PIN(6,9) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPG9_NRTS1 (PIN(6,9) | FUNC(3) | PU)
+#endif
+#define GPG9_GPIO (PIN(6,9) | FUNC(0) | PU)
+#define GPG10_EINT18 (PIN(6,10) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2440
+# define GPG10_NCTS1 (PIN(6,10) | FUNC(3) | PU)
+#endif
+#define GPG10_GPIO (PIN(6,10) | FUNC(0) | PU)
+#define GPG11_EINT19 (PIN(6,11) | FUNC(2) | PU)
+#define GPG11_TCLK (PIN(6,11) | FUNC(3) | PU)
+#define GPG11_GPIO (PIN(6,11) | FUNC(0) | PU)
+#define GPG12_EINT20 (PIN(6,12) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG12_XMON (PIN(6,12) | FUNC(3) | PU)
+#endif
+#define GPG12_GPIO (PIN(6,12) | FUNC(0) | PU)
+#define GPG13_EINT21 (PIN(6,13) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG13_NXPON (PIN(6,13) | FUNC(3) | PU)
+#endif
+#define GPG13_GPIO (PIN(6,13) | FUNC(0) | PU) /* must be input in NAND boot mode */
+#define GPG14_EINT22 (PIN(6,14) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG14_YMON (PIN(6,14) | FUNC(3) | PU)
+#endif
+#define GPG14_GPIO (PIN(6,14) | FUNC(0) | PU) /* must be input in NAND boot mode */
+#define GPG15_EINT23 (PIN(6,15) | FUNC(2) | PU)
+#ifdef CONFIG_CPU_S3C2410
+# define GPG15_YPON (PIN(6,15) | FUNC(3) | PU)
+#endif
+#define GPG15_GPIO (PIN(6,15) | FUNC(0) | PU) /* must be input in NAND boot mode */
+
+/*
+ * Group 1: GPIO 224..255
+ * Used GPIO: 0...15
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPH0_NCTS0 (PIN(7,0) | FUNC(2) | PU)
+#define GPH0_GPIO (PIN(7,0) | FUNC(0) | PU)
+#define GPH1_NRTS0 (PIN(7,1) | FUNC(2) | PU)
+#define GPH1_GPIO (PIN(7,1) | FUNC(0) | PU)
+#define GPH2_TXD0 (PIN(7,2) | FUNC(2) | PU)
+#define GPH2_GPIO (PIN(7,2) | FUNC(0) | PU)
+#define GPH3_RXD0 (PIN(7,3) | FUNC(2) | PU)
+#define GPH3_GPIO (PIN(7,3) | FUNC(0) | PU)
+#define GPH4_TXD1 (PIN(7,4) | FUNC(2) | PU)
+#define GPH4_GPIO (PIN(7,4) | FUNC(0) | PU)
+#define GPH5_RXD1 (PIN(7,5) | FUNC(2) | PU)
+#define GPH5_GPIO (PIN(7,5) | FUNC(0) | PU)
+#define GPH6_TXD2 (PIN(7,6) | FUNC(2) | PU)
+#define GPH6_NRTS1 (PIN(7,6) | FUNC(3) | PU)
+#define GPH6_GPIO (PIN(7,6) | FUNC(0) | PU)
+#define GPH7_RXD2 (PIN(7,7) | FUNC(2) | PU)
+#define GPH7_NCTS1 (PIN(7,7) | FUNC(3) | PU)
+#define GPH7_GPIO (PIN(7,7) | FUNC(0) | PU)
+#define GPH8_UEXTCLK (PIN(7,8) | FUNC(2) | PU)
+#define GPH8_GPIO (PIN(7,8) | FUNC(0) | PU)
+#define GPH9_CLOCKOUT0 (PIN(7,9) | FUNC(2) | PU)
+#define GPH9_GPIO (PIN(7,9) | FUNC(0) | PU)
+#define GPH10_CLKOUT1 (PIN(7,10) | FUNC(2) | PU)
+#define GPH10_GPIO (PIN(7,10) | FUNC(0) | PU)
+
+#ifdef CONFIG_CPU_S3C2440
+/*
+ * Group 1: GPIO 256..287
+ * Used GPIO: 0...12
+ * These pins can also act as GPIO inputs/outputs
+ */
+#define GPJ0_CAMDATA0 (PIN(8,0) | FUNC(2) | PU)
+#define GPJ0_GPIO (PIN(8,0) | FUNC(0) | PU)
+#define GPJ1_CAMDATA1 (PIN(8,1) | FUNC(2) | PU)
+#define GPJ1_GPIO (PIN(8,1) | FUNC(0) | PU)
+#define GPJ2_CAMDATA2 (PIN(8,2) | FUNC(2) | PU)
+#define GPJ2_GPIO (PIN(8,2) | FUNC(0) | PU)
+#define GPJ3_CAMDATA3 (PIN(8,3) | FUNC(2) | PU)
+#define GPJ3_GPIO (PIN(8,3) | FUNC(0) | PU)
+#define GPJ4_CAMDATA4 (PIN(8,4) | FUNC(2) | PU)
+#define GPJ4_GPIO (PIN(8,4) | FUNC(0) | PU)
+#define GPJ5_CAMDATA5 (PIN(8,5) | FUNC(2) | PU)
+#define GPJ5_GPIO (PIN(8,5) | FUNC(0) | PU)
+#define GPJ6_CAMDATA6 (PIN(8,6) | FUNC(2) | PU)
+#define GPJ6_GPIO (PIN(8,6) | FUNC(0) | PU)
+#define GPJ7_CAMDATA7 (PIN(8,7) | FUNC(2) | PU)
+#define GPJ7_GPIO (PIN(8,7) | FUNC(0) | PU)
+#define GPJ8_CAMPCLK (PIN(8,8) | FUNC(2) | PU)
+#define GPJ8_GPIO (PIN(8,8) | FUNC(0) | PU)
+#define GPJ9_CAMVSYNC (PIN(8,9) | FUNC(2) | PU)
+#define GPJ9_GPIO (PIN(8,9) | FUNC(0) | PU)
+#define GPJ10_CAMHREF (PIN(8,10) | FUNC(2) | PU)
+#define GPJ10_GPIO (PIN(8,10) | FUNC(0) | PU)
+#define GPJ11_CAMCLKOUT (PIN(8,11) | FUNC(2) | PU)
+#define GPJ11_GPIO (PIN(8,11) | FUNC(0) | PU)
+#define GPJ12_CAMRESET (PIN(8,12) | FUNC(0) | PU)
+#define GPJ12_GPIO (PIN(8,12) | FUNC(0) | PU)
+
+#endif
+
+#endif /* __MACH_IOMUX_S3C24x0_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/mci.h b/arch/arm/mach-s3c24xx/include/mach/mci.h
new file mode 100644
index 0000000..6ba8961
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/include/mach/mci.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert, Pengutronix
+ *
+ * This code is partially based on u-boot code:
+ *
+ * Copyright 2008, Freescale Semiconductor, Inc
+ * Andy Fleming
+ *
+ * Based (loosely) on the Linux code
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MMC_H_
+#define __MACH_MMC_H_
+
+struct s3c_mci_platform_data {
+ unsigned caps; /**< supported operating modes (MMC_MODE_*) */
+ unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
+ unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */
+ unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */
+ /* TODO */
+ /* function to modify the voltage */
+ /* function to switch the voltage */
+ /* function to detect the presence of a SD card in the socket */
+ unsigned gpio_detect;
+ unsigned detect_invert;
+};
+
+#endif /* __MACH_MMC_H_ */
diff --git a/arch/arm/mach-stm/Kconfig b/arch/arm/mach-stm/Kconfig
new file mode 100644
index 0000000..021919a
--- /dev/null
+++ b/arch/arm/mach-stm/Kconfig
@@ -0,0 +1,48 @@
+if ARCH_STM
+
+config ARCH_TEXT_BASE
+ hex
+ default 0x41000000 if MACH_MX23EVK
+ default 0x42000000 if MACH_CHUMBY
+
+config BOARDINFO
+ default "Freescale i.MX23-EVK" if MACH_MX23EVK
+ default "Chumby Falconwing" if MACH_CHUMBY
+
+comment "SigmaTel/Freescale i.MX System-on-Chip"
+
+choice
+ prompt "Freescale i.MX Processor"
+
+config ARCH_IMX23
+ bool "i.MX23"
+ select CPU_ARM926T
+
+endchoice
+
+if ARCH_IMX23
+
+choice
+ prompt "i.MX23 Board Type"
+
+config MACH_MX23EVK
+ bool "mx23-evk"
+ help
+ Say Y here if you are using the Freescale i.MX23-EVK board
+
+config MACH_CHUMBY
+ bool "Chumby Falconwing"
+ select HAVE_MMU
+ help
+ Say Y here if you are using the "chumby one" aka falconwing from
+ Chumby Industries
+
+endchoice
+
+endif
+
+menu "Board specific settings "
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-stm/Makefile b/arch/arm/mach-stm/Makefile
new file mode 100644
index 0000000..59d70b6
--- /dev/null
+++ b/arch/arm/mach-stm/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o imx23.o iomux-imx23.o clocksource-imx23.o reset-imx23.o
+
diff --git a/arch/arm/mach-stm/clocksource-imx23.c b/arch/arm/mach-stm/clocksource-imx23.c
new file mode 100644
index 0000000..7c0268c
--- /dev/null
+++ b/arch/arm/mach-stm/clocksource-imx23.c
@@ -0,0 +1,82 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define TIMROTCTRL 0x00
+#define TIMCTRL1 0x40
+#define TIMCTRL1_SET 0x44
+#define TIMCTRL1_CLR 0x48
+#define TIMCTRL1_TOG 0x4c
+# define TIMCTRL_RELOAD (1 << 6)
+# define TIMCTRL_UPDATE (1 << 7)
+# define TIMCTRL_PRESCALE(x) ((x & 0x3) << 4)
+# define TIMCTRL_SELECT(x) (x & 0xf)
+#define TIMCOUNT1 0x50
+
+static const unsigned long timer_base = IMX_TIM1_BASE;
+
+#define CLOCK_TICK_RATE (32000)
+
+static uint64_t imx23_clocksource_read(void)
+{
+ /* only the upper bits are the valid */
+ return ~(readl(timer_base + TIMCOUNT1) >> 16);
+}
+
+static struct clocksource cs = {
+ .read = imx23_clocksource_read,
+ .mask = 0x0000ffff,
+ .shift = 10,
+};
+
+static int imx23_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data)
+{
+ cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE/*imx_get_xclk()*/, cs.shift);
+ return 0;
+}
+
+static struct notifier_block imx23_clock_notifier = {
+ .notifier_call = imx23_clocksource_clock_change,
+};
+
+static int clocksource_init(void)
+{
+ /* enable the whole timer block */
+ writel(0x3e000000, timer_base + TIMROTCTRL);
+ /* setup general purpose timer 1 */
+ writel(0x00000000, timer_base + TIMCTRL1);
+ writel(TIMCTRL_UPDATE, timer_base + TIMCTRL1);
+ writel(0x0000ffff, timer_base + TIMCOUNT1);
+
+ writel(TIMCTRL_UPDATE | TIMCTRL_RELOAD | TIMCTRL_PRESCALE(0) | TIMCTRL_SELECT(8), timer_base + TIMCTRL1);
+ cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE/*imx_get_xclk()*/, cs.shift);
+ init_clock(&cs);
+
+ clock_register_client(&imx23_clock_notifier);
+ return 0;
+}
+
+core_initcall(clocksource_init);
diff --git a/arch/arm/mach-stm/imx23.c b/arch/arm/mach-stm/imx23.c
new file mode 100644
index 0000000..14a4249
--- /dev/null
+++ b/arch/arm/mach-stm/imx23.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+
+extern void imx_dump_clocks(void);
+
+static int do_clocks(struct command *cmdtp, int argc, char *argv[])
+{
+ imx_dump_clocks();
+
+ return 0;
+}
+
+BAREBOX_CMD_START(dump_clocks)
+ .cmd = do_clocks,
+ .usage = "show clock frequencies",
+BAREBOX_CMD_END
diff --git a/arch/arm/mach-stm/include/mach/clock.h b/arch/arm/mach-stm/include/mach/clock.h
new file mode 100644
index 0000000..0e1a6d6
--- /dev/null
+++ b/arch/arm/mach-stm/include/mach/clock.h
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef ASM_ARCH_CLOCK_IMX23_H
+#define ASM_ARCH_CLOCK_IMX23_H
+
+unsigned imx_get_mpllclk(void);
+unsigned imx_get_emiclk(void);
+unsigned imx_get_ioclk(void);
+unsigned imx_get_armclk(void);
+unsigned imx_get_hclk(void);
+unsigned imx_get_xclk(void);
+unsigned imx_get_sspclk(unsigned);
+unsigned imx_set_sspclk(unsigned, unsigned, int);
+unsigned imx_set_ioclk(unsigned);
+
+#endif /* ASM_ARCH_CLOCK_IMX23_H */
+
diff --git a/arch/arm/mach-stm/include/mach/generic.h b/arch/arm/mach-stm/include/mach/generic.h
new file mode 100644
index 0000000..3a552a8
--- /dev/null
+++ b/arch/arm/mach-stm/include/mach/generic.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef CONFIG_ARCH_IMX23
+# define cpu_is_mx23() (1)
+#else
+# define cpu_is_mx23() (0)
+#endif
diff --git a/arch/arm/mach-stm/include/mach/gpio.h b/arch/arm/mach-stm/include/mach/gpio.h
new file mode 100644
index 0000000..fa8263c
--- /dev/null
+++ b/arch/arm/mach-stm/include/mach/gpio.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_MACH_GPIO_H
+#define __ASM_MACH_GPIO_H
+
+#if defined CONFIG_ARCH_IMX23
+# include
+#endif
+
+void imx_gpio_mode(unsigned);
+
+#endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-stm/include/mach/imx-regs.h b/arch/arm/mach-stm/include/mach/imx-regs.h
new file mode 100644
index 0000000..40dc742
--- /dev/null
+++ b/arch/arm/mach-stm/include/mach/imx-regs.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _IMX_REGS_H
+# define _IMX_REGS_H
+
+#if defined CONFIG_ARCH_IMX23
+# include
+#endif
+
+#endif /* _IMX_REGS_H */
diff --git a/arch/arm/mach-stm/include/mach/imx23-regs.h b/arch/arm/mach-stm/include/mach/imx23-regs.h
new file mode 100644
index 0000000..89ca453
--- /dev/null
+++ b/arch/arm/mach-stm/include/mach/imx23-regs.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MX23_REGS_H
+#define __ASM_ARCH_MX23_REGS_H
+
+/*
+ * sanity check
+ */
+#ifndef _IMX_REGS_H
+# error "Please do not include directly. Use imx-regs.h instead."
+#endif
+
+#define IMX_MEMORY_BASE 0x40000000
+#define IMX_UART1_BASE 0x8006c000
+#define IMX_UART2_BASE 0x8006e000
+#define IMX_DBGUART_BASE 0x80070000
+#define IMX_TIM1_BASE 0x80068000
+#define IMX_IOMUXC_BASE 0x80018000
+#define IMX_WDT_BASE 0x8005c000
+#define IMX_CCM_BASE 0x80040000
+#define IMX_I2C1_BASE 0x80058000
+#define IMX_SSP1_BASE 0x80010000
+#define IMX_SSP2_BASE 0x80034000
+
+#endif /* __ASM_ARCH_MX23_REGS_H */
diff --git a/arch/arm/mach-stm/include/mach/iomux-imx23.h b/arch/arm/mach-stm/include/mach/iomux-imx23.h
new file mode 100644
index 0000000..bebaf56
--- /dev/null
+++ b/arch/arm/mach-stm/include/mach/iomux-imx23.h
@@ -0,0 +1,424 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+/* 3322222222221111111111
+ * 10987654321098765432109876543210
+ * ^^^_ Register Number
+ * ^^^^____ Bit offset
+ * ^^________ Function
+ * ^__________ Drive strength feature present
+ * ^___________ Pull up / bit keeper present
+ * ^^____________ Drive strength setting
+ * ^______________ Pull up / bit keeper setting
+ * ^_______________ Voltage select present
+ * ^________________ Voltage selection
+ * ^____________________ direction if enabled as GPIO (1 = output)
+ * ^_____________________ initial output value if enabled as GPIO and configured as output
+ */
+#ifndef __ASM_MACH_IOMUX_H
+#define __ASM_MACH_IOMUX_H
+
+/* control pad's function */
+#define FBIT_SHIFT (3)
+#define PORTF(bank,bit) (((bit) << FBIT_SHIFT) | (bank))
+#define GET_PORTF(x) ((x) & 0x7)
+#define GET_FBITPOS(x) (((x) >> FBIT_SHIFT) & 0xf)
+#define GET_GPIO_NO(x) ((GET_PORTF(x) << 4) + GET_FBITPOS(m))
+#define FUNC_SHIFT 7
+#define FUNC(x) ((x) << FUNC_SHIFT)
+#define GET_FUNC(x) (((x) >> FUNC_SHIFT) & 3)
+#define IS_GPIO (3)
+
+/* control pad's GPIO feature if enabled */
+#define GPIO_OUT (1 << 19)
+#define GPIO_VALUE(x) ((x) << 20)
+#define GPIO_IN (0 << 19)
+#define GET_GPIODIR(x) (!!((x) & (1 << 19)))
+#define GET_GPIOVAL(x) (!!((x) & (1 << 20)))
+
+/* control pad's drive strength */
+#define SE (1 << 9)
+#define SE_PRESENT(x) (!!((x) & SE))
+#define STRENGTH(x) ((x) << 11)
+#define S4MA 0 /* used to define a 4 mA drive strength */
+#define S8MA 1 /* used to define a 8 mA drive strength */
+#define S12MA 2 /* used to define a 12 mA drive strength */
+#define S16MA 3 /* used to define a 16 mA drive strength, not all pads can drive this current! */
+#define GET_STRENGTH(x) (((x) >> 11) & 0x3)
+
+/* control pad's pull up / bit keeper feature */
+#define PE (1 << 10)
+#define PE_PRESENT(x) (!!((x) & PE))
+#define PULLUP(x) ((x) << 13)
+#define GET_PULLUP(x) (!!((x) & (1 << 13)))
+
+/* control pad's voltage feature */
+#define VE (1 << 14)
+#define VE_PRESENT(x) (!!((x) & VE))
+#define VE_1_8V (0 << 15)
+#define VE_2_5V (0 << 15) /* don't ask my why, RTFM */
+#define GET_VOLTAGE(x) (!!((x) & (1 << 15)))
+
+/* Bank 0, pins 0 ... 15, GPIO pins 0 ... 15 */
+#define GPMI_D15 (FUNC(0) | PORTF(0, 15) | SE | PE)
+#define GPMI_D15_AUART2_TX (FUNC(1) | PORTF(0, 15) | SE | PE)
+#define GPMI_D15_GPMI_CE3N (FUNC(2) | PORTF(0, 15) | SE | PE)
+#define GPMI_D15_GPIO (FUNC(3) | PORTF(0, 15) | SE | PE)
+#define GPMI_D14 (FUNC(0) | PORTF(0, 14) | SE)
+#define GPMI_D14_AUART2_RX (FUNC(1) | PORTF(0, 14) | SE)
+#define GPMI_D14_GPIO (FUNC(3) | PORTF(0, 14) | SE)
+#define GPMI_D13 (FUNC(0) | PORTF(0, 13) | SE)
+#define GPMI_D13_LCD_D23 (FUNC(1) | PORTF(0, 13) | SE)
+#define GPMI_D13_GPIO (FUNC(3) | PORTF(0, 13) | SE)
+#define GPMI_D12 (FUNC(0) | PORTF(0, 12) | SE)
+#define GPMI_D12_LCD_D22 (FUNC(1) | PORTF(0, 12) | SE)
+#define GPMI_D12_GPIO (FUNC(3) | PORTF(0, 12) | SE)
+#define GPMI_D11 (FUNC(0) | PORTF(0, 11) | SE | PE)
+#define GPMI_D11_LCD_D21 (FUNC(1) | PORTF(0, 11) | SE | PE)
+#define GPMI_D11_SSP1_D7 (FUNC(2) | PORTF(0, 11) | SE | PE)
+#define GPMI_D11_GPIO (FUNC(3) | PORTF(0, 11) | SE | PE)
+#define GPMI_D10 (FUNC(0) | PORTF(0, 10) | SE | PE)
+#define GPMI_D10_LCD_D20 (FUNC(1) | PORTF(0, 10) | SE | PE)
+#define GPMI_D10_SSP1_D6 (FUNC(2) | PORTF(0, 10) | SE | PE)
+#define GPMI_D10_GPIO (FUNC(3) | PORTF(0, 10) | SE | PE)
+#define GPMI_D09 (FUNC(0) | PORTF(0, 9) | SE | PE)
+#define GPMI_D09_LCD_D19 (FUNC(1) | PORTF(0, 9) | SE | PE)
+#define GPMI_D09_SSP1_D5 (FUNC(2) | PORTF(0, 9) | SE | PE)
+#define GPMI_D09_GPIO (FUNC(3) | PORTF(0, 9) | SE | PE)
+#define GPMI_D08 (FUNC(0) | PORTF(0, 8) | SE | PE)
+#define GPMI_D08_LCD_D18 (FUNC(1) | PORTF(0, 8) | SE | PE)
+#define GPMI_D08_SSP1_D4 (FUNC(2) | PORTF(0, 8) | SE | PE)
+#define GPMI_D08_GPIO (FUNC(3) | PORTF(0, 8) | SE | PE)
+#define GPMI_D07 (FUNC(0) | PORTF(0, 7) | SE | PE)
+#define GPMI_D07_LCD_D15 (FUNC(1) | PORTF(0, 7) | SE | PE)
+#define GPMI_D07_SSP2_D7 (FUNC(2) | PORTF(0, 7) | SE | PE)
+#define GPMI_D07_GPIO (FUNC(3) | PORTF(0, 7) | SE | PE)
+#define GPMI_D06 (FUNC(0) | PORTF(0, 6) | SE | PE)
+#define GPMI_D06_LCD_D14 (FUNC(1) | PORTF(0, 6) | SE | PE)
+#define GPMI_D06_SSP2_D6 (FUNC(2) | PORTF(0, 6) | SE | PE)
+#define GPMI_D06_GPIO (FUNC(3) | PORTF(0, 6) | SE | PE)
+#define GPMI_D05 (FUNC(0) | PORTF(0, 5) | SE | PE)
+#define GPMI_D05_LCD_D13 (FUNC(1) | PORTF(0, 5) | SE | PE)
+#define GPMI_D05_SSP2_D5 (FUNC(2) | PORTF(0, 5) | SE | PE)
+#define GPMI_D05_GPIO (FUNC(3) | PORTF(0, 5) | SE | PE)
+#define GPMI_D04 (FUNC(0) | PORTF(0, 4) | SE | PE)
+#define GPMI_D04_LCD_D12 (FUNC(1) | PORTF(0, 4) | SE | PE)
+#define GPMI_D04_SSP2_D4 (FUNC(2) | PORTF(0, 4) | SE | PE)
+#define GPMI_D04_GPIO (FUNC(3) | PORTF(0, 4) | SE | PE)
+#define GPMI_D03 (FUNC(0) | PORTF(0, 3) | SE | PE)
+#define GPMI_D03_LCD_D11 (FUNC(1) | PORTF(0, 3) | SE | PE)
+#define GPMI_D03_SSP2_D3 (FUNC(2) | PORTF(0, 3) | SE | PE)
+#define GPMI_D03_GPIO (FUNC(3) | PORTF(0, 3) | SE | PE)
+#define GPMI_D02 (FUNC(0) | PORTF(0, 2) | SE | PE)
+#define GPMI_D02_LCD_D10 (FUNC(1) | PORTF(0, 2) | SE | PE)
+#define GPMI_D02_SSP2_D2 (FUNC(2) | PORTF(0, 2) | SE | PE)
+#define GPMI_D02_GPIO (FUNC(3) | PORTF(0, 2) | SE | PE)
+#define GPMI_D01 (FUNC(0) | PORTF(0, 1) | SE | PE)
+#define GPMI_D01_LCD_D9 (FUNC(1) | PORTF(0, 1) | SE | PE)
+#define GPMI_D01_SSP2_D1 (FUNC(2) | PORTF(0, 1) | SE | PE)
+#define GPMI_D01_GPIO (FUNC(3) | PORTF(0, 1) | SE | PE)
+#define GPMI_D00 (FUNC(0) | PORTF(0, 0) | SE | PE)
+#define GPMI_D00_LCD_D8 (FUNC(1) | PORTF(0, 0) | SE | PE)
+#define GPMI_D00_SSP2_D0 (FUNC(2) | PORTF(0, 0) | SE | PE)
+#define GPMI_D00_GPIO (FUNC(3) | PORTF(0, 0) | SE | PE)
+
+/* Bank 0, pins 16 ... 31 GPIO pins 16 ... 31 */
+#define I2C_SDA (FUNC(0) | PORTF(1, 15) | SE)
+#define I2C_SDA_GPMI_CE2N (FUNC(1) | PORTF(1, 15) | SE)
+#define I2C_SDA_AUART1_RX (FUNC(2) | PORTF(1, 15) | SE)
+#define I2C_SDA_GPIO (FUNC(3) | PORTF(1, 15) | SE)
+#define I2C_CLK (FUNC(0) | PORTF(1, 14) | SE | PE)
+#define I2C_CLK_GPMI_RDY2 (FUNC(1) | PORTF(1, 14) | SE | PE)
+#define I2C_CLK_AUART1_TX (FUNC(2) | PORTF(1, 14) | SE | PE)
+#define I2C_CLK_GPIO (FUNC(3) | PORTF(1, 14) | SE | PE)
+#define AUART1_TX (FUNC(0) | PORTF(1, 13) | SE | PE)
+#define AUART1_TX_SSP1_D7 (FUNC(2) | PORTF(1, 13) | SE | PE)
+#define AUART1_TX_GPIO (FUNC(3) | PORTF(1, 13) | SE | PE)
+#define AUART1_RX (FUNC(0) | PORTF(1, 12) | SE | PE)
+#define AUART1_RX_SSP1_D6 (FUNC(2) | PORTF(1, 12) | SE | PE)
+#define AUART1_RX_GPIO (FUNC(3) | PORTF(1, 12) | SE | PE)
+#define AUART1_RTS (FUNC(0) | PORTF(1, 11) | SE | PE)
+#define AUART1_RTS_SSP1_D5 (FUNC(2) | PORTF(1, 11) | SE | PE)
+#define AUART1_RTS_GPIO (FUNC(3) | PORTF(1, 11) | SE | PE)
+#define AUART1_CTS (FUNC(0) | PORTF(1, 10) | SE | PE)
+#define AUART1_CTS_SSP1_D4 (FUNC(2) | PORTF(1, 10) | SE | PE)
+#define AUART1_CTS_GPIO (FUNC(3) | PORTF(1, 10) | SE | PE)
+#define GPMI_RDN (FUNC(0) | PORTF(1, 9) | SE)
+#define GPMI_RDN_GPIO (FUNC(3) | PORTF(1, 9) | SE)
+#define GPMI_WRN (FUNC(0) | PORTF(1, 8) | SE)
+#define GPMI_WRN_SSP2_SCK (FUNC(2) | PORTF(1, 8) | SE)
+#define GPMI_WRN_GPIO (FUNC(3) | PORTF(1, 8) | SE)
+#define GPMI_WPM (FUNC(0) | PORTF(1, 7) | SE)
+#define GPMI_WPM_GPIO (FUNC(3) | PORTF(1, 7) | SE)
+#define GPMI_RDY3 (FUNC(0) | PORTF(1, 6) | SE | PE)
+#define GPMI_RDY3_GPIO (FUNC(3) | PORTF(1, 6) | SE | PE)
+#define GPMI_RDY2 (FUNC(0) | PORTF(1, 5) | SE | PE)
+#define GPMI_RDY2_GPIO (FUNC(3) | PORTF(1, 5) | SE | PE)
+#define GPMI_RDY1 (FUNC(0) | PORTF(1, 4) | SE | PE)
+#define GPMI_RDY1_SSP2_CMD (FUNC(2) | PORTF(1, 4) | SE | PE)
+#define GPMI_RDY1_GPIO (FUNC(3) | PORTF(1, 4) | SE | PE)
+#define GPMI_RDY0 (FUNC(0) | PORTF(1, 3) | SE | PE)
+#define GPMI_RDY0_SSP2_DETECT (FUNC(2) | PORTF(1, 3) | SE | PE)
+#define GPMI_RDY0_GPIO (FUNC(3) | PORTF(1, 3) | SE | PE)
+#define GPMI_CE2N (FUNC(0) | PORTF(1, 2) | SE | PE)
+#define GPMI_CE2N_GPIO (FUNC(3) | PORTF(1, 2) | SE | PE)
+#define GPMI_ALE (FUNC(0) | PORTF(1, 1) | SE)
+#define GPMI_ALE_LCD_D17 (FUNC(1) | PORTF(1, 1) | SE)
+#define GPMI_ALE_GPIO (FUNC(3) | PORTF(1, 1) | SE)
+#define GPMI_CLE (FUNC(0) | PORTF(1, 0) | SE)
+#define GPMI_CLE_LCD_D16 (FUNC(1) | PORTF(1, 1) | SE)
+#define GPMI_CLE_GPIO (FUNC(3) | PORTF(1, 0) | SE)
+
+/* Bank 1, pins 0 ... 15 GPIO pins 32 ... 47 */
+#define LCD_D15 (FUNC(0) | PORTF(2, 15) | SE)
+#define LCD_D15_ETM_DA7 (FUNC(1) | PORTF(2, 15) | SE)
+#define LCD_D15_SAIF1_SDATA1 (FUNC(2) | PORTF(2, 15) | SE)
+#define LCD_D15_GPIO (FUNC(3) | PORTF(2, 15) | SE)
+#define LCD_D14 (FUNC(0) | PORTF(2, 14) | SE)
+#define LCD_D14_ETM_DA6 (FUNC(1) | PORTF(2, 14) | SE)
+#define LCD_D14_SAIF1_SDATA2 (FUNC(2) | PORTF(2, 14) | SE)
+#define LCD_D14_GPIO (FUNC(3) | PORTF(2, 14) | SE)
+#define LCD_D13 (FUNC(0) | PORTF(2, 13) | SE)
+#define LCD_D13_ETM_DA5 (FUNC(1) | PORTF(2, 13) | SE)
+#define LCD_D13_SAIF2_SDATA2 (FUNC(2) | PORTF(2, 13) | SE)
+#define LCD_D13_GPIO (FUNC(3) | PORTF(2, 13) | SE)
+#define LCD_D12 (FUNC(0) | PORTF(2, 12) | SE)
+#define LCD_D12_ETM_DA4 (FUNC(1) | PORTF(2, 12) | SE)
+#define LCD_D12_SAIF2_SDATA1 (FUNC(2) | PORTF(2, 12) | SE)
+#define LCD_D12_GPIO (FUNC(3) | PORTF(2, 12) | SE)
+#define LCD_D11 (FUNC(0) | PORTF(2, 11) | SE)
+#define LCD_D11_ETM_DA3 (FUNC(1) | PORTF(2, 11) | SE)
+#define LCD_D11_SAIF_LRCLK (FUNC(2) | PORTF(2, 11) | SE)
+#define LCD_D11_GPIO (FUNC(3) | PORTF(2, 11) | SE)
+#define LCD_D10 (FUNC(0) | PORTF(2, 10) | SE)
+#define LCD_D10_ETM_DA2 (FUNC(1) | PORTF(2, 10) | SE)
+#define LCD_D10_SAIF_BITCLK (FUNC(2) | PORTF(2, 10) | SE)
+#define LCD_D10_GPIO (FUNC(3) | PORTF(2, 10) | SE)
+#define LCD_D9 (FUNC(0) | PORTF(2, 9) | SE)
+#define LCD_D9_ETM_DA1 (FUNC(1) | PORTF(2, 9) | SE)
+#define LCD_D9_SAIF1_SDATA0 (FUNC(2) | PORTF(2, 9) | SE)
+#define LCD_D9_GPIO (FUNC(3) | PORTF(2, 9) | SE)
+#define LCD_D8 (FUNC(0) | PORTF(2, 8) | SE)
+#define LCD_D8_ETM_DA0 (FUNC(1) | PORTF(2, 8) | SE)
+#define LCD_D8_SAIF2_SDATA0 (FUNC(2) | PORTF(2, 8) | SE)
+#define LCD_D8_GPIO (FUNC(3) | PORTF(2, 8) | SE)
+#define LCD_D7 (FUNC(0) | PORTF(2, 7) | SE)
+#define LCD_D7_ETM_DA15 (FUNC(1) | PORTF(2, 7) | SE)
+#define LCD_D7_GPIO (FUNC(3) | PORTF(2, 7) | SE)
+#define LCD_D6 (FUNC(0) | PORTF(2, 6) | SE)
+#define LCD_D6_ETM_DA14 (FUNC(1) | PORTF(2, 6) | SE)
+#define LCD_D6_GPIO (FUNC(3) | PORTF(2, 6) | SE)
+#define LCD_D5 (FUNC(0) | PORTF(2, 5) | SE)
+#define LCD_D5_ETM_DA13 (FUNC(1) | PORTF(2, 5) | SE)
+#define LCD_D5_GPIO (FUNC(3) | PORTF(2, 5) | SE)
+#define LCD_D4 (FUNC(0) | PORTF(2, 4) | SE)
+#define LCD_D4_ETM_DA12 (FUNC(1) | PORTF(2, 4) | SE)
+#define LCD_D4_GPIO (FUNC(3) | PORTF(2, 4) | SE)
+#define LCD_D3 (FUNC(0) | PORTF(2, 3) | SE)
+#define LCD_D3_ETM_DA11 (FUNC(1) | PORTF(2, 3) | SE)
+#define LCD_D3_GPIO (FUNC(3) | PORTF(2, 3) | SE)
+#define LCD_D2 (FUNC(0) | PORTF(2, 2) | SE)
+#define LCD_D2_ETM_DA10 (FUNC(1) | PORTF(2, 2) | SE)
+#define LCD_D2_GPIO (FUNC(3) | PORTF(2, 2) | SE)
+#define LCD_D1 (FUNC(0) | PORTF(2, 1) | SE)
+#define LCD_D1_ETM_DA9 (FUNC(1) | PORTF(2, 1) | SE)
+#define LCD_D1_GPIO (FUNC(3) | PORTF(2, 1) | SE)
+#define LCD_D0 (FUNC(0) | PORTF(2, 0) | SE)
+#define LCD_D0_ETM_DA8 (FUNC(1) | PORTF(2, 0) | SE)
+#define LCD_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE)
+
+/* Bank 1, pins 16 ... 30 GPIO pins 48 ... 63 */
+#define PWM4 (FUNC(0) | PORTF(3, 14) | SE)
+#define PWM4_ETM_CLK (FUNC(1) | PORTF(3, 14) | SE)
+#define PWM4_AUART1_RTS (FUNC(2) | PORTF(3, 14) | SE)
+#define PWM4_GPIO (FUNC(3) | PORTF(3, 14) | SE)
+#define PWM3 (FUNC(0) | PORTF(3, 13) | SE)
+#define PWM3_ETM_TCTL (FUNC(1) | PORTF(3, 13) | SE)
+#define PWM3_AUART1_CTS (FUNC(2) | PORTF(3, 13) | SE)
+#define PWM3_GPIO (FUNC(3) | PORTF(3, 13) | SE)
+#define PWM2 (FUNC(0) | PORTF(3, 12) | SE | PE)
+#define PWM2_GPMI_READY3 (FUNC(1) | PORTF(3, 12) | SE | PE)
+#define PWM2_GPIO (FUNC(3) | PORTF(3, 12) | SE | PE)
+#define PWM1 (FUNC(0) | PORTF(3, 11) | SE)
+#define PWM1_TIMROT2 (FUNC(1) | PORTF(3, 11) | SE)
+#define PWM1_DUART_TX (FUNC(2) | PORTF(3, 11) | SE)
+#define PWM1_GPIO (FUNC(3) | PORTF(3, 11) | SE)
+#define PWM0 (FUNC(0) | PORTF(3, 10) | SE)
+#define PWM0_TIMROT1 (FUNC(1) | PORTF(3, 10) | SE)
+#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 10) | SE)
+#define PWM0_GPIO (FUNC(3) | PORTF(3, 10) | SE)
+#define LCD_VSYNC (FUNC(0) | PORTF(3, 9) | SE)
+#define LCD_VSYNC_LCD_BUSY (FUNC(1) | PORTF(3, 9) | SE)
+#define LCD_VSYNC_GPIO (FUNC(3) | PORTF(3, 9) | SE)
+#define LCD_HSYNC (FUNC(0) | PORTF(3, 8) | SE)
+#define LCD_HSYNC_I2C_SD (FUNC(1) | PORTF(3, 8) | SE)
+#define LCD_HSYNC_GPIO (FUNC(3) | PORTF(3, 8) | SE)
+#define LCD_ENABE (FUNC(0) | PORTF(3, 7) | SE)
+#define LCD_ENABE_I2C_CLK (FUNC(1) | PORTF(3, 7) | SE)
+#define LCD_ENABE_GPIO (FUNC(3) | PORTF(3, 7) | SE)
+#define LCD_DOTCLOCK (FUNC(0) | PORTF(3, 6) | SE | PE)
+#define LCD_DOTCLOCK_GPMI_READY3 (FUNC(1) | PORTF(3, 6) | SE | PE)
+#define LCD_DOTCLOCK_GPIO (FUNC(3) | PORTF(3, 6) | SE | PE)
+#define LCD_CS (FUNC(0) | PORTF(3, 5) | SE)
+#define LCD_CS_GPIO (FUNC(3) | PORTF(3, 5) | SE)
+#define LCD_WR (FUNC(0) | PORTF(3, 4) | SE)
+#define LCD_WR_GPIO (FUNC(3) | PORTF(3, 4) | SE)
+#define LCD_RS (FUNC(0) | PORTF(3, 3) | SE)
+#define LCD_RS_ETM_TCLK (FUNC(1) | PORTF(3, 3) | SE)
+#define LCD_RS_GPIO (FUNC(3) | PORTF(3, 3) | SE)
+#define LCD_RESET (FUNC(0) | PORTF(3, 2) | SE | PE)
+#define LCD_RESET_ETM_TCTL (FUNC(1) | PORTF(3, 2) | SE | PE)
+#define LCD_RESET_GPMI_CE3N (FUNC(2) | PORTF(3, 2) | SE | PE)
+#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 2) | SE | PE)
+#define LCD_D17 (FUNC(0) | PORTF(3, 1) | SE)
+#define LCD_D17_GPIO (FUNC(3) | PORTF(3, 1) | SE)
+#define LCD_D16 (FUNC(0) | PORTF(3, 0) | SE)
+#define LCD_D16_SAIF_ALT_BITCLK (FUNC(2) | PORTF(3, 0) | SE)
+#define LCD_D16_GPIO (FUNC(3) | PORTF(3, 0) | SE)
+
+/* Bank 2, pins 0 ... 15 GPIO pins 64 ... 79 */
+#define EMI_A6 (FUNC(0) | PORTF(4, 15) | SE | VE)
+#define EMI_A6_GPIO (FUNC(3) | PORTF(4, 15) | SE | VE)
+#define EMI_A5 (FUNC(0) | PORTF(4, 14) | SE | VE)
+#define EMI_A5_GPIO (FUNC(3) | PORTF(4, 14) | SE | VE)
+#define EMI_A4 (FUNC(0) | PORTF(4, 13) | SE | VE)
+#define EMI_A4_GPIO (FUNC(3) | PORTF(4, 13) | SE | VE)
+#define EMI_A3 (FUNC(0) | PORTF(4, 12) | SE | VE)
+#define EMI_A3_GPIO (FUNC(3) | PORTF(4, 12) | SE | VE)
+#define EMI_A2 (FUNC(0) | PORTF(4, 11) | SE | VE)
+#define EMI_A2_GPIO (FUNC(3) | PORTF(4, 11) | SE | VE)
+#define EMI_A1 (FUNC(0) | PORTF(4, 10) | SE | VE)
+#define EMI_A1_GPIO (FUNC(3) | PORTF(4, 10) | SE | VE)
+#define EMI_A0 (FUNC(0) | PORTF(4, 9) | SE | VE)
+#define EMI_A0_GPIO (FUNC(3) | PORTF(4, 9) | SE | VE)
+#define ROTARYB (FUNC(0) | PORTF(4, 8) | SE | PE)
+#define ROTARYB_AUART2_CTS (FUNC(1) | PORTF(4, 8) | SE | PE)
+#define ROTARYB_GPMI_CE3N (FUNC(2) | PORTF(4, 8) | SE | PE)
+#define ROTARYB_GPIO (FUNC(3) | PORTF(4, 8) | SE | PE)
+#define ROTARYA (FUNC(0) | PORTF(4, 7) | SE)
+#define ROTARYA_AUART2_RTS (FUNC(1) | PORTF(4, 7) | SE)
+#define ROTARYA_SPDIF (FUNC(2) | PORTF(4, 7) | SE)
+#define ROTARYA_GPIO (FUNC(3) | PORTF(4, 7) | SE)
+#define SSP1_SCK (FUNC(0) | PORTF(4, 6) | SE)
+#define SSP1_SCK_ALT_JTAG_TRST (FUNC(2) | PORTF(4, 6) | SE)
+#define SSP1_SCK_GPIO (FUNC(3) | PORTF(4, 6) | SE)
+#define SSP1_DATA3 (FUNC(0) | PORTF(4, 5) | SE | PE)
+#define SSP1_DATA3_ALT_JTAG_TMS (FUNC(2) | PORTF(4, 5) | SE | PE)
+#define SSP1_DATA3_GPIO (FUNC(3) | PORTF(4, 5) | SE | PE)
+#define SSP1_DATA2 (FUNC(0) | PORTF(4, 4) | SE | PE)
+#define SSP1_DATA2_I2C_SD (FUNC(1) | PORTF(4, 4) | SE | PE)
+#define SSP1_DATA2_ALT_JTAG_RTCK (FUNC(2) | PORTF(4, 4) | SE | PE)
+#define SSP1_DATA2_GPIO (FUNC(3) | PORTF(4, 4) | SE | PE)
+#define SSP1_DATA1 (FUNC(0) | PORTF(4, 3) | SE | PE)
+#define SSP1_DATA1_I2C_CLK (FUNC(1) | PORTF(4, 3) | SE | PE)
+#define SSP1_DATA1_ALT_JTAG_TCK (FUNC(2) | PORTF(4, 3) | SE | PE)
+#define SSP1_DATA1_GPIO (FUNC(3) | PORTF(4, 3) | SE | PE)
+#define SSP1_DATA0 (FUNC(0) | PORTF(4, 2) | SE | PE)
+#define SSP1_DATA0_ALT_JTAG_TDI (FUNC(2) | PORTF(4, 2) | SE | PE)
+#define SSP1_DATA0_GPIO (FUNC(3) | PORTF(4, 2) | SE | PE)
+#define SSP1_DETECT (FUNC(0) | PORTF(4, 1) | SE | PE)
+#define SSP1_DETECT_GPMI_CE3N (FUNC(1) | PORTF(4, 1) | SE | PE)
+#define SSP1_DETECT_USB_ID (FUNC(2) | PORTF(4, 1) | SE | PE)
+#define SSP1_DETECT_GPIO (FUNC(3) | PORTF(4, 1) | SE | PE)
+#define SSP1_CMD (FUNC(0) | PORTF(4, 0) | SE | PE)
+#define SSP1_CMD_JTAG_TDO (FUNC(2) | PORTF(4, 0) | SE | PE)
+#define SSP1_CMD_GPIO (FUNC(3) | PORTF(4, 0) | SE | PE)
+
+/* Bank 2, pins 16 ... 31 GPIO pins 80 ... 95 */
+#define EMI_WEN (FUNC(0) | PORTF(5, 15) | SE | VE)
+#define EMI_WEN_GPIO (FUNC(3) | PORTF(5, 15) | SE | VE)
+#define EMI_RASN (FUNC(0) | PORTF(5, 14) | SE | VE)
+#define EMI_RASN_GPIO (FUNC(3) | PORTF(5, 14) | SE | VE)
+#define EMI_CKE (FUNC(0) | PORTF(5, 13) | SE | VE)
+#define EMI_CKE_GPIO (FUNC(3) | PORTF(5, 13) | SE | VE)
+#define GPMI_CE0N (FUNC(0) | PORTF(5, 12) | SE)
+#define GPMI_CE0N_GPIO (FUNC(3) | PORTF(5, 12) | SE)
+#define GPMI_CE1N (FUNC(0) | PORTF(5, 11) | SE | PE)
+#define GPMI_CE1N_GPIO (FUNC(3) | PORTF(5, 11) | SE | PE)
+#define EMI_CE1N (FUNC(0) | PORTF(5, 10) | SE | VE | PE)
+#define EMI_CE1N_GPIO (FUNC(3) | PORTF(5, 10) | SE | VE | PE)
+#define EMI_CE0N (FUNC(0) | PORTF(5, 9) | SE | VE)
+#define EMI_CE0N_GPIO (FUNC(3) | PORTF(5, 9) | SE | VE)
+#define EMI_CASN (FUNC(0) | PORTF(5, 8) | SE | VE)
+#define EMI_CASN_GPIO (FUNC(3) | PORTF(5, 8) | SE | VE)
+#define EMI_BA1 (FUNC(0) | PORTF(5, 7) | SE | VE)
+#define EMI_BA1_GPIO (FUNC(3) | PORTF(5, 7) | SE | VE)
+#define EMI_BA0 (FUNC(0) | PORTF(5, 6) | SE | VE)
+#define EMI_BA0_GPIO (FUNC(3) | PORTF(5, 6) | SE | VE)
+#define EMI_A12 (FUNC(0) | PORTF(5, 5) | SE | VE)
+#define EMI_A12_GPIO (FUNC(3) | PORTF(5, 5) | SE | VE)
+#define EMI_A11 (FUNC(0) | PORTF(5, 4) | SE | VE)
+#define EMI_A11_GPIO (FUNC(3) | PORTF(5, 4) | SE | VE)
+#define EMI_A10 (FUNC(0) | PORTF(5, 3) | SE | VE)
+#define EMI_A10_GPIO (FUNC(3) | PORTF(5, 3) | SE | VE)
+#define EMI_A9 (FUNC(0) | PORTF(5, 2) | SE | VE)
+#define EMI_A9_GPIO (FUNC(3) | PORTF(5, 2) | SE | VE)
+#define EMI_A8 (FUNC(0) | PORTF(5, 1) | SE | VE)
+#define EMI_A8_GPIO (FUNC(3) | PORTF(5, 1) | SE | VE)
+#define EMI_A7 (FUNC(0) | PORTF(5, 0) | SE | VE)
+#define EMI_A7_GPIO (FUNC(3) | PORTF(5, 0) | SE | VE)
+
+/* Bank 3, pins 0 ... 15 GPIO pins 96 ... 111 */
+#define EMI_D15 (FUNC(0) | PORTF(6, 15) | SE | VE | PE)
+#define EMI_D15_DISABLED (FUNC(3) | PORTF(6, 15) | SE | VE | PE)
+#define EMI_D14 (FUNC(0) | PORTF(6, 14) | SE | VE | PE)
+#define EMI_D14_DISABLED (FUNC(3) | PORTF(6, 14) | SE | VE | PE)
+#define EMI_D13 (FUNC(0) | PORTF(6, 13) | SE | VE | PE)
+#define EMI_D13_DISABLED (FUNC(3) | PORTF(6, 13) | SE | VE | PE)
+#define EMI_D12 (FUNC(0) | PORTF(6, 12) | SE | VE | PE)
+#define EMI_D12_DISABLED (FUNC(3) | PORTF(6, 12) | SE | VE | PE)
+#define EMI_D11 (FUNC(0) | PORTF(6, 11) | SE | VE | PE)
+#define EMI_D11_DISABLED (FUNC(3) | PORTF(6, 11) | SE | VE | PE)
+#define EMI_D10 (FUNC(0) | PORTF(6, 10) | SE | VE | PE)
+#define EMI_D10_DISABLED (FUNC(3) | PORTF(6, 10) | SE | VE | PE)
+#define EMI_D9 (FUNC(0) | PORTF(6, 9) | SE | VE | PE)
+#define EMI_D9_DISABLED (FUNC(3) | PORTF(6, 9) | SE | VE | PE)
+#define EMI_D8 (FUNC(0) | PORTF(6, 8) | SE | VE | PE)
+#define EMI_D8_DISABLED (FUNC(3) | PORTF(6, 8) | SE | VE | PE)
+#define EMI_D7 (FUNC(0) | PORTF(6, 7) | SE | VE | PE)
+#define EMI_D7_DISABLED (FUNC(3) | PORTF(6, 7) | SE | VE | PE)
+#define EMI_D6 (FUNC(0) | PORTF(6, 6) | SE | VE | PE)
+#define EMI_D6_DISABLED (FUNC(3) | PORTF(6, 6) | SE | VE | PE)
+#define EMI_D5 (FUNC(0) | PORTF(6, 5) | SE | VE | PE)
+#define EMI_D5_DISABLED (FUNC(3) | PORTF(6, 5) | SE | VE | PE)
+#define EMI_D4 (FUNC(0) | PORTF(6, 4) | SE | VE | PE)
+#define EMI_D4_DISABLED (FUNC(3) | PORTF(6, 4) | SE | VE | PE)
+#define EMI_D3 (FUNC(0) | PORTF(6, 3) | SE | VE | PE)
+#define EMI_D3_DISABLED (FUNC(3) | PORTF(6, 3) | SE | VE | PE)
+#define EMI_D2 (FUNC(0) | PORTF(6, 2) | SE | VE | PE)
+#define EMI_D2_DISABLED (FUNC(3) | PORTF(6, 2) | SE | VE | PE)
+#define EMI_D1 (FUNC(0) | PORTF(6, 1) | SE | VE | PE)
+#define EMI_D1_DISABLED (FUNC(3) | PORTF(6, 1) | SE | VE | PE)
+#define EMI_D0 (FUNC(0) | PORTF(6, 0) | SE | VE | PE)
+#define EMI_D0_DISABLED (FUNC(3) | PORTF(6, 0) | SE | VE | PE)
+
+/* Bank 3, pins 16 ... 21 GPIO pins 112 ... 117 */
+#define EMI_CLKN (FUNC(0) | PORTF(7, 5) | SE | VE)
+#define EMI_CLKN_DISABLED (FUNC(3) | PORTF(7, 5) | SE | VE)
+#define EMI_CLK (FUNC(0) | PORTF(7, 4) | SE | VE)
+#define EMI_CLK_DISABLED (FUNC(3) | PORTF(7, 4) | SE | VE)
+#define EMI_DQS1 (FUNC(0) | PORTF(7, 3) | SE | VE)
+#define EMI_DQS1_DISABLED (FUNC(3) | PORTF(7, 3) | SE | VE)
+#define EMI_DQS0 (FUNC(0) | PORTF(7, 2) | SE | VE)
+#define EMI_DQS0_DISABLED (FUNC(3) | PORTF(7, 2) | SE | VE)
+#define EMI_DQM1 (FUNC(0) | PORTF(7, 1) | SE | VE | PE)
+#define EMI_DQM1_DISABLED (FUNC(3) | PORTF(7, 1) | SE | VE | PE)
+#define EMI_DQM0 (FUNC(0) | PORTF(7, 0) | SE | VE | PE)
+#define EMI_DQM0_DISABLED (FUNC(3) | PORTF(7, 0) | SE | VE | PE)
+
+#endif /* __ASM_MACH_IOMUX_H */
diff --git a/arch/arm/mach-stm/include/mach/mci.h b/arch/arm/mach-stm/include/mach/mci.h
new file mode 100644
index 0000000..b924908
--- /dev/null
+++ b/arch/arm/mach-stm/include/mach/mci.h
@@ -0,0 +1,32 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MACH_MMC_H
+#define __MACH_MMC_H
+
+struct stm_mci_platform_data {
+ unsigned caps; /**< supported operating modes (MMC_MODE_*) */
+ unsigned voltages; /**< supported voltage range (MMC_VDD_*) */
+ unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */
+ unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */
+ /* TODO */
+ /* function to modify the voltage */
+ /* function to switch the voltage */
+ /* function to detect the presence of a SD card in the socket */
+};
+
+#endif /* __MACH_MMC_H */
diff --git a/arch/arm/mach-stm/iomux-imx23.c b/arch/arm/mach-stm/iomux-imx23.c
new file mode 100644
index 0000000..b0f4046
--- /dev/null
+++ b/arch/arm/mach-stm/iomux-imx23.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define HW_PINCTRL_CTRL 0x000
+#define HW_PINCTRL_MUXSEL0 0x100
+#define HW_PINCTRL_DRIVE0 0x200
+#define HW_PINCTRL_PULL0 0x400
+#define HW_PINCTRL_DOUT0 0x500
+#define HW_PINCTRL_DIN0 0x600
+#define HW_PINCTRL_DOE0 0x700
+
+static uint32_t calc_mux_reg(uint32_t no)
+{
+ /* each register controls 16 pads */
+ return ((no >> 4) << 4) + HW_PINCTRL_MUXSEL0;
+}
+
+static uint32_t calc_strength_reg(uint32_t no)
+{
+ /* each register controls 8 pads */
+ return ((no >> 3) << 4) + HW_PINCTRL_DRIVE0;
+}
+
+static uint32_t calc_pullup_reg(uint32_t no)
+{
+ /* each register controls 32 pads */
+ return ((no >> 5) << 4) + HW_PINCTRL_PULL0;
+}
+
+static uint32_t calc_output_enable_reg(uint32_t no)
+{
+ /* each register controls 32 pads */
+ return ((no >> 5) << 4) + HW_PINCTRL_DOE0;
+}
+
+static uint32_t calc_output_reg(uint32_t no)
+{
+ /* each register controls 32 pads */
+ return ((no >> 5) << 4) + HW_PINCTRL_DOUT0;
+}
+
+/**
+ * @param[in] m One of the defines from iomux-mx23.h to configure *one* pin
+ */
+void imx_gpio_mode(unsigned m)
+{
+ uint32_t reg_offset, gpio_pin, reg;
+
+ gpio_pin = GET_GPIO_NO(m);
+
+ /* configure the pad to its function (always) */
+ reg_offset = calc_mux_reg(gpio_pin);
+ reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 16) << 1));
+ reg |= GET_FUNC(m) << ((gpio_pin % 16) << 1);
+ writel(reg, IMX_IOMUXC_BASE + reg_offset);
+
+ /* some pins are disabled when configured for GPIO */
+ if ((gpio_pin > 95) && (GET_FUNC(m) == IS_GPIO)) {
+ printf("Cannot configure pad %d to GPIO\n", gpio_pin);
+ return;
+ }
+
+ if (SE_PRESENT(m)) {
+ reg_offset = calc_strength_reg(gpio_pin);
+ reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 8) << 2));
+ reg |= GET_STRENGTH(m) << ((gpio_pin % 8) << 2);
+ writel(reg, IMX_IOMUXC_BASE + reg_offset);
+ }
+
+ if (VE_PRESENT(m)) {
+ reg_offset = calc_strength_reg(gpio_pin);
+ if (GET_VOLTAGE(m) == 1)
+ writel(0x1 << (((gpio_pin % 8) << 2) + 2), IMX_IOMUXC_BASE + reg_offset + 4);
+ else
+ writel(0x1 << (((gpio_pin % 8) << 2) + 2), IMX_IOMUXC_BASE + reg_offset + 8);
+ }
+
+ if (PE_PRESENT(m)) {
+ reg_offset = calc_pullup_reg(gpio_pin);
+ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + (GET_PULLUP(m) == 1 ? 4 : 8));
+ }
+
+ if (GET_FUNC(m) == IS_GPIO) {
+ if (GET_GPIODIR(m) == 1) {
+ /* first set the output value */
+ reg_offset = calc_output_reg(gpio_pin);
+ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + (GET_GPIOVAL(m) == 1 ? 4 : 8));
+ /* then the direction */
+ reg_offset = calc_output_enable_reg(gpio_pin);
+ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + 4);
+ } else {
+ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + 8);
+ }
+ }
+}
diff --git a/arch/arm/mach-stm/reset-imx23.c b/arch/arm/mach-stm/reset-imx23.c
new file mode 100644
index 0000000..b35f796
--- /dev/null
+++ b/arch/arm/mach-stm/reset-imx23.c
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define HW_RTC_CTRL 0x000
+# define BM_RTC_CTRL_WATCHDOGEN (1 << 4)
+#define HW_RTC_CTRL_SET 0x004
+#define HW_RTC_CTRL_CLR 0x008
+#define HW_RTC_CTRL_TOG 0x00C
+
+#define HW_RTC_WATCHDOG 0x050
+#define HW_RTC_WATCHDOG_SET 0x054
+#define HW_RTC_WATCHDOG_CLR 0x058
+#define HW_RTC_WATCHDOG_TOG 0x05C
+
+#define WDOG_COUNTER_RATE 1000 /* 1 kHz clock */
+
+#define HW_RTC_PERSISTENT1 0x070
+# define BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER 0x80000000
+#define HW_RTC_PERSISTENT1_SET 0x074
+#define HW_RTC_PERSISTENT1_CLR 0x078
+#define HW_RTC_PERSISTENT1_TOG 0x07C
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let it time out
+ *
+ * TODO There is a much easier way to reset the CPU: Refer bit 2 in
+ * the HW_CLKCTRL_RESET register, data sheet page 106/4-30
+ */
+void __noreturn reset_cpu (unsigned long addr)
+{
+ writel(WDOG_COUNTER_RATE, IMX_WDT_BASE + HW_RTC_WATCHDOG);
+ writel(BM_RTC_CTRL_WATCHDOGEN, IMX_WDT_BASE + HW_RTC_CTRL_SET);
+ writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, IMX_WDT_BASE + HW_RTC_PERSISTENT1);
+
+ while (1)
+ ;
+ /*NOTREACHED*/
+}
+EXPORT_SYMBOL(reset_cpu);
diff --git a/arch/arm/mach-stm/speed-imx23.c b/arch/arm/mach-stm/speed-imx23.c
new file mode 100644
index 0000000..7418ad5
--- /dev/null
+++ b/arch/arm/mach-stm/speed-imx23.c
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2010 Juergen Beisert - Pengutronix
+ *
+ * This code is based partially on code of:
+ *
+ * (c) 2008 Embedded Alley Solutions, Inc.
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Note: all clock frequencies are returned in kHz */
+
+#define HW_CLKCTRL_PLLCTRL0 0x000
+#define HW_CLKCTRL_PLLCTRL1 0x010
+#define HW_CLKCTRL_CPU 0x20
+# define GET_CPU_XTAL_DIV(x) (((x) >> 16) & 0x3ff)
+# define GET_CPU_PLL_DIV(x) ((x) & 0x3f)
+#define HW_CLKCTRL_HBUS 0x30
+#define HW_CLKCTRL_XBUS 0x40
+#define HW_CLKCTRL_XTAL 0x050
+#define HW_CLKCTRL_PIX 0x060
+/* note: no set/clear register! */
+#define HW_CLKCTRL_SSP 0x070
+/* note: no set/clear register! */
+# define CLKCTRL_SSP_CLKGATE (1 << 31)
+# define CLKCTRL_SSP_BUSY (1 << 29)
+# define CLKCTRL_SSP_DIV_MASK 0x1ff
+# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
+# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
+#define HW_CLKCTRL_GPMI 0x080
+/* note: no set/clear register! */
+#define HW_CLKCTRL_SPDIF 0x090
+/* note: no set/clear register! */
+#define HW_CLKCTRL_EMI 0xa0
+/* note: no set/clear register! */
+# define CLKCTRL_EMI_CLKGATE (1 << 31)
+# define GET_EMI_XTAL_DIV(x) (((x) >> 8) & 0xf)
+# define GET_EMI_PLL_DIV(x) ((x) & 0x3f)
+#define HW_CLKCTRL_SAIF 0x0c0
+#define HW_CLKCTRL_TV 0x0d0
+#define HW_CLKCTRL_ETM 0x0e0
+#define HW_CLKCTRL_FRAC 0xf0
+# define CLKCTRL_FRAC_CLKGATEIO (1 << 31)
+# define GET_IOFRAC(x) (((x) >> 24) & 0x3f)
+# define SET_IOFRAC(x) (((x) & 0x3f) << 24)
+# define CLKCTRL_FRAC_CLKGATEPIX (1 << 23)
+# define GET_PIXFRAC(x) (((x) >> 16) & 0x3f)
+# define CLKCTRL_FRAC_CLKGATEEMI (1 << 15)
+# define GET_EMIFRAC(x) (((x) >> 8) & 0x3f)
+# define CLKCTRL_FRAC_CLKGATECPU (1 << 7)
+# define GET_CPUFRAC(x) ((x) & 0x3f)
+#define HW_CLKCTRL_FRAC1 0x100
+#define HW_CLKCTRL_CLKSEQ 0x110
+# define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
+# define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7)
+# define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6)
+# define CLKCTRL_CLKSEQ_BYPASS_SSP (1 << 5)
+# define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4)
+#define HW_CLKCTRL_RESET 0x120
+#define HW_CLKCTRL_STATUS 0x130
+#define HW_CLKCTRL_VERSION 0x140
+
+unsigned imx_get_mpllclk(void)
+{
+ /* the main PLL runs at 480 MHz */
+ return 480U * 1000U;
+}
+
+unsigned imx_get_xtalclk(void)
+{
+ /* the external reference runs at 24 MHz */
+ return 24U * 1000U;
+}
+
+/* used for the SDRAM controller */
+unsigned imx_get_emiclk(void)
+{
+ uint32_t reg;
+ unsigned rate;
+
+ if (readl(IMX_CCM_BASE + HW_CLKCTRL_EMI) & CLKCTRL_EMI_CLKGATE)
+ return 0U; /* clock is off */
+
+ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_EMI)
+ return imx_get_xtalclk() / GET_EMI_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI));
+
+ rate = imx_get_mpllclk();
+ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC);
+ if (!(reg & CLKCTRL_FRAC_CLKGATEEMI)) {
+ rate *= 18U;
+ rate /= GET_EMIFRAC(reg);
+ }
+
+ return rate / GET_EMI_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI));
+}
+
+/*
+ * Source of ssp, gpmi, ir
+ */
+unsigned imx_get_ioclk(void)
+{
+ uint32_t reg;
+ unsigned rate = imx_get_mpllclk();
+
+ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC);
+ if (reg & CLKCTRL_FRAC_CLKGATEIO)
+ return 0U; /* clock is off */
+
+ rate *= 18U;
+ rate /= GET_IOFRAC(reg);
+ return rate;
+}
+
+/**
+ * Setup a new frequency to the IOCLK domain.
+ * @param nc New frequency in [kHz]
+ *
+ * The FRAC divider for the IOCLK must be between 18 (* 18/18) and 35 (* 18/35)
+ */
+unsigned imx_set_ioclk(unsigned nc)
+{
+ uint32_t reg;
+ unsigned div;
+
+ div = imx_get_mpllclk();
+ div *= 18U;
+ div += nc >> 1;
+ div /= nc;
+ if (div > 0x3f)
+ div = 0x3f;
+ /* mask the current settings */
+ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC) & ~(SET_IOFRAC(0x3f));
+ writel(reg | SET_IOFRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC);
+ /* enable the IO clock at its new frequency */
+ writel(CLKCTRL_FRAC_CLKGATEIO, IMX_CCM_BASE + HW_CLKCTRL_FRAC + 8);
+
+ return imx_get_ioclk();
+}
+
+/* this is CPU core clock */
+unsigned imx_get_armclk(void)
+{
+ uint32_t reg;
+ unsigned rate;
+
+ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_CPU)
+ return imx_get_xtalclk() / GET_CPU_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU));
+
+ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC);
+ if (reg & CLKCTRL_FRAC_CLKGATECPU)
+ return 0U; /* should not possible, shouldn't it? */
+
+ rate = imx_get_mpllclk();
+ rate *= 18U;
+ rate /= GET_CPUFRAC(reg);
+
+ return rate / GET_CPU_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU));
+}
+
+/* this is the AHB and APBH bus clock */
+unsigned imx_get_hclk(void)
+{
+ unsigned rate = imx_get_armclk();
+
+ if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) {
+ rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f;
+ rate >>= 5U; /* / 32 */
+ } else
+ rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f;
+ return rate;
+}
+
+/*
+ * Source of UART, debug UART, audio, PWM, dri, timer, digctl
+ */
+unsigned imx_get_xclk(void)
+{
+ unsigned rate = imx_get_xtalclk(); /* runs from the 24 MHz crystal reference */
+
+ return rate / (readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS) & 0x3ff);
+}
+
+/* 'index' gets ignored on i.MX23 */
+unsigned imx_get_sspclk(unsigned index)
+{
+ unsigned rate;
+
+ if (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE)
+ return 0U; /* clock is off */
+
+ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_SSP)
+ rate = imx_get_xtalclk();
+ else
+ rate = imx_get_ioclk();
+
+ return rate / GET_SSP_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_SSP));
+}
+
+/**
+ * @param index Unit index (ignored on i.MX23)
+ * @param nc New frequency in [kHz]
+ * @param high != 0 if ioclk should be the source
+ * @return The new possible frequency in [kHz]
+ */
+unsigned imx_set_sspclk(unsigned index, unsigned nc, int high)
+{
+ uint32_t reg;
+ unsigned ssp_div;
+
+ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_CLKGATE;
+ /* Datasheet says: Do not change the DIV setting if the clock is off */
+ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_SSP);
+ /* Wait while clock is gated */
+ while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE)
+ ;
+
+ if (high)
+ ssp_div = imx_get_ioclk();
+ else
+ ssp_div = imx_get_xtalclk();
+
+ if (nc > ssp_div) {
+ printf("Cannot setup SSP unit clock to %u Hz, base clock is only %u Hz\n", nc, ssp_div);
+ ssp_div = 1U;
+ } else {
+ ssp_div += nc - 1U;
+ ssp_div /= nc;
+ if (ssp_div > CLKCTRL_SSP_DIV_MASK)
+ ssp_div = CLKCTRL_SSP_DIV_MASK;
+ }
+
+ /* Set new divider value */
+ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_DIV_MASK;
+ writel(reg | SET_SSP_DIV(ssp_div), IMX_CCM_BASE + HW_CLKCTRL_SSP);
+
+ /* Wait until new divider value is set */
+ while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_BUSY)
+ ;
+
+ if (high)
+ /* switch to ioclock */
+ writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 8);
+ else
+ /* switch to 24 MHz crystal */
+ writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 4);
+
+ return imx_get_sspclk(index);
+}
+
+void imx_dump_clocks(void)
+{
+ printf("mpll: %10u kHz\n", imx_get_mpllclk());
+ printf("arm: %10u kHz\n", imx_get_armclk());
+ printf("ioclk: %10u kHz\n", imx_get_ioclk());
+ printf("emiclk: %10u kHz\n", imx_get_emiclk());
+ printf("hclk: %10u kHz\n", imx_get_hclk());
+ printf("xclk: %10u kHz\n", imx_get_xclk());
+ printf("ssp: %10u kHz\n", imx_get_sspclk(0));
+}
diff --git a/arch/blackfin/lib/cpu.c b/arch/blackfin/lib/cpu.c
index f96d22d..aed0864 100644
--- a/arch/blackfin/lib/cpu.c
+++ b/arch/blackfin/lib/cpu.c
@@ -32,7 +32,7 @@
#include
#include
-void __noreturn reset_cpu(ulong ignored)
+void __noreturn reset_cpu(unsigned long addr)
{
icache_disable();
diff --git a/arch/m68k/lib/m68k-linuxboot.c b/arch/m68k/lib/m68k-linuxboot.c
index e5e90a8..144d5a3 100644
--- a/arch/m68k/lib/m68k-linuxboot.c
+++ b/arch/m68k/lib/m68k-linuxboot.c
@@ -109,7 +109,7 @@
const char *commandline = getenv ("bootargs");
uint32_t loadaddr,loadsize;
- if (image_check_type(os_header, IH_TYPE_MULTI)) {
+ if (image_get_type(os_header) == IH_TYPE_MULTI) {
printf("Multifile images not handled at the moment\n");
return -1;
}
diff --git a/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c b/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c
index 3b1a25b..d4659d2 100644
--- a/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c
+++ b/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c
@@ -27,7 +27,7 @@
/**
* Reset the cpu by setting up the watchdog timer and let it time out
*/
-void __noreturn reset_cpu (unsigned long ignored)
+void __noreturn reset_cpu (unsigned long addr)
{
while ( ignored ) { ; };
diff --git a/arch/ppc/lib/Makefile b/arch/ppc/lib/Makefile
index 400b1e1..0844d56 100644
--- a/arch/ppc/lib/Makefile
+++ b/arch/ppc/lib/Makefile
@@ -1,6 +1,5 @@
obj-y += bat_rw.o
obj-y += board.o
-obj-y += cache.o
obj-y += extable.o
obj-$(CONFIG_USE_IRQ) += interrupts.o
obj-y += kgdb.o
diff --git a/arch/ppc/lib/cache.c b/arch/ppc/lib/cache.c
deleted file mode 100644
index 3d863b3..0000000
--- a/arch/ppc/lib/cache.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include
-
-
-void flush_cache (ulong start_addr, ulong size)
-{
-#ifndef CONFIG_5xx
- ulong addr, end_addr = start_addr + size;
-
- if (CONFIG_CACHELINE_SIZE) {
- addr = start_addr & (CONFIG_CACHELINE_SIZE - 1);
- for (addr = start_addr;
- addr < end_addr;
- addr += CONFIG_CACHELINE_SIZE) {
- asm ("dcbst 0,%0": :"r" (addr));
- }
- asm ("sync"); /* Wait for all dcbst to complete on bus */
-
- for (addr = start_addr;
- addr < end_addr;
- addr += CONFIG_CACHELINE_SIZE) {
- asm ("icbi 0,%0": :"r" (addr));
- }
- }
- asm ("sync"); /* Always flush prefetch queue in any case */
- asm ("isync");
-#endif
-}
diff --git a/arch/ppc/lib/ppclinux.c b/arch/ppc/lib/ppclinux.c
index 5ee908d..fc22a87 100644
--- a/arch/ppc/lib/ppclinux.c
+++ b/arch/ppc/lib/ppclinux.c
@@ -45,7 +45,7 @@
printf("entering %s: os_header: %p initrd_header: %p oftree: %s\n",
__FUNCTION__, os_header, initrd_header, idata->oftree);
- if (image_check_type(os_header, IH_TYPE_MULTI)) {
+ if (image_get_type(os_header) == IH_TYPE_MULTI) {
unsigned long *data = (unsigned long *)(idata->os->data);
unsigned long len1 = 0, len2 = 0;
diff --git a/arch/ppc/mach-mpc5xxx/cpu.c b/arch/ppc/mach-mpc5xxx/cpu.c
index 7ee1954..4d08c55 100644
--- a/arch/ppc/mach-mpc5xxx/cpu.c
+++ b/arch/ppc/mach-mpc5xxx/cpu.c
@@ -71,7 +71,7 @@
/* ------------------------------------------------------------------------- */
-void __noreturn reset_cpu (unsigned long unused)
+void __noreturn reset_cpu (unsigned long addr)
{
ulong msr;
/* Interrupts and MMU off */
diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c
index ad625d7..38a52a8 100644
--- a/arch/sandbox/board/hostfile.c
+++ b/arch/sandbox/board/hostfile.c
@@ -79,7 +79,9 @@
priv->cdev.size = hf->size;
priv->cdev.ops = &hf_fops;
priv->cdev.priv = hf;
+#ifdef CONFIG_FS_DEVFS
devfs_create(&priv->cdev);
+#endif
return 0;
}
diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c
index c73aa79..287be0d 100644
--- a/arch/sandbox/os/common.c
+++ b/arch/sandbox/os/common.c
@@ -138,7 +138,7 @@
return now;
}
-void __attribute__((noreturn)) reset_cpu(int unused)
+void __attribute__((noreturn)) reset_cpu(unsigned long addr)
{
cookmode();
exit(0);
@@ -213,11 +213,6 @@
return lseek(fd, offset, SEEK_SET);
}
-void flush_cache(unsigned long dummy1, unsigned long dummy2)
-{
- /* why should we? */
-}
-
extern void start_barebox(void);
extern void mem_malloc_init(void *start, void *end);
diff --git a/arch/x86/boards/x86_generic/generic_pc.c b/arch/x86/boards/x86_generic/generic_pc.c
index a6cd7e0..b9c31aa 100644
--- a/arch/x86/boards/x86_generic/generic_pc.c
+++ b/arch/x86/boards/x86_generic/generic_pc.c
@@ -46,7 +46,7 @@
static struct device_d bios_disk_dev = {
.id = -1,
.name = "biosdrive",
- .size = 1,
+ .size = 0, /* auto guess */
};
/*
diff --git a/arch/x86/boot/boot_hdisk.S b/arch/x86/boot/boot_hdisk.S
index 40388e9..fc4c4d5 100644
--- a/arch/x86/boot/boot_hdisk.S
+++ b/arch/x86/boot/boot_hdisk.S
@@ -31,7 +31,6 @@
* from the boot media.
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
.file "boot_hdisk.S"
.code16
@@ -173,4 +172,3 @@
chs_string: .asciz "CHS "
jmp_string: .asciz "JMP "
-#endif
diff --git a/arch/x86/boot/boot_main.S b/arch/x86/boot/boot_main.S
index f3d248a..94fe434 100644
--- a/arch/x86/boot/boot_main.S
+++ b/arch/x86/boot/boot_main.S
@@ -30,7 +30,6 @@
* @brief Fix segment:offset settings of some buggy BIOSs
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
.file "boot_main.S"
.code16
@@ -55,4 +54,3 @@
.size _start, .-_start
-#endif
diff --git a/arch/x86/boot/pmjump.S b/arch/x86/boot/pmjump.S
index d48e198..0e4cd38 100644
--- a/arch/x86/boot/pmjump.S
+++ b/arch/x86/boot/pmjump.S
@@ -20,7 +20,6 @@
* @fn void protected_mode_jump(void)
* @brief Switches the first time from real mode to flat mode
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
#include
#include "boot.h"
@@ -86,4 +85,3 @@
.size protected_mode_jump, .-protected_mode_jump
-#endif
diff --git a/arch/x86/lib/memory16.S b/arch/x86/lib/memory16.S
index 01450fa..cb2f833 100644
--- a/arch/x86/lib/memory16.S
+++ b/arch/x86/lib/memory16.S
@@ -38,7 +38,6 @@
*
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
.section .boot.text.bios_get_memsize, "ax"
.code32
@@ -70,4 +69,3 @@
.size bios_get_memsize, .-bios_get_memsize
-#endif
diff --git a/arch/x86/lib/traveler.S b/arch/x86/lib/traveler.S
index 2b6dc85..0614195 100644
--- a/arch/x86/lib/traveler.S
+++ b/arch/x86/lib/traveler.S
@@ -41,8 +41,6 @@
* Called from a 16 bit real mode segment and returns into a 32 bit segment
*/
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
#include
.file "walkyrie.S"
@@ -180,4 +178,3 @@
.size prot_to_real, .-prot_to_real
-#endif
diff --git a/arch/x86/mach-x86.dox b/arch/x86/mach-x86.dox
index fc5b85a..661e905 100644
--- a/arch/x86/mach-x86.dox
+++ b/arch/x86/mach-x86.dox
@@ -2,7 +2,7 @@
* how to integrate a new CPU (MACH) into this part of the barebox tree
*/
-/** @page x86_runtime barebox on x86 at runtime
+/** @page dev_x86_mach barebox on x86 at runtime
@section mach_x86_memory_layout barebox's memory layout (BIOS based)
diff --git a/commands/Kconfig b/commands/Kconfig
index 0fc80aa..5416073 100644
--- a/commands/Kconfig
+++ b/commands/Kconfig
@@ -202,6 +202,11 @@
select CRC32
prompt "crc"
+config CMD_CRC_CMP
+ tristate
+ depends on CMD_CRC
+ prompt "compare 2 files crc"
+
config CMD_MTEST
tristate
prompt "mtest"
diff --git a/commands/bmp.c b/commands/bmp.c
index 6e17200..5bac031 100644
--- a/commands/bmp.c
+++ b/commands/bmp.c
@@ -193,17 +193,28 @@
return 1;
}
-static const __maybe_unused char cmd_bmp_help[] =
-"Usage: bmp [OPTION]... FILE\n"
-"show bmp image FILE.\n"
-" -f framebuffer device (/dev/fb0)\n"
-" -x x offset (default center)\n"
-" -y y offset (default center)\n"
-" -o render offscreen\n";
+BAREBOX_CMD_HELP_START(bmp)
+BAREBOX_CMD_HELP_USAGE("bmp [OPTIONS] FILE\n")
+BAREBOX_CMD_HELP_SHORT("Show the bitmap FILE on the framebuffer.\n")
+BAREBOX_CMD_HELP_OPT ("-f ", "framebuffer device (/dev/fb0)\n")
+BAREBOX_CMD_HELP_OPT ("-x ", "x offset (default center)\n")
+BAREBOX_CMD_HELP_OPT ("-y ", "y offset (default center)\n")
+BAREBOX_CMD_HELP_OPT ("-o", "render offscreen\n")
+BAREBOX_CMD_HELP_END
+
+/**
+ * @page bmp_command
+
+This command displays a graphics in the bitmap (.bmp) format on the
+framebuffer. Currently the bmp command supports images with 8 and 24 bit
+color depth.
+
+\todo What does the -o (offscreen) option do?
+
+ */
BAREBOX_CMD_START(bmp)
.cmd = do_bmp,
.usage = "show a bmp image",
BAREBOX_CMD_HELP(cmd_bmp_help)
BAREBOX_CMD_END
-
diff --git a/commands/bootm.c b/commands/bootm.c
index 83d36d3..991431b 100644
--- a/commands/bootm.c
+++ b/commands/bootm.c
@@ -167,7 +167,7 @@
goto err_out;
}
- if (image_check_magic(header)) {
+ if (image_get_magic(header) != IH_MAGIC) {
puts ("Bad Magic Number\n");
goto err_out;
}
@@ -225,7 +225,7 @@
}
EXPORT_SYMBOL(unmap_image);
-LIST_HEAD(handler_list);
+static LIST_HEAD(handler_list);
int register_image_handler(struct image_handler *handler)
{
@@ -332,7 +332,7 @@
os_header = &os_handle->header;
- if (image_check_arch(os_header, IH_ARCH)) {
+ if (image_get_arch(os_header) != IH_ARCH) {
printf("Unsupported Architecture 0x%x\n",
image_get_arch(os_header));
goto err_out;
@@ -350,7 +350,7 @@
/* loop through the registered handlers */
list_for_each_entry(handler, &handler_list, list) {
- if (image_check_os(os_header, handler->image_type)) {
+ if (image_get_os(os_header) == handler->image_type) {
handler->bootm(&data);
printf("handler returned!\n");
goto err_out;
@@ -368,19 +368,25 @@
return 1;
}
-static const __maybe_unused char cmd_bootm_help[] =
-"Usage: bootm [OPTION] image\n"
-"Boot application image\n"
-" -n do not verify the images (speeds up boot process)\n"
-" -h show advanced options\n";
-
+BAREBOX_CMD_HELP_START(bootm)
+BAREBOX_CMD_HELP_USAGE("bootm [-n] image\n")
+BAREBOX_CMD_HELP_SHORT("Boot an application image.\n")
+BAREBOX_CMD_HELP_OPT ("-n", "Do not verify the image (speeds up boot process)\n")
+BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(bootm)
.cmd = do_bootm,
- .usage = "boot application image",
+ .usage = "boot an application image",
BAREBOX_CMD_HELP(cmd_bootm_help)
BAREBOX_CMD_END
+/**
+ * @page bootm_command
+
+\todo What does bootm do, what kind of image does it boot?
+
+ */
+
#ifdef CONFIG_CMD_IMI
static int do_iminfo(struct command *cmdtp, int argc, char *argv[])
{
@@ -409,7 +415,7 @@
/* Copy header so we can blank CRC field for re-calculation */
memmove (&header, (char *)addr, image_get_header_size());
- if (image_check_magic(hdr)) {
+ if (image_get_magic(hdr) != IH_MAGIC) {
puts (" Bad Magic Number\n");
return 1;
}
@@ -440,14 +446,16 @@
return 0;
}
-BAREBOX_CMD(
- iminfo, 1, do_iminfo,
- "iminfo - print header information for application image\n",
- "addr [addr ...]\n"
- " - print header information for application image starting at\n"
- " address 'addr' in memory; this includes verification of the\n"
- " image contents (magic number, header and payload checksums)\n"
-);
+BAREBOX_CMD_HELP_START(iminfo)
+BAREBOX_CMD_HELP_USAGE("iminfo\n")
+BAREBOX_CMD_HELP_SHORT("Print header information for an application image.\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(iminfo)
+ .cmd = do_iminfo,
+ .usage = "print header information for an application image",
+ BAREBOX_CMD_HELP(cmd_iminfo_help)
+BAREBOX_CMD_END
#endif /* CONFIG_CMD_IMI */
diff --git a/commands/cat.c b/commands/cat.c
index 41b3324..37e6505 100644
--- a/commands/cat.c
+++ b/commands/cat.c
@@ -85,22 +85,15 @@
return err;
}
-static const __maybe_unused char cmd_cat_help[] =
-"Usage: cat [FILES]\n"
-"Concatenate files on stdout. Currently only printable characters\n"
-"and \\n and \\t are printed, but this should be optional\n";
+BAREBOX_CMD_HELP_START(cat)
+BAREBOX_CMD_HELP_USAGE("cat [FILES]\n")
+BAREBOX_CMD_HELP_SHORT("Concatenate files on stdout.\n")
+BAREBOX_CMD_HELP_TEXT ("Currently only printable characters and \\ n and \\ t are printed,\n")
+BAREBOX_CMD_HELP_TEXT ("but this should be optional.\n")
+BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(cat)
.cmd = do_cat,
.usage = "concatenate file(s)",
BAREBOX_CMD_HELP(cmd_cat_help)
BAREBOX_CMD_END
-
-/**
- * @page cat_command cat (concatenate)
- *
- * Usage is: cat \ [\ ...]
- *
- * Concatenate files to stdout. Currently only printable characters
- * and \\n and \\t are printed, but this should be optional
- */
diff --git a/commands/cd.c b/commands/cd.c
index a842f4d..d73be32 100644
--- a/commands/cd.c
+++ b/commands/cd.c
@@ -47,21 +47,14 @@
return 0;
}
-static const __maybe_unused char cmd_cd_help[] =
-"Usage: cd [directory]\n"
-"change to directory. If called without argument, change to /\n";
+BAREBOX_CMD_HELP_START(cd)
+BAREBOX_CMD_HELP_USAGE("cd [directory]\n")
+BAREBOX_CMD_HELP_SHORT("Change to directory.\n")
+BAREBOX_CMD_HELP_TEXT ("If called without an argument, change to the root directory /.\n")
+BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(cd)
.cmd = do_cd,
.usage = "change working directory",
BAREBOX_CMD_HELP(cmd_cd_help)
BAREBOX_CMD_END
-
-/**
- * @page cd_command cd (change working directory)
- *
- * Usage is: cd [\]
- *
- * Change to \. If called without argument, change to \b /
- * (root)
- */
diff --git a/commands/clear.c b/commands/clear.c
index 7589a0c..6a6b6c5 100644
--- a/commands/clear.c
+++ b/commands/clear.c
@@ -31,6 +31,11 @@
return 0;
}
+BAREBOX_CMD_HELP_START(clear)
+BAREBOX_CMD_HELP_USAGE("clear\n")
+BAREBOX_CMD_HELP_SHORT("Clear the screen.\n")
+BAREBOX_CMD_HELP_END
+
BAREBOX_CMD_START(clear)
.cmd = do_clear,
.usage = "clear screen",
diff --git a/commands/cp.c b/commands/cp.c
index 2c35ba1..ae8719b 100644
--- a/commands/cp.c
+++ b/commands/cp.c
@@ -51,7 +51,7 @@
if (S_ISDIR(statbuf.st_mode))
last_is_dir = 1;
}
-
+
if (argc > 3 && !last_is_dir) {
printf("cp: target `%s' is not a directory\n", argv[argc - 1]);
return 1;
@@ -77,10 +77,19 @@
return ret;
}
-static const __maybe_unused char cmd_cp_help[] =
-"Usage: cp \n"
-"cp copies file to .\n"
-"This command is file based only. See memcpy for memory copy\n";
+BAREBOX_CMD_HELP_START(cp)
+BAREBOX_CMD_HELP_USAGE("cp \n")
+BAREBOX_CMD_HELP_SHORT("copy file from to .\n")
+BAREBOX_CMD_HELP_END
+
+/**
+ * @page cp_command
+This command operates on files.
+
+If you want to copy between memory blocks, use 'memcpy'.
+
+\todo What does this mean? Add examples.
+ */
BAREBOX_CMD_START(cp)
.cmd = do_cp,
@@ -88,14 +97,3 @@
BAREBOX_CMD_HELP(cmd_cp_help)
BAREBOX_CMD_END
-/**
- * @page cp_command cp: Copy file
- *
- * Usage: cp \ [\] \
- *
- * \c cp copies file \ to \
- *
- * Currently only this form is supported and you have to specify the exact
- * target filename (not a target directory).\n
- * This command is file based only. See memcpy for generic memory copy
- */
diff --git a/commands/crc.c b/commands/crc.c
index 4842cdc..0873a1c 100644
--- a/commands/crc.c
+++ b/commands/crc.c
@@ -30,20 +30,80 @@
#include