diff --git a/Documentation/boards.dox b/Documentation/boards.dox index 41de836..6bcc14f 100644 --- a/Documentation/boards.dox +++ b/Documentation/boards.dox @@ -56,6 +56,7 @@ MIPS type: @li @subpage dlink_dir_320 +@li @subpage loongson_ls1b @li @subpage qemu_malta @li @subpage rzx50 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ca240d2..b819b49 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -63,6 +63,9 @@ select SYS_SUPPORTS_LITTLE_ENDIAN select HAS_DEBUG_LL +config MACH_MIPS_LOONGSON + bool "Loongson-based boards" + config MACH_MIPS_XBURST bool "Ingenic XBurst-based boards" select SYS_HAS_CPU_MIPS32_R1 @@ -78,6 +81,7 @@ source arch/mips/mach-malta/Kconfig source arch/mips/mach-ar231x/Kconfig source arch/mips/mach-bcm47xx/Kconfig +source arch/mips/mach-loongson/Kconfig source arch/mips/mach-xburst/Kconfig endmenu @@ -114,6 +118,14 @@ prompt "CPU type" default CPU_MIPS32_R2 +config CPU_LOONGSON1B + bool "Loongson 1B" + depends on SYS_HAS_CPU_LOONGSON1B + select CPU_LOONGSON1 + help + The Loongson 1B is a 32-bit SoC, which implements the MIPS32 + release 2 instruction set. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -170,6 +182,15 @@ endchoice +config CPU_LOONGSON1 + bool + select CPU_MIPS32 + select CPU_MIPSR2 + select CPU_SUPPORTS_32BIT_KERNEL + +config SYS_HAS_CPU_LOONGSON1B + bool + config SYS_HAS_CPU_MIPS32_R1 bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 62e1acf..8986fcf 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -49,6 +49,9 @@ cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON1) += \ + $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ + -Wa,-mips32r2 -Wa,--trap CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) @@ -78,6 +81,9 @@ machine-$(CONFIG_MACH_MIPS_BCM47XX) := bcm47xx board-$(CONFIG_BOARD_DLINK_DIR320) := dlink-dir-320 +machine-$(CONFIG_MACH_MIPS_LOONGSON) := loongson +board-$(CONFIG_BOARD_LOONGSON_TECH_LS1B) := loongson-ls1b + machine-$(CONFIG_MACH_MIPS_XBURST) := xburst board-$(CONFIG_BOARD_RZX50) := rzx50 diff --git a/arch/mips/boards/loongson-ls1b/Makefile b/arch/mips/boards/loongson-ls1b/Makefile new file mode 100644 index 0000000..a21952b --- /dev/null +++ b/arch/mips/boards/loongson-ls1b/Makefile @@ -0,0 +1,2 @@ +obj-y += ram.o +obj-y += serial.o diff --git a/arch/mips/boards/loongson-ls1b/include/board/board_pbl_start.h b/arch/mips/boards/loongson-ls1b/include/board/board_pbl_start.h new file mode 100644 index 0000000..1a92794 --- /dev/null +++ b/arch/mips/boards/loongson-ls1b/include/board/board_pbl_start.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Antony Pavlov + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + + .macro board_pbl_start + .set push + .set noreorder + + mips_barebox_10h + + mips_disable_interrupts + + debug_ll_ns16550_init + + debug_ll_ns16550_outc '.' + debug_ll_ns16550_outnl + + mips_nmon + + copy_to_link_location pbl_start + + .set pop + .endm diff --git a/arch/mips/boards/loongson-ls1b/include/board/debug_ll.h b/arch/mips/boards/loongson-ls1b/include/board/debug_ll.h new file mode 100644 index 0000000..e60ce4c --- /dev/null +++ b/arch/mips/boards/loongson-ls1b/include/board/debug_ll.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 Antony Pavlov + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/** @file + * This File contains declaration for early output support + */ +#ifndef __LOONGSON_TECH_LS1B_DEBUG_LL_H__ +#define __LOONGSON_TECH_LS1B_DEBUG_LL_H__ + +#include +#include + +#define DEBUG_LL_UART_ADDR KSEG1ADDR(LS1X_UART2_BASE) +#define DEBUG_LL_UART_SHIFT 0 + +#define DEBUG_LL_UART_CLK (83000000 / 16) +#define DEBUG_LL_UART_BPS CONFIG_BAUDRATE +#define DEBUG_LL_UART_DIVISOR (DEBUG_LL_UART_CLK / DEBUG_LL_UART_BPS) + +#endif /* __LOONGSON_TECH_LS1B_DEBUG_LL_H__ */ diff --git a/arch/mips/boards/loongson-ls1b/loongson_ls1b.dox b/arch/mips/boards/loongson-ls1b/loongson_ls1b.dox new file mode 100644 index 0000000..f96a3f8 --- /dev/null +++ b/arch/mips/boards/loongson-ls1b/loongson_ls1b.dox @@ -0,0 +1,47 @@ +/** @page loongson_ls1b Loongson LS1B demo board + +The LS1B is a development board made by Loongson Technology Corp. Ltd. + +The board has +@li Loongson LS1B SoC 250 MHz; +@li 64 MiB SDRAM; +@li 512 KiB SPI boot ROM; +@li 128M x 8 Bit NAND Flash Memory; +@li 2 x RS232 serial interfaces (DB9 connectors); +@li 2 x Ethernet interfaces; +@li 4 x USB interfaces; +@li microSD card slot; +@li LCD display (480x272); +@li audio controller; +@li beeper; +@li buttons; +@li EJTAG 10-pin connector. + +The board uses PMON2000 as bootloader. + +Barebox mini-howto: + +1. Connect to the boards's UART2; + +2. Turn board's power on; + +3. Wait 'Press to execute loading image' prompt and press the space key. + +4. Upload zbarebox.bin via Ymodem +@verbatim + PMON> ymodem base=0xa0200000 +@endverbatim + +5. Run barebox +@verbatim + PMON> g -e 0xa0200000 +@endverbatim + +Loongson links: +@li http://en.wikipedia.org/wiki/Loongson +@li http://www.linux-mips.org/wiki/Loongson +@li https://github.com/loongson-gz +@li http://www.linux-mips.org/wiki/PMON_2000 +@li http://www.opsycon.se/PMON2000/Main + +*/ diff --git a/arch/mips/boards/loongson-ls1b/ram.c b/arch/mips/boards/loongson-ls1b/ram.c new file mode 100644 index 0000000..9e655ab --- /dev/null +++ b/arch/mips/boards/loongson-ls1b/ram.c @@ -0,0 +1,12 @@ +#include +#include +#include +#include + +static int mem_init(void) +{ + mips_add_ram0(SZ_64M); + + return 0; +} +mem_initcall(mem_init); diff --git a/arch/mips/boards/loongson-ls1b/serial.c b/arch/mips/boards/loongson-ls1b/serial.c new file mode 100644 index 0000000..d8e0f7c --- /dev/null +++ b/arch/mips/boards/loongson-ls1b/serial.c @@ -0,0 +1,22 @@ +#include +#include +#include + +#include + +static struct NS16550_plat serial_plat = { + .clock = 83000000, + .shift = 0, +}; + +static int console_init(void) +{ + barebox_set_model("Loongson Tech LS1B Demo Board"); + barebox_set_hostname("ls1b"); + + add_ns16550_device(DEVICE_ID_DYNAMIC, KSEG1ADDR(LS1X_UART2_BASE), + 8, IORESOURCE_MEM_8BIT, &serial_plat); + + return 0; +} +console_initcall(console_init); diff --git a/arch/mips/configs/loongson-ls1b_defconfig b/arch/mips/configs/loongson-ls1b_defconfig new file mode 100644 index 0000000..0322052 --- /dev/null +++ b/arch/mips/configs/loongson-ls1b_defconfig @@ -0,0 +1,42 @@ +CONFIG_MACH_MIPS_LOONGSON=y +CONFIG_PBL_IMAGE=y +CONFIG_STACK_SIZE=0x7000 +CONFIG_BROKEN=y +CONFIG_EXPERIMENTAL=y +CONFIG_MALLOC_TLSF=y +CONFIG_LONGHELP=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_HUSH_GETOPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_PARTITION=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +CONFIG_POLLER=y +CONFIG_RESET_SOURCE=y +CONFIG_DEBUG_INFO=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_LET=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GLOBAL=y +# CONFIG_CMD_MOUNT is not set +# CONFIG_CMD_UMOUNT is not set +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_SAVES=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_IOMEM=y +# CONFIG_CMD_BOOTM is not set +CONFIG_FLEXIBLE_BOOTARGS=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_TIMEOUT=y +# CONFIG_SPI is not set +CONFIG_ZLIB=y +CONFIG_BZLIB=y diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index e63f847..dcc2a27 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -28,6 +28,20 @@ #define PRID_COMP_BROADCOM 0x020000 #define PRID_COMP_INGENIC 0xd00000 +/* + * Assigned Processor ID (implementation) values for bits 15:8 of the PRId + * register. In order to detect a certain CPU type exactly eventually + * additional registers may need to be examined. + */ + +#define PRID_IMP_MASK 0xff00 + +/* + * These are valid when 23:16 == PRID_COMP_LEGACY + */ + +#define PRID_IMP_LOONGSON1 0x4200 + #define PRID_IMP_UNKNOWN 0xff00 /* @@ -50,6 +64,18 @@ #define PRID_IMP_JZRISC 0x0200 /* + * Particular Revision values for bits 7:0 of the PRId register. + */ + +#define PRID_REV_MASK 0x00ff + +/* + * Definitions for 7:0 on legacy processors + */ + +#define PRID_REV_LOONGSON1B 0x0020 + +/* * Older processors used to encode processor version and revision in two * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores * have switched to use the 8-bits as 3:3:2 bitfield with the last field as @@ -80,6 +106,7 @@ CPU_24K, CPU_BMIPS3300, CPU_JZRISC, + CPU_LOONGSON1, CPU_LAST }; diff --git a/arch/mips/lib/cpu-probe.c b/arch/mips/lib/cpu-probe.c index de45421..8235a54 100644 --- a/arch/mips/lib/cpu-probe.c +++ b/arch/mips/lib/cpu-probe.c @@ -81,6 +81,24 @@ BUG_ON(!ok); /* Arch spec violation! */ } +static inline void cpu_probe_legacy(struct cpuinfo_mips *c) +{ + switch (c->processor_id & PRID_IMP_MASK) { + case PRID_IMP_LOONGSON1: + decode_configs(c); + + c->cputype = CPU_LOONGSON1; + + switch (c->processor_id & PRID_REV_MASK) { + case PRID_REV_LOONGSON1B: + __cpu_name = "Loongson 1B"; + break; + } + + break; + } +} + static inline void cpu_probe_mips(struct cpuinfo_mips *c) { decode_configs(c); @@ -130,6 +148,9 @@ c->processor_id = read_c0_prid(); switch (c->processor_id & 0xff0000) { + case PRID_COMP_LEGACY: + cpu_probe_legacy(c); + break; case PRID_COMP_MIPS: cpu_probe_mips(c); break; diff --git a/arch/mips/lib/csrc-r4k.c b/arch/mips/lib/csrc-r4k.c index 2978fcf..c699f2b 100644 --- a/arch/mips/lib/csrc-r4k.c +++ b/arch/mips/lib/csrc-r4k.c @@ -32,7 +32,7 @@ static struct clocksource cs = { .read = c0_hpt_read, - .mask = 0xffffffff, + .mask = CLOCKSOURCE_MASK(32), }; static int clocksource_init(void) diff --git a/arch/mips/mach-loongson/Kconfig b/arch/mips/mach-loongson/Kconfig new file mode 100644 index 0000000..c9f1902 --- /dev/null +++ b/arch/mips/mach-loongson/Kconfig @@ -0,0 +1,24 @@ +if MACH_MIPS_LOONGSON + +config ARCH_TEXT_BASE + hex + default 0xa0800000 + +choice + prompt "Board type" + +config BOARD_LOONGSON_TECH_LS1B + bool "Loongson Tech. LS1B demo board" + select SYS_HAS_CPU_LOONGSON1B + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select CSRC_R4K_LIB + select HAS_DEBUG_LL + select DRIVER_SERIAL_NS16550 + select HAVE_PBL_IMAGE + select HAVE_IMAGE_COMPRESSION + select HAS_NMON + +endchoice + +endif diff --git a/arch/mips/mach-loongson/Makefile b/arch/mips/mach-loongson/Makefile new file mode 100644 index 0000000..52b36f3 --- /dev/null +++ b/arch/mips/mach-loongson/Makefile @@ -0,0 +1 @@ +obj-y += loongson1_reset.o diff --git a/arch/mips/mach-loongson/include/mach/debug_ll.h b/arch/mips/mach-loongson/include/mach/debug_ll.h new file mode 100644 index 0000000..b999f5e --- /dev/null +++ b/arch/mips/mach-loongson/include/mach/debug_ll.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Antony Pavlov + * + * This file is part of barebox. + * See file CREDITS for list of people who contributed to this project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_LOONGSON_DEBUG_LL__ +#define __MACH_LOONGSON_DEBUG_LL__ + +/** @file + * This File contains declaration for early output support + */ +#include +#include + +#endif /* __MACH_LOONGSON_DEBUG_LL__ */ diff --git a/arch/mips/mach-loongson/include/mach/loongson1.h b/arch/mips/mach-loongson/include/mach/loongson1.h new file mode 100644 index 0000000..12fdbc0 --- /dev/null +++ b/arch/mips/mach-loongson/include/mach/loongson1.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2011 Zhang, Keguang + * + * Register mappings for Loongson 1 + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H +#define __ASM_MACH_LOONGSON1_LOONGSON1_H + +#include + +/* Loongson 1 Register Bases */ +#define LS1X_UART0_BASE 0x1fe40000 +#define LS1X_UART1_BASE 0x1fe44000 +#define LS1X_UART2_BASE 0x1fe48000 +#define LS1X_UART3_BASE 0x1fe4c000 +#define LS1X_WDT_BASE 0x1fe5c060 + +/* Loongson 1 watchdog register definitions */ +#define LS1X_WDT_REG(x) \ + ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x))) + +#define LS1X_WDT_EN LS1X_WDT_REG(0x0) +#define LS1X_WDT_SET LS1X_WDT_REG(0x4) +#define LS1X_WDT_TIMER LS1X_WDT_REG(0x8) + +#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */ diff --git a/arch/mips/mach-loongson/loongson1_reset.c b/arch/mips/mach-loongson/loongson1_reset.c new file mode 100644 index 0000000..8975392 --- /dev/null +++ b/arch/mips/mach-loongson/loongson1_reset.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Antony Pavlov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include + +void __noreturn reset_cpu(ulong addr) +{ + __raw_writel(0x1, LS1X_WDT_EN); + __raw_writel(0x1, LS1X_WDT_SET); + __raw_writel(0x1, LS1X_WDT_TIMER); + + unreachable(); +} +EXPORT_SYMBOL(reset_cpu); diff --git a/arch/mips/mach-loongson/mach-loongson.dox b/arch/mips/mach-loongson/mach-loongson.dox new file mode 100644 index 0000000..7838ce5 --- /dev/null +++ b/arch/mips/mach-loongson/mach-loongson.dox @@ -0,0 +1,7 @@ +/** @page dev_loongson_mach Loongson in barebox + +@section loongson_boards Loongson-based boards + +@li @subpage loongson_ls1b + +*/ diff --git a/arch/mips/mach-mips.dox b/arch/mips/mach-mips.dox index 750a451..1002b16 100644 --- a/arch/mips/mach-mips.dox +++ b/arch/mips/mach-mips.dox @@ -59,6 +59,10 @@ @li @subpage dev_bcm47xx_mach +@subsection mach_loongson_info Loongson-based boards + +@li @subpage dev_loongson_mach + @subsection mach_xburst_info XBurst-based boards @li @subpage dev_xburst_mach