diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 0749239..c7c657b 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -25,6 +25,12 @@
 			device-path = &usdhc1, "partname:barebox-environment";
 			status = "disabled";
 		};
+
+		environment-sd2 {
+			compatible = "barebox,environment";
+			device-path = &usdhc2, "partname:barebox-environment";
+			status = "disabled";
+		};
 	};
 };
 
@@ -125,6 +131,27 @@
 	};
 };
 
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	bus-width = <8>;
+	non-removable;
+	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0xe0000>;
+	};
+
+	partition@e0000 {
+		label = "barebox-environment";
+		reg = <0xe0000 0x20000>;
+	};
+};
+
 &iomuxc {
         pinctrl-names = "default";
 
@@ -196,6 +223,21 @@
 				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 			>;
 		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     	0x17059
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     	0x10059
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 	0x17059
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 	0x17059
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 	0x17059
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 	0x17059
+				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 	0x17059
+				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 	0x17059
+				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 	0x17059
+				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 	0x17059
+			>;
+		};
 	};
 };