diff --git a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h index 74a1a88..73028d2 100644 --- a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h +++ b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h @@ -22,16 +22,38 @@ #define FB_SYNC_CLK_SEL_EN 0x02000000 /* + * Specify the way your display is connected. The IPU can arbitrarily + * map the internal colors to the external data lines. We only support + * the following mappings at the moment. + */ +enum disp_data_mapping { + /* blue -> d[0..5], green -> d[6..11], red -> d[12..17] */ + IPU_DISP_DATA_MAPPING_RGB666, + /* blue -> d[0..4], green -> d[5..10], red -> d[11..15] */ + IPU_DISP_DATA_MAPPING_RGB565, + /* blue -> d[0..7], green -> d[8..15], red -> d[16..23] */ + IPU_DISP_DATA_MAPPING_RGB888, +}; + +/* * struct mx3fb_platform_data - mx3fb platform data */ struct imx_ipu_fb_platform_data { struct fb_videomode *mode; unsigned char bpp; u_int num_modes; + enum disp_data_mapping disp_data_fmt; void __iomem *framebuffer; + unsigned long framebuffer_size; void __iomem *framebuffer_ovl; + unsigned long framebuffer_ovl_size; /** hook to enable backlight and stuff */ void (*enable)(int enable); + /* + * Fractional pixelclock divider causes jitter which some displays + * or LVDS transceivers can't handle. Disable it if necessary. + */ + int disable_fractional_divider; }; #endif /* __MACH_IMX_IPU_FB_H__ */ diff --git a/drivers/video/fb.c b/drivers/video/fb.c index 4263027..c36b9ad 100644 --- a/drivers/video/fb.c +++ b/drivers/video/fb.c @@ -78,6 +78,8 @@ if (!info->line_length) info->line_length = info->xres * (info->bits_per_pixel >> 3); + if (!info->screen_size) + info->screen_size = info->line_length * info->yres; if (!ret) { dev->resource[0].start = (resource_size_t)info->screen_base; diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c index b2ed723..7276647 100644 --- a/drivers/video/imx-ipu-fb.c +++ b/drivers/video/imx-ipu-fb.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -36,11 +37,14 @@ void (*enable)(int enable); + enum disp_data_mapping disp_data_fmt; + struct fb_info info; struct fb_info overlay; struct device_d *dev; unsigned int alpha; + int disable_fractional_divider; }; /* IPU DMA Controller channel definitions. */ @@ -89,28 +93,18 @@ IPU_PIX_FMT_BGR666, /* 3 bytes */ IPU_PIX_FMT_RGB24, + /* 3 bytes */ + IPU_PIX_FMT_RGB32, }; -struct pixel_fmt_cfg { - u32 b0; - u32 b1; - u32 b2; - u32 acc; +struct di_mapping { + uint32_t b0, b1, b2; }; -static struct pixel_fmt_cfg fmt_cfg[] = { - [IPU_PIX_FMT_RGB24] = { - 0x1600AAAA, 0x00E05555, 0x00070000, 3, - }, - [IPU_PIX_FMT_RGB666] = { - 0x0005000F, 0x000B000F, 0x0011000F, 1, - }, - [IPU_PIX_FMT_BGR666] = { - 0x0011000F, 0x000B000F, 0x0005000F, 1, - }, - [IPU_PIX_FMT_RGB565] = { - 0x0004003F, 0x000A000F, 0x000F003F, 1, - } +static const struct di_mapping di_mappings[] = { + [IPU_DISP_DATA_MAPPING_RGB666] = { 0x0005000f, 0x000b000f, 0x0011000f }, + [IPU_DISP_DATA_MAPPING_RGB565] = { 0x0004003f, 0x000a000f, 0x000f003f }, + [IPU_DISP_DATA_MAPPING_RGB888] = { 0x00070000, 0x000f0000, 0x00170000 }, }; enum ipu_panel { @@ -268,6 +262,7 @@ struct fb_bitfield green; struct fb_bitfield blue; struct fb_bitfield transp; + int bits_per_pixel; }; static struct imx_ipu_fb_rgb def_rgb_16 = { @@ -275,6 +270,7 @@ .green = {.offset = 5, .length = 6,}, .blue = {.offset = 0, .length = 5,}, .transp = {.offset = 0, .length = 0,}, + .bits_per_pixel = 16, }; static struct imx_ipu_fb_rgb def_rgb_24 = { @@ -282,6 +278,7 @@ .green = {.offset = 8, .length = 8,}, .blue = {.offset = 0, .length = 8,}, .transp = {.offset = 0, .length = 0,}, + .bits_per_pixel = 24, }; static struct imx_ipu_fb_rgb def_rgb_32 = { @@ -289,112 +286,99 @@ .green = {.offset = 8, .length = 8,}, .blue = {.offset = 0, .length = 8,}, .transp = {.offset = 24, .length = 8,}, + .bits_per_pixel = 32, }; -struct chan_param_mem_planar { - /* Word 0 */ - u32 xv:10; - u32 yv:10; - u32 xb:12; +#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size)) - u32 yb:12; - u32 res1:2; - u32 nsb:1; - u32 lnpb:6; - u32 ubo_l:11; +#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10) +#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 10) +#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 20, 12) - u32 ubo_h:15; - u32 vbo_l:17; +#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12) +#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 44, 1) +#define IPU_FIELD_RES1 IPU_CPMEM_WORD(0, 45, 1) +#define IPU_FIELD_NSB IPU_CPMEM_WORD(0, 46, 1) +#define IPU_FIELD_LNPB IPU_CPMEM_WORD(0, 47, 6) +#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 53, 10) +#define IPU_FIELD_SY_L IPU_CPMEM_WORD(0, 63, 1) - u32 vbo_h:9; - u32 res2:3; - u32 fw:12; - u32 fh_l:8; +#define IPU_FIELD_SY_H IPU_CPMEM_WORD(0, 64, 9) +#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 73, 10) +#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 83, 10) +#define IPU_FIELD_SDX_L IPU_CPMEM_WORD(0, 93, 3) - u32 fh_h:4; - u32 res3:28; +#define IPU_FIELD_SDX_H IPU_CPMEM_WORD(0, 96, 2) +#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 5) +#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 103, 1) +#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 104, 1) +#define IPU_FIELD_SDR1 IPU_CPMEM_WORD(0, 105, 1) +#define IPU_FIELD_RES2 IPU_CPMEM_WORD(0, 106, 2) +#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 108, 12) +#define IPU_FIELD_FH_L IPU_CPMEM_WORD(0, 120, 8) - /* Word 1 */ - u32 eba0; +#define IPU_FIELD_FH_H IPU_CPMEM_WORD(0, 128, 4) +#define IPU_FIELD_RES3 IPU_CPMEM_WORD(0, 132, 28) - u32 eba1; +#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 32) - u32 bpp:3; - u32 sl:14; - u32 pfs:3; - u32 bam:3; - u32 res4:2; - u32 npb:6; - u32 res5:1; +#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 32, 32) - u32 sat:2; - u32 res6:30; -} __attribute__ ((packed)); +#define IPU_FIELD_BPP IPU_CPMEM_WORD(1, 64, 3) +#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 67, 14) +#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 81, 3) +#define IPU_FIELD_BAM IPU_CPMEM_WORD(1, 84, 3) +#define IPU_FIELD_RES4 IPU_CPMEM_WORD(1, 87, 2) +#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 89, 6) +#define IPU_FIELD_RES5 IPU_CPMEM_WORD(1, 95, 1) -struct chan_param_mem_interleaved { - /* Word 0 */ - u32 xv:10; - u32 yv:10; - u32 xb:12; +#define IPU_FIELD_SAT IPU_CPMEM_WORD(1, 96, 2) +#define IPU_FIELD_SCC IPU_CPMEM_WORD(1, 98, 1) +#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 99, 5) +#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 104, 5) +#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 109, 5) +#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 114, 5) +#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 119, 3) +#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 122, 3) +#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 125, 3) - u32 yb:12; - u32 sce:1; - u32 res1:1; - u32 nsb:1; - u32 lnpb:6; - u32 sx:10; - u32 sy_l:1; +#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 128, 3) +#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(1, 131, 1) +#define IPU_FIELD_RES6 IPU_CPMEM_WORD(1, 132, 28) - u32 sy_h:9; - u32 ns:10; - u32 sm:10; - u32 sdx_l:3; - - u32 sdx_h:2; - u32 sdy:5; - u32 sdrx:1; - u32 sdry:1; - u32 sdr1:1; - u32 res2:2; - u32 fw:12; - u32 fh_l:8; - - u32 fh_h:4; - u32 res3:28; - - /* Word 1 */ - u32 eba0; - - u32 eba1; - - u32 bpp:3; - u32 sl:14; - u32 pfs:3; - u32 bam:3; - u32 res4:2; - u32 npb:6; - u32 res5:1; - - u32 sat:2; - u32 scc:1; - u32 ofs0:5; - u32 ofs1:5; - u32 ofs2:5; - u32 ofs3:5; - u32 wid0:3; - u32 wid1:3; - u32 wid2:3; - - u32 wid3:3; - u32 dec_sel:1; - u32 res6:28; -} __attribute__ ((packed)); - -union chan_param_mem { - struct chan_param_mem_planar pp; - struct chan_param_mem_interleaved ip; +struct ipu_cpmem_word { + u32 data[5]; }; +struct ipu_ch_param { + struct ipu_cpmem_word word[2]; +}; + +void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v) +{ + u32 bit = (wbs >> 8) % 160; + u32 size = wbs & 0xff; + u32 word = (wbs >> 8) / 160; + u32 i = bit / 32; + u32 ofs = bit % 32; + u32 mask = (1 << size) - 1; + u32 val; + + pr_debug("%s %d %d %d\n", __func__, word, bit , size); + + val = readl(&base->word[word].data[i]); + val &= ~(mask << ofs); + val |= v << ofs; + writel(val, &base->word[word].data[i]); + + if ((bit + size - 1) / 32 > i) { + val = readl(&base->word[word].data[i + 1]); + val &= ~(mask >> (ofs ? (32 - ofs) : 0)); + val |= v >> (ofs ? (32 - ofs) : 0); + writel(val, &base->word[word].data[i + 1]); + } +} + static inline u32 reg_read(struct ipu_fb_info *fbi, unsigned long reg) { u32 val; @@ -421,13 +405,13 @@ * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. * @return: 0 on success or negative error code on failure. */ -static int sdc_init_panel(struct fb_info *info, enum pixel_fmt pixel_fmt) +static int sdc_init_panel(struct fb_info *info, enum disp_data_mapping fmt) { struct ipu_fb_info *fbi = info->priv; struct fb_videomode *mode = info->mode; u32 reg, old_conf, div; enum ipu_panel panel = IPU_PANEL_TFT; - unsigned long pixel_clk; + unsigned long pixel_clk, rate; /* Init panel size and blanking periods */ reg = ((mode->hsync_len - 1) << 26) | @@ -484,7 +468,12 @@ * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz */ pixel_clk = PICOS2KHZ(mode->pixclock) * 1000UL; - div = clk_get_rate(fbi->clk) * 16 / pixel_clk; + rate = clk_get_rate(fbi->clk); + + if (fbi->disable_fractional_divider) + div = DIV_ROUND_CLOSEST(rate, pixel_clk) * 16; + else + div = rate * 16 / pixel_clk; if (div < 0x40) { /* Divider less than 4 */ dev_dbg(&info->dev, @@ -493,7 +482,7 @@ } dev_dbg(&info->dev, "pixel clk = %lu, divider %u.%u\n", - pixel_clk, div >> 4, (div & 7) * 125); + pixel_clk, div >> 4, (div & 0xf) * (1000 / 16)); /* * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits @@ -502,69 +491,105 @@ */ reg_write(fbi, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); - reg_write(fbi, fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP); - reg_write(fbi, fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP); - reg_write(fbi, fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP); - reg_write(fbi, reg_read(fbi, DI_DISP_ACC_CC) | - ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC); + reg_write(fbi, di_mappings[fmt].b0, DI_DISP3_B0_MAP); + reg_write(fbi, di_mappings[fmt].b1, DI_DISP3_B1_MAP); + reg_write(fbi, di_mappings[fmt].b2, DI_DISP3_B2_MAP); + reg_write(fbi, 0, DI_DISP_ACC_CC); return 0; } -static void ipu_ch_param_set_size(union chan_param_mem *params, +int ipu_cpmem_set_format_rgb(struct ipu_ch_param *p, struct imx_ipu_fb_rgb *rgb) +{ + int bpp = 0, npb = 0, ro, go, bo, to; + + ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset; + go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset; + bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset; + to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset; + + ipu_ch_param_write_field(p, IPU_FIELD_WID0, rgb->red.length - 1); + ipu_ch_param_write_field(p, IPU_FIELD_OFS0, ro); + ipu_ch_param_write_field(p, IPU_FIELD_WID1, rgb->green.length - 1); + ipu_ch_param_write_field(p, IPU_FIELD_OFS1, go); + ipu_ch_param_write_field(p, IPU_FIELD_WID2, rgb->blue.length - 1); + ipu_ch_param_write_field(p, IPU_FIELD_OFS2, bo); + + if (rgb->transp.length) { + ipu_ch_param_write_field(p, IPU_FIELD_WID3, rgb->transp.length - 1); + ipu_ch_param_write_field(p, IPU_FIELD_OFS3, to); + } else { + ipu_ch_param_write_field(p, IPU_FIELD_WID3, 7); + ipu_ch_param_write_field(p, IPU_FIELD_OFS3, rgb->bits_per_pixel); + } + + switch (rgb->bits_per_pixel) { + case 32: + bpp = 0; + npb = 7; + break; + case 24: + bpp = 1; + npb = 7; + break; + case 16: + bpp = 2; + npb = 15; + break; + case 8: + bpp = 3; + npb = 31; + break; + default: + return -EINVAL; + } + + ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp); + ipu_ch_param_write_field(p, IPU_FIELD_PFS, 4); + ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb); + ipu_ch_param_write_field(p, IPU_FIELD_SAT, 2); + + return 0; +} + +static void ipu_ch_param_set_size(struct ipu_ch_param *p, u32 pixel_fmt, uint16_t width, uint16_t height, uint16_t stride) { - params->pp.fw = width - 1; - params->pp.fh_l = height - 1; - params->pp.fh_h = (height - 1) >> 8; - params->pp.sl = stride - 1; + ipu_ch_param_write_field(p, IPU_FIELD_FW, width - 1); + ipu_ch_param_write_field(p, IPU_FIELD_FH_L, height - 1); + ipu_ch_param_write_field(p, IPU_FIELD_FH_H, (height - 1) >> 8); + ipu_ch_param_write_field(p, IPU_FIELD_SL, stride - 1); /* See above, for further formats see the Linux driver */ switch (pixel_fmt) { case IPU_PIX_FMT_RGB565: - params->ip.bpp = 2; - params->ip.pfs = 4; - params->ip.npb = 7; - params->ip.sat = 2; /* SAT = 32-bit access */ - params->ip.ofs0 = 0; /* Red bit offset */ - params->ip.ofs1 = 5; /* Green bit offset */ - params->ip.ofs2 = 11; /* Blue bit offset */ - params->ip.ofs3 = 16; /* Alpha bit offset */ - params->ip.wid0 = 4; /* Red bit width - 1 */ - params->ip.wid1 = 5; /* Green bit width - 1 */ - params->ip.wid2 = 4; /* Blue bit width - 1 */ + ipu_cpmem_set_format_rgb(p, &def_rgb_16); break; case IPU_PIX_FMT_RGB24: - params->ip.bpp = 1; /* 24 BPP & RGB PFS */ - params->ip.pfs = 4; - params->ip.npb = 7; - params->ip.sat = 2; /* SAT = 32-bit access */ - params->ip.ofs0 = 16; /* Red bit offset */ - params->ip.ofs1 = 8; /* Green bit offset */ - params->ip.ofs2 = 0; /* Blue bit offset */ - params->ip.ofs3 = 24; /* Alpha bit offset */ - params->ip.wid0 = 7; /* Red bit width - 1 */ - params->ip.wid1 = 7; /* Green bit width - 1 */ - params->ip.wid2 = 7; /* Blue bit width - 1 */ + ipu_cpmem_set_format_rgb(p, &def_rgb_24); + break; + case IPU_PIX_FMT_RGB32: + ipu_cpmem_set_format_rgb(p, &def_rgb_32); break; default: break; } - params->pp.nsb = 1; + ipu_ch_param_write_field(p, IPU_FIELD_NSB, 1); } -static void ipu_ch_param_set_buffer(union chan_param_mem *params, - void *buf0, void *buf1) +static void ipu_ch_param_set_buffer(struct ipu_ch_param *p, void *buf0, void *buf1) { - params->pp.eba0 = (u32)buf0; - params->pp.eba1 = (u32)buf1; + ipu_ch_param_write_field(p, IPU_FIELD_EBA0, (u32)buf0); + ipu_ch_param_write_field(p, IPU_FIELD_EBA1, (u32)buf1); } static void ipu_write_param_mem(struct ipu_fb_info *fbi, u32 addr, - u32 *data, u32 num_words) + struct ipu_ch_param *p, u32 num_words) { + u32 *data = (void *)p; + for (; num_words > 0; num_words--) { reg_write(fbi, addr, IPU_IMA_ADDR); reg_write(fbi, *data++, IPU_IMA_DATA); @@ -581,6 +606,10 @@ switch (bpp) { case 16: return IPU_PIX_FMT_RGB565; + case 24: + return IPU_PIX_FMT_RGB24; + case 32: + return IPU_PIX_FMT_RGB32; default: return 0; } @@ -595,7 +624,7 @@ static void ipu_init_channel_buffer(struct ipu_fb_info *fbi, enum ipu_channel channel, void *fbmem) { - union chan_param_mem params = {}; + struct ipu_ch_param p = {}; u32 reg; u32 stride_bytes; @@ -603,23 +632,12 @@ stride_bytes = (stride_bytes + 3) & ~3; /* Build parameter memory data for DMA channel */ - ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(fbi->info.bits_per_pixel), + ipu_ch_param_set_size(&p, bpp_to_pixfmt(fbi->info.bits_per_pixel), fbi->info.xres, fbi->info.yres, stride_bytes); - ipu_ch_param_set_buffer(¶ms, fbmem, NULL); - params.pp.bam = 0; - /* Some channels (rotation) have restriction on burst length */ - switch (channel) { - case IDMAC_SDC_0: - case IDMAC_SDC_1: - /* In original code only IPU_PIX_FMT_RGB565 was setting burst */ - params.pp.npb = 16 - 1; - break; - default: - break; - } + ipu_ch_param_set_buffer(&p, fbmem, NULL); - ipu_write_param_mem(fbi, dma_param_addr(channel), (u32 *)¶ms, 10); + ipu_write_param_mem(fbi, dma_param_addr(channel), &p, 10); /* Disable double-buffering */ reg = reg_read(fbi, IPU_CHA_DB_MODE_SEL); @@ -765,11 +783,6 @@ reg_write(fbi, 0x00100010L, DI_HSP_CLK_PER); /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ - /* mx3fb.c::sdc_set_brightness() */ - - /* This might be board-specific */ - reg_write(fbi, 0x03000000UL | 255 << 16, SDC_PWM_CTRL); - /* mx3fb.c::sdc_set_global_alpha() */ /* Use global - not per-pixel - Alpha-blending */ @@ -786,7 +799,7 @@ ~(SDC_COM_KEY_COLOR_G); reg_write(fbi, reg, SDC_COM_CONF); - sdc_init_panel(info, IPU_PIX_FMT_RGB666); + sdc_init_panel(info, fbi->disp_data_fmt); reg_write(fbi, (mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS); @@ -876,7 +889,7 @@ struct fb_videomode *mode = overlay->mode; int reg; - sdc_init_panel(overlay, IPU_PIX_FMT_RGB666); + sdc_init_panel(overlay, fbi->disp_data_fmt); reg_write(fbi, (mode->left_margin << 16) | mode->upper_margin, SDC_FG_POS); @@ -952,6 +965,8 @@ if (!overlay->screen_base) return -ENOMEM; + overlay->screen_size = pdata->framebuffer_ovl_size; + sdc_enable_channel(fbi, overlay->screen_base, IDMAC_SDC_1); ret = register_framebuffer(&fbi->overlay); @@ -988,6 +1003,8 @@ fbi->regs = dev_request_mem_region(dev, 0); fbi->dev = dev; fbi->enable = pdata->enable; + fbi->disp_data_fmt = pdata->disp_data_fmt; + fbi->disable_fractional_divider = pdata->disable_fractional_divider; info->priv = fbi; info->fbops = &imxfb_ops; info->num_modes = pdata->num_modes; @@ -997,14 +1014,21 @@ dev_info(dev, "i.MX Framebuffer driver\n"); + fbi->info.screen_size = pdata->framebuffer_size; + if (!fbi->info.screen_size) + fbi->info.screen_size = info->xres * info->yres * + (info->bits_per_pixel >> 3); /* * Use a given frambuffer or reserve some * memory for screen usage */ fbi->info.screen_base = pdata->framebuffer; - if (fbi->info.screen_base == NULL) { - fbi->info.screen_base = malloc(info->xres * info->yres * - (info->bits_per_pixel >> 3)); + if (fbi->info.screen_base) { + remap_range(fbi->info.screen_base, + fbi->info.screen_size, + mmu_get_pte_uncached_flags()); + } else { + fbi->info.screen_base = dma_alloc_coherent(fbi->info.screen_size); if (!fbi->info.screen_base) return -ENOMEM; } diff --git a/drivers/video/simplefb.c b/drivers/video/simplefb.c index 834704b..3572629 100644 --- a/drivers/video/simplefb.c +++ b/drivers/video/simplefb.c @@ -37,7 +37,15 @@ .green = { .length = 6, .offset = 5 }, .blue = { .length = 5, .offset = 0 }, .transp = { .length = 0, .offset = 0 }, + }, { + .format = "a8r8g8b8", + .bpp = 32, + .red = { .length = 8, .offset = 16 }, + .green = { .length = 8, .offset = 8 }, + .blue = { .length = 8, .offset = 0 }, + .transp = { .length = 8, .offset = 24 }, }, + }; static bool simplefb_bitfield_cmp(const struct fb_bitfield *a, @@ -126,6 +134,9 @@ if (ret < 0) return ret; + of_add_reserve_entry((u32)fbi->screen_base, + (u32)fbi->screen_base + fbi->screen_size); + return of_set_property(node, "status", okay, strlen(okay) + 1, 1); } diff --git a/include/fb.h b/include/fb.h index 98d5a03..22fa9b1 100644 --- a/include/fb.h +++ b/include/fb.h @@ -86,6 +86,7 @@ struct device_d dev; /* This is this fb device */ void *screen_base; + unsigned long screen_size; void *priv;