diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c
index 775c818..117d834 100644
--- a/arch/arm/boards/animeo_ip/init.c
+++ b/arch/arm/boards/animeo_ip/init.c
@@ -327,7 +327,7 @@
 	 * so linux can detect that we only enable the uart2
 	 * and use it for decompress
 	 */
-	animeo_ip_shutdown_uart(IOMEM(AT91_DBGU + AT91_BASE_SYS));
+	animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_DBGU));
 	animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US0));
 	animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US1));
 }
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index a110ee3..b4d7cb1 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -253,7 +253,7 @@
 	at91_set_A_periph(AT91_PIN_PA30, 1);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PA31, 0);		/* DTXD */
 
-	return AT91_BASE_SYS + AT91_DBGU;
+	return AT91RM9200_BASE_DBGU;
 }
 
 resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index c5323e2..9b8654f 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -132,8 +132,8 @@
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= AT91_BASE_SYS + AT91_ECC,
-		.end	= AT91_BASE_SYS + AT91_ECC + 512 - 1,
+		.start	= AT91SAM9260_BASE_ECC,
+		.end	= AT91SAM9260_BASE_ECC + 512 - 1,
 		.flags	= IORESOURCE_MEM,
 	}
 };
@@ -266,7 +266,7 @@
 	at91_set_A_periph(AT91_PIN_PB14, 1);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PB15, 0);		/* DTXD */
 
-	return AT91_BASE_SYS + AT91_DBGU;
+	return AT91SAM9260_BASE_DBGU;
 }
 
 resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 9b7703e..3b869f9 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -270,7 +270,7 @@
 	at91_set_A_periph(AT91_PIN_PA9, 1);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PA10, 0);		/* DTXD */
 
-	return AT91_BASE_SYS + AT91_DBGU;
+	return AT91SAM9261_BASE_DBGU;
 }
 
 resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index ab3968e..877acc0 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -126,8 +126,8 @@
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= AT91_BASE_SYS + AT91_ECC0,
-		.end	= AT91_BASE_SYS + AT91_ECC0 + 512 - 1,
+		.start	= AT91SAM9263_BASE_ECC0,
+		.end	= AT91SAM9263_BASE_ECC0 + 512 - 1,
 		.flags	= IORESOURCE_MEM,
 	}
 };
@@ -301,7 +301,7 @@
 	at91_set_A_periph(AT91_PIN_PC30, 1);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PC31, 0);		/* DTXD */
 
-	return AT91_BASE_SYS + AT91_DBGU;
+	return AT91SAM9263_BASE_DBGU;
 }
 
 resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index b44273a..ae4bd50 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -128,8 +128,8 @@
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= AT91_BASE_SYS + AT91_ECC,
-		.end	= AT91_BASE_SYS + AT91_ECC + 512 - 1,
+		.start	= AT91SAM9G45_BASE_ECC,
+		.end	= AT91SAM9G45_BASE_ECC + 512 - 1,
 		.flags	= IORESOURCE_MEM,
 	}
 };
@@ -218,7 +218,7 @@
 	at91_set_A_periph(AT91_PIN_PB12, 1);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PB13, 0);		/* DTXD */
 
-	return AT91_BASE_SYS + AT91_DBGU;
+	return AT91SAM9G45_BASE_DBGU;
 }
 
 resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index e38fc77..3c606d5 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -133,13 +133,13 @@
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= AT91_BASE_SYS + AT91_PMECC,
-		.end	= AT91_BASE_SYS + AT91_PMECC + 0x600 - 1,
+		.start	= AT91SAM9N12_BASE_PMECC,
+		.end	= AT91SAM9N12_BASE_PMECC + 0x600 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[2] = {
-		.start	= AT91_BASE_SYS + AT91_PMERRLOC,
-		.end	= AT91_BASE_SYS + AT91_PMERRLOC + 0x200 - 1,
+		.start	= AT91SAM9N12_BASE_PMERRLOC,
+		.end	= AT91SAM9N12_BASE_PMERRLOC + 0x200 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[3] = {
@@ -373,7 +373,7 @@
 	at91_set_A_periph(AT91_PIN_PA9, 1);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PA10, 0);		/* DTXD */
 
-	return AT91_BASE_SYS + AT91_DBGU;
+	return AT91SAM9N12_BASE_DBGU;
 }
 
 resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index e21bd59..b8035c1 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -225,13 +225,13 @@
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= AT91_BASE_SYS + AT91_PMECC,
-		.end	= AT91_BASE_SYS + AT91_PMECC + 0x600 - 1,
+		.start	= AT91SAM9X5_BASE_PMECC,
+		.end	= AT91SAM9X5_BASE_PMECC + 0x600 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[2] = {
-		.start	= AT91_BASE_SYS + AT91_PMERRLOC,
-		.end	= AT91_BASE_SYS + AT91_PMERRLOC + 0x200 - 1,
+		.start	= AT91SAM9X5_BASE_PMERRLOC,
+		.end	= AT91SAM9X5_BASE_PMERRLOC + 0x200 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 	[3] = {
@@ -457,7 +457,7 @@
 	at91_set_A_periph(AT91_PIN_PA9, 1);		/* DRXD */
 	at91_set_A_periph(AT91_PIN_PA10, 0);		/* DTXD */
 
-	return AT91_BASE_SYS + AT91_DBGU;
+	return AT91SAM9X5_BASE_DBGU;
 }
 
 resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 3ea2501..5454496 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -90,7 +90,7 @@
  * System Peripherals
  */
 #define AT91SAM9X5_BASE_MATRIX		0xffffde00
-#define AT9SAM9X5_BASE1_PMECC		0xffffe000
+#define AT91SAM9X5_BASE_PMECC		0xffffe000
 #define AT91SAM9X5_BASE_PMERRLOC	0xffffe600
 #define AT91SAM9X5_BASE_DDRSDRC0	0xffffe800
 #define AT91SAM9X5_BASE_SMC		0xffffea00