diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..637da79 --- /dev/null +++ b/.gitignore @@ -0,0 +1,8 @@ +board/myna-player-odyssey/utilities/certs.txt +board/myna-player-odyssey/utilities/genimage.cfg +board/myna-player-odyssey/utilities/machine-id +pki +easy-rsa +board/myna-player-odyssey/rootfs_overlay/etc/rauc/keyring.pem +output/* +dl/* diff --git a/Config.in b/Config.in new file mode 100644 index 0000000..2aff75d --- /dev/null +++ b/Config.in @@ -0,0 +1,3 @@ +# packages + +source "$BR2_EXTERNAL_MynaPlayer_PATH/packages/Config.in" diff --git a/board/myna-player-odyssey/configs/barebox.config b/board/myna-player-odyssey/configs/barebox.config new file mode 100644 index 0000000..246e6e8 --- /dev/null +++ b/board/myna-player-odyssey/configs/barebox.config @@ -0,0 +1,141 @@ +CONFIG_ARCH_STM32MP=y +CONFIG_MACH_SEEED_ODYSSEY=y +CONFIG_THUMB2_BAREBOX=y +CONFIG_ARM_BOARD_APPEND_ATAG=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_MMU=y +CONFIG_MALLOC_SIZE=0x0 +CONFIG_MALLOC_TLSF=y +CONFIG_KALLSYMS=y +CONFIG_RELOCATABLE=y +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_BOOTM_VERBOSE=y +CONFIG_BOOTM_INITRD=y +CONFIG_BOOTM_OFTREE=y +CONFIG_BOOTM_OFTREE_UIMAGE=y +CONFIG_BLSPEC=y +CONFIG_CONSOLE_ACTIVATE_NONE=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PBL_CONSOLE=y +CONFIG_PARTITION_DISK_EFI=y +# CONFIG_PARTITION_DISK_EFI_GPT_NO_FORCE is not set +# CONFIG_PARTITION_DISK_EFI_GPT_COMPARE is not set +CONFIG_DEFAULT_COMPRESSION_XZ=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_STATE=y +CONFIG_BOOTCHOOSER=y +CONFIG_RESET_SOURCE=y +CONFIG_DEFAULT_LOGLEVEL=3 +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_ARM_MMUINFO=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MMC_EXTCSD=y +CONFIG_CMD_POLLER=y +# CONFIG_CMD_BOOTU is not set +CONFIG_CMD_GO=y +CONFIG_CMD_RESET=y +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_DEFAULTENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_FILETYPE=y +CONFIG_CMD_LN=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_LET=y +CONFIG_CMD_MSLEEP=y +CONFIG_CMD_READF=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_MENUTREE=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MM=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DETECT=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_LED=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_SMC=y +CONFIG_CMD_WD=y +CONFIG_CMD_BAREBOX_UPDATE=y +CONFIG_CMD_OF_DIFF=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_STATE=y +CONFIG_CMD_BOOTCHOOSER=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_SERIAL_STM32=y +# CONFIG_SPI is not set +CONFIG_I2C=y +CONFIG_I2C_STM32=y +CONFIG_MCI=y +CONFIG_MCI_MMC_BOOT_PARTITIONS=y +CONFIG_MCI_STM32_SDMMC2=y +CONFIG_MFD_STPMIC1=y +CONFIG_MFD_STM32_TIMERS=y +CONFIG_STATE_DRV=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_LED_PWM=y +CONFIG_LED_GPIO_OF=y +CONFIG_LED_TRIGGERS=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_INPUT_SPECIALKEYS=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_POLLER=y +CONFIG_STM32_IWDG_WATCHDOG=y +CONFIG_STPMIC1_WATCHDOG=y +CONFIG_PWM=y +CONFIG_PWM_STM32=y +CONFIG_HWRNG=y +CONFIG_HWRNG_STM32=y +CONFIG_NVMEM=y +CONFIG_STM32_BSEC=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y +CONFIG_REGULATOR_STM32_PWR=y +CONFIG_REGULATOR_STPMIC1=y +CONFIG_REMOTEPROC=y +CONFIG_STM32_REMOTEPROC=y +CONFIG_RESET_STM32=y +CONFIG_GENERIC_PHY=y +CONFIG_PHY_STM32_USBPHYC=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y +CONFIG_FS_SQUASHFS=y +CONFIG_FS_RATP=y +CONFIG_ZLIB=y +CONFIG_XZ_DECOMPRESS=y +CONFIG_RATP=y +CONFIG_CRC8=y +CONFIG_DIGEST_HMAC_GENERIC=y +CONFIG_CRYPTO_KEYSTORE=y diff --git a/board/myna-player-odyssey/configs/busybox.config b/board/myna-player-odyssey/configs/busybox.config new file mode 100644 index 0000000..d8f6d6d --- /dev/null +++ b/board/myna-player-odyssey/configs/busybox.config @@ -0,0 +1,1162 @@ +# +# Busybox version: 1.31.1 +# Thu Jun 18 13:45:37 2020 +# +CONFIG_HAVE_DOT_CONFIG=y + +# +# Settings +# +# CONFIG_DESKTOP is not set +# CONFIG_EXTRA_COMPAT is not set +# CONFIG_FEDORA_COMPAT is not set +# CONFIG_INCLUDE_SUSv2 is not set +CONFIG_LONG_OPTS=y +# CONFIG_SHOW_USAGE is not set +# CONFIG_FEATURE_VERBOSE_USAGE is not set +# CONFIG_FEATURE_COMPRESS_USAGE is not set +CONFIG_LFS=y +# CONFIG_PAM is not set +CONFIG_FEATURE_DEVPTS=y +CONFIG_FEATURE_UTMP=y +CONFIG_FEATURE_WTMP=y +# CONFIG_FEATURE_PIDFILE is not set +CONFIG_PID_FILE_PATH="" +CONFIG_BUSYBOX=y +CONFIG_FEATURE_SHOW_SCRIPT=y +CONFIG_FEATURE_INSTALLER=y +# CONFIG_INSTALL_NO_USR is not set +CONFIG_FEATURE_SUID=y +# CONFIG_FEATURE_SUID_CONFIG is not set +# CONFIG_FEATURE_SUID_CONFIG_QUIET is not set +# CONFIG_FEATURE_PREFER_APPLETS is not set +CONFIG_BUSYBOX_EXEC_PATH="/proc/self/exe" +# CONFIG_SELINUX is not set +# CONFIG_FEATURE_CLEAN_UP is not set +CONFIG_FEATURE_SYSLOG_INFO=y +CONFIG_FEATURE_SYSLOG=y +CONFIG_PLATFORM_LINUX=y + +# +# Build Options +# +# CONFIG_STATIC is not set +# CONFIG_PIE is not set +# CONFIG_NOMMU is not set +# CONFIG_BUILD_LIBBUSYBOX is not set +# CONFIG_FEATURE_LIBBUSYBOX_STATIC is not set +# CONFIG_FEATURE_INDIVIDUAL is not set +# CONFIG_FEATURE_SHARED_BUSYBOX is not set +CONFIG_CROSS_COMPILER_PREFIX="" +CONFIG_SYSROOT="" +CONFIG_EXTRA_CFLAGS="" +CONFIG_EXTRA_LDFLAGS="" +CONFIG_EXTRA_LDLIBS="" +# CONFIG_USE_PORTABLE_CODE is not set +CONFIG_STACK_OPTIMIZATION_386=y + +# +# Installation Options ("make install" behavior) +# +CONFIG_INSTALL_APPLET_SYMLINKS=y +# CONFIG_INSTALL_APPLET_HARDLINKS is not set +# CONFIG_INSTALL_APPLET_SCRIPT_WRAPPERS is not set +# CONFIG_INSTALL_APPLET_DONT is not set +# CONFIG_INSTALL_SH_APPLET_SYMLINK is not set +# CONFIG_INSTALL_SH_APPLET_HARDLINK is not set +# CONFIG_INSTALL_SH_APPLET_SCRIPT_WRAPPER is not set +CONFIG_PREFIX="./_install" + +# +# Debugging Options +# +# CONFIG_DEBUG is not set +# CONFIG_DEBUG_PESSIMIZE is not set +# CONFIG_DEBUG_SANITIZE is not set +# CONFIG_UNIT_TEST is not set +# CONFIG_WERROR is not set +CONFIG_NO_DEBUG_LIB=y +# CONFIG_DMALLOC is not set +# CONFIG_EFENCE is not set + +# +# Library Tuning +# +# CONFIG_FEATURE_USE_BSS_TAIL is not set +CONFIG_FLOAT_DURATION=y +CONFIG_FEATURE_RTMINMAX=y +CONFIG_FEATURE_RTMINMAX_USE_LIBC_DEFINITIONS=y +CONFIG_FEATURE_BUFFERS_USE_MALLOC=y +# CONFIG_FEATURE_BUFFERS_GO_ON_STACK is not set +# CONFIG_FEATURE_BUFFERS_GO_IN_BSS is not set +CONFIG_PASSWORD_MINLEN=6 +CONFIG_MD5_SMALL=1 +CONFIG_SHA3_SMALL=1 +# CONFIG_FEATURE_FAST_TOP is not set +# CONFIG_FEATURE_ETC_NETWORKS is not set +# CONFIG_FEATURE_ETC_SERVICES is not set +# CONFIG_FEATURE_EDITING is not set +CONFIG_FEATURE_EDITING_MAX_LEN=0 +# CONFIG_FEATURE_EDITING_VI is not set +CONFIG_FEATURE_EDITING_HISTORY=0 +# CONFIG_FEATURE_EDITING_SAVEHISTORY is not set +# CONFIG_FEATURE_EDITING_SAVE_ON_EXIT is not set +# CONFIG_FEATURE_REVERSE_SEARCH is not set +# CONFIG_FEATURE_TAB_COMPLETION is not set +# CONFIG_FEATURE_USERNAME_COMPLETION is not set +# CONFIG_FEATURE_EDITING_FANCY_PROMPT is not set +# CONFIG_FEATURE_EDITING_WINCH is not set +# CONFIG_FEATURE_EDITING_ASK_TERMINAL is not set +# CONFIG_LOCALE_SUPPORT is not set +# CONFIG_UNICODE_SUPPORT is not set +# CONFIG_UNICODE_USING_LOCALE is not set +# CONFIG_FEATURE_CHECK_UNICODE_IN_ENV is not set +CONFIG_SUBST_WCHAR=0 +CONFIG_LAST_SUPPORTED_WCHAR=0 +# CONFIG_UNICODE_COMBINING_WCHARS is not set +# CONFIG_UNICODE_WIDE_WCHARS is not set +# CONFIG_UNICODE_BIDI_SUPPORT is not set +# CONFIG_UNICODE_NEUTRAL_TABLE is not set +# CONFIG_UNICODE_PRESERVE_BROKEN is not set +CONFIG_FEATURE_NON_POSIX_CP=y +# CONFIG_FEATURE_VERBOSE_CP_MESSAGE is not set +CONFIG_FEATURE_USE_SENDFILE=y +CONFIG_FEATURE_COPYBUF_KB=4 +CONFIG_FEATURE_SKIP_ROOTFS=y +CONFIG_MONOTONIC_SYSCALL=y +CONFIG_IOCTL_HEX2STR_ERROR=y +CONFIG_FEATURE_HWIB=y + +# +# Applets +# + +# +# Archival Utilities +# +# CONFIG_FEATURE_SEAMLESS_XZ is not set +# CONFIG_FEATURE_SEAMLESS_LZMA is not set +# CONFIG_FEATURE_SEAMLESS_BZ2 is not set +# CONFIG_FEATURE_SEAMLESS_GZ is not set +# CONFIG_FEATURE_SEAMLESS_Z is not set +# CONFIG_AR is not set +# CONFIG_FEATURE_AR_LONG_FILENAMES is not set +# CONFIG_FEATURE_AR_CREATE is not set +# CONFIG_UNCOMPRESS is not set +# CONFIG_GUNZIP is not set +# CONFIG_ZCAT is not set +# CONFIG_FEATURE_GUNZIP_LONG_OPTIONS is not set +# CONFIG_BUNZIP2 is not set +# CONFIG_BZCAT is not set +# CONFIG_UNLZMA is not set +# CONFIG_LZCAT is not set +# CONFIG_LZMA is not set +# CONFIG_UNXZ is not set +# CONFIG_XZCAT is not set +# CONFIG_XZ is not set +# CONFIG_BZIP2 is not set +CONFIG_BZIP2_SMALL=0 +# CONFIG_FEATURE_BZIP2_DECOMPRESS is not set +# CONFIG_CPIO is not set +# CONFIG_FEATURE_CPIO_O is not set +# CONFIG_FEATURE_CPIO_P is not set +# CONFIG_DPKG is not set +# CONFIG_DPKG_DEB is not set +# CONFIG_GZIP is not set +# CONFIG_FEATURE_GZIP_LONG_OPTIONS is not set +CONFIG_GZIP_FAST=0 +# CONFIG_FEATURE_GZIP_LEVELS is not set +# CONFIG_FEATURE_GZIP_DECOMPRESS is not set +# CONFIG_LZOP is not set +# CONFIG_UNLZOP is not set +# CONFIG_LZOPCAT is not set +# CONFIG_LZOP_COMPR_HIGH is not set +# CONFIG_RPM is not set +# CONFIG_RPM2CPIO is not set +# CONFIG_TAR is not set +# CONFIG_FEATURE_TAR_LONG_OPTIONS is not set +# CONFIG_FEATURE_TAR_CREATE is not set +# CONFIG_FEATURE_TAR_AUTODETECT is not set +# CONFIG_FEATURE_TAR_FROM is not set +# CONFIG_FEATURE_TAR_OLDGNU_COMPATIBILITY is not set +# CONFIG_FEATURE_TAR_OLDSUN_COMPATIBILITY is not set +# CONFIG_FEATURE_TAR_GNU_EXTENSIONS is not set +# CONFIG_FEATURE_TAR_TO_COMMAND is not set +# CONFIG_FEATURE_TAR_UNAME_GNAME is not set +# CONFIG_FEATURE_TAR_NOPRESERVE_TIME is not set +# CONFIG_FEATURE_TAR_SELINUX is not set +# CONFIG_UNZIP is not set +# CONFIG_FEATURE_UNZIP_CDF is not set +# CONFIG_FEATURE_UNZIP_BZIP2 is not set +# CONFIG_FEATURE_UNZIP_LZMA is not set +# CONFIG_FEATURE_UNZIP_XZ is not set +# CONFIG_FEATURE_LZMA_FAST is not set + +# +# Coreutils +# +CONFIG_BASENAME=y +CONFIG_CAT=y +CONFIG_FEATURE_CATN=y +CONFIG_FEATURE_CATV=y +CONFIG_CHGRP=y +CONFIG_CHMOD=y +CONFIG_CHOWN=y +# CONFIG_FEATURE_CHOWN_LONG_OPTIONS is not set +CONFIG_CHROOT=y +# CONFIG_CKSUM is not set +# CONFIG_COMM is not set +CONFIG_CP=y +# CONFIG_FEATURE_CP_LONG_OPTIONS is not set +# CONFIG_FEATURE_CP_REFLINK is not set +CONFIG_CUT=y +# CONFIG_DATE is not set +# CONFIG_FEATURE_DATE_ISOFMT is not set +# CONFIG_FEATURE_DATE_NANO is not set +# CONFIG_FEATURE_DATE_COMPAT is not set +# CONFIG_DD is not set +# CONFIG_FEATURE_DD_SIGNAL_HANDLING is not set +# CONFIG_FEATURE_DD_THIRD_STATUS_LINE is not set +# CONFIG_FEATURE_DD_IBS_OBS is not set +# CONFIG_FEATURE_DD_STATUS is not set +# CONFIG_DF is not set +# CONFIG_FEATURE_DF_FANCY is not set +CONFIG_DIRNAME=y +# CONFIG_DOS2UNIX is not set +# CONFIG_UNIX2DOS is not set +# CONFIG_DU is not set +# CONFIG_FEATURE_DU_DEFAULT_BLOCKSIZE_1K is not set +CONFIG_ECHO=y +CONFIG_FEATURE_FANCY_ECHO=y +CONFIG_ENV=y +# CONFIG_EXPAND is not set +# CONFIG_UNEXPAND is not set +CONFIG_EXPR=y +CONFIG_EXPR_MATH_SUPPORT_64=y +# CONFIG_FACTOR is not set +CONFIG_FALSE=y +# CONFIG_FOLD is not set +CONFIG_HEAD=y +CONFIG_FEATURE_FANCY_HEAD=y +CONFIG_HOSTID=y +CONFIG_ID=y +# CONFIG_GROUPS is not set +CONFIG_INSTALL=y +CONFIG_FEATURE_INSTALL_LONG_OPTIONS=y +CONFIG_LINK=y +CONFIG_LN=y +# CONFIG_LOGNAME is not set +# CONFIG_LS is not set +# CONFIG_FEATURE_LS_FILETYPES is not set +# CONFIG_FEATURE_LS_FOLLOWLINKS is not set +# CONFIG_FEATURE_LS_RECURSIVE is not set +# CONFIG_FEATURE_LS_WIDTH is not set +# CONFIG_FEATURE_LS_SORTFILES is not set +# CONFIG_FEATURE_LS_TIMESTAMPS is not set +# CONFIG_FEATURE_LS_USERNAME is not set +# CONFIG_FEATURE_LS_COLOR is not set +# CONFIG_FEATURE_LS_COLOR_IS_DEFAULT is not set +# CONFIG_MD5SUM is not set +# CONFIG_SHA1SUM is not set +# CONFIG_SHA256SUM is not set +# CONFIG_SHA512SUM is not set +# CONFIG_SHA3SUM is not set +# CONFIG_FEATURE_MD5_SHA1_SUM_CHECK is not set +CONFIG_MKDIR=y +CONFIG_MKFIFO=y +CONFIG_MKNOD=y +CONFIG_MKTEMP=y +CONFIG_MV=y +CONFIG_NICE=y +# CONFIG_NL is not set +# CONFIG_NOHUP is not set +CONFIG_NPROC=y +# CONFIG_OD is not set +CONFIG_PASTE=y +# CONFIG_PRINTENV is not set +CONFIG_PRINTF=y +# CONFIG_PWD is not set +CONFIG_READLINK=y +CONFIG_FEATURE_READLINK_FOLLOW=y +CONFIG_REALPATH=y +CONFIG_RM=y +CONFIG_RMDIR=y +CONFIG_SEQ=y +# CONFIG_SHRED is not set +# CONFIG_SHUF is not set +CONFIG_SLEEP=y +CONFIG_FEATURE_FANCY_SLEEP=y +CONFIG_SORT=y +CONFIG_FEATURE_SORT_BIG=y +# CONFIG_FEATURE_SORT_OPTIMIZE_MEMORY is not set +# CONFIG_SPLIT is not set +# CONFIG_FEATURE_SPLIT_FANCY is not set +# CONFIG_STAT is not set +# CONFIG_FEATURE_STAT_FORMAT is not set +# CONFIG_FEATURE_STAT_FILESYSTEM is not set +# CONFIG_STTY is not set +# CONFIG_SUM is not set +CONFIG_SYNC=y +# CONFIG_FEATURE_SYNC_FANCY is not set +# CONFIG_FSYNC is not set +# CONFIG_TAC is not set +CONFIG_TAIL=y +CONFIG_FEATURE_FANCY_TAIL=y +CONFIG_TEE=y +CONFIG_FEATURE_TEE_USE_BLOCK_IO=y +CONFIG_TEST=y +CONFIG_TEST1=y +CONFIG_TEST2=y +CONFIG_FEATURE_TEST_64=y +# CONFIG_TIMEOUT is not set +CONFIG_TOUCH=y +# CONFIG_FEATURE_TOUCH_NODEREF is not set +CONFIG_FEATURE_TOUCH_SUSV3=y +CONFIG_TR=y +CONFIG_FEATURE_TR_CLASSES=y +CONFIG_FEATURE_TR_EQUIV=y +CONFIG_TRUE=y +CONFIG_TRUNCATE=y +CONFIG_TTY=y +CONFIG_UNAME=y +CONFIG_UNAME_OSNAME="GNU/Linux" +CONFIG_BB_ARCH=y +CONFIG_UNIQ=y +CONFIG_UNLINK=y +CONFIG_USLEEP=y +CONFIG_UUDECODE=y +CONFIG_BASE64=y +CONFIG_UUENCODE=y +CONFIG_WC=y +# CONFIG_FEATURE_WC_LARGE is not set +CONFIG_WHOAMI=y +CONFIG_WHO=y +CONFIG_W=y +# CONFIG_USERS is not set +CONFIG_YES=y + +# +# Common options +# +CONFIG_FEATURE_VERBOSE=y + +# +# Common options for cp and mv +# +CONFIG_FEATURE_PRESERVE_HARDLINKS=y +# CONFIG_FEATURE_HUMAN_READABLE is not set + +# +# Console Utilities +# +# CONFIG_CHVT is not set +CONFIG_CLEAR=y +# CONFIG_DEALLOCVT is not set +CONFIG_DUMPKMAP=y +# CONFIG_FGCONSOLE is not set +# CONFIG_KBD_MODE is not set +# CONFIG_LOADFONT is not set +# CONFIG_SETFONT is not set +# CONFIG_FEATURE_SETFONT_TEXTUAL_MAP is not set +CONFIG_DEFAULT_SETFONT_DIR="" +# CONFIG_FEATURE_LOADFONT_PSF2 is not set +# CONFIG_FEATURE_LOADFONT_RAW is not set +# CONFIG_LOADKMAP is not set +# CONFIG_OPENVT is not set +CONFIG_RESET=y +CONFIG_RESIZE=y +CONFIG_FEATURE_RESIZE_PRINT=y +CONFIG_SETCONSOLE=y +# CONFIG_FEATURE_SETCONSOLE_LONG_OPTIONS is not set +# CONFIG_SETKEYCODES is not set +# CONFIG_SETLOGCONS is not set +# CONFIG_SHOWKEY is not set + +# +# Debian Utilities +# +# CONFIG_PIPE_PROGRESS is not set +# CONFIG_RUN_PARTS is not set +# CONFIG_FEATURE_RUN_PARTS_LONG_OPTIONS is not set +# CONFIG_FEATURE_RUN_PARTS_FANCY is not set +# CONFIG_START_STOP_DAEMON is not set +# CONFIG_FEATURE_START_STOP_DAEMON_LONG_OPTIONS is not set +# CONFIG_FEATURE_START_STOP_DAEMON_FANCY is not set +CONFIG_WHICH=y + +# +# klibc-utils +# +# CONFIG_MINIPS is not set +# CONFIG_NUKE is not set +# CONFIG_RESUME is not set +# CONFIG_RUN_INIT is not set + +# +# Editors +# +# CONFIG_AWK is not set +# CONFIG_FEATURE_AWK_LIBM is not set +# CONFIG_FEATURE_AWK_GNU_EXTENSIONS is not set +# CONFIG_CMP is not set +# CONFIG_DIFF is not set +# CONFIG_FEATURE_DIFF_LONG_OPTIONS is not set +# CONFIG_FEATURE_DIFF_DIR is not set +# CONFIG_ED is not set +# CONFIG_PATCH is not set +# CONFIG_SED is not set +# CONFIG_VI is not set +CONFIG_FEATURE_VI_MAX_LEN=0 +# CONFIG_FEATURE_VI_8BIT is not set +# CONFIG_FEATURE_VI_COLON is not set +# CONFIG_FEATURE_VI_YANKMARK is not set +# CONFIG_FEATURE_VI_SEARCH is not set +# CONFIG_FEATURE_VI_REGEX_SEARCH is not set +# CONFIG_FEATURE_VI_USE_SIGNALS is not set +# CONFIG_FEATURE_VI_DOT_CMD is not set +# CONFIG_FEATURE_VI_READONLY is not set +# CONFIG_FEATURE_VI_SETOPTS is not set +# CONFIG_FEATURE_VI_SET is not set +# CONFIG_FEATURE_VI_WIN_RESIZE is not set +# CONFIG_FEATURE_VI_ASK_TERMINAL is not set +# CONFIG_FEATURE_VI_UNDO is not set +# CONFIG_FEATURE_VI_UNDO_QUEUE is not set +CONFIG_FEATURE_VI_UNDO_QUEUE_MAX=0 +# CONFIG_FEATURE_ALLOW_EXEC is not set + +# +# Finding Utilities +# +CONFIG_FIND=y +CONFIG_FEATURE_FIND_PRINT0=y +CONFIG_FEATURE_FIND_MTIME=y +CONFIG_FEATURE_FIND_MMIN=y +CONFIG_FEATURE_FIND_PERM=y +CONFIG_FEATURE_FIND_TYPE=y +CONFIG_FEATURE_FIND_EXECUTABLE=y +CONFIG_FEATURE_FIND_XDEV=y +CONFIG_FEATURE_FIND_MAXDEPTH=y +CONFIG_FEATURE_FIND_NEWER=y +# CONFIG_FEATURE_FIND_INUM is not set +CONFIG_FEATURE_FIND_EXEC=y +CONFIG_FEATURE_FIND_EXEC_PLUS=y +CONFIG_FEATURE_FIND_USER=y +CONFIG_FEATURE_FIND_GROUP=y +CONFIG_FEATURE_FIND_NOT=y +CONFIG_FEATURE_FIND_DEPTH=y +CONFIG_FEATURE_FIND_PAREN=y +CONFIG_FEATURE_FIND_SIZE=y +CONFIG_FEATURE_FIND_PRUNE=y +CONFIG_FEATURE_FIND_QUIT=y +# CONFIG_FEATURE_FIND_DELETE is not set +CONFIG_FEATURE_FIND_PATH=y +CONFIG_FEATURE_FIND_REGEX=y +# CONFIG_FEATURE_FIND_CONTEXT is not set +# CONFIG_FEATURE_FIND_LINKS is not set +CONFIG_GREP=y +CONFIG_EGREP=y +CONFIG_FGREP=y +CONFIG_FEATURE_GREP_CONTEXT=y +CONFIG_XARGS=y +# CONFIG_FEATURE_XARGS_SUPPORT_CONFIRMATION is not set +CONFIG_FEATURE_XARGS_SUPPORT_QUOTES=y +CONFIG_FEATURE_XARGS_SUPPORT_TERMOPT=y +CONFIG_FEATURE_XARGS_SUPPORT_ZERO_TERM=y +CONFIG_FEATURE_XARGS_SUPPORT_REPL_STR=y +CONFIG_FEATURE_XARGS_SUPPORT_PARALLEL=y +CONFIG_FEATURE_XARGS_SUPPORT_ARGS_FILE=y + +# +# Init Utilities +# +# CONFIG_BOOTCHARTD is not set +# CONFIG_FEATURE_BOOTCHARTD_BLOATED_HEADER is not set +# CONFIG_FEATURE_BOOTCHARTD_CONFIG_FILE is not set +CONFIG_HALT=y +CONFIG_POWEROFF=y +CONFIG_REBOOT=y +CONFIG_FEATURE_WAIT_FOR_INIT=y +# CONFIG_FEATURE_CALL_TELINIT is not set +CONFIG_TELINIT_PATH="" +CONFIG_INIT=y +CONFIG_LINUXRC=y +CONFIG_FEATURE_USE_INITTAB=y +CONFIG_FEATURE_KILL_REMOVED=y +CONFIG_FEATURE_KILL_DELAY=0 +CONFIG_FEATURE_INIT_SCTTY=y +CONFIG_FEATURE_INIT_SYSLOG=y +CONFIG_FEATURE_INIT_QUIET=y +# CONFIG_FEATURE_INIT_COREDUMPS is not set +CONFIG_INIT_TERMINAL_TYPE="linux" +CONFIG_FEATURE_INIT_MODIFY_CMDLINE=y + +# +# Login/Password Management Utilities +# +CONFIG_FEATURE_SHADOWPASSWDS=y +# CONFIG_USE_BB_PWD_GRP is not set +# CONFIG_USE_BB_SHADOW is not set +CONFIG_USE_BB_CRYPT=y +CONFIG_USE_BB_CRYPT_SHA=y +# CONFIG_ADDGROUP is not set +# CONFIG_FEATURE_ADDUSER_TO_GROUP is not set +# CONFIG_ADD_SHELL is not set +# CONFIG_REMOVE_SHELL is not set +# CONFIG_ADDUSER is not set +# CONFIG_FEATURE_CHECK_NAMES is not set +CONFIG_LAST_ID=0 +CONFIG_FIRST_SYSTEM_ID=0 +CONFIG_LAST_SYSTEM_ID=0 +# CONFIG_CHPASSWD is not set +CONFIG_FEATURE_DEFAULT_PASSWD_ALGO="" +# CONFIG_CRYPTPW is not set +CONFIG_MKPASSWD=y +# CONFIG_DELUSER is not set +# CONFIG_DELGROUP is not set +# CONFIG_FEATURE_DEL_USER_FROM_GROUP is not set +# CONFIG_GETTY is not set +# CONFIG_LOGIN is not set +# CONFIG_LOGIN_SESSION_AS_CHILD is not set +# CONFIG_LOGIN_SCRIPTS is not set +# CONFIG_FEATURE_NOLOGIN is not set +# CONFIG_FEATURE_SECURETTY is not set +# CONFIG_PASSWD is not set +# CONFIG_FEATURE_PASSWD_WEAK_CHECK is not set +# CONFIG_SU is not set +# CONFIG_FEATURE_SU_SYSLOG is not set +# CONFIG_FEATURE_SU_CHECKS_SHELLS is not set +# CONFIG_FEATURE_SU_BLANK_PW_NEEDS_SECURE_TTY is not set +# CONFIG_SULOGIN is not set +# CONFIG_VLOCK is not set + +# +# Linux Ext2 FS Progs +# +# CONFIG_CHATTR is not set +CONFIG_FSCK=y +# CONFIG_LSATTR is not set +# CONFIG_TUNE2FS is not set + +# +# Linux Module Utilities +# +# CONFIG_MODPROBE_SMALL is not set +# CONFIG_DEPMOD is not set +# CONFIG_INSMOD is not set +# CONFIG_LSMOD is not set +# CONFIG_FEATURE_LSMOD_PRETTY_2_6_OUTPUT is not set +# CONFIG_MODINFO is not set +# CONFIG_MODPROBE is not set +# CONFIG_FEATURE_MODPROBE_BLACKLIST is not set +# CONFIG_RMMOD is not set + +# +# Options common to multiple modutils +# +# CONFIG_FEATURE_CMDLINE_MODULE_OPTIONS is not set +# CONFIG_FEATURE_MODPROBE_SMALL_CHECK_ALREADY_LOADED is not set +# CONFIG_FEATURE_2_4_MODULES is not set +# CONFIG_FEATURE_INSMOD_VERSION_CHECKING is not set +# CONFIG_FEATURE_INSMOD_KSYMOOPS_SYMBOLS is not set +# CONFIG_FEATURE_INSMOD_LOADINKMEM is not set +# CONFIG_FEATURE_INSMOD_LOAD_MAP is not set +# CONFIG_FEATURE_INSMOD_LOAD_MAP_FULL is not set +# CONFIG_FEATURE_CHECK_TAINTED_MODULE is not set +# CONFIG_FEATURE_INSMOD_TRY_MMAP is not set +# CONFIG_FEATURE_MODUTILS_ALIAS is not set +# CONFIG_FEATURE_MODUTILS_SYMBOLS is not set +CONFIG_DEFAULT_MODULES_DIR="" +CONFIG_DEFAULT_DEPMOD_FILE="" + +# +# Linux System Utilities +# +# CONFIG_ACPID is not set +# CONFIG_FEATURE_ACPID_COMPAT is not set +# CONFIG_BLKDISCARD is not set +# CONFIG_BLKID is not set +# CONFIG_FEATURE_BLKID_TYPE is not set +# CONFIG_BLOCKDEV is not set +# CONFIG_CAL is not set +# CONFIG_CHRT is not set +# CONFIG_DMESG is not set +# CONFIG_FEATURE_DMESG_PRETTY is not set +# CONFIG_EJECT is not set +# CONFIG_FEATURE_EJECT_SCSI is not set +# CONFIG_FALLOCATE is not set +# CONFIG_FATATTR is not set +# CONFIG_FBSET is not set +# CONFIG_FEATURE_FBSET_FANCY is not set +# CONFIG_FEATURE_FBSET_READMODE is not set +# CONFIG_FDFORMAT is not set +# CONFIG_FDISK is not set +# CONFIG_FDISK_SUPPORT_LARGE_DISKS is not set +# CONFIG_FEATURE_FDISK_WRITABLE is not set +# CONFIG_FEATURE_AIX_LABEL is not set +# CONFIG_FEATURE_SGI_LABEL is not set +# CONFIG_FEATURE_SUN_LABEL is not set +# CONFIG_FEATURE_OSF_LABEL is not set +# CONFIG_FEATURE_GPT_LABEL is not set +# CONFIG_FEATURE_FDISK_ADVANCED is not set +# CONFIG_FINDFS is not set +# CONFIG_FLOCK is not set +# CONFIG_FDFLUSH is not set +# CONFIG_FREERAMDISK is not set +# CONFIG_FSCK_MINIX is not set +CONFIG_FSFREEZE=y +CONFIG_FSTRIM=y +CONFIG_GETOPT=y +CONFIG_FEATURE_GETOPT_LONG=y +CONFIG_HEXDUMP=y +# CONFIG_FEATURE_HEXDUMP_REVERSE is not set +# CONFIG_HD is not set +CONFIG_XXD=y +# CONFIG_HWCLOCK is not set +# CONFIG_FEATURE_HWCLOCK_ADJTIME_FHS is not set +# CONFIG_IONICE is not set +# CONFIG_IPCRM is not set +# CONFIG_IPCS is not set +# CONFIG_LAST is not set +# CONFIG_FEATURE_LAST_FANCY is not set +CONFIG_LOSETUP=y +# CONFIG_LSPCI is not set +# CONFIG_LSUSB is not set +# CONFIG_MDEV is not set +# CONFIG_FEATURE_MDEV_CONF is not set +# CONFIG_FEATURE_MDEV_RENAME is not set +# CONFIG_FEATURE_MDEV_RENAME_REGEXP is not set +# CONFIG_FEATURE_MDEV_EXEC is not set +# CONFIG_FEATURE_MDEV_LOAD_FIRMWARE is not set +# CONFIG_FEATURE_MDEV_DAEMON is not set +# CONFIG_MESG is not set +# CONFIG_FEATURE_MESG_ENABLE_ONLY_GROUP is not set +CONFIG_MKE2FS=y +# CONFIG_MKFS_EXT2 is not set +# CONFIG_MKFS_MINIX is not set +# CONFIG_FEATURE_MINIX2 is not set +# CONFIG_MKFS_REISER is not set +# CONFIG_MKDOSFS is not set +# CONFIG_MKFS_VFAT is not set +# CONFIG_MKSWAP is not set +# CONFIG_FEATURE_MKSWAP_UUID is not set +# CONFIG_MORE is not set +# CONFIG_MOUNT is not set +# CONFIG_FEATURE_MOUNT_FAKE is not set +# CONFIG_FEATURE_MOUNT_VERBOSE is not set +# CONFIG_FEATURE_MOUNT_HELPERS is not set +# CONFIG_FEATURE_MOUNT_LABEL is not set +# CONFIG_FEATURE_MOUNT_NFS is not set +# CONFIG_FEATURE_MOUNT_CIFS is not set +# CONFIG_FEATURE_MOUNT_FLAGS is not set +# CONFIG_FEATURE_MOUNT_FSTAB is not set +# CONFIG_FEATURE_MOUNT_OTHERTAB is not set +# CONFIG_MOUNTPOINT is not set +CONFIG_NOLOGIN=y +CONFIG_NOLOGIN_DEPENDENCIES=y +# CONFIG_NSENTER is not set +CONFIG_PIVOT_ROOT=y +# CONFIG_RDATE is not set +# CONFIG_RDEV is not set +# CONFIG_READPROFILE is not set +# CONFIG_RENICE is not set +# CONFIG_REV is not set +# CONFIG_RTCWAKE is not set +# CONFIG_SCRIPT is not set +# CONFIG_SCRIPTREPLAY is not set +# CONFIG_SETARCH is not set +# CONFIG_LINUX32 is not set +# CONFIG_LINUX64 is not set +# CONFIG_SETPRIV is not set +# CONFIG_FEATURE_SETPRIV_DUMP is not set +# CONFIG_FEATURE_SETPRIV_CAPABILITIES is not set +# CONFIG_FEATURE_SETPRIV_CAPABILITY_NAMES is not set +# CONFIG_SETSID is not set +# CONFIG_SWAPON is not set +# CONFIG_FEATURE_SWAPON_DISCARD is not set +# CONFIG_FEATURE_SWAPON_PRI is not set +# CONFIG_SWAPOFF is not set +# CONFIG_FEATURE_SWAPONOFF_LABEL is not set +CONFIG_SWITCH_ROOT=y +# CONFIG_TASKSET is not set +# CONFIG_FEATURE_TASKSET_FANCY is not set +# CONFIG_UEVENT is not set +# CONFIG_UMOUNT is not set +# CONFIG_FEATURE_UMOUNT_ALL is not set +# CONFIG_UNSHARE is not set +# CONFIG_WALL is not set +# CONFIG_FEATURE_MOUNT_LOOP is not set +# CONFIG_FEATURE_MOUNT_LOOP_CREATE is not set +# CONFIG_FEATURE_MTAB_SUPPORT is not set +# CONFIG_VOLUMEID is not set +# CONFIG_FEATURE_VOLUMEID_BCACHE is not set +# CONFIG_FEATURE_VOLUMEID_BTRFS is not set +# CONFIG_FEATURE_VOLUMEID_CRAMFS is not set +# CONFIG_FEATURE_VOLUMEID_EXFAT is not set +# CONFIG_FEATURE_VOLUMEID_EXT is not set +# CONFIG_FEATURE_VOLUMEID_F2FS is not set +# CONFIG_FEATURE_VOLUMEID_FAT is not set +# CONFIG_FEATURE_VOLUMEID_HFS is not set +# CONFIG_FEATURE_VOLUMEID_ISO9660 is not set +# CONFIG_FEATURE_VOLUMEID_JFS is not set +# CONFIG_FEATURE_VOLUMEID_LFS is not set +# CONFIG_FEATURE_VOLUMEID_LINUXRAID is not set +# CONFIG_FEATURE_VOLUMEID_LINUXSWAP is not set +# CONFIG_FEATURE_VOLUMEID_LUKS is not set +# CONFIG_FEATURE_VOLUMEID_MINIX is not set +# CONFIG_FEATURE_VOLUMEID_NILFS is not set +# CONFIG_FEATURE_VOLUMEID_NTFS is not set +# CONFIG_FEATURE_VOLUMEID_OCFS2 is not set +# CONFIG_FEATURE_VOLUMEID_REISERFS is not set +# CONFIG_FEATURE_VOLUMEID_ROMFS is not set +# CONFIG_FEATURE_VOLUMEID_SQUASHFS is not set +# CONFIG_FEATURE_VOLUMEID_SYSV is not set +# CONFIG_FEATURE_VOLUMEID_UBIFS is not set +# CONFIG_FEATURE_VOLUMEID_UDF is not set +# CONFIG_FEATURE_VOLUMEID_XFS is not set + +# +# Miscellaneous Utilities +# +# CONFIG_ADJTIMEX is not set +# CONFIG_BBCONFIG is not set +# CONFIG_FEATURE_COMPRESS_BBCONFIG is not set +CONFIG_BC=y +# CONFIG_DC is not set +CONFIG_FEATURE_DC_BIG=y +# CONFIG_FEATURE_DC_LIBM is not set +CONFIG_FEATURE_BC_INTERACTIVE=y +CONFIG_FEATURE_BC_LONG_OPTIONS=y +# CONFIG_BEEP is not set +CONFIG_FEATURE_BEEP_FREQ=0 +CONFIG_FEATURE_BEEP_LENGTH_MS=0 +# CONFIG_CHAT is not set +# CONFIG_FEATURE_CHAT_NOFAIL is not set +# CONFIG_FEATURE_CHAT_TTY_HIFI is not set +# CONFIG_FEATURE_CHAT_IMPLICIT_CR is not set +# CONFIG_FEATURE_CHAT_SWALLOW_OPTS is not set +# CONFIG_FEATURE_CHAT_SEND_ESCAPES is not set +# CONFIG_FEATURE_CHAT_VAR_ABORT_LEN is not set +# CONFIG_FEATURE_CHAT_CLR_ABORT is not set +# CONFIG_CONSPY is not set +# CONFIG_CROND is not set +# CONFIG_FEATURE_CROND_D is not set +# CONFIG_FEATURE_CROND_CALL_SENDMAIL is not set +# CONFIG_FEATURE_CROND_SPECIAL_TIMES is not set +CONFIG_FEATURE_CROND_DIR="" +# CONFIG_CRONTAB is not set +# CONFIG_DEVFSD is not set +# CONFIG_DEVFSD_MODLOAD is not set +# CONFIG_DEVFSD_FG_NP is not set +# CONFIG_DEVFSD_VERBOSE is not set +# CONFIG_FEATURE_DEVFS is not set +# CONFIG_DEVMEM is not set +# CONFIG_FBSPLASH is not set +# CONFIG_FLASHCP is not set +# CONFIG_FLASH_ERASEALL is not set +# CONFIG_FLASH_LOCK is not set +# CONFIG_FLASH_UNLOCK is not set +# CONFIG_HDPARM is not set +# CONFIG_FEATURE_HDPARM_GET_IDENTITY is not set +# CONFIG_FEATURE_HDPARM_HDIO_SCAN_HWIF is not set +# CONFIG_FEATURE_HDPARM_HDIO_UNREGISTER_HWIF is not set +# CONFIG_FEATURE_HDPARM_HDIO_DRIVE_RESET is not set +# CONFIG_FEATURE_HDPARM_HDIO_TRISTATE_HWIF is not set +# CONFIG_FEATURE_HDPARM_HDIO_GETSET_DMA is not set +CONFIG_HEXEDIT=y +# CONFIG_I2CGET is not set +# CONFIG_I2CSET is not set +# CONFIG_I2CDUMP is not set +# CONFIG_I2CDETECT is not set +# CONFIG_I2CTRANSFER is not set +# CONFIG_INOTIFYD is not set +CONFIG_LESS=y +CONFIG_FEATURE_LESS_MAXLINES=9999999 +CONFIG_FEATURE_LESS_BRACKETS=y +CONFIG_FEATURE_LESS_FLAGS=y +CONFIG_FEATURE_LESS_TRUNCATE=y +# CONFIG_FEATURE_LESS_MARKS is not set +CONFIG_FEATURE_LESS_REGEXP=y +# CONFIG_FEATURE_LESS_WINCH is not set +# CONFIG_FEATURE_LESS_ASK_TERMINAL is not set +# CONFIG_FEATURE_LESS_DASHCMD is not set +# CONFIG_FEATURE_LESS_LINENUMS is not set +# CONFIG_FEATURE_LESS_RAW is not set +# CONFIG_FEATURE_LESS_ENV is not set +# CONFIG_LSSCSI is not set +# CONFIG_MAKEDEVS is not set +# CONFIG_FEATURE_MAKEDEVS_LEAF is not set +# CONFIG_FEATURE_MAKEDEVS_TABLE is not set +# CONFIG_MAN is not set +# CONFIG_MICROCOM is not set +# CONFIG_MT is not set +# CONFIG_NANDWRITE is not set +# CONFIG_NANDDUMP is not set +CONFIG_PARTPROBE=y +# CONFIG_RAIDAUTORUN is not set +# CONFIG_READAHEAD is not set +# CONFIG_RFKILL is not set +CONFIG_RUNLEVEL=y +# CONFIG_RX is not set +CONFIG_SETFATTR=y +# CONFIG_SETSERIAL is not set +# CONFIG_STRINGS is not set +# CONFIG_TIME is not set +CONFIG_TS=y +# CONFIG_TTYSIZE is not set +# CONFIG_UBIRENAME is not set +# CONFIG_UBIATTACH is not set +# CONFIG_UBIDETACH is not set +# CONFIG_UBIMKVOL is not set +# CONFIG_UBIRMVOL is not set +# CONFIG_UBIRSVOL is not set +# CONFIG_UBIUPDATEVOL is not set +# CONFIG_VOLNAME is not set +# CONFIG_WATCHDOG is not set + +# +# Networking Utilities +# +# CONFIG_FEATURE_IPV6 is not set +# CONFIG_FEATURE_UNIX_LOCAL is not set +# CONFIG_FEATURE_PREFER_IPV4_ADDRESS is not set +# CONFIG_VERBOSE_RESOLUTION_ERRORS is not set +# CONFIG_FEATURE_TLS_SHA1 is not set +# CONFIG_ARP is not set +# CONFIG_ARPING is not set +# CONFIG_BRCTL is not set +# CONFIG_FEATURE_BRCTL_FANCY is not set +# CONFIG_FEATURE_BRCTL_SHOW is not set +# CONFIG_DNSD is not set +# CONFIG_ETHER_WAKE is not set +# CONFIG_FTPD is not set +# CONFIG_FEATURE_FTPD_WRITE is not set +# CONFIG_FEATURE_FTPD_ACCEPT_BROKEN_LIST is not set +# CONFIG_FEATURE_FTPD_AUTHENTICATION is not set +# CONFIG_FTPGET is not set +# CONFIG_FTPPUT is not set +# CONFIG_FEATURE_FTPGETPUT_LONG_OPTIONS is not set +# CONFIG_HOSTNAME is not set +# CONFIG_DNSDOMAINNAME is not set +# CONFIG_HTTPD is not set +# CONFIG_FEATURE_HTTPD_RANGES is not set +# CONFIG_FEATURE_HTTPD_SETUID is not set +# CONFIG_FEATURE_HTTPD_BASIC_AUTH is not set +# CONFIG_FEATURE_HTTPD_AUTH_MD5 is not set +# CONFIG_FEATURE_HTTPD_CGI is not set +# CONFIG_FEATURE_HTTPD_CONFIG_WITH_SCRIPT_INTERPR is not set +# CONFIG_FEATURE_HTTPD_SET_REMOTE_PORT_TO_ENV is not set +# CONFIG_FEATURE_HTTPD_ENCODE_URL_STR is not set +# CONFIG_FEATURE_HTTPD_ERROR_PAGES is not set +# CONFIG_FEATURE_HTTPD_PROXY is not set +# CONFIG_FEATURE_HTTPD_GZIP is not set +# CONFIG_IFCONFIG is not set +# CONFIG_FEATURE_IFCONFIG_STATUS is not set +# CONFIG_FEATURE_IFCONFIG_SLIP is not set +# CONFIG_FEATURE_IFCONFIG_MEMSTART_IOADDR_IRQ is not set +# CONFIG_FEATURE_IFCONFIG_HW is not set +# CONFIG_FEATURE_IFCONFIG_BROADCAST_PLUS is not set +# CONFIG_IFENSLAVE is not set +# CONFIG_IFPLUGD is not set +# CONFIG_IFUP is not set +# CONFIG_IFDOWN is not set +CONFIG_IFUPDOWN_IFSTATE_PATH="" +# CONFIG_FEATURE_IFUPDOWN_IP is not set +# CONFIG_FEATURE_IFUPDOWN_IPV4 is not set +# CONFIG_FEATURE_IFUPDOWN_IPV6 is not set +# CONFIG_FEATURE_IFUPDOWN_MAPPING is not set +# CONFIG_FEATURE_IFUPDOWN_EXTERNAL_DHCP is not set +# CONFIG_INETD is not set +# CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_ECHO is not set +# CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DISCARD is not set +# CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_TIME is not set +# CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_DAYTIME is not set +# CONFIG_FEATURE_INETD_SUPPORT_BUILTIN_CHARGEN is not set +# CONFIG_FEATURE_INETD_RPC is not set +# CONFIG_IP is not set +# CONFIG_IPADDR is not set +# CONFIG_IPLINK is not set +# CONFIG_IPROUTE is not set +# CONFIG_IPTUNNEL is not set +# CONFIG_IPRULE is not set +# CONFIG_IPNEIGH is not set +# CONFIG_FEATURE_IP_ADDRESS is not set +# CONFIG_FEATURE_IP_LINK is not set +# CONFIG_FEATURE_IP_ROUTE is not set +CONFIG_FEATURE_IP_ROUTE_DIR="" +# CONFIG_FEATURE_IP_TUNNEL is not set +# CONFIG_FEATURE_IP_RULE is not set +# CONFIG_FEATURE_IP_NEIGH is not set +# CONFIG_FEATURE_IP_RARE_PROTOCOLS is not set +# CONFIG_IPCALC is not set +# CONFIG_FEATURE_IPCALC_LONG_OPTIONS is not set +# CONFIG_FEATURE_IPCALC_FANCY is not set +# CONFIG_FAKEIDENTD is not set +# CONFIG_NAMEIF is not set +# CONFIG_FEATURE_NAMEIF_EXTENDED is not set +# CONFIG_NBDCLIENT is not set +# CONFIG_NC is not set +# CONFIG_NETCAT is not set +# CONFIG_NC_SERVER is not set +# CONFIG_NC_EXTRA is not set +# CONFIG_NC_110_COMPAT is not set +# CONFIG_NETSTAT is not set +# CONFIG_FEATURE_NETSTAT_WIDE is not set +# CONFIG_FEATURE_NETSTAT_PRG is not set +# CONFIG_NSLOOKUP is not set +# CONFIG_FEATURE_NSLOOKUP_BIG is not set +# CONFIG_FEATURE_NSLOOKUP_LONG_OPTIONS is not set +# CONFIG_NTPD is not set +# CONFIG_FEATURE_NTPD_SERVER is not set +# CONFIG_FEATURE_NTPD_CONF is not set +# CONFIG_FEATURE_NTP_AUTH is not set +# CONFIG_PING is not set +# CONFIG_PING6 is not set +# CONFIG_FEATURE_FANCY_PING is not set +# CONFIG_PSCAN is not set +# CONFIG_ROUTE is not set +# CONFIG_SLATTACH is not set +# CONFIG_SSL_CLIENT is not set +# CONFIG_TC is not set +# CONFIG_FEATURE_TC_INGRESS is not set +# CONFIG_TCPSVD is not set +# CONFIG_UDPSVD is not set +# CONFIG_TELNET is not set +# CONFIG_FEATURE_TELNET_TTYPE is not set +# CONFIG_FEATURE_TELNET_AUTOLOGIN is not set +# CONFIG_FEATURE_TELNET_WIDTH is not set +# CONFIG_TELNETD is not set +# CONFIG_FEATURE_TELNETD_STANDALONE is not set +# CONFIG_FEATURE_TELNETD_INETD_WAIT is not set +# CONFIG_TFTP is not set +# CONFIG_FEATURE_TFTP_PROGRESS_BAR is not set +# CONFIG_FEATURE_TFTP_HPA_COMPAT is not set +# CONFIG_TFTPD is not set +# CONFIG_FEATURE_TFTP_GET is not set +# CONFIG_FEATURE_TFTP_PUT is not set +# CONFIG_FEATURE_TFTP_BLOCKSIZE is not set +# CONFIG_TFTP_DEBUG is not set +# CONFIG_TLS is not set +# CONFIG_TRACEROUTE is not set +# CONFIG_TRACEROUTE6 is not set +# CONFIG_FEATURE_TRACEROUTE_VERBOSE is not set +# CONFIG_FEATURE_TRACEROUTE_USE_ICMP is not set +# CONFIG_TUNCTL is not set +# CONFIG_FEATURE_TUNCTL_UG is not set +# CONFIG_VCONFIG is not set +# CONFIG_WGET is not set +# CONFIG_FEATURE_WGET_LONG_OPTIONS is not set +# CONFIG_FEATURE_WGET_STATUSBAR is not set +# CONFIG_FEATURE_WGET_AUTHENTICATION is not set +# CONFIG_FEATURE_WGET_TIMEOUT is not set +# CONFIG_FEATURE_WGET_HTTPS is not set +# CONFIG_FEATURE_WGET_OPENSSL is not set +# CONFIG_WHOIS is not set +# CONFIG_ZCIP is not set +# CONFIG_UDHCPD is not set +# CONFIG_FEATURE_UDHCPD_BASE_IP_ON_MAC is not set +# CONFIG_FEATURE_UDHCPD_WRITE_LEASES_EARLY is not set +CONFIG_DHCPD_LEASES_FILE="" +# CONFIG_DUMPLEASES is not set +# CONFIG_DHCPRELAY is not set +# CONFIG_UDHCPC is not set +# CONFIG_FEATURE_UDHCPC_ARPING is not set +# CONFIG_FEATURE_UDHCPC_SANITIZEOPT is not set +CONFIG_UDHCPC_DEFAULT_SCRIPT="" +# CONFIG_UDHCPC6 is not set +# CONFIG_FEATURE_UDHCPC6_RFC3646 is not set +# CONFIG_FEATURE_UDHCPC6_RFC4704 is not set +# CONFIG_FEATURE_UDHCPC6_RFC4833 is not set +# CONFIG_FEATURE_UDHCPC6_RFC5970 is not set +# CONFIG_FEATURE_UDHCP_PORT is not set +CONFIG_UDHCP_DEBUG=0 +CONFIG_UDHCPC_SLACK_FOR_BUGGY_SERVERS=0 +# CONFIG_FEATURE_UDHCP_RFC3397 is not set +# CONFIG_FEATURE_UDHCP_8021Q is not set +CONFIG_IFUPDOWN_UDHCPC_CMD_OPTIONS="" + +# +# Print Utilities +# +# CONFIG_LPD is not set +# CONFIG_LPR is not set +# CONFIG_LPQ is not set + +# +# Mail Utilities +# +# CONFIG_MAKEMIME is not set +# CONFIG_POPMAILDIR is not set +# CONFIG_FEATURE_POPMAILDIR_DELIVERY is not set +# CONFIG_REFORMIME is not set +# CONFIG_FEATURE_REFORMIME_COMPAT is not set +# CONFIG_SENDMAIL is not set +CONFIG_FEATURE_MIME_CHARSET="" + +# +# Process Utilities +# +CONFIG_FREE=y +# CONFIG_FUSER is not set +# CONFIG_IOSTAT is not set +CONFIG_KILL=y +CONFIG_KILLALL=y +CONFIG_KILLALL5=y +CONFIG_LSOF=y +# CONFIG_MPSTAT is not set +# CONFIG_NMETER is not set +# CONFIG_PGREP is not set +# CONFIG_PKILL is not set +CONFIG_PIDOF=y +CONFIG_FEATURE_PIDOF_SINGLE=y +CONFIG_FEATURE_PIDOF_OMIT=y +# CONFIG_PMAP is not set +# CONFIG_POWERTOP is not set +# CONFIG_FEATURE_POWERTOP_INTERACTIVE is not set +CONFIG_PS=y +CONFIG_FEATURE_PS_WIDE=y +CONFIG_FEATURE_PS_LONG=y +# CONFIG_FEATURE_PS_TIME is not set +# CONFIG_FEATURE_PS_UNUSUAL_SYSTEMS is not set +# CONFIG_FEATURE_PS_ADDITIONAL_COLUMNS is not set +# CONFIG_PSTREE is not set +# CONFIG_PWDX is not set +# CONFIG_SMEMCAP is not set +CONFIG_BB_SYSCTL=y +# CONFIG_TOP is not set +# CONFIG_FEATURE_TOP_INTERACTIVE is not set +# CONFIG_FEATURE_TOP_CPU_USAGE_PERCENTAGE is not set +# CONFIG_FEATURE_TOP_CPU_GLOBAL_PERCENTS is not set +# CONFIG_FEATURE_TOP_SMP_CPU is not set +# CONFIG_FEATURE_TOP_DECIMALS is not set +# CONFIG_FEATURE_TOP_SMP_PROCESS is not set +# CONFIG_FEATURE_TOPMEM is not set +# CONFIG_UPTIME is not set +# CONFIG_FEATURE_UPTIME_UTMP_SUPPORT is not set +# CONFIG_WATCH is not set +# CONFIG_FEATURE_SHOW_THREADS is not set + +# +# Runit Utilities +# +# CONFIG_CHPST is not set +# CONFIG_SETUIDGID is not set +# CONFIG_ENVUIDGID is not set +# CONFIG_ENVDIR is not set +# CONFIG_SOFTLIMIT is not set +# CONFIG_RUNSV is not set +# CONFIG_RUNSVDIR is not set +# CONFIG_FEATURE_RUNSVDIR_LOG is not set +# CONFIG_SV is not set +CONFIG_SV_DEFAULT_SERVICE_DIR="" +# CONFIG_SVC is not set +# CONFIG_SVOK is not set +# CONFIG_SVLOGD is not set +# CONFIG_CHCON is not set +# CONFIG_GETENFORCE is not set +# CONFIG_GETSEBOOL is not set +# CONFIG_LOAD_POLICY is not set +# CONFIG_MATCHPATHCON is not set +# CONFIG_RUNCON is not set +# CONFIG_SELINUXENABLED is not set +# CONFIG_SESTATUS is not set +# CONFIG_SETENFORCE is not set +# CONFIG_SETFILES is not set +# CONFIG_FEATURE_SETFILES_CHECK_OPTION is not set +# CONFIG_RESTORECON is not set +# CONFIG_SETSEBOOL is not set + +# +# Shells +# +CONFIG_SH_IS_ASH=y +# CONFIG_SH_IS_HUSH is not set +# CONFIG_SH_IS_NONE is not set +# CONFIG_BASH_IS_ASH is not set +# CONFIG_BASH_IS_HUSH is not set +CONFIG_BASH_IS_NONE=y +CONFIG_ASH=y +CONFIG_ASH_OPTIMIZE_FOR_SIZE=y +CONFIG_ASH_INTERNAL_GLOB=y +CONFIG_ASH_BASH_COMPAT=y +# CONFIG_ASH_BASH_SOURCE_CURDIR is not set +CONFIG_ASH_BASH_NOT_FOUND_HOOK=y +CONFIG_ASH_JOB_CONTROL=y +CONFIG_ASH_ALIAS=y +CONFIG_ASH_RANDOM_SUPPORT=y +CONFIG_ASH_EXPAND_PRMT=y +CONFIG_ASH_IDLE_TIMEOUT=y +# CONFIG_ASH_MAIL is not set +CONFIG_ASH_ECHO=y +CONFIG_ASH_PRINTF=y +CONFIG_ASH_TEST=y +CONFIG_ASH_HELP=y +CONFIG_ASH_GETOPTS=y +CONFIG_ASH_CMDCMD=y +# CONFIG_CTTYHACK is not set +# CONFIG_HUSH is not set +# CONFIG_HUSH_BASH_COMPAT is not set +# CONFIG_HUSH_BRACE_EXPANSION is not set +# CONFIG_HUSH_LINENO_VAR is not set +# CONFIG_HUSH_BASH_SOURCE_CURDIR is not set +# CONFIG_HUSH_INTERACTIVE is not set +# CONFIG_HUSH_SAVEHISTORY is not set +# CONFIG_HUSH_JOB is not set +# CONFIG_HUSH_TICK is not set +# CONFIG_HUSH_IF is not set +# CONFIG_HUSH_LOOPS is not set +# CONFIG_HUSH_CASE is not set +# CONFIG_HUSH_FUNCTIONS is not set +# CONFIG_HUSH_LOCAL is not set +# CONFIG_HUSH_RANDOM_SUPPORT is not set +# CONFIG_HUSH_MODE_X is not set +# CONFIG_HUSH_ECHO is not set +# CONFIG_HUSH_PRINTF is not set +# CONFIG_HUSH_TEST is not set +# CONFIG_HUSH_HELP is not set +# CONFIG_HUSH_EXPORT is not set +# CONFIG_HUSH_EXPORT_N is not set +# CONFIG_HUSH_READONLY is not set +# CONFIG_HUSH_KILL is not set +# CONFIG_HUSH_WAIT is not set +# CONFIG_HUSH_COMMAND is not set +# CONFIG_HUSH_TRAP is not set +# CONFIG_HUSH_TYPE is not set +# CONFIG_HUSH_TIMES is not set +# CONFIG_HUSH_READ is not set +# CONFIG_HUSH_SET is not set +# CONFIG_HUSH_UNSET is not set +# CONFIG_HUSH_ULIMIT is not set +# CONFIG_HUSH_UMASK is not set +# CONFIG_HUSH_GETOPTS is not set +# CONFIG_HUSH_MEMLEAK is not set + +# +# Options common to all shells +# +CONFIG_FEATURE_SH_MATH=y +CONFIG_FEATURE_SH_MATH_64=y +CONFIG_FEATURE_SH_MATH_BASE=y +CONFIG_FEATURE_SH_EXTRA_QUIET=y +# CONFIG_FEATURE_SH_STANDALONE is not set +# CONFIG_FEATURE_SH_NOFORK is not set +CONFIG_FEATURE_SH_READ_FRAC=y +# CONFIG_FEATURE_SH_HISTFILESIZE is not set +CONFIG_FEATURE_SH_EMBEDDED_SCRIPTS=y + +# +# System Logging Utilities +# +# CONFIG_KLOGD is not set +# CONFIG_FEATURE_KLOGD_KLOGCTL is not set +# CONFIG_LOGGER is not set +# CONFIG_LOGREAD is not set +# CONFIG_FEATURE_LOGREAD_REDUCED_LOCKING is not set +# CONFIG_SYSLOGD is not set +# CONFIG_FEATURE_ROTATE_LOGFILE is not set +# CONFIG_FEATURE_REMOTE_LOG is not set +# CONFIG_FEATURE_SYSLOGD_DUP is not set +# CONFIG_FEATURE_SYSLOGD_CFG is not set +CONFIG_FEATURE_SYSLOGD_READ_BUFFER_SIZE=0 +# CONFIG_FEATURE_IPC_SYSLOG is not set +CONFIG_FEATURE_IPC_SYSLOG_BUFFER_SIZE=0 +# CONFIG_FEATURE_KMSG_SYSLOG is not set diff --git a/board/myna-player-odyssey/configs/linux.config b/board/myna-player-odyssey/configs/linux.config new file mode 100644 index 0000000..873d37c --- /dev/null +++ b/board/myna-player-odyssey/configs/linux.config @@ -0,0 +1,850 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_KERNEL_XZ=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_USELIB=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio" +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_BPF_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_STM32=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_798181=y +CONFIG_SMP=y +CONFIG_MCPM=y +CONFIG_HIGHMEM=y +CONFIG_FORCE_MAX_ZONEORDER=12 +CONFIG_SECCOMP=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_CRC32_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +# CONFIG_GCC_PLUGINS is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_TRIM_UNUSED_KSYMS=y +CONFIG_BLK_CMDLINE_PARSER=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_FIB_TRIE_STATS=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_ADVANCED is not set +CONFIG_NF_CONNTRACK_LABELS=y +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +# CONFIG_NF_NAT is not set +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_IP_NF_NAT is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP6_NF_MANGLE is not set +CONFIG_L2TP=m +CONFIG_IEEE802154=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_DEFAULT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_DNS_RESOLVER=y +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BPF_JIT=y +CONFIG_NET_DROP_MONITOR=y +CONFIG_BT=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_SIMPLE_PM_BUS=y +CONFIG_VEXPRESS_CONFIG=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VIRTIO_BLK=y +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_ICS932S401=y +CONFIG_SRAM=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_93CX6=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_ATA=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_TUN=m +CONFIG_TUN_VNET_CROSS_LE=y +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_BCMGENET=m +CONFIG_SYSTEMPORT=m +CONFIG_MACB=y +CONFIG_HIX5HD2_GMAC=y +CONFIG_MVMDIO=y +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_SMC91X=m +CONFIG_SMC911X=m +CONFIG_SMSC911X=m +CONFIG_STMMAC_ETH=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_MDIO_BITBANG=m +CONFIG_BROADCOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MICREL_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_B43=m +CONFIG_B43_SDIO=y +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCM_TRACING=y +CONFIG_BRCMDBG=y +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_RT2X00=m +CONFIG_RT2800USB=m +CONFIG_RTL8192CU=m +CONFIG_NET_FAILOVER=y +CONFIG_INPUT_JOYDEV=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_SAMSUNG=m +CONFIG_KEYBOARD_BCM=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MAX77693_HAPTIC=m +CONFIG_INPUT_MAX8997_HAPTIC=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_STPMIC1_ONKEY=y +CONFIG_SERIO_AMBAKMI=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y +CONFIG_SERIAL_STM32=y +CONFIG_SERIAL_STM32_CONSOLE=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_ST33ZP24_I2C=y +CONFIG_TCG_TIS_ST33ZP24_SPI=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=m +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_PINCTRL=y +CONFIG_I2C_DEMUX_PINCTRL=y +CONFIG_I2C_NOMADIK=y +CONFIG_I2C_STM32F7=y +CONFIG_SPI=y +CONFIG_SPI_MEM=y +CONFIG_SPI_CADENCE=y +CONFIG_SPI_GPIO=m +CONFIG_SPI_PL022=y +CONFIG_SPI_ROCKCHIP=m +CONFIG_SPI_STM32=y +CONFIG_SPI_STM32_QSPI=y +CONFIG_SPI_XILINX=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=y +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y +CONFIG_SPMI=y +CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_STMFX=y +CONFIG_PINCTRL_PALMAS=y +CONFIG_GPIO_DWAPB=y +CONFIG_GPIO_PL061=y +CONFIG_GPIO_SYSCON=y +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_PALMAS=y +CONFIG_GPIO_TPS6586X=y +CONFIG_GPIO_TPS65910=y +CONFIG_GPIO_TWL4030=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_AS3722=y +CONFIG_POWER_RESET_BRCMKONA=y +CONFIG_POWER_RESET_BRCMSTB=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_LM95245=y +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_STTS751=y +CONFIG_SENSORS_INA2XX=m +CONFIG_ST_THERMAL_MEMMAP=y +CONFIG_WATCHDOG=y +CONFIG_DA9063_WATCHDOG=m +CONFIG_XILINX_WATCHDOG=y +CONFIG_ARM_SP805_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +CONFIG_RN5T618_WATCHDOG=y +CONFIG_STPMIC1_WATCHDOG=y +CONFIG_BCMA=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_MFD_ACT8945A=y +CONFIG_MFD_AS3711=y +CONFIG_MFD_AS3722=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_ATMEL_HLCDC=m +CONFIG_MFD_BCM590XX=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_DA9063=m +CONFIG_MFD_MAX14577=y +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX77693=m +CONFIG_MFD_MAX8907=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_MAX8998=y +CONFIG_MFD_CPCAP=y +CONFIG_MFD_PM8XXX=y +CONFIG_MFD_RK808=y +CONFIG_MFD_RN5T618=y +CONFIG_MFD_SEC_CORE=y +CONFIG_ABX500_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_MFD_PALMAS=y +CONFIG_MFD_TPS65090=y +CONFIG_MFD_TPS65217=y +CONFIG_MFD_TPS65218=y +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y +CONFIG_TWL4030_CORE=y +CONFIG_TWL4030_POWER=y +CONFIG_MFD_WM8994=y +CONFIG_MFD_STM32_LPTIMER=y +CONFIG_MFD_STPMIC1=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ACT8945A=y +CONFIG_REGULATOR_AS3711=y +CONFIG_REGULATOR_AS3722=y +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BCM590XX=y +CONFIG_REGULATOR_CPCAP=y +CONFIG_REGULATOR_DA9210=y +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_LP872X=y +CONFIG_REGULATOR_MAX14577=m +CONFIG_REGULATOR_MAX8907=y +CONFIG_REGULATOR_MAX8973=y +CONFIG_REGULATOR_MAX8997=m +CONFIG_REGULATOR_MAX8998=m +CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_MAX77693=m +CONFIG_REGULATOR_MAX77802=m +CONFIG_REGULATOR_PALMAS=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK808=y +CONFIG_REGULATOR_RN5T618=y +CONFIG_REGULATOR_S2MPS11=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_REGULATOR_STM32_VREFBUF=y +CONFIG_REGULATOR_STM32_PWR=y +CONFIG_REGULATOR_STPMIC1=y +CONFIG_REGULATOR_TPS51632=y +CONFIG_REGULATOR_TPS62360=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_REGULATOR_TPS65217=y +CONFIG_REGULATOR_TPS65218=y +CONFIG_REGULATOR_TPS6586X=y +CONFIG_REGULATOR_TPS65910=y +CONFIG_REGULATOR_TWL4030=y +CONFIG_REGULATOR_VEXPRESS=y +CONFIG_DRM=y +CONFIG_DRM_EXYNOS=m +CONFIG_DRM_EXYNOS_FIMD=y +CONFIG_DRM_EXYNOS_MIXER=y +CONFIG_DRM_EXYNOS_DPI=y +CONFIG_DRM_EXYNOS_DSI=y +CONFIG_DRM_EXYNOS_HDMI=y +CONFIG_DRM_ATMEL_HLCDC=m +CONFIG_DRM_RCAR_LVDS=y +CONFIG_DRM_FSL_DCU=m +CONFIG_DRM_STM=y +CONFIG_DRM_STM_DSI=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=y +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_SII902X=y +CONFIG_DRM_SII9234=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_STI=m +CONFIG_DRM_MXSFB=m +CONFIG_FB_ARMCLCD=y +CONFIG_FB_SIMPLE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_AS3711=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=m +CONFIG_SND_ATMEL_SOC=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_STM32_SAI=m +CONFIG_SND_SOC_STM32_I2S=m +CONFIG_SND_SOC_STM32_SPDIFRX=m +CONFIG_SND_SOC_STM32_DFSDM=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_CPCAP=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=y +CONFIG_USB=y +CONFIG_USB_OTG=y +CONFIG_USB_OTG_FSM=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_MON=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_FOTG210_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +CONFIG_USB_DWC2=m +CONFIG_USB_CHIPIDEA=m +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USB_TEST=m +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_CHAOSKEY=m +CONFIG_NOP_USB_XCEIV=m +CONFIG_AM335X_PHY_USB=m +CONFIG_USB_GPIO_VBUS=m +CONFIG_USB_ISP1301=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=m +CONFIG_USB_SNP_UDC_PLAT=m +CONFIG_USB_BDC_UDC=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_CDC=y +CONFIG_TYPEC=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=16 +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_DW=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_SDHCI_OMAP=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_MAX77693=m +CONFIG_LEDS_MAX8997=m +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_EDAC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AS3722=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_MAX8907=y +CONFIG_RTC_DRV_MAX8998=m +CONFIG_RTC_DRV_MAX8997=m +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_BQ32K=m +CONFIG_RTC_DRV_TWL4030=y +CONFIG_RTC_DRV_PALMAS=y +CONFIG_RTC_DRV_TPS6586X=y +CONFIG_RTC_DRV_TPS65910=y +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_RX8581=m +CONFIG_RTC_DRV_EM3027=y +CONFIG_RTC_DRV_S5M=m +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_STM32=y +CONFIG_RTC_DRV_CPCAP=m +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_PL330_DMA=y +CONFIG_STM32_DMA=y +CONFIG_STM32_DMAMUX=y +CONFIG_STM32_MDMA=y +CONFIG_DW_DMAC=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_COMMON_CLK_MAX77686=y +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_S2MPS11=m +CONFIG_CLK_QORIQ=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_PL320_MBOX=y +CONFIG_STM32_IPCC=y +CONFIG_REMOTEPROC=y +CONFIG_STM32_RPROC=y +CONFIG_RPMSG_VIRTIO=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_IIO=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_SW_TRIGGER=y +CONFIG_CPCAP_ADC=m +CONFIG_SD_ADC_MODULATOR=y +CONFIG_STM32_ADC_CORE=y +CONFIG_STM32_ADC=y +CONFIG_STM32_DFSDM_ADC=y +CONFIG_VF610_ADC=m +CONFIG_STM32_DAC=y +CONFIG_MPU3050_I2C=y +CONFIG_HTS221=y +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_CM36651=m +CONFIG_SENSORS_ISL29018=y +CONFIG_SENSORS_ISL29028=y +CONFIG_AK8975=y +CONFIG_IIO_HRTIMER_TRIGGER=y +CONFIG_IIO_STM32_LPTIMER_TRIGGER=y +CONFIG_IIO_ST_PRESS=m +CONFIG_PWM=y +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_FSL_FTM=m +CONFIG_PWM_STM32=y +CONFIG_PWM_STM32_LP=y +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_SAMSUNG_USB2=m +CONFIG_PHY_STM32_USBPHYC=y +CONFIG_RAS=y +CONFIG_NVMEM_STM32_ROMEM=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_OVERLAY_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +# CONFIG_SECURITYFS is not set +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_DEV_STM32_CRC=y +CONFIG_CRYPTO_DEV_STM32_HASH=y +CONFIG_CRYPTO_DEV_STM32_CRYP=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=128 +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_GDB_SCRIPTS=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m diff --git a/board/myna-player-odyssey/initramfs_overlay/etc/fstab b/board/myna-player-odyssey/initramfs_overlay/etc/fstab new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_overlay/etc/fstab diff --git a/board/myna-player-odyssey/initramfs_overlay/etc/group b/board/myna-player-odyssey/initramfs_overlay/etc/group new file mode 100644 index 0000000..18acc30 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_overlay/etc/group @@ -0,0 +1 @@ +root:x:0:root diff --git a/board/myna-player-odyssey/initramfs_overlay/etc/initrd-release b/board/myna-player-odyssey/initramfs_overlay/etc/initrd-release new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_overlay/etc/initrd-release diff --git a/board/myna-player-odyssey/initramfs_overlay/etc/passwd b/board/myna-player-odyssey/initramfs_overlay/etc/passwd new file mode 100644 index 0000000..5183638 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_overlay/etc/passwd @@ -0,0 +1 @@ +root:x:0:0:root:/:/bin/sh diff --git a/board/myna-player-odyssey/initramfs_overlay/etc/shadow b/board/myna-player-odyssey/initramfs_overlay/etc/shadow new file mode 100644 index 0000000..6a17be6 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_overlay/etc/shadow @@ -0,0 +1 @@ +root:::::::: diff --git a/board/myna-player-odyssey/initramfs_overlay/etc/systemd/system/systemd-udevd.service.d/resolve-names.conf b/board/myna-player-odyssey/initramfs_overlay/etc/systemd/system/systemd-udevd.service.d/resolve-names.conf new file mode 100644 index 0000000..272dc59 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_overlay/etc/systemd/system/systemd-udevd.service.d/resolve-names.conf @@ -0,0 +1,3 @@ +[Service] +ExecStart= +ExecStart=/usr/lib/systemd/systemd-udevd --resolve-names=never diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0001-fdts-stm32mp157ca-dk1-Use-STPMIC-on-I2C2-and-eMMC-on.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0001-fdts-stm32mp157ca-dk1-Use-STPMIC-on-I2C2-and-eMMC-on.patch new file mode 100644 index 0000000..a67ecd6 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0001-fdts-stm32mp157ca-dk1-Use-STPMIC-on-I2C2-and-eMMC-on.patch @@ -0,0 +1,90 @@ +From ce8f8385e099b5dfee521d58bba40771c072b0df Mon Sep 17 00:00:00 2001 +From: Jookia +Date: Tue, 28 Jul 2020 14:13:17 +1000 +Subject: [PATCH 1/7] fdts: stm32mp157ca-dk1: Use STPMIC on I2C2 and eMMC on + SDMMC2 + +Quick hack to get things working on the Seeed Odyssey board. +--- + fdts/stm32mp157-pinctrl.dtsi | 10 ++++++++++ + fdts/stm32mp157a-dk1.dts | 8 ++++---- + fdts/stm32mp157c.dtsi | 14 ++++++++++++++ + 3 files changed, 28 insertions(+), 4 deletions(-) + +diff --git a/fdts/stm32mp157-pinctrl.dtsi b/fdts/stm32mp157-pinctrl.dtsi +index 8e480b2c1..4b746b225 100644 +--- a/fdts/stm32mp157-pinctrl.dtsi ++++ b/fdts/stm32mp157-pinctrl.dtsi +@@ -214,6 +214,16 @@ + }; + }; + ++ i2c2_pins_a: i2c2-0 { ++ pins { ++ pinmux = , /* I2C2_SCL */ ++ ; /* I2C2_SDA */ ++ bias-disable; ++ drive-open-drain; ++ slew-rate = <0>; ++ }; ++ }; ++ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ +diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts +index 4ea83f7cd..78681b0ba 100644 +--- a/fdts/stm32mp157a-dk1.dts ++++ b/fdts/stm32mp157a-dk1.dts +@@ -29,9 +29,9 @@ + st,digbypass; + }; + +-&i2c4 { ++&i2c2 { + pinctrl-names = "default"; +- pinctrl-0 = <&i2c4_pins_a>; ++ pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +@@ -162,9 +162,9 @@ + status = "okay"; + }; + +-&sdmmc1 { ++&sdmmc2 { + pinctrl-names = "default"; +- pinctrl-0 = <&sdmmc1_b4_pins_a>; ++ pinctrl-0 = <&sdmmc2_b4_pins_a>; + broken-cd; + st,neg-edge; + bus-width = <4>; +diff --git a/fdts/stm32mp157c.dtsi b/fdts/stm32mp157c.dtsi +index 0942a91c2..faa409f2d 100644 +--- a/fdts/stm32mp157c.dtsi ++++ b/fdts/stm32mp157c.dtsi +@@ -312,6 +312,20 @@ + status = "disabled"; + }; + ++ ++ i2c2: i2c@40013000 { ++ compatible = "st,stm32f7-i2c"; ++ reg = <0x40013000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C2_K>; ++ resets = <&rcc I2C2_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2c4: i2c@5c002000 { + compatible = "st,stm32f7-i2c"; + reg = <0x5c002000 0x400>; +-- +2.27.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0002-arch-rename-CNTBaseN-register-offsets-defines.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0002-arch-rename-CNTBaseN-register-offsets-defines.patch new file mode 100644 index 0000000..269cda7 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0002-arch-rename-CNTBaseN-register-offsets-defines.patch @@ -0,0 +1,62 @@ +From 3a29660ebc69c11fc841a662e8692e59c45eda10 Mon Sep 17 00:00:00 2001 +From: Yann Gautier +Date: Tue, 21 May 2019 18:32:14 +0200 +Subject: [PATCH 2/7] arch: rename CNTBaseN register offsets defines + +The CNTFRQ already has a CNTBASEN_ prefix. +To be able to use CNTP_CTL from CP15, the CNTP_CTL define is renamed +CNTBASEN_CNTP_CTL. +To keep consistency, CNTPCT_LO and CNTP_CVAL_LO are also prefixed. + +Change-Id: Ie328daa694a708130ee369218b57c0f4b08f7f44 +Signed-off-by: Yann Gautier +--- + include/arch/aarch32/arch.h | 6 +++--- + include/arch/aarch64/arch.h | 6 +++--- + 2 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h +index 20175481f..047770e4f 100644 +--- a/include/arch/aarch32/arch.h ++++ b/include/arch/aarch32/arch.h +@@ -457,13 +457,13 @@ + * system level implementation of the Generic Timer. + ******************************************************************************/ + /* Physical Count register. */ +-#define CNTPCT_LO U(0x0) ++#define CNTBASEN_CNTPCT_LO U(0x0) + /* Counter Frequency register. */ + #define CNTBASEN_CNTFRQ U(0x10) + /* Physical Timer CompareValue register. */ +-#define CNTP_CVAL_LO U(0x20) ++#define CNTBASEN_CNTP_CVAL_LO U(0x20) + /* Physical Timer Control register. */ +-#define CNTP_CTL U(0x2c) ++#define CNTBASEN_CNTP_CTL U(0x2c) + + /* Physical timer control register bit fields shifts and masks */ + #define CNTP_CTL_ENABLE_SHIFT 0 +diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h +index 3ff2912f1..307dad585 100644 +--- a/include/arch/aarch64/arch.h ++++ b/include/arch/aarch64/arch.h +@@ -670,13 +670,13 @@ + * system level implementation of the Generic Timer. + ******************************************************************************/ + /* Physical Count register. */ +-#define CNTPCT_LO U(0x0) ++#define CNTBASEN_CNTPCT_LO U(0x0) + /* Counter Frequency register. */ + #define CNTBASEN_CNTFRQ U(0x10) + /* Physical Timer CompareValue register. */ +-#define CNTP_CVAL_LO U(0x20) ++#define CNTBASEN_CNTP_CVAL_LO U(0x20) + /* Physical Timer Control register. */ +-#define CNTP_CTL U(0x2c) ++#define CNTBASEN_CNTP_CTL U(0x2c) + + /* PMCR_EL0 definitions */ + #define PMCR_EL0_RESET_VAL U(0x0) +-- +2.27.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0003-aarch32-add-virtual-timer-control-support.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0003-aarch32-add-virtual-timer-control-support.patch new file mode 100644 index 0000000..bb79878 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0003-aarch32-add-virtual-timer-control-support.patch @@ -0,0 +1,50 @@ +From 7e3d16e5f993271e20136e732cebc78fd90adddb Mon Sep 17 00:00:00 2001 +From: Yann Gautier +Date: Tue, 21 May 2019 18:46:27 +0200 +Subject: [PATCH 3/7] aarch32: add virtual timer control support + +Define virtual timer resources for a platform to be able to control +virtual timers, even if TF-A does not enable them. +This is required for example when the secure world wants to reset +the system. Virtual timers enabled from non-secure world can +jeopardize the reset sequence due to pending interrupts. + +Change-Id: Ieb0ce4819809ae9c4ab11f9244a6cacf9437d6b4 +Signed-off-by: Nicolas Le Bayon +Signed-off-by: Yann Gautier +--- + include/arch/aarch32/arch.h | 3 +++ + include/arch/aarch32/arch_helpers.h | 3 +++ + 2 files changed, 6 insertions(+) + +diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h +index 047770e4f..edf12873d 100644 +--- a/include/arch/aarch32/arch.h ++++ b/include/arch/aarch32/arch.h +@@ -522,6 +522,9 @@ + #define HSTR p15, 4, c1, c1, 3 + #define CNTHCTL p15, 4, c14, c1, 0 + #define CNTKCTL p15, 0, c14, c1, 0 ++#define CNTP_TVAL p15, 0, c14, c2, 0 ++#define CNTP_CTL p15, 0, c14, c2, 1 ++#define CNTV_CTL p15, 0, c14, c3, 1 + #define VPIDR p15, 4, c0, c0, 0 + #define VMPIDR p15, 4, c0, c0, 5 + #define ISR p15, 0, c12, c1, 0 +diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h +index cbac84b93..b060f855c 100644 +--- a/include/arch/aarch32/arch_helpers.h ++++ b/include/arch/aarch32/arch_helpers.h +@@ -246,6 +246,9 @@ DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64) + DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64) + DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR) + DEFINE_COPROCR_RW_FUNCS(hstr, HSTR) ++DEFINE_COPROCR_RW_FUNCS(cntp_tval, CNTP_TVAL) ++DEFINE_COPROCR_RW_FUNCS(cntp_ctl, CNTP_CTL) ++DEFINE_COPROCR_RW_FUNCS(cntv_ctl, CNTV_CTL) + DEFINE_COPROCR_RW_FUNCS(cnthp_ctl_el2, CNTHP_CTL) + DEFINE_COPROCR_RW_FUNCS(cnthp_tval_el2, CNTHP_TVAL) + DEFINE_COPROCR_RW_FUNCS_64(cnthp_cval_el2, CNTHP_CVAL_64) +-- +2.27.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0004-stm32mp1-add-RTC-driver.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0004-stm32mp1-add-RTC-driver.patch new file mode 100644 index 0000000..a9a9dc3 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0004-stm32mp1-add-RTC-driver.patch @@ -0,0 +1,736 @@ +From 50302f6ebc885c3788794587203a6a6012d48d04 Mon Sep 17 00:00:00 2001 +From: Yann Gautier +Date: Mon, 13 May 2019 18:37:00 +0200 +Subject: [PATCH 4/7] stm32mp1: add RTC driver + +This driver is responsible to manage STM32MP1 Real Time Clock IP. + +Change-Id: I8bb84cf2a2786be718944d69153f676d57bfbc37 +Signed-off-by: Yann Gautier +Signed-off-by: Nicolas Le Bayon +--- + drivers/st/clk/stm32mp1_clk.c | 37 ++ + drivers/st/rtc/stm32_rtc.c | 488 +++++++++++++++++++++ + include/drivers/st/stm32_rtc.h | 78 ++++ + include/drivers/st/stm32mp1_clk.h | 2 + + plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk | 1 + + plat/st/stm32mp1/sp_min/sp_min_setup.c | 34 +- + 6 files changed, 632 insertions(+), 8 deletions(-) + create mode 100644 drivers/st/rtc/stm32_rtc.c + create mode 100644 include/drivers/st/stm32_rtc.h + +diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c +index 0cc87cc71..994614f03 100644 +--- a/drivers/st/clk/stm32mp1_clk.c ++++ b/drivers/st/clk/stm32mp1_clk.c +@@ -1572,6 +1572,43 @@ void stm32mp1_stgen_increment(unsigned long long offset_in_ms) + mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); + } + ++/******************************************************************************* ++ * This function determines the number of needed RTC calendar read operations ++ * to get consistent values (1 or 2 depending on clock frequencies). ++ * If APB1 frequency is lower than 7 times the RTC one, the software has to ++ * read the calendar time and date registers twice. ++ * Returns true if read twice is needed, false else. ++ ******************************************************************************/ ++bool stm32mp1_rtc_get_read_twice(void) ++{ ++ unsigned long apb1_freq; ++ uint32_t rtc_freq; ++ uint32_t apb1_div; ++ uintptr_t rcc_base = stm32mp_rcc_base(); ++ ++ switch ((mmio_read_32(rcc_base + RCC_BDCR) & ++ RCC_BDCR_RTCSRC_MASK) >> RCC_BDCR_RTCSRC_SHIFT) { ++ case 1: ++ rtc_freq = stm32mp_clk_get_rate(CK_LSE); ++ break; ++ case 2: ++ rtc_freq = stm32mp_clk_get_rate(CK_LSI); ++ break; ++ case 3: ++ rtc_freq = stm32mp_clk_get_rate(CK_HSE); ++ rtc_freq /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & ++ RCC_DIVR_DIV_MASK) + 1U; ++ break; ++ default: ++ panic(); ++ } ++ ++ apb1_div = mmio_read_32(rcc_base + RCC_APB1DIVR) & RCC_APBXDIV_MASK; ++ apb1_freq = stm32mp_clk_get_rate(CK_MCU) >> apb1_div; ++ ++ return apb1_freq < (rtc_freq * 7U); ++} ++ + static void stm32mp1_pkcs_config(uint32_t pkcs) + { + uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); +diff --git a/drivers/st/rtc/stm32_rtc.c b/drivers/st/rtc/stm32_rtc.c +new file mode 100644 +index 000000000..eaa6f7508 +--- /dev/null ++++ b/drivers/st/rtc/stm32_rtc.c +@@ -0,0 +1,488 @@ ++/* ++ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define RTC_COMPAT "st,stm32mp1-rtc" ++ ++#define RTC_TR_SU_MASK GENMASK(3, 0) ++#define RTC_TR_ST_MASK GENMASK(6, 4) ++#define RTC_TR_ST_SHIFT 4 ++#define RTC_TR_MNU_MASK GENMASK(11, 8) ++#define RTC_TR_MNU_SHIFT 8 ++#define RTC_TR_MNT_MASK GENMASK(14, 12) ++#define RTC_TR_MNT_SHIFT 12 ++#define RTC_TR_HU_MASK GENMASK(19, 16) ++#define RTC_TR_HU_SHIFT 16 ++#define RTC_TR_HT_MASK GENMASK(21, 20) ++#define RTC_TR_HT_SHIFT 20 ++#define RTC_TR_PM BIT(22) ++ ++#define RTC_DR_DU_MASK GENMASK(3, 0) ++#define RTC_DR_DT_MASK GENMASK(5, 4) ++#define RTC_DR_DT_SHIFT 4 ++#define RTC_DR_MU_MASK GENMASK(11, 8) ++#define RTC_DR_MU_SHIFT 8 ++#define RTC_DR_MT BIT(12) ++#define RTC_DR_MT_SHIFT 12 ++#define RTC_DR_WDU_MASK GENMASK(15, 13) ++#define RTC_DR_WDU_SHIFT 13 ++#define RTC_DR_YU_MASK GENMASK(19, 16) ++#define RTC_DR_YU_SHIFT 16 ++#define RTC_DR_YT_MASK GENMASK(23, 20) ++#define RTC_DR_YT_SHIFT 20 ++ ++#define RTC_SSR_SS_MASK GENMASK(15, 0) ++ ++#define RTC_ICSR_ALRAWF BIT(0) ++#define RTC_ICSR_RSF BIT(5) ++ ++#define RTC_PRER_PREDIV_S_MASK GENMASK(14, 0) ++ ++#define RTC_CR_BYPSHAD BIT(5) ++#define RTC_CR_BYPSHAD_SHIFT 5 ++#define RTC_CR_ALRAE BIT(8) ++#define RTC_CR_ALRAIE BIT(12) ++#define RTC_CR_TAMPTS BIT(25) ++ ++#define RTC_SMCR_TS_DPROT BIT(3) ++ ++#define RTC_TSDR_DU_MASK GENMASK(3, 0) ++#define RTC_TSDR_DU_SHIFT 0 ++#define RTC_TSDR_DT_MASK GENMASK(5, 4) ++#define RTC_TSDR_DT_SHIFT 4 ++#define RTC_TSDR_MU_MASK GENMASK(11, 8) ++#define RTC_TSDR_MU_SHIFT 8 ++ ++#define RTC_ALRMAR_DU_SHIFT 24 ++ ++#define RTC_SR_TSF BIT(3) ++#define RTC_SR_TSOVF BIT(4) ++ ++#define RTC_SCR_CTSF BIT(3) ++#define RTC_SCR_CTSOVF BIT(4) ++ ++#define RTC_WPR_KEY1 0xCA ++#define RTC_WPR_KEY2 0x53 ++#define RTC_WPR_KEY_LOCK 0xFF ++ ++static struct dt_node_info rtc_dev; ++ ++static struct spinlock lock; ++ ++void stm32_rtc_regs_lock(void) ++{ ++ if (stm32mp_lock_available()) { ++ spin_lock(&lock); ++ } ++} ++ ++void stm32_rtc_regs_unlock(void) ++{ ++ if (stm32mp_lock_available()) { ++ spin_unlock(&lock); ++ } ++} ++ ++static void stm32_rtc_write_unprotect(void) ++{ ++ mmio_write_32(rtc_dev.base + RTC_WPR, RTC_WPR_KEY1); ++ mmio_write_32(rtc_dev.base + RTC_WPR, RTC_WPR_KEY2); ++} ++ ++static void stm32_rtc_write_protect(void) ++{ ++ mmio_write_32(rtc_dev.base + RTC_WPR, RTC_WPR_KEY_LOCK); ++} ++ ++/******************************************************************************* ++ * This function gets the BYPSHAD bit value of the RTC_CR register. ++ * It will determine if we need to reset RTC_ISCR.RSF after each RTC calendar ++ * read, and also wait for RTC_ISCR.RSF=1 before next read. ++ * Returns true or false depending on the bit value. ++ ******************************************************************************/ ++static bool stm32_rtc_get_bypshad(void) ++{ ++ return ((mmio_read_32(rtc_dev.base + RTC_CR) & RTC_CR_BYPSHAD) >> ++ RTC_CR_BYPSHAD_SHIFT) != 0U; ++} ++ ++/******************************************************************************* ++ * This function reads the RTC calendar register values. ++ * If shadow registers are not bypassed, then a reset/poll is done. ++ ******************************************************************************/ ++static void stm32_rtc_read_calendar(struct stm32_rtc_calendar *calendar) ++{ ++ bool bypshad = stm32_rtc_get_bypshad(); ++ ++ if (!bypshad) { ++ mmio_clrbits_32((uint32_t)(rtc_dev.base + RTC_ICSR), ++ RTC_ICSR_RSF); ++ while ((mmio_read_32(rtc_dev.base + RTC_ICSR) & RTC_ICSR_RSF) != ++ RTC_ICSR_RSF) { ++ ; ++ } ++ } ++ ++ calendar->ssr = mmio_read_32(rtc_dev.base + RTC_SSR); ++ calendar->tr = mmio_read_32(rtc_dev.base + RTC_TR); ++ calendar->dr = mmio_read_32(rtc_dev.base + RTC_DR); ++} ++ ++/******************************************************************************* ++ * This function fill the rtc_time structure based on rtc_calendar register. ++ ******************************************************************************/ ++static void stm32_rtc_get_time(struct stm32_rtc_calendar *cal, ++ struct stm32_rtc_time *tm) ++{ ++ assert(cal != NULL); ++ assert(tm != NULL); ++ ++ tm->hour = (((cal->tr & RTC_TR_HT_MASK) >> RTC_TR_HT_SHIFT) * 10U) + ++ ((cal->tr & RTC_TR_HU_MASK) >> RTC_TR_HU_SHIFT); ++ ++ if ((cal->tr & RTC_TR_PM) != 0U) { ++ tm->hour += 12U; ++ } ++ ++ tm->min = (((cal->tr & RTC_TR_MNT_MASK) >> RTC_TR_MNT_SHIFT) * 10U) + ++ ((cal->tr & RTC_TR_MNU_MASK) >> RTC_TR_MNU_SHIFT); ++ tm->sec = (((cal->tr & RTC_TR_ST_MASK) >> RTC_TR_ST_SHIFT) * 10U) + ++ (cal->tr & RTC_TR_SU_MASK); ++} ++ ++/******************************************************************************* ++ * This function fill the rtc_time structure with the given date register. ++ ******************************************************************************/ ++static void stm32_rtc_get_date(struct stm32_rtc_calendar *cal, ++ struct stm32_rtc_time *tm) ++{ ++ assert(cal != NULL); ++ assert(tm != NULL); ++ ++ tm->wday = (((cal->dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT)); ++ ++ tm->day = (((cal->dr & RTC_DR_DT_MASK) >> RTC_DR_DT_SHIFT) * 10U) + ++ (cal->dr & RTC_DR_DU_MASK); ++ ++ tm->month = (((cal->dr & RTC_DR_MT) >> RTC_DR_MT_SHIFT) * 10U) + ++ ((cal->dr & RTC_DR_MU_MASK) >> RTC_DR_MU_SHIFT); ++ ++ tm->year = (((cal->dr & RTC_DR_YT_MASK) >> RTC_DR_YT_SHIFT) * 10U) + ++ ((cal->dr & RTC_DR_YU_MASK) >> RTC_DR_YU_SHIFT) + 2000U; ++} ++ ++/******************************************************************************* ++ * This function reads the RTC timestamp register values and update time ++ * structure with the corresponding value. ++ ******************************************************************************/ ++static void stm32_rtc_read_timestamp(struct stm32_rtc_time *time) ++{ ++ assert(time != NULL); ++ ++ struct stm32_rtc_calendar cal_tamp; ++ ++ cal_tamp.tr = mmio_read_32(rtc_dev.base + RTC_TSTR); ++ cal_tamp.dr = mmio_read_32(rtc_dev.base + RTC_TSDR); ++ stm32_rtc_get_time(&cal_tamp, time); ++ stm32_rtc_get_date(&cal_tamp, time); ++} ++ ++/******************************************************************************* ++ * This function gets the RTC calendar register values. ++ * It takes into account the need of reading twice or not, depending on ++ * frequencies previously setted, and the bypass or not of the shadow ++ * registers. This service is exposed externally. ++ ******************************************************************************/ ++void stm32_rtc_get_calendar(struct stm32_rtc_calendar *calendar) ++{ ++ bool read_twice = stm32mp1_rtc_get_read_twice(); ++ ++ stm32_rtc_regs_lock(); ++ stm32mp_clk_enable(rtc_dev.clock); ++ ++ stm32_rtc_read_calendar(calendar); ++ ++ if (read_twice) { ++ uint32_t tr_save = calendar->tr; ++ ++ stm32_rtc_read_calendar(calendar); ++ ++ if (calendar->tr != tr_save) { ++ stm32_rtc_read_calendar(calendar); ++ } ++ } ++ ++ stm32mp_clk_disable(rtc_dev.clock); ++ stm32_rtc_regs_unlock(); ++} ++ ++/******************************************************************************* ++ * This function computes the second fraction in milliseconds. ++ * The returned value is a uint32_t between 0 and 1000. ++ ******************************************************************************/ ++static uint32_t stm32_rtc_get_second_fraction(struct stm32_rtc_calendar *cal) ++{ ++ uint32_t prediv_s = mmio_read_32(rtc_dev.base + RTC_PRER) & ++ RTC_PRER_PREDIV_S_MASK; ++ uint32_t ss = cal->ssr & RTC_SSR_SS_MASK; ++ ++ return ((prediv_s - ss) * 1000U) / (prediv_s + 1U); ++} ++ ++/******************************************************************************* ++ * This function computes the fraction difference between two timestamps. ++ * Here again the returned value is in milliseconds. ++ ******************************************************************************/ ++static unsigned long long stm32_rtc_diff_frac(struct stm32_rtc_calendar *cur, ++ struct stm32_rtc_calendar *ref) ++{ ++ unsigned long long val_r; ++ unsigned long long val_c; ++ ++ val_r = stm32_rtc_get_second_fraction(ref); ++ val_c = stm32_rtc_get_second_fraction(cur); ++ ++ if (val_c >= val_r) { ++ return val_c - val_r; ++ } else { ++ return 1000U - val_r + val_c; ++ } ++} ++ ++/******************************************************************************* ++ * This function computes the time difference between two timestamps. ++ * It includes seconds, minutes and hours. ++ * Here again the returned value is in milliseconds. ++ ******************************************************************************/ ++static unsigned long long stm32_rtc_diff_time(struct stm32_rtc_time *current, ++ struct stm32_rtc_time *ref) ++{ ++ signed long long diff_in_s; ++ signed long long curr_s; ++ signed long long ref_s; ++ ++ curr_s = (signed long long)current->sec + ++ (((signed long long)current->min + ++ (((signed long long)current->hour * 60))) * 60); ++ ++ ref_s = (signed long long)ref->sec + ++ (((signed long long)ref->min + ++ (((signed long long)ref->hour * 60))) * 60); ++ ++ diff_in_s = curr_s - ref_s; ++ if (diff_in_s < 0) { ++ diff_in_s += 24 * 60 * 60; ++ } ++ ++ return (unsigned long long)diff_in_s * 1000U; ++} ++ ++/******************************************************************************* ++ * This function determines if the year is leap or not. ++ * Returned value is true or false. ++ ******************************************************************************/ ++static bool stm32_is_a_leap_year(uint32_t year) ++{ ++ return ((year % 4U) == 0U) && ++ (((year % 100U) != 0U) || ((year % 400U) == 0U)); ++} ++ ++/******************************************************************************* ++ * This function computes the date difference between two timestamps. ++ * It includes days, months, years, with exceptions. ++ * Here again the returned value is in milliseconds. ++ ******************************************************************************/ ++static unsigned long long stm32_rtc_diff_date(struct stm32_rtc_time *current, ++ struct stm32_rtc_time *ref) ++{ ++ uint32_t diff_in_days = 0; ++ uint32_t m; ++ static const uint8_t month_len[NB_MONTHS] = { ++ 31, 28, 31, 30, 31, 30, ++ 31, 31, 30, 31, 30, 31 ++ }; ++ ++ /* Get the number of non-entire month days */ ++ if (current->day >= ref->day) { ++ diff_in_days += current->day - ref->day; ++ } else { ++ diff_in_days += (uint32_t)month_len[ref->month - 1U] - ++ ref->day + current->day; ++ } ++ ++ /* Get the number of entire months, and compute the related days */ ++ if (current->month > (ref->month + 1U)) { ++ for (m = (ref->month + 1U); (m < current->month) && ++ (m < 12U); m++) { ++ diff_in_days += (uint32_t)month_len[m - 1U]; ++ } ++ } ++ ++ if (current->month < (ref->month - 1U)) { ++ for (m = 1U; (m < current->month) && (m < 12U); m++) { ++ diff_in_days += (uint32_t)month_len[m - 1U]; ++ } ++ ++ for (m = (ref->month + 1U); m < 12U; m++) { ++ diff_in_days += (uint32_t)month_len[m - 1U]; ++ } ++ } ++ ++ /* Get complete years */ ++ if (current->year > (ref->year + 1U)) { ++ diff_in_days += (current->year - ref->year - 1U) * 365U; ++ } ++ ++ /* Particular cases: leap years (one day more) */ ++ if (diff_in_days > 0U) { ++ if (current->year == ref->year) { ++ if (stm32_is_a_leap_year(current->year)) { ++ if ((ref->month <= 2U) && ++ (current->month >= 3U) && ++ (current->day <= 28U)) { ++ diff_in_days++; ++ } ++ } ++ } else { ++ uint32_t y; ++ ++ /* Ref year is leap */ ++ if ((stm32_is_a_leap_year(ref->year)) && ++ (ref->month <= 2U) && (ref->day <= 28U)) { ++ diff_in_days++; ++ } ++ ++ /* Current year is leap */ ++ if ((stm32_is_a_leap_year(current->year)) && ++ (current->month >= 3U)) { ++ diff_in_days++; ++ } ++ ++ /* Interleaved years are leap */ ++ for (y = ref->year + 1U; y < current->year; y++) { ++ if (stm32_is_a_leap_year(y)) { ++ diff_in_days++; ++ } ++ } ++ } ++ } ++ ++ return (24ULL * 60U * 60U * 1000U) * (unsigned long long)diff_in_days; ++} ++ ++/******************************************************************************* ++ * This function computes the date difference between two rtc value. ++ * Here again the returned value is in milliseconds. ++ ******************************************************************************/ ++unsigned long long stm32_rtc_diff_calendar(struct stm32_rtc_calendar *cur, ++ struct stm32_rtc_calendar *ref) ++{ ++ unsigned long long diff_in_ms = 0; ++ struct stm32_rtc_time curr_t; ++ struct stm32_rtc_time ref_t; ++ ++ stm32mp_clk_enable(rtc_dev.clock); ++ ++ stm32_rtc_get_date(cur, &curr_t); ++ stm32_rtc_get_date(ref, &ref_t); ++ stm32_rtc_get_time(cur, &curr_t); ++ stm32_rtc_get_time(ref, &ref_t); ++ ++ diff_in_ms += stm32_rtc_diff_frac(cur, ref); ++ diff_in_ms += stm32_rtc_diff_time(&curr_t, &ref_t); ++ diff_in_ms += stm32_rtc_diff_date(&curr_t, &ref_t); ++ ++ stm32mp_clk_disable(rtc_dev.clock); ++ ++ return diff_in_ms; ++} ++ ++/******************************************************************************* ++ * This function fill the RTC timestamp structure. ++ ******************************************************************************/ ++void stm32_rtc_get_timestamp(struct stm32_rtc_time *tamp_ts) ++{ ++ stm32_rtc_regs_lock(); ++ stm32mp_clk_enable(rtc_dev.clock); ++ ++ if ((mmio_read_32(rtc_dev.base + RTC_SR) & RTC_SR_TSF) != 0U) { ++ /* Print timestamp for tamper event */ ++ stm32_rtc_read_timestamp(tamp_ts); ++ mmio_setbits_32(rtc_dev.base + RTC_SCR, RTC_SCR_CTSF); ++ if ((mmio_read_32(rtc_dev.base + RTC_SR) & RTC_SR_TSOVF) != ++ 0U) { ++ /* Overflow detected */ ++ mmio_setbits_32(rtc_dev.base + RTC_SCR, RTC_SCR_CTSOVF); ++ } ++ } ++ ++ stm32mp_clk_disable(rtc_dev.clock); ++ stm32_rtc_regs_unlock(); ++} ++ ++/******************************************************************************* ++ * This function enable the timestamp bit for tamper and secure timestamp ++ * access. ++ ******************************************************************************/ ++void stm32_rtc_set_tamper_timestamp(void) ++{ ++ stm32_rtc_regs_lock(); ++ stm32mp_clk_enable(rtc_dev.clock); ++ ++ stm32_rtc_write_unprotect(); ++ ++ /* Enable tamper timestamper */ ++ mmio_setbits_32(rtc_dev.base + RTC_CR, RTC_CR_TAMPTS); ++ ++ /* Secure Timestamp bit */ ++ mmio_clrbits_32(rtc_dev.base + RTC_SMCR, RTC_SMCR_TS_DPROT); ++ ++ stm32_rtc_write_protect(); ++ ++ stm32mp_clk_disable(rtc_dev.clock); ++ stm32_rtc_regs_unlock(); ++} ++ ++/******************************************************************************* ++ * This function return state of tamper timestamp. ++ ******************************************************************************/ ++bool stm32_rtc_is_timestamp_enable(void) ++{ ++ bool ret; ++ ++ stm32mp_clk_enable(rtc_dev.clock); ++ ++ ret = (mmio_read_32(rtc_dev.base + RTC_CR) & RTC_CR_TAMPTS) != 0U; ++ ++ stm32mp_clk_disable(rtc_dev.clock); ++ ++ return ret; ++} ++ ++/******************************************************************************* ++ * RTC initialisation function. ++ ******************************************************************************/ ++int stm32_rtc_init(void) ++{ ++ int node; ++ ++ node = dt_get_node(&rtc_dev, -1, RTC_COMPAT); ++ if (node < 0) { ++ return node; ++ } ++ ++ return 0; ++} +diff --git a/include/drivers/st/stm32_rtc.h b/include/drivers/st/stm32_rtc.h +new file mode 100644 +index 000000000..128dd2d14 +--- /dev/null ++++ b/include/drivers/st/stm32_rtc.h +@@ -0,0 +1,78 @@ ++/* ++ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef STM32_RTC_H ++#define STM32_RTC_H ++ ++#include ++ ++#define RTC_TR 0x00U ++#define RTC_DR 0x04U ++#define RTC_SSR 0x08U ++#define RTC_ICSR 0x0CU ++#define RTC_PRER 0x10U ++#define RTC_WUTR 0x14U ++#define RTC_CR 0x18U ++#define RTC_SMCR 0x20U ++#define RTC_WPR 0x24U ++#define RTC_CALR 0x28U ++#define RTC_SHIFTR 0x2CU ++#define RTC_TSTR 0x30U ++#define RTC_TSDR 0x34U ++#define RTC_TSSSR 0x38U ++#define RTC_ALRMAR 0x40U ++#define RTC_ALRMASSR 0x44U ++#define RTC_ALRMBR 0x48U ++#define RTC_ALRMBSSR 0x4CU ++#define RTC_SR 0x50U ++#define RTC_SCR 0x5CU ++#define RTC_OR 0x60U ++ ++struct stm32_rtc_calendar { ++ uint32_t ssr; ++ uint32_t tr; ++ uint32_t dr; ++}; ++ ++enum months { ++ JANUARY = 1, ++ FEBRUARY, ++ MARCH, ++ APRIL, ++ MAY, ++ JUNE, ++ JULY, ++ AUGUST, ++ SEPTEMBER, ++ OCTOBER, ++ NOVEMBER, ++ DECEMBER, ++ NB_MONTHS = 12 ++}; ++ ++struct stm32_rtc_time { ++ uint32_t hour; ++ uint32_t min; ++ uint32_t sec; ++ uint32_t wday; ++ uint32_t day; ++ enum months month; ++ uint32_t year; ++}; ++ ++void stm32_rtc_get_calendar(struct stm32_rtc_calendar *calendar); ++unsigned long long stm32_rtc_diff_calendar(struct stm32_rtc_calendar *current, ++ struct stm32_rtc_calendar *ref); ++void stm32_rtc_set_tamper_timestamp(void); ++bool stm32_rtc_is_timestamp_enable(void); ++void stm32_rtc_get_timestamp(struct stm32_rtc_time *tamp_ts); ++int stm32_rtc_init(void); ++ ++/* SMP protection on RTC registers access */ ++void stm32_rtc_regs_lock(void); ++void stm32_rtc_regs_unlock(void); ++ ++#endif /* STM32_RTC_H */ +diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h +index 1ebd39ff7..81ae5d8ae 100644 +--- a/include/drivers/st/stm32mp1_clk.h ++++ b/include/drivers/st/stm32mp1_clk.h +@@ -53,6 +53,8 @@ static inline void stm32mp1_clk_disable_secure(unsigned long id) + + unsigned int stm32mp1_clk_get_refcount(unsigned long id); + ++bool stm32mp1_rtc_get_read_twice(void); ++ + /* SMP protection on RCC registers access */ + void stm32mp1_clk_rcc_regs_lock(void); + void stm32mp1_clk_rcc_regs_unlock(void); +diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +index 4188cc58a..6c7107ca2 100644 +--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk ++++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +@@ -7,6 +7,7 @@ + SP_MIN_WITH_SECURE_FIQ := 1 + + BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \ ++ drivers/st/rtc/stm32_rtc.c \ + plat/st/stm32mp1/sp_min/sp_min_setup.c \ + plat/st/stm32mp1/stm32mp1_pm.c \ + plat/st/stm32mp1/stm32mp1_topology.c +diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c +index e10dfbfc0..ff69358e0 100644 +--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c ++++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c +@@ -20,6 +20,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -147,16 +148,11 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + } + + /******************************************************************************* +- * Initialize the MMU, security and the GIC. ++ * Set security setup in sp_min + ******************************************************************************/ +-void sp_min_platform_setup(void) ++static void stm32mp1_sp_min_security_setup(void) + { +- /* Initialize tzc400 after DDR initialization */ +- stm32mp1_security_setup(); +- +- generic_delay_timer_init(); +- +- stm32mp1_gic_init(); ++ int ret; + + /* Unlock ETZPC securable peripherals */ + #define STM32MP1_ETZPC_BASE 0x5C007000U +@@ -168,6 +164,28 @@ void sp_min_platform_setup(void) + set_gpio_secure_cfg(GPIO_BANK_Z, pin, false); + } + ++ /* Init rtc driver */ ++ ret = stm32_rtc_init(); ++ if (ret < 0) { ++ WARN("RTC driver init error %i\n", ret); ++ } ++} ++ ++/******************************************************************************* ++ * Initialize the MMU, security and the GIC. ++ ******************************************************************************/ ++void sp_min_platform_setup(void) ++{ ++ /* Initialize tzc400 after DDR initialization */ ++ stm32mp1_security_setup(); ++ ++ generic_delay_timer_init(); ++ ++ stm32mp1_gic_init(); ++ ++ /* Update security settings */ ++ stm32mp1_sp_min_security_setup(); ++ + if (stm32_iwdg_init() < 0) { + panic(); + } +-- +2.27.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0005-stm32mp-add-function-to-protect-access-on-PWR-regist.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0005-stm32mp-add-function-to-protect-access-on-PWR-regist.patch new file mode 100644 index 0000000..3fc2cef --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0005-stm32mp-add-function-to-protect-access-on-PWR-regist.patch @@ -0,0 +1,70 @@ +From 4d4214a8dea31d531df6739e6f74005090018faa Mon Sep 17 00:00:00 2001 +From: Yann Gautier +Date: Wed, 24 Apr 2019 13:38:41 +0200 +Subject: [PATCH 5/7] stm32mp: add function to protect access on PWR registers + +In SMP context, we need to add spinlocks to protect against concurrent +accesses on PWR registers. + +Change-Id: I27cb698ffa085eca7b61b042ce5ccaa1fd2daaf4 +Signed-off-by: Yann Gautier +--- + plat/st/common/include/stm32mp_common.h | 4 ++++ + plat/st/common/stm32mp_common.c | 17 +++++++++++++++++ + 2 files changed, 21 insertions(+) + +diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h +index 4f8567979..052402854 100644 +--- a/plat/st/common/include/stm32mp_common.h ++++ b/plat/st/common/include/stm32mp_common.h +@@ -33,6 +33,10 @@ uintptr_t stm32mp_rcc_base(void); + /* Check MMU status to allow spinlock use */ + bool stm32mp_lock_available(void); + ++/* SMP protection on PWR registers access */ ++void stm32mp_pwr_regs_lock(void); ++void stm32mp_pwr_regs_unlock(void); ++ + /* Get IWDG platform instance ID from peripheral IO memory base address */ + uint32_t stm32_iwdg_get_instance(uintptr_t base); + +diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c +index afa87f487..5e7c74b48 100644 +--- a/plat/st/common/stm32mp_common.c ++++ b/plat/st/common/stm32mp_common.c +@@ -12,8 +12,11 @@ + #include + #include + #include ++#include + #include + ++static struct spinlock lock; ++ + uintptr_t plat_get_ns_image_entrypoint(void) + { + return BL33_BASE; +@@ -96,6 +99,20 @@ bool stm32mp_lock_available(void) + return (read_sctlr() & c_m_bits) == c_m_bits; + } + ++void stm32mp_pwr_regs_lock(void) ++{ ++ if (stm32mp_lock_available()) { ++ spin_lock(&lock); ++ } ++} ++ ++void stm32mp_pwr_regs_unlock(void) ++{ ++ if (stm32mp_lock_available()) { ++ spin_unlock(&lock); ++ } ++} ++ + uintptr_t stm32_get_gpio_bank_base(unsigned int bank) + { + if (bank == GPIO_BANK_Z) { +-- +2.27.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0006-ddr-stm32mp1-add-DDR-self-refresh-management.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0006-ddr-stm32mp1-add-DDR-self-refresh-management.patch new file mode 100644 index 0000000..ca1e3c2 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0006-ddr-stm32mp1-add-DDR-self-refresh-management.patch @@ -0,0 +1,801 @@ +From 3e5e9e77b190336b040389d0a5e62bfea7e22ae4 Mon Sep 17 00:00:00 2001 +From: Yann Gautier +Date: Wed, 24 Apr 2019 13:40:04 +0200 +Subject: [PATCH 6/7] ddr: stm32mp1: add DDR self-refresh management + +In order to prepare low power use cases, functions are added to manage +the entry or exit of DDR from self-refresh mode. + +Change-Id: I8a1cbc48d613366fca69b4fc6870e53f8b917598 +Signed-off-by: Yann Gautier +--- + drivers/st/ddr/stm32mp1_ddr.c | 134 +++++- + drivers/st/ddr/stm32mp1_ddr_helpers.c | 472 ++++++++++++++++++++++ + include/drivers/st/stm32mp1_ddr.h | 6 +- + include/drivers/st/stm32mp1_ddr_helpers.h | 9 +- + plat/st/common/stm32mp_dt.c | 2 - + plat/st/stm32mp1/stm32mp1_def.h | 3 + + 6 files changed, 619 insertions(+), 7 deletions(-) + +diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c +index 7d89d027e..f5cffd887 100644 +--- a/drivers/st/ddr/stm32mp1_ddr.c ++++ b/drivers/st/ddr/stm32mp1_ddr.c +@@ -29,6 +29,7 @@ struct reg_desc { + + #define INVALID_OFFSET 0xFFU + ++#define TIMESLOT_US_1US 1U + #define TIMEOUT_US_1S 1000000U + + #define DDRCTL_REG(x, y) \ +@@ -698,6 +699,83 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, + stm32mp1_wait_sw_done_ack(ctl); + } + ++static void stm32mp1_refresh_cmd(struct stm32mp1_ddrctl *ctl) ++{ ++ uint32_t dbgstat; ++ ++ do { ++ dbgstat = mmio_read_32((uintptr_t)&ctl->dbgstat); ++ } while ((dbgstat & DDRCTRL_DBGSTAT_RANK0_REFRESH_BUSY) != 0U); ++ ++ mmio_setbits_32((uintptr_t)&ctl->dbgcmd, DDRCTRL_DBGCMD_RANK0_REFRESH); ++} ++ ++/* Refresh compensation by forcing refresh command ++ * Rule1: Tref should be always < tREFW ? R x tREBW/8 ++ * Rule2: refcomp = RU(Tref/tREFI) = RU(RxTref/tREFW) ++ */ ++static ++void stm32mp1_refresh_compensation(const struct stm32mp1_ddr_config *config, ++ struct stm32mp1_ddrctl *ctl, ++ uint64_t start) ++{ ++ uint32_t tck_ps; ++ uint64_t time_us, tref, trefi, refcomp, i; ++ ++ time_us = timeout_init_us(0) - start; ++ tck_ps = 1000000000U / config->info.speed; ++ if (tck_ps == 0U) { ++ return; ++ } ++ /* ref = refresh time in tck */ ++ tref = time_us * 1000000U / tck_ps; ++ trefi = ((mmio_read_32((uintptr_t)&ctl->rfshtmg) & ++ DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK) ++ >> DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_SHIFT) * 32U; ++ if (trefi == 0U) { ++ return; ++ } ++ ++ /* div round up : number of refresh to compensate */ ++ refcomp = (tref + trefi - 1U) / trefi; ++ ++ for (i = 0; i < refcomp; i++) { ++ stm32mp1_refresh_cmd(ctl); ++ } ++} ++ ++static void stm32mp1_self_refresh_zcal(struct ddr_info *priv, uint32_t zdata) ++{ ++ /* sequence for PUBL I/O Data Retention during Power-Down */ ++ ++ /* 10. Override ZQ calibration with previously (pre-retention) ++ * calibrated values. This is done by writing 1 to ZQ0CRN.ZDEN ++ * and the override data to ZQ0CRN.ZDATA. ++ */ ++ mmio_setbits_32((uintptr_t)&priv->phy->zq0cr0, DDRPHYC_ZQ0CRN_ZDEN); ++ ++ mmio_clrsetbits_32((uintptr_t)&priv->phy->zq0cr0, ++ DDRPHYC_ZQ0CRN_ZDATA_MASK, ++ zdata << DDRPHYC_ZQ0CRN_ZDATA_SHIFT); ++ ++ /* 11. De-assert the PHY_top data retention enable signals ++ * (ret_en or ret_en_i/ret_en_n_i). ++ */ ++ mmio_setbits_32((uintptr_t)(priv->pwr) + PWR_CR3, PWR_CR3_DDRSRDIS); ++ mmio_clrbits_32((uintptr_t)(priv->pwr) + PWR_CR3, PWR_CR3_DDRRETEN); ++ ++ /* 12. Remove ZQ calibration override by writing 0 to ZQ0CRN.ZDEN. */ ++ mmio_clrbits_32((uintptr_t)&priv->phy->zq0cr0, DDRPHYC_ZQ0CRN_ZDEN); ++ ++ /* 13. Trigger ZQ calibration by writing 1 to PIR.INIT ++ * and '1' to PIR.ZCAL ++ */ ++ /* 14. Wait for ZQ calibration to finish by polling a 1 status ++ * on PGSR.IDONE. ++ */ ++ stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_ZCAL); ++} ++ + static int board_ddr_power_init(enum ddr_type ddr_type) + { + if (dt_pmic_status() > 0) { +@@ -710,8 +788,9 @@ static int board_ddr_power_init(enum ddr_type ddr_type) + void stm32mp1_ddr_init(struct ddr_info *priv, + struct stm32mp1_ddr_config *config) + { +- uint32_t pir; ++ uint32_t pir, ddr_reten; + int ret = -EINVAL; ++ uint64_t time; + + if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) { + ret = board_ddr_power_init(STM32MP_DDR3); +@@ -730,6 +809,27 @@ void stm32mp1_ddr_init(struct ddr_info *priv, + VERBOSE("name = %s\n", config->info.name); + VERBOSE("speed = %d kHz\n", config->info.speed); + VERBOSE("size = 0x%x\n", config->info.size); ++ if (config->self_refresh) { ++ VERBOSE("sel-refresh exit (zdata = 0x%x)\n", config->zdata); ++ } ++ ++ /* Check DDR PHY pads retention */ ++ ddr_reten = mmio_read_32((uint32_t)(priv->pwr) + PWR_CR3) & ++ PWR_CR3_DDRRETEN; ++ if (config->self_refresh) { ++ if (ddr_reten == 0U) { ++ VERBOSE("self-refresh aborted: no retention\n"); ++ config->self_refresh = false; ++ } ++ } else { ++ if (ddr_reten != 0U) { ++ VERBOSE("disable DDR PHY retention\n"); ++ mmio_setbits_32((uint32_t)(priv->pwr) + PWR_CR3, ++ PWR_CR3_DDRSRDIS); ++ mmio_clrbits_32((uint32_t)(priv->pwr) + PWR_CR3, ++ PWR_CR3_DDRRETEN); ++ } ++ } + + /* DDR INIT SEQUENCE */ + +@@ -790,6 +890,12 @@ void stm32mp1_ddr_init(struct ddr_info *priv, + set_reg(priv, REG_TIMING, &config->c_timing); + set_reg(priv, REG_MAP, &config->c_map); + ++ /* Keep the controller in self-refresh mode */ ++ if (config->self_refresh) { ++ mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl, ++ DDRCTRL_PWRCTL_SELFREF_SW); ++ } ++ + /* Skip CTRL init, SDRAM init is done by PHY PUBL */ + mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0, + DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK, +@@ -843,8 +949,20 @@ void stm32mp1_ddr_init(struct ddr_info *priv, + pir |= DDRPHYC_PIR_DRAMRST; /* Only for DDR3 */ + } + ++ /* Treat self-refresh exit : hot boot */ ++ if (config->self_refresh) { ++ /* DDR in self refresh mode, remove zcal & reset & init */ ++ pir &= ~(DDRPHYC_PIR_ZCAL & DDRPHYC_PIR_DRAMRST ++ & DDRPHYC_PIR_DRAMINIT); ++ pir |= DDRPHYC_PIR_ZCALBYP; ++ } ++ + stm32mp1_ddrphy_init(priv->phy, pir); + ++ if (config->self_refresh) { ++ stm32mp1_self_refresh_zcal(priv, config->zdata); ++ } ++ + /* + * 6. SET DFIMISC.dfi_init_complete_en to 1 + * Enable quasi-dynamic register programming. +@@ -865,6 +983,13 @@ void stm32mp1_ddr_init(struct ddr_info *priv, + */ + + /* Wait uMCTL2 ready */ ++ ++ /* Trigger self-refresh exit */ ++ if (config->self_refresh) { ++ mmio_clrbits_32((uintptr_t)&priv->ctl->pwrctl, ++ DDRCTRL_PWRCTL_SELFREF_SW); ++ } ++ + stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); + + /* Switch to DLL OFF mode */ +@@ -874,6 +999,8 @@ void stm32mp1_ddr_init(struct ddr_info *priv, + + VERBOSE("DDR DQS training : "); + ++ time = timeout_init_us(0); ++ + /* + * 8. Disable Auto refresh and power down by setting + * - RFSHCTL3.dis_au_refresh = 1 +@@ -898,6 +1025,11 @@ void stm32mp1_ddr_init(struct ddr_info *priv, + /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */ + stm32mp1_ddrphy_idone_wait(priv->phy); + ++ /* Refresh compensation: forcing refresh command */ ++ if (config->self_refresh) { ++ stm32mp1_refresh_compensation(config, priv->ctl, time); ++ } ++ + /* + * 12. set back registers in step 8 to the orginal values if desidered + */ +diff --git a/drivers/st/ddr/stm32mp1_ddr_helpers.c b/drivers/st/ddr/stm32mp1_ddr_helpers.c +index fcb4cfcfd..2071bb2a2 100644 +--- a/drivers/st/ddr/stm32mp1_ddr_helpers.c ++++ b/drivers/st/ddr/stm32mp1_ddr_helpers.c +@@ -6,8 +6,14 @@ + + #include + ++#include ++#include ++#include + #include + #include ++#include ++ ++#define TIMEOUT_500US 500U + + void ddr_enable_clock(void) + { +@@ -22,3 +28,469 @@ void ddr_enable_clock(void) + + stm32mp1_clk_rcc_regs_unlock(); + } ++ ++static void do_sw_handshake(void) ++{ ++ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); ++ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); ++} ++ ++static void do_sw_ack(void) ++{ ++ uint64_t timeout; ++ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); ++ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); ++ ++ timeout = timeout_init_us(TIMEOUT_500US); ++ while ((mmio_read_32(ddrctrl_base + DDRCTRL_SWSTAT) & ++ DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U) { ++ if (timeout_elapsed(timeout)) { ++ panic(); ++ } ++ } ++} ++ ++static int ddr_sw_self_refresh_in(void) ++{ ++ uint64_t timeout; ++ uint32_t stat; ++ uint32_t operating_mode; ++ uint32_t selref_type; ++ uint8_t op_mode_changed = 0; ++ uintptr_t rcc_base = stm32mp_rcc_base(); ++ uintptr_t pwr_base = stm32mp_pwr_base(); ++ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); ++ uintptr_t ddrphyc_base = stm32mp_ddrphyc_base(); ++ ++ stm32mp1_clk_rcc_regs_lock(); ++ ++ mmio_clrbits_32(rcc_base + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); ++ ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ /* Blocks AXI ports from taking anymore transactions */ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PCTRL_0, ++ DDRCTRL_PCTRL_N_PORT_EN); ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PCTRL_1, ++ DDRCTRL_PCTRL_N_PORT_EN); ++ ++ /* Waits unit all AXI ports are idle ++ * Poll PSTAT.rd_port_busy_n = 0 ++ * Poll PSTAT.wr_port_busy_n = 0 ++ */ ++ timeout = timeout_init_us(TIMEOUT_500US); ++ while (mmio_read_32(ddrctrl_base + DDRCTRL_PSTAT)) { ++ if (timeout_elapsed(timeout)) { ++ goto pstat_failed; ++ } ++ } ++ /* SW Self-Refresh entry */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_SELFREF_SW); ++ ++ /* Wait operating mode change in self-refresh mode ++ * with STAT.operating_mode[1:0]==11. ++ * Ensure transition to self-refresh was due to software ++ * by checking also that STAT.selfref_type[1:0]=2. ++ */ ++ timeout = timeout_init_us(TIMEOUT_500US); ++ while (!timeout_elapsed(timeout)) { ++ stat = mmio_read_32(ddrctrl_base + DDRCTRL_STAT); ++ operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK; ++ selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK; ++ ++ if ((operating_mode == DDRCTRL_STAT_OPERATING_MODE_SR) && ++ (selref_type == DDRCTRL_STAT_SELFREF_TYPE_SR)) { ++ op_mode_changed = 1; ++ break; ++ } ++ } ++ ++ if (op_mode_changed == 0U) ++ goto selfref_sw_failed; ++ ++ /* IOs powering down (PUBL registers) */ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR); ++ ++ mmio_clrsetbits_32(ddrphyc_base + DDRPHYC_ACIOCR, ++ DDRPHYC_ACIOCR_CKPDD_MASK, ++ DDRPHYC_ACIOCR_CKPDD_0); ++ ++ mmio_clrsetbits_32(ddrphyc_base + DDRPHYC_ACIOCR, ++ DDRPHYC_ACIOCR_CKPDR_MASK, ++ DDRPHYC_ACIOCR_CKPDR_0); ++ ++ mmio_clrsetbits_32(ddrphyc_base + DDRPHYC_ACIOCR, ++ DDRPHYC_ACIOCR_CSPDD_MASK, ++ DDRPHYC_ACIOCR_CSPDD_0); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); ++ ++ mmio_clrsetbits_32(ddrphyc_base + DDRPHYC_DSGCR, ++ DDRPHYC_DSGCR_ODTPDD_MASK, ++ DDRPHYC_DSGCR_ODTPDD_0); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); ++ ++ mmio_clrsetbits_32(ddrphyc_base + DDRPHYC_DSGCR, ++ DDRPHYC_DSGCR_CKEPDD_MASK, ++ DDRPHYC_DSGCR_CKEPDD_0); ++ ++ /* Disable PZQ cell (PUBL register) */ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); ++ ++ /* Activate sw retention in PWRCTRL */ ++ stm32mp_pwr_regs_lock(); ++ mmio_setbits_32(pwr_base + PWR_CR3, PWR_CR3_DDRRETEN); ++ stm32mp_pwr_regs_unlock(); ++ ++ /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ ++ stm32mp1_clk_rcc_regs_lock(); ++ mmio_setbits_32(rcc_base + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ /* Disable all DLLs: GLITCH window */ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_ACDLLCR, ++ DDRPHYC_ACDLLCR_DLLDIS); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_DX0DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_DX1DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_DX2DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_DX3DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ stm32mp1_clk_rcc_regs_lock(); ++ ++ /* Switch controller clocks (uMCTL2/PUBL) to DLL output clock */ ++ mmio_clrbits_32(rcc_base + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); ++ ++ /* Deactivate all DDR clocks */ ++ mmio_clrbits_32(rcc_base + RCC_DDRITFCR, ++ RCC_DDRITFCR_DDRC1EN | ++ RCC_DDRITFCR_DDRC2EN | ++ RCC_DDRITFCR_DDRCAPBEN | ++ RCC_DDRITFCR_DDRPHYCAPBEN); ++ ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ return 0; ++ ++selfref_sw_failed: ++ /* This bit should be cleared to restore DDR in its previous state */ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_SELFREF_SW); ++ ++pstat_failed: ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PCTRL_0, ++ DDRCTRL_PCTRL_N_PORT_EN); ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PCTRL_1, ++ DDRCTRL_PCTRL_N_PORT_EN); ++ ++ return -1; ++} ++ ++int ddr_sw_self_refresh_exit(void) ++{ ++ uint64_t timeout; ++ uintptr_t rcc_base = stm32mp_rcc_base(); ++ uintptr_t pwr_base = stm32mp_pwr_base(); ++ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); ++ uintptr_t ddrphyc_base = stm32mp_ddrphyc_base(); ++ ++ /* Enable all clocks */ ++ ddr_enable_clock(); ++ ++ do_sw_handshake(); ++ ++ /* Mask dfi_init_complete_en */ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_DFIMISC, ++ DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); ++ ++ do_sw_ack(); ++ ++ /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ ++ stm32mp1_clk_rcc_regs_lock(); ++ mmio_setbits_32(rcc_base + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ /* Enable all DLLs: GLITCH window */ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_ACDLLCR, ++ DDRPHYC_ACDLLCR_DLLDIS); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DX0DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DX1DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DX2DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DX3DLLCR, ++ DDRPHYC_DXNDLLCR_DLLDIS); ++ ++ /* Additional delay to avoid early DLL clock switch */ ++ udelay(10); ++ ++ /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ ++ stm32mp1_clk_rcc_regs_lock(); ++ mmio_clrbits_32(rcc_base + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_ACDLLCR, ++ DDRPHYC_ACDLLCR_DLLSRST); ++ ++ udelay(10); ++ ++ mmio_setbits_32(ddrphyc_base + DDRPHYC_ACDLLCR, ++ DDRPHYC_ACDLLCR_DLLSRST); ++ ++ /* PHY partial init: (DLL lock and ITM reset) */ ++ mmio_write_32(ddrphyc_base + DDRPHYC_PIR, ++ DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | ++ DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_INIT); ++ ++ /* Need to wait at least 10 clock cycles before accessing PGSR */ ++ udelay(1); ++ ++ /* Pool end of init */ ++ timeout = timeout_init_us(TIMEOUT_500US); ++ ++ while ((mmio_read_32(ddrphyc_base + DDRPHYC_PGSR) & ++ DDRPHYC_PGSR_IDONE) == 0U) { ++ if (timeout_elapsed(timeout)) { ++ return -1; ++ } ++ } ++ ++ do_sw_handshake(); ++ ++ /* Unmask dfi_init_complete_en to uMCTL2 */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_DFIMISC, ++ DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); ++ ++ do_sw_ack(); ++ ++ /* Deactivate sw retention in PWR */ ++ stm32mp_pwr_regs_lock(); ++ mmio_clrbits_32(pwr_base + PWR_CR3, PWR_CR3_DDRRETEN); ++ stm32mp_pwr_regs_unlock(); ++ ++ /* Enable PZQ cell (PUBL register) */ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); ++ ++ /* Enable pad drivers */ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_ACIOCR, ++ DDRPHYC_ACIOCR_CKPDD_MASK); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_ACIOCR, ++ DDRPHYC_ACIOCR_CSPDD_MASK); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DSGCR, ++ DDRPHYC_DSGCR_ODTPDD_MASK); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); ++ ++ mmio_clrbits_32(ddrphyc_base + DDRPHYC_DSGCR, ++ DDRPHYC_DSGCR_CKEPDD_MASK); ++ ++ /* Remove selfrefresh */ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_SELFREF_SW); ++ ++ /* Wait operating_mode == normal */ ++ timeout = timeout_init_us(TIMEOUT_500US); ++ while ((mmio_read_32(ddrctrl_base + DDRCTRL_STAT) & ++ DDRCTRL_STAT_OPERATING_MODE_MASK) != ++ DDRCTRL_STAT_OPERATING_MODE_NORMAL) { ++ if (timeout_elapsed(timeout)) { ++ return -1; ++ } ++ } ++ ++ /* AXI ports are no longer blocked from taking transactions */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PCTRL_0, ++ DDRCTRL_PCTRL_N_PORT_EN); ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PCTRL_1, ++ DDRCTRL_PCTRL_N_PORT_EN); ++ ++ stm32mp1_clk_rcc_regs_lock(); ++ ++ mmio_setbits_32(rcc_base + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); ++ ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ return 0; ++} ++ ++int ddr_standby_sr_entry(uint32_t *zq0cr0_zdata) ++{ ++ uintptr_t pwr_base = stm32mp_pwr_base(); ++ uintptr_t ddrphyc_base = stm32mp_ddrphyc_base(); ++ ++ /* Save IOs calibration values */ ++ if (zq0cr0_zdata != NULL) { ++ *zq0cr0_zdata = mmio_read_32(ddrphyc_base + DDRPHYC_ZQ0CR0) & ++ DDRPHYC_ZQ0CRN_ZDATA_MASK; ++ } ++ ++ /* Put DDR in Self-Refresh */ ++ if (ddr_sw_self_refresh_in() != 0) { ++ return -1; ++ } ++ ++ /* Enable I/O retention mode in standby */ ++ stm32mp_pwr_regs_lock(); ++ mmio_setbits_32(pwr_base + PWR_CR3, PWR_CR3_DDRSREN); ++ stm32mp_pwr_regs_unlock(); ++ ++ return 0; ++} ++ ++void ddr_sr_mode_ssr(void) ++{ ++ uintptr_t rcc_ddritfcr = stm32mp_rcc_base() + RCC_DDRITFCR; ++ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); ++ ++ stm32mp1_clk_rcc_regs_lock(); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC1LPEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC2LPEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC1EN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC2EN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRCAPBLPEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRPHYCAPBLPEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRCAPBEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRPHYCAPBEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRPHYCEN); ++ ++ mmio_clrbits_32(rcc_ddritfcr, RCC_DDRITFCR_AXIDCGEN); ++ ++ mmio_clrbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRCKMOD_MASK); ++ ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ /* Disable HW LP interface of uMCTL2 */ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_HWLPCTL, ++ DDRCTRL_HWLPCTL_HW_LP_EN); ++ ++ /* Configure Automatic LP modes of uMCTL2 */ ++ mmio_clrsetbits_32(ddrctrl_base + DDRCTRL_PWRTMG, ++ DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK, ++ DDRCTRL_PWRTMG_SELFREF_TO_X32_0); ++ ++ /* ++ * Disable Clock disable with LP modes ++ * (used in RUN mode for LPDDR2 with specific timing). ++ */ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); ++ ++ /* Disable automatic Self-Refresh mode */ ++ mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_SELFREF_EN); ++} ++ ++void ddr_sr_mode_asr(void) ++{ ++ uintptr_t rcc_ddritfcr = stm32mp_rcc_base() + RCC_DDRITFCR; ++ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); ++ ++ stm32mp1_clk_rcc_regs_lock(); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_AXIDCGEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC1LPEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC2LPEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRPHYCLPEN); ++ ++ mmio_clrsetbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRCKMOD_MASK, ++ RCC_DDRITFCR_DDRCKMOD_ASR1); ++ ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ /* Enable HW LP interface of uMCTL2 */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_HWLPCTL, ++ DDRCTRL_HWLPCTL_HW_LP_EN); ++ ++ /* Configure Automatic LP modes of uMCTL2 */ ++ mmio_clrsetbits_32(ddrctrl_base + DDRCTRL_PWRTMG, ++ DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK, ++ DDRCTRL_PWRTMG_SELFREF_TO_X32_0); ++ ++ /* ++ * Enable Clock disable with LP modes ++ * (used in RUN mode for LPDDR2 with specific timing). ++ */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); ++ ++ /* Enable automatic Self-Refresh for ASR mode */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_SELFREF_EN); ++} ++ ++void ddr_sr_mode_hsr(void) ++{ ++ uintptr_t rcc_ddritfcr = stm32mp_rcc_base() + RCC_DDRITFCR; ++ uintptr_t ddrctrl_base = stm32mp_ddrctrl_base(); ++ ++ stm32mp1_clk_rcc_regs_lock(); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_AXIDCGEN); ++ ++ mmio_clrbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC1LPEN); ++ ++ mmio_clrbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRC2LPEN); ++ ++ mmio_setbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRPHYCLPEN); ++ ++ mmio_clrsetbits_32(rcc_ddritfcr, RCC_DDRITFCR_DDRCKMOD_MASK, ++ RCC_DDRITFCR_DDRCKMOD_HSR1); ++ ++ stm32mp1_clk_rcc_regs_unlock(); ++ ++ /* Enable HW LP interface of uMCTL2 */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_HWLPCTL, ++ DDRCTRL_HWLPCTL_HW_LP_EN); ++ ++ /* Configure Automatic LP modes of uMCTL2 */ ++ mmio_clrsetbits_32(ddrctrl_base + DDRCTRL_PWRTMG, ++ DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK, ++ DDRCTRL_PWRTMG_SELFREF_TO_X32_0); ++ ++ /* ++ * Enable Clock disable with LP modes ++ * (used in RUN mode for LPDDR2 with specific timing). ++ */ ++ mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, ++ DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); ++} +diff --git a/include/drivers/st/stm32mp1_ddr.h b/include/drivers/st/stm32mp1_ddr.h +index 4ab37d6b4..f52609f66 100644 +--- a/include/drivers/st/stm32mp1_ddr.h ++++ b/include/drivers/st/stm32mp1_ddr.h +@@ -8,9 +8,6 @@ + #define STM32MP1_DDR_H + + #include +-#include +- +-#define DT_DDR_COMPAT "st,stm32mp1-ddr" + + struct stm32mp1_ddr_size { + uint64_t base; +@@ -166,9 +163,12 @@ struct stm32mp1_ddr_config { + struct stm32mp1_ddrphy_reg p_reg; + struct stm32mp1_ddrphy_timing p_timing; + struct stm32mp1_ddrphy_cal p_cal; ++ bool self_refresh; ++ uint32_t zdata; + }; + + int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed); + void stm32mp1_ddr_init(struct ddr_info *priv, + struct stm32mp1_ddr_config *config); ++ + #endif /* STM32MP1_DDR_H */ +diff --git a/include/drivers/st/stm32mp1_ddr_helpers.h b/include/drivers/st/stm32mp1_ddr_helpers.h +index 38f24152a..80bf9de6f 100644 +--- a/include/drivers/st/stm32mp1_ddr_helpers.h ++++ b/include/drivers/st/stm32mp1_ddr_helpers.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved ++ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -7,6 +7,13 @@ + #ifndef STM32MP1_DDR_HELPERS_H + #define STM32MP1_DDR_HELPERS_H + ++#include ++ + void ddr_enable_clock(void); ++int ddr_sw_self_refresh_exit(void); ++int ddr_standby_sr_entry(uint32_t *zq0cr0_zdata); ++void ddr_sr_mode_ssr(void); ++void ddr_sr_mode_asr(void); ++void ddr_sr_mode_hsr(void); + + #endif /* STM32MP1_DDR_HELPERS_H */ +diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c +index 17da4904a..863c2cc94 100644 +--- a/plat/st/common/stm32mp_dt.c ++++ b/plat/st/common/stm32mp_dt.c +@@ -13,8 +13,6 @@ + + #include + #include +-#include +-#include + + #include + +diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h +index a40852bde..dbe62f09d 100644 +--- a/plat/st/stm32mp1/stm32mp1_def.h ++++ b/plat/st/stm32mp1/stm32mp1_def.h +@@ -17,6 +17,8 @@ + #ifndef __ASSEMBLER__ + #include + #include ++#include ++#include + + #include + #include +@@ -336,6 +338,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx) + * Device Tree defines + ******************************************************************************/ + #define DT_BSEC_COMPAT "st,stm32mp15-bsec" ++#define DT_DDR_COMPAT "st,stm32mp1-ddr" + #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" + #define DT_PWR_COMPAT "st,stm32mp1-pwr" + #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" +-- +2.27.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0007-stm32mp1-add-low-power-management.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0007-stm32mp1-add-low-power-management.patch new file mode 100644 index 0000000..5cb331b --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0007-stm32mp1-add-low-power-management.patch @@ -0,0 +1,2889 @@ +From 89dcbaa9307e004bd4f009de6554cab2632a9c15 Mon Sep 17 00:00:00 2001 +From: Yann Gautier +Date: Mon, 20 May 2019 19:20:30 +0200 +Subject: [PATCH 7/7] stm32mp1: add low power management + +Change-Id: I8e0ba794e5ded1290fb83fe8d43ce54d4dc0e320 +Signed-off-by: Yann Gautier +--- + drivers/st/ddr/stm32mp1_ram.c | 92 ++- + drivers/st/pmic/stm32mp_pmic.c | 95 +++ + drivers/st/pmic/stpmic1.c | 52 ++ + fdts/stm32mp157a-dk1.dts | 136 ++++ + fdts/stm32mp157c-ed1.dts | 150 +++++ + include/drivers/st/stm32mp1_pwr.h | 21 +- + include/drivers/st/stm32mp_pmic.h | 2 + + include/drivers/st/stpmic1.h | 4 + + include/dt-bindings/power/stm32mp1-power.h | 19 + + plat/st/stm32mp1/bl2_plat_setup.c | 33 + + plat/st/stm32mp1/include/boot_api.h | 105 ++- + plat/st/stm32mp1/include/platform_def.h | 2 + + plat/st/stm32mp1/include/stm32mp1_context.h | 13 +- + plat/st/stm32mp1/include/stm32mp1_low_power.h | 19 + + .../stm32mp1/include/stm32mp1_power_config.h | 19 + + plat/st/stm32mp1/include/stm32mp1_private.h | 3 + + plat/st/stm32mp1/plat_image_load.c | 63 +- + plat/st/stm32mp1/platform.mk | 4 + + plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk | 4 + + plat/st/stm32mp1/sp_min/sp_min_setup.c | 79 ++- + plat/st/stm32mp1/stm32mp1_context.c | 199 ++++++ + plat/st/stm32mp1/stm32mp1_def.h | 4 + + plat/st/stm32mp1/stm32mp1_low_power.c | 327 ++++++++++ + plat/st/stm32mp1/stm32mp1_pm.c | 88 ++- + plat/st/stm32mp1/stm32mp1_power_config.c | 130 ++++ + plat/st/stm32mp1/stm32mp1_private.c | 39 ++ + .../stm32mp1/stm32mp1_shared_resources.c.bak | 597 ++++++++++++++++++ + 27 files changed, 2268 insertions(+), 31 deletions(-) + create mode 100644 include/dt-bindings/power/stm32mp1-power.h + create mode 100644 plat/st/stm32mp1/include/stm32mp1_low_power.h + create mode 100644 plat/st/stm32mp1/include/stm32mp1_power_config.h + create mode 100644 plat/st/stm32mp1/stm32mp1_low_power.c + create mode 100644 plat/st/stm32mp1/stm32mp1_power_config.c + create mode 100644 plat/st/stm32mp1/stm32mp1_shared_resources.c.bak + +diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c +index 4ae55fcc7..f94980c94 100644 +--- a/drivers/st/ddr/stm32mp1_ram.c ++++ b/drivers/st/ddr/stm32mp1_ram.c +@@ -49,6 +49,26 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) + return 0; + } + ++/******************************************************************************* ++ * This function tests a simple read/write access to the DDR. ++ * Note that the previous content is restored after test. ++ * Returns 0 if success, and address value else. ++ ******************************************************************************/ ++static uint32_t ddr_test_rw_access(void) ++{ ++ uint32_t saved_value = mmio_read_32(STM32MP_DDR_BASE); ++ ++ mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); ++ ++ if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { ++ return (uint32_t)STM32MP_DDR_BASE; ++ } ++ ++ mmio_write_32(STM32MP_DDR_BASE, saved_value); ++ ++ return 0; ++} ++ + /******************************************************************************* + * This function tests the DDR data bus wiring. + * This is inspired from the Data Bus Test algorithm written by Michael Barr +@@ -168,8 +188,12 @@ static int stm32mp1_ddr_setup(void) + int ret; + struct stm32mp1_ddr_config config; + int node, len; +- uint32_t uret, idx; ++ uint32_t magic, uret, idx; + void *fdt; ++ uint32_t bkpr_core1_addr = ++ tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); ++ uint32_t bkpr_core1_magic = ++ tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); + + #define PARAM(x, y) \ + { \ +@@ -237,6 +261,18 @@ static int stm32mp1_ddr_setup(void) + } + } + ++ config.self_refresh = false; ++ ++ stm32mp_clk_enable(RTCAPB); ++ ++ magic = mmio_read_32(bkpr_core1_magic); ++ if (magic == BOOT_API_A7_CORE0_MAGIC_NUMBER) { ++ config.self_refresh = true; ++ config.zdata = stm32_get_zdata_from_context(); ++ } ++ ++ stm32mp_clk_disable(RTCAPB); ++ + /* Disable axidcg clock gating during init */ + mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); + +@@ -245,6 +281,14 @@ static int stm32mp1_ddr_setup(void) + /* Enable axidcg clock gating */ + mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); + ++ /* check if DDR content is lost (self-refresh aborted) */ ++ if ((magic == BOOT_API_A7_CORE0_MAGIC_NUMBER) && !config.self_refresh) { ++ /* clear Backup register */ ++ mmio_write_32(bkpr_core1_addr, 0); ++ /* clear magic number */ ++ mmio_write_32(bkpr_core1_magic, 0); ++ } ++ + priv->info.size = config.info.size; + + VERBOSE("%s : ram size(%x, %x)\n", __func__, +@@ -253,25 +297,37 @@ static int stm32mp1_ddr_setup(void) + write_sctlr(read_sctlr() & ~SCTLR_C_BIT); + dcsw_op_all(DC_OP_CISW); + +- uret = ddr_test_data_bus(); +- if (uret != 0U) { +- ERROR("DDR data bus test: can't access memory @ 0x%x\n", +- uret); +- panic(); +- } ++ if (config.self_refresh) { ++ uret = ddr_test_rw_access(); ++ if (uret != 0U) { ++ ERROR("DDR rw test: Can't access memory @ 0x%x\n", ++ uret); ++ panic(); ++ } + +- uret = ddr_test_addr_bus(); +- if (uret != 0U) { +- ERROR("DDR addr bus test: can't access memory @ 0x%x\n", +- uret); +- panic(); +- } ++ /* Restore area overwritten by training */ ++ stm32_restore_ddr_training_area(); ++ } else { ++ uret = ddr_test_data_bus(); ++ if (uret != 0U) { ++ ERROR("DDR data bus test: can't access memory @ 0x%x\n", ++ uret); ++ panic(); ++ } + +- uret = ddr_check_size(); +- if (uret < config.info.size) { +- ERROR("DDR size: 0x%x does not match DT config: 0x%x\n", +- uret, config.info.size); +- panic(); ++ uret = ddr_test_addr_bus(); ++ if (uret != 0U) { ++ ERROR("DDR addr bus test: can't access memory @ 0x%x\n", ++ uret); ++ panic(); ++ } ++ ++ uret = ddr_check_size(); ++ if (uret < config.info.size) { ++ ERROR("DDR size: 0x%x does not match DT config: 0x%x\n", ++ uret, config.info.size); ++ panic(); ++ } + } + + write_sctlr(read_sctlr() | SCTLR_C_BIT); +diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c +index 9e9dddc4d..dc44b735f 100644 +--- a/drivers/st/pmic/stm32mp_pmic.c ++++ b/drivers/st/pmic/stm32mp_pmic.c +@@ -27,6 +27,8 @@ + #define STPMIC1_BUCK_OUTPUT_SHIFT 2 + #define STPMIC1_BUCK3_1V8 (39U << STPMIC1_BUCK_OUTPUT_SHIFT) + ++#define REGULATOR_MODE_STANDBY 8U ++ + #define STPMIC1_DEFAULT_START_UP_DELAY_MS 1 + + static struct i2c_handle_s i2c_handle; +@@ -174,6 +176,99 @@ int dt_pmic_configure_boot_on_regulators(void) + return 0; + } + ++int dt_pmic_set_lp_config(const char *node_name) ++{ ++ int pmic_node, regulators_node, regulator_node; ++ int status; ++ void *fdt; ++ ++ if (node_name == NULL) { ++ return 0; ++ } ++ ++ if (fdt_get_address(&fdt) == 0) { ++ return -ENOENT; ++ } ++ ++ pmic_node = dt_get_pmic_node(fdt); ++ if (pmic_node < 0) { ++ return -FDT_ERR_NOTFOUND; ++ } ++ ++ status = stpmic1_powerctrl_on(); ++ if (status != 0) { ++ return status; ++ }; ++ ++ regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators"); ++ ++ fdt_for_each_subnode(regulator_node, fdt, regulators_node) { ++ const fdt32_t *cuint; ++ const char *reg_name; ++ int regulator_state_node; ++ ++ /* ++ * First, copy active configuration (Control register) to ++ * PWRCTRL Control register, even if regulator_state_node ++ * does not exist. ++ */ ++ reg_name = fdt_get_name(fdt, regulator_node, NULL); ++ status = stpmic1_lp_copy_reg(reg_name); ++ if (status != 0) { ++ return status; ++ } ++ ++ /* Then apply configs from regulator_state_node */ ++ regulator_state_node = fdt_subnode_offset(fdt, ++ regulator_node, ++ node_name); ++ if (regulator_state_node <= 0) { ++ continue; ++ } ++ ++ if (fdt_getprop(fdt, regulator_state_node, ++ "regulator-on-in-suspend", NULL) != NULL) { ++ status = stpmic1_lp_reg_on_off(reg_name, 1); ++ if (status != 0) { ++ return status; ++ } ++ } ++ ++ if (fdt_getprop(fdt, regulator_state_node, ++ "regulator-off-in-suspend", NULL) != NULL) { ++ status = stpmic1_lp_reg_on_off(reg_name, 0); ++ if (status != 0) { ++ return status; ++ } ++ } ++ ++ cuint = fdt_getprop(fdt, regulator_state_node, ++ "regulator-suspend-microvolt", NULL); ++ if (cuint != NULL) { ++ uint16_t voltage = (uint16_t)(fdt32_to_cpu(*cuint) / ++ 1000U); ++ ++ status = stpmic1_lp_set_voltage(reg_name, voltage); ++ if (status != 0) { ++ return status; ++ } ++ } ++ ++ cuint = fdt_getprop(fdt, regulator_state_node, ++ "regulator-mode", NULL); ++ if (cuint != NULL) { ++ if (fdt32_to_cpu(*cuint) == REGULATOR_MODE_STANDBY) { ++ status = stpmic1_lp_set_mode(reg_name, 1); ++ if (status != 0) { ++ return status; ++ } ++ } ++ } ++ } ++ ++ return 0; ++} ++ + bool initialize_pmic_i2c(void) + { + int ret; +diff --git a/drivers/st/pmic/stpmic1.c b/drivers/st/pmic/stpmic1.c +index 999963054..51754fc3b 100644 +--- a/drivers/st/pmic/stpmic1.c ++++ b/drivers/st/pmic/stpmic1.c +@@ -648,6 +648,58 @@ int stpmic1_regulator_mask_reset_set(const char *name) + regul->mask_reset); + } + ++/* Low-power functions */ ++int stpmic1_lp_copy_reg(const char *name) ++{ ++ uint8_t val; ++ int status; ++ const struct regul_struct *regul = get_regulator_data(name); ++ ++ status = stpmic1_register_read(regul->control_reg, &val); ++ if (status != 0) { ++ return status; ++ } ++ ++ return stpmic1_register_write(regul->low_power_reg, val); ++} ++ ++int stpmic1_lp_reg_on_off(const char *name, uint8_t enable) ++{ ++ const struct regul_struct *regul = get_regulator_data(name); ++ ++ return stpmic1_register_update(regul->low_power_reg, enable, ++ LDO_BUCK_ENABLE_MASK); ++} ++ ++int stpmic1_lp_set_mode(const char *name, uint8_t hplp) ++{ ++ const struct regul_struct *regul = get_regulator_data(name); ++ ++ return stpmic1_register_update(regul->low_power_reg, ++ hplp << LDO_BUCK_HPLP_SHIFT, ++ LDO_BUCK_HPLP_ENABLE_MASK); ++} ++ ++int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts) ++{ ++ uint8_t voltage_index = voltage_to_index(name, millivolts); ++ const struct regul_struct *regul = get_regulator_data(name); ++ uint8_t mask; ++ ++ /* Voltage can be set for buck or ldo (except ldo4) regulators */ ++ if (strncmp(name, "buck", 4) == 0) { ++ mask = BUCK_VOLTAGE_MASK; ++ } else if ((strncmp(name, "ldo", 3) == 0) && ++ (strncmp(name, "ldo4", 4) != 0)) { ++ mask = LDO_VOLTAGE_MASK; ++ } else { ++ return 0; ++ } ++ ++ return stpmic1_register_update(regul->low_power_reg, voltage_index << 2, ++ mask); ++} ++ + int stpmic1_regulator_voltage_get(const char *name) + { + const struct regul_struct *regul = get_regulator_data(name); +diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts +index 78681b0ba..2eced8f53 100644 +--- a/fdts/stm32mp157a-dk1.dts ++++ b/fdts/stm32mp157a-dk1.dts +@@ -192,6 +192,7 @@ + + /* ATF Specific */ + #include ++#include + #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" + #include "stm32mp157c-security.dtsi" + +@@ -309,3 +310,138 @@ + secure-status = "okay"; + }; + }; ++ ++&pwr { ++ system_suspend_supported_soc_modes = < ++ STM32_PM_CSLEEP_RUN ++ STM32_PM_CSTOP_ALLOW_LP_STOP ++ STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR ++ >; ++ ++ system_off_soc_mode = ; ++}; ++ ++/* Low-power states of regulators */ ++&vddcore { ++ lp-stop { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1200000>; ++ }; ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdd_ddr { ++ lp-stop { ++ regulator-suspend-microvolt = <1350000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-suspend-microvolt = <1350000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdd { ++ lp-stop { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++}; ++ ++&v3v3 { ++ lp-stop { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&v1v8_audio { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&v3v3_hdmi { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vtt_ddr { ++ lp-stop { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdd_usb { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdda { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&v1v2_hdmi { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vref_ddr { ++ lp-stop { ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; +diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts +index 779492552..d766cc6a8 100644 +--- a/fdts/stm32mp157c-ed1.dts ++++ b/fdts/stm32mp157c-ed1.dts +@@ -196,6 +196,7 @@ + + /* ATF Specific */ + #include ++#include + #include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" + #include "stm32mp157c-security.dtsi" + +@@ -315,3 +316,152 @@ + secure-status = "okay"; + }; + }; ++ ++&pwr { ++ system_suspend_supported_soc_modes = < ++ STM32_PM_CSLEEP_RUN ++ STM32_PM_CSTOP_ALLOW_LP_STOP ++ STM32_PM_CSTOP_ALLOW_LPLV_STOP ++ STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR ++ >; ++ system_off_soc_mode = ; ++}; ++ ++/* Low-power states of regulators */ ++&vddcore { ++ lp-stop { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1200000>; ++ }; ++ lplv-stop { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdd_ddr { ++ lp-stop { ++ regulator-suspend-microvolt = <1350000>; ++ regulator-on-in-suspend; ++ }; ++ lplv-stop { ++ regulator-suspend-microvolt = <1350000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-suspend-microvolt = <1350000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdd { ++ lp-stop { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ lplv-stop { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-suspend-microvolt = <3300000>; ++ regulator-on-in-suspend; ++ }; ++}; ++ ++&v3v3 { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdda { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&v2v8 { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vtt_ddr { ++ lp-stop { ++ regulator-off-in-suspend; ++ }; ++ lplv-stop { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdd_usb { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vdd_sd { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&v1v8 { ++ standby-ddr-sr { ++ regulator-off-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; ++ ++&vref_ddr { ++ lp-stop { ++ regulator-on-in-suspend; ++ }; ++ lplv-stop { ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-sr { ++ regulator-on-in-suspend; ++ }; ++ standby-ddr-off { ++ regulator-off-in-suspend; ++ }; ++}; +diff --git a/include/drivers/st/stm32mp1_pwr.h b/include/drivers/st/stm32mp1_pwr.h +index e17df44fb..9b662f2d1 100644 +--- a/include/drivers/st/stm32mp1_pwr.h ++++ b/include/drivers/st/stm32mp1_pwr.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved ++ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -13,20 +13,39 @@ + #define PWR_CR2 U(0x08) + #define PWR_CR3 U(0x0C) + #define PWR_MPUCR U(0x10) ++#define PWR_MCUCR U(0x14) + #define PWR_WKUPCR U(0x20) + #define PWR_MPUWKUPENR U(0x28) + ++#define PWR_OFFSET_MASK GENMASK(9, 0) ++ + #define PWR_CR1_LPDS BIT(0) + #define PWR_CR1_LPCFG BIT(1) + #define PWR_CR1_LVDS BIT(2) + #define PWR_CR1_DBP BIT(8) + ++#define PWR_CR2_BREN BIT(0) ++#define PWR_CR2_RREN BIT(1) ++#define PWR_CR2_BRRDY BIT(16) ++#define PWR_CR2_RRRDY BIT(17) ++ ++#define PWR_CR3_VBE BIT(8) ++#define PWR_CR3_VBRS BIT(9) + #define PWR_CR3_DDRSREN BIT(10) + #define PWR_CR3_DDRSRDIS BIT(11) + #define PWR_CR3_DDRRETEN BIT(12) ++#define PWR_CR3_USB33DEN BIT(24) ++#define PWR_CR3_REG18EN BIT(28) ++#define PWR_CR3_REG11EN BIT(30) + + #define PWR_MPUCR_PDDS BIT(0) + #define PWR_MPUCR_CSTDBYDIS BIT(3) + #define PWR_MPUCR_CSSF BIT(9) + ++#define PWR_MCUCR_PDDS BIT(0) ++ ++#define PWR_WKUPCR_MASK GENMASK(27, 16) | GENMASK(13, 8) | GENMASK(5, 0) ++ ++#define PWR_MPUWKUPENR_MASK GENMASK(5, 0) ++ + #endif /* STM32MP1_PWR_H */ +diff --git a/include/drivers/st/stm32mp_pmic.h b/include/drivers/st/stm32mp_pmic.h +index 984cd6014..f5810f38c 100644 +--- a/include/drivers/st/stm32mp_pmic.h ++++ b/include/drivers/st/stm32mp_pmic.h +@@ -27,6 +27,8 @@ int dt_pmic_status(void); + */ + int dt_pmic_configure_boot_on_regulators(void); + ++int dt_pmic_set_lp_config(const char *node_name); ++ + /* + * initialize_pmic_i2c - Initialize I2C for the PMIC control + * +diff --git a/include/drivers/st/stpmic1.h b/include/drivers/st/stpmic1.h +index f7e293b18..e4ceea5e9 100644 +--- a/include/drivers/st/stpmic1.h ++++ b/include/drivers/st/stpmic1.h +@@ -161,6 +161,10 @@ int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts); + int stpmic1_regulator_voltage_get(const char *name); + int stpmic1_regulator_pull_down_set(const char *name); + int stpmic1_regulator_mask_reset_set(const char *name); ++int stpmic1_lp_copy_reg(const char *name); ++int stpmic1_lp_reg_on_off(const char *name, uint8_t enable); ++int stpmic1_lp_set_mode(const char *name, uint8_t hplp); ++int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts); + void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr); + + int stpmic1_get_version(unsigned long *version); +diff --git a/include/dt-bindings/power/stm32mp1-power.h b/include/dt-bindings/power/stm32mp1-power.h +new file mode 100644 +index 000000000..d588dd71f +--- /dev/null ++++ b/include/dt-bindings/power/stm32mp1-power.h +@@ -0,0 +1,19 @@ ++/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ ++/* ++ * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved ++ * Author: Yann Gautier for STMicroelectronics. ++ */ ++ ++#ifndef DT_BINDINGS_STM32MP1_POWER_H ++#define DT_BINDINGS_STM32MP1_POWER_H ++ ++#define STM32_PM_CSLEEP_RUN 0 ++#define STM32_PM_CSTOP_ALLOW_STOP 1 ++#define STM32_PM_CSTOP_ALLOW_LP_STOP 2 ++#define STM32_PM_CSTOP_ALLOW_LPLV_STOP 3 ++#define STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR 4 ++#define STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF 5 ++#define STM32_PM_SHUTDOWN 6 ++#define STM32_PM_MAX_SOC_MODE 7 ++ ++#endif /* DT_BINDINGS_STM32MP1_POWER_H */ +diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c +index d9e29b4e8..c729c0238 100644 +--- a/plat/st/stm32mp1/bl2_plat_setup.c ++++ b/plat/st/stm32mp1/bl2_plat_setup.c +@@ -31,6 +31,8 @@ + #include + #include + ++#define PWRLP_TEMPO_5_HSI 5 ++ + static struct console_stm32 console; + static struct stm32mp_auth_ops stm32mp1_auth_ops; + +@@ -160,6 +162,10 @@ void bl2_el3_plat_arch_setup(void) + uint32_t clk_rate; + uintptr_t pwr_base; + uintptr_t rcc_base; ++ uint32_t bkpr_core1_magic = ++ tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); ++ uint32_t bkpr_core1_addr = ++ tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); + + mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, + BL_CODE_END - BL_CODE_BASE, +@@ -204,6 +210,11 @@ void bl2_el3_plat_arch_setup(void) + pwr_base = stm32mp_pwr_base(); + rcc_base = stm32mp_rcc_base(); + ++ /* Clear Stop Request bits to correctly manage low-power exit */ ++ mmio_write_32(rcc_base + RCC_MP_SREQCLRR, ++ (uint32_t)(RCC_MP_SREQCLRR_STPREQ_P0 | ++ RCC_MP_SREQCLRR_STPREQ_P1)); ++ + /* + * Disable the backup domain write protection. + * The protection is enable at each reset by hardware +@@ -215,6 +226,12 @@ void bl2_el3_plat_arch_setup(void) + ; + } + ++ /* ++ * Configure Standby mode available for MCU by default ++ * and allow to switch in standby SoC in all case ++ */ ++ mmio_setbits_32(pwr_base + PWR_MCUCR, PWR_MCUCR_PDDS); ++ + if (bsec_probe() != 0) { + panic(); + } +@@ -231,9 +248,25 @@ void bl2_el3_plat_arch_setup(void) + mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); + } + ++ /* Wait 5 HSI periods before re-enabling PLLs after STOP modes */ ++ mmio_clrsetbits_32(rcc_base + RCC_PWRLPDLYCR, ++ RCC_PWRLPDLYCR_PWRLP_DLY_MASK, ++ PWRLP_TEMPO_5_HSI); ++ ++ /* Disable retention and backup RAM content after standby */ ++ mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | PWR_CR2_RREN); ++ + /* Disable MCKPROT */ + mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); + ++ if ((boot_context->boot_action != ++ BOOT_API_CTX_BOOT_ACTION_WAKEUP_CSTANDBY) && ++ (boot_context->boot_action != ++ BOOT_API_CTX_BOOT_ACTION_WAKEUP_STANDBY)) { ++ mmio_write_32(bkpr_core1_addr, 0); ++ mmio_write_32(bkpr_core1_magic, 0); ++ } ++ + generic_delay_timer_init(); + + if (stm32mp1_clk_probe() < 0) { +diff --git a/plat/st/stm32mp1/include/boot_api.h b/plat/st/stm32mp1/include/boot_api.h +index 2284970fa..6088b3701 100644 +--- a/plat/st/stm32mp1/include/boot_api.h ++++ b/plat/st/stm32mp1/include/boot_api.h +@@ -10,6 +10,90 @@ + #include + #include + ++/* ++ * Exported constants ++ */ ++ ++/* ++ * Boot Context related definitions ++ */ ++ ++/* ++ * Possible value of boot context field 'boot_action' ++ */ ++/* Boot action is Process Cold Boot */ ++#define BOOT_API_CTX_BOOT_ACTION_COLD_BOOT_PROCESS 0x09U ++/* Boot action is Process Wakeup from CSTANDBY */ ++#define BOOT_API_CTX_BOOT_ACTION_WAKEUP_CSTANDBY 0x0AU ++/* Boot action is Process Wakeup from STANDBY */ ++#define BOOT_API_CTX_BOOT_ACTION_WAKEUP_STANDBY 0x0BU ++/* Boot action is Process Engineering Boot */ ++#define BOOT_API_CTX_BOOT_ACTION_ENGI_BOOT 0x0CU ++ ++#define BOOT_API_CTX_BOOT_ACTION_MPU_CORE0_RESET_PROCESS 0x0F ++ ++/* ++ * Possible value of boot context field 'stby_exit_status' ++ */ ++ ++/* The boot reason is not a STANDBY Exit reason */ ++#define BOOT_API_CTX_STBY_EXIT_STATUS_NO_STANDBY 0x00 ++ ++/* STANDBY Exit with MPU_BEN=1, MCU_BEN=0 */ ++#define BOOT_API_CTX_STBY_EXIT_STATUS_WKUP_MPU_ONLY 0x01 ++ ++/* ++ * STANDBY Exit with MPU_BEN=1, MCU_BEN=1, MPU will go for cold boot ++ * MCU restarted by bootROM ++ */ ++#define BOOT_API_CTX_STBY_EXIT_STATUS_WKUP_ALL_CORES 0x02 ++ ++/* ++ * STANDBY Exit with MPU_BEN=1, MCU_BEN=1, MPU will go for cold boot ++ * but MCU restart aborted (code integrity check) : have not been restarted ++ * by bootROM ++ */ ++#define BOOT_API_CTX_STBY_EXIT_STATUS_WKUP_ALL_CORES_MCU_ABT 0x03 ++ ++/* ++ * STANDBY Exit with MPU_BEN=0, MCU_BEN=1, MPU gone to CSTANDBY, ++ * MCU restarted correctly by bootROM ++ * This value should never be read by FSBL, because not executed in that case ++ */ ++#define BOOT_API_CTX_STBY_EXIT_STATUS_WKUP_MCU_ONLY 0x04 ++ ++/* ++ * STANDBY Exit with MPU_BEN=0, MCU_BEN=1, MCU restart aborted ++ * due code integrity check, then MPU will go for cold boot despite ++ * was not planned initially ++ */ ++#define BOOT_API_CTX_STBY_EXIT_STATUS_WKUP_MCU_ONLY_MCU_ABT 0x05 ++ ++/* ++ * STANDBY Exit with MPU_BEN=1, MCU_BEN=1, MCU restart aborted ++ * due to MCU security perimeter issue ++ */ ++#define \ ++BOOT_API_CTX_STBY_EXIT_STATUS_WKUP_ALL_CORES_MCU_ABT_SEC_PERIMETER_ISSUE 0x06 ++ ++/* ++ * STANDBY Exit with MPU_BEN=0, MCU_BEN=1, MCU restart aborted ++ * due to MCU security perimeter issue, then MPU will go for cold boot ++ * despite was not planned initially ++ */ ++#define \ ++BOOT_API_CTX_STBY_EXIT_STATUS_WKUP_MCU_ONLY_MCU_ABT_SEC_PERIMETER_ISSUE 0x07 ++ ++/* ++ * Possible value of boot context field 'cstby_exit_status' ++ */ ++/* The boot reason is not a CSTANDBY Exit reason */ ++#define BOOT_API_CTX_CSTBY_EXIT_STATUS_NO_CSTBY 0x00 ++/* CSTANDBY Exit with MCU detected as Not running */ ++#define BOOT_API_CTX_CSTBY_EXIT_STATUS_MCU_NOT_RUNNING 0x01 ++/* CSTANDBY Exit with MCU detected as Running */ ++#define BOOT_API_CTX_CSTBY_EXIT_STATUS_MCU_RUNNING 0x02 ++ + /* + * Possible value of boot context field 'auth_status' + */ +@@ -144,7 +228,26 @@ typedef struct { + uint16_t boot_interface_instance; + uint32_t reserved1[13]; + uint32_t otp_afmux_values[3]; +- uint32_t reserved[5]; ++ uint32_t reserved[2]; ++ /* ++ * Log to boot context, what was the kind of boot action ++ * takes values from defines BOOT_API_BOOT_ACTION_XXX above ++ */ ++ uint32_t boot_action; ++ /* ++ * STANDBY Exit status to be checked by FSBL in case ++ * field 'boot_action' == BOOT_API_CTX_BOOT_ACTION_WAKEUP_STANDBY ++ * take values from defines above 'BOOT_API_CTX_STBY_EXIT_STATUS_XXX' ++ * depending on encountered situation ++ */ ++ uint32_t stby_exit_status; ++ /* ++ * CSTANDBY Exit status to be checked by FSBL in case ++ * boot_action == BOOT_API_CTX_BOOT_ACTION_WAKEUP_CSTANDBY ++ * take values from defines above 'BOOT_API_CTX_CSTBY_EXIT_STATUS_XXX' ++ * depending on encountered situation ++ */ ++ uint32_t cstby_exit_status; + uint32_t auth_status; + + /* +diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h +index 263e6d6e1..2f6773e84 100644 +--- a/plat/st/stm32mp1/include/platform_def.h ++++ b/plat/st/stm32mp1/include/platform_def.h +@@ -112,6 +112,8 @@ + */ + #define ARM_IRQ_SEC_PHY_TIMER U(29) + ++#define ARM_IRQ_NON_SEC_SGI_0 U(0) ++ + #define ARM_IRQ_SEC_SGI_0 U(8) + #define ARM_IRQ_SEC_SGI_1 U(9) + #define ARM_IRQ_SEC_SGI_2 U(10) +diff --git a/plat/st/stm32mp1/include/stm32mp1_context.h b/plat/st/stm32mp1/include/stm32mp1_context.h +index 698415af2..081691788 100644 +--- a/plat/st/stm32mp1/include/stm32mp1_context.h ++++ b/plat/st/stm32mp1/include/stm32mp1_context.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. ++ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -7,8 +7,19 @@ + #ifndef STM32MP1_CONTEXT_H + #define STM32MP1_CONTEXT_H + ++#include + #include + ++#define DDR_CRC_GRANULE 32 ++ ++void stm32_clean_context(void); ++int stm32_save_context(uint32_t zq0cr0_zdata); ++int stm32_restore_context(void); ++int stm32_restore_backup_reg(void); ++uint32_t stm32_get_zdata_from_context(void); + int stm32_save_boot_interface(uint32_t interface, uint32_t instance); ++void stm32_save_ddr_training_area(void); ++void stm32_restore_ddr_training_area(void); ++uint32_t stm32_pm_get_optee_ep(void); + + #endif /* STM32MP1_CONTEXT_H */ +diff --git a/plat/st/stm32mp1/include/stm32mp1_low_power.h b/plat/st/stm32mp1/include/stm32mp1_low_power.h +new file mode 100644 +index 000000000..82b3d36c1 +--- /dev/null ++++ b/plat/st/stm32mp1/include/stm32mp1_low_power.h +@@ -0,0 +1,19 @@ ++/* ++ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef STM32MP1_LOW_POWER_H ++#define STM32MP1_LOW_POWER_H ++ ++#include ++#include ++ ++void stm32_rcc_wakeup_update(bool state); ++void stm32_apply_pmic_suspend_config(uint32_t mode); ++void stm32_exit_cstop(void); ++void stm32_pwr_down_wfi(void); ++void stm32_enter_low_power(uint32_t mode, uint32_t nsec_addr); ++ ++#endif /* STM32MP1_LOW_POWER_H */ +diff --git a/plat/st/stm32mp1/include/stm32mp1_power_config.h b/plat/st/stm32mp1/include/stm32mp1_power_config.h +new file mode 100644 +index 000000000..7c7571a5a +--- /dev/null ++++ b/plat/st/stm32mp1/include/stm32mp1_power_config.h +@@ -0,0 +1,19 @@ ++/* ++ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#ifndef STM32MP1_POWER_CONFIG_H ++#define STM32MP1_POWER_CONFIG_H ++ ++#include ++#include ++ ++#define PSCI_MODE_SYSTEM_SUSPEND 0 ++#define PSCI_MODE_SYSTEM_OFF 1 ++ ++void stm32mp1_init_lp_states(void); ++uint32_t stm32mp1_get_lp_soc_mode(uint32_t psci_mode); ++ ++#endif /* STM32MP1_POWER_CONFIG_H */ +diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h +index e38fca012..7adc7f6f1 100644 +--- a/plat/st/stm32mp1/include/stm32mp1_private.h ++++ b/plat/st/stm32mp1/include/stm32mp1_private.h +@@ -11,6 +11,9 @@ + + void configure_mmu(void); + ++void stm32mp_mask_timer(void); ++void __dead2 stm32mp_wait_cpu_reset(void); ++ + void stm32mp1_arch_security_setup(void); + void stm32mp1_security_setup(void); + +diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c +index a52db6cac..1fb3ec510 100644 +--- a/plat/st/stm32mp1/plat_image_load.c ++++ b/plat/st/stm32mp1/plat_image_load.c +@@ -1,10 +1,14 @@ + /* +- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. ++ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + ++#include ++ ++#include + #include ++#include + #include + + /******************************************************************************* +@@ -16,11 +20,68 @@ void plat_flush_next_bl_params(void) + flush_bl_params_desc(); + } + ++#ifdef AARCH32_SP_OPTEE ++static bool addr_inside_backupsram(uintptr_t addr) ++{ ++ return (addr >= STM32MP_BACKUP_RAM_BASE) && ++ (addr < (STM32MP_BACKUP_RAM_BASE + STM32MP_BACKUP_RAM_SIZE)); ++} ++#endif ++ + /******************************************************************************* + * This function returns the list of loadable images. + ******************************************************************************/ + bl_load_info_t *plat_get_bl_image_load_info(void) + { ++ boot_api_context_t *boot_context = ++ (boot_api_context_t *)stm32mp_get_boot_ctx_address(); ++#ifdef AARCH32_SP_OPTEE ++ bl_mem_params_node_t *bl32 = get_bl_mem_params_node(BL32_IMAGE_ID); ++#endif ++ bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID); ++ uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); ++ uint32_t bkpr_core1_addr = ++ tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); ++ uintptr_t pwr_base = stm32mp_pwr_base(); ++ ++ /* ++ * If going back from CSTANDBY / STANDBY and DDR was in Self-Refresh, ++ * BL33 must not be loaded as it would overwrite the code already ++ * in DDR. For this, the BL33 part of the bl_mem_params_desc_ptr ++ * struct should be modified to skip its loading ++ */ ++ if (((boot_context->boot_action == ++ BOOT_API_CTX_BOOT_ACTION_WAKEUP_CSTANDBY) || ++ (boot_context->boot_action == ++ BOOT_API_CTX_BOOT_ACTION_WAKEUP_STANDBY)) && ++ ((mmio_read_32(pwr_base + PWR_CR3) & PWR_CR3_DDRSREN) != 0U) && ++ ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U)) { ++ stm32mp_clk_enable(RTCAPB); ++ ++ if (mmio_read_32(bkpr_core1_addr) != 0U) { ++ bl33->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING; ++ ++#ifdef AARCH32_SP_OPTEE ++ bl32->image_info.h.attr |= IMAGE_ATTRIB_SKIP_LOADING; ++ bl32->ep_info.pc = stm32_pm_get_optee_ep(); ++ ++ if (addr_inside_backupsram(bl32->ep_info.pc)) { ++ stm32mp_clk_enable(BKPSRAM); ++ } ++#else ++ /* ++ * Set ep_info PC to 0, to inform BL32 it is a reset ++ * after STANDBY ++ */ ++ bl33->ep_info.pc = 0; ++#endif ++ } ++ ++ stm32mp_clk_disable(RTCAPB); ++ } ++ ++ bl33->image_info.image_max_size = dt_get_ddr_size(); ++ + return get_bl_load_info_from_mem_params_desc(); + } + +diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk +index 90b3e3c1e..0c57c85af 100644 +--- a/plat/st/stm32mp1/platform.mk ++++ b/plat/st/stm32mp1/platform.mk +@@ -94,6 +94,10 @@ ifeq ($(AARCH32_SP),optee) + BL2_SOURCES += lib/optee/optee_utils.c + endif + ++ ++# Do not use neon in TF-A code, it leads to issues in low-power functions ++TF_CFLAGS += -mfloat-abi=soft ++ + # Macros and rules to build TF binary + STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed + STM32_DT_BASENAME := $(DTB_FILE_NAME:.dtb=) +diff --git a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +index 6c7107ca2..34530f181 100644 +--- a/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk ++++ b/plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk +@@ -6,10 +6,14 @@ + + SP_MIN_WITH_SECURE_FIQ := 1 + ++BL32_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 ++ + BL32_SOURCES += plat/common/aarch32/platform_mp_stack.S \ + drivers/st/rtc/stm32_rtc.c \ + plat/st/stm32mp1/sp_min/sp_min_setup.c \ ++ plat/st/stm32mp1/stm32mp1_low_power.c \ + plat/st/stm32mp1/stm32mp1_pm.c \ ++ plat/st/stm32mp1/stm32mp1_power_config.c \ + plat/st/stm32mp1/stm32mp1_topology.c + # Generic GIC v2 + BL32_SOURCES += drivers/arm/gic/common/gic_common.c \ +diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c +index ff69358e0..62b358cb3 100644 +--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c ++++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -29,6 +30,7 @@ + #include + + #include ++#include + + /****************************************************************************** + * Placeholder variables for copying the arguments that have been passed to +@@ -38,6 +40,27 @@ static entry_point_info_t bl33_image_ep_info; + + static struct console_stm32 console; + ++static void stm32_sgi1_it_handler(void) ++{ ++ uint32_t id; ++ ++ stm32mp_mask_timer(); ++ ++ gicv2_end_of_interrupt(ARM_IRQ_SEC_SGI_1); ++ ++ do { ++ id = plat_ic_get_pending_interrupt_id(); ++ ++ if (id <= MAX_SPI_ID) { ++ gicv2_end_of_interrupt(id); ++ ++ plat_ic_disable_interrupt(id); ++ } ++ } while (id <= MAX_SPI_ID); ++ ++ stm32mp_wait_cpu_reset(); ++} ++ + /******************************************************************************* + * Interrupt handler for FIQ (secure IRQ) + ******************************************************************************/ +@@ -48,12 +71,15 @@ void sp_min_plat_fiq_handler(uint32_t id) + ERROR("STM32MP1_IRQ_TZC400 generated\n"); + panic(); + break; ++ case ARM_IRQ_SEC_SGI_1: ++ stm32_sgi1_it_handler(); ++ break; + case STM32MP1_IRQ_AXIERRIRQ: + ERROR("STM32MP1_IRQ_AXIERRIRQ generated\n"); + panic(); + break; + default: +- ERROR("SECURE IT handler not define for it : %u", id); ++ ERROR("SECURE IT handler not define for it : %u\n", id); + break; + } + } +@@ -67,11 +93,54 @@ void sp_min_plat_fiq_handler(uint32_t id) + entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) + { + entry_point_info_t *next_image_info; ++ uint32_t bkpr_core1_addr = ++ tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); ++ uint32_t bkpr_core1_magic = ++ tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); + + next_image_info = &bl33_image_ep_info; + ++ /* ++ * PC is set to 0 when resetting after STANDBY ++ * The context should be restored, and the image information ++ * should be filled with what what was saved ++ */ + if (next_image_info->pc == 0U) { +- return NULL; ++ void *cpu_context; ++ uint32_t magic_nb, saved_pc; ++ ++ stm32mp_clk_enable(RTCAPB); ++ ++ magic_nb = mmio_read_32(bkpr_core1_magic); ++ saved_pc = mmio_read_32(bkpr_core1_addr); ++ ++ stm32mp_clk_disable(RTCAPB); ++ ++ if (stm32_restore_context() != 0) { ++ panic(); ++ } ++ ++ cpu_context = cm_get_context(NON_SECURE); ++ ++ next_image_info->spsr = read_ctx_reg(get_regs_ctx(cpu_context), ++ CTX_SPSR); ++ ++ /* PC should be retrieved in backup register if OK, else it can ++ * be retrieved from non-secure context ++ */ ++ if (magic_nb == BOOT_API_A7_CORE0_MAGIC_NUMBER) { ++ /* BL33 return address should be in DDR */ ++ if ((saved_pc < STM32MP_DDR_BASE) || ++ (saved_pc > (STM32MP_DDR_BASE + ++ (dt_get_ddr_size() - 1U)))) { ++ panic(); ++ } ++ ++ next_image_info->pc = saved_pc; ++ } else { ++ next_image_info->pc = ++ read_ctx_reg(get_regs_ctx(cpu_context), CTX_LR); ++ } + } + + return next_image_info; +@@ -145,6 +214,12 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + #endif + console_set_scope(&console.console, console_flags); + } ++ ++ if (dt_pmic_status() > 0) { ++ initialize_pmic(); ++ } ++ ++ stm32mp1_init_lp_states(); + } + + /******************************************************************************* +diff --git a/plat/st/stm32mp1/stm32mp1_context.c b/plat/st/stm32mp1/stm32mp1_context.c +index cf8a91eb4..ed54fc625 100644 +--- a/plat/st/stm32mp1/stm32mp1_context.c ++++ b/plat/st/stm32mp1/stm32mp1_context.c +@@ -5,19 +5,171 @@ + */ + + #include ++#include + + #include + ++#include ++#include ++#include + #include ++#include + #include ++#include + #include ++#include ++#include ++#include + + #include + ++#include ++ + #define TAMP_BOOT_ITF_BACKUP_REG_ID U(20) + #define TAMP_BOOT_ITF_MASK U(0x0000FF00) + #define TAMP_BOOT_ITF_SHIFT 8 + ++#define TRAINING_AREA_SIZE 64 ++ ++#ifdef AARCH32_SP_OPTEE ++/* OPTEE_MAILBOX_MAGIC relates to struct backup_data_s as defined */ ++#define OPTEE_MAILBOX_MAGIC_V1 0x01 ++#define OPTEE_MAILBOX_MAGIC ((OPTEE_MAILBOX_MAGIC_V1 << 16) + \ ++ TRAINING_AREA_SIZE) ++#endif ++ ++struct backup_data_s { ++#ifdef AARCH32_SP_OPTEE ++ uint32_t magic; ++ uint32_t core0_resume_hint; ++ uint32_t zq0cr0_zdata; ++ uint8_t ddr_training_backup[TRAINING_AREA_SIZE]; ++#else ++ smc_ctx_t saved_smc_context[PLATFORM_CORE_COUNT]; ++ cpu_context_t saved_cpu_context[PLATFORM_CORE_COUNT]; ++ uint32_t zq0cr0_zdata; ++ struct stm32_rtc_calendar rtc; ++ uint8_t ddr_training_backup[TRAINING_AREA_SIZE]; ++#endif ++}; ++ ++#ifdef AARCH32_SP_OPTEE ++uint32_t stm32_pm_get_optee_ep(void) ++{ ++ struct backup_data_s *backup_data; ++ uint32_t ep; ++ ++ stm32mp_clk_enable(BKPSRAM); ++ ++ /* Context & Data to be saved at the beginning of Backup SRAM */ ++ backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE; ++ ++ if (backup_data->magic != OPTEE_MAILBOX_MAGIC) { ++ panic(); ++ } ++ ++ ep = backup_data->core0_resume_hint; ++ ++ stm32mp_clk_disable(BKPSRAM); ++ ++ return ep; ++} ++#else /*AARCH32_SP_OPTEE*/ ++void stm32_clean_context(void) ++{ ++ stm32mp_clk_enable(BKPSRAM); ++ ++ zeromem((void *)STM32MP_BACKUP_RAM_BASE, sizeof(struct backup_data_s)); ++ ++ stm32mp_clk_disable(BKPSRAM); ++} ++ ++int stm32_save_context(uint32_t zq0cr0_zdata) ++{ ++ void *smc_context; ++ void *cpu_context; ++ struct backup_data_s *backup_data; ++ ++ stm32mp_clk_enable(BKPSRAM); ++ ++ /* Context & Data to be saved at the beginning of Backup SRAM */ ++ backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE; ++ ++ /* Retrieve smc context struct address */ ++ smc_context = smc_get_ctx(NON_SECURE); ++ ++ /* Retrieve smc context struct address */ ++ cpu_context = cm_get_context(NON_SECURE); ++ ++ /* Save context in Backup SRAM */ ++ memcpy(&backup_data->saved_smc_context[0], smc_context, ++ sizeof(smc_ctx_t) * PLATFORM_CORE_COUNT); ++ memcpy(&backup_data->saved_cpu_context[0], cpu_context, ++ sizeof(cpu_context_t) * PLATFORM_CORE_COUNT); ++ ++ backup_data->zq0cr0_zdata = zq0cr0_zdata; ++ ++ stm32_rtc_get_calendar(&backup_data->rtc); ++ ++ stm32mp_clk_disable(BKPSRAM); ++ ++ return 0; ++} ++ ++int stm32_restore_context(void) ++{ ++ void *smc_context; ++ void *cpu_context; ++ struct backup_data_s *backup_data; ++ struct stm32_rtc_calendar current_calendar; ++ unsigned long long stdby_time_in_ms; ++ ++ stm32mp_clk_enable(BKPSRAM); ++ ++ /* Context & Data to be saved at the beginning of Backup SRAM */ ++ backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE; ++ ++ /* Retrieve smc context struct address */ ++ smc_context = smc_get_ctx(NON_SECURE); ++ ++ /* Retrieve smc context struct address */ ++ cpu_context = cm_get_context(NON_SECURE); ++ ++ /* Restore data from Backup SRAM */ ++ memcpy(smc_context, backup_data->saved_smc_context, ++ sizeof(smc_ctx_t) * PLATFORM_CORE_COUNT); ++ memcpy(cpu_context, backup_data->saved_cpu_context, ++ sizeof(cpu_context_t) * PLATFORM_CORE_COUNT); ++ ++ /* update STGEN counter with standby mode length */ ++ stm32_rtc_get_calendar(¤t_calendar); ++ stdby_time_in_ms = stm32_rtc_diff_calendar(¤t_calendar, ++ &backup_data->rtc); ++ stm32mp1_stgen_increment(stdby_time_in_ms); ++ ++ stm32mp_clk_disable(BKPSRAM); ++ ++ return 0; ++} ++#endif /*AARCH32_SP_OPTEE*/ ++ ++uint32_t stm32_get_zdata_from_context(void) ++{ ++ struct backup_data_s *backup_data; ++ uint32_t zdata; ++ ++ stm32mp_clk_enable(BKPSRAM); ++ ++ backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE; ++ ++ zdata = (backup_data->zq0cr0_zdata >> DDRPHYC_ZQ0CRN_ZDATA_SHIFT) & ++ DDRPHYC_ZQ0CRN_ZDATA_MASK; ++ ++ stm32mp_clk_disable(BKPSRAM); ++ ++ return zdata; ++} ++ + int stm32_save_boot_interface(uint32_t interface, uint32_t instance) + { + uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID); +@@ -33,3 +185,50 @@ int stm32_save_boot_interface(uint32_t interface, uint32_t instance) + + return 0; + } ++ ++#if defined(IMAGE_BL32) ++/* ++ * When returning from STANDBY, the 64 first bytes of DDR will be overwritten ++ * during DDR DQS training. This area must then be saved before going to ++ * standby, and will be restored after ++ */ ++void stm32_save_ddr_training_area(void) ++{ ++ struct backup_data_s *backup_data; ++ int ret __unused; ++ ++ stm32mp_clk_enable(BKPSRAM); ++ ++ backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE; ++ ++ ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, ++ PAGE_SIZE, MT_MEMORY | MT_RW | MT_NS); ++ assert(ret == 0); ++ ++ memcpy(&backup_data->ddr_training_backup, ++ (const uint32_t *)STM32MP_DDR_BASE, ++ TRAINING_AREA_SIZE); ++ dsb(); ++ ++ ret = mmap_remove_dynamic_region(STM32MP_DDR_BASE, PAGE_SIZE); ++ assert(ret == 0); ++ ++ stm32mp_clk_disable(BKPSRAM); ++} ++#endif ++ ++void stm32_restore_ddr_training_area(void) ++{ ++ struct backup_data_s *backup_data; ++ ++ stm32mp_clk_enable(BKPSRAM); ++ ++ backup_data = (struct backup_data_s *)STM32MP_BACKUP_RAM_BASE; ++ ++ memcpy((uint32_t *)STM32MP_DDR_BASE, ++ &backup_data->ddr_training_backup, ++ TRAINING_AREA_SIZE); ++ dsb(); ++ ++ stm32mp_clk_disable(BKPSRAM); ++} +diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h +index dbe62f09d..26a194acb 100644 +--- a/plat/st/stm32mp1/stm32mp1_def.h ++++ b/plat/st/stm32mp1/stm32mp1_def.h +@@ -25,6 +25,7 @@ + #include + #include + #include ++#include + #include + #include + #endif +@@ -58,6 +59,9 @@ + #define STM32MP_SYSRAM_BASE U(0x2FFC0000) + #define STM32MP_SYSRAM_SIZE U(0x00040000) + ++#define STM32MP_BACKUP_RAM_BASE U(0x54000000) ++#define STM32MP_BACKUP_RAM_SIZE U(0x00001000) ++ + /* DDR configuration */ + #define STM32MP_DDR_BASE U(0xC0000000) + #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ +diff --git a/plat/st/stm32mp1/stm32mp1_low_power.c b/plat/st/stm32mp1/stm32mp1_low_power.c +new file mode 100644 +index 000000000..36664c21c +--- /dev/null ++++ b/plat/st/stm32mp1/stm32mp1_low_power.c +@@ -0,0 +1,327 @@ ++/* ++ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static unsigned int gicc_pmr; ++static struct stm32_rtc_calendar sleep_time, current_calendar; ++static unsigned long long stdby_time_in_ms; ++static bool enter_cstop_done; ++ ++struct pwr_lp_config { ++ uint32_t pwr_cr1; ++ uint32_t pwr_mpucr; ++ const char *regul_suspend_node_name; ++}; ++ ++#define PWR_CR1_MASK (PWR_CR1_LPDS | PWR_CR1_LPCFG | PWR_CR1_LVDS) ++#define PWR_MPUCR_MASK (PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_CSSF | PWR_MPUCR_PDDS) ++ ++static const struct pwr_lp_config config_pwr[STM32_PM_MAX_SOC_MODE] = { ++ [STM32_PM_CSLEEP_RUN] = { ++ .pwr_cr1 = 0U, ++ .pwr_mpucr = PWR_MPUCR_CSSF, ++ .regul_suspend_node_name = NULL, ++ }, ++ [STM32_PM_CSTOP_ALLOW_STOP] = { ++ .pwr_cr1 = 0U, ++ .pwr_mpucr = PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_CSSF, ++ .regul_suspend_node_name = NULL, ++ }, ++ [STM32_PM_CSTOP_ALLOW_LP_STOP] = { ++ .pwr_cr1 = PWR_CR1_LPDS, ++ .pwr_mpucr = PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_CSSF, ++ .regul_suspend_node_name = "lp-stop", ++ }, ++ [STM32_PM_CSTOP_ALLOW_LPLV_STOP] = { ++ .pwr_cr1 = PWR_CR1_LVDS | PWR_CR1_LPDS | PWR_CR1_LPCFG, ++ .pwr_mpucr = PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_CSSF, ++ .regul_suspend_node_name = "lplv-stop", ++ }, ++ [STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR] = { ++ .pwr_cr1 = 0U, ++ .pwr_mpucr = PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_CSSF | ++ PWR_MPUCR_PDDS, ++ .regul_suspend_node_name = "standby-ddr-sr", ++ }, ++ [STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF] = { ++ .pwr_cr1 = 0U, ++ .pwr_mpucr = PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_CSSF | ++ PWR_MPUCR_PDDS, ++ .regul_suspend_node_name = "standby-ddr-off", ++ }, ++ [STM32_PM_SHUTDOWN] = { ++ .pwr_cr1 = 0U, ++ .pwr_mpucr = 0U, ++ .regul_suspend_node_name = "standby-ddr-off", ++ }, ++}; ++ ++#define GICC_PMR_PRIORITY_8 U(0x8) ++ ++void stm32_apply_pmic_suspend_config(uint32_t mode) ++{ ++ const char *node_name = config_pwr[mode].regul_suspend_node_name; ++ ++ assert(mode < ARRAY_SIZE(config_pwr)); ++ ++ if (node_name != NULL) { ++ if (!initialize_pmic_i2c()) { ++ panic(); ++ } ++ ++ if (dt_pmic_set_lp_config(node_name) != 0) { ++ panic(); ++ } ++ ++ if (dt_pmic_configure_boot_on_regulators() != 0) { ++ panic(); ++ } ++ } ++} ++ ++/* ++ * stm32_enter_cstop - Prepare CSTOP mode ++ * ++ * @mode - Target low power mode ++ * @nsec_addr - Non secure resume entry point ++ * Return 0 if succeed to suspend, non 0 else. ++ */ ++static void enter_cstop(uint32_t mode, uint32_t nsec_addr) ++{ ++ uint32_t zq0cr0_zdata; ++ uint32_t bkpr_core1_addr = ++ tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX); ++ uint32_t bkpr_core1_magic = ++ tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); ++ uint32_t pwr_cr1 = config_pwr[mode].pwr_cr1; ++ uintptr_t pwr_base = stm32mp_pwr_base(); ++ uintptr_t rcc_base = stm32mp_rcc_base(); ++ ++ stm32mp1_syscfg_disable_io_compensation(); ++ ++ dcsw_op_all(DC_OP_CISW); ++ ++ stm32_clean_context(); ++ ++ if (mode == STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR) { ++ /* ++ * The first 64 bytes of DDR need to be saved for DDR DQS ++ * training ++ */ ++ stm32_save_ddr_training_area(); ++ } ++ ++ if (dt_pmic_status() > 0) { ++ stm32_apply_pmic_suspend_config(mode); ++ ++ if (mode == STM32_PM_CSTOP_ALLOW_LP_STOP) { ++ pwr_cr1 |= PWR_CR1_LPCFG; ++ } ++ } ++ ++ /* Clear RCC interrupt before enabling it */ ++ mmio_setbits_32(rcc_base + RCC_MP_CIFR, RCC_MP_CIFR_WKUPF); ++ ++ /* Enable RCC Wake-up */ ++ mmio_setbits_32(rcc_base + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); ++ ++ /* Configure low power mode */ ++ mmio_clrsetbits_32(pwr_base + PWR_MPUCR, PWR_MPUCR_MASK, ++ config_pwr[mode].pwr_mpucr); ++ mmio_clrsetbits_32(pwr_base + PWR_CR1, PWR_CR1_MASK, ++ pwr_cr1); ++ ++ /* Clear RCC pending interrupt flags */ ++ mmio_write_32(rcc_base + RCC_MP_CIFR, RCC_MP_CIFR_MASK); ++ ++ /* Request CSTOP mode to RCC */ ++ mmio_setbits_32(rcc_base + RCC_MP_SREQSETR, ++ RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1); ++ ++ stm32_iwdg_refresh(); ++ ++ gicc_pmr = plat_ic_set_priority_mask(GICC_PMR_PRIORITY_8); ++ ++ /* ++ * Set DDR in Self-refresh, even if no return address is given. ++ * This is also the procedure awaited when switching off power supply. ++ */ ++ if (ddr_standby_sr_entry(&zq0cr0_zdata) != 0) { ++ return; ++ } ++ ++ stm32mp_clk_enable(RTCAPB); ++ ++ mmio_write_32(bkpr_core1_addr, 0); ++ mmio_write_32(bkpr_core1_magic, 0); ++ ++ if (mode == STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR) { ++ /* ++ * Save non-secure world entrypoint after standby in Backup ++ * register ++ */ ++ mmio_write_32(bkpr_core1_addr, nsec_addr); ++ mmio_write_32(bkpr_core1_magic, ++ BOOT_API_A7_CORE0_MAGIC_NUMBER); ++ ++ if (stm32_save_context(zq0cr0_zdata) != 0) { ++ panic(); ++ } ++ ++ /* Keep retention and backup RAM content in standby */ ++ mmio_setbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | ++ PWR_CR2_RREN); ++ while ((mmio_read_32(pwr_base + PWR_CR2) & ++ (PWR_CR2_BRRDY | PWR_CR2_RRRDY)) == 0U) { ++ ; ++ } ++ } ++ ++ stm32mp_clk_disable(RTCAPB); ++ ++ stm32_rtc_get_calendar(&sleep_time); ++ ++ enter_cstop_done = true; ++} ++ ++/* ++ * stm32_exit_cstop - Exit from CSTOP mode ++ */ ++void stm32_exit_cstop(void) ++{ ++ uintptr_t pwr_base = stm32mp_pwr_base(); ++ uintptr_t rcc_base = stm32mp_rcc_base(); ++ ++ if (!enter_cstop_done) { ++ return; ++ } ++ ++ enter_cstop_done = false; ++ ++ if (ddr_sw_self_refresh_exit() != 0) { ++ panic(); ++ } ++ ++ plat_ic_set_priority_mask(gicc_pmr); ++ ++ /* Disable RCC Wake-up */ ++ mmio_clrbits_32(rcc_base + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); ++ ++ /* Disable STOP request */ ++ mmio_setbits_32(rcc_base + RCC_MP_SREQCLRR, ++ RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1); ++ ++ dsb(); ++ isb(); ++ ++ /* Disable retention and backup RAM content after stop */ ++ mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | PWR_CR2_RREN); ++ ++ /* Update STGEN counter with low power mode duration */ ++ stm32_rtc_get_calendar(¤t_calendar); ++ ++ stdby_time_in_ms = stm32_rtc_diff_calendar(¤t_calendar, ++ &sleep_time); ++ ++ stm32mp1_stgen_increment(stdby_time_in_ms); ++ ++ stm32mp1_syscfg_enable_io_compensation(); ++} ++ ++static void enter_shutdown(void) ++{ ++ /* Set DDR in Self-refresh before shutting down the platform */ ++ if (ddr_standby_sr_entry(NULL) != 0) { ++ WARN("DDR can't be set in Self-refresh mode\n"); ++ } ++ ++ if (dt_pmic_status() > 0) { ++ if (!initialize_pmic_i2c()) { ++ panic(); ++ } ++ ++ stpmic1_switch_off(); ++ ++ udelay(100); ++ ++ /* Shouldn't be reached */ ++ panic(); ++ } ++} ++ ++static void enter_csleep(void) ++{ ++ uintptr_t pwr_base = stm32mp_pwr_base(); ++ ++ mmio_clrsetbits_32(pwr_base + PWR_MPUCR, PWR_MPUCR_MASK, ++ config_pwr[STM32_PM_CSLEEP_RUN].pwr_mpucr); ++ mmio_clrsetbits_32(pwr_base + PWR_CR1, PWR_CR1_MASK, ++ config_pwr[STM32_PM_CSLEEP_RUN].pwr_cr1); ++ ++ stm32_pwr_down_wfi(); ++} ++ ++void stm32_enter_low_power(uint32_t mode, uint32_t nsec_addr) ++{ ++ switch (mode) { ++ case STM32_PM_SHUTDOWN: ++ enter_shutdown(); ++ break; ++ ++ case STM32_PM_CSLEEP_RUN: ++ enter_csleep(); ++ break; ++ ++ default: ++ enter_cstop(mode, nsec_addr); ++ break; ++ } ++} ++ ++void stm32_pwr_down_wfi(void) ++{ ++ uint32_t interrupt = GIC_SPURIOUS_INTERRUPT; ++ ++ while (interrupt == GIC_SPURIOUS_INTERRUPT) { ++ wfi(); ++ ++ interrupt = gicv2_acknowledge_interrupt(); ++ ++ if (interrupt != GIC_SPURIOUS_INTERRUPT) { ++ gicv2_end_of_interrupt(interrupt); ++ } ++ ++ stm32_iwdg_refresh(); ++ } ++} +diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c +index cf9fa8e69..9ebea40f1 100644 +--- a/plat/st/stm32mp1/stm32mp1_pm.c ++++ b/plat/st/stm32mp1/stm32mp1_pm.c +@@ -13,14 +13,20 @@ + #include + #include + #include ++#include + #include ++#include + #include + #include + #include + #include + ++#include ++#include ++ + static uintptr_t stm32_sec_entrypoint; + static uint32_t cntfrq_core0; ++static uintptr_t saved_entrypoint; + + /******************************************************************************* + * STM32MP1 handler called when a CPU is about to enter standby. +@@ -33,11 +39,12 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state) + assert(cpu_state == ARM_LOCAL_STATE_RET); + + /* +- * Enter standby state +- * dsb is good practice before using wfi to enter low power states ++ * Enter standby state. ++ * Synchronize on memory accesses and instruction flow before the WFI ++ * instruction. + */ +- isb(); + dsb(); ++ isb(); + while (interrupt == GIC_SPURIOUS_INTERRUPT) { + wfi(); + +@@ -64,10 +71,23 @@ static int stm32_pwr_domain_on(u_register_t mpidr) + uint32_t bkpr_core1_magic = + tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX); + ++ if (stm32mp_is_single_core()) { ++ return PSCI_E_INTERN_FAIL; ++ } ++ + if (mpidr == current_cpu_mpidr) { + return PSCI_E_INVALID_PARAMS; + } + ++ /* Reset backup register content */ ++ mmio_write_32(bkpr_core1_magic, 0); ++ ++ /* Need to send additional IT 0 after individual core 1 reset */ ++ gicv2_raise_sgi(ARM_IRQ_NON_SEC_SGI_0, STM32MP_SECONDARY_CPU); ++ ++ /* Wait for this IT to be acknowledged by ROM code. */ ++ udelay(10); ++ + if ((stm32_sec_entrypoint < STM32MP_SYSRAM_BASE) || + (stm32_sec_entrypoint > (STM32MP_SYSRAM_BASE + + (STM32MP_SYSRAM_SIZE - 1)))) { +@@ -107,7 +127,9 @@ static void stm32_pwr_domain_off(const psci_power_state_t *target_state) + ******************************************************************************/ + static void stm32_pwr_domain_suspend(const psci_power_state_t *target_state) + { +- /* Nothing to do, power domain is not disabled */ ++ uint32_t soc_mode = stm32mp1_get_lp_soc_mode(PSCI_MODE_SYSTEM_SUSPEND); ++ ++ stm32_enter_low_power(soc_mode, saved_entrypoint); + } + + /******************************************************************************* +@@ -134,16 +156,59 @@ static void stm32_pwr_domain_suspend_finish(const psci_power_state_t + /* Nothing to do, power domain is not disabled */ + } + ++/******************************************************************************* ++ * STM32MP1 handler called when a core tries to power itself down. If this ++ * call is made by core 0, it is a return from stop mode. In this case, we ++ * should restore previous context and jump to secure entrypoint. ++ ******************************************************************************/ + static void __dead2 stm32_pwr_domain_pwr_down_wfi(const psci_power_state_t + *target_state) + { +- ERROR("stm32mpu1 Power Down WFI: operation not handled.\n"); ++ if (MPIDR_AFFLVL0_VAL(read_mpidr_el1()) == STM32MP_PRIMARY_CPU) { ++ void (*warm_entrypoint)(void) = ++ (void (*)(void))stm32_sec_entrypoint; ++ ++ stm32_pwr_down_wfi(); ++ ++ stm32_exit_cstop(); ++ ++ disable_mmu_icache_secure(); ++ ++ warm_entrypoint(); ++ } ++ ++ mmio_write_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR, ++ RCC_MP_GRSTCSETR_MPUP1RST); ++ ++ /* ++ * Synchronize on memory accesses and instruction flow before ++ * auto-reset from the WFI instruction. ++ */ ++ dsb(); ++ isb(); ++ wfi(); ++ ++ /* This shouldn't be reached */ + panic(); + } + + static void __dead2 stm32_system_off(void) + { +- ERROR("stm32mpu1 System Off: operation not handled.\n"); ++ uint32_t soc_mode = stm32mp1_get_lp_soc_mode(PSCI_MODE_SYSTEM_OFF); ++ ++ if (!stm32mp_is_single_core()) { ++ /* Prepare Core 1 reset */ ++ mmio_setbits_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR, ++ RCC_MP_GRSTCSETR_MPUP1RST); ++ /* Send IT to core 1 to put itself in WFI */ ++ gicv2_raise_sgi(ARM_IRQ_SEC_SGI_1, STM32MP_SECONDARY_CPU); ++ } ++ ++ stm32_enter_low_power(soc_mode, 0); ++ ++ stm32_pwr_down_wfi(); ++ ++ /* This shouldn't be reached */ + panic(); + } + +@@ -188,6 +253,8 @@ static int stm32_validate_ns_entrypoint(uintptr_t entrypoint) + return PSCI_E_INVALID_ADDRESS; + } + ++ saved_entrypoint = entrypoint; ++ + return PSCI_E_SUCCESS; + } + +@@ -211,6 +278,12 @@ static int stm32_node_hw_state(u_register_t target_cpu, + return (int)HW_ON; + } + ++static void stm32_get_sys_suspend_power_state(psci_power_state_t *req_state) ++{ ++ req_state->pwr_domain_state[0] = ARM_LOCAL_STATE_OFF; ++ req_state->pwr_domain_state[1] = ARM_LOCAL_STATE_OFF; ++} ++ + /******************************************************************************* + * Export the platform handlers. The ARM Standard platform layer will take care + * of registering the handlers with PSCI. +@@ -227,7 +300,8 @@ static const plat_psci_ops_t stm32_psci_ops = { + .system_reset = stm32_system_reset, + .validate_power_state = stm32_validate_power_state, + .validate_ns_entrypoint = stm32_validate_ns_entrypoint, +- .get_node_hw_state = stm32_node_hw_state ++ .get_node_hw_state = stm32_node_hw_state, ++ .get_sys_suspend_power_state = stm32_get_sys_suspend_power_state, + }; + + /******************************************************************************* +diff --git a/plat/st/stm32mp1/stm32mp1_power_config.c b/plat/st/stm32mp1/stm32mp1_power_config.c +new file mode 100644 +index 000000000..93644f4ea +--- /dev/null ++++ b/plat/st/stm32mp1/stm32mp1_power_config.c +@@ -0,0 +1,130 @@ ++/* ++ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#define DT_PWR_COMPAT "st,stm32mp1-pwr" ++#define SYSTEM_SUSPEND_SUPPORTED_MODES "system_suspend_supported_soc_modes" ++#define SYSTEM_OFF_MODE "system_off_soc_mode" ++ ++static uint32_t deepest_system_suspend_mode; ++static uint32_t system_off_mode; ++static uint8_t stm32mp1_supported_soc_modes[STM32_PM_MAX_SOC_MODE]; ++ ++static int dt_get_pwr_node(void *fdt) ++{ ++ return fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT); ++} ++ ++static void save_supported_mode(void *fdt, int pwr_node) ++{ ++ int len; ++ uint32_t count; ++ unsigned int i; ++ uint32_t supported[ARRAY_SIZE(stm32mp1_supported_soc_modes)]; ++ const void *prop; ++ ++ prop = fdt_getprop(fdt, pwr_node, SYSTEM_SUSPEND_SUPPORTED_MODES, &len); ++ if (prop == NULL) { ++ panic(); ++ } ++ ++ count = (uint32_t)len / sizeof(uint32_t); ++ if (count > STM32_PM_MAX_SOC_MODE) { ++ panic(); ++ } ++ ++ if (fdt_read_uint32_array(pwr_node, SYSTEM_SUSPEND_SUPPORTED_MODES, ++ &supported[0], count) < 0) { ++ ERROR("PWR DT\n"); ++ panic(); ++ } ++ ++ for (i = 0; i < count; i++) { ++ if (supported[i] >= STM32_PM_MAX_SOC_MODE) { ++ ERROR("Invalid mode\n"); ++ panic(); ++ } ++ stm32mp1_supported_soc_modes[supported[i]] = 1U; ++ } ++ ++ /* Initialize to deepest possible mode */ ++ for (i = STM32_PM_MAX_SOC_MODE - 1U; i != STM32_PM_CSLEEP_RUN; i--) { ++ if (stm32mp1_supported_soc_modes[i] == 1U) { ++ deepest_system_suspend_mode = i; ++ break; ++ } ++ } ++} ++ ++static int dt_fill_lp_state(uint32_t *lp_state_config, const char *lp_state) ++{ ++ int pwr_node; ++ void *fdt; ++ const fdt32_t *cuint; ++ ++ if (fdt_get_address(&fdt) == 0) { ++ return -ENOENT; ++ } ++ ++ pwr_node = dt_get_pwr_node(fdt); ++ if (pwr_node < 0) { ++ return -FDT_ERR_NOTFOUND; ++ } ++ ++ cuint = fdt_getprop(fdt, pwr_node, lp_state, NULL); ++ if (cuint == NULL) { ++ return -FDT_ERR_NOTFOUND; ++ } ++ ++ *lp_state_config = fdt32_to_cpu(*cuint); ++ ++ save_supported_mode(fdt, pwr_node); ++ ++ return 0; ++} ++ ++void stm32mp1_init_lp_states(void) ++{ ++ if (dt_fill_lp_state(&system_off_mode, SYSTEM_OFF_MODE) < 0) { ++ ERROR("Node %s not found\n", SYSTEM_OFF_MODE); ++ panic(); ++ } ++} ++ ++static bool is_allowed_mode(uint32_t soc_mode) ++{ ++ assert(soc_mode < ARRAY_SIZE(stm32mp1_supported_soc_modes)); ++ ++ return stm32mp1_supported_soc_modes[soc_mode] == 1U; ++} ++ ++uint32_t stm32mp1_get_lp_soc_mode(uint32_t psci_mode) ++{ ++ uint32_t mode; ++ ++ if (psci_mode == PSCI_MODE_SYSTEM_OFF) { ++ return system_off_mode; ++ } ++ ++ mode = deepest_system_suspend_mode; ++ ++ while ((mode > STM32_PM_CSLEEP_RUN) && !is_allowed_mode(mode)) { ++ mode--; ++ } ++ ++ return mode; ++} +diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c +index e2dcd2af7..3a7b22e37 100644 +--- a/plat/st/stm32mp1/stm32mp1_private.c ++++ b/plat/st/stm32mp1/stm32mp1_private.c +@@ -10,8 +10,11 @@ + + #include + ++#include ++#include + #include + #include ++#include + + /* Internal layout of the 32bit OTP word board_id */ + #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) +@@ -76,6 +79,42 @@ void configure_mmu(void) + enable_mmu_svc_mon(0); + } + ++#define ARM_CNTXCTL_IMASK BIT(1) ++ ++void stm32mp_mask_timer(void) ++{ ++ /* Mask timer interrupts */ ++ write_cntp_ctl(read_cntp_ctl() | ARM_CNTXCTL_IMASK); ++ write_cntv_ctl(read_cntv_ctl() | ARM_CNTXCTL_IMASK); ++} ++ ++void __dead2 stm32mp_wait_cpu_reset(void) ++{ ++ uint32_t id; ++ ++ dcsw_op_all(DC_OP_CISW); ++ write_sctlr(read_sctlr() & ~SCTLR_C_BIT); ++ dcsw_op_all(DC_OP_CISW); ++ __asm__("clrex"); ++ ++ dsb(); ++ isb(); ++ ++ for ( ; ; ) { ++ do { ++ id = plat_ic_get_pending_interrupt_id(); ++ ++ if (id <= MAX_SPI_ID) { ++ gicv2_end_of_interrupt(id); ++ ++ plat_ic_disable_interrupt(id); ++ } ++ } while (id <= MAX_SPI_ID); ++ ++ wfi(); ++ } ++} ++ + unsigned long stm32_get_gpio_bank_clock(unsigned int bank) + { + if (bank == GPIO_BANK_Z) { +diff --git a/plat/st/stm32mp1/stm32mp1_shared_resources.c.bak b/plat/st/stm32mp1/stm32mp1_shared_resources.c.bak +new file mode 100644 +index 000000000..208e34a8b +--- /dev/null ++++ b/plat/st/stm32mp1/stm32mp1_shared_resources.c.bak +@@ -0,0 +1,597 @@ ++/* ++ * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved ++ * ++ * SPDX-License-Identifier: BSD-3-Clause ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++#include ++ ++/* ++ * Once one starts to get the resource registering state, one cannot register ++ * new resources. This ensures resource state cannot change. ++ */ ++static bool registering_locked; ++ ++/* ++ * Shared peripherals and resources registration ++ * ++ * Each resource assignation is stored in a table. The state defaults ++ * to PERIPH_UNREGISTERED if the resource is not explicitly assigned. ++ * ++ * Resource driver that as not embedded (a.k.a their related CFG_xxx build ++ * directive is disabled) are assigned to the non-secure world. ++ * ++ * Each pin of the GPIOZ bank can be secure or non-secure. ++ * ++ * It is the platform responsibility the ensure resource assignation ++ * matches the access permission firewalls configuration. ++ */ ++enum shres_state { ++ SHRES_UNREGISTERED = 0, ++ SHRES_SECURE, ++ SHRES_NON_SECURE, ++}; ++ ++/* Force uint8_t array for array of enum shres_state for size considerations */ ++static uint8_t shres_state[STM32MP1_SHRES_COUNT]; ++ ++static const char *shres2str_id_tbl[STM32MP1_SHRES_COUNT] __unused = { ++ [STM32MP1_SHRES_GPIOZ(0)] = "GPIOZ0", ++ [STM32MP1_SHRES_GPIOZ(1)] = "GPIOZ1", ++ [STM32MP1_SHRES_GPIOZ(2)] = "GPIOZ2", ++ [STM32MP1_SHRES_GPIOZ(3)] = "GPIOZ3", ++ [STM32MP1_SHRES_GPIOZ(4)] = "GPIOZ4", ++ [STM32MP1_SHRES_GPIOZ(5)] = "GPIOZ5", ++ [STM32MP1_SHRES_GPIOZ(6)] = "GPIOZ6", ++ [STM32MP1_SHRES_GPIOZ(7)] = "GPIOZ7", ++ [STM32MP1_SHRES_IWDG1] = "IWDG1", ++ [STM32MP1_SHRES_USART1] = "USART1", ++ [STM32MP1_SHRES_SPI6] = "SPI6", ++ [STM32MP1_SHRES_I2C4] = "I2C4", ++ [STM32MP1_SHRES_RNG1] = "RNG1", ++ [STM32MP1_SHRES_HASH1] = "HASH1", ++ [STM32MP1_SHRES_CRYP1] = "CRYP1", ++ [STM32MP1_SHRES_I2C6] = "I2C6", ++ [STM32MP1_SHRES_RTC] = "RTC", ++ [STM32MP1_SHRES_MCU] = "MCU", ++ [STM32MP1_SHRES_MDMA] = "MDMA", ++ [STM32MP1_SHRES_PLL3] = "PLL3", ++}; ++ ++static const char __unused *shres2str_id(enum stm32mp_shres id) ++{ ++ assert(id < ARRAY_SIZE(shres2str_id_tbl)); ++ ++ return shres2str_id_tbl[id]; ++} ++ ++static const char __unused *shres2str_state_tbl[] = { ++ [SHRES_UNREGISTERED] = "unregistered", ++ [SHRES_NON_SECURE] = "non-secure", ++ [SHRES_SECURE] = "secure", ++}; ++ ++static const char __unused *shres2str_state(unsigned int state) ++{ ++ assert(state < ARRAY_SIZE(shres2str_state_tbl)); ++ ++ return shres2str_state_tbl[state]; ++} ++ ++/* Get resource state: these accesses lock the registering support */ ++static void lock_registering(void) ++{ ++ registering_locked = true; ++} ++ ++static bool periph_is_non_secure(enum stm32mp_shres id) ++{ ++ lock_registering(); ++ ++ return (shres_state[id] == SHRES_NON_SECURE) || ++ (shres_state[id] == SHRES_UNREGISTERED); ++} ++ ++static bool periph_is_secure(enum stm32mp_shres id) ++{ ++ return !periph_is_non_secure(id); ++} ++ ++/* GPIOZ pin count is saved in RAM to prevent parsing FDT several times */ ++static int8_t gpioz_nbpin = -1; ++ ++static unsigned int get_gpio_nbpin(unsigned int bank) ++{ ++ if (bank != GPIO_BANK_Z) { ++ int count = fdt_get_gpio_bank_pin_count(bank); ++ ++ assert((count >= 0) || (count <= (GPIO_PIN_MAX + 1))); ++ ++ return (unsigned int)count; ++ } ++ ++ if (gpioz_nbpin < 0) { ++ int count = fdt_get_gpio_bank_pin_count(GPIO_BANK_Z); ++ ++ assert((count == 0) || (count == STM32MP_GPIOZ_PIN_MAX_COUNT)); ++ ++ gpioz_nbpin = count; ++ } ++ ++ return (unsigned int)gpioz_nbpin; ++} ++ ++static unsigned int get_gpioz_nbpin(void) ++{ ++ return get_gpio_nbpin(GPIO_BANK_Z); ++} ++ ++static void register_periph(enum stm32mp_shres id, unsigned int state) ++{ ++ assert((id < STM32MP1_SHRES_COUNT) && ++ ((state == SHRES_SECURE) || (state == SHRES_NON_SECURE))); ++ ++ if (registering_locked) { ++ if (shres_state[id] == state) { ++ return; ++ } ++ panic(); ++ } ++ ++ if ((shres_state[id] != SHRES_UNREGISTERED) && ++ (shres_state[id] != state)) { ++ VERBOSE("Cannot change %s from %s to %s\n", ++ shres2str_id(id), ++ shres2str_state(shres_state[id]), ++ shres2str_state(state)); ++ panic(); ++ } ++ ++ if (shres_state[id] == SHRES_UNREGISTERED) { ++ VERBOSE("Register %s as %s\n", ++ shres2str_id(id), shres2str_state(state)); ++ } ++ ++ if ((id >= STM32MP1_SHRES_GPIOZ(0)) && ++ (id <= STM32MP1_SHRES_GPIOZ(7)) && ++ ((id - STM32MP1_SHRES_GPIOZ(0)) >= get_gpioz_nbpin())) { ++ ERROR("Invalid GPIO pin %u, %u pin(s) available\n", ++ id - STM32MP1_SHRES_GPIOZ(0), get_gpioz_nbpin()); ++ panic(); ++ } ++ ++ shres_state[id] = (uint8_t)state; ++ ++ /* Explore clock tree to lock dependencies */ ++ if (state == SHRES_SECURE) { ++ enum stm32mp_shres clock_res_id; ++ ++ switch (id) { ++ case STM32MP1_SHRES_GPIOZ(0): ++ case STM32MP1_SHRES_GPIOZ(1): ++ case STM32MP1_SHRES_GPIOZ(2): ++ case STM32MP1_SHRES_GPIOZ(3): ++ case STM32MP1_SHRES_GPIOZ(4): ++ case STM32MP1_SHRES_GPIOZ(5): ++ case STM32MP1_SHRES_GPIOZ(6): ++ case STM32MP1_SHRES_GPIOZ(7): ++ clock_res_id = GPIOZ; ++ break; ++ case STM32MP1_SHRES_IWDG1: ++ clock_res_id = IWDG1; ++ break; ++ case STM32MP1_SHRES_USART1: ++ clock_res_id = USART1_K; ++ break; ++ case STM32MP1_SHRES_SPI6: ++ clock_res_id = SPI6_K; ++ break; ++ case STM32MP1_SHRES_I2C4: ++ clock_res_id = I2C4_K; ++ break; ++ case STM32MP1_SHRES_RNG1: ++ clock_res_id = RNG1_K; ++ break; ++ case STM32MP1_SHRES_HASH1: ++ clock_res_id = HASH1; ++ break; ++ case STM32MP1_SHRES_CRYP1: ++ clock_res_id = CRYP1; ++ break; ++ case STM32MP1_SHRES_I2C6: ++ clock_res_id = I2C6_K; ++ break; ++ case STM32MP1_SHRES_RTC: ++ clock_res_id = RTC; ++ break; ++ default: ++ /* No clock resource dependency */ ++ return; ++ } ++ ++ stm32mp1_register_clock_parents_secure(clock_res_id); ++ } ++} ++ ++/* Register resource by ID */ ++void stm32mp_register_secure_periph(enum stm32mp_shres id) ++{ ++ register_periph(id, SHRES_SECURE); ++} ++ ++void stm32mp_register_non_secure_periph(enum stm32mp_shres id) ++{ ++ register_periph(id, SHRES_NON_SECURE); ++} ++ ++static void register_periph_iomem(uintptr_t base, unsigned int state) ++{ ++ enum stm32mp_shres id; ++ ++ switch (base) { ++ case CRYP1_BASE: ++ id = STM32MP1_SHRES_CRYP1; ++ break; ++ case HASH1_BASE: ++ id = STM32MP1_SHRES_HASH1; ++ break; ++ case I2C4_BASE: ++ id = STM32MP1_SHRES_I2C4; ++ break; ++ case I2C6_BASE: ++ id = STM32MP1_SHRES_I2C6; ++ break; ++ case IWDG1_BASE: ++ id = STM32MP1_SHRES_IWDG1; ++ break; ++ case RNG1_BASE: ++ id = STM32MP1_SHRES_RNG1; ++ break; ++ case RTC_BASE: ++ id = STM32MP1_SHRES_RTC; ++ break; ++ case SPI6_BASE: ++ id = STM32MP1_SHRES_SPI6; ++ break; ++ case USART1_BASE: ++ id = STM32MP1_SHRES_USART1; ++ break; ++ ++ case GPIOA_BASE: ++ case GPIOB_BASE: ++ case GPIOC_BASE: ++ case GPIOD_BASE: ++ case GPIOE_BASE: ++ case GPIOF_BASE: ++ case GPIOG_BASE: ++ case GPIOH_BASE: ++ case GPIOI_BASE: ++ case GPIOJ_BASE: ++ case GPIOK_BASE: ++ case USART2_BASE: ++ case USART3_BASE: ++ case UART4_BASE: ++ case UART5_BASE: ++ case USART6_BASE: ++ case UART7_BASE: ++ case UART8_BASE: ++ case IWDG2_BASE: ++ /* Allow drivers to register some non-secure resources */ ++ VERBOSE("IO for non-secure resource 0x%x\n", ++ (unsigned int)base); ++ if (state != SHRES_NON_SECURE) { ++ panic(); ++ } ++ ++ return; ++ ++ default: ++ panic(); ++ } ++ ++ register_periph(id, state); ++} ++ ++void stm32mp_register_secure_periph_iomem(uintptr_t base) ++{ ++ register_periph_iomem(base, SHRES_SECURE); ++} ++ ++void stm32mp_register_non_secure_periph_iomem(uintptr_t base) ++{ ++ register_periph_iomem(base, SHRES_NON_SECURE); ++} ++ ++void stm32mp_register_secure_gpio(unsigned int bank, unsigned int pin) ++{ ++ switch (bank) { ++ case GPIO_BANK_Z: ++ register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_SECURE); ++ break; ++ default: ++ ERROR("GPIO bank %u cannot be secured\n", bank); ++ panic(); ++ } ++} ++ ++void stm32mp_register_non_secure_gpio(unsigned int bank, unsigned int pin) ++{ ++ switch (bank) { ++ case GPIO_BANK_Z: ++ register_periph(STM32MP1_SHRES_GPIOZ(pin), SHRES_NON_SECURE); ++ break; ++ default: ++ break; ++ } ++} ++ ++static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank) ++{ ++ unsigned int non_secure = 0U; ++ unsigned int i; ++ ++ lock_registering(); ++ ++ if (bank != GPIO_BANK_Z) { ++ return true; ++ } ++ ++ for (i = 0U; i < get_gpioz_nbpin(); i++) { ++ if (periph_is_non_secure(STM32MP1_SHRES_GPIOZ(i))) { ++ non_secure++; ++ } ++ } ++ ++ return non_secure == get_gpioz_nbpin(); ++} ++ ++static bool stm32mp_gpio_bank_is_secure(unsigned int bank) ++{ ++ unsigned int secure = 0U; ++ unsigned int i; ++ ++ lock_registering(); ++ ++ if (bank != GPIO_BANK_Z) { ++ return false; ++ } ++ ++ for (i = 0U; i < get_gpioz_nbpin(); i++) { ++ if (periph_is_secure(STM32MP1_SHRES_GPIOZ(i))) { ++ secure++; ++ } ++ } ++ ++ return secure == get_gpioz_nbpin(); ++} ++ ++bool stm32mp_nsec_can_access_clock(unsigned long clock_id) ++{ ++ enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT; ++ ++ switch (clock_id) { ++ case CK_CSI: ++ case CK_HSE: ++ case CK_HSE_DIV2: ++ case CK_HSI: ++ case CK_LSE: ++ case CK_LSI: ++ case PLL1_P: ++ case PLL1_Q: ++ case PLL1_R: ++ case PLL2_P: ++ case PLL2_Q: ++ case PLL2_R: ++ case PLL3_P: ++ case PLL3_Q: ++ case PLL3_R: ++ case RTCAPB: ++ return true; ++ case GPIOZ: ++ /* Allow clock access if at least one pin is non-secure */ ++ return !stm32mp_gpio_bank_is_secure(GPIO_BANK_Z); ++ case CRYP1: ++ shres_id = STM32MP1_SHRES_CRYP1; ++ break; ++ case HASH1: ++ shres_id = STM32MP1_SHRES_HASH1; ++ break; ++ case I2C4_K: ++ shres_id = STM32MP1_SHRES_I2C4; ++ break; ++ case I2C6_K: ++ shres_id = STM32MP1_SHRES_I2C6; ++ break; ++ case IWDG1: ++ shres_id = STM32MP1_SHRES_IWDG1; ++ break; ++ case RNG1_K: ++ shres_id = STM32MP1_SHRES_RNG1; ++ break; ++ case RTC: ++ shres_id = STM32MP1_SHRES_RTC; ++ break; ++ case SPI6_K: ++ shres_id = STM32MP1_SHRES_SPI6; ++ break; ++ case USART1_K: ++ shres_id = STM32MP1_SHRES_USART1; ++ break; ++ default: ++ return false; ++ } ++ ++ return periph_is_non_secure(shres_id); ++} ++ ++bool stm32mp_nsec_can_access_reset(unsigned int reset_id) ++{ ++ enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT; ++ ++ switch (reset_id) { ++ case CRYP1_R: ++ shres_id = STM32MP1_SHRES_CRYP1; ++ break; ++ case GPIOZ_R: ++ /* GPIOZ reset mandates all pins are non-secure */ ++ return stm32mp_gpio_bank_is_non_secure(GPIO_BANK_Z); ++ case HASH1_R: ++ shres_id = STM32MP1_SHRES_HASH1; ++ break; ++ case I2C4_R: ++ shres_id = STM32MP1_SHRES_I2C4; ++ break; ++ case I2C6_R: ++ shres_id = STM32MP1_SHRES_I2C6; ++ break; ++ case MCU_R: ++ shres_id = STM32MP1_SHRES_MCU; ++ break; ++ case MDMA_R: ++ shres_id = STM32MP1_SHRES_MDMA; ++ break; ++ case RNG1_R: ++ shres_id = STM32MP1_SHRES_RNG1; ++ break; ++ case SPI6_R: ++ shres_id = STM32MP1_SHRES_SPI6; ++ break; ++ case USART1_R: ++ shres_id = STM32MP1_SHRES_USART1; ++ break; ++ default: ++ return false; ++ } ++ ++ return periph_is_non_secure(shres_id); ++} ++ ++static bool mckprot_protects_periph(enum stm32mp_shres id) ++{ ++ switch (id) { ++ case STM32MP1_SHRES_MCU: ++ case STM32MP1_SHRES_PLL3: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++/* ETZPC configuration at drivers initialization completion */ ++static enum etzpc_decprot_attributes shres2decprot_attr(enum stm32mp_shres id) ++{ ++ assert((id < STM32MP1_SHRES_GPIOZ(0)) || ++ (id > STM32MP1_SHRES_GPIOZ(7))); ++ ++ if (periph_is_non_secure(id)) { ++ return ETZPC_DECPROT_NS_RW; ++ } ++ ++ return ETZPC_DECPROT_S_RW; ++} ++ ++static void set_etzpc_secure_configuration(void) ++{ ++ /* Some system peripherals shall be secure */ ++ etzpc_configure_decprot(STM32MP1_ETZPC_STGENC_ID, ETZPC_DECPROT_S_RW); ++ etzpc_configure_decprot(STM32MP1_ETZPC_BKPSRAM_ID, ETZPC_DECPROT_S_RW); ++ etzpc_configure_decprot(STM32MP1_ETZPC_DDRCTRL_ID, ++ ETZPC_DECPROT_NS_R_S_W); ++ etzpc_configure_decprot(STM32MP1_ETZPC_DDRPHYC_ID, ++ ETZPC_DECPROT_NS_R_S_W); ++ ++ /* Configure ETZPC with peripheral registering */ ++ etzpc_configure_decprot(STM32MP1_ETZPC_CRYP1_ID, ++ shres2decprot_attr(STM32MP1_SHRES_CRYP1)); ++ etzpc_configure_decprot(STM32MP1_ETZPC_HASH1_ID, ++ shres2decprot_attr(STM32MP1_SHRES_HASH1)); ++ etzpc_configure_decprot(STM32MP1_ETZPC_I2C4_ID, ++ shres2decprot_attr(STM32MP1_SHRES_I2C4)); ++ etzpc_configure_decprot(STM32MP1_ETZPC_I2C6_ID, ++ shres2decprot_attr(STM32MP1_SHRES_I2C6)); ++ etzpc_configure_decprot(STM32MP1_ETZPC_IWDG1_ID, ++ shres2decprot_attr(STM32MP1_SHRES_IWDG1)); ++ etzpc_configure_decprot(STM32MP1_ETZPC_RNG1_ID, ++ shres2decprot_attr(STM32MP1_SHRES_RNG1)); ++ etzpc_configure_decprot(STM32MP1_ETZPC_USART1_ID, ++ shres2decprot_attr(STM32MP1_SHRES_USART1)); ++ etzpc_configure_decprot(STM32MP1_ETZPC_SPI6_ID, ++ shres2decprot_attr(STM32MP1_SHRES_SPI6)); ++} ++ ++static void check_rcc_secure_configuration(void) ++{ ++ uint32_t n; ++ uint32_t error = 0U; ++ bool mckprot = stm32mp1_rcc_is_mckprot(); ++ bool secure = stm32mp1_rcc_is_secure(); ++ ++ for (n = 0U; n < ARRAY_SIZE(shres_state); n++) { ++ if (shres_state[n] != SHRES_SECURE) { ++ continue; ++ } ++ ++ if (!secure || (mckprot_protects_periph(n) && (!mckprot))) { ++ ERROR("RCC %s MCKPROT %s and %s secure\n", ++ secure ? "secure" : "non-secure", ++ mckprot ? "set" : "not set", ++ shres2str_id(n)); ++ error++; ++ } ++ } ++ ++ if (error != 0U) { ++ panic(); ++ } ++} ++ ++static void set_gpio_secure_configuration(void) ++{ ++ uint32_t pin; ++ ++ for (pin = 0U; pin < get_gpioz_nbpin(); pin++) { ++ bool secure_state = periph_is_secure(STM32MP1_SHRES_GPIOZ(pin)); ++ ++ set_gpio_secure_cfg(GPIO_BANK_Z, pin, secure_state); ++ } ++} ++ ++static void print_shared_resources_state(void) ++{ ++ unsigned int id; ++ ++ for (id = 0U; id < STM32MP1_SHRES_COUNT; id++) { ++ switch (shres_state[id]) { ++ case SHRES_SECURE: ++ INFO("stm32mp1 %s is secure\n", shres2str_id(id)); ++ break; ++ case SHRES_NON_SECURE: ++ case SHRES_UNREGISTERED: ++ VERBOSE("stm32mp %s is non-secure\n", shres2str_id(id)); ++ break; ++ default: ++ VERBOSE("stm32mp %s is invalid\n", shres2str_id(id)); ++ panic(); ++ } ++ } ++} ++ ++void stm32mp_lock_periph_registering(void) ++{ ++ registering_locked = true; ++ ++ print_shared_resources_state(); ++ ++ check_rcc_secure_configuration(); ++ set_etzpc_secure_configuration(); ++ set_gpio_secure_configuration(); ++} +-- +2.27.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0008-fix-for-ethernet.patch b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0008-fix-for-ethernet.patch new file mode 100644 index 0000000..e4f6cbb --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/arm-trusted-firmware/0008-fix-for-ethernet.patch @@ -0,0 +1,31 @@ +diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts +index 2eced8f53..e5b092be1 100644 +--- a/fdts/stm32mp157a-dk1.dts ++++ b/fdts/stm32mp157a-dk1.dts +@@ -245,7 +245,7 @@ + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK +- CLK_ETH_DISABLED ++ CLK_ETH_PLL4P + CLK_SDMMC12_PLL4P + CLK_DSI_DSIPLL + CLK_STGEN_HSE +@@ -297,10 +297,15 @@ + frac = < 0x1a04 >; + }; + +- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ ++ /* ++ * ETH_CLK required a 125MHz clock, so ++ * original: VCO = 594.0 MHz => P = 99, Q = 74, R = 74 ++ * current : VCO = 750.0 MHz => P =125, Q = 75, R = 75 ++ */ + pll4: st,pll@3 { +- cfg = < 3 98 5 7 7 PQR(1,1,1) >; ++ cfg = < 3 124 5 11 11 PQR(1,1,1) >; + }; ++ + }; + + &bsec { diff --git a/board/myna-player-odyssey/initramfs_patches/barebox/0001-dts-stm32mp157c-odyssey-add-partitions-and-state-framework-support.patch b/board/myna-player-odyssey/initramfs_patches/barebox/0001-dts-stm32mp157c-odyssey-add-partitions-and-state-framework-support.patch new file mode 100644 index 0000000..a7137db --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/barebox/0001-dts-stm32mp157c-odyssey-add-partitions-and-state-framework-support.patch @@ -0,0 +1,99 @@ +From f2c72e8b170f05390896fc845f28ca77dd8ee658 Mon Sep 17 00:00:00 2001 +From: Xogium +Date: Wed, 29 Jul 2020 23:41:35 +0200 +Subject: [PATCH 1/4] dts: stm32mp157c-odyssey: add partitions and state + framework support. + +--- + arch/arm/dts/stm32mp157c-odyssey.dts | 68 ++++++++++++++++++++++++++++ + 1 file changed, 68 insertions(+) + +diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts +index 0e395bdec..8b570443b 100644 +--- a/arch/arm/dts/stm32mp157c-odyssey.dts ++++ b/arch/arm/dts/stm32mp157c-odyssey.dts +@@ -7,6 +7,10 @@ + #include "stm32mp151.dtsi" + + / { ++ aliases { ++ state = &state; ++ }; ++ + chosen { + environment-sd { + compatible = "barebox,environment"; +@@ -19,6 +23,70 @@ + device-path = &sdmmc2, "partname:barebox-environment"; + status = "disabled"; + }; ++ ++ state: state { ++ magic = <0x12222013>; ++ compatible = "barebox,state"; ++ backend-type = "raw"; ++ backend = <&state_mmc>; ++ backend-stridesize = <1024>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ bootstate { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ system0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ remaining_attempts { ++ reg = <0x0 0x4>; ++ type = "uint32"; ++ default = <3>; ++ }; ++ priority { ++ reg = <0x4 0x4>; ++ type = "uint32"; ++ default = <21>; ++ }; ++ }; ++ system1 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ remaining_attempts { ++ reg = <0x10 0x4>; ++ type = "uint32"; ++ default = <3>; ++ }; ++ priority { ++ reg = <0x14 0x4>; ++ type = "uint32"; ++ default = <20>; ++ }; ++ }; ++ }; ++ last_chosen { ++ reg = <0x20 0x4>; ++ type = "uint32"; ++ }; ++ }; ++ }; ++}; ++ ++&sdmmc2 { ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #size-cells = <1>; ++ #address-cells = <1>; ++ ++ state_mmc: partition@14400 { ++ label = "state"; ++ reg = <0x14400 0x30000>; ++ }; + }; + }; + +-- +2.28.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/barebox/0001-dts-stm32mp157c-odyssey-fix-location-of-last_chosen.patch b/board/myna-player-odyssey/initramfs_patches/barebox/0001-dts-stm32mp157c-odyssey-fix-location-of-last_chosen.patch new file mode 100644 index 0000000..6e16fd8 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/barebox/0001-dts-stm32mp157c-odyssey-fix-location-of-last_chosen.patch @@ -0,0 +1,32 @@ +From 09d292d3a1cc99047a98916a1aad8ece2ce18954 Mon Sep 17 00:00:00 2001 +From: Xogium +Date: Sun, 2 Aug 2020 12:49:35 +0200 +Subject: [PATCH 4/4] dts: stm32mp157c-odyssey.dts: fix location of last_chosen + node. + +--- + arch/arm/dts/stm32mp157c-odyssey.dts | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts +index 182a5149d..1e2510cdc 100644 +--- a/arch/arm/dts/stm32mp157c-odyssey.dts ++++ b/arch/arm/dts/stm32mp157c-odyssey.dts +@@ -67,10 +67,10 @@ + default = <20>; + }; + }; +- }; +- last_chosen { +- reg = <0x20 0x4>; +- type = "uint32"; ++ last_chosen { ++ reg = <0x20 0x4>; ++ type = "uint32"; ++ }; + }; + }; + }; +-- +2.28.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/barebox/0002-Revert-fs-free-inodes-we-no-longer-need.patch b/board/myna-player-odyssey/initramfs_patches/barebox/0002-Revert-fs-free-inodes-we-no-longer-need.patch new file mode 100644 index 0000000..21836a5 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/barebox/0002-Revert-fs-free-inodes-we-no-longer-need.patch @@ -0,0 +1,33 @@ +From 3eabdda706a8124e90cc1b2e6af918e6439dee6b Mon Sep 17 00:00:00 2001 +From: Jookia +Date: Tue, 4 Aug 2020 10:21:11 +1000 +Subject: [PATCH 2/4] Revert "fs: free inodes we no longer need" + +This reverts commit 43902e57633f5dd9bc71f1a30d69d7bc0f49dc6b. +--- + fs/fs.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/fs/fs.c b/fs/fs.c +index e04cadfe5..cecb3d70e 100644 +--- a/fs/fs.c ++++ b/fs/fs.c +@@ -1090,12 +1090,10 @@ void iput(struct inode *inode) + if (!inode) + return; + +- inode->i_count--; ++ if (!inode->i_count) ++ return; + +- if (!inode->i_count) { +- list_del(&inode->i_sb_list); +- destroy_inode(inode); +- } ++ inode->i_count--; + } + + struct inode *iget(struct inode *inode) +-- +2.28.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/barebox/0003-dts-stm32mp157c-odyssey-Add-Ethernet-support.patch b/board/myna-player-odyssey/initramfs_patches/barebox/0003-dts-stm32mp157c-odyssey-Add-Ethernet-support.patch new file mode 100644 index 0000000..cfffbb2 --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/barebox/0003-dts-stm32mp157c-odyssey-Add-Ethernet-support.patch @@ -0,0 +1,48 @@ +From 5011a3d9cbfa734a34718cc2471ef481550b3032 Mon Sep 17 00:00:00 2001 +From: Jookia +Date: Tue, 4 Aug 2020 10:21:47 +1000 +Subject: [PATCH 3/4] dts: stm32mp157c-odyssey: Add Ethernet support + +This uses PLL4_P as the internal Ethernet clock, so ATF or U-Boot must +clock PLL4 to 750MHz for this to work. +--- + arch/arm/dts/stm32mp157c-odyssey.dts | 26 ++++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts +index 8b570443b..182a5149d 100644 +--- a/arch/arm/dts/stm32mp157c-odyssey.dts ++++ b/arch/arm/dts/stm32mp157c-odyssey.dts +@@ -93,3 +93,29 @@ + &phy0 { + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + }; ++ ++ðernet0 { ++ status = "okay"; ++ pinctrl-0 = <ðernet0_rgmii_pins_a>; ++ pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ phy-mode = "rgmii-id"; ++ max-speed = <1000>; ++ phy-handle = <&phy0>; ++ assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; ++ assigned-clock-parents = <&rcc PLL4_P>; ++ assigned-clock-rates = <125000000>; ++ st,eth-clk-sel; ++ ++ mdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: ethernet-phy@7 { /* KSZ9031RN */ ++ reg = <7>; ++ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <300>; ++ }; ++ }; ++}; +-- +2.28.0 + diff --git a/board/myna-player-odyssey/initramfs_patches/linux/0001-dt-bindings-vendor-prefixes-add-Seeed-Studio.patch b/board/myna-player-odyssey/initramfs_patches/linux/0001-dt-bindings-vendor-prefixes-add-Seeed-Studio.patch new file mode 100644 index 0000000..af9007c --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/linux/0001-dt-bindings-vendor-prefixes-add-Seeed-Studio.patch @@ -0,0 +1,160 @@ +From patchwork Fri Jul 31 14:30:51 2020 +Content-Type: text/plain; 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+ Fri, 31 Jul 2020 07:31:06 -0700 (PDT) +From: Marcin Sloniewski +To: linux-arm-kernel@lists.infradead.org +Subject: [PATCH v6 1/3] dt-bindings: vendor-prefixes: add Seeed Studio +Date: Fri, 31 Jul 2020 16:30:51 +0200 +Message-Id: <20200731143053.44866-1-marcin.sloniewski@gmail.com> +X-Mailer: git-send-email 2.27.0 +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200731_103111_656264_F6F92A11 +X-CRM114-Status: GOOD ( 11.66 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, + no trust [2a00:1450:4864:20:0:0:0:641 listed in] + [list.dnswl.org] + 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail + provider [marcin.sloniewski[at]gmail.com] + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Cc: robh@kernel.org, a.fatoum@pengutronix.de, alexandre.torgue@st.com, + stephan@gerhold.net, mani@kernel.org, heiko.stuebner@theobroma-systems.com, + linus.walleij@linaro.org, linux-kernel@vger.kernel.org, lkundrak@v3.sk, + marcin.sloniewski@gmail.com, robh+dt@kernel.org, broonie@kernel.org, + mcoquelin.stm32@gmail.com, allen.chen@ite.com.tw, sam@ravnborg.org, + linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org + +Add the "seeed" vendor prefix for Seeed Technology Co., Ltd +Website: https://www.seeedstudio.com/ + +Signed-off-by: Marcin Sloniewski +Acked-by: Rob Herring +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index 9aeab66be85f..7dd03b3e9d3c 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -902,6 +902,8 @@ patternProperties: + description: Schindler + "^seagate,.*": + description: Seagate Technology PLC ++ "^seeed,.*": ++ description: Seeed Technology Co., Ltd + "^seirobotics,.*": + description: Shenzhen SEI Robotics Co., Ltd + "^semtech,.*": diff --git a/board/myna-player-odyssey/initramfs_patches/linux/0002-ARM-dts-stm32-add-initial-support-for-stm32mp157-odyssey-board.patch b/board/myna-player-odyssey/initramfs_patches/linux/0002-ARM-dts-stm32-add-initial-support-for-stm32mp157-odyssey-board.patch new file mode 100644 index 0000000..12ce50e --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/linux/0002-ARM-dts-stm32-add-initial-support-for-stm32mp157-odyssey-board.patch @@ -0,0 +1,592 @@ +From patchwork Fri Jul 31 14:30:53 2020 +Content-Type: text/plain; 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+ Fri, 31 Jul 2020 07:31:12 -0700 (PDT) +From: Marcin Sloniewski +To: linux-arm-kernel@lists.infradead.org +Subject: [PATCH v6 3/3] ARM: dts: stm32: add initial support for + stm32mp157-odyssey board +Date: Fri, 31 Jul 2020 16:30:53 +0200 +Message-Id: <20200731143053.44866-3-marcin.sloniewski@gmail.com> +X-Mailer: git-send-email 2.27.0 +In-Reply-To: <20200731143053.44866-1-marcin.sloniewski@gmail.com> +References: <20200731143053.44866-1-marcin.sloniewski@gmail.com> +MIME-Version: 1.0 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20200731_103115_377803_90B11FBF +X-CRM114-Status: GOOD ( 22.84 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, + no trust [2a00:1450:4864:20:0:0:0:544 listed in] + [list.dnswl.org] + 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail + provider [marcin.sloniewski[at]gmail.com] + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: +List-Unsubscribe: + , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: + , + +Cc: robh@kernel.org, a.fatoum@pengutronix.de, alexandre.torgue@st.com, + stephan@gerhold.net, mani@kernel.org, heiko.stuebner@theobroma-systems.com, + linus.walleij@linaro.org, linux-kernel@vger.kernel.org, lkundrak@v3.sk, + marcin.sloniewski@gmail.com, robh+dt@kernel.org, broonie@kernel.org, + mcoquelin.stm32@gmail.com, allen.chen@ite.com.tw, sam@ravnborg.org, + linux-stm32@st-md-mailman.stormreply.com, devicetree@vger.kernel.org +Sender: "linux-arm-kernel" +Errors-To: + linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org + +Add support for Seeed Studio's stm32mp157c odyssey board. +Board consists of SoM with stm32mp157c with 4GB eMMC and 512 MB DDR3 RAM +and carrier board with USB and ETH interfaces, SD card connector, +wifi and BT chip AP6236. + +In this patch only basic kernel boot is supported and interfacing +SD card and on-board eMMC. + +Signed-off-by: Marcin Sloniewski +--- + +Changes in v6: +- add reset pin for eth phy +- move pinctrl for sdmmc2 to stm32mp15-pinctrl.dtsi + +Changes in v5: +- fix schema for board's dts + +Changes in v4: +- add seeed,stm32mp157c-odyssey-som in compatible + for carrier board +- fix sdmmc2 interface by changing one of the pins + to use +- change eth phy address to 7 + +Changes in v3: +- fix compilation on tip of stm32-next + due to change in names for pinctrl +- fix deprecated binding for led node +- fix redundant "okay" statuses +- add phy part number for eth in comment + +Changes in v2: +- add new odyssey dts to Makefile + + + arch/arm/boot/dts/Makefile | 3 +- + arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 18 ++ + .../arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 276 ++++++++++++++++++ + arch/arm/boot/dts/stm32mp157c-odyssey.dts | 76 +++++ + 4 files changed, 372 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi + create mode 100644 arch/arm/boot/dts/stm32mp157c-odyssey.dts + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index e6a1cac0bfc7..a3ea2301c82c 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -1047,7 +1047,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ + stm32mp157c-dk2.dtb \ + stm32mp157c-ed1.dtb \ + stm32mp157c-ev1.dtb \ +- stm32mp157c-lxa-mc1.dtb ++ stm32mp157c-lxa-mc1.dtb \ ++ stm32mp157c-odyssey.dtb + dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ + sun4i-a10-ba10-tvbox.dtb \ +diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +index b5a66429670c..a47eaecbde42 100644 +--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi ++++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +@@ -1437,6 +1437,24 @@ pins { + }; + }; + ++ sdmmc2_d47_pins_d: sdmmc2-d47-3 { ++ pins { ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_D7 */ ++ }; ++ }; ++ ++ sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { ++ pins { ++ pinmux = , /* SDMMC2_D4 */ ++ , /* SDMMC2_D5 */ ++ , /* SDMMC2_D6 */ ++ ; /* SDMMC2_D7 */ ++ }; ++ }; ++ + sdmmc3_b4_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux = , /* SDMMC3_D0 */ +diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +new file mode 100644 +index 000000000000..6cf49a0a9e69 +--- /dev/null ++++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +@@ -0,0 +1,276 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) 2020 Marcin Sloniewski . ++ */ ++ ++/dts-v1/; ++ ++#include "stm32mp157.dtsi" ++#include "stm32mp15xc.dtsi" ++#include "stm32mp15-pinctrl.dtsi" ++#include "stm32mp15xxac-pinctrl.dtsi" ++#include ++#include ++#include ++ ++/ { ++ model = "Seeed Studio Odyssey-STM32MP157C SOM"; ++ compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; ++ ++ memory@c0000000 { ++ device_type = "memory"; ++ reg = <0xc0000000 0x20000000>; ++ }; ++ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ mcuram2: mcuram2@10000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10000000 0x40000>; ++ no-map; ++ }; ++ ++ vdev0vring0: vdev0vring0@10040000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10040000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0vring1: vdev0vring1@10041000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10041000 0x1000>; ++ no-map; ++ }; ++ ++ vdev0buffer: vdev0buffer@10042000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x10042000 0x4000>; ++ no-map; ++ }; ++ ++ mcuram: mcuram@30000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x30000000 0x40000>; ++ no-map; ++ }; ++ ++ retram: retram@38000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x38000000 0x10000>; ++ no-map; ++ }; ++ ++ gpu_reserved: gpu@d4000000 { ++ reg = <0xd4000000 0x4000000>; ++ no-map; ++ }; ++ }; ++ ++ led { ++ compatible = "gpio-leds"; ++ led-blue { ++ color = ; ++ function = LED_FUNCTION_HEARTBEAT; ++ gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++}; ++ ++&gpu { ++ contiguous-area = <&gpu_reserved>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins_a>; ++ i2c-scl-rising-time-ns = <185>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ /* spare dmas for other usage */ ++ /delete-property/dmas; ++ /delete-property/dma-names; ++ ++ pmic: stpmic@33 { ++ compatible = "st,stpmic1"; ++ reg = <0x33>; ++ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ regulators { ++ compatible = "st,stpmic1-regulators"; ++ ldo1-supply = <&v3v3>; ++ ldo3-supply = <&vdd_ddr>; ++ ldo6-supply = <&v3v3>; ++ pwr_sw1-supply = <&bst_out>; ++ pwr_sw2-supply = <&bst_out>; ++ ++ vddcore: buck1 { ++ regulator-name = "vddcore"; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_ddr: buck2 { ++ regulator-name = "vdd_ddr"; ++ regulator-min-microvolt = <1350000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-always-on; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ vdd: buck3 { ++ regulator-name = "vdd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ st,mask-reset; ++ regulator-initial-mode = <0>; ++ regulator-over-current-protection; ++ }; ++ ++ v3v3: buck4 { ++ regulator-name = "v3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ regulator-initial-mode = <0>; ++ }; ++ ++ v1v8_audio: ldo1 { ++ regulator-name = "v1v8_audio"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ v3v3_hdmi: ldo2 { ++ regulator-name = "v3v3_hdmi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ vtt_ddr: ldo3 { ++ regulator-name = "vtt_ddr"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <750000>; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ vdd_usb: ldo4 { ++ regulator-name = "vdd_usb"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ interrupts = ; ++ }; ++ ++ vdda: ldo5 { ++ regulator-name = "vdda"; ++ regulator-min-microvolt = <2900000>; ++ regulator-max-microvolt = <2900000>; ++ interrupts = ; ++ regulator-boot-on; ++ }; ++ ++ v1v2_hdmi: ldo6 { ++ regulator-name = "v1v2_hdmi"; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-always-on; ++ interrupts = ; ++ }; ++ ++ vref_ddr: vref_ddr { ++ regulator-name = "vref_ddr"; ++ regulator-always-on; ++ regulator-over-current-protection; ++ }; ++ ++ bst_out: boost { ++ regulator-name = "bst_out"; ++ interrupts = ; ++ }; ++ ++ vbus_otg: pwr_sw1 { ++ regulator-name = "vbus_otg"; ++ interrupts = ; ++ }; ++ ++ vbus_sw: pwr_sw2 { ++ regulator-name = "vbus_sw"; ++ interrupts = ; ++ regulator-active-discharge; ++ }; ++ }; ++ ++ onkey { ++ compatible = "st,stpmic1-onkey"; ++ interrupts = , ; ++ interrupt-names = "onkey-falling", "onkey-rising"; ++ power-off-time-sec = <10>; ++ }; ++ ++ watchdog { ++ compatible = "st,stpmic1-wdt"; ++ status = "disabled"; ++ }; ++ }; ++}; ++ ++&ipcc { ++ status = "okay"; ++}; ++ ++&iwdg2 { ++ timeout-sec = <32>; ++ status = "okay"; ++}; ++ ++&m4_rproc { ++ memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, ++ <&vdev0vring1>, <&vdev0buffer>; ++ mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; ++ mbox-names = "vq0", "vq1", "shutdown"; ++ interrupt-parent = <&exti>; ++ interrupts = <68 1>; ++ status = "okay"; ++}; ++ ++&rng1 { ++ status = "okay"; ++}; ++ ++&rtc { ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; ++ non-removable; ++ no-sd; ++ no-sdio; ++ st,neg-edge; ++ bus-width = <8>; ++ vmmc-supply = <&v3v3>; ++ vqmmc-supply = <&v3v3>; ++ mmc-ddr-3_3v; ++ status = "okay"; ++}; ++ +diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts +new file mode 100644 +index 000000000000..f2ac92f1ad10 +--- /dev/null ++++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts +@@ -0,0 +1,76 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * Copyright (C) 2020 Marcin Sloniewski . ++ */ ++ ++/dts-v1/; ++ ++#include "stm32mp157c-odyssey-som.dtsi" ++ ++/ { ++ model = "Seeed Studio Odyssey-STM32MP157C Board"; ++ compatible = "seeed,stm32mp157c-odyssey", ++ "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; ++ ++ aliases { ++ ethernet0 = ðernet0; ++ serial0 = &uart4; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++ðernet0 { ++ status = "okay"; ++ pinctrl-0 = <ðernet0_rgmii_pins_a>; ++ pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ phy-mode = "rgmii-id"; ++ max-speed = <1000>; ++ phy-handle = <&phy0>; ++ ++ mdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ phy0: ethernet-phy@7 { /* KSZ9031RN */ ++ reg = <7>; ++ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ ++ reset-assert-us = <10000>; ++ reset-deassert-us = <300>; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default", "sleep"; ++ pinctrl-0 = <&i2c1_pins_a>; ++ pinctrl-1 = <&i2c1_sleep_pins_a>; ++ i2c-scl-rising-time-ns = <100>; ++ i2c-scl-falling-time-ns = <7>; ++ status = "okay"; ++ /delete-property/dmas; ++ /delete-property/dma-names; ++}; ++ ++&sdmmc1 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc1_b4_pins_a>; ++ pinctrl-1 = <&sdmmc1_b4_od_pins_a>; ++ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; ++ cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ disable-wp; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ status = "okay"; ++}; ++ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart4_pins_a>; ++ status = "okay"; ++}; ++ diff --git a/board/myna-player-odyssey/initramfs_patches/linux/0003-ARM-dts-stm32mp157c-odyssey-fix-ethernet.patch b/board/myna-player-odyssey/initramfs_patches/linux/0003-ARM-dts-stm32mp157c-odyssey-fix-ethernet.patch new file mode 100644 index 0000000..41621cf --- /dev/null +++ b/board/myna-player-odyssey/initramfs_patches/linux/0003-ARM-dts-stm32mp157c-odyssey-fix-ethernet.patch @@ -0,0 +1,41 @@ +diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +index 2f75b631feac..afeb85ac66ca 100644 +--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi ++++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +@@ -120,8 +120,7 @@ + + ethernet0_rgmii_pins_a: rgmii-0 { + pins1 { +- pinmux = , /* ETH_RGMII_CLK125 */ +- , /* ETH_RGMII_GTX_CLK */ ++ pinmux = , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ +diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts +index f2ac92f1ad10..ac9fa784419d 100644 +--- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts ++++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts +@@ -30,6 +30,22 @@ + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; ++ assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; ++ assigned-clock-parents = <&rcc PLL4_P>; ++ assigned-clock-rates = <125000000>; ++ st,eth-clk-sel; ++ clock-names = "stmmaceth", ++ "mac-clk-tx", ++ "mac-clk-rx", ++ "eth-ck", ++ "syscfg-clk", ++ "ethstp"; ++ clocks = <&rcc ETHMAC>, ++ <&rcc ETHTX>, ++ <&rcc ETHRX>, ++ <&rcc ETHCK_K>, ++ <&rcc SYSCFG>, ++ <&rcc ETHSTP>; + + mdio0 { + #address-cells = <1>; diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/fstab b/board/myna-player-odyssey/rootfs_overlay/etc/fstab new file mode 100644 index 0000000..97c2706 --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/fstab @@ -0,0 +1 @@ +PARTLABEL=Rauc /rauc ext4 rw,relatime,data=journal,noauto,x-systemd.automount diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/pam.d/login b/board/myna-player-odyssey/rootfs_overlay/etc/pam.d/login new file mode 100644 index 0000000..e415a11 --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/pam.d/login @@ -0,0 +1,12 @@ +auth required pam_unix.so nullok + +account required pam_unix.so + +password required pam_unix.so nullok + +# session required pam_selinux.so close +session required pam_limits.so +session required pam_env.so +session required pam_unix.so +# session required pam_selinux.so open +-session optional pam_systemd.so diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/pam.d/sshd b/board/myna-player-odyssey/rootfs_overlay/etc/pam.d/sshd new file mode 100644 index 0000000..95cbe70 --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/pam.d/sshd @@ -0,0 +1,8 @@ +#%PAM-1.0 +auth required /lib/security/pam_unix.so shadow nodelay +account required /lib/security/pam_nologin.so +account required /lib/security/pam_unix.so +password required /lib/security/pam_unix.so shadow nullok use_authtok +session required /lib/security/pam_unix.so +session required /lib/security/pam_limits.so +-session optional pam_systemd.so diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/profile b/board/myna-player-odyssey/rootfs_overlay/etc/profile new file mode 100644 index 0000000..a3de2f0 --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/profile @@ -0,0 +1,12 @@ +export PATH=/bin:/sbin:/usr/bin:/usr/sbin +export PS1='[\u@\h \W]\$ ' +export PAGER='/bin/less ' +export EDITOR='/bin/nano' + +# Source configuration files from /etc/profile.d +for i in /etc/profile.d/*.sh ; do + if [ -r "$i" ]; then + . $i + fi + unset i +done diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/rauc/system.conf b/board/myna-player-odyssey/rootfs_overlay/etc/rauc/system.conf new file mode 100644 index 0000000..03c286a --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/rauc/system.conf @@ -0,0 +1,20 @@ +[system] +compatible=LuminaSensum MynaPlayer +bootloader=barebox +statusfile=/rauc/slot.status +max-bundle-download-size=40000000 + +[keyring] +path=/etc/rauc/keyring.pem + +[slot.rootfs.1] +type=ext4 +device=/dev/disk/by-partlabel/PrimaryRootfs +bootname=system0 +resize=true + +[slot.rootfs.2] +type=ext4 +device=/dev/disk/by-partlabel/SecondaryRootfs +bootname=system1 +resize=true diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/ssh/sshd_config b/board/myna-player-odyssey/rootfs_overlay/etc/ssh/sshd_config new file mode 100644 index 0000000..084d18a --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/ssh/sshd_config @@ -0,0 +1,118 @@ +# $OpenBSD: sshd_config,v 1.101 2017/03/14 07:19:07 djm Exp $ + +# This is the sshd server system-wide configuration file. See +# sshd_config(5) for more information. + +# This sshd was compiled with PATH=/usr/bin:/bin:/usr/sbin:/sbin + +# The strategy used for options in the default sshd_config shipped with +# OpenSSH is to specify options with their default value where +# possible, but leave them commented. Uncommented options override the +# default value. + +Port 18430 +#AddressFamily any +#ListenAddress 0.0.0.0 +#ListenAddress :: + +#HostKey /etc/ssh/ssh_host_rsa_key +#HostKey /etc/ssh/ssh_host_dsa_key +#HostKey /etc/ssh/ssh_host_ecdsa_key +#HostKey /data/ssh/ssh_host_ed25519_key + +# Ciphers and keying +#RekeyLimit default none + +# Logging +#SyslogFacility AUTH +#LogLevel INFO + +# Authentication: + +#LoginGraceTime 2m +PermitRootLogin no +#StrictModes yes +#MaxAuthTries 6 +#MaxSessions 10 + +PubkeyAuthentication yes + +# The default is to check both .ssh/authorized_keys and .ssh/authorized_keys2 +# but this is overridden so installations will only check .ssh/authorized_keys +AuthorizedKeysFile .ssh/authorized_keys + +#AuthorizedPrincipalsFile none + +#AuthorizedKeysCommand none +#AuthorizedKeysCommandUser nobody + +# For this to work you will also need host keys in /etc/ssh/ssh_known_hosts +#HostbasedAuthentication no +# Change to yes if you don't trust ~/.ssh/known_hosts for +# HostbasedAuthentication +#IgnoreUserKnownHosts no +# Don't read the user's ~/.rhosts and ~/.shosts files +#IgnoreRhosts yes + +# To disable tunneled clear text passwords, change to no here! +# PasswordAuthentication no +#PermitEmptyPasswords no + +# Change to no to disable s/key passwords +ChallengeResponseAuthentication no + +# Kerberos options +#KerberosAuthentication no +#KerberosOrLocalPasswd yes +#KerberosTicketCleanup yes +#KerberosGetAFSToken no + +# GSSAPI options +#GSSAPIAuthentication no +#GSSAPICleanupCredentials yes + +# Set this to 'yes' to enable PAM authentication, account processing, +# and session processing. If this is enabled, PAM authentication will +# be allowed through the ChallengeResponseAuthentication and +# PasswordAuthentication. Depending on your PAM configuration, +# PAM authentication via ChallengeResponseAuthentication may bypass +# the setting of "PermitRootLogin without-password". +# If you just want the PAM account and session checks to run without +# PAM authentication, then enable this but set PasswordAuthentication +# and ChallengeResponseAuthentication to 'no'. +UsePAM yes + +#AllowAgentForwarding yes +#AllowTcpForwarding yes +#GatewayPorts no +#X11Forwarding no +#X11DisplayOffset 10 +#X11UseLocalhost yes +#PermitTTY yes +PrintMotd no # pam does that +#PrintLastLog yes +#TCPKeepAlive yes +#UseLogin no +#PermitUserEnvironment no +#Compression delayed +#ClientAliveInterval 0 +#ClientAliveCountMax 3 +#UseDNS no +#PidFile /run/sshd.pid +#MaxStartups 10:30:100 +#PermitTunnel no +#ChrootDirectory none +#VersionAddendum none + +# no default banner path +#Banner none + +# override default of no subsystems +Subsystem sftp /usr/libexec/sftp-server + +# Example of overriding settings on a per-user basis +#Match User anoncvs +# X11Forwarding no +# AllowTcpForwarding no +# PermitTTY no +# ForceCommand cvs server diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system.conf.d/watchdog.conf b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system.conf.d/watchdog.conf new file mode 100644 index 0000000..aa62c1f --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system.conf.d/watchdog.conf @@ -0,0 +1,2 @@ +[Manager] +RuntimeWatchdogSec=30 diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/rngd.service.d/override.conf b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/rngd.service.d/override.conf new file mode 100644 index 0000000..f14eaff --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/rngd.service.d/override.conf @@ -0,0 +1,3 @@ +[Service] +ExecStart= +ExecStart=/sbin/rngd -f -x jitter diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/sshd.service b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/sshd.service new file mode 100644 index 0000000..993b0e6 --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/sshd.service @@ -0,0 +1,14 @@ +[Unit] +Description=OpenSSH Daemon +Wants=sshdgenkeys.service +After=sshdgenkeys.service +After=network.target + +[Service] +ExecStart=/sbin/sshd -D +ExecReload=/bin/kill -HUP $MAINPID +KillMode=process +Type=notify + +[Install] +WantedBy=multi-user.target diff --git a/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/sshdgenkeys.service b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/sshdgenkeys.service new file mode 100644 index 0000000..77e73a1 --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/etc/systemd/system/sshdgenkeys.service @@ -0,0 +1,9 @@ +[Unit] +Description=SSH Key Generation +ConditionPathExists=|!/etc/ssh/ssh_host_ed25519_key +ConditionPathExists=|!/etc/ssh/ssh_host_ed25519_key.pub + +[Service] +ExecStart=/usr/bin/ssh-keygen -t ed25519 -f /etc/ssh/ssh_host_ed25519_key -q -N "" +Type=oneshot +RemainAfterExit=yes diff --git a/board/myna-player-odyssey/rootfs_overlay/loader/entries/myna-player.conf b/board/myna-player-odyssey/rootfs_overlay/loader/entries/myna-player.conf new file mode 100644 index 0000000..eb0794d --- /dev/null +++ b/board/myna-player-odyssey/rootfs_overlay/loader/entries/myna-player.conf @@ -0,0 +1,6 @@ +title MynaPlayer +version 5.8rc7 +linux boot/zImage +devicetree boot/stm32mp157c-odyssey.dtb +options rootfstype=ext4 rw earlycon quiet +linux-appendroot true diff --git a/board/myna-player-odyssey/rootfs_patches/dt-utils/0001-add-amba.patch b/board/myna-player-odyssey/rootfs_patches/dt-utils/0001-add-amba.patch new file mode 100644 index 0000000..fb3fbeb --- /dev/null +++ b/board/myna-player-odyssey/rootfs_patches/dt-utils/0001-add-amba.patch @@ -0,0 +1,12 @@ +diff --git a/src/libdt.c b/src/libdt.c +index 4638678..fbbd5a2 100644 +--- a/src/libdt.c ++++ b/src/libdt.c +@@ -2057,6 +2057,7 @@ static void of_scan_udev_devices(void) + udev_enumerate_add_match_subsystem(enumerate, "i2c"); + udev_enumerate_add_match_subsystem(enumerate, "spi"); + udev_enumerate_add_match_subsystem(enumerate, "mtd"); ++ udev_enumerate_add_match_subsystem(enumerate, "amba"); + udev_enumerate_scan_devices(enumerate); + devices = udev_enumerate_get_list_entry(enumerate); + diff --git a/board/myna-player-odyssey/rootfs_patches/openssh-systemd/0001-systemd-readyness.patch b/board/myna-player-odyssey/rootfs_patches/openssh-systemd/0001-systemd-readyness.patch new file mode 100644 index 0000000..c3b8f9f --- /dev/null +++ b/board/myna-player-odyssey/rootfs_patches/openssh-systemd/0001-systemd-readyness.patch @@ -0,0 +1,84 @@ +From d23f57ff1e85ded1298886968c9949282c4cba08 Mon Sep 17 00:00:00 2001 +From: Michael Biebl +Date: Mon, 21 Dec 2015 16:08:47 +0000 +Subject: Add systemd readiness notification support + +Bug-Debian: https://bugs.debian.org/778913 +Forwarded: no +Last-Update: 2017-08-22 + +Patch-Name: systemd-readiness.patch +--- + configure.ac | 24 ++++++++++++++++++++++++ + sshd.c | 9 +++++++++ + 2 files changed, 33 insertions(+) + +diff --git a/configure.ac b/configure.ac +index ce16e7758..de140f578 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -4526,6 +4526,29 @@ AC_ARG_WITH([kerberos5], + AC_SUBST([GSSLIBS]) + AC_SUBST([K5LIBS]) + ++# Check whether user wants systemd support ++SYSTEMD_MSG="no" ++AC_ARG_WITH(systemd, ++ [ --with-systemd Enable systemd support], ++ [ if test "x$withval" != "xno" ; then ++ AC_PATH_TOOL([PKGCONFIG], [pkg-config], [no]) ++ if test "$PKGCONFIG" != "no"; then ++ AC_MSG_CHECKING([for libsystemd]) ++ if $PKGCONFIG --exists libsystemd; then ++ SYSTEMD_CFLAGS=`$PKGCONFIG --cflags libsystemd` ++ SYSTEMD_LIBS=`$PKGCONFIG --libs libsystemd` ++ CPPFLAGS="$CPPFLAGS $SYSTEMD_CFLAGS" ++ SSHDLIBS="$SSHDLIBS $SYSTEMD_LIBS" ++ AC_MSG_RESULT([yes]) ++ AC_DEFINE(HAVE_SYSTEMD, 1, [Define if you want systemd support.]) ++ SYSTEMD_MSG="yes" ++ else ++ AC_MSG_RESULT([no]) ++ fi ++ fi ++ fi ] ++) ++ + # Looking for programs, paths and files + + PRIVSEP_PATH=/var/empty +@@ -5332,6 +5355,7 @@ echo " libldns support: $LDNS_MSG" + echo " Solaris process contract support: $SPC_MSG" + echo " Solaris project support: $SP_MSG" + echo " Solaris privilege support: $SPP_MSG" ++echo " systemd support: $SYSTEMD_MSG" + echo " IP address in \$DISPLAY hack: $DISPLAY_HACK_MSG" + echo " Translate v4 in v6 hack: $IPV4_IN6_HACK_MSG" + echo " BSD Auth support: $BSD_AUTH_MSG" +diff --git a/sshd.c b/sshd.c +index 1e7ece588..48162b629 100644 +--- a/sshd.c ++++ b/sshd.c +@@ -85,6 +85,10 @@ + #include + #endif + ++#ifdef HAVE_SYSTEMD ++#include ++#endif ++ + #include "xmalloc.h" + #include "ssh.h" + #include "ssh2.h" +@@ -1946,6 +1950,11 @@ main(int ac, char **av) + } + } + ++#ifdef HAVE_SYSTEMD ++ /* Signal systemd that we are ready to accept connections */ ++ sd_notify(0, "READY=1"); ++#endif ++ + /* Accept a connection and return in a forked child */ + server_accept_loop(&sock_in, &sock_out, + &newsock, config_s); diff --git a/board/myna-player-odyssey/rootfs_patches/polkit-duktape/0001-add-duktape-support.patch b/board/myna-player-odyssey/rootfs_patches/polkit-duktape/0001-add-duktape-support.patch new file mode 100644 index 0000000..e60734f --- /dev/null +++ b/board/myna-player-odyssey/rootfs_patches/polkit-duktape/0001-add-duktape-support.patch @@ -0,0 +1,1512 @@ +From b7c8fd25eb5b978c4572dadb7e1a25b8aa6bbdae Mon Sep 17 00:00:00 2001 +From: Wu Xiaotian +Date: Wed, 24 Jul 2019 15:55:17 +0800 +Subject: [PATCH] Add duktape as javascript engine. + +--- + configure.ac | 28 +- + src/polkitbackend/Makefile.am | 14 +- + .../polkitbackendduktapeauthority.c | 1402 +++++++++++++++++ + 3 files changed, 1436 insertions(+), 8 deletions(-) + create mode 100644 src/polkitbackend/polkitbackendduktapeauthority.c + +diff --git a/configure.ac b/configure.ac +index 5cedb4e..6c27486 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -79,11 +79,22 @@ PKG_CHECK_MODULES(GLIB, [gmodule-2.0 gio-unix-2.0 >= 2.30.0]) + AC_SUBST(GLIB_CFLAGS) + AC_SUBST(GLIB_LIBS) + +-PKG_CHECK_MODULES(LIBJS, [mozjs-60]) +- +-AC_SUBST(LIBJS_CFLAGS) +-AC_SUBST(LIBJS_CXXFLAGS) +-AC_SUBST(LIBJS_LIBS) ++dnl --------------------------------------------------------------------------- ++dnl - Check javascript backend ++dnl --------------------------------------------------------------------------- ++AC_ARG_WITH(duktape, AS_HELP_STRING([--with-duktape],[Use Duktape as javascript backend]),with_duktape=yes,with_duktape=no) ++AS_IF([test x${with_duktape} == xyes], [ ++ PKG_CHECK_MODULES(LIBJS, [duktape >= 2.0.0 ]) ++ AC_SUBST(LIBJS_CFLAGS) ++ AC_SUBST(LIBJS_LIBS) ++], [ ++ PKG_CHECK_MODULES(LIBJS, [mozjs-60]) ++ ++ AC_SUBST(LIBJS_CFLAGS) ++ AC_SUBST(LIBJS_CXXFLAGS) ++ AC_SUBST(LIBJS_LIBS) ++]) ++AM_CONDITIONAL(USE_DUKTAPE, [test x$with_duktape == xyes], [Using duktape as javascript engine library]) + + EXPAT_LIB="" + AC_ARG_WITH(expat, [ --with-expat= Use expat from here], +@@ -580,6 +591,13 @@ echo " + PAM support: ${have_pam} + systemdsystemunitdir: ${systemdsystemunitdir} + polkitd user: ${POLKITD_USER}" ++if test "x${with_duktape}" = xyes; then ++echo " ++ Javascript engine: Duktape" ++else ++echo " ++ Javascript engine: Mozjs" ++fi + + if test "$have_pam" = yes ; then + echo " +diff --git a/src/polkitbackend/Makefile.am b/src/polkitbackend/Makefile.am +index e48b739..9572b06 100644 +--- a/src/polkitbackend/Makefile.am ++++ b/src/polkitbackend/Makefile.am +@@ -33,7 +33,7 @@ libpolkit_backend_1_la_SOURCES = \ + polkitbackendprivate.h \ + polkitbackendauthority.h polkitbackendauthority.c \ + polkitbackendinteractiveauthority.h polkitbackendinteractiveauthority.c \ +- polkitbackendjsauthority.h polkitbackendjsauthority.cpp \ ++ polkitbackendjsauthority.h \ + polkitbackendactionpool.h polkitbackendactionpool.c \ + polkitbackendactionlookup.h polkitbackendactionlookup.c \ + $(NULL) +@@ -51,19 +51,27 @@ libpolkit_backend_1_la_CFLAGS = \ + -D_POLKIT_BACKEND_COMPILATION \ + $(GLIB_CFLAGS) \ + $(LIBSYSTEMD_CFLAGS) \ +- $(LIBJS_CFLAGS) \ ++ $(LIBJS_CFLAGS) \ + $(NULL) + + libpolkit_backend_1_la_CXXFLAGS = $(libpolkit_backend_1_la_CFLAGS) + + libpolkit_backend_1_la_LIBADD = \ + $(GLIB_LIBS) \ ++ $(DUKTAPE_LIBS) \ + $(LIBSYSTEMD_LIBS) \ + $(top_builddir)/src/polkit/libpolkit-gobject-1.la \ + $(EXPAT_LIBS) \ +- $(LIBJS_LIBS) \ ++ $(LIBJS_LIBS) \ + $(NULL) + ++if USE_DUKTAPE ++libpolkit_backend_1_la_SOURCES += polkitbackendduktapeauthority.c ++libpolkit_backend_1_la_LIBADD += -lm ++else ++libpolkit_backend_1_la_SOURCES += polkitbackendjsauthority.cpp ++endif ++ + rulesdir = $(sysconfdir)/polkit-1/rules.d + rules_DATA = 50-default.rules + +diff --git a/src/polkitbackend/polkitbackendduktapeauthority.c b/src/polkitbackend/polkitbackendduktapeauthority.c +new file mode 100644 +index 0000000..ae98453 +--- /dev/null ++++ b/src/polkitbackend/polkitbackendduktapeauthority.c +@@ -0,0 +1,1402 @@ ++/* ++ * Copyright (C) 2008-2012 Red Hat, Inc. ++ * Copyright (C) 2015 Tangent Space ++ * Copyright (C) 2019 Wu Xiaotian ++ * ++ * This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU Lesser General Public ++ * License as published by the Free Software Foundation; either ++ * version 2 of the License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * Lesser General Public License for more details. ++ * ++ * You should have received a copy of the GNU Lesser General ++ * Public License along with this library; if not, write to the ++ * Free Software Foundation, Inc., 59 Temple Place, Suite 330, ++ * Boston, MA 02111-1307, USA. ++ * ++ * Author: David Zeuthen ++ */ ++ ++#include "config.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "polkitbackendjsauthority.h" ++ ++#include ++ ++#ifdef HAVE_LIBSYSTEMD ++#include ++#endif /* HAVE_LIBSYSTEMD */ ++ ++#include "initjs.h" /* init.js */ ++#include "duktape.h" ++ ++/** ++ * SECTION:polkitbackendjsauthority ++ * @title: PolkitBackendJsAuthority ++ * @short_description: JS Authority ++ * @stability: Unstable ++ * ++ * An implementation of #PolkitBackendAuthority that reads and ++ * evalates Javascript files and supports interaction with ++ * authentication agents (virtue of being based on ++ * #PolkitBackendInteractiveAuthority). ++ */ ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++struct _PolkitBackendJsAuthorityPrivate ++{ ++ gchar **rules_dirs; ++ GFileMonitor **dir_monitors; /* NULL-terminated array of GFileMonitor instances */ ++ duk_context *cx; ++}; ++ ++#define WATCHDOG_TIMEOUT (15 * G_TIME_SPAN_SECOND) ++ ++static void utils_spawn (const gchar *const *argv, ++ guint timeout_seconds, ++ GCancellable *cancellable, ++ GAsyncReadyCallback callback, ++ gpointer user_data); ++ ++gboolean utils_spawn_finish (GAsyncResult *res, ++ gint *out_exit_status, ++ gchar **out_standard_output, ++ gchar **out_standard_error, ++ GError **error); ++ ++static void on_dir_monitor_changed (GFileMonitor *monitor, ++ GFile *file, ++ GFile *other_file, ++ GFileMonitorEvent event_type, ++ gpointer user_data); ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++enum ++{ ++ PROP_0, ++ PROP_RULES_DIRS, ++}; ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static GList *polkit_backend_js_authority_get_admin_auth_identities (PolkitBackendInteractiveAuthority *authority, ++ PolkitSubject *caller, ++ PolkitSubject *subject, ++ PolkitIdentity *user_for_subject, ++ gboolean subject_is_local, ++ gboolean subject_is_active, ++ const gchar *action_id, ++ PolkitDetails *details); ++ ++static PolkitImplicitAuthorization polkit_backend_js_authority_check_authorization_sync ( ++ PolkitBackendInteractiveAuthority *authority, ++ PolkitSubject *caller, ++ PolkitSubject *subject, ++ PolkitIdentity *user_for_subject, ++ gboolean subject_is_local, ++ gboolean subject_is_active, ++ const gchar *action_id, ++ PolkitDetails *details, ++ PolkitImplicitAuthorization implicit); ++ ++G_DEFINE_TYPE (PolkitBackendJsAuthority, polkit_backend_js_authority, POLKIT_BACKEND_TYPE_INTERACTIVE_AUTHORITY); ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static void ++polkit_backend_js_authority_init (PolkitBackendJsAuthority *authority) ++{ ++ authority->priv = G_TYPE_INSTANCE_GET_PRIVATE (authority, ++ POLKIT_BACKEND_TYPE_JS_AUTHORITY, ++ PolkitBackendJsAuthorityPrivate); ++} ++ ++static gint ++rules_file_name_cmp (const gchar *a, ++ const gchar *b) ++{ ++ gint ret; ++ const gchar *a_base; ++ const gchar *b_base; ++ ++ a_base = strrchr (a, '/'); ++ b_base = strrchr (b, '/'); ++ ++ g_assert (a_base != NULL); ++ g_assert (b_base != NULL); ++ a_base += 1; ++ b_base += 1; ++ ++ ret = g_strcmp0 (a_base, b_base); ++ if (ret == 0) ++ { ++ /* /etc wins over /usr */ ++ ret = g_strcmp0 (a, b); ++ g_assert (ret != 0); ++ } ++ ++ return ret; ++} ++ ++static void ++load_scripts (PolkitBackendJsAuthority *authority) ++{ ++ duk_context *cx = authority->priv->cx; ++ GList *files = NULL; ++ GList *l; ++ guint num_scripts = 0; ++ GError *error = NULL; ++ guint n; ++ ++ files = NULL; ++ ++ for (n = 0; authority->priv->rules_dirs != NULL && authority->priv->rules_dirs[n] != NULL; n++) ++ { ++ const gchar *dir_name = authority->priv->rules_dirs[n]; ++ GDir *dir = NULL; ++ ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Loading rules from directory %s", ++ dir_name); ++ ++ dir = g_dir_open (dir_name, ++ 0, ++ &error); ++ if (dir == NULL) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error opening rules directory: %s (%s, %d)", ++ error->message, g_quark_to_string (error->domain), error->code); ++ g_clear_error (&error); ++ } ++ else ++ { ++ const gchar *name; ++ while ((name = g_dir_read_name (dir)) != NULL) ++ { ++ if (g_str_has_suffix (name, ".rules")) ++ files = g_list_prepend (files, g_strdup_printf ("%s/%s", dir_name, name)); ++ } ++ g_dir_close (dir); ++ } ++ } ++ ++ files = g_list_sort (files, (GCompareFunc) rules_file_name_cmp); ++ ++ for (l = files; l != NULL; l = l->next) ++ { ++ const gchar *filename = l->data; ++ ++#if (DUK_VERSION >= 20000) ++ gchar *contents; ++ gsize length; ++ GError *error = NULL; ++ if (!g_file_get_contents (filename, &contents, &length, &error)){ ++ g_warning("Error when file contents of %s: %s\n", filename, error->message); ++ g_error_free (error); ++ continue; ++ } ++ if (duk_peval_lstring_noresult(cx, contents,length) != 0) ++#else ++ if (duk_peval_file_noresult (cx, filename) != 0) ++#endif ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error compiling script %s: %s", ++ filename, duk_safe_to_string (authority->priv->cx, -1)); ++#if (DUK_VERSION >= 20000) ++ g_free (contents); ++#endif ++ continue; ++ } ++#if (DUK_VERSION >= 20000) ++ g_free (contents); ++#endif ++ num_scripts++; ++ } ++ ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Finished loading, compiling and executing %d rules", ++ num_scripts); ++ g_list_free_full (files, g_free); ++} ++ ++static void ++reload_scripts (PolkitBackendJsAuthority *authority) ++{ ++ duk_context *cx = authority->priv->cx; ++ ++ duk_set_top (cx, 0); ++ duk_get_global_string (cx, "polkit"); ++ duk_push_string (cx, "_deleteRules"); ++ ++ duk_call_prop (cx, 0, 0); ++ ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Collecting garbage unconditionally..."); ++ ++ load_scripts (authority); ++ ++ /* Let applications know we have new rules... */ ++ g_signal_emit_by_name (authority, "changed"); ++} ++ ++static void ++on_dir_monitor_changed (GFileMonitor *monitor, ++ GFile *file, ++ GFile *other_file, ++ GFileMonitorEvent event_type, ++ gpointer user_data) ++{ ++ PolkitBackendJsAuthority *authority = POLKIT_BACKEND_JS_AUTHORITY (user_data); ++ ++ /* TODO: maybe rate-limit so storms of events are collapsed into one with a 500ms resolution? ++ * Because when editing a file with emacs we get 4-8 events.. ++ */ ++ ++ if (file != NULL) ++ { ++ gchar *name; ++ ++ name = g_file_get_basename (file); ++ ++ /* g_print ("event_type=%d file=%p name=%s\n", event_type, file, name); */ ++ if (!g_str_has_prefix (name, ".") && ++ !g_str_has_prefix (name, "#") && ++ g_str_has_suffix (name, ".rules") && ++ (event_type == G_FILE_MONITOR_EVENT_CREATED || ++ event_type == G_FILE_MONITOR_EVENT_DELETED || ++ event_type == G_FILE_MONITOR_EVENT_CHANGES_DONE_HINT)) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Reloading rules"); ++ reload_scripts (authority); ++ } ++ g_free (name); ++ } ++} ++ ++ ++static void ++setup_file_monitors (PolkitBackendJsAuthority *authority) ++{ ++ guint n; ++ GPtrArray *p; ++ ++ p = g_ptr_array_new (); ++ for (n = 0; authority->priv->rules_dirs != NULL && authority->priv->rules_dirs[n] != NULL; n++) ++ { ++ GFile *file; ++ GError *error; ++ GFileMonitor *monitor; ++ ++ file = g_file_new_for_path (authority->priv->rules_dirs[n]); ++ error = NULL; ++ monitor = g_file_monitor_directory (file, ++ G_FILE_MONITOR_NONE, ++ NULL, ++ &error); ++ g_object_unref (file); ++ if (monitor == NULL) ++ { ++ g_warning ("Error monitoring directory %s: %s", ++ authority->priv->rules_dirs[n], ++ error->message); ++ g_clear_error (&error); ++ } ++ else ++ { ++ g_signal_connect (monitor, ++ "changed", ++ G_CALLBACK (on_dir_monitor_changed), ++ authority); ++ g_ptr_array_add (p, monitor); ++ } ++ } ++ g_ptr_array_add (p, NULL); ++ authority->priv->dir_monitors = (GFileMonitor**) g_ptr_array_free (p, FALSE); ++} ++ ++static duk_ret_t js_polkit_log (duk_context *cx); ++static duk_ret_t js_polkit_spawn (duk_context *cx); ++static duk_ret_t js_polkit_user_is_in_netgroup (duk_context *cx); ++ ++static const duk_function_list_entry js_polkit_functions[] = ++{ ++ { "log", js_polkit_log, 1 }, ++ { "spawn", js_polkit_spawn, 1 }, ++ { "_userIsInNetGroup", js_polkit_user_is_in_netgroup, 2 }, ++ { NULL, NULL, 0 }, ++}; ++ ++static void ++polkit_backend_js_authority_constructed (GObject *object) ++{ ++ PolkitBackendJsAuthority *authority = POLKIT_BACKEND_JS_AUTHORITY (object); ++ duk_context *cx; ++ ++ cx = duk_create_heap (NULL, NULL, NULL, authority, NULL); ++ if (cx == NULL) ++ goto fail; ++ ++ authority->priv->cx = cx; ++ ++ duk_push_global_object (cx); ++ duk_push_object (cx); ++ duk_put_function_list (cx, -1, js_polkit_functions); ++ duk_put_prop_string (cx, -2, "polkit"); ++ ++ duk_eval_string (cx, init_js); ++ ++ if (authority->priv->rules_dirs == NULL) ++ { ++ authority->priv->rules_dirs = g_new0 (gchar *, 3); ++ authority->priv->rules_dirs[0] = g_strdup (PACKAGE_SYSCONF_DIR "/polkit-1/rules.d"); ++ authority->priv->rules_dirs[1] = g_strdup (PACKAGE_DATA_DIR "/polkit-1/rules.d"); ++ } ++ ++ setup_file_monitors (authority); ++ load_scripts (authority); ++ ++ G_OBJECT_CLASS (polkit_backend_js_authority_parent_class)->constructed (object); ++ return; ++ ++ fail: ++ g_critical ("Error initializing JavaScript environment"); ++ g_assert_not_reached (); ++} ++ ++static void ++polkit_backend_js_authority_finalize (GObject *object) ++{ ++ PolkitBackendJsAuthority *authority = POLKIT_BACKEND_JS_AUTHORITY (object); ++ guint n; ++ ++ for (n = 0; authority->priv->dir_monitors != NULL && authority->priv->dir_monitors[n] != NULL; n++) ++ { ++ GFileMonitor *monitor = authority->priv->dir_monitors[n]; ++ g_signal_handlers_disconnect_by_func (monitor, ++ G_CALLBACK (on_dir_monitor_changed), ++ authority); ++ g_object_unref (monitor); ++ } ++ g_free (authority->priv->dir_monitors); ++ g_strfreev (authority->priv->rules_dirs); ++ ++ duk_destroy_heap (authority->priv->cx); ++ ++ G_OBJECT_CLASS (polkit_backend_js_authority_parent_class)->finalize (object); ++} ++ ++static void ++polkit_backend_js_authority_set_property (GObject *object, ++ guint property_id, ++ const GValue *value, ++ GParamSpec *pspec) ++{ ++ PolkitBackendJsAuthority *authority = POLKIT_BACKEND_JS_AUTHORITY (object); ++ ++ switch (property_id) ++ { ++ case PROP_RULES_DIRS: ++ g_assert (authority->priv->rules_dirs == NULL); ++ authority->priv->rules_dirs = (gchar **) g_value_dup_boxed (value); ++ break; ++ ++ default: ++ G_OBJECT_WARN_INVALID_PROPERTY_ID (object, property_id, pspec); ++ break; ++ } ++} ++ ++static const gchar * ++polkit_backend_js_authority_get_name (PolkitBackendAuthority *authority) ++{ ++ return "js"; ++} ++ ++static const gchar * ++polkit_backend_js_authority_get_version (PolkitBackendAuthority *authority) ++{ ++ return PACKAGE_VERSION; ++} ++ ++static PolkitAuthorityFeatures ++polkit_backend_js_authority_get_features (PolkitBackendAuthority *authority) ++{ ++ return POLKIT_AUTHORITY_FEATURES_TEMPORARY_AUTHORIZATION; ++} ++ ++static void ++polkit_backend_js_authority_class_init (PolkitBackendJsAuthorityClass *klass) ++{ ++ GObjectClass *gobject_class; ++ PolkitBackendAuthorityClass *authority_class; ++ PolkitBackendInteractiveAuthorityClass *interactive_authority_class; ++ ++ ++ gobject_class = G_OBJECT_CLASS (klass); ++ gobject_class->finalize = polkit_backend_js_authority_finalize; ++ gobject_class->set_property = polkit_backend_js_authority_set_property; ++ gobject_class->constructed = polkit_backend_js_authority_constructed; ++ ++ authority_class = POLKIT_BACKEND_AUTHORITY_CLASS (klass); ++ authority_class->get_name = polkit_backend_js_authority_get_name; ++ authority_class->get_version = polkit_backend_js_authority_get_version; ++ authority_class->get_features = polkit_backend_js_authority_get_features; ++ ++ interactive_authority_class = POLKIT_BACKEND_INTERACTIVE_AUTHORITY_CLASS (klass); ++ interactive_authority_class->get_admin_identities = polkit_backend_js_authority_get_admin_auth_identities; ++ interactive_authority_class->check_authorization_sync = polkit_backend_js_authority_check_authorization_sync; ++ ++ g_object_class_install_property (gobject_class, ++ PROP_RULES_DIRS, ++ g_param_spec_boxed ("rules-dirs", ++ NULL, ++ NULL, ++ G_TYPE_STRV, ++ G_PARAM_CONSTRUCT_ONLY | G_PARAM_WRITABLE)); ++ ++ ++ g_type_class_add_private (klass, sizeof (PolkitBackendJsAuthorityPrivate)); ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static void ++set_property_str (duk_context *cx, ++ const gchar *name, ++ const gchar *value) ++{ ++ duk_push_string (cx, value); ++ duk_put_prop_string (cx, -2, name); ++} ++ ++static void ++set_property_strv (duk_context *cx, ++ const gchar *name, ++ GPtrArray *value) ++{ ++ guint n; ++ duk_push_array (cx); ++ for (n = 0; n < value->len; n++) ++ { ++ duk_push_string (cx, g_ptr_array_index (value, n)); ++ duk_put_prop_index (cx, -2, n); ++ } ++ duk_put_prop_string (cx, -2, name); ++} ++ ++static void ++set_property_int32 (duk_context *cx, ++ const gchar *name, ++ gint32 value) ++{ ++ duk_push_int (cx, value); ++ duk_put_prop_string (cx, -2, name); ++} ++ ++static void ++set_property_bool (duk_context *cx, ++ const char *name, ++ gboolean value) ++{ ++ duk_push_boolean (cx, value); ++ duk_put_prop_string (cx, -2, name); ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static gboolean ++push_subject (duk_context *cx, ++ PolkitSubject *subject, ++ PolkitIdentity *user_for_subject, ++ gboolean subject_is_local, ++ gboolean subject_is_active, ++ GError **error) ++{ ++ gboolean ret = FALSE; ++ pid_t pid; ++ uid_t uid; ++ gchar *user_name = NULL; ++ GPtrArray *groups = NULL; ++ struct passwd *passwd; ++ char *seat_str = NULL; ++ char *session_str = NULL; ++ ++ duk_get_global_string (cx, "Subject"); ++ duk_new (cx, 0); ++ ++ if (POLKIT_IS_UNIX_PROCESS (subject)) ++ { ++ pid = polkit_unix_process_get_pid (POLKIT_UNIX_PROCESS (subject)); ++ } ++ else if (POLKIT_IS_SYSTEM_BUS_NAME (subject)) ++ { ++ PolkitSubject *process; ++ process = polkit_system_bus_name_get_process_sync (POLKIT_SYSTEM_BUS_NAME (subject), NULL, error); ++ if (process == NULL) ++ goto out; ++ pid = polkit_unix_process_get_pid (POLKIT_UNIX_PROCESS (process)); ++ g_object_unref (process); ++ } ++ else ++ { ++ g_assert_not_reached (); ++ } ++ ++#ifdef HAVE_LIBSYSTEMD ++ if (sd_pid_get_session (pid, &session_str) == 0) ++ { ++ if (sd_session_get_seat (session_str, &seat_str) == 0) ++ { ++ /* do nothing */ ++ } ++ } ++#endif /* HAVE_LIBSYSTEMD */ ++ ++ g_assert (POLKIT_IS_UNIX_USER (user_for_subject)); ++ uid = polkit_unix_user_get_uid (POLKIT_UNIX_USER (user_for_subject)); ++ ++ groups = g_ptr_array_new_with_free_func (g_free); ++ ++ passwd = getpwuid (uid); ++ if (passwd == NULL) ++ { ++ user_name = g_strdup_printf ("%d", (gint) uid); ++ g_warning ("Error looking up info for uid %d: %m", (gint) uid); ++ } ++ else ++ { ++ gid_t gids[512]; ++ int num_gids = 512; ++ ++ user_name = g_strdup (passwd->pw_name); ++ ++ if (getgrouplist (passwd->pw_name, ++ passwd->pw_gid, ++ gids, ++ &num_gids) < 0) ++ { ++ g_warning ("Error looking up groups for uid %d: %m", (gint) uid); ++ } ++ else ++ { ++ gint n; ++ for (n = 0; n < num_gids; n++) ++ { ++ struct group *group; ++ group = getgrgid (gids[n]); ++ if (group == NULL) ++ { ++ g_ptr_array_add (groups, g_strdup_printf ("%d", (gint) gids[n])); ++ } ++ else ++ { ++ g_ptr_array_add (groups, g_strdup (group->gr_name)); ++ } ++ } ++ } ++ } ++ ++ set_property_int32 (cx, "pid", pid); ++ set_property_str (cx, "user", user_name); ++ set_property_strv (cx, "groups", groups); ++ set_property_str (cx, "seat", seat_str); ++ set_property_str (cx, "session", session_str); ++ set_property_bool (cx, "local", subject_is_local); ++ set_property_bool (cx, "active", subject_is_active); ++ ++ ret = TRUE; ++ ++ out: ++ free (session_str); ++ free (seat_str); ++ g_free (user_name); ++ if (groups != NULL) ++ g_ptr_array_unref (groups); ++ ++ return ret; ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static gboolean ++push_action_and_details (duk_context *cx, ++ const gchar *action_id, ++ PolkitDetails *details, ++ GError **error) ++{ ++ gchar **keys; ++ guint n; ++ ++ duk_get_global_string (cx, "Action"); ++ duk_new (cx, 0); ++ ++ set_property_str (cx, "id", action_id); ++ ++ keys = polkit_details_get_keys (details); ++ for (n = 0; keys != NULL && keys[n] != NULL; n++) ++ { ++ gchar *key; ++ const gchar *value; ++ key = g_strdup_printf ("_detail_%s", keys[n]); ++ value = polkit_details_lookup (details, keys[n]); ++ set_property_str (cx, key, value); ++ g_free (key); ++ } ++ g_strfreev (keys); ++ ++ return TRUE; ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static GList * ++polkit_backend_js_authority_get_admin_auth_identities (PolkitBackendInteractiveAuthority *_authority, ++ PolkitSubject *caller, ++ PolkitSubject *subject, ++ PolkitIdentity *user_for_subject, ++ gboolean subject_is_local, ++ gboolean subject_is_active, ++ const gchar *action_id, ++ PolkitDetails *details) ++{ ++ PolkitBackendJsAuthority *authority = POLKIT_BACKEND_JS_AUTHORITY (_authority); ++ GList *ret = NULL; ++ guint n; ++ GError *error = NULL; ++ const char *ret_str = NULL; ++ gchar **ret_strs = NULL; ++ duk_context *cx = authority->priv->cx; ++ ++ duk_set_top (cx, 0); ++ duk_get_global_string (cx, "polkit"); ++ duk_push_string (cx, "_runAdminRules"); ++ ++ if (!push_action_and_details (cx, action_id, details, &error)) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error converting action and details to JS object: %s", ++ error->message); ++ g_clear_error (&error); ++ goto out; ++ } ++ ++ if (!push_subject (cx, subject, user_for_subject, subject_is_local, subject_is_active, &error)) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error converting subject to JS object: %s", ++ error->message); ++ g_clear_error (&error); ++ goto out; ++ } ++ ++ if (duk_pcall_prop (cx, 0, 2) != DUK_ERR_NONE) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error evaluating admin rules: ", ++ duk_safe_to_string (cx, -1)); ++ goto out; ++ } ++ ++ ret_str = duk_require_string (cx, -1); ++ ++ ret_strs = g_strsplit (ret_str, ",", -1); ++ for (n = 0; ret_strs != NULL && ret_strs[n] != NULL; n++) ++ { ++ const gchar *identity_str = ret_strs[n]; ++ PolkitIdentity *identity; ++ ++ error = NULL; ++ identity = polkit_identity_from_string (identity_str, &error); ++ if (identity == NULL) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Identity `%s' is not valid, ignoring: %s", ++ identity_str, error->message); ++ g_clear_error (&error); ++ } ++ else ++ { ++ ret = g_list_prepend (ret, identity); ++ } ++ } ++ ret = g_list_reverse (ret); ++ ++ out: ++ g_strfreev (ret_strs); ++ /* fallback to root password auth */ ++ if (ret == NULL) ++ ret = g_list_prepend (ret, polkit_unix_user_new (0)); ++ ++ return ret; ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static PolkitImplicitAuthorization ++polkit_backend_js_authority_check_authorization_sync (PolkitBackendInteractiveAuthority *_authority, ++ PolkitSubject *caller, ++ PolkitSubject *subject, ++ PolkitIdentity *user_for_subject, ++ gboolean subject_is_local, ++ gboolean subject_is_active, ++ const gchar *action_id, ++ PolkitDetails *details, ++ PolkitImplicitAuthorization implicit) ++{ ++ PolkitBackendJsAuthority *authority = POLKIT_BACKEND_JS_AUTHORITY (_authority); ++ PolkitImplicitAuthorization ret = implicit; ++ GError *error = NULL; ++ gchar *ret_str = NULL; ++ gboolean good = FALSE; ++ duk_context *cx = authority->priv->cx; ++ ++ duk_set_top (cx, 0); ++ duk_get_global_string (cx, "polkit"); ++ duk_push_string (cx, "_runRules"); ++ ++ if (!push_action_and_details (cx, action_id, details, &error)) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error converting action and details to JS object: %s", ++ error->message); ++ g_clear_error (&error); ++ goto out; ++ } ++ ++ if (!push_subject (cx, subject, user_for_subject, subject_is_local, subject_is_active, &error)) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error converting subject to JS object: %s", ++ error->message); ++ g_clear_error (&error); ++ goto out; ++ } ++ ++ if (duk_pcall_prop (cx, 0, 2) != DUK_ERR_NONE) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Error evaluating authorization rules: ", ++ duk_safe_to_string (cx, -1)); ++ goto out; ++ } ++ ++ if (duk_is_null(cx, -1)) { ++ good = TRUE; ++ goto out; ++ } ++ ret_str = g_strdup (duk_require_string (cx, -1)); ++ if (!polkit_implicit_authorization_from_string (ret_str, &ret)) ++ { ++ polkit_backend_authority_log (POLKIT_BACKEND_AUTHORITY (authority), ++ "Returned result `%s' is not valid", ++ ret_str); ++ goto out; ++ } ++ ++ good = TRUE; ++ ++ out: ++ if (!good) ++ ret = POLKIT_IMPLICIT_AUTHORIZATION_NOT_AUTHORIZED; ++ g_free (ret_str); ++ ++ return ret; ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static duk_ret_t ++js_polkit_log (duk_context *cx) ++{ ++ const char *str = duk_require_string (cx, 0); ++ fprintf (stderr, "%s\n", str); ++ return 0; ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++static const gchar * ++get_signal_name (gint signal_number) ++{ ++ switch (signal_number) ++ { ++#define _HANDLE_SIG(sig) case sig: return #sig; ++ _HANDLE_SIG (SIGHUP); ++ _HANDLE_SIG (SIGINT); ++ _HANDLE_SIG (SIGQUIT); ++ _HANDLE_SIG (SIGILL); ++ _HANDLE_SIG (SIGABRT); ++ _HANDLE_SIG (SIGFPE); ++ _HANDLE_SIG (SIGKILL); ++ _HANDLE_SIG (SIGSEGV); ++ _HANDLE_SIG (SIGPIPE); ++ _HANDLE_SIG (SIGALRM); ++ _HANDLE_SIG (SIGTERM); ++ _HANDLE_SIG (SIGUSR1); ++ _HANDLE_SIG (SIGUSR2); ++ _HANDLE_SIG (SIGCHLD); ++ _HANDLE_SIG (SIGCONT); ++ _HANDLE_SIG (SIGSTOP); ++ _HANDLE_SIG (SIGTSTP); ++ _HANDLE_SIG (SIGTTIN); ++ _HANDLE_SIG (SIGTTOU); ++ _HANDLE_SIG (SIGBUS); ++#ifdef SIGPOLL ++ _HANDLE_SIG (SIGPOLL); ++#endif ++ _HANDLE_SIG (SIGPROF); ++ _HANDLE_SIG (SIGSYS); ++ _HANDLE_SIG (SIGTRAP); ++ _HANDLE_SIG (SIGURG); ++ _HANDLE_SIG (SIGVTALRM); ++ _HANDLE_SIG (SIGXCPU); ++ _HANDLE_SIG (SIGXFSZ); ++#undef _HANDLE_SIG ++ default: ++ break; ++ } ++ return "UNKNOWN_SIGNAL"; ++} ++ ++typedef struct ++{ ++ GMainLoop *loop; ++ GAsyncResult *res; ++} SpawnData; ++ ++static void ++spawn_cb (GObject *source_object, ++ GAsyncResult *res, ++ gpointer user_data) ++{ ++ SpawnData *data = user_data; ++ data->res = g_object_ref (res); ++ g_main_loop_quit (data->loop); ++} ++ ++static duk_ret_t ++js_polkit_spawn (duk_context *cx) ++{ ++#if (DUK_VERSION >= 20000) ++ duk_ret_t ret = DUK_RET_ERROR; ++#else ++ duk_ret_t ret = DUK_RET_INTERNAL_ERROR; ++#endif ++ gchar *standard_output = NULL; ++ gchar *standard_error = NULL; ++ gint exit_status; ++ GError *error = NULL; ++ guint32 array_len; ++ gchar **argv = NULL; ++ GMainContext *context = NULL; ++ GMainLoop *loop = NULL; ++ SpawnData data = {0}; ++ char *err_str = NULL; ++ guint n; ++ ++ if (!duk_is_array (cx, 0)) ++ goto out; ++ ++ array_len = duk_get_length (cx, 0); ++ ++ argv = g_new0 (gchar*, array_len + 1); ++ for (n = 0; n < array_len; n++) ++ { ++ duk_get_prop_index (cx, 0, n); ++ argv[n] = g_strdup (duk_to_string (cx, -1)); ++ duk_pop (cx); ++ } ++ ++ context = g_main_context_new (); ++ loop = g_main_loop_new (context, FALSE); ++ ++ g_main_context_push_thread_default (context); ++ ++ data.loop = loop; ++ utils_spawn ((const gchar *const *) argv, ++ 10, /* timeout_seconds */ ++ NULL, /* cancellable */ ++ spawn_cb, ++ &data); ++ ++ g_main_loop_run (loop); ++ ++ g_main_context_pop_thread_default (context); ++ ++ if (!utils_spawn_finish (data.res, ++ &exit_status, ++ &standard_output, ++ &standard_error, ++ &error)) ++ { ++ err_str = g_strdup_printf ("Error spawning helper: %s (%s, %d)", ++ error->message, g_quark_to_string (error->domain), error->code); ++ g_clear_error (&error); ++ goto out; ++ } ++ ++ if (!(WIFEXITED (exit_status) && WEXITSTATUS (exit_status) == 0)) ++ { ++ GString *gstr; ++ gstr = g_string_new (NULL); ++ if (WIFEXITED (exit_status)) ++ { ++ g_string_append_printf (gstr, ++ "Helper exited with non-zero exit status %d", ++ WEXITSTATUS (exit_status)); ++ } ++ else if (WIFSIGNALED (exit_status)) ++ { ++ g_string_append_printf (gstr, ++ "Helper was signaled with signal %s (%d)", ++ get_signal_name (WTERMSIG (exit_status)), ++ WTERMSIG (exit_status)); ++ } ++ g_string_append_printf (gstr, ", stdout=`%s', stderr=`%s'", ++ standard_output, standard_error); ++ err_str = g_string_free (gstr, FALSE); ++ goto out; ++ } ++ ++ duk_push_string (cx, standard_output); ++ ret = 1; ++ ++ out: ++ g_strfreev (argv); ++ g_free (standard_output); ++ g_free (standard_error); ++ g_clear_object (&data.res); ++ if (loop != NULL) ++ g_main_loop_unref (loop); ++ if (context != NULL) ++ g_main_context_unref (context); ++ ++ if (err_str) ++ duk_error (cx, DUK_ERR_ERROR, err_str); ++ ++ return ret; ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++ ++static duk_ret_t ++js_polkit_user_is_in_netgroup (duk_context *cx) ++{ ++ const char *user; ++ const char *netgroup; ++ gboolean is_in_netgroup = FALSE; ++ ++ user = duk_require_string (cx, 0); ++ netgroup = duk_require_string (cx, 1); ++ ++ if (innetgr (netgroup, ++ NULL, /* host */ ++ user, ++ NULL)) /* domain */ ++ { ++ is_in_netgroup = TRUE; ++ } ++ ++ duk_push_boolean (cx, is_in_netgroup); ++ return 1; ++} ++ ++/* ---------------------------------------------------------------------------------------------------- */ ++ ++typedef struct ++{ ++ GSimpleAsyncResult *simple; /* borrowed reference */ ++ GMainContext *main_context; /* may be NULL */ ++ ++ GCancellable *cancellable; /* may be NULL */ ++ gulong cancellable_handler_id; ++ ++ GPid child_pid; ++ gint child_stdout_fd; ++ gint child_stderr_fd; ++ ++ GIOChannel *child_stdout_channel; ++ GIOChannel *child_stderr_channel; ++ ++ GSource *child_watch_source; ++ GSource *child_stdout_source; ++ GSource *child_stderr_source; ++ ++ guint timeout_seconds; ++ gboolean timed_out; ++ GSource *timeout_source; ++ ++ GString *child_stdout; ++ GString *child_stderr; ++ ++ gint exit_status; ++} UtilsSpawnData; ++ ++static void ++utils_child_watch_from_release_cb (GPid pid, ++ gint status, ++ gpointer user_data) ++{ ++} ++ ++static void ++utils_spawn_data_free (UtilsSpawnData *data) ++{ ++ if (data->timeout_source != NULL) ++ { ++ g_source_destroy (data->timeout_source); ++ data->timeout_source = NULL; ++ } ++ ++ /* Nuke the child, if necessary */ ++ if (data->child_watch_source != NULL) ++ { ++ g_source_destroy (data->child_watch_source); ++ data->child_watch_source = NULL; ++ } ++ ++ if (data->child_pid != 0) ++ { ++ GSource *source; ++ kill (data->child_pid, SIGTERM); ++ /* OK, we need to reap for the child ourselves - we don't want ++ * to use waitpid() because that might block the calling ++ * thread (the child might handle SIGTERM and use several ++ * seconds for cleanup/rollback). ++ * ++ * So we use GChildWatch instead. ++ * ++ * Avoid taking a references to ourselves. but note that we need ++ * to pass the GSource so we can nuke it once handled. ++ */ ++ source = g_child_watch_source_new (data->child_pid); ++ g_source_set_callback (source, ++ (GSourceFunc) utils_child_watch_from_release_cb, ++ source, ++ (GDestroyNotify) g_source_destroy); ++ g_source_attach (source, data->main_context); ++ g_source_unref (source); ++ data->child_pid = 0; ++ } ++ ++ if (data->child_stdout != NULL) ++ { ++ g_string_free (data->child_stdout, TRUE); ++ data->child_stdout = NULL; ++ } ++ ++ if (data->child_stderr != NULL) ++ { ++ g_string_free (data->child_stderr, TRUE); ++ data->child_stderr = NULL; ++ } ++ ++ if (data->child_stdout_channel != NULL) ++ { ++ g_io_channel_unref (data->child_stdout_channel); ++ data->child_stdout_channel = NULL; ++ } ++ if (data->child_stderr_channel != NULL) ++ { ++ g_io_channel_unref (data->child_stderr_channel); ++ data->child_stderr_channel = NULL; ++ } ++ ++ if (data->child_stdout_source != NULL) ++ { ++ g_source_destroy (data->child_stdout_source); ++ data->child_stdout_source = NULL; ++ } ++ if (data->child_stderr_source != NULL) ++ { ++ g_source_destroy (data->child_stderr_source); ++ data->child_stderr_source = NULL; ++ } ++ ++ if (data->child_stdout_fd != -1) ++ { ++ g_warn_if_fail (close (data->child_stdout_fd) == 0); ++ data->child_stdout_fd = -1; ++ } ++ if (data->child_stderr_fd != -1) ++ { ++ g_warn_if_fail (close (data->child_stderr_fd) == 0); ++ data->child_stderr_fd = -1; ++ } ++ ++ if (data->cancellable_handler_id > 0) ++ { ++ g_cancellable_disconnect (data->cancellable, data->cancellable_handler_id); ++ data->cancellable_handler_id = 0; ++ } ++ ++ if (data->main_context != NULL) ++ g_main_context_unref (data->main_context); ++ ++ if (data->cancellable != NULL) ++ g_object_unref (data->cancellable); ++ ++ g_slice_free (UtilsSpawnData, data); ++} ++ ++/* called in the thread where @cancellable was cancelled */ ++static void ++utils_on_cancelled (GCancellable *cancellable, ++ gpointer user_data) ++{ ++ UtilsSpawnData *data = user_data; ++ GError *error; ++ ++ error = NULL; ++ g_warn_if_fail (g_cancellable_set_error_if_cancelled (cancellable, &error)); ++ g_simple_async_result_take_error (data->simple, error); ++ g_simple_async_result_complete_in_idle (data->simple); ++ g_object_unref (data->simple); ++} ++ ++static gboolean ++utils_read_child_stderr (GIOChannel *channel, ++ GIOCondition condition, ++ gpointer user_data) ++{ ++ UtilsSpawnData *data = user_data; ++ gchar buf[1024]; ++ gsize bytes_read; ++ ++ g_io_channel_read_chars (channel, buf, sizeof buf, &bytes_read, NULL); ++ g_string_append_len (data->child_stderr, buf, bytes_read); ++ return TRUE; ++} ++ ++static gboolean ++utils_read_child_stdout (GIOChannel *channel, ++ GIOCondition condition, ++ gpointer user_data) ++{ ++ UtilsSpawnData *data = user_data; ++ gchar buf[1024]; ++ gsize bytes_read; ++ ++ g_io_channel_read_chars (channel, buf, sizeof buf, &bytes_read, NULL); ++ g_string_append_len (data->child_stdout, buf, bytes_read); ++ return TRUE; ++} ++ ++static void ++utils_child_watch_cb (GPid pid, ++ gint status, ++ gpointer user_data) ++{ ++ UtilsSpawnData *data = user_data; ++ gchar *buf; ++ gsize buf_size; ++ ++ if (g_io_channel_read_to_end (data->child_stdout_channel, &buf, &buf_size, NULL) == G_IO_STATUS_NORMAL) ++ { ++ g_string_append_len (data->child_stdout, buf, buf_size); ++ g_free (buf); ++ } ++ if (g_io_channel_read_to_end (data->child_stderr_channel, &buf, &buf_size, NULL) == G_IO_STATUS_NORMAL) ++ { ++ g_string_append_len (data->child_stderr, buf, buf_size); ++ g_free (buf); ++ } ++ ++ data->exit_status = status; ++ ++ /* ok, child watch is history, make sure we don't free it in spawn_data_free() */ ++ data->child_pid = 0; ++ data->child_watch_source = NULL; ++ ++ /* we're done */ ++ g_simple_async_result_complete_in_idle (data->simple); ++ g_object_unref (data->simple); ++} ++ ++static gboolean ++utils_timeout_cb (gpointer user_data) ++{ ++ UtilsSpawnData *data = user_data; ++ ++ data->timed_out = TRUE; ++ ++ /* ok, timeout is history, make sure we don't free it in spawn_data_free() */ ++ data->timeout_source = NULL; ++ ++ /* we're done */ ++ g_simple_async_result_complete_in_idle (data->simple); ++ g_object_unref (data->simple); ++ ++ return FALSE; /* remove source */ ++} ++ ++static void ++utils_spawn (const gchar *const *argv, ++ guint timeout_seconds, ++ GCancellable *cancellable, ++ GAsyncReadyCallback callback, ++ gpointer user_data) ++{ ++ UtilsSpawnData *data; ++ GError *error; ++ ++ data = g_slice_new0 (UtilsSpawnData); ++ data->timeout_seconds = timeout_seconds; ++ data->simple = g_simple_async_result_new (NULL, ++ callback, ++ user_data, ++ utils_spawn); ++ data->main_context = g_main_context_get_thread_default (); ++ if (data->main_context != NULL) ++ g_main_context_ref (data->main_context); ++ ++ data->cancellable = cancellable != NULL ? g_object_ref (cancellable) : NULL; ++ ++ data->child_stdout = g_string_new (NULL); ++ data->child_stderr = g_string_new (NULL); ++ data->child_stdout_fd = -1; ++ data->child_stderr_fd = -1; ++ ++ /* the life-cycle of UtilsSpawnData is tied to its GSimpleAsyncResult */ ++ g_simple_async_result_set_op_res_gpointer (data->simple, data, (GDestroyNotify) utils_spawn_data_free); ++ ++ error = NULL; ++ if (data->cancellable != NULL) ++ { ++ /* could already be cancelled */ ++ error = NULL; ++ if (g_cancellable_set_error_if_cancelled (data->cancellable, &error)) ++ { ++ g_simple_async_result_take_error (data->simple, error); ++ g_simple_async_result_complete_in_idle (data->simple); ++ g_object_unref (data->simple); ++ goto out; ++ } ++ ++ data->cancellable_handler_id = g_cancellable_connect (data->cancellable, ++ G_CALLBACK (utils_on_cancelled), ++ data, ++ NULL); ++ } ++ ++ error = NULL; ++ if (!g_spawn_async_with_pipes (NULL, /* working directory */ ++ (gchar **) argv, ++ NULL, /* envp */ ++ G_SPAWN_SEARCH_PATH | G_SPAWN_DO_NOT_REAP_CHILD, ++ NULL, /* child_setup */ ++ NULL, /* child_setup's user_data */ ++ &(data->child_pid), ++ NULL, /* gint *stdin_fd */ ++ &(data->child_stdout_fd), ++ &(data->child_stderr_fd), ++ &error)) ++ { ++ g_prefix_error (&error, "Error spawning: "); ++ g_simple_async_result_take_error (data->simple, error); ++ g_simple_async_result_complete_in_idle (data->simple); ++ g_object_unref (data->simple); ++ goto out; ++ } ++ ++ if (timeout_seconds > 0) ++ { ++ data->timeout_source = g_timeout_source_new_seconds (timeout_seconds); ++ g_source_set_priority (data->timeout_source, G_PRIORITY_DEFAULT); ++ g_source_set_callback (data->timeout_source, utils_timeout_cb, data, NULL); ++ g_source_attach (data->timeout_source, data->main_context); ++ g_source_unref (data->timeout_source); ++ } ++ ++ data->child_watch_source = g_child_watch_source_new (data->child_pid); ++ g_source_set_callback (data->child_watch_source, (GSourceFunc) utils_child_watch_cb, data, NULL); ++ g_source_attach (data->child_watch_source, data->main_context); ++ g_source_unref (data->child_watch_source); ++ ++ data->child_stdout_channel = g_io_channel_unix_new (data->child_stdout_fd); ++ g_io_channel_set_flags (data->child_stdout_channel, G_IO_FLAG_NONBLOCK, NULL); ++ data->child_stdout_source = g_io_create_watch (data->child_stdout_channel, G_IO_IN); ++ g_source_set_callback (data->child_stdout_source, (GSourceFunc) utils_read_child_stdout, data, NULL); ++ g_source_attach (data->child_stdout_source, data->main_context); ++ g_source_unref (data->child_stdout_source); ++ ++ data->child_stderr_channel = g_io_channel_unix_new (data->child_stderr_fd); ++ g_io_channel_set_flags (data->child_stderr_channel, G_IO_FLAG_NONBLOCK, NULL); ++ data->child_stderr_source = g_io_create_watch (data->child_stderr_channel, G_IO_IN); ++ g_source_set_callback (data->child_stderr_source, (GSourceFunc) utils_read_child_stderr, data, NULL); ++ g_source_attach (data->child_stderr_source, data->main_context); ++ g_source_unref (data->child_stderr_source); ++ ++ out: ++ ; ++} ++ ++gboolean ++utils_spawn_finish (GAsyncResult *res, ++ gint *out_exit_status, ++ gchar **out_standard_output, ++ gchar **out_standard_error, ++ GError **error) ++{ ++ GSimpleAsyncResult *simple = G_SIMPLE_ASYNC_RESULT (res); ++ UtilsSpawnData *data; ++ gboolean ret = FALSE; ++ ++ g_return_val_if_fail (G_IS_ASYNC_RESULT (res), FALSE); ++ g_return_val_if_fail (error == NULL || *error == NULL, FALSE); ++ ++ g_warn_if_fail (g_simple_async_result_get_source_tag (simple) == utils_spawn); ++ ++ if (g_simple_async_result_propagate_error (simple, error)) ++ goto out; ++ ++ data = g_simple_async_result_get_op_res_gpointer (simple); ++ ++ if (data->timed_out) ++ { ++ g_set_error (error, ++ G_IO_ERROR, ++ G_IO_ERROR_TIMED_OUT, ++ "Timed out after %d seconds", ++ data->timeout_seconds); ++ goto out; ++ } ++ ++ if (out_exit_status != NULL) ++ *out_exit_status = data->exit_status; ++ ++ if (out_standard_output != NULL) ++ *out_standard_output = g_strdup (data->child_stdout->str); ++ ++ if (out_standard_error != NULL) ++ *out_standard_error = g_strdup (data->child_stderr->str); ++ ++ ret = TRUE; ++ ++ out: ++ return ret; ++} +-- +2.26.2 + diff --git a/board/myna-player-odyssey/scripts/initramfs_postbuild.sh b/board/myna-player-odyssey/scripts/initramfs_postbuild.sh new file mode 100755 index 0000000..faf744d --- /dev/null +++ b/board/myna-player-odyssey/scripts/initramfs_postbuild.sh @@ -0,0 +1,260 @@ +#!/bin/sh + +unlink "${TARGET_DIR}"/usr/lib/systemd/system/default.target +unlink "${TARGET_DIR}"/etc/systemd/system/default.target +ln -srf "${TARGET_DIR}"/usr/lib/systemd/system/initrd.target \ + "${TARGET_DIR}"/usr/lib/systemd/system/default.target +ln -srf "${TARGET_DIR}"/lib/systemd/systemd \ + "${TARGET_DIR}"/init + +dbus-uuidgen > "${BR2_EXTERNAL_MynaPlayer_PATH}"/board/myna-player-odyssey/utilities/machine-id +cp "${BR2_EXTERNAL_MynaPlayer_PATH}"/board/myna-player-odyssey/utilities/machine-id \ +"${TARGET_DIR}"/etc/machine-id +chmod 444 "${TARGET_DIR}"/etc/machine-id + +# lets point emergency.target to reboot.target + +rm "${TARGET_DIR}"/usr/lib/systemd/system/emergency.target +ln -sr "${TARGET_DIR}"/usr/lib/systemd/system/reboot.target "${TARGET_DIR}"/usr/lib/systemd/system/emergency.target + +# lets clean up the initramfs + +cleanup() { find "${CLEANUP_DIR}" -depth -name "$1" -exec rm -rv "{}" \; ; } +CLEANUP_DIR="${TARGET_DIR}/usr/bin" +cleanup attr +cleanup busctl +cleanup chacl +cleanup choom +cleanup col +cleanup colcrt +cleanup colrm +cleanup column +cleanup dbus-* +cleanup dmesg +cleanup fincore +cleanup findmnt +cleanup flock +cleanup getfacl +cleanup getfattr +cleanup ipcmk +cleanup isosize +cleanup kernel-install +cleanup kmod +cleanup ldd +cleanup look +cleanup lsblk +cleanup lscpu +cleanup lsipc +cleanup lslocks +cleanup lsns +cleanup mcookie +cleanup namei +cleanup portablectl +cleanup prlimit +cleanup renice +cleanup rev +cleanup script +cleanup scriptlive +cleanup scriptreplay +cleanup setarch +cleanup setfacl +cleanup setsid +cleanup systemd-analyze +cleanup systemd-ask-password +cleanup systemd-cat +cleanup systemd-cgls +cleanup systemd-cgtop +cleanup systemd-delta +cleanup systemd-detect-virt +cleanup systemd-escape +cleanup systemd-id128 +cleanup systemd-machine-id-setup +cleanup systemd-mount +cleanup systemd-notify +cleanup systemd-nspawn +cleanup systemd-path +cleanup systemd-run +cleanup systemd-socket-activate +cleanup systemd-stdio-bridge +cleanup systemd-tty-ask-password-agent +cleanup systemd-umount +cleanup uuidgen +cleanup uuidparse +cleanup whereis +cleanup xmlwf + +CLEANUP_DIR="${TARGET_DIR}/usr/sbin" +cleanup depmod +cleanup fdisk +cleanup findfs +cleanup insmod +cleanup ldattach +cleanup lsmod +cleanup mkswap +cleanup modinfo +cleanup modprobe +cleanup readprofile +cleanup rmmod +cleanup rtcwake +cleanup sfdisk +cleanup swaplabel +cleanup swapoff +cleanup swapon + +CLEANUP_DIR="${TARGET_DIR}/usr/lib/systemd/system" +cleanup multi-user.target.wants +cleanup local-fs.target.wants +cleanup timers.target.wants +cleanup rescue.target.wants +cleanup graphical.target.wants +cleanup "runlevel*.target.wants" +cleanup systemd-ask-password-console.path +cleanup systemd-journal-catalog-update.service +cleanup systemd-journal-flush.service +cleanup systemd-machine-id-commit.service +cleanup systemd-sysctl.service +cleanup systemd-tmpfiles-setup.service +cleanup systemd-update-done.service +cleanup systemd-update-utmp.service +cleanup "*.mount" +cleanup dbus.socket +cleanup systemd-initctl.socket +cleanup "user*" +cleanup systemd-user-sessions.service +cleanup system-update-cleanup.service +cleanup system-update-pre.target +cleanup system-update.target +cleanup time-set.target +cleanup time-sync.target +cleanup systemd-vconsole-setup.service +cleanup systemd-update-done.service +cleanup systemd-update-utmp-runlevel.service +cleanup systemd-update-utmp.service +cleanup systemd-udev-settle.service +cleanup systemd-tmpfiles-setup.service +cleanup systemd-remount-fs.service +cleanup systemd-suspend.service +cleanup systemd-sysctl.service +cleanup systemd-tmpfiles-clean.service +cleanup systemd-tmpfiles-clean.timer +cleanup systemd-nspawn@.service +cleanup systemd-portabled.service +cleanup systemd-poweroff.service +cleanup systemd-pstore.service +cleanup systemd-journal-flush.service +cleanup systemd-kexec.service +cleanup systemd-machine-id-commit.service +cleanup systemd-halt.service +cleanup systemd-initctl.service +cleanup systemd-initctl.socket +cleanup systemd-journal-catalog-update.service +cleanup systemd-exit.service +cleanup systemd-ask-password-console.path +cleanup systemd-ask-password-console.service +cleanup systemd-ask-password-wall.path +cleanup systemd-ask-password-wall.service +cleanup systemd-boot-check-no-failures.service +cleanup syslog.socket +cleanup sound.target +cleanup suspend.target +cleanup smartcard.target +cleanup sigpwr.target +cleanup sleep.target +cleanup "runlevel*.target" +cleanup rpcbind.target +cleanup remote-fs-pre.target +cleanup remote-fs.target +cleanup multi-user.target +cleanup network-online.target +cleanup network-pre.target +cleanup network.target +cleanup nss-lookup.target +cleanup nss-user-lookup.target +cleanup poweroff.target +cleanup printer.target +cleanup rc-local.service +cleanup kexec.target +cleanup graphical.target +cleanup halt.target +cleanup exit.target +cleanup dbus-org.freedesktop.portable1.service +cleanup dbus.service +cleanup debug-shell.service +cleanup bluetooth.target +cleanup boot-complete.target +cleanup console-getty.service +cleanup container-getty@.service +cleanup autovt@.service + +CLEANUP_DIR="${TARGET_DIR}/usr/lib/systemd" +cleanup "*user*" +cleanup system-preset +cleanup system-shutdown +cleanup system-sleep +cleanup systemd-update-done +cleanup systemd-update-utmp +cleanup systemd-sleep +cleanup systemd-socket-proxyd +cleanup systemd-portabled +cleanup systemd-pstore +cleanup systemd-remount-fs +cleanup systemd-reply-password +cleanup systemd-makefs +cleanup systemd-growfs +cleanup systemd-initctl +cleanup systemd-ac-power +cleanup systemd-boot-check-no-failures +cleanup systemd-cgroups-agent +cleanup systemd-dissect +cleanup network +cleanup portable +cleanup catalog + +CLEANUP_DIR="${TARGET_DIR}/usr/lib" +cleanup tmpfiles.d +cleanup modules-load.d +cleanup sysusers.d +cleanup rpm +cleanup security +cleanup sysctl.d + +CLEANUP_DIR="${TARGET_DIR}/etc" +cleanup dbus-1 +cleanup environment +cleanup init.d +cleanup kernel +cleanup network +cleanup os-release +cleanup pam.d +cleanup profile +cleanup profile.d +cleanup protocols +cleanup resolv.conf +cleanup security +cleanup services +cleanup shells +cleanup sysctl.d +cleanup timezone +cleanup tmpfiles.d +cleanup udev +cleanup X11 +cleanup xattr.conf +cleanup xdg + +CLEANUP_DIR="${TARGET_DIR}/etc/systemd" +cleanup *.conf +cleanup user +cleanup tmpfiles.d + +CLEANUP_DIR="${TARGET_DIR}/etc/systemd/system" +cleanup boot-complete.target.requires +cleanup ctrl-alt-del.target +cleanup default.target +cleanup multi-user.target.wants +cleanup network.service +cleanup systemd-remount-fs.service.wants + +# Moving kernel modules to a well known location + +mkdir -p "${BASE_DIR}"/../kmod +mv "${TARGET_DIR}"/usr/lib/modules "${BASE_DIR}"/../kmod/modules ||true diff --git a/board/myna-player-odyssey/scripts/initramfs_postimage.sh b/board/myna-player-odyssey/scripts/initramfs_postimage.sh new file mode 100755 index 0000000..5d6d527 --- /dev/null +++ b/board/myna-player-odyssey/scripts/initramfs_postimage.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +# copy kernel, bootloader and device tree to a well known location + +mkdir -p "${BASE_DIR}"/../kernel +cp -a "${BINARIES_DIR}"/zImage \ + "${BINARIES_DIR}"/stm32mp157c-odyssey.dtb \ + "${BINARIES_DIR}"/barebox.bin \ + "${BASE_DIR}"/../kernel diff --git a/board/myna-player-odyssey/scripts/rootfs_postbuild.sh b/board/myna-player-odyssey/scripts/rootfs_postbuild.sh new file mode 100755 index 0000000..e73da18 --- /dev/null +++ b/board/myna-player-odyssey/scripts/rootfs_postbuild.sh @@ -0,0 +1,29 @@ +#!/bin/sh +# setup machine-id + +cp "${BR2_EXTERNAL_MynaPlayer_PATH}"/board/myna-player-odyssey/utilities/machine-id \ + "${TARGET_DIR}"/etc/machine-id +chmod 444 "${TARGET_DIR}"/etc/machine-id + +# Moving kernel modules into place + +rsync -ar ${BASE_DIR}/../kmod/modules/* \ + ${TARGET_DIR}/usr/lib/modules + +# lets point emergency.target to reboot.target + +rm "${TARGET_DIR}"/usr/lib/systemd/system/emergency.target +ln -sr "${TARGET_DIR}"/usr/lib/systemd/system/reboot.target \ + "${TARGET_DIR}"/usr/lib/systemd/system/emergency.target + +# copy changelog into the target + +cp "${BR2_EXTERNAL_MynaPlayer_PATH}"/changelog.md \ + "${TARGET_DIR}"/etc/changelog.md + +# copy the kernel and device tree + +mkdir -p "${TARGET_DIR}"/boot +cp -a "${BASE_DIR}"/../kernel/stm32mp157c-odyssey.dtb \ + "${BASE_DIR}"/../kernel/zImage \ + "${TARGET_DIR}"/boot diff --git a/board/myna-player-odyssey/scripts/rootfs_postimage.sh b/board/myna-player-odyssey/scripts/rootfs_postimage.sh new file mode 100755 index 0000000..99bb858 --- /dev/null +++ b/board/myna-player-odyssey/scripts/rootfs_postimage.sh @@ -0,0 +1,31 @@ +#!/bin/bash + +set -e + +# copy bootloader + +cp "${BASE_DIR}"/../kernel/barebox.bin \ + "${BINARIES_DIR}"/barebox.bin + +# prepare for genimage + +export GENIMAGE_TMP=${BR2_EXTERNAL_MynaPlayer_PATH}/board/myna-player-odyssey/utilities/genimage.tmp +GENIMAGE_CFG="${BR2_EXTERNAL_MynaPlayer_PATH}/board/myna-player-odyssey/utilities/genimage.cfg" +export GENIMAGE_DATE=$(date -Idate) +export GENIMAGE_USER=$(whoami) +export GENIMAGE_HOST=$(hostname) +export GENIMAGE_BUILD_ID=$(uuidgen) +export GENIMAGE_CERTIFICATE_AUTHORITY=$(awk '{print $3}' "${BR2_EXTERNAL_MynaPlayer_PATH}/board/myna-player-odyssey/utilities/certs.txt" | sed -n '1p') +export GENIMAGE_PRIVATE_KEY=$(awk '{print $3}' "${BR2_EXTERNAL_MynaPlayer_PATH}/board/myna-player-odyssey/utilities/certs.txt" | sed -n '2p') +export GENIMAGE_PUBLIC_KEY=$(awk '{print $3}' "${BR2_EXTERNAL_MynaPlayer_PATH}/board/myna-player-odyssey/utilities/certs.txt" | sed -n '3p') + +envsubst \ +\$GENIMAGE_DATE,\ +\$GENIMAGE_USER,\ +\$GENIMAGE_HOST,\ +\$GENIMAGE_BUILD_ID,\ +\$GENIMAGE_CERTIFICATE_AUTHORITY,\ +\$GENIMAGE_PRIVATE_KEY,\ +\$GENIMAGE_PUBLIC_KEY \ +< ${GENIMAGE_TMP} \ +> ${GENIMAGE_CFG} diff --git a/board/myna-player-odyssey/utilities/certs.txt.example b/board/myna-player-odyssey/utilities/certs.txt.example new file mode 100644 index 0000000..53ab94e --- /dev/null +++ b/board/myna-player-odyssey/utilities/certs.txt.example @@ -0,0 +1,3 @@ +Certificate authority: /path/to/ca.crt +Private key: /path/to/private.key +Public key: /path/to/public.crt diff --git a/board/myna-player-odyssey/utilities/genimage.tmp b/board/myna-player-odyssey/utilities/genimage.tmp new file mode 100644 index 0000000..4b91262 --- /dev/null +++ b/board/myna-player-odyssey/utilities/genimage.tmp @@ -0,0 +1,53 @@ +image MynaPlayer.img { + name = "MynaPlayer-${GENIMAGE_DATE}" + hdimage { + gpt = "true" + } + + partition state { + offset = 0x14400 + size = 0x30000 + image = "/dev/null" + in-partition-table = "no" + } + + partition barebox-environment { + size = 64K + image = "/dev/null" + } + + partition ssbl { + partition-type = 0x83 + image = "barebox.bin" + } + + partition PrimaryRootfs { + partition-type = 0x83 + image = "rootfs.ext4" + } + + partition SecondaryRootfs { + partition-type = 0x83 + image = "rootfs.ext4" + } +} + +image bundle-MynaPlayer-${GENIMAGE_DATE}.${GENIMAGE_BUILD_ID}.raucb { + name = "bundle-MynaPlayer-${GENIMAGE_DATE}" + rauc { + files = { + "rootfs.tar.xz" + } + key = "${GENIMAGE_PRIVATE_KEY}" + cert = "${GENIMAGE_PUBLIC_KEY}" + extraargs = "--keyring ${GENIMAGE_CERTIFICATE_AUTHORITY}" + manifest = + "[update] + compatible=LuminaSensum MynaPlayer + version=${GENIMAGE_DATE} + build=${GENIMAGE_BUILD_ID} + description=RAUC bundle for LuminaSensum MynaPlayer version ${GENIMAGE_DATE}, built by ${GENIMAGE_USER}@${GENIMAGE_HOST}. + [image.rootfs] + filename=rootfs.tar.xz" + } +} diff --git a/changelog.md b/changelog.md new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/changelog.md diff --git a/configs/myna_player_odyssey_defconfig b/configs/myna_player_odyssey_defconfig new file mode 100644 index 0000000..1db236e --- /dev/null +++ b/configs/myna_player_odyssey_defconfig @@ -0,0 +1,103 @@ +BR2_arm=y +BR2_cortex_a7=y +BR2_CCACHE=y +BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/rootfs_patches" +BR2_PER_PACKAGE_DIRECTORIES=y +BR2_SSP_STRONG=y +BR2_RELRO_FULL=y +BR2_FORTIFY_SOURCE_2=y +BR2_TOOLCHAIN_EXTERNAL=y +BR2_TOOLCHAIN_EXTERNAL_CUSTOM=y +BR2_TOOLCHAIN_EXTERNAL_DOWNLOAD=y +BR2_TOOLCHAIN_EXTERNAL_URL="https://toolchains.bootlin.com/downloads/releases/toolchains/armv7-eabihf/tarballs/armv7-eabihf--glibc--bleeding-edge-2020.02-2.tar.bz2" +BR2_TOOLCHAIN_EXTERNAL_HEADERS_4_19=y +BR2_TOOLCHAIN_EXTERNAL_CUSTOM_GLIBC=y +BR2_TOOLCHAIN_EXTERNAL_CXX=y +BR2_TARGET_GENERIC_HOSTNAME="MynaPlayer" +BR2_TARGET_GENERIC_ISSUE="Welcome to MynaPlayer" +BR2_INIT_SYSTEMD=y +BR2_SYSTEM_BIN_SH_BASH=y +# BR2_TARGET_GENERIC_GETTY is not set +# BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW is not set +BR2_ENABLE_LOCALE_WHITELIST="en_US.UTF-8" +BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/rootfs_overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/scripts/rootfs_postbuild.sh" +BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/scripts/rootfs_postimage.sh support/scripts/genimage.sh" +BR2_ROOTFS_POST_SCRIPT_ARGS="-c $(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/utilities/genimage.cfg" +# BR2_PACKAGE_BUSYBOX is not set +BR2_PACKAGE_XZ=y +BR2_PACKAGE_ZIP=y +BR2_PACKAGE_FINDUTILS=y +BR2_PACKAGE_GREP=y +BR2_PACKAGE_SED=y +BR2_PACKAGE_DOSFSTOOLS=y +BR2_PACKAGE_DOSFSTOOLS_FATLABEL=y +BR2_PACKAGE_DOSFSTOOLS_FSCK_FAT=y +BR2_PACKAGE_DOSFSTOOLS_MKFS_FAT=y +BR2_PACKAGE_E2FSPROGS=y +BR2_PACKAGE_EXFATPROGS=y +BR2_PACKAGE_B43_FIRMWARE=y +BR2_PACKAGE_LINUX_FIRMWARE=y +BR2_PACKAGE_LINUX_FIRMWARE_BRCM_BCM43XX=y +BR2_PACKAGE_LINUX_FIRMWARE_BRCM_BCM43XXX=y +BR2_PACKAGE_DT_UTILS=y +BR2_PACKAGE_I2C_TOOLS=y +BR2_PACKAGE_LM_SENSORS=y +BR2_PACKAGE_RNG_TOOLS=y +BR2_PACKAGE_RTC_TOOLS=y +BR2_PACKAGE_UBOOT_TOOLS=y +BR2_PACKAGE_USBUTILS=y +BR2_PACKAGE_LIBARCHIVE=y +BR2_PACKAGE_LIBARCHIVE_BSDTAR=y +BR2_PACKAGE_LIBARCHIVE_BSDCAT=y +BR2_PACKAGE_CA_CERTIFICATES=y +BR2_PACKAGE_NCURSES_TARGET_PROGS=y +BR2_PACKAGE_CRDA=y +# BR2_PACKAGE_IFUPDOWN_SCRIPTS is not set +BR2_PACKAGE_IPROUTE2=y +BR2_PACKAGE_IPUTILS=y +BR2_PACKAGE_NETWORK_MANAGER=y +BR2_PACKAGE_NETWORK_MANAGER_TUI=y +BR2_PACKAGE_RSYNC=y +BR2_PACKAGE_WGET=y +BR2_PACKAGE_BASH_COMPLETION=y +BR2_PACKAGE_FILE=y +BR2_PACKAGE_WHICH=y +BR2_PACKAGE_ACL=y +BR2_PACKAGE_COREUTILS=y +BR2_PACKAGE_PROCPS_NG=y +BR2_PACKAGE_PSMISC=y +BR2_PACKAGE_RAUC=y +BR2_PACKAGE_RAUC_NETWORK=y +# BR2_PACKAGE_SYSTEMD_PSTORE is not set +# BR2_PACKAGE_SYSTEMD_HWDB is not set +BR2_PACKAGE_SYSTEMD_LOGIND=y +# BR2_PACKAGE_SYSTEMD_NETWORKD is not set +BR2_PACKAGE_SYSTEMD_POLKIT=y +# BR2_PACKAGE_SYSTEMD_VCONSOLE is not set +BR2_PACKAGE_SYSTEMD_BOOTCHART=y +BR2_PACKAGE_TAR=y +BR2_PACKAGE_UTIL_LINUX_HWCLOCK=y +BR2_PACKAGE_UTIL_LINUX_KILL=y +BR2_PACKAGE_UTIL_LINUX_LAST=y +BR2_PACKAGE_UTIL_LINUX_LOGIN=y +BR2_PACKAGE_UTIL_LINUX_LOSETUP=y +BR2_PACKAGE_UTIL_LINUX_MOUNTPOINT=y +BR2_PACKAGE_UTIL_LINUX_NEWGRP=y +BR2_PACKAGE_UTIL_LINUX_SCHEDUTILS=y +BR2_PACKAGE_UTIL_LINUX_SULOGIN=y +BR2_PACKAGE_UTIL_LINUX_UUIDD=y +BR2_PACKAGE_UTIL_LINUX_WALL=y +BR2_PACKAGE_UTIL_LINUX_WIPEFS=y +BR2_PACKAGE_LESS=y +BR2_PACKAGE_NANO=y +BR2_PACKAGE_VIM=y +# BR2_PACKAGE_VIM_RUNTIME is not set +BR2_TARGET_ROOTFS_EXT2=y +BR2_TARGET_ROOTFS_EXT2_4=y +BR2_TARGET_ROOTFS_EXT2_SIZE="512M" +BR2_TARGET_ROOTFS_TAR_XZ=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_RAUC=y +BR2_PACKAGE_DISABLED_SERVICES=y +BR2_PACKAGE_OPENSSH_SYSTEMD=y diff --git a/configs/myna_player_odyssey_initramfs_defconfig b/configs/myna_player_odyssey_initramfs_defconfig new file mode 100644 index 0000000..281540f --- /dev/null +++ b/configs/myna_player_odyssey_initramfs_defconfig @@ -0,0 +1,64 @@ +BR2_arm=y +BR2_cortex_a7=y +BR2_CCACHE=y +BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/initramfs_patches" +BR2_PER_PACKAGE_DIRECTORIES=y +BR2_SSP_ALL=y +BR2_RELRO_FULL=y +BR2_FORTIFY_SOURCE_1=y +BR2_TOOLCHAIN_EXTERNAL=y +BR2_TOOLCHAIN_EXTERNAL_CUSTOM=y +BR2_TOOLCHAIN_EXTERNAL_DOWNLOAD=y +BR2_TOOLCHAIN_EXTERNAL_URL="https://toolchains.bootlin.com/downloads/releases/toolchains/armv7-eabihf/tarballs/armv7-eabihf--glibc--bleeding-edge-2020.02-2.tar.bz2" +BR2_TOOLCHAIN_EXTERNAL_HEADERS_4_19=y +BR2_TOOLCHAIN_EXTERNAL_CUSTOM_GLIBC=y +BR2_TOOLCHAIN_EXTERNAL_CXX=y +BR2_INIT_SYSTEMD=y +# BR2_TARGET_ENABLE_ROOT_LOGIN is not set +# BR2_TARGET_GENERIC_GETTY is not set +# BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW is not set +BR2_ENABLE_LOCALE_WHITELIST="en_US.UTF-8" +BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/initramfs_overlay" +BR2_ROOTFS_POST_BUILD_SCRIPT="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/scripts/initramfs_postbuild.sh" +BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/scripts/initramfs_postimage.sh" +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_VERSION=y +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.8" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/configs/linux.config" +BR2_LINUX_KERNEL_XZ=y +BR2_LINUX_KERNEL_DTS_SUPPORT=y +BR2_LINUX_KERNEL_INTREE_DTS_NAME="stm32mp157c-odyssey" +BR2_LINUX_KERNEL_DTB_OVERLAY_SUPPORT=y +BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y +BR2_LINUX_KERNEL_NEEDS_HOST_LIBELF=y +BR2_PACKAGE_BUSYBOX_CONFIG="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/configs/busybox.config" +BR2_PACKAGE_ACL=y +# BR2_PACKAGE_SYSTEMD_HOSTNAMED is not set +# BR2_PACKAGE_SYSTEMD_HWDB is not set +# BR2_PACKAGE_SYSTEMD_MYHOSTNAME is not set +# BR2_PACKAGE_SYSTEMD_NETWORKD is not set +BR2_PACKAGE_SYSTEMD_REPART=y +# BR2_PACKAGE_SYSTEMD_RESOLVED is not set +# BR2_PACKAGE_SYSTEMD_TIMEDATED is not set +# BR2_PACKAGE_SYSTEMD_TIMESYNCD is not set +BR2_PACKAGE_SYSTEMD_BOOTCHART=y +BR2_PACKAGE_UTIL_LINUX_SULOGIN=y +BR2_TARGET_ROOTFS_CPIO_XZ=y +BR2_TARGET_ROOTFS_INITRAMFS=y +# BR2_TARGET_ROOTFS_TAR is not set +BR2_TARGET_ARM_TRUSTED_FIRMWARE=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_VERSION=y +BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_VERSION_VALUE="v2.2" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="stm32mp1" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="ENABLE_STACK_PROTECTOR=strong STM32MP_EMMC=1 STM32MP_MMC=1 AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-dk2.dtb" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="*.stm32" +BR2_TARGET_ARM_TRUSTED_FIRMWARE_NEEDS_DTC=y +BR2_TARGET_BAREBOX=y +BR2_TARGET_BAREBOX_CUSTOM_GIT=y +BR2_TARGET_BAREBOX_CUSTOM_GIT_REPO_URL="https://git.pengutronix.de/cgit/barebox" +BR2_TARGET_BAREBOX_CUSTOM_GIT_VERSION="d4d3e9c87" +BR2_TARGET_BAREBOX_USE_CUSTOM_CONFIG=y +BR2_TARGET_BAREBOX_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_MynaPlayer_PATH)/board/myna-player-odyssey/configs/barebox.config" +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_DISABLED_SERVICES=y diff --git a/external.desc b/external.desc new file mode 100644 index 0000000..3316542 --- /dev/null +++ b/external.desc @@ -0,0 +1,2 @@ +name: MynaPlayer +desc: external tree for LuminaSensum MynaPlayer diff --git a/external.mk b/external.mk new file mode 100644 index 0000000..4c56968 --- /dev/null +++ b/external.mk @@ -0,0 +1,8 @@ +include $(sort $(wildcard $(BR2_EXTERNAL_MynaPlayer_PATH)/packages/*/*.mk)) + +export MODULES_PLACE = $(BASE_DIR)/../kmod +export KERNEL_PLACE = $(BASE_DIR)/../kernel + +pre-clean: + rm -rf $(MAGIC_PLACE) + rm -rf $(KERNEL_PLACE) diff --git a/packages/Config.in b/packages/Config.in new file mode 100644 index 0000000..b6acc54 --- /dev/null +++ b/packages/Config.in @@ -0,0 +1,8 @@ +menu "Target packages" + +source "$BR2_EXTERNAL_MynaPlayer_PATH/packages/disabled-services/Config.in" +source "$BR2_EXTERNAL_MynaPlayer_PATH/packages/duktape-pc/Config.in" +source "$BR2_EXTERNAL_MynaPlayer_PATH/packages/openssh-systemd/Config.in" +source "$BR2_EXTERNAL_MynaPlayer_PATH/packages/polkit-duktape/Config.in" + +endmenu diff --git a/packages/disabled-services/70-disabled.preset b/packages/disabled-services/70-disabled.preset new file mode 100644 index 0000000..7841595 --- /dev/null +++ b/packages/disabled-services/70-disabled.preset @@ -0,0 +1,7 @@ +disable alsa-state.service +disable alsa-restore.service +disable ninfod.service +disable rdisc.service +disable systemd-network-generator.service +disable systemd-pstore.service +disable systemd-time-wait-sync.service diff --git a/packages/disabled-services/Config.in b/packages/disabled-services/Config.in new file mode 100644 index 0000000..e353713 --- /dev/null +++ b/packages/disabled-services/Config.in @@ -0,0 +1,4 @@ +config BR2_PACKAGE_DISABLED_SERVICES + bool "disabled-services" + help + Provides a systemd preset file to disable units. diff --git a/packages/disabled-services/disabled-services.mk b/packages/disabled-services/disabled-services.mk new file mode 100644 index 0000000..dcfa1c4 --- /dev/null +++ b/packages/disabled-services/disabled-services.mk @@ -0,0 +1,16 @@ +################################################################################ +# +# disabled-services +# +################################################################################ + +DISABLED_SERVICES_VERSION = local +DISABLED_SERVICES_SITE = $(DISABLED_SERVICES_PKGDIR)/. +DISABLED_SERVICES_SITE_METHOD = local + +define DISABLED_SERVICES_INSTALL_INIT_SYSTEMD + mkdir -p $(TARGET_DIR)/etc/systemd/system-preset + $(INSTALL) -D -m 0644 $(DISABLED_SERVICES_PKGDIR)/70-disabled.preset \ + $(TARGET_DIR)/etc/systemd/system-preset/70-disabled.preset +endef +$(eval $(generic-package)) diff --git a/packages/duktape-pc/Config.in b/packages/duktape-pc/Config.in new file mode 100644 index 0000000..d086a76 --- /dev/null +++ b/packages/duktape-pc/Config.in @@ -0,0 +1,16 @@ +config BR2_PACKAGE_DUKTAPE_PC + bool "duktape-pc" + depends on !BR2_STATIC_LIBS + help + Duktape is an embeddable Javascript engine, with a focus on + portability and compact footprint. + + Duktape is easy to integrate into a C/C++ project: add + duktape.c, duktape.h, and duk_config.h to your build, and use + the Duktape API to call Ecmascript functions from C code and + vice versa. + + http://www.duktape.org + +comment "duktape needs a toolchain w/ dynamic library" + depends on BR2_STATIC_LIBS diff --git a/packages/duktape-pc/duktape-pc.hash b/packages/duktape-pc/duktape-pc.hash new file mode 100644 index 0000000..39eb5f1 --- /dev/null +++ b/packages/duktape-pc/duktape-pc.hash @@ -0,0 +1,4 @@ +# Locally computed: +sha256 810e1dab50dfd3040cac4bb18b96d749a5fdebfd898a7bfe74512044c1a89880 duktape-pc-2.5.0.tar.gz +sha256 5b42d02dbd084fd6d7e61d93f52e02b596f25400e54e0f86d5780045e5b754c8 LICENSE.txt +sha256 c23b6353a0a0b237470e7ed128402004622a3cfeac5fd0411ae6a42b18d2fe16 duktape-pkgconfig.pc diff --git a/packages/duktape-pc/duktape-pc.mk b/packages/duktape-pc/duktape-pc.mk new file mode 100644 index 0000000..00b4e69 --- /dev/null +++ b/packages/duktape-pc/duktape-pc.mk @@ -0,0 +1,31 @@ +################################################################################ +# +# duktape-pkgconfig +# +################################################################################ + +DUKTAPE_PC_VERSION = 2.5.0 +DUKTAPE_PC_SITE = $(call github,svaarala,duktape-releases,v$(DUKTAPE_PC_VERSION)) +DUKTAPE_PC_LICENSE = MIT +DUKTAPE_PC_LICENSE_FILES = LICENSE.txt +DUKTAPE_PC_INSTALL_STAGING = YES + +define DUKTAPE_PC_BUILD_CMDS + $(MAKE) $(TARGET_CONFIGURE_OPTS) -C $(@D) -f Makefile.sharedlibrary +endef + +define DUKTAPE_PC_INSTALL_STAGING_CMDS + $(MAKE) $(TARGET_CONFIGURE_OPTS) -C $(@D) -f Makefile.sharedlibrary \ + INSTALL_PREFIX=$(STAGING_DIR)/usr install + $(INSTALL) -D -m 644 $(DUKTAPE_PC_PKGDIR)/duktape-pc.pc \ + $(STAGING_DIR)/usr/lib/pkgconfig/duktape.pc +endef + +define DUKTAPE_PC_INSTALL_TARGET_CMDS + $(MAKE) $(TARGET_CONFIGURE_OPTS) -C $(@D) -f Makefile.sharedlibrary \ + INSTALL_PREFIX=$(TARGET_DIR)/usr install + $(INSTALL) -D -m 644 $(DUKTAPE_PC_PKGDIR)/duktape-pc.pc \ + $(TARGET_DIR)/usr/lib/pkgconfig/duktape.pc +endef + +$(eval $(generic-package)) diff --git a/packages/duktape-pc/duktape-pc.pc b/packages/duktape-pc/duktape-pc.pc new file mode 100644 index 0000000..941a2c3 --- /dev/null +++ b/packages/duktape-pc/duktape-pc.pc @@ -0,0 +1,10 @@ +prefix=/usr +exec_prefix=${prefix} +libdir=${exec_prefix}/lib +includedir=${prefix}/include + +Name: duktape +Description: Embeddable Javascript engine +Version: 2.5.0 +Libs: -L${libdir} -lduktape +Cflags: -I${includedir} diff --git a/packages/openssh-systemd/Config.in b/packages/openssh-systemd/Config.in new file mode 100644 index 0000000..7de1cad --- /dev/null +++ b/packages/openssh-systemd/Config.in @@ -0,0 +1,11 @@ +config BR2_PACKAGE_OPENSSH_SYSTEMD + bool "openssh-systemd" + depends on BR2_USE_MMU # fork() + select BR2_PACKAGE_OPENSSL + select BR2_PACKAGE_ZLIB + help + A free version of the SSH protocol suite of network + connectivity tools. The standard 'ssh', 'sshd', 'scp', and + friends. + + http://www.openssh.com/ diff --git a/packages/openssh-systemd/S50sshd b/packages/openssh-systemd/S50sshd new file mode 100644 index 0000000..22da41d --- /dev/null +++ b/packages/openssh-systemd/S50sshd @@ -0,0 +1,47 @@ +#!/bin/sh +# +# sshd Starts sshd. +# + +# Make sure the ssh-keygen progam exists +[ -f /usr/bin/ssh-keygen ] || exit 0 + +umask 077 + +start() { + # Create any missing keys + /usr/bin/ssh-keygen -A + + printf "Starting sshd: " + /usr/sbin/sshd + touch /var/lock/sshd + echo "OK" +} +stop() { + printf "Stopping sshd: " + killall sshd + rm -f /var/lock/sshd + echo "OK" +} +restart() { + stop + start +} + +case "$1" in + start) + start + ;; + stop) + stop + ;; + restart|reload) + restart + ;; + *) + echo "Usage: $0 {start|stop|restart}" + exit 1 +esac + +exit $? + diff --git a/packages/openssh-systemd/openssh-systemd.hash b/packages/openssh-systemd/openssh-systemd.hash new file mode 100644 index 0000000..2f962d4 --- /dev/null +++ b/packages/openssh-systemd/openssh-systemd.hash @@ -0,0 +1,4 @@ +# From https://www.openssh.com/txt/release-8.2 (base64 encoded) +sha256 43925151e6cf6cee1450190c0e9af4dc36b41c12737619edff8bcebdff64e671 openssh-8.2p1.tar.gz +# Locally calculated +sha256 73d0db766229670c7b4e1ec5e6baed54977a0694a565e7cc878c45ee834045d7 LICENCE diff --git a/packages/openssh-systemd/openssh-systemd.mk b/packages/openssh-systemd/openssh-systemd.mk new file mode 100644 index 0000000..507e16b --- /dev/null +++ b/packages/openssh-systemd/openssh-systemd.mk @@ -0,0 +1,100 @@ +################################################################################ +# +# openssh-systemd +# +################################################################################ + +OPENSSH_SYSTEMD_VERSION = 8.2p1 +OPENSSH_SYSTEMD_SITE = http://ftp.openbsd.org/pub/OpenBSD/OpenSSH/portable +OPENSSH_SYSTEMD_SOURCE = openssh-$(OPENSSH_SYSTEMD_VERSION).tar.gz +OPENSSH_SYSTEMD_LICENSE = BSD-3-Clause, BSD-2-Clause, Public Domain +OPENSSH_SYSTEMD_LICENSE_FILES = LICENCE +OPENSSH_SYSTEMD_CONF_ENV = \ + LD="$(TARGET_CC)" \ + LDFLAGS="$(TARGET_CFLAGS)" \ + LIBS=`$(PKG_CONFIG_HOST_BINARY) --libs openssl` +OPENSSH_SYSTEMD_CONF_OPTS = \ + --sysconfdir=/etc/ssh \ + --with-default-path=$(BR2_SYSTEM_DEFAULT_PATH) \ + --disable-utmp \ + --disable-utmpx \ + --disable-wtmp \ + --disable-wtmpx \ + --disable-strip \ + --with-lastlog=/var/log/lastlog + +define OPENSSH_SYSTEMD_PERMISSIONS + /var/empty d 755 root root - - - - - +endef + +ifeq ($(BR2_TOOLCHAIN_SUPPORTS_PIE),) +OPENSSH_SYSTEMD_CONF_OPTS += --without-pie +endif + +OPENSSH_SYSTEMD_DEPENDENCIES = host-pkgconf zlib openssl + +ifeq ($(BR2_INIT_SYSTEMD),y) +OPENSSH_SYSTEMD_DEPENDENCIES += systemd +OPENSSH_SYSTEMD_CONF_OPTS += --with-systemd +endif + +# --with-systemd option requires reconfigure +OPENSSH_SYSTEMD_AUTORECONF = YES + +ifeq ($(BR2_PACKAGE_CRYPTODEV_LINUX),y) +OPENSSH_SYSTEMD_DEPENDENCIES += cryptodev-linux +OPENSSH_SYSTEMD_CONF_OPTS += --with-ssl-engine +else +OPENSSH_SYSTEMD_CONF_OPTS += --without-ssl-engine +endif + +ifeq ($(BR2_PACKAGE_LINUX_PAM),y) +define OPENSSH_SYSTEMD_INSTALL_PAM_CONF + $(INSTALL) -D -m 644 $(@D)/contrib/sshd.pam.generic $(TARGET_DIR)/etc/pam.d/sshd + $(SED) '\%password required /lib/security/pam_cracklib.so%d' $(TARGET_DIR)/etc/pam.d/sshd + $(SED) 's/\#UsePAM no/UsePAM yes/' $(TARGET_DIR)/etc/ssh/sshd_config +endef + +OPENSSH_SYSTEMD_DEPENDENCIES += linux-pam +OPENSSH_SYSTEMD_CONF_OPTS += --with-pam +OPENSSH_SYSTEMD_POST_INSTALL_TARGET_HOOKS += OPENSSH_SYSTEMD_INSTALL_PAM_CONF +else +OPENSSH_SYSTEMD_CONF_OPTS += --without-pam +endif + +ifeq ($(BR2_PACKAGE_LIBSELINUX),y) +OPENSSH_SYSTEMD_DEPENDENCIES += libselinux +OPENSSH_SYSTEMD_CONF_OPTS += --with-selinux +else +OPENSSH_SYSTEMD_CONF_OPTS += --without-selinux +endif + +ifeq ($(BR2_PACKAGE_SYSTEMD_SYSUSERS),y) +define OPENSSH_SYSTEMD_INSTALL_SYSTEMD_SYSUSERS + $(INSTALL) -m 0644 -D package/openssh/sshd-sysusers.conf \ + $(TARGET_DIR)/usr/lib/sysusers.d/sshd.conf +endef +else +define OPENSSH_SYSTEMD_USERS + sshd -1 sshd -1 * /var/empty - - SSH drop priv user +endef +endif + +define OPENSSH_SYSTEMD_INSTALL_INIT_SYSTEMD + $(INSTALL) -D -m 644 package/openssh/sshd.service \ + $(TARGET_DIR)/usr/lib/systemd/system/sshd.service + $(OPENSSH_SYSTEMD_INSTALL_SYSTEMD_SYSUSERS) +endef + +define OPENSSH_SYSTEMD_INSTALL_INIT_SYSV + $(INSTALL) -D -m 755 package/openssh/S50sshd \ + $(TARGET_DIR)/etc/init.d/S50sshd +endef + +define OPENSSH_SYSTEMD_INSTALL_SSH_COPY_ID + $(INSTALL) -D -m 755 $(@D)/contrib/ssh-copy-id $(TARGET_DIR)/usr/bin/ssh-copy-id +endef + +OPENSSH_SYSTEMD_POST_INSTALL_TARGET_HOOKS += OPENSSH_SYSTEMD_INSTALL_SSH_COPY_ID + +$(eval $(autotools-package)) diff --git a/packages/openssh-systemd/sshd-sysusers.conf b/packages/openssh-systemd/sshd-sysusers.conf new file mode 100644 index 0000000..ac77aec --- /dev/null +++ b/packages/openssh-systemd/sshd-sysusers.conf @@ -0,0 +1 @@ +u sshd - "SSH drop priv user" /var/empty diff --git a/packages/openssh-systemd/sshd.service b/packages/openssh-systemd/sshd.service new file mode 100644 index 0000000..b5e96b3 --- /dev/null +++ b/packages/openssh-systemd/sshd.service @@ -0,0 +1,11 @@ +[Unit] +Description=OpenSSH server daemon +After=syslog.target network.target auditd.service + +[Service] +ExecStartPre=/usr/bin/ssh-keygen -A +ExecStart=/usr/sbin/sshd -D -e +ExecReload=/bin/kill -HUP $MAINPID + +[Install] +WantedBy=multi-user.target diff --git a/packages/polkit-duktape/0001-make-netgroup-support-optional.patch b/packages/polkit-duktape/0001-make-netgroup-support-optional.patch new file mode 100644 index 0000000..86916ab --- /dev/null +++ b/packages/polkit-duktape/0001-make-netgroup-support-optional.patch @@ -0,0 +1,403 @@ +From 1b854ef4bb15032091a33fed587e5ba6f3e582eb Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Wed, 22 May 2019 13:18:55 -0700 +Subject: [PATCH] make netgroup support optional + +On at least Linux/musl and Linux/uclibc, netgroup +support is not available. PolKit fails to compile on these systems +for that reason. + +This change makes netgroup support conditional on the presence of the +setnetgrent(3) function which is required for the support to work. If +that function is not available on the system, an error will be returned +to the administrator if unix-netgroup: is specified in configuration. + +Fixes bug 50145. + +Signed-off-by: A. Wilcox +Signed-off-by: Khem Raj +Signed-off-by: Adam Duskett +[Thomas: add introspection.m4.] +Signed-off-by: Thomas Petazzoni +--- + buildutil/introspection.m4 | 142 ++++++++++++++++++ + configure.ac | 2 +- + src/polkit/polkitidentity.c | 16 ++ + src/polkit/polkitunixnetgroup.c | 3 + + .../polkitbackendinteractiveauthority.c | 14 +- + .../polkitbackendjsauthority.cpp | 2 + + test/polkit/polkitidentitytest.c | 9 +- + test/polkit/polkitunixnetgrouptest.c | 3 + + .../test-polkitbackendjsauthority.c | 2 + + 9 files changed, 185 insertions(+), 8 deletions(-) + create mode 100644 buildutil/introspection.m4 + +diff --git a/buildutil/introspection.m4 b/buildutil/introspection.m4 +new file mode 100644 +index 0000000..b0ccd68 +--- /dev/null ++++ b/buildutil/introspection.m4 +@@ -0,0 +1,142 @@ ++dnl -*- mode: autoconf -*- ++dnl Copyright 2009 Johan Dahlin ++dnl ++dnl This file is free software; the author(s) gives unlimited ++dnl permission to copy and/or distribute it, with or without ++dnl modifications, as long as this notice is preserved. ++dnl ++ ++# serial 1 ++ ++dnl This is a copy of AS_AC_EXPAND ++dnl ++dnl (C) 2003, 2004, 2005 Thomas Vander Stichele ++dnl Copying and distribution of this file, with or without modification, ++dnl are permitted in any medium without royalty provided the copyright ++dnl notice and this notice are preserved. ++m4_define([_GOBJECT_INTROSPECTION_AS_AC_EXPAND], ++[ ++ EXP_VAR=[$1] ++ FROM_VAR=[$2] ++ ++ dnl first expand prefix and exec_prefix if necessary ++ prefix_save=$prefix ++ exec_prefix_save=$exec_prefix ++ ++ dnl if no prefix given, then use /usr/local, the default prefix ++ if test "x$prefix" = "xNONE"; then ++ prefix="$ac_default_prefix" ++ fi ++ dnl if no exec_prefix given, then use prefix ++ if test "x$exec_prefix" = "xNONE"; then ++ exec_prefix=$prefix ++ fi ++ ++ full_var="$FROM_VAR" ++ dnl loop until it doesn't change anymore ++ while true; do ++ new_full_var="`eval echo $full_var`" ++ if test "x$new_full_var" = "x$full_var"; then break; fi ++ full_var=$new_full_var ++ done ++ ++ dnl clean up ++ full_var=$new_full_var ++ AC_SUBST([$1], "$full_var") ++ ++ dnl restore prefix and exec_prefix ++ prefix=$prefix_save ++ exec_prefix=$exec_prefix_save ++]) ++ ++m4_define([_GOBJECT_INTROSPECTION_CHECK_INTERNAL], ++[ ++ AC_BEFORE([AC_PROG_LIBTOOL],[$0])dnl setup libtool first ++ AC_BEFORE([AM_PROG_LIBTOOL],[$0])dnl setup libtool first ++ AC_BEFORE([LT_INIT],[$0])dnl setup libtool first ++ ++ dnl enable/disable introspection ++ m4_if([$2], [require], ++ [dnl ++ enable_introspection=yes ++ ],[dnl ++ AC_ARG_ENABLE(introspection, ++ AS_HELP_STRING([--enable-introspection[=@<:@no/auto/yes@:>@]], ++ [Enable introspection for this build]),, ++ [enable_introspection=auto]) ++ ])dnl ++ ++ AC_MSG_CHECKING([for gobject-introspection]) ++ ++ dnl presence/version checking ++ AS_CASE([$enable_introspection], ++ [no], [dnl ++ found_introspection="no (disabled, use --enable-introspection to enable)" ++ ],dnl ++ [yes],[dnl ++ PKG_CHECK_EXISTS([gobject-introspection-1.0],, ++ AC_MSG_ERROR([gobject-introspection-1.0 is not installed])) ++ PKG_CHECK_EXISTS([gobject-introspection-1.0 >= $1], ++ found_introspection=yes, ++ AC_MSG_ERROR([You need to have gobject-introspection >= $1 installed to build AC_PACKAGE_NAME])) ++ ],dnl ++ [auto],[dnl ++ PKG_CHECK_EXISTS([gobject-introspection-1.0 >= $1], found_introspection=yes, found_introspection=no) ++ dnl Canonicalize enable_introspection ++ enable_introspection=$found_introspection ++ ],dnl ++ [dnl ++ AC_MSG_ERROR([invalid argument passed to --enable-introspection, should be one of @<:@no/auto/yes@:>@]) ++ ])dnl ++ ++ AC_MSG_RESULT([$found_introspection]) ++ ++ dnl expand datadir/libdir so we can pass them to pkg-config ++ dnl and get paths relative to our target directories ++ _GOBJECT_INTROSPECTION_AS_AC_EXPAND(_GI_EXP_DATADIR, "$datadir") ++ _GOBJECT_INTROSPECTION_AS_AC_EXPAND(_GI_EXP_LIBDIR, "$libdir") ++ ++ INTROSPECTION_SCANNER= ++ INTROSPECTION_COMPILER= ++ INTROSPECTION_GENERATE= ++ INTROSPECTION_GIRDIR= ++ INTROSPECTION_TYPELIBDIR= ++ if test "x$found_introspection" = "xyes"; then ++ INTROSPECTION_SCANNER=$PKG_CONFIG_SYSROOT_DIR`$PKG_CONFIG --variable=g_ir_scanner gobject-introspection-1.0` ++ INTROSPECTION_COMPILER=$PKG_CONFIG_SYSROOT_DIR`$PKG_CONFIG --variable=g_ir_compiler gobject-introspection-1.0` ++ INTROSPECTION_GENERATE=$PKG_CONFIG_SYSROOT_DIR`$PKG_CONFIG --variable=g_ir_generate gobject-introspection-1.0` ++ INTROSPECTION_GIRDIR=`$PKG_CONFIG --define-variable=datadir="${_GI_EXP_DATADIR}" --variable=girdir gobject-introspection-1.0` ++ INTROSPECTION_TYPELIBDIR="$($PKG_CONFIG --define-variable=libdir="${_GI_EXP_LIBDIR}" --variable=typelibdir gobject-introspection-1.0)" ++ INTROSPECTION_CFLAGS=`$PKG_CONFIG --cflags gobject-introspection-1.0` ++ INTROSPECTION_LIBS=`$PKG_CONFIG --libs gobject-introspection-1.0` ++ INTROSPECTION_MAKEFILE=$PKG_CONFIG_SYSROOT_DIR`$PKG_CONFIG --variable=datadir gobject-introspection-1.0`/gobject-introspection-1.0/Makefile.introspection ++ fi ++ AC_SUBST(INTROSPECTION_SCANNER) ++ AC_SUBST(INTROSPECTION_COMPILER) ++ AC_SUBST(INTROSPECTION_GENERATE) ++ AC_SUBST(INTROSPECTION_GIRDIR) ++ AC_SUBST(INTROSPECTION_TYPELIBDIR) ++ AC_SUBST(INTROSPECTION_CFLAGS) ++ AC_SUBST(INTROSPECTION_LIBS) ++ AC_SUBST(INTROSPECTION_MAKEFILE) ++ ++ AM_CONDITIONAL(HAVE_INTROSPECTION, test "x$found_introspection" = "xyes") ++]) ++ ++ ++dnl Usage: ++dnl GOBJECT_INTROSPECTION_CHECK([minimum-g-i-version]) ++ ++AC_DEFUN([GOBJECT_INTROSPECTION_CHECK], ++[ ++ _GOBJECT_INTROSPECTION_CHECK_INTERNAL([$1]) ++]) ++ ++dnl Usage: ++dnl GOBJECT_INTROSPECTION_REQUIRE([minimum-g-i-version]) ++ ++ ++AC_DEFUN([GOBJECT_INTROSPECTION_REQUIRE], ++[ ++ _GOBJECT_INTROSPECTION_CHECK_INTERNAL([$1], [require]) ++]) +diff --git a/configure.ac b/configure.ac +index 5cedb4e..87aa0ad 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -99,7 +99,7 @@ AC_CHECK_LIB(expat,XML_ParserCreate,[EXPAT_LIBS="-lexpat"], + [AC_MSG_ERROR([Can't find expat library. Please install expat.])]) + AC_SUBST(EXPAT_LIBS) + +-AC_CHECK_FUNCS(clearenv fdatasync) ++AC_CHECK_FUNCS(clearenv fdatasync setnetgrent) + + if test "x$GCC" = "xyes"; then + LDFLAGS="-Wl,--as-needed $LDFLAGS" +diff --git a/src/polkit/polkitidentity.c b/src/polkit/polkitidentity.c +index 3aa1f7f..10e9c17 100644 +--- a/src/polkit/polkitidentity.c ++++ b/src/polkit/polkitidentity.c +@@ -182,7 +182,15 @@ polkit_identity_from_string (const gchar *str, + } + else if (g_str_has_prefix (str, "unix-netgroup:")) + { ++#ifndef HAVE_SETNETGRENT ++ g_set_error (error, ++ POLKIT_ERROR, ++ POLKIT_ERROR_FAILED, ++ "Netgroups are not available on this machine ('%s')", ++ str); ++#else + identity = polkit_unix_netgroup_new (str + sizeof "unix-netgroup:" - 1); ++#endif + } + + if (identity == NULL && (error != NULL && *error == NULL)) +@@ -344,6 +352,13 @@ polkit_identity_new_for_gvariant (GVariant *variant, + GVariant *v; + const char *name; + ++#ifndef HAVE_SETNETGRENT ++ g_set_error (error, ++ POLKIT_ERROR, ++ POLKIT_ERROR_FAILED, ++ "Netgroups are not available on this machine"); ++ goto out; ++#else + v = lookup_asv (details_gvariant, "name", G_VARIANT_TYPE_STRING, error); + if (v == NULL) + { +@@ -353,6 +368,7 @@ polkit_identity_new_for_gvariant (GVariant *variant, + name = g_variant_get_string (v, NULL); + ret = polkit_unix_netgroup_new (name); + g_variant_unref (v); ++#endif + } + else + { +diff --git a/src/polkit/polkitunixnetgroup.c b/src/polkit/polkitunixnetgroup.c +index 8a2b369..83f8d4a 100644 +--- a/src/polkit/polkitunixnetgroup.c ++++ b/src/polkit/polkitunixnetgroup.c +@@ -194,6 +194,9 @@ polkit_unix_netgroup_set_name (PolkitUnixNetgroup *group, + PolkitIdentity * + polkit_unix_netgroup_new (const gchar *name) + { ++#ifndef HAVE_SETNETGRENT ++ g_assert_not_reached(); ++#endif + g_return_val_if_fail (name != NULL, NULL); + return POLKIT_IDENTITY (g_object_new (POLKIT_TYPE_UNIX_NETGROUP, + "name", name, +diff --git a/src/polkitbackend/polkitbackendinteractiveauthority.c b/src/polkitbackend/polkitbackendinteractiveauthority.c +index 056d9a8..36c2f3d 100644 +--- a/src/polkitbackend/polkitbackendinteractiveauthority.c ++++ b/src/polkitbackend/polkitbackendinteractiveauthority.c +@@ -2233,25 +2233,26 @@ get_users_in_net_group (PolkitIdentity *group, + GList *ret; + + ret = NULL; ++#ifdef HAVE_SETNETGRENT + name = polkit_unix_netgroup_get_name (POLKIT_UNIX_NETGROUP (group)); + +-#ifdef HAVE_SETNETGRENT_RETURN ++# ifdef HAVE_SETNETGRENT_RETURN + if (setnetgrent (name) == 0) + { + g_warning ("Error looking up net group with name %s: %s", name, g_strerror (errno)); + goto out; + } +-#else ++# else + setnetgrent (name); +-#endif ++# endif /* HAVE_SETNETGRENT_RETURN */ + + for (;;) + { +-#if defined(HAVE_NETBSD) || defined(HAVE_OPENBSD) ++# if defined(HAVE_NETBSD) || defined(HAVE_OPENBSD) + const char *hostname, *username, *domainname; +-#else ++# else + char *hostname, *username, *domainname; +-#endif ++# endif /* defined(HAVE_NETBSD) || defined(HAVE_OPENBSD) */ + PolkitIdentity *user; + GError *error = NULL; + +@@ -2282,6 +2283,7 @@ get_users_in_net_group (PolkitIdentity *group, + + out: + endnetgrent (); ++#endif /* HAVE_SETNETGRENT */ + return ret; + } + +diff --git a/src/polkitbackend/polkitbackendjsauthority.cpp b/src/polkitbackend/polkitbackendjsauthority.cpp +index 9b752d1..09b2878 100644 +--- a/src/polkitbackend/polkitbackendjsauthority.cpp ++++ b/src/polkitbackend/polkitbackendjsauthority.cpp +@@ -1502,6 +1502,7 @@ js_polkit_user_is_in_netgroup (JSContext *cx, + + JS::CallArgs args = JS::CallArgsFromVp (argc, vp); + ++#ifdef HAVE_SETNETGRENT + JS::RootedString usrstr (authority->priv->cx); + usrstr = args[0].toString(); + user = JS_EncodeStringToUTF8 (cx, usrstr); +@@ -1519,6 +1520,7 @@ js_polkit_user_is_in_netgroup (JSContext *cx, + + JS_free (cx, netgroup); + JS_free (cx, user); ++#endif + + ret = true; + +diff --git a/test/polkit/polkitidentitytest.c b/test/polkit/polkitidentitytest.c +index e91967b..e829aaa 100644 +--- a/test/polkit/polkitidentitytest.c ++++ b/test/polkit/polkitidentitytest.c +@@ -19,6 +19,7 @@ + * Author: Nikki VonHollen + */ + ++#include "config.h" + #include "glib.h" + #include + #include +@@ -145,11 +146,15 @@ struct ComparisonTestData comparison_test_data [] = { + {"unix-group:root", "unix-group:jane", FALSE}, + {"unix-group:jane", "unix-group:jane", TRUE}, + ++#ifdef HAVE_SETNETGRENT + {"unix-netgroup:foo", "unix-netgroup:foo", TRUE}, + {"unix-netgroup:foo", "unix-netgroup:bar", FALSE}, ++#endif + + {"unix-user:root", "unix-group:root", FALSE}, ++#ifdef HAVE_SETNETGRENT + {"unix-user:jane", "unix-netgroup:foo", FALSE}, ++#endif + + {NULL}, + }; +@@ -181,11 +186,13 @@ main (int argc, char *argv[]) + g_test_add_data_func ("/PolkitIdentity/group_string_2", "unix-group:jane", test_string); + g_test_add_data_func ("/PolkitIdentity/group_string_3", "unix-group:users", test_string); + ++#ifdef HAVE_SETNETGRENT + g_test_add_data_func ("/PolkitIdentity/netgroup_string", "unix-netgroup:foo", test_string); ++ g_test_add_data_func ("/PolkitIdentity/netgroup_gvariant", "unix-netgroup:foo", test_gvariant); ++#endif + + g_test_add_data_func ("/PolkitIdentity/user_gvariant", "unix-user:root", test_gvariant); + g_test_add_data_func ("/PolkitIdentity/group_gvariant", "unix-group:root", test_gvariant); +- g_test_add_data_func ("/PolkitIdentity/netgroup_gvariant", "unix-netgroup:foo", test_gvariant); + + add_comparison_tests (); + +diff --git a/test/polkit/polkitunixnetgrouptest.c b/test/polkit/polkitunixnetgrouptest.c +index 3701ba1..e3352eb 100644 +--- a/test/polkit/polkitunixnetgrouptest.c ++++ b/test/polkit/polkitunixnetgrouptest.c +@@ -19,6 +19,7 @@ + * Author: Nikki VonHollen + */ + ++#include "config.h" + #include "glib.h" + #include + #include +@@ -69,7 +70,9 @@ int + main (int argc, char *argv[]) + { + g_test_init (&argc, &argv, NULL); ++#ifdef HAVE_SETNETGRENT + g_test_add_func ("/PolkitUnixNetgroup/new", test_new); + g_test_add_func ("/PolkitUnixNetgroup/set_name", test_set_name); ++#endif + return g_test_run (); + } +diff --git a/test/polkitbackend/test-polkitbackendjsauthority.c b/test/polkitbackend/test-polkitbackendjsauthority.c +index 71aad23..fdd28f3 100644 +--- a/test/polkitbackend/test-polkitbackendjsauthority.c ++++ b/test/polkitbackend/test-polkitbackendjsauthority.c +@@ -137,12 +137,14 @@ test_get_admin_identities (void) + "unix-group:users" + } + }, ++#ifdef HAVE_SETNETGRENT + { + "net.company.action3", + { + "unix-netgroup:foo" + } + }, ++#endif + }; + guint n; + +-- +2.25.1 + diff --git a/packages/polkit-duktape/0002-jsauthority-memleak.patch b/packages/polkit-duktape/0002-jsauthority-memleak.patch new file mode 100644 index 0000000..4f07331 --- /dev/null +++ b/packages/polkit-duktape/0002-jsauthority-memleak.patch @@ -0,0 +1,28 @@ +From 28e3a6653d8c3777b07e0128a0d97d46e586e311 Mon Sep 17 00:00:00 2001 +From: Jan Rybar +Date: Tue, 8 Oct 2019 13:28:18 +0000 +Subject: [PATCH] jsauthority: Fix two minor memory leaks + +(cherry picked from commit 28e3a6653d8c3777b07e0128a0d97d46e586e311) +Signed-off-by: Jan Rybar +Signed-off-by: Adam Duskett +--- + src/polkitbackend/polkitbackendjsauthority.cpp | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/polkitbackend/polkitbackendjsauthority.cpp b/src/polkitbackend/polkitbackendjsauthority.cpp +index 9b752d1..e97b8aa 100644 +--- a/src/polkitbackend/polkitbackendjsauthority.cpp ++++ b/src/polkitbackend/polkitbackendjsauthority.cpp +@@ -567,6 +567,8 @@ polkit_backend_js_authority_finalize (GObject *object) + g_strfreev (authority->priv->rules_dirs); + + delete authority->priv->ac; ++ delete authority->priv->js_global; ++ delete authority->priv->js_polkit; + + JS_DestroyContext (authority->priv->cx); + /* JS_ShutDown (); */ +-- +2.24.1 + diff --git a/packages/polkit-duktape/0003-polkit-0.116-pkttyagent-sigttou-bg-job.patch b/packages/polkit-duktape/0003-polkit-0.116-pkttyagent-sigttou-bg-job.patch new file mode 100644 index 0000000..fb41df3 --- /dev/null +++ b/packages/polkit-duktape/0003-polkit-0.116-pkttyagent-sigttou-bg-job.patch @@ -0,0 +1,34 @@ +From 76aae4fce586b400f5fe08df31497db19d624609 Mon Sep 17 00:00:00 2001 +From: Jan Rybar +Date: Thu, 1 Aug 2019 06:46:10 +0000 +Subject: [PATCH] pkttyagent: process stopped by SIGTTOU if run in background + job + + +(cherry picked from commit 76aae4fce586b400f5fe08df31497db19d624609) +Signed-off-by: Jan Rybar +Signed-off-by: Adam Duskett +--- + src/programs/pkttyagent.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/src/programs/pkttyagent.c b/src/programs/pkttyagent.c +index 3c8d502..13879a2 100644 +--- a/src/programs/pkttyagent.c ++++ b/src/programs/pkttyagent.c +@@ -264,6 +264,12 @@ main (int argc, char *argv[]) + + memset (&sa, 0, sizeof (sa)); + sa.sa_handler = &tty_handler; ++/* If tty_handler() resets terminal while pkttyagent is run in background job, ++ the process gets stopped by SIGTTOU. This impacts systemctl, hence it must ++ be blocked for a while and then the process gets killed anyway. ++ */ ++ sigemptyset(&sa.sa_mask); ++ sigaddset(&sa.sa_mask, SIGTTOU); + sigaction (SIGTERM, &sa, &savesigterm); + sigaction (SIGINT, &sa, &savesigint); + sigaction (SIGTSTP, &sa, &savesigtstp); +-- +2.24.1 + diff --git a/packages/polkit-duktape/Config.in b/packages/polkit-duktape/Config.in new file mode 100644 index 0000000..deae3ff --- /dev/null +++ b/packages/polkit-duktape/Config.in @@ -0,0 +1,17 @@ +config BR2_PACKAGE_POLKIT_DUKTAPE + bool "polkit-duktape" + depends on BR2_USE_MMU # libglib2, dbus + depends on BR2_USE_WCHAR # libglib2 + select BR2_PACKAGE_DBUS # runtime + select BR2_PACKAGE_EXPAT + select BR2_PACKAGE_LIBGLIB2 + select BR2_PACKAGE_DUKTAPE_PC + help + PolicyKit is a toolkit for defining and handling + authorizations. It is used for allowing unprivileged + processes to speak to privileged processes. + + http://www.freedesktop.org/wiki/Software/polkit + +comment "polkit needs a toolchain with wchar, dynamic library" + depends on BR2_USE_MMU diff --git a/packages/polkit-duktape/polkit-duktape.hash b/packages/polkit-duktape/polkit-duktape.hash new file mode 100644 index 0000000..bacd682 --- /dev/null +++ b/packages/polkit-duktape/polkit-duktape.hash @@ -0,0 +1,5 @@ +# Locally calculated after checking pgp signature +sha256 88170c9e711e8db305a12fdb8234fac5706c61969b94e084d0f117d8ec5d34b1 polkit-0.116.tar.gz + +# Locally calculated +sha256 d2e2aa973e29c75e1b492e67ea7b7da9de2d501d49a934657971fd74f9a0b0a8 COPYING diff --git a/packages/polkit-duktape/polkit-duktape.mk b/packages/polkit-duktape/polkit-duktape.mk new file mode 100644 index 0000000..70602bb --- /dev/null +++ b/packages/polkit-duktape/polkit-duktape.mk @@ -0,0 +1,61 @@ +################################################################################ +# +# polkit-duktape +# +################################################################################ + +POLKIT_DUKTAPE_VERSION = 0.116 +POLKIT_DUKTAPE_SITE = http://www.freedesktop.org/software/polkit/releases +POLKIT_DUKTAPE_SOURCE = polkit-$(POLKIT_DUKTAPE_VERSION).tar.gz +POLKIT_DUKTAPE_LICENSE = GPL-2.0 +POLKIT_DUKTAPE_LICENSE_FILES = COPYING +POLKIT_DUKTAPE_AUTORECONF = YES +POLKIT_DUKTAPE_INSTALL_STAGING = YES + +POLKIT_DUKTAPE_DEPENDENCIES = \ + libglib2 host-intltool expat duktape-pc $(TARGET_NLS_DEPENDENCIES) + +# spidermonkey needs C++11 +POLKIT_DUKTAPE_CONF_ENV = \ +# CXXFLAGS="$(TARGET_CXXFLAGS) -std=c++11" \ + LIBS=$(TARGET_NLS_LIBS) + +POLKIT_DUKTAPE_CONF_OPTS = \ + --with-os-type=unknown \ + --disable-man-pages \ + --disable-examples \ + --disable-libelogind \ + --disable-libsystemd-login \ + --with-duktape + +ifeq ($(BR2_PACKAGE_GOBJECT_INTROSPECTION),y) +POLKIT_DUKTAPE_CONF_OPTS += --enable-introspection +POLKIT_DUKTAPE_DEPENDENCIES += gobject-introspection +else +POLKIT_DUKTAPE_CONF_OPTS += --disable-introspection +endif + +ifeq ($(BR2_PACKAGE_LINUX_PAM),y) +POLKIT_DUKTAPE_DEPENDENCIES += linux-pam +POLKIT_DUKTAPE_CONF_OPTS += --with-authfw=pam +else +POLKIT_DUKTAPE_CONF_OPTS += --with-authfw=shadow +endif + +define POLKIT_DUKTAPE_USERS + polkitd -1 polkitd -1 * - - - Polkit Daemon +endef + +define POLKIT_DUKTAPE_PERMISSIONS + /etc/polkit-1 r 750 root polkitd - - - - - + /usr/share/polkit-1 r 750 root polkitd - - - - - + /usr/bin/pkexec f 4755 root root - - - - - +endef + +define POLKIT_DUKTAPE_INSTALL_INIT_SYSTEMD + $(INSTALL) -D -m 644 $(POLKIT_DUKTAPE_PKGDIR)/polkit.service \ + $(TARGET_DIR)/usr/lib/systemd/system/polkit.service + +endef + +$(eval $(autotools-package)) diff --git a/packages/polkit-duktape/polkit.service b/packages/polkit-duktape/polkit.service new file mode 100644 index 0000000..a69b28c --- /dev/null +++ b/packages/polkit-duktape/polkit.service @@ -0,0 +1,12 @@ +[Unit] + +Description=Authorization Manager +Documentation=man:polkit(8) + +[Service] +Type=dbus +BusName=org.freedesktop.PolicyKit1 +ExecStart=/usr/lib/polkit-1/polkitd --no-debug + +[Install] +WantedBy=multi-user.target