diff --git a/drivers/tests/TESTS/mbed_drivers/ticker/main.cpp b/drivers/tests/TESTS/mbed_drivers/ticker/main.cpp
index da0f371..2d3c015 100644
--- a/drivers/tests/TESTS/mbed_drivers/ticker/main.cpp
+++ b/drivers/tests/TESTS/mbed_drivers/ticker/main.cpp
@@ -185,6 +185,7 @@
     }
 
     ThisThread::sleep_for(MULTI_TICKER_TIME + extra_wait);
+
     TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter);
 
     for (int i = 0; i < TICKER_COUNT; i++) {
diff --git a/hal/tests/TESTS/mbed_hal/sleep/main.cpp b/hal/tests/TESTS/mbed_hal/sleep/main.cpp
index 2ff4712..bbd8b66 100644
--- a/hal/tests/TESTS/mbed_hal/sleep/main.cpp
+++ b/hal/tests/TESTS/mbed_hal/sleep/main.cpp
@@ -20,6 +20,8 @@
 
 #include "mbed.h"
 
+#include <cinttypes>
+
 #include "utest/utest.h"
 #include "unity/unity.h"
 #include "greentea-client/test_env.h"
@@ -146,7 +148,7 @@
 
         const timestamp_t wakeup_timestamp = lp_ticker_read();
 
-        sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %d, Actual wake up tick: %d, delay ticks: %d, wake up after ticks: %d",
+        sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %" PRIu32 ", Actual wake up tick: %" PRIu32 ", delay ticks: %d, wake up after ticks: %" PRIu32 "\n",
                 us_to_ticks(deepsleep_mode_delta_us, ticker_freq), ticker_width, next_match_timestamp, wakeup_timestamp, us_to_ticks(i, ticker_freq),  wakeup_timestamp - start_timestamp);
 
         TEST_ASSERT_MESSAGE(compare_timestamps(us_to_ticks(deepsleep_mode_delta_us, ticker_freq), ticker_width,
@@ -196,7 +198,7 @@
 
     TEST_ASSERT_UINT32_WITHIN(1000, 0, ticks_to_us(us_ticks_diff, us_ticker_freq));
 
-    sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %d, Actual wake up tick: %d",
+    sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %" PRIu32 ", Actual wake up tick: %d\n",
             us_to_ticks(deepsleep_mode_delta_us, lp_ticker_freq), lp_ticker_width, wakeup_time, lp_ticks_after_sleep);
 
     /* Check if we have woken-up after expected time. */
diff --git a/hal/tests/TESTS/mbed_hal/sleep_manager/main.cpp b/hal/tests/TESTS/mbed_hal/sleep_manager/main.cpp
index 470884e..4aa74cd 100644
--- a/hal/tests/TESTS/mbed_hal/sleep_manager/main.cpp
+++ b/hal/tests/TESTS/mbed_hal/sleep_manager/main.cpp
@@ -28,7 +28,12 @@
 #error [NOT_SUPPORTED] test not supported
 #else
 
-#define SLEEP_DURATION_US 20000ULL
+#define SLEEP_DURATION_US 50000ULL
+
+// Tolerance for extra sleep time in the deep sleep test.
+// Current leader is the MIMXRT105x, which takes almost 5ms to enter/exit deep sleep.
+#define DEEP_SLEEP_TOLERANCE_US 5000ULL
+
 #define DEEP_SLEEP_TEST_CHECK_WAIT_US 2000
 // As sleep_manager_can_deep_sleep_test_check() is based on wait_ns
 // and wait_ns can be up to 40% slower, use a 50% delta here.
@@ -217,9 +222,12 @@
     // 1. current lp_ticker increment,
     // 2. previous us_ticker increment (locked sleep test above)
 
+    const unsigned int deepsleep_tolerance_lp_ticks = us_to_ticks(DEEP_SLEEP_TOLERANCE_US, lp_ticker_info->frequency);
+    const unsigned int deepsleep_tolerance_us_ticks = us_to_ticks(DEEP_SLEEP_TOLERANCE_US, us_ticker_info->frequency);
+
     // us ticker should not have incremented during deep sleep.  It should be zero, plus some tolerance for the time to enter deep sleep.
-    TEST_ASSERT_UINT64_WITHIN_MESSAGE(sleep_duration_us_ticks / 10ULL, 0, us_diff2, "us ticker sleep time incorrect - perhaps deep sleep mode was not used?");
-    TEST_ASSERT_UINT64_WITHIN_MESSAGE(sleep_duration_lp_ticks / 10ULL, sleep_duration_lp_ticks, lp_diff2, "lp ticker sleep time incorrect");
+    TEST_ASSERT_UINT64_WITHIN_MESSAGE(deepsleep_tolerance_us_ticks, 0, us_diff2, "us ticker sleep time incorrect - perhaps deep sleep mode was not used?");
+    TEST_ASSERT_UINT64_WITHIN_MESSAGE(deepsleep_tolerance_lp_ticks, sleep_duration_lp_ticks, lp_diff2, "lp ticker sleep time incorrect");
 
     set_us_ticker_irq_handler(us_ticker_irq_handler_org);
     set_lp_ticker_irq_handler(lp_ticker_irq_handler_org);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.c
index 59bc5eb..dd5e8d2 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.c
@@ -20,14 +20,13 @@
  *
  */
 
-
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
 product: Clocks v11.0
 processor: MIMXRT1052xxxxB
 package_id: MIMXRT1052DVL6B
 mcu_data: ksdk2_0
-processor_version: 13.0.1
+processor_version: 13.0.2
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
 #include "clock_config.h"
@@ -46,6 +45,7 @@
  ******************************************************************************/
 void BOARD_InitBootClocks(void)
 {
+    BOARD_ClockOverdrive();
 }
 
 /*******************************************************************************
@@ -66,15 +66,15 @@
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
-- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz}
-- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 132 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
-- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 10 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 2880/77 MHz}
 - {id: LVDS1_CLK.outFreq, value: 1.056 GHz}
 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
-- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
@@ -89,7 +89,7 @@
 - {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
-- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
 settings:
@@ -97,10 +97,14 @@
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
 - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
 - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
-- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
-- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.LPI2C_CLK_PODF.scale, value: '6', locked: true}
+- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '7', locked: true}
+- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
+- {id: CCM.PERCLK_PODF.scale, value: '1', locked: true}
 - {id: CCM.SEMC_PODF.scale, value: '8'}
 - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '44', locked: true}
@@ -194,7 +198,7 @@
     CLOCK_DisableClock(kCLOCK_Gpt2S);
     CLOCK_DisableClock(kCLOCK_Pit);
     /* Set PERCLK_PODF. */
-    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
     /* Disable USDHC1 clock gate. */
     CLOCK_DisableClock(kCLOCK_Usdhc1);
     /* Set USDHC1_PODF. */
@@ -243,9 +247,9 @@
     CLOCK_DisableClock(kCLOCK_Lpspi3);
     CLOCK_DisableClock(kCLOCK_Lpspi4);
     /* Set LPSPI_PODF. */
-    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 6);
     /* Set Lpspi clock source. */
-    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    CLOCK_SetMux(kCLOCK_LpspiMux, 1);
     /* Disable TRACE clock gate. */
     CLOCK_DisableClock(kCLOCK_Trace);
     /* Set TRACE_PODF. */
@@ -281,7 +285,7 @@
     CLOCK_DisableClock(kCLOCK_Lpi2c2);
     CLOCK_DisableClock(kCLOCK_Lpi2c3);
     /* Set LPI2C_CLK_PODF. */
-    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
     /* Set Lpi2c clock source. */
     CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
     /* Disable CAN clock gate. */
@@ -305,7 +309,7 @@
     /* Set UART_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
     /* Set Uart clock source. */
-    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    CLOCK_SetMux(kCLOCK_UartMux, 1);
     /* Disable LCDIF clock gate. */
     CLOCK_DisableClock(kCLOCK_LcdPixel);
     /* Set LCDIF_PRED. */
@@ -417,7 +421,7 @@
     /* Set periph clock2 clock source. */
     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
     /* Set per clock source. */
-    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    CLOCK_SetMux(kCLOCK_PerclkMux, 1);
     /* Set lvds1 clock source. */
     CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
     /* Set clock out1 divider. */
@@ -469,6 +473,7 @@
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!Configuration
 name: BOARD_ClockOverdrive
+called_from_default_init: true
 outputs:
 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
@@ -481,15 +486,15 @@
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
-- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
-- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
-- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 10 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 2880/77 MHz}
 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
-- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
@@ -504,7 +509,7 @@
 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
-- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
 settings:
@@ -512,10 +517,14 @@
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
 - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
 - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
-- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
-- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.LPI2C_CLK_PODF.scale, value: '6', locked: true}
+- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '7', locked: true}
+- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
+- {id: CCM.PERCLK_PODF.scale, value: '1', locked: true}
 - {id: CCM.SEMC_PODF.scale, value: '8'}
 - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
@@ -615,7 +624,7 @@
     CLOCK_DisableClock(kCLOCK_Gpt2S);
     CLOCK_DisableClock(kCLOCK_Pit);
     /* Set PERCLK_PODF. */
-    CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+    CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
     /* Disable USDHC1 clock gate. */
     CLOCK_DisableClock(kCLOCK_Usdhc1);
     /* Set USDHC1_PODF. */
@@ -664,9 +673,9 @@
     CLOCK_DisableClock(kCLOCK_Lpspi3);
     CLOCK_DisableClock(kCLOCK_Lpspi4);
     /* Set LPSPI_PODF. */
-    CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 6);
     /* Set Lpspi clock source. */
-    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    CLOCK_SetMux(kCLOCK_LpspiMux, 1);
     /* Disable TRACE clock gate. */
     CLOCK_DisableClock(kCLOCK_Trace);
     /* Set TRACE_PODF. */
@@ -702,7 +711,7 @@
     CLOCK_DisableClock(kCLOCK_Lpi2c2);
     CLOCK_DisableClock(kCLOCK_Lpi2c3);
     /* Set LPI2C_CLK_PODF. */
-    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
     /* Set Lpi2c clock source. */
     CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
     /* Disable CAN clock gate. */
@@ -726,7 +735,7 @@
     /* Set UART_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
     /* Set Uart clock source. */
-    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    CLOCK_SetMux(kCLOCK_UartMux, 1);
     /* Disable LCDIF clock gate. */
     CLOCK_DisableClock(kCLOCK_LcdPixel);
     /* Set LCDIF_PRED. */
@@ -838,7 +847,7 @@
     /* Set periph clock2 clock source. */
     CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
     /* Set per clock source. */
-    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    CLOCK_SetMux(kCLOCK_PerclkMux, 1);
     /* Set lvds1 clock source. */
     CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
     /* Set clock out1 divider. */
@@ -902,15 +911,15 @@
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz}
-- {id: GPT1_ipg_clk_highfreq.outFreq, value: 12 MHz}
-- {id: GPT2_ipg_clk_highfreq.outFreq, value: 12 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 12 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: LVDS1_CLK.outFreq, value: 24 MHz}
 - {id: MQS_MCLK.outFreq, value: 3 MHz}
-- {id: PERCLK_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
 - {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: SAI1_MCLK1.outFreq, value: 3 MHz}
@@ -925,15 +934,19 @@
 - {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
 - {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
-- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
 - {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
 settings:
 - {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
 - {id: CCM.IPG_PODF.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '8', locked: true}
+- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM.PERIPH_CLK2_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM.PERIPH_CLK_SEL.sel, value: CCM.PERIPH_CLK2_PODF}
 - {id: CCM.SEMC_PODF.scale, value: '1', locked: true}
+- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM_ANALOG.PLL2.denom, value: '1'}
 - {id: CCM_ANALOG.PLL2.num, value: '0'}
 - {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'}
@@ -1036,9 +1049,9 @@
     CLOCK_DisableClock(kCLOCK_Lpspi3);
     CLOCK_DisableClock(kCLOCK_Lpspi4);
     /* Set LPSPI_PODF. */
-    CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
+    CLOCK_SetDiv(kCLOCK_LpspiDiv, 7);
     /* Set Lpspi clock source. */
-    CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+    CLOCK_SetMux(kCLOCK_LpspiMux, 1);
     /* Disable TRACE clock gate. */
     CLOCK_DisableClock(kCLOCK_Trace);
     /* Set TRACE_PODF. */
@@ -1098,7 +1111,7 @@
     /* Set UART_CLK_PODF. */
     CLOCK_SetDiv(kCLOCK_UartDiv, 0);
     /* Set Uart clock source. */
-    CLOCK_SetMux(kCLOCK_UartMux, 0);
+    CLOCK_SetMux(kCLOCK_UartMux, 1);
     /* Disable LCDIF clock gate. */
     CLOCK_DisableClock(kCLOCK_LcdPixel);
     /* Set LCDIF_PRED. */
@@ -1206,7 +1219,7 @@
     /* Set periph clock source. */
     CLOCK_SetMux(kCLOCK_PeriphMux, 1);
     /* Set per clock source. */
-    CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+    CLOCK_SetMux(kCLOCK_PerclkMux, 1);
     /* Set lvds1 clock source. */
     CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
     /* Set clock out1 divider. */
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.h
index 57cbd76..565b11f 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.h
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.h
@@ -58,15 +58,15 @@
 #define BOARD_CLOCKFULLSPEED_FLEXIO1_CLK_ROOT         30000000UL
 #define BOARD_CLOCKFULLSPEED_FLEXIO2_CLK_ROOT         30000000UL
 #define BOARD_CLOCKFULLSPEED_FLEXSPI_CLK_ROOT         160000000UL
-#define BOARD_CLOCKFULLSPEED_GPT1_IPG_CLK_HIGHFREQ    66000000UL
-#define BOARD_CLOCKFULLSPEED_GPT2_IPG_CLK_HIGHFREQ    66000000UL
+#define BOARD_CLOCKFULLSPEED_GPT1_IPG_CLK_HIGHFREQ    24000000UL
+#define BOARD_CLOCKFULLSPEED_GPT2_IPG_CLK_HIGHFREQ    24000000UL
 #define BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT             132000000UL
 #define BOARD_CLOCKFULLSPEED_LCDIF_CLK_ROOT           67500000UL
-#define BOARD_CLOCKFULLSPEED_LPI2C_CLK_ROOT           60000000UL
-#define BOARD_CLOCKFULLSPEED_LPSPI_CLK_ROOT           105600000UL
+#define BOARD_CLOCKFULLSPEED_LPI2C_CLK_ROOT           10000000UL
+#define BOARD_CLOCKFULLSPEED_LPSPI_CLK_ROOT           37402597UL
 #define BOARD_CLOCKFULLSPEED_LVDS1_CLK                1056000000UL
 #define BOARD_CLOCKFULLSPEED_MQS_MCLK                 63529411UL
-#define BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT          66000000UL
+#define BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT          24000000UL
 #define BOARD_CLOCKFULLSPEED_PLL7_MAIN_CLK            24000000UL
 #define BOARD_CLOCKFULLSPEED_SAI1_CLK_ROOT            63529411UL
 #define BOARD_CLOCKFULLSPEED_SAI1_MCLK1               63529411UL
@@ -84,7 +84,7 @@
 #define BOARD_CLOCKFULLSPEED_SPDIF0_CLK_ROOT          30000000UL
 #define BOARD_CLOCKFULLSPEED_SPDIF0_EXTCLK_OUT        0UL
 #define BOARD_CLOCKFULLSPEED_TRACE_CLK_ROOT           117333333UL
-#define BOARD_CLOCKFULLSPEED_UART_CLK_ROOT            80000000UL
+#define BOARD_CLOCKFULLSPEED_UART_CLK_ROOT            24000000UL
 #define BOARD_CLOCKFULLSPEED_USBPHY1_CLK              0UL
 #define BOARD_CLOCKFULLSPEED_USBPHY2_CLK              0UL
 #define BOARD_CLOCKFULLSPEED_USDHC1_CLK_ROOT          198000000UL
@@ -141,15 +141,15 @@
 #define BOARD_CLOCKOVERDRIVE_FLEXIO1_CLK_ROOT         30000000UL
 #define BOARD_CLOCKOVERDRIVE_FLEXIO2_CLK_ROOT         30000000UL
 #define BOARD_CLOCKOVERDRIVE_FLEXSPI_CLK_ROOT         160000000UL
-#define BOARD_CLOCKOVERDRIVE_GPT1_IPG_CLK_HIGHFREQ    75000000UL
-#define BOARD_CLOCKOVERDRIVE_GPT2_IPG_CLK_HIGHFREQ    75000000UL
+#define BOARD_CLOCKOVERDRIVE_GPT1_IPG_CLK_HIGHFREQ    24000000UL
+#define BOARD_CLOCKOVERDRIVE_GPT2_IPG_CLK_HIGHFREQ    24000000UL
 #define BOARD_CLOCKOVERDRIVE_IPG_CLK_ROOT             150000000UL
 #define BOARD_CLOCKOVERDRIVE_LCDIF_CLK_ROOT           67500000UL
-#define BOARD_CLOCKOVERDRIVE_LPI2C_CLK_ROOT           60000000UL
-#define BOARD_CLOCKOVERDRIVE_LPSPI_CLK_ROOT           105600000UL
+#define BOARD_CLOCKOVERDRIVE_LPI2C_CLK_ROOT           10000000UL
+#define BOARD_CLOCKOVERDRIVE_LPSPI_CLK_ROOT           37402597UL
 #define BOARD_CLOCKOVERDRIVE_LVDS1_CLK                1200000000UL
 #define BOARD_CLOCKOVERDRIVE_MQS_MCLK                 63529411UL
-#define BOARD_CLOCKOVERDRIVE_PERCLK_CLK_ROOT          75000000UL
+#define BOARD_CLOCKOVERDRIVE_PERCLK_CLK_ROOT          24000000UL
 #define BOARD_CLOCKOVERDRIVE_PLL7_MAIN_CLK            24000000UL
 #define BOARD_CLOCKOVERDRIVE_SAI1_CLK_ROOT            63529411UL
 #define BOARD_CLOCKOVERDRIVE_SAI1_MCLK1               63529411UL
@@ -167,7 +167,7 @@
 #define BOARD_CLOCKOVERDRIVE_SPDIF0_CLK_ROOT          30000000UL
 #define BOARD_CLOCKOVERDRIVE_SPDIF0_EXTCLK_OUT        0UL
 #define BOARD_CLOCKOVERDRIVE_TRACE_CLK_ROOT           117333333UL
-#define BOARD_CLOCKOVERDRIVE_UART_CLK_ROOT            80000000UL
+#define BOARD_CLOCKOVERDRIVE_UART_CLK_ROOT            24000000UL
 #define BOARD_CLOCKOVERDRIVE_USBPHY1_CLK              0UL
 #define BOARD_CLOCKOVERDRIVE_USBPHY2_CLK              0UL
 #define BOARD_CLOCKOVERDRIVE_USDHC1_CLK_ROOT          198000000UL
@@ -224,15 +224,15 @@
 #define BOARD_CLOCKLOWPOWER_FLEXIO1_CLK_ROOT          1500000UL
 #define BOARD_CLOCKLOWPOWER_FLEXIO2_CLK_ROOT          1500000UL
 #define BOARD_CLOCKLOWPOWER_FLEXSPI_CLK_ROOT          24000000UL
-#define BOARD_CLOCKLOWPOWER_GPT1_IPG_CLK_HIGHFREQ     12000000UL
-#define BOARD_CLOCKLOWPOWER_GPT2_IPG_CLK_HIGHFREQ     12000000UL
+#define BOARD_CLOCKLOWPOWER_GPT1_IPG_CLK_HIGHFREQ     24000000UL
+#define BOARD_CLOCKLOWPOWER_GPT2_IPG_CLK_HIGHFREQ     24000000UL
 #define BOARD_CLOCKLOWPOWER_IPG_CLK_ROOT              12000000UL
 #define BOARD_CLOCKLOWPOWER_LCDIF_CLK_ROOT            3000000UL
 #define BOARD_CLOCKLOWPOWER_LPI2C_CLK_ROOT            3000000UL
-#define BOARD_CLOCKLOWPOWER_LPSPI_CLK_ROOT            6000000UL
+#define BOARD_CLOCKLOWPOWER_LPSPI_CLK_ROOT            3000000UL
 #define BOARD_CLOCKLOWPOWER_LVDS1_CLK                 24000000UL
 #define BOARD_CLOCKLOWPOWER_MQS_MCLK                  3000000UL
-#define BOARD_CLOCKLOWPOWER_PERCLK_CLK_ROOT           12000000UL
+#define BOARD_CLOCKLOWPOWER_PERCLK_CLK_ROOT           24000000UL
 #define BOARD_CLOCKLOWPOWER_PLL7_MAIN_CLK             24000000UL
 #define BOARD_CLOCKLOWPOWER_SAI1_CLK_ROOT             3000000UL
 #define BOARD_CLOCKLOWPOWER_SAI1_MCLK1                3000000UL
@@ -250,7 +250,7 @@
 #define BOARD_CLOCKLOWPOWER_SPDIF0_CLK_ROOT           1500000UL
 #define BOARD_CLOCKLOWPOWER_SPDIF0_EXTCLK_OUT         0UL
 #define BOARD_CLOCKLOWPOWER_TRACE_CLK_ROOT            6000000UL
-#define BOARD_CLOCKLOWPOWER_UART_CLK_ROOT             4000000UL
+#define BOARD_CLOCKLOWPOWER_UART_CLK_ROOT             24000000UL
 #define BOARD_CLOCKLOWPOWER_USBPHY1_CLK               0UL
 #define BOARD_CLOCKLOWPOWER_USBPHY2_CLK               0UL
 #define BOARD_CLOCKLOWPOWER_USDHC1_CLK_ROOT           12000000UL
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c
index 2e1d22c..07247f5 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mbed_overrides.c
@@ -20,9 +20,12 @@
 #include "fsl_xbara.h"
 #include "fsl_iomuxc.h"
 #include "fsl_gpio.h"
+#include "fsl_pit.h"
 #include "lpm.h"
 #include "usb_phy.h"
 #include "usb_device_config.h"
+#include "us_ticker_defines.h"
+#include "us_ticker_api.h"
 
 #define LPSPI_CLOCK_SOURCE_DIVIDER (7U)
 #define LPI2C_CLOCK_SOURCE_DIVIDER (5U)
@@ -180,6 +183,9 @@
     BOARD_ClockFullSpeed();
 #endif
 
+    // Initialize us ticker before LPM, because LPM uses it for timing
+    us_ticker_init();
+
 
 #if TARGET_EVK
     /* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is
@@ -193,59 +199,32 @@
 
 void spi_setup_clock()
 {
-    /*Set clock source for LPSPI*/
-    CLOCK_SetMux(kCLOCK_LpspiMux, 1U);
-    CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLOCK_SOURCE_DIVIDER);
+    // Not needed on MIMXRT105x
 }
 
 uint32_t spi_get_clock(void)
 {
-    return (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (LPSPI_CLOCK_SOURCE_DIVIDER + 1U));
-}
-
-void us_ticker_setup_clock()
-{
-    /* Set PERCLK_CLK source to OSC_CLK*/
-    CLOCK_SetMux(kCLOCK_PerclkMux, 1U);
-    /* Set PERCLK_CLK divider to 1 */
-    CLOCK_SetDiv(kCLOCK_PerclkDiv, 0U);
+    return BOARD_CLOCKFULLSPEED_LPSPI_CLK_ROOT;
 }
 
 uint32_t us_ticker_get_clock()
 {
-    return CLOCK_GetFreq(kCLOCK_OscClk);
-}
-
-void serial_setup_clock(void)
-{
-    /* Configure UART divider to default */
-    CLOCK_SetMux(kCLOCK_UartMux, 1); /* Set UART source to OSC 24M */
-    CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
+    return BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT;
 }
 
 uint32_t serial_get_clock(void)
 {
-    uint32_t clock_freq;
-
-    if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ {
-        clock_freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
-    } else {
-        clock_freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
-    }
-
-    return clock_freq;
+    return BOARD_CLOCKFULLSPEED_UART_CLK_ROOT;
 }
 
 void i2c_setup_clock()
 {
-    /* Select USB1 PLL (480 MHz) as master lpi2c clock source */
-    CLOCK_SetMux(kCLOCK_Lpi2cMux, 0U);
-    CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER);
+    // Not needed on MIMXRT105x
 }
 
 uint32_t i2c_get_clock()
 {
-    return ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U));
+    return BOARD_CLOCKFULLSPEED_LPI2C_CLK_ROOT;
 }
 
 void pwm_setup(uint32_t instance)
@@ -391,11 +370,38 @@
 {
     LPM_EnableWakeupSource(GPT2_IRQn);
     LPM_EnterLowPowerIdle(LPM_POWER_MODE);
+
+    // Disable us ticker during deep sleep.
+    // Note: Must do this last because SDK_DelayAtLeastUs() uses the us ticker
+    PIT_StopTimer(PIT, kPIT_Chnl_0);
+    PIT_StopTimer(PIT, kPIT_Chnl_2);
 }
 
 void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode)
 {
+    // reenable us ticker
+    // Note: Must do this first because SDK_DelayAtLeastUs() uses the us ticker
+    PIT_StartTimer(PIT, kPIT_Chnl_0);
+    PIT_StartTimer(PIT, kPIT_Chnl_2);
+
     LPM_ExitLowPowerIdle(LPM_POWER_MODE);
     LPM_DisableWakeupSource(GPT2_IRQn);
 }
 
+// Override of MIMXRT SDK delay function.
+// The default delay function used the full CPU clock frequency, so it produced massive overshoots
+// (delaying 30x longer than intended) when the MCU is exiting sleep (and core clock is reduced to 24MHz).
+// This delay function uses the us ticker which always ticks at the same speed even when the CPU clock is reduced.
+void SDK_DelayAtLeastUs(uint32_t delay_us)
+{
+    uint32_t initialTickerValue = us_ticker_read();
+    uint32_t targetTickerValue = delay_us + initialTickerValue;
+
+    // Wait for rollover if needed
+    if(targetTickerValue < initialTickerValue) {
+        while(us_ticker_read() > initialTickerValue) {}
+    }
+
+    // Wait until target time
+    while(us_ticker_read() < targetTickerValue) {}
+}
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mimxrt_clock_adjustment.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mimxrt_clock_adjustment.c
index e5cdcef..de2303d 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mimxrt_clock_adjustment.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/mimxrt_clock_adjustment.c
@@ -56,10 +56,10 @@
         case LPM_PowerModeOverRun:
             CLOCK_SET_DIV(kCLOCK_SemcDiv, BOARD_CLOCKOVERDRIVE_AHB_CLK_ROOT / BOARD_CLOCKOVERDRIVE_SEMC_CLK_ROOT - 1); // Deduce SEMC divider from clock_config.h defines
             /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */
-            CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT / BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider
+            CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_XTAL0_CLK_HZ / BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider
             CLOCK_SET_DIV(kCLOCK_IpgDiv, BOARD_CLOCKOVERDRIVE_AHB_CLK_ROOT / BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT - 1);
             CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
-            CLOCK_SET_MUX(kCLOCK_PerclkMux, 0);    // PERCLK mux to IPG CLK
+            CLOCK_SET_MUX(kCLOCK_PerclkMux, 1); // PERCLK mux to OSC CLK
             CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL
             CLOCK_SET_MUX(kCLOCK_PeriphMux, 0);    // PERIPH_CLK mux to PRE_PERIPH_CLK
 
@@ -68,10 +68,10 @@
         case LPM_PowerModeFullRun:
             CLOCK_SET_DIV(kCLOCK_SemcDiv, BOARD_CLOCKFULLSPEED_AHB_CLK_ROOT / BOARD_CLOCKFULLSPEED_SEMC_CLK_ROOT - 1); // Deduce SEMC divider from clock_config.h defines
             /* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */
-            CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT / BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider
+            CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_XTAL0_CLK_HZ / BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider
             CLOCK_SET_DIV(kCLOCK_IpgDiv, BOARD_CLOCKFULLSPEED_AHB_CLK_ROOT / BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT - 1);
             CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
-            CLOCK_SET_MUX(kCLOCK_PerclkMux, 0);    // PERCLK mux to IPG CLK
+            CLOCK_SET_MUX(kCLOCK_PerclkMux, 1); // PERCLK mux to OSC CLK
             CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL
             CLOCK_SET_MUX(kCLOCK_PeriphMux, 0);    // PERIPH_CLK mux to PRE_PERIPH_CLK
 
@@ -86,10 +86,10 @@
             CLOCK_SET_MUX(kCLOCK_SemcMux, 0); // SEMC mux to PERIPH_CLK
             CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre
             /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */
-            CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_CLOCKLOWPOWER_IPG_CLK_ROOT / BOARD_CLOCKLOWPOWER_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider
+            CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_XTAL0_CLK_HZ / BOARD_CLOCKLOWPOWER_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider
             CLOCK_SET_DIV(kCLOCK_IpgDiv, BOARD_CLOCKLOWPOWER_AHB_CLK_ROOT / BOARD_CLOCKLOWPOWER_IPG_CLK_ROOT - 1);
             CLOCK_SET_DIV(kCLOCK_AhbDiv, 0);
-            CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK
+            CLOCK_SET_MUX(kCLOCK_PerclkMux, 1); // PERCLK mux to OSC CLK
             break;
         default:
             break;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/serial_api.c
index 5caa8c0..f593af8 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/serial_api.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/serial_api.c
@@ -39,7 +39,6 @@
 int stdio_uart_inited = 0;
 serial_t stdio_uart;
 
-extern void serial_setup_clock(void);
 extern uint32_t serial_get_clock(void);
 
 void serial_init(serial_t *obj, PinName tx, PinName rx)
@@ -49,8 +48,6 @@
     obj->index = pinmap_merge(uart_tx, uart_rx);
     MBED_ASSERT((int)obj->index != NC);
 
-    serial_setup_clock();
-
     lpuart_config_t config;
     LPUART_GetDefaultConfig(&config);
     config.baudRate_Bps = 9600;
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/sleep.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/sleep.c
index 44e1ede..33f1443 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/sleep.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/sleep.c
@@ -17,6 +17,10 @@
 #include "sleep_api.h"
 #include "cmsis.h"
 #include "fsl_clock.h"
+#include "lp_ticker_api.h"
+#include "stdio.h"
+#include "inttypes.h"
+#include "fsl_gpt.h"
 
 extern void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode);
 extern void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode);
diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/us_ticker.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/us_ticker.c
index 57897e9..912f7e5 100644
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/us_ticker.c
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/us_ticker.c
@@ -31,7 +31,6 @@
 
 static bool us_ticker_inited = false;
 
-extern void us_ticker_setup_clock();
 extern uint32_t us_ticker_get_clock();
 
 static void pit_isr(void)
@@ -52,8 +51,6 @@
     /* Common for ticker/timer. */
     uint32_t busClock;
 
-    us_ticker_setup_clock();
-
     busClock = us_ticker_get_clock();
 
     /* Let the timer to count if re-init. */
diff --git a/tools/cmake/upload_methods/UploadMethodJLINK.cmake b/tools/cmake/upload_methods/UploadMethodJLINK.cmake
index 4b339f0..0e2d4ea 100644
--- a/tools/cmake/upload_methods/UploadMethodJLINK.cmake
+++ b/tools/cmake/upload_methods/UploadMethodJLINK.cmake
@@ -54,6 +54,7 @@
 	file(GENERATE OUTPUT ${COMMAND_FILE_PATH} CONTENT
 "loadfile ${HEX_FILE}
 r
+go
 exit
 ")
 	add_custom_target(flash-${TARGET_NAME}