diff --git a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_emac.cpp b/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_emac.cpp deleted file mode 100644 index 9355041..0000000 --- a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_emac.cpp +++ /dev/null @@ -1,223 +0,0 @@ -/* Copyright (c) 2018 Renesas Electronics Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "cmsis_os.h" -#include "rtos/ThisThread.h" -#include "netsocket/nsapi_types.h" -#include "events/mbed_shared_queues.h" -#include "rza1_eth.h" -#include "rza1_eth_ext.h" -#include "rza1_emac.h" - -#define RZ_A1_ETH_IF_NAME "en" - -// Weak so a module can override -MBED_WEAK EMAC &EMAC::get_default_instance() { - return RZ_A1_EMAC::get_instance(); -} - -RZ_A1_EMAC &RZ_A1_EMAC::get_instance() { - static RZ_A1_EMAC emac; - return emac; -} - -RZ_A1_EMAC::RZ_A1_EMAC() : hwaddr(), hwaddr_set(false), power_on(false), connect_sts(false), - link_mode_last(NEGO_FAIL), recvThread(osPriorityNormal, 896) -{ -} - -uint32_t RZ_A1_EMAC::get_mtu_size() const -{ - return 1500; -} - -uint32_t RZ_A1_EMAC::get_align_preference() const -{ - return 0; -} - -void RZ_A1_EMAC::get_ifname(char *name, uint8_t size) const -{ - memcpy(name, RZ_A1_ETH_IF_NAME, (size < sizeof(RZ_A1_ETH_IF_NAME)) ? size : sizeof(RZ_A1_ETH_IF_NAME)); -} - -uint8_t RZ_A1_EMAC::get_hwaddr_size() const -{ - return 6; -} - -bool RZ_A1_EMAC::get_hwaddr(uint8_t *addr) const -{ - return false; -} - -void RZ_A1_EMAC::set_hwaddr(const uint8_t *addr) -{ - memcpy(hwaddr, addr, sizeof(hwaddr)); - hwaddr_set = true; - - /* Reconnect */ - if (power_on != false) { - rza1_ethernet_cfg_t ethcfg; - ethcfg.int_priority = 6; - ethcfg.recv_cb = &_recv_callback; - ethcfg.ether_mac = NULL; - ethcfg.ether_mac = (char *)hwaddr; - ethernetext_init(ðcfg); - } -} - -bool RZ_A1_EMAC::link_out(emac_mem_buf_t *buf) -{ - emac_mem_buf_t *copy_buf = buf; - uint32_t retry_cnt; - bool result = false; - int write_size; - int total_write_size = 0; - - while ((copy_buf != NULL) && (memory_manager->get_ptr(copy_buf) != NULL) && (memory_manager->get_len(copy_buf) != 0)) { - for (retry_cnt = 0; retry_cnt < 100; retry_cnt++) { - write_size = rza1_ethernet_write((char *)memory_manager->get_ptr(copy_buf), memory_manager->get_len(copy_buf)); - if (write_size != 0) { - total_write_size += write_size; - break; - } - osDelay(1); - } - copy_buf = memory_manager->get_next(copy_buf); - } - memory_manager->free(buf); - - if (total_write_size > 0) { - if (rza1_ethernet_send() == 1) { - result = true; - } - } - - return result; -} - -bool RZ_A1_EMAC::power_up() -{ - if (power_on != false) { - return true; - } - - rza1_ethernet_cfg_t ethcfg; - ethcfg.int_priority = 6; - ethcfg.recv_cb = &_recv_callback; - ethcfg.ether_mac = NULL; - if (hwaddr_set) { - ethcfg.ether_mac = (char *)hwaddr; - } - ethernetext_init(ðcfg); - - /* task */ - recvThread.start(mbed::callback(this, &RZ_A1_EMAC::recv_task)); - phy_task_handle = mbed::mbed_event_queue()->call_every(200, mbed::callback(this, &RZ_A1_EMAC::phy_task)); - - power_on = true; - return true; -} - -void RZ_A1_EMAC::power_down() -{ - power_on = false; -} - -void RZ_A1_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) -{ - emac_link_input_cb = input_cb; -} - -void RZ_A1_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) -{ - emac_link_state_cb = state_cb; -} - -void RZ_A1_EMAC::add_multicast_group(const uint8_t *addr) -{ - ethernetext_add_multicast_group(addr); -} - -void RZ_A1_EMAC::remove_multicast_group(const uint8_t *addr) -{ - ethernetext_remove_multicast_group(addr); -} - -void RZ_A1_EMAC::set_all_multicast(bool all) -{ - ethernetext_set_all_multicast(all); -} - -void RZ_A1_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) -{ - memory_manager = &mem_mngr; -} - - -void RZ_A1_EMAC::_recv_callback(void) { - get_instance().recv_callback(); -} - -void RZ_A1_EMAC::recv_callback(void) { - recvThread.flags_set(1); -} - -void RZ_A1_EMAC::recv_task(void) { - uint16_t recv_size; - emac_mem_buf_t *buf; - int cnt; - - while (1) { - rtos::ThisThread::flags_wait_all(1); - for (cnt = 0; cnt < 16; cnt++) { - recv_size = rza1_ethernet_receive(); - if (recv_size == 0) { - break; - } - buf = memory_manager->alloc_heap(recv_size, 0); - if (buf != NULL) { - (void)rza1_ethernet_read((char *)memory_manager->get_ptr(buf), memory_manager->get_len(buf)); - emac_link_input_cb(buf); - } - } - } -} - -void RZ_A1_EMAC::phy_task(void) -{ - if (rza1_ethernet_link() == 1) { - int link_mode = ethernetext_chk_link_mode(); - if (link_mode != link_mode_last) { - if (connect_sts != false) { - emac_link_state_cb(false); - } - if (link_mode != NEGO_FAIL) { - ethernetext_set_link_mode(link_mode); - emac_link_state_cb(true); - connect_sts = true; - } - link_mode_last = link_mode; - } - } else { - if (connect_sts != false) { - emac_link_state_cb(false); - link_mode_last = NEGO_FAIL; - connect_sts = false; - } - } -} - diff --git a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_emac.h b/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_emac.h deleted file mode 100644 index 70f5507..0000000 --- a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_emac.h +++ /dev/null @@ -1,169 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef RZ_A1_EMAC_H -#define RZ_A1_EMAC_H - -#include "EMAC.h" -#include "rtos/Thread.h" - -class RZ_A1_EMAC : public EMAC { -public: - RZ_A1_EMAC(); - - static RZ_A1_EMAC &get_instance(); - - /** - * Return maximum transmission unit - * - * @return MTU in bytes - */ - virtual uint32_t get_mtu_size() const; - - /** - * Gets memory buffer alignment preference - * - * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not - * align link out memory buffer chains using the alignment. - * - * @return Memory alignment requirement in bytes - */ - virtual uint32_t get_align_preference() const; - - /** - * Return interface name - * - * @param name Pointer to where the name should be written - * @param size Maximum number of character to copy - */ - virtual void get_ifname(char *name, uint8_t size) const; - - /** - * Returns size of the underlying interface HW address size. - * - * @return HW address size in bytes - */ - virtual uint8_t get_hwaddr_size() const; - - /** - * Return interface-supplied HW address - * - * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size - * - * HW address need not be provided if this interface does not have its own HW - * address configuration; stack will choose address from central system - * configuration if the function returns false and does not write to addr. - * - * @param addr HW address for underlying interface - * @return true if HW address is available - */ - virtual bool get_hwaddr(uint8_t *addr) const; - - /** - * Set HW address for interface - * - * Provided address has to be of correct size, see @a get_hwaddr_size - * - * Called to set the MAC address to actually use - if @a get_hwaddr is provided - * the stack would normally use that, but it could be overridden, eg for test - * purposes. - * - * @param addr Address to be set - */ - virtual void set_hwaddr(const uint8_t *addr); - - /** - * Sends the packet over the link - * - * That can not be called from an interrupt context. - * - * @param buf Packet to be send - * @return True if the packet was send successfully, False otherwise - */ - virtual bool link_out(emac_mem_buf_t *buf); - - /** - * Initializes the HW - * - * @return True on success, False in case of an error. - */ - virtual bool power_up(); - - /** - * Deinitializes the HW - * - */ - virtual void power_down(); - - /** - * Sets a callback that needs to be called for packets received for that interface - * - * @param input_cb Function to be register as a callback - */ - virtual void set_link_input_cb(emac_link_input_cb_t input_cb); - - /** - * Sets a callback that needs to be called on link status changes for given interface - * - * @param state_cb Function to be register as a callback - */ - virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); - - /** Add device to a multicast group - * - * @param address A multicast group hardware address - */ - virtual void add_multicast_group(const uint8_t *address); - - /** Remove device from a multicast group - * - * @param address A multicast group hardware address - */ - virtual void remove_multicast_group(const uint8_t *address); - - /** Request reception of all multicast packets - * - * @param all True to receive all multicasts - * False to receive only multicasts addressed to specified groups - */ - virtual void set_all_multicast(bool all); - - /** Sets memory manager that is used to handle memory buffers - * - * @param mem_mngr Pointer to memory manager - */ - virtual void set_memory_manager(EMACMemoryManager &mem_mngr); - -private: - EMACMemoryManager *memory_manager; /**< Memory manager */ - uint8_t hwaddr[6]; - bool hwaddr_set; - bool power_on; - emac_link_input_cb_t emac_link_input_cb; /**< Callback for incoming data */ - emac_link_state_change_cb_t emac_link_state_cb; /**< Link state change callback */ - bool connect_sts; - int link_mode_last; - rtos::Thread recvThread; - int phy_task_handle; /**< Handle for phy task event */ - - static void _recv_callback(void); - void recv_callback(void); - void recv_task(void); - void phy_task(void); - -}; - -#endif /* RZ_A1_EMAC_H */ diff --git a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth.c b/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth.c deleted file mode 100644 index 3777327..0000000 --- a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth.c +++ /dev/null @@ -1,793 +0,0 @@ -/* Copyright (c) 2020 Renesas Electronics Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "rza1_eth.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" -#include "mbed_error.h" -#include "iodefine.h" -#include "rza1_eth_ext.h" - -#if DEVICE_ETHERNET - -/* Descriptor info */ -#define NUM_OF_TX_DESCRIPTOR (16) -#define NUM_OF_RX_DESCRIPTOR (16) -#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */ -#define MAX_SEND_SIZE (1514) -/* Ethernet Descriptor Value Define */ -#define TD0_TFP_TOP_BOTTOM (0x30000000) -#define TD0_TACT (0x80000000) -#define TD0_TDLE (0x40000000) -#define RD0_RACT (0x80000000) -#define RD0_RDLE (0x40000000) -#define RD0_RFE (0x08000000) -#define RD0_RCSE (0x04000000) -#define RD0_RFS (0x03FF0000) -#define RD0_RCS (0x0000FFFF) -#define RD0_RFS_RFOF (0x02000000) -#define RD0_RFS_RUAF (0x00400000) -#define RD0_RFS_RRF (0x00100000) -#define RD0_RFS_RTLF (0x00080000) -#define RD0_RFS_RTSF (0x00040000) -#define RD0_RFS_PRE (0x00020000) -#define RD0_RFS_CERF (0x00010000) -#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \ - RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF) -#define RD1_RDL_MSK (0x0000FFFF) -/* PHY Register */ -#define BASIC_MODE_CONTROL_REG (0) -#define BASIC_MODE_STATUS_REG (1) -#define PHY_IDENTIFIER1_REG (2) -#define PHY_IDENTIFIER2_REG (3) -#define PHY_SP_CTL_STS_REG (31) -/* MII management interface access */ -#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */ -#define PHY_ST (1) -#define PHY_WRITE (1) -#define PHY_READ (2) -#define MDC_WAIT (6) /* 400ns/4 */ -#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */ -#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */ -#define M_PHY_ID (0xFFFFFFF0) -#define PHY_ID_LAN8710A (0x0007C0F0) -/* ETHERPIR0 */ -#define PIR0_MDI (0x00000008) -#define PIR0_MDO (0x00000004) -#define PIR0_MMD (0x00000002) -#define PIR0_MDC (0x00000001) -#define PIR0_MDC_HIGH (0x00000001) -#define PIR0_MDC_LOW (0x00000000) -/* ETHEREDRRR0 */ -#define EDRRR0_RR (0x00000001) -/* ETHEREDTRR0 */ -#define EDTRR0_TR (0x00000003) -/* software wait */ -#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ - -#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ - /* 0x00040000 : Detect frame reception */ - /* 0x00010000 : Receive FIFO overflow */ - /* 0x00000010 : Residual bit frame reception */ - /* 0x00000008 : Long frame reception */ - /* 0x00000004 : Short frame reception */ - /* 0x00000002 : PHY-LSI reception error */ - /* 0x00000001 : Receive frame CRC error */ -#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ - -void rza1_ethernet_address(char *); -void rza1_ethernet_set_link(int, int); - - -/* Send descriptor */ -typedef struct tag_edmac_send_desc { - uint32_t td0; - uint32_t td1; - uint8_t *td2; - uint32_t padding4; -} edmac_send_desc_t; - -/* Receive descriptor */ -typedef struct tag_edmac_recv_desc { - uint32_t rd0; - uint32_t rd1; - uint8_t *rd2; - uint32_t padding4; -} edmac_recv_desc_t; - -/* memory */ -/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */ -/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */ -#if defined(__ICCARM__) -#pragma data_alignment=16 -static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned! - @ ".mirrorram"; -#else -static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + - (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + - (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + - (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] - __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! -#endif -static int32_t rx_read_offset; /* read offset */ -static int32_t tx_wite_offset; /* write offset */ -static uint32_t send_top_index; -static uint32_t recv_top_index; -static int32_t Interrupt_priority; -static edmac_send_desc_t *p_eth_desc_dsend = NULL; -static edmac_recv_desc_t *p_eth_desc_drecv = NULL; -static edmac_recv_desc_t *p_recv_end_desc = NULL; -static ethernetext_cb_fnc *p_recv_cb_fnc = NULL; -static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */ -static uint32_t phy_id = 0; -static uint32_t start_stop = 1; /* 0:stop 1:start */ -static uint32_t tsu_ten_tmp = 0; - -volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = - /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ - ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; - /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ - -/* function */ -static void lan_reg_reset(void); -static void lan_desc_create(void); -static void lan_reg_set(int32_t link); -static uint16_t phy_reg_read(uint16_t reg_addr); -static void phy_reg_write(uint16_t reg_addr, uint16_t data); -static void mii_preamble(void); -static void mii_cmd(uint16_t reg_addr, uint32_t option); -static void mii_reg_read(uint16_t *data); -static void mii_reg_write(uint16_t data); -static void mii_z(void); -static void mii_write_1(void); -static void mii_write_0(void); -static void set_ether_pir(uint32_t set_data); -static void wait_100us(int32_t wait_cnt); - - -int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) { - int32_t i; - uint16_t val; - - CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ - -#if defined(TARGET_RZ_A1H) - /* P4_2(PHY Reset) */ - GPIOP4 &= ~0x0004; /* Outputs low level */ - GPIOPMC4 &= ~0x0004; /* Port mode */ - GPIOPM4 &= ~0x0004; /* Output mode */ - - /* GPIO P1 P1_14(ET_COL) */ - GPIOPMC1 |= 0x4000; - GPIOPFCAE1 &= ~0x4000; - GPIOPFCE1 |= 0x4000; - GPIOPFC1 |= 0x4000; - - /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ - GPIOPMC3 |= 0x0079; - GPIOPFCAE3 &= ~0x0079; - GPIOPFCE3 &= ~0x0079; - GPIOPFC3 |= 0x0079; - GPIOPIPC3 |= 0x0079; - - /* P5_9(ET_MDC) */ - GPIOPMC5 |= 0x0200; - GPIOPFCAE5 &= ~0x0200; - GPIOPFCE5 &= ~0x0200; - GPIOPFC5 |= 0x0200; - GPIOPIPC5 |= 0x0200; - - /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */ - /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */ - GPIOPMC10 |= 0x0FFE; - GPIOPFCAE10 &= ~0x0FFE; - GPIOPFCE10 |= 0x0FFE; - GPIOPFC10 |= 0x0FFE; - GPIOPIPC10 |= 0x0FFE; - - /* Resets the E-MAC,E-DMAC */ - lan_reg_reset(); - - /* PHY Reset */ - GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */ - wait_100us(250); /* 25msec */ - GPIOP4 |= 0x0004; /* P4_2 Outputs high level */ - wait_100us(100); /* 10msec */ -#else -#error "There is no initialization processing." -#endif - - /* Resets the PHY-LSI */ - phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); - for (i = 10000; i > 0; i--) { - val = phy_reg_read(BASIC_MODE_CONTROL_REG); - if (((uint32_t)val & 0x8000uL) == 0) { - break; /* Reset complete */ - } - } - - phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) - | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); - - Interrupt_priority = p_ethcfg->int_priority; - p_recv_cb_fnc = p_ethcfg->recv_cb; - start_stop = 1; - - if (p_ethcfg->ether_mac != NULL) { - (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr)); - } else { - rza1_ethernet_address(mac_addr); /* Get MAC Address */ - } - - return 0; -} - -void ethernetext_start_stop(int32_t mode) { - if (mode == 1) { - /* start */ - ETHEREDTRR0 |= EDTRR0_TR; - ETHEREDRRR0 |= EDRRR0_RR; - start_stop = 1; - } else { - /* stop */ - ETHEREDTRR0 &= ~EDTRR0_TR; - ETHEREDRRR0 &= ~EDRRR0_RR; - start_stop = 0; - } -} - -int ethernetext_chk_link_mode(void) { - int32_t link; - uint16_t data; - - if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) { - data = phy_reg_read(PHY_SP_CTL_STS_REG); - switch (((uint32_t)data >> 2) & 0x00000007) { - case 0x0001: - link = HALF_10M; - break; - case 0x0005: - link = FULL_10M; - break; - case 0x0002: - link = HALF_TX; - break; - case 0x0006: - link = FULL_TX; - break; - default: - link = NEGO_FAIL; - break; - } - } else { - link = NEGO_FAIL; - } - - return link; -} - -void ethernetext_set_link_mode(int32_t link) { - lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ - lan_desc_create(); /* Initialize of buffer memory */ - lan_reg_set(link); /* E-DMAC, E-MAC initialization */ -} - -void ethernetext_add_multicast_group(const uint8_t *addr) { - uint32_t cnt; - uint32_t tmp_data_h; - uint32_t tmp_data_l; - - if (tsu_ten_tmp == 0xFFFFFFFF) { - ethernetext_set_all_multicast(1); - } else { - tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]); - tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]); - - for (cnt = 0; cnt < 32; cnt++) { - if ((tsu_ten_tmp & (0x80000000 >> cnt)) == 0) { - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = tmp_data_h; - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = tmp_data_l; - if ((ETHERECMR0 & 0x00002000) != 0) { - ETHERTSU_TEN |= (0x80000000 >> cnt); - } - tsu_ten_tmp |= (0x80000000 >> cnt); - break; - } - } - } -} - -void ethernetext_remove_multicast_group(const uint8_t *addr) { - uint32_t cnt; - uint32_t tmp_data_h; - uint32_t tmp_data_l; - - tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]); - tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]); - - for (cnt = 0; cnt< 32; cnt++) { - if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 == tmp_data_h) && - (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 == tmp_data_l)) { - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = 0; - while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { - ; - } - ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = 0; - - ETHERTSU_TEN &= ~(0x80000000 >> cnt); - tsu_ten_tmp &= ~(0x80000000 >> cnt); - break; - } - } -} - -void ethernetext_set_all_multicast(int all) { - if (all != 0) { - ETHERECMR0 &= ~(0x00002000); - ETHERTSU_TEN = 0x00000000; - } else { - ETHERECMR0 |= 0x00002000; - ETHERTSU_TEN = tsu_ten_tmp; - } -} - - -int rza1_ethernet_init() { - rza1_ethernet_cfg_t ethcfg; - - ethcfg.int_priority = 5; - ethcfg.recv_cb = NULL; - ethcfg.ether_mac = NULL; - ethernetext_init(ðcfg); - rza1_ethernet_set_link(-1, 0); /* Auto-Negotiation */ - - return 0; -} - -void rza1_ethernet_free() { - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ -} - -int rza1_ethernet_write(const char *data, int slen) { - edmac_send_desc_t *p_send_desc; - int32_t copy_size; - - if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) - || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { - copy_size = 0; - } else { - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - if ((p_send_desc->td0 & TD0_TACT) != 0) { - copy_size = 0; - } else { - copy_size = MAX_SEND_SIZE - tx_wite_offset; - if (copy_size > slen) { - copy_size = slen; - } - (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size); - tx_wite_offset += copy_size; - } - } - - return copy_size; -} - -int rza1_ethernet_send() { - edmac_send_desc_t *p_send_desc; - int32_t ret; - - if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) { - ret = 0; - } else { - /* Transfer 1 frame */ - p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ - - /* Sets the frame length */ - p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16); - tx_wite_offset = 0; - - /* Sets the transmit descriptor to transmit again */ - p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM); - p_send_desc->td0 |= TD0_TACT; - if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) { - ETHEREDTRR0 |= EDTRR0_TR; - } - - /* Update the current descriptor */ - send_top_index++; - if (send_top_index >= NUM_OF_TX_DESCRIPTOR) { - send_top_index = 0; - } - ret = 1; - } - - return ret; -} - -int rza1_ethernet_receive() { - edmac_recv_desc_t *p_recv_desc; - int32_t receive_size = 0; - - if (p_eth_desc_drecv != NULL) { - if (p_recv_end_desc != NULL) { - /* Sets the receive descriptor to receive again */ - p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_end_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - p_recv_end_desc = NULL; - } - - p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */ - if ((p_recv_desc->rd0 & RD0_RACT) == 0) { - /* Receives 1 frame */ - if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) { - /* Receive frame error */ - /* Sets the receive descriptor to receive again */ - p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE); - p_recv_desc->rd0 |= RD0_RACT; - if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { - ETHEREDRRR0 |= EDRRR0_RR; - } - } else { - /* Copies the received frame */ - rx_read_offset = 0; - p_recv_end_desc = p_recv_desc; - receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */ - } - - /* Update the current descriptor */ - recv_top_index++; - if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) { - recv_top_index = 0; - } - } - } - - return receive_size; -} - -int rza1_ethernet_read(char *data, int dlen) { - edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ - int32_t copy_size; - - if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) { - copy_size = 0; - } else { - copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset; - if (copy_size > dlen) { - copy_size = dlen; - } - (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size); - rx_read_offset += copy_size; - } - - return copy_size; -} - -void rza1_ethernet_address(char *mac) { - if (mac != NULL) { - mbed_mac_address(mac); /* Get MAC Address */ - } -} - -int rza1_ethernet_link(void) { - int32_t ret; - uint16_t data; - - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) { - ret = 1; - } else { - ret = 0; - } - - return ret; -} - -void rza1_ethernet_set_link(int speed, int duplex) { - uint16_t data; - int32_t i; - int32_t link; - - if ((speed < 0) || (speed > 1)) { - data = 0x1000; /* Auto-Negotiation Enable */ - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - for (i = 0; i < 1000; i++) { - data = phy_reg_read(BASIC_MODE_STATUS_REG); - if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) { - break; - } - wait_100us(10); - } - } else { - data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8)); - phy_reg_write(BASIC_MODE_CONTROL_REG, data); - wait_100us(1); - } - - link = ethernetext_chk_link_mode(); - ethernetext_set_link_mode(link); -} - -void INT_Ether(void) { - uint32_t stat_edmac; - uint32_t stat_etherc; - - /* Clear the interrupt request flag */ - stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */ - ETHEREESR0 = stat_edmac; - /* Reception-related */ - if (stat_edmac & EDMAC_EESIPR_INI_RECV) { - if (p_recv_cb_fnc != NULL) { - p_recv_cb_fnc(); - } - } - /* E-MAC-related */ - if (stat_edmac & EDMAC_EESIPR_INI_EtherC) { - /* Clear the interrupt request flag */ - stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */ - ETHERECSR0 = stat_etherc; - } -} - -static void lan_reg_reset(void) { - volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ - - ETHERARSTR |= 0x00000001; /* ETHER software reset */ - while (j--) { - /* Do Nothing */ - } - - ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */ - ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */ - - /* Check clear software reset */ - while ((ETHEREDMR0 & 0x00000003) != 0) { - /* Do Nothing */ - } -} - -static void lan_desc_create(void) { - int32_t i; - uint8_t *p_memory_top; - - (void)memset((void *)rza1_ethernet_nc_memory, 0, sizeof(rza1_ethernet_nc_memory)); - p_memory_top = rza1_ethernet_nc_memory; - - /* Descriptor area configuration */ - p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR); - p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top; - p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR); - - /* Transmit descriptor */ - for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) { - p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */ - p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */ - } - p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */ - - /* Receive descriptor */ - for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) { - p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */ - p_memory_top += SIZE_OF_BUFFER; - p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */ - p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */ - } - p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */ - - /* Initialize descriptor management information */ - send_top_index = 0; - recv_top_index = 0; - rx_read_offset = 0; - tx_wite_offset = 0; - p_recv_end_desc = NULL; -} - -static void lan_reg_set(int32_t link) { - /* MAC address setting */ - ETHERMAHR0 = ((uint8_t)mac_addr[0] << 24) - | ((uint8_t)mac_addr[1] << 16) - | ((uint8_t)mac_addr[2] << 8) - | (uint8_t)mac_addr[3]; - ETHERMALR0 = ((uint8_t)mac_addr[4] << 8) - | (uint8_t)mac_addr[5]; - - /* E-DMAC */ - ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0]; - ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0]; - ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1]; - ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1]; - ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */ - ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */ - ETHEREDMR0 |= 0x00000040; /* Little endian */ - ETHERTRSCER0 &= ~0x0003009F; /* All clear */ - ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */ - ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */ - ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */ - ETHERFCFTR0 &= ~0x001F00FF; - ETHERFCFTR0 |= 0x00070007; - ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */ - - /* E-MAC */ - ETHERECMR0 &= ~0x04BF2063; /* All clear */ - ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */ - ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */ - ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */ - ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */ - ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */ - if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) { - ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */ - } else { - ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */ - } - ETHERECMR0 |= 0x00002000; /* MCT = 1 */ - - /* Interrupt-related */ - if (p_recv_cb_fnc != NULL) { - ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */ - ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */ - ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */ - ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ - InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ - GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ - GIC_SetConfiguration(ETHERI_IRQn, 1); - GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ - } - - ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */ - - /* Enable transmission/reception */ - if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) { - ETHEREDRRR0 |= 0x00000001; /* RR */ - } -} - -static uint16_t phy_reg_read(uint16_t reg_addr) { - uint16_t data; - - mii_preamble(); - mii_cmd(reg_addr, PHY_READ); - mii_z(); - mii_reg_read(&data); - mii_z(); - - return data; -} - -static void phy_reg_write(uint16_t reg_addr, uint16_t data) { - mii_preamble(); - mii_cmd(reg_addr, PHY_WRITE); - mii_write_1(); - mii_write_0(); - mii_reg_write(data); - mii_z(); -} - -static void mii_preamble(void) { - int32_t i = 32; - - for (i = 32; i > 0; i--) { - /* 1 is output via the MII (Media Independent Interface) block. */ - mii_write_1(); - } -} - -static void mii_cmd(uint16_t reg_addr, uint32_t option) { - int32_t i; - uint16_t data = 0; - - data |= (PHY_ST << 14); /* ST code */ - data |= (option << 12); /* OP code */ - data |= (PHY_ADDR << 7); /* PHY Address */ - data |= (uint16_t)(reg_addr << 2); /* Reg Address */ - for (i = 14; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_reg_read(uint16_t *data) { - int32_t i; - uint16_t reg_data = 0; - - /* Data are read in one bit at a time */ - for (i = 16; i > 0; i--) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - reg_data <<= 1; - reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */ - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); - } - *data = reg_data; -} - -static void mii_reg_write(uint16_t data) { - int32_t i; - - /* Data are written one bit at a time */ - for (i = 16; i > 0; i--) { - if ((data & 0x8000) == 0) { - mii_write_0(); - } else { - mii_write_1(); - } - data <<= 1; - } -} - -static void mii_z(void) { - set_ether_pir(PIR0_MDC_LOW); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_HIGH); - set_ether_pir(PIR0_MDC_LOW); -} - -static void mii_write_1(void) { - set_ether_pir(PIR0_MDO | PIR0_MMD); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MDO | PIR0_MMD); -} - -static void mii_write_0(void) { - set_ether_pir(PIR0_MMD); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD | PIR0_MDC); - set_ether_pir(PIR0_MMD); -} - -static void set_ether_pir(uint32_t set_data) { - int32_t i; - - for (i = MDC_WAIT; i > 0; i--) { - ETHERPIR0 = set_data; - } -} - -static void wait_100us(int32_t wait_cnt) { - volatile int32_t j = LOOP_100us * wait_cnt; - - while (--j) { - /* Do Nothing */ - } -} -#endif /* DEVICE_ETHERNET */ diff --git a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth.h b/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth.h deleted file mode 100644 index 3553879..0000000 --- a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth.h +++ /dev/null @@ -1,65 +0,0 @@ -/* Copyright (c) 2020 Renesas Electronics Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_ETHERNET_API_H -#define MBED_ETHERNET_API_H - -#include "device.h" -#include "platform/mbed_toolchain.h" - -#if DEVICE_ETHERNET - -#ifdef __cplusplus -extern "C" { -#endif - -// Connection constants -int rza1_ethernet_init(void); -void rza1_ethernet_free(void); - -// write size bytes from data to ethernet buffer -// return num bytes written -// or -1 if size is too big -int rza1_ethernet_write(const char *data, int size); - -// send ethernet write buffer, returning the packet size sent -int rza1_ethernet_send(void); - -// receive from ethernet buffer, returning packet size, or 0 if no packet -int rza1_ethernet_receive(void); - -// read size bytes in to data, return actual num bytes read (0..size) -// if data == NULL, throw the bytes away -int rza1_ethernet_read(char *data, int size); - -// get the ethernet address -void rza1_ethernet_address(char *mac); - -// see if the link is up -int rza1_ethernet_link(void); - -// force link settings -void rza1_ethernet_set_link(int speed, int duplex); - -#ifdef __cplusplus -} -#endif - -#endif - -#endif - - -/** @}*/ diff --git a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth_ext.h b/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth_ext.h deleted file mode 100644 index e61a15f..0000000 --- a/connectivity/drivers/emac/TARGET_RZ_A1_EMAC/rza1_eth_ext.h +++ /dev/null @@ -1,49 +0,0 @@ -/* Copyright (c) 2020 Renesas Electronics Corporation. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef ETHERNETEXT_H -#define ETHERNETEXT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* PHY link mode */ -#define NEGO_FAIL (0) -#define HALF_10M (1) -#define FULL_10M (2) -#define HALF_TX (3) -#define FULL_TX (4) - -typedef void (ethernetext_cb_fnc)(void); - -typedef struct tag_rza1_ethernet_cfg { - int int_priority; - ethernetext_cb_fnc *recv_cb; - char *ether_mac; -} rza1_ethernet_cfg_t; - -extern int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg); -extern void ethernetext_start_stop(int32_t mode); -extern int ethernetext_chk_link_mode(void); -extern void ethernetext_set_link_mode(int32_t link); -extern void ethernetext_add_multicast_group(const uint8_t *addr); -extern void ethernetext_remove_multicast_group(const uint8_t *addr); -extern void ethernetext_set_all_multicast(int all); -#ifdef __cplusplus -} -#endif - -#endif diff --git a/connectivity/libraries/ppp/mbed_lib.json b/connectivity/libraries/ppp/mbed_lib.json index 3ba6d14..90ffce4 100644 --- a/connectivity/libraries/ppp/mbed_lib.json +++ b/connectivity/libraries/ppp/mbed_lib.json @@ -33,7 +33,10 @@ } }, "target_overrides": { - "RZ_A1_EMAC": { + "RZ_A1XX": { + "thread-stacksize": 896 + }, + "RZ_A2XX": { "thread-stacksize": 896 }, "CY8CPROTO_062_4343W": { diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index 72f14db..c94c420 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -174,7 +174,17 @@ "EFM32GG11_STK3701": { "mem-size": 36560 }, - "RZ_A1_EMAC": { + "RZ_A1XX": { + "tcpip-thread-stacksize": 1328, + "default-thread-stacksize": 640, + "memp-num-tcp-seg": 32, + "tcp-mss": 1440, + "tcp-snd-buf": "(8 * TCP_MSS)", + "tcp-wnd": "(TCP_MSS * 8)", + "pbuf-pool-size": 16, + "mem-size": 51200 + }, + "RZ_A2XX": { "tcpip-thread-stacksize": 1328, "default-thread-stacksize": 640, "memp-num-tcp-seg": 32, diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.cpp b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.cpp new file mode 100644 index 0000000..6484f53 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.cpp @@ -0,0 +1,223 @@ +/* Copyright (c) 2018 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "cmsis_os.h" +#include "rtos/ThisThread.h" +#include "netsocket/nsapi_types.h" +#include "mbed_shared_queues.h" +#include "rza1_eth.h" +#include "rza1_eth_ext.h" +#include "rza1_emac.h" + +#define RZ_A1_ETH_IF_NAME "en" + +// Weak so a module can override +MBED_WEAK EMAC &EMAC::get_default_instance() { + return RZ_A1_EMAC::get_instance(); +} + +RZ_A1_EMAC &RZ_A1_EMAC::get_instance() { + static RZ_A1_EMAC emac; + return emac; +} + +RZ_A1_EMAC::RZ_A1_EMAC() : hwaddr(), hwaddr_set(false), power_on(false), connect_sts(false), + link_mode_last(NEGO_FAIL), recvThread(osPriorityNormal, 896) +{ +} + +uint32_t RZ_A1_EMAC::get_mtu_size() const +{ + return 1500; +} + +uint32_t RZ_A1_EMAC::get_align_preference() const +{ + return 0; +} + +void RZ_A1_EMAC::get_ifname(char *name, uint8_t size) const +{ + memcpy(name, RZ_A1_ETH_IF_NAME, (size < sizeof(RZ_A1_ETH_IF_NAME)) ? size : sizeof(RZ_A1_ETH_IF_NAME)); +} + +uint8_t RZ_A1_EMAC::get_hwaddr_size() const +{ + return 6; +} + +bool RZ_A1_EMAC::get_hwaddr(uint8_t *addr) const +{ + return false; +} + +void RZ_A1_EMAC::set_hwaddr(const uint8_t *addr) +{ + memcpy(hwaddr, addr, sizeof(hwaddr)); + hwaddr_set = true; + + /* Reconnect */ + if (power_on != false) { + rza1_ethernet_cfg_t ethcfg; + ethcfg.int_priority = 6; + ethcfg.recv_cb = &_recv_callback; + ethcfg.ether_mac = NULL; + ethcfg.ether_mac = (char *)hwaddr; + ethernetext_init(ðcfg); + } +} + +bool RZ_A1_EMAC::link_out(emac_mem_buf_t *buf) +{ + emac_mem_buf_t *copy_buf = buf; + uint32_t retry_cnt; + bool result = false; + int write_size; + int total_write_size = 0; + + while ((copy_buf != NULL) && (memory_manager->get_ptr(copy_buf) != NULL) && (memory_manager->get_len(copy_buf) != 0)) { + for (retry_cnt = 0; retry_cnt < 100; retry_cnt++) { + write_size = rza1_ethernet_write((char *)memory_manager->get_ptr(copy_buf), memory_manager->get_len(copy_buf)); + if (write_size != 0) { + total_write_size += write_size; + break; + } + osDelay(1); + } + copy_buf = memory_manager->get_next(copy_buf); + } + memory_manager->free(buf); + + if (total_write_size > 0) { + if (rza1_ethernet_send() == 1) { + result = true; + } + } + + return result; +} + +bool RZ_A1_EMAC::power_up() +{ + if (power_on != false) { + return true; + } + + rza1_ethernet_cfg_t ethcfg; + ethcfg.int_priority = 6; + ethcfg.recv_cb = &_recv_callback; + ethcfg.ether_mac = NULL; + if (hwaddr_set) { + ethcfg.ether_mac = (char *)hwaddr; + } + ethernetext_init(ðcfg); + + /* task */ + recvThread.start(mbed::callback(this, &RZ_A1_EMAC::recv_task)); + phy_task_handle = mbed::mbed_event_queue()->call_every(200, mbed::callback(this, &RZ_A1_EMAC::phy_task)); + + power_on = true; + return true; +} + +void RZ_A1_EMAC::power_down() +{ + power_on = false; +} + +void RZ_A1_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + emac_link_input_cb = input_cb; +} + +void RZ_A1_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + emac_link_state_cb = state_cb; +} + +void RZ_A1_EMAC::add_multicast_group(const uint8_t *addr) +{ + ethernetext_add_multicast_group(addr); +} + +void RZ_A1_EMAC::remove_multicast_group(const uint8_t *addr) +{ + ethernetext_remove_multicast_group(addr); +} + +void RZ_A1_EMAC::set_all_multicast(bool all) +{ + ethernetext_set_all_multicast(all); +} + +void RZ_A1_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + memory_manager = &mem_mngr; +} + + +void RZ_A1_EMAC::_recv_callback(void) { + get_instance().recv_callback(); +} + +void RZ_A1_EMAC::recv_callback(void) { + recvThread.flags_set(1); +} + +void RZ_A1_EMAC::recv_task(void) { + uint16_t recv_size; + emac_mem_buf_t *buf; + int cnt; + + while (1) { + rtos::ThisThread::flags_wait_all(1); + for (cnt = 0; cnt < 16; cnt++) { + recv_size = rza1_ethernet_receive(); + if (recv_size == 0) { + break; + } + buf = memory_manager->alloc_heap(recv_size, 0); + if (buf != NULL) { + (void)rza1_ethernet_read((char *)memory_manager->get_ptr(buf), memory_manager->get_len(buf)); + emac_link_input_cb(buf); + } + } + } +} + +void RZ_A1_EMAC::phy_task(void) +{ + if (rza1_ethernet_link() == 1) { + int link_mode = ethernetext_chk_link_mode(); + if (link_mode != link_mode_last) { + if (connect_sts != false) { + emac_link_state_cb(false); + } + if (link_mode != NEGO_FAIL) { + ethernetext_set_link_mode(link_mode); + emac_link_state_cb(true); + connect_sts = true; + } + link_mode_last = link_mode; + } + } else { + if (connect_sts != false) { + emac_link_state_cb(false); + link_mode_last = NEGO_FAIL; + connect_sts = false; + } + } +} + diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.h new file mode 100644 index 0000000..70f5507 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_emac.h @@ -0,0 +1,169 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef RZ_A1_EMAC_H +#define RZ_A1_EMAC_H + +#include "EMAC.h" +#include "rtos/Thread.h" + +class RZ_A1_EMAC : public EMAC { +public: + RZ_A1_EMAC(); + + static RZ_A1_EMAC &get_instance(); + + /** + * Return maximum transmission unit + * + * @return MTU in bytes + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets memory buffer alignment preference + * + * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not + * align link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes + */ + virtual uint32_t get_align_preference() const; + + /** + * Return interface name + * + * @param name Pointer to where the name should be written + * @param size Maximum number of character to copy + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Return interface-supplied HW address + * + * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size + * + * HW address need not be provided if this interface does not have its own HW + * address configuration; stack will choose address from central system + * configuration if the function returns false and does not write to addr. + * + * @param addr HW address for underlying interface + * @return true if HW address is available + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for interface + * + * Provided address has to be of correct size, see @a get_hwaddr_size + * + * Called to set the MAC address to actually use - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden, eg for test + * purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success, False in case of an error. + */ + virtual bool power_up(); + + /** + * Deinitializes the HW + * + */ + virtual void power_down(); + + /** + * Sets a callback that needs to be called for packets received for that interface + * + * @param input_cb Function to be register as a callback + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that needs to be called on link status changes for given interface + * + * @param state_cb Function to be register as a callback + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Add device to a multicast group + * + * @param address A multicast group hardware address + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Remove device from a multicast group + * + * @param address A multicast group hardware address + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Request reception of all multicast packets + * + * @param all True to receive all multicasts + * False to receive only multicasts addressed to specified groups + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager that is used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + +private: + EMACMemoryManager *memory_manager; /**< Memory manager */ + uint8_t hwaddr[6]; + bool hwaddr_set; + bool power_on; + emac_link_input_cb_t emac_link_input_cb; /**< Callback for incoming data */ + emac_link_state_change_cb_t emac_link_state_cb; /**< Link state change callback */ + bool connect_sts; + int link_mode_last; + rtos::Thread recvThread; + int phy_task_handle; /**< Handle for phy task event */ + + static void _recv_callback(void); + void recv_callback(void); + void recv_task(void); + void phy_task(void); + +}; + +#endif /* RZ_A1_EMAC_H */ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.c b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.c new file mode 100644 index 0000000..3777327 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.c @@ -0,0 +1,793 @@ +/* Copyright (c) 2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "rza1_eth.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "mbed_toolchain.h" +#include "mbed_error.h" +#include "iodefine.h" +#include "rza1_eth_ext.h" + +#if DEVICE_ETHERNET + +/* Descriptor info */ +#define NUM_OF_TX_DESCRIPTOR (16) +#define NUM_OF_RX_DESCRIPTOR (16) +#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */ +#define MAX_SEND_SIZE (1514) +/* Ethernet Descriptor Value Define */ +#define TD0_TFP_TOP_BOTTOM (0x30000000) +#define TD0_TACT (0x80000000) +#define TD0_TDLE (0x40000000) +#define RD0_RACT (0x80000000) +#define RD0_RDLE (0x40000000) +#define RD0_RFE (0x08000000) +#define RD0_RCSE (0x04000000) +#define RD0_RFS (0x03FF0000) +#define RD0_RCS (0x0000FFFF) +#define RD0_RFS_RFOF (0x02000000) +#define RD0_RFS_RUAF (0x00400000) +#define RD0_RFS_RRF (0x00100000) +#define RD0_RFS_RTLF (0x00080000) +#define RD0_RFS_RTSF (0x00040000) +#define RD0_RFS_PRE (0x00020000) +#define RD0_RFS_CERF (0x00010000) +#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \ + RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF) +#define RD1_RDL_MSK (0x0000FFFF) +/* PHY Register */ +#define BASIC_MODE_CONTROL_REG (0) +#define BASIC_MODE_STATUS_REG (1) +#define PHY_IDENTIFIER1_REG (2) +#define PHY_IDENTIFIER2_REG (3) +#define PHY_SP_CTL_STS_REG (31) +/* MII management interface access */ +#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */ +#define PHY_ST (1) +#define PHY_WRITE (1) +#define PHY_READ (2) +#define MDC_WAIT (6) /* 400ns/4 */ +#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */ +#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */ +#define M_PHY_ID (0xFFFFFFF0) +#define PHY_ID_LAN8710A (0x0007C0F0) +/* ETHERPIR0 */ +#define PIR0_MDI (0x00000008) +#define PIR0_MDO (0x00000004) +#define PIR0_MMD (0x00000002) +#define PIR0_MDC (0x00000001) +#define PIR0_MDC_HIGH (0x00000001) +#define PIR0_MDC_LOW (0x00000000) +/* ETHEREDRRR0 */ +#define EDRRR0_RR (0x00000001) +/* ETHEREDTRR0 */ +#define EDTRR0_TR (0x00000003) +/* software wait */ +#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */ + +#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */ + /* 0x00040000 : Detect frame reception */ + /* 0x00010000 : Receive FIFO overflow */ + /* 0x00000010 : Residual bit frame reception */ + /* 0x00000008 : Long frame reception */ + /* 0x00000004 : Short frame reception */ + /* 0x00000002 : PHY-LSI reception error */ + /* 0x00000001 : Receive frame CRC error */ +#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */ + +void rza1_ethernet_address(char *); +void rza1_ethernet_set_link(int, int); + + +/* Send descriptor */ +typedef struct tag_edmac_send_desc { + uint32_t td0; + uint32_t td1; + uint8_t *td2; + uint32_t padding4; +} edmac_send_desc_t; + +/* Receive descriptor */ +typedef struct tag_edmac_recv_desc { + uint32_t rd0; + uint32_t rd1; + uint8_t *rd2; + uint32_t padding4; +} edmac_recv_desc_t; + +/* memory */ +/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */ +/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */ +#if defined(__ICCARM__) +#pragma data_alignment=16 +static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + + (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + + (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + + (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned! + @ ".mirrorram"; +#else +static uint8_t rza1_ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) + + (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) + + (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) + + (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] + __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned! +#endif +static int32_t rx_read_offset; /* read offset */ +static int32_t tx_wite_offset; /* write offset */ +static uint32_t send_top_index; +static uint32_t recv_top_index; +static int32_t Interrupt_priority; +static edmac_send_desc_t *p_eth_desc_dsend = NULL; +static edmac_recv_desc_t *p_eth_desc_drecv = NULL; +static edmac_recv_desc_t *p_recv_end_desc = NULL; +static ethernetext_cb_fnc *p_recv_cb_fnc = NULL; +static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */ +static uint32_t phy_id = 0; +static uint32_t start_stop = 1; /* 0:stop 1:start */ +static uint32_t tsu_ten_tmp = 0; + +volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ + +/* function */ +static void lan_reg_reset(void); +static void lan_desc_create(void); +static void lan_reg_set(int32_t link); +static uint16_t phy_reg_read(uint16_t reg_addr); +static void phy_reg_write(uint16_t reg_addr, uint16_t data); +static void mii_preamble(void); +static void mii_cmd(uint16_t reg_addr, uint32_t option); +static void mii_reg_read(uint16_t *data); +static void mii_reg_write(uint16_t data); +static void mii_z(void); +static void mii_write_1(void); +static void mii_write_0(void); +static void set_ether_pir(uint32_t set_data); +static void wait_100us(int32_t wait_cnt); + + +int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg) { + int32_t i; + uint16_t val; + + CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ + +#if defined(TARGET_RZ_A1H) + /* P4_2(PHY Reset) */ + GPIOP4 &= ~0x0004; /* Outputs low level */ + GPIOPMC4 &= ~0x0004; /* Port mode */ + GPIOPM4 &= ~0x0004; /* Output mode */ + + /* GPIO P1 P1_14(ET_COL) */ + GPIOPMC1 |= 0x4000; + GPIOPFCAE1 &= ~0x4000; + GPIOPFCE1 |= 0x4000; + GPIOPFC1 |= 0x4000; + + /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */ + GPIOPMC3 |= 0x0079; + GPIOPFCAE3 &= ~0x0079; + GPIOPFCE3 &= ~0x0079; + GPIOPFC3 |= 0x0079; + GPIOPIPC3 |= 0x0079; + + /* P5_9(ET_MDC) */ + GPIOPMC5 |= 0x0200; + GPIOPFCAE5 &= ~0x0200; + GPIOPFCE5 &= ~0x0200; + GPIOPFC5 |= 0x0200; + GPIOPIPC5 |= 0x0200; + + /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */ + /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */ + GPIOPMC10 |= 0x0FFE; + GPIOPFCAE10 &= ~0x0FFE; + GPIOPFCE10 |= 0x0FFE; + GPIOPFC10 |= 0x0FFE; + GPIOPIPC10 |= 0x0FFE; + + /* Resets the E-MAC,E-DMAC */ + lan_reg_reset(); + + /* PHY Reset */ + GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */ + wait_100us(250); /* 25msec */ + GPIOP4 |= 0x0004; /* P4_2 Outputs high level */ + wait_100us(100); /* 10msec */ +#else +#error "There is no initialization processing." +#endif + + /* Resets the PHY-LSI */ + phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); + for (i = 10000; i > 0; i--) { + val = phy_reg_read(BASIC_MODE_CONTROL_REG); + if (((uint32_t)val & 0x8000uL) == 0) { + break; /* Reset complete */ + } + } + + phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16) + | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG); + + Interrupt_priority = p_ethcfg->int_priority; + p_recv_cb_fnc = p_ethcfg->recv_cb; + start_stop = 1; + + if (p_ethcfg->ether_mac != NULL) { + (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr)); + } else { + rza1_ethernet_address(mac_addr); /* Get MAC Address */ + } + + return 0; +} + +void ethernetext_start_stop(int32_t mode) { + if (mode == 1) { + /* start */ + ETHEREDTRR0 |= EDTRR0_TR; + ETHEREDRRR0 |= EDRRR0_RR; + start_stop = 1; + } else { + /* stop */ + ETHEREDTRR0 &= ~EDTRR0_TR; + ETHEREDRRR0 &= ~EDRRR0_RR; + start_stop = 0; + } +} + +int ethernetext_chk_link_mode(void) { + int32_t link; + uint16_t data; + + if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) { + data = phy_reg_read(PHY_SP_CTL_STS_REG); + switch (((uint32_t)data >> 2) & 0x00000007) { + case 0x0001: + link = HALF_10M; + break; + case 0x0005: + link = FULL_10M; + break; + case 0x0002: + link = HALF_TX; + break; + case 0x0006: + link = FULL_TX; + break; + default: + link = NEGO_FAIL; + break; + } + } else { + link = NEGO_FAIL; + } + + return link; +} + +void ethernetext_set_link_mode(int32_t link) { + lan_reg_reset(); /* Resets the E-MAC,E-DMAC */ + lan_desc_create(); /* Initialize of buffer memory */ + lan_reg_set(link); /* E-DMAC, E-MAC initialization */ +} + +void ethernetext_add_multicast_group(const uint8_t *addr) { + uint32_t cnt; + uint32_t tmp_data_h; + uint32_t tmp_data_l; + + if (tsu_ten_tmp == 0xFFFFFFFF) { + ethernetext_set_all_multicast(1); + } else { + tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]); + tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]); + + for (cnt = 0; cnt < 32; cnt++) { + if ((tsu_ten_tmp & (0x80000000 >> cnt)) == 0) { + while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { + ; + } + ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = tmp_data_h; + while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { + ; + } + ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = tmp_data_l; + if ((ETHERECMR0 & 0x00002000) != 0) { + ETHERTSU_TEN |= (0x80000000 >> cnt); + } + tsu_ten_tmp |= (0x80000000 >> cnt); + break; + } + } + } +} + +void ethernetext_remove_multicast_group(const uint8_t *addr) { + uint32_t cnt; + uint32_t tmp_data_h; + uint32_t tmp_data_l; + + tmp_data_h = ((uint32_t)addr[0] << 24) | ((uint32_t)addr[1] << 16) | ((uint32_t)addr[2] << 8) | ((uint32_t)addr[3]); + tmp_data_l = ((uint32_t)addr[4] << 8) | ((uint32_t)addr[5]); + + for (cnt = 0; cnt< 32; cnt++) { + if ((ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 == tmp_data_h) && + (ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 == tmp_data_l)) { + while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { + ; + } + ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRH0 = 0; + while ((ETHERTSU_ADSBSY & 0x00000001) != 0) { + ; + } + ETHER_FROM_TSU_ADRH0_ARRAY[cnt]->TSU_ADRL0 = 0; + + ETHERTSU_TEN &= ~(0x80000000 >> cnt); + tsu_ten_tmp &= ~(0x80000000 >> cnt); + break; + } + } +} + +void ethernetext_set_all_multicast(int all) { + if (all != 0) { + ETHERECMR0 &= ~(0x00002000); + ETHERTSU_TEN = 0x00000000; + } else { + ETHERECMR0 |= 0x00002000; + ETHERTSU_TEN = tsu_ten_tmp; + } +} + + +int rza1_ethernet_init() { + rza1_ethernet_cfg_t ethcfg; + + ethcfg.int_priority = 5; + ethcfg.recv_cb = NULL; + ethcfg.ether_mac = NULL; + ethernetext_init(ðcfg); + rza1_ethernet_set_link(-1, 0); /* Auto-Negotiation */ + + return 0; +} + +void rza1_ethernet_free() { + ETHERARSTR |= 0x00000001; /* ETHER software reset */ + CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */ +} + +int rza1_ethernet_write(const char *data, int slen) { + edmac_send_desc_t *p_send_desc; + int32_t copy_size; + + if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0) + || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) { + copy_size = 0; + } else { + p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ + if ((p_send_desc->td0 & TD0_TACT) != 0) { + copy_size = 0; + } else { + copy_size = MAX_SEND_SIZE - tx_wite_offset; + if (copy_size > slen) { + copy_size = slen; + } + (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size); + tx_wite_offset += copy_size; + } + } + + return copy_size; +} + +int rza1_ethernet_send() { + edmac_send_desc_t *p_send_desc; + int32_t ret; + + if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) { + ret = 0; + } else { + /* Transfer 1 frame */ + p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */ + + /* Sets the frame length */ + p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16); + tx_wite_offset = 0; + + /* Sets the transmit descriptor to transmit again */ + p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM); + p_send_desc->td0 |= TD0_TACT; + if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) { + ETHEREDTRR0 |= EDTRR0_TR; + } + + /* Update the current descriptor */ + send_top_index++; + if (send_top_index >= NUM_OF_TX_DESCRIPTOR) { + send_top_index = 0; + } + ret = 1; + } + + return ret; +} + +int rza1_ethernet_receive() { + edmac_recv_desc_t *p_recv_desc; + int32_t receive_size = 0; + + if (p_eth_desc_drecv != NULL) { + if (p_recv_end_desc != NULL) { + /* Sets the receive descriptor to receive again */ + p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE); + p_recv_end_desc->rd0 |= RD0_RACT; + if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { + ETHEREDRRR0 |= EDRRR0_RR; + } + p_recv_end_desc = NULL; + } + + p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */ + if ((p_recv_desc->rd0 & RD0_RACT) == 0) { + /* Receives 1 frame */ + if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) { + /* Receive frame error */ + /* Sets the receive descriptor to receive again */ + p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE); + p_recv_desc->rd0 |= RD0_RACT; + if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) { + ETHEREDRRR0 |= EDRRR0_RR; + } + } else { + /* Copies the received frame */ + rx_read_offset = 0; + p_recv_end_desc = p_recv_desc; + receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */ + } + + /* Update the current descriptor */ + recv_top_index++; + if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) { + recv_top_index = 0; + } + } + } + + return receive_size; +} + +int rza1_ethernet_read(char *data, int dlen) { + edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */ + int32_t copy_size; + + if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) { + copy_size = 0; + } else { + copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset; + if (copy_size > dlen) { + copy_size = dlen; + } + (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size); + rx_read_offset += copy_size; + } + + return copy_size; +} + +void rza1_ethernet_address(char *mac) { + if (mac != NULL) { + mbed_mac_address(mac); /* Get MAC Address */ + } +} + +int rza1_ethernet_link(void) { + int32_t ret; + uint16_t data; + + data = phy_reg_read(BASIC_MODE_STATUS_REG); + if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) { + ret = 1; + } else { + ret = 0; + } + + return ret; +} + +void rza1_ethernet_set_link(int speed, int duplex) { + uint16_t data; + int32_t i; + int32_t link; + + if ((speed < 0) || (speed > 1)) { + data = 0x1000; /* Auto-Negotiation Enable */ + phy_reg_write(BASIC_MODE_CONTROL_REG, data); + for (i = 0; i < 1000; i++) { + data = phy_reg_read(BASIC_MODE_STATUS_REG); + if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) { + break; + } + wait_100us(10); + } + } else { + data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8)); + phy_reg_write(BASIC_MODE_CONTROL_REG, data); + wait_100us(1); + } + + link = ethernetext_chk_link_mode(); + ethernetext_set_link_mode(link); +} + +void INT_Ether(void) { + uint32_t stat_edmac; + uint32_t stat_etherc; + + /* Clear the interrupt request flag */ + stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */ + ETHEREESR0 = stat_edmac; + /* Reception-related */ + if (stat_edmac & EDMAC_EESIPR_INI_RECV) { + if (p_recv_cb_fnc != NULL) { + p_recv_cb_fnc(); + } + } + /* E-MAC-related */ + if (stat_edmac & EDMAC_EESIPR_INI_EtherC) { + /* Clear the interrupt request flag */ + stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */ + ETHERECSR0 = stat_etherc; + } +} + +static void lan_reg_reset(void) { + volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */ + + ETHERARSTR |= 0x00000001; /* ETHER software reset */ + while (j--) { + /* Do Nothing */ + } + + ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */ + ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */ + + /* Check clear software reset */ + while ((ETHEREDMR0 & 0x00000003) != 0) { + /* Do Nothing */ + } +} + +static void lan_desc_create(void) { + int32_t i; + uint8_t *p_memory_top; + + (void)memset((void *)rza1_ethernet_nc_memory, 0, sizeof(rza1_ethernet_nc_memory)); + p_memory_top = rza1_ethernet_nc_memory; + + /* Descriptor area configuration */ + p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top; + p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR); + p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top; + p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR); + + /* Transmit descriptor */ + for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) { + p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */ + p_memory_top += SIZE_OF_BUFFER; + p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */ + p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */ + } + p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */ + + /* Receive descriptor */ + for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) { + p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */ + p_memory_top += SIZE_OF_BUFFER; + p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */ + p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */ + } + p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */ + + /* Initialize descriptor management information */ + send_top_index = 0; + recv_top_index = 0; + rx_read_offset = 0; + tx_wite_offset = 0; + p_recv_end_desc = NULL; +} + +static void lan_reg_set(int32_t link) { + /* MAC address setting */ + ETHERMAHR0 = ((uint8_t)mac_addr[0] << 24) + | ((uint8_t)mac_addr[1] << 16) + | ((uint8_t)mac_addr[2] << 8) + | (uint8_t)mac_addr[3]; + ETHERMALR0 = ((uint8_t)mac_addr[4] << 8) + | (uint8_t)mac_addr[5]; + + /* E-DMAC */ + ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0]; + ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0]; + ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0]; + ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0]; + ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1]; + ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1]; + ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */ + ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */ + ETHEREDMR0 |= 0x00000040; /* Little endian */ + ETHERTRSCER0 &= ~0x0003009F; /* All clear */ + ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */ + ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */ + ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */ + ETHERFCFTR0 &= ~0x001F00FF; + ETHERFCFTR0 |= 0x00070007; + ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */ + + /* E-MAC */ + ETHERECMR0 &= ~0x04BF2063; /* All clear */ + ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */ + ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */ + ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */ + ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */ + ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */ + if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) { + ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */ + } else { + ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */ + } + ETHERECMR0 |= 0x00002000; /* MCT = 1 */ + + /* Interrupt-related */ + if (p_recv_cb_fnc != NULL) { + ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */ + ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */ + ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */ + ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */ + InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */ + GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */ + GIC_SetConfiguration(ETHERI_IRQn, 1); + GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */ + } + + ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */ + + /* Enable transmission/reception */ + if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) { + ETHEREDRRR0 |= 0x00000001; /* RR */ + } +} + +static uint16_t phy_reg_read(uint16_t reg_addr) { + uint16_t data; + + mii_preamble(); + mii_cmd(reg_addr, PHY_READ); + mii_z(); + mii_reg_read(&data); + mii_z(); + + return data; +} + +static void phy_reg_write(uint16_t reg_addr, uint16_t data) { + mii_preamble(); + mii_cmd(reg_addr, PHY_WRITE); + mii_write_1(); + mii_write_0(); + mii_reg_write(data); + mii_z(); +} + +static void mii_preamble(void) { + int32_t i = 32; + + for (i = 32; i > 0; i--) { + /* 1 is output via the MII (Media Independent Interface) block. */ + mii_write_1(); + } +} + +static void mii_cmd(uint16_t reg_addr, uint32_t option) { + int32_t i; + uint16_t data = 0; + + data |= (PHY_ST << 14); /* ST code */ + data |= (option << 12); /* OP code */ + data |= (PHY_ADDR << 7); /* PHY Address */ + data |= (uint16_t)(reg_addr << 2); /* Reg Address */ + for (i = 14; i > 0; i--) { + if ((data & 0x8000) == 0) { + mii_write_0(); + } else { + mii_write_1(); + } + data <<= 1; + } +} + +static void mii_reg_read(uint16_t *data) { + int32_t i; + uint16_t reg_data = 0; + + /* Data are read in one bit at a time */ + for (i = 16; i > 0; i--) { + set_ether_pir(PIR0_MDC_LOW); + set_ether_pir(PIR0_MDC_HIGH); + reg_data <<= 1; + reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */ + set_ether_pir(PIR0_MDC_HIGH); + set_ether_pir(PIR0_MDC_LOW); + } + *data = reg_data; +} + +static void mii_reg_write(uint16_t data) { + int32_t i; + + /* Data are written one bit at a time */ + for (i = 16; i > 0; i--) { + if ((data & 0x8000) == 0) { + mii_write_0(); + } else { + mii_write_1(); + } + data <<= 1; + } +} + +static void mii_z(void) { + set_ether_pir(PIR0_MDC_LOW); + set_ether_pir(PIR0_MDC_HIGH); + set_ether_pir(PIR0_MDC_HIGH); + set_ether_pir(PIR0_MDC_LOW); +} + +static void mii_write_1(void) { + set_ether_pir(PIR0_MDO | PIR0_MMD); + set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MDO | PIR0_MMD); +} + +static void mii_write_0(void) { + set_ether_pir(PIR0_MMD); + set_ether_pir(PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MMD | PIR0_MDC); + set_ether_pir(PIR0_MMD); +} + +static void set_ether_pir(uint32_t set_data) { + int32_t i; + + for (i = MDC_WAIT; i > 0; i--) { + ETHERPIR0 = set_data; + } +} + +static void wait_100us(int32_t wait_cnt) { + volatile int32_t j = LOOP_100us * wait_cnt; + + while (--j) { + /* Do Nothing */ + } +} +#endif /* DEVICE_ETHERNET */ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.h new file mode 100644 index 0000000..3553879 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth.h @@ -0,0 +1,65 @@ +/* Copyright (c) 2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_ETHERNET_API_H +#define MBED_ETHERNET_API_H + +#include "device.h" +#include "platform/mbed_toolchain.h" + +#if DEVICE_ETHERNET + +#ifdef __cplusplus +extern "C" { +#endif + +// Connection constants +int rza1_ethernet_init(void); +void rza1_ethernet_free(void); + +// write size bytes from data to ethernet buffer +// return num bytes written +// or -1 if size is too big +int rza1_ethernet_write(const char *data, int size); + +// send ethernet write buffer, returning the packet size sent +int rza1_ethernet_send(void); + +// receive from ethernet buffer, returning packet size, or 0 if no packet +int rza1_ethernet_receive(void); + +// read size bytes in to data, return actual num bytes read (0..size) +// if data == NULL, throw the bytes away +int rza1_ethernet_read(char *data, int size); + +// get the ethernet address +void rza1_ethernet_address(char *mac); + +// see if the link is up +int rza1_ethernet_link(void); + +// force link settings +void rza1_ethernet_set_link(int speed, int duplex); + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + + +/** @}*/ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth_ext.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth_ext.h new file mode 100644 index 0000000..e61a15f --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A1XX/rza1_eth_ext.h @@ -0,0 +1,49 @@ +/* Copyright (c) 2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef ETHERNETEXT_H +#define ETHERNETEXT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* PHY link mode */ +#define NEGO_FAIL (0) +#define HALF_10M (1) +#define FULL_10M (2) +#define HALF_TX (3) +#define FULL_TX (4) + +typedef void (ethernetext_cb_fnc)(void); + +typedef struct tag_rza1_ethernet_cfg { + int int_priority; + ethernetext_cb_fnc *recv_cb; + char *ether_mac; +} rza1_ethernet_cfg_t; + +extern int ethernetext_init(rza1_ethernet_cfg_t *p_ethcfg); +extern void ethernetext_start_stop(int32_t mode); +extern int ethernetext_chk_link_mode(void); +extern void ethernetext_set_link_mode(int32_t link); +extern void ethernetext_add_multicast_group(const uint8_t *addr); +extern void ethernetext_remove_multicast_group(const uint8_t *addr); +extern void ethernetext_set_all_multicast(int all); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/r_ether_rza2_if.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/r_ether_rza2_if.h new file mode 100644 index 0000000..962da91 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/r_ether_rza2_if.h @@ -0,0 +1,201 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + ***********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*********************************************************************************************************************** + * File Name : r_ether_rza2_if.h + * Version : 1.00 + * Description : Ethernet module device driver + ***********************************************************************************************************************/ + +/* Guards against multiple inclusion */ +#ifndef R_ETHER_RZA2_IF_H + #define R_ETHER_RZA2_IF_H + +/*********************************************************************************************************************** + Includes , "Project Includes" + ***********************************************************************************************************************/ + #include + + #include "r_ether_rza2_config.h" + #include "src/phy/phy.h" + +#ifdef __cplusplus +extern "C" { +#endif +/*********************************************************************************************************************** + Macro definitions + ***********************************************************************************************************************/ +/* Version Number of API. */ + #define ETHER_RZA2_VERSION_MAJOR (1) + #define ETHER_RZA2_VERSION_MINOR (0) + +/* When using the Read functions, ETHER_NO_DATA is the return value that indicates that no received data. */ + #define ETHER_NO_DATA (0) + +/* The value of flag which indicates that the interrupt of Ethernet occur. */ + #define ETHER_FLAG_OFF (0) + #define ETHER_FLAG_ON (1) + #define ETHER_FLAG_ON_LINK_ON (3) + #define ETHER_FLAG_ON_LINK_OFF (2) + +/* Channel definition of Ethernet */ + #define ETHER_CHANNEL_0 (0) + #define ETHER_CHANNEL_1 (1) + + #define ETHER_CHANNEL_MAX (ETHER_CH0_EN + ETHER_CH1_EN) + +/*********************************************************************************************************************** + Typedef definitions + ***********************************************************************************************************************/ +/* ETHER API error codes */ +typedef enum +{ + ETHER_SUCCESS = 0, /* Processing completed successfully */ + ETHER_ERR_INVALID_PTR = -1, /* Value of the pointer is NULL */ + ETHER_ERR_INVALID_DATA = -2, /* Value of the argument is out of range */ + ETHER_ERR_INVALID_CHAN = -3, /* Nonexistent channel number */ + ETHER_ERR_INVALID_ARG = -4, /* Invalid argument */ + ETHER_ERR_LINK = -5, /* Auto-negotiation is not completed, and transmission/reception is not enabled. */ + ETHER_ERR_MPDE = -6, /* As a Magic Packet is being detected, and transmission/reception is not enabled. */ + ETHER_ERR_TACT = -7, /* Transmit buffer is not empty. */ + ETHER_ERR_CHAN_OPEN = -8, /* Indicates the Ethernet cannot be opened because it is being used by another application */ + ETHER_ERR_MC_FRAME = -9, /* Detect multicast frame when multicast frame filtering enable */ + ETHER_ERR_RECV_ENABLE = -10, /* Enable receive function in ETHERC */ + ETHER_ERR_OTHER = -11 /* Other error */ +} ether_return_t; + +/* Event code of callback function */ +typedef enum +{ + ETHER_CB_EVENT_ID_WAKEON_LAN, /* Magic packet detection */ + ETHER_CB_EVENT_ID_LINK_ON, /* Link up detection */ + ETHER_CB_EVENT_ID_LINK_OFF, /* Link down detection */ +} ether_cb_event_t; + +/* Structure of the callback function pointer */ +typedef struct +{ + void (*pcb_func) (void *); /* Callback function pointer */ + void (*pcb_int_hnd) (void*); /* Interrupt handler function pointer */ +} ether_cb_t; + +/* Structure to be used when decoding the argument of the callback function */ +typedef struct +{ + uint32_t channel; /* ETHERC channel */ + ether_cb_event_t event_id; /* Event code for callback function */ + uint32_t status_ecsr; /* ETHERC status register for interrupt handler */ + uint32_t status_eesr; /* ETHERC/EDMAC status register for interrupt handler */ +} ether_cb_arg_t; + +/* Parameters of the control function (1st argument) */ +typedef enum +{ + CONTROL_SET_CALLBACK, /* Callback function registration */ + CONTROL_SET_PROMISCUOUS_MODE, /* Promiscuous mode setting */ + CONTROL_SET_INT_HANDLER, /* Interrupt handler function registration */ + CONTROL_POWER_ON, /* Cancel ETHERC/EDMAC module stop */ + CONTROL_POWER_OFF, /* Transition to ETHERC/EDMAC module stop */ + CONTROL_MULTICASTFRAME_FILTER,/* Multicast frame filter setting*/ + CONTROL_BROADCASTFRAME_FILTER /* Broadcast frame filter setting*/ +} ether_cmd_t; + +typedef enum +{ + ETHER_PROMISCUOUS_OFF, /* ETHERC operates in standard mode */ + ETHER_PROMISCUOUS_ON /* ETHERC operates in promiscuous mode */ +} ether_promiscuous_bit_t; + +typedef enum +{ + ETHER_MC_FILTER_OFF, /* Multicast frame filter disable */ + ETHER_MC_FILTER_ON /* Multicast frame filter enable */ +} ether_mc_filter_t; + +typedef struct +{ + uint32_t channel; /* ETHERC channel */ + ether_promiscuous_bit_t bit; /* Promiscuous mode */ +} ether_promiscuous_t; + +typedef struct +{ + uint32_t channel; /* ETHERC channel */ + ether_mc_filter_t flag; /* Multicast frame filter */ +} ether_multicast_t; + +typedef struct +{ + uint32_t channel; /* ETHERC channel */ + uint32_t counter; /* Continuous reception number of Broadcast frame */ +} ether_broadcast_t; + +/* Parameters of the control function (2nd argument) */ +typedef union +{ + ether_cb_t ether_callback; /* Callback function pointer */ + ether_promiscuous_t * p_ether_promiscuous; /* Promiscuous mode setting */ + ether_cb_t ether_int_hnd; /* Interrupt handler function pointer */ + uint32_t channel; /* ETHERC channel number */ + ether_multicast_t * p_ether_multicast; /* Multicast frame filter setting */ + ether_broadcast_t * p_ether_broadcast; /* Broadcast frame filter setting */ +} ether_param_t; + +/*********************************************************************************************************************** + Exported global variables + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ +extern void R_ETHER_Initial (void); +extern ether_return_t R_ETHER_Open_ZC2 (uint32_t channel, const uint8_t mac_addr[], uint8_t pause); +extern ether_return_t R_ETHER_Close_ZC2 (uint32_t channel); +extern int32_t R_ETHER_Read (uint32_t channel, void *pbuf); +extern int32_t R_ETHER_Read_ZC2 (uint32_t channel, void **pbuf); +extern int32_t R_ETHER_Read_ZC2_BufRelease (uint32_t channel); +extern ether_return_t R_ETHER_Write (uint32_t channel, void *pbuf, uint32_t len); +extern ether_return_t R_ETHER_Write_ZC2_GetBuf (uint32_t channel, void **pbuf, uint16_t *pbuf_size); +extern ether_return_t R_ETHER_Write_ZC2_SetBuf (uint32_t channel, const uint32_t len); +extern ether_return_t R_ETHER_CheckLink_ZC (uint32_t channel); +extern void R_ETHER_LinkProcess (uint32_t channel); +extern ether_return_t R_ETHER_WakeOnLAN (uint32_t channel); +extern ether_return_t R_ETHER_CheckWrite (uint32_t channel); +extern ether_return_t R_ETHER_Control (ether_cmd_t const cmd, ether_param_t const control); +extern uint32_t R_ETHER_GetVersion (void); + +#ifdef __cplusplus +} +#endif + +#endif /* R_ETHER_RZA2_IF_H*/ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.c b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.c new file mode 100644 index 0000000..8e97b5b --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.c @@ -0,0 +1,737 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + ***********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*********************************************************************************************************************** + * File Name : phy.c + * Version : 1.00 + * Description : Ethernet PHY device driver + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Includes , "Project Includes" + ***********************************************************************************************************************/ +#include "iodefine.h" +#include "iobitmask.h" +#include "cmsis.h" + +/* Access to peripherals and board defines. */ + +#include "r_ether_rza2_config.h" +#include "src/r_ether_rza2_private.h" +#include "src/phy/phy.h" + +/*********************************************************************************************************************** + Macro definitions + ***********************************************************************************************************************/ +/* Media Independent Interface */ +#define PHY_MII_ST (1) +#define PHY_MII_READ (2) +#define PHY_MII_WRITE (1) + +/* Standard PHY Registers */ +#define PHY_REG_CONTROL (0) +#define PHY_REG_STATUS (1) +#define PHY_REG_IDENTIFIER1 (2) +#define PHY_REG_IDENTIFIER2 (3) +#define PHY_REG_AN_ADVERTISEMENT (4) +#define PHY_REG_AN_LINK_PARTNER (5) +#define PHY_REG_AN_EXPANSION (6) + +/* Vendor Specific PHY Registers */ +#ifdef ETHER_CFG_USE_PHY_KSZ8041NL + #define PHY_REG_PHY_CONTROL_1 (0x1E) +#endif /* MICREL_KSZ8041NL */ + +/* Basic Mode Control Register Bit Definitions */ +#define PHY_CONTROL_RESET (1 << 15) +#define PHY_CONTROL_LOOPBACK (1 << 14) +#define PHY_CONTROL_100_MBPS (1 << 13) +#define PHY_CONTROL_AN_ENABLE (1 << 12) +#define PHY_CONTROL_POWER_DOWN (1 << 11) +#define PHY_CONTROL_ISOLATE (1 << 10) +#define PHY_CONTROL_AN_RESTART (1 << 9) +#define PHY_CONTROL_FULL_DUPLEX (1 << 8) +#define PHY_CONTROL_COLLISION (1 << 7) + +/* Basic Mode Status Register Bit Definitions */ +#define PHY_STATUS_100_T4 (1 << 15) +#define PHY_STATUS_100F (1 << 14) +#define PHY_STATUS_100H (1 << 13) +#define PHY_STATUS_10F (1 << 12) +#define PHY_STATUS_10H (1 << 11) +#define PHY_STATUS_AN_COMPLETE (1 << 5) +#define PHY_STATUS_RM_FAULT (1 << 4) +#define PHY_STATUS_AN_ABILITY (1 << 3) +#define PHY_STATUS_LINK_UP (1 << 2) +#define PHY_STATUS_JABBER (1 << 1) +#define PHY_STATUS_EX_CAPABILITY (1 << 0) + +/* Auto Negotiation Advertisement Bit Definitions */ +#define PHY_AN_ADVERTISEMENT_NEXT_PAGE (1 << 15) +#define PHY_AN_ADVERTISEMENT_RM_FAULT (1 << 13) +#define PHY_AN_ADVERTISEMENT_ASM_DIR (1 << 11) +#define PHY_AN_ADVERTISEMENT_PAUSE (1 << 10) +#define PHY_AN_ADVERTISEMENT_100_T4 (1 << 9) +#define PHY_AN_ADVERTISEMENT_100F (1 << 8) +#define PHY_AN_ADVERTISEMENT_100H (1 << 7) +#define PHY_AN_ADVERTISEMENT_10F (1 << 6) +#define PHY_AN_ADVERTISEMENT_10H (1 << 5) +#define PHY_AN_ADVERTISEMENT_SELECTOR (1 << 0) + +/* Auto Negotiate Link Partner Ability Bit Definitions */ +#define PHY_AN_LINK_PARTNER_NEXT_PAGE (1 << 15) +#define PHY_AN_LINK_PARTNER_ACK (1 << 14) +#define PHY_AN_LINK_PARTNER_RM_FAULT (1 << 13) +#define PHY_AN_LINK_PARTNER_ASM_DIR (1 << 11) +#define PHY_AN_LINK_PARTNER_PAUSE (1 << 10) +#define PHY_AN_LINK_PARTNER_100_T4 (1 << 9) +#define PHY_AN_LINK_PARTNER_100F (1 << 8) +#define PHY_AN_LINK_PARTNER_100H (1 << 7) +#define PHY_AN_LINK_PARTNER_10F (1 << 6) +#define PHY_AN_LINK_PARTNER_10H (1 << 5) +#define PHY_AN_LINK_PARTNER_SELECTOR (1 << 0) + +/*********************************************************************************************************************** + Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Private global variables and functions + ***********************************************************************************************************************/ +static uint16_t phy_read (uint32_t ether_channel, uint16_t reg_addr); +static void phy_write (uint32_t ether_channel, uint16_t reg_addr, uint16_t data); +static void phy_preamble (uint32_t ether_channel); +static void phy_reg_set (uint32_t ether_channel, uint16_t reg_addr, int32_t option); +static void phy_reg_read (uint32_t ether_channel, uint16_t *pdata); +static void phy_reg_write (uint32_t ether_channel, uint16_t data); +static void phy_trans_zto0 (uint32_t ether_channel); +static void phy_trans_1to0 (uint32_t ether_channel); +static void phy_mii_write1 (uint32_t ether_channel); +static void phy_mii_write0 (uint32_t ether_channel); +static int16_t phy_get_pir_address (uint32_t ether_channel, volatile uint32_t ** pppir_addr); +static uint32_t phy_get_ctrl_tbl_idx (uint32_t ether_channel); + +static uint16_t local_advertise[ETHER_CHANNEL_MAX]; /* the capabilities of the local link as PHY data */ + +/** + * Public functions + */ + +/*********************************************************************************************************************** + * Function Name: phy_init + * Description : Resets Ethernet PHY device + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : R_PHY_OK - + * + * R_PHY_ERROR - + * + ***********************************************************************************************************************/ +int16_t phy_init (uint32_t ether_channel) +{ + uint16_t reg; + uint32_t count; + + /* Reset PHY */ + phy_write(ether_channel, PHY_REG_CONTROL, PHY_CONTROL_RESET); + + count = 0; + + /* Reset completion waiting */ + do { + reg = phy_read(ether_channel, PHY_REG_CONTROL); + count++; + } while ((reg & PHY_CONTROL_RESET) && (count < ETHER_CFG_PHY_DELAY_RESET)); + + if (count < ETHER_CFG_PHY_DELAY_RESET) { + /* + * When KSZ8041NL of the Micrel, Inc. is used, + * the pin that outputs the state of LINK is used combinedly with ACTIVITY in default. + * The setting of the pin is changed so that only the state of LINK is output. + */ +#if ETHER_CFG_USE_PHY_KSZ8041NL != 0 + reg = phy_read(ether_channel, PHY_REG_PHY_CONTROL_1); + reg &= ~0x8000; + reg |= 0x4000; + phy_write(ether_channel, PHY_REG_PHY_CONTROL_1, reg); +#endif /* ETHER_CFG_USE_PHY_KSZ8041NL != 0 */ + + return R_PHY_OK; + } + return R_PHY_ERROR; +} /* End of function phy_init() */ + +/*********************************************************************************************************************** + * Function Name: phy_start_autonegotiate + * Description : Starts auto-negotiate + * Arguments : ether_channel - + * Ethernet channel number + * pause - + * Using state of pause frames + * Return Value : none + ***********************************************************************************************************************/ +void phy_start_autonegotiate (uint32_t ether_channel, uint8_t pause) +{ + volatile uint16_t reg = 0; + uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel); + + /* Set local ability */ + /* When pause frame is not used */ + if (ETHER_FLAG_OFF == pause) { + local_advertise[ether_channel_index] = ((((PHY_AN_ADVERTISEMENT_100F | + PHY_AN_ADVERTISEMENT_100H) | + PHY_AN_ADVERTISEMENT_10F) | + PHY_AN_ADVERTISEMENT_10H) | + PHY_AN_ADVERTISEMENT_SELECTOR); + + } + + /* When pause frame is used */ + else { + local_advertise[ether_channel_index] = ((((((PHY_AN_ADVERTISEMENT_ASM_DIR | + PHY_AN_ADVERTISEMENT_PAUSE) | + PHY_AN_ADVERTISEMENT_100F) | + PHY_AN_ADVERTISEMENT_100H) | + PHY_AN_ADVERTISEMENT_10F) | + PHY_AN_ADVERTISEMENT_10H) | + PHY_AN_ADVERTISEMENT_SELECTOR); + } + + /* Configure what the PHY and the Ethernet controller on this board supports */ + phy_write(ether_channel, PHY_REG_AN_ADVERTISEMENT, local_advertise[ether_channel_index]); + phy_write(ether_channel, PHY_REG_CONTROL, (PHY_CONTROL_AN_ENABLE | + PHY_CONTROL_AN_RESTART)); + + reg = phy_read(ether_channel, PHY_REG_AN_ADVERTISEMENT); + (void)reg; + +} /* End of function phy_start_autonegotiate() */ + +/*********************************************************************************************************************** + * Function Name: phy_set_autonegotiate + * Description : reports the other side's physical capability + * Arguments : ether_channel - + * Ethernet channel number + * : *pline_speed_duplex - + * a pointer to the location of both the line speed and the duplex + * *plocal_pause - + * a pointer to the location to store the local pause bits. + * *ppartner_pause - + * a pointer to the location to store the partner pause bits. + * Return Value : R_PHY_OK - + * + * R_PHY_ERROR - + * + * Note : The value returned to local_pause and patner_pause is used + * as it is as an argument of ether_pause_resolution function. + ***********************************************************************************************************************/ +int16_t phy_set_autonegotiate (uint32_t ether_channel, uint16_t *pline_speed_duplex, uint16_t *plocal_pause, + uint16_t *ppartner_pause) +{ + uint16_t reg; + uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel); + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + reg = phy_read(ether_channel, PHY_REG_STATUS); + reg = phy_read(ether_channel, PHY_REG_STATUS); + + /* When the link isn't up, return error */ + if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP)) { + return R_PHY_ERROR; + } + + /* Establish local pause capability */ + if (PHY_AN_ADVERTISEMENT_PAUSE == (local_advertise[ether_channel_index] & PHY_AN_ADVERTISEMENT_PAUSE)) { + (*plocal_pause) |= (1 << 1); + } + + if (PHY_AN_ADVERTISEMENT_ASM_DIR == (local_advertise[ether_channel_index] & PHY_AN_ADVERTISEMENT_ASM_DIR)) { + (*plocal_pause) |= 1; + } + + /* When the auto-negotiation isn't completed, return error */ + if (PHY_STATUS_AN_COMPLETE != (reg & PHY_STATUS_AN_COMPLETE)) { + return R_PHY_ERROR; + } + + /* Get the link partner response */ + reg = phy_read(ether_channel, PHY_REG_AN_LINK_PARTNER); + + /* Establish partner pause capability */ + if (PHY_AN_LINK_PARTNER_PAUSE == (reg & PHY_AN_LINK_PARTNER_PAUSE)) + { + (*ppartner_pause) = (1 << 1); + } + + if (PHY_AN_LINK_PARTNER_ASM_DIR == (reg & PHY_AN_LINK_PARTNER_ASM_DIR)) + { + (*ppartner_pause) |= 1; + } + + /* Establish the line speed and the duplex */ + if (PHY_AN_LINK_PARTNER_10H == (reg & PHY_AN_LINK_PARTNER_10H)) + { + (*pline_speed_duplex) = PHY_LINK_10H; + } + + if (PHY_AN_LINK_PARTNER_10F == (reg & PHY_AN_LINK_PARTNER_10F)) + { + (*pline_speed_duplex) = PHY_LINK_10F; + } + + if (PHY_AN_LINK_PARTNER_100H == (reg & PHY_AN_LINK_PARTNER_100H)) + { + (*pline_speed_duplex) = PHY_LINK_100H; + } + + if (PHY_AN_LINK_PARTNER_100F == (reg & PHY_AN_LINK_PARTNER_100F)) + { + (*pline_speed_duplex) = PHY_LINK_100F; + } + + return R_PHY_OK; +} /* End of function phy_set_autonegotiate() */ + +/*********************************************************************************************************************** + * Function Name: phy_get_link_status + * Description : Returns the status of the physical link + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : -1 if links is down, 0 otherwise + ***********************************************************************************************************************/ +int16_t phy_get_link_status (uint32_t ether_channel) +{ + uint16_t reg; + + /* Because reading the first time shows the previous state, the Link status bit is read twice. */ + reg = phy_read(ether_channel, PHY_REG_STATUS); + reg = phy_read(ether_channel, PHY_REG_STATUS); + + + /* When the link isn't up, return error */ + if (PHY_STATUS_LINK_UP != (reg & PHY_STATUS_LINK_UP)) { + /* Link is down */ + return R_PHY_ERROR; + } + + /* Link is up */ + return R_PHY_OK; +} /* End of function phy_get_link_status() */ + +/** + * Private functions + */ + +/*********************************************************************************************************************** + * Function Name: phy_read + * Description : Reads a PHY register + * Arguments : ether_channel - + * Ethernet channel number + * reg_addr - + * address of the PHY register + * Return Value : read value + ***********************************************************************************************************************/ +static uint16_t phy_read (uint32_t ether_channel, uint16_t reg_addr) +{ + uint16_t data; + + /* + * The value is read from the PHY register by the frame format of MII Management Interface provided + * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2. + */ + phy_preamble(ether_channel); + phy_reg_set(ether_channel, reg_addr, PHY_MII_READ); + phy_trans_zto0(ether_channel); + phy_reg_read(ether_channel, &data); + phy_trans_zto0(ether_channel); + + return (data); +} /* End of function phy_read() */ + +/*********************************************************************************************************************** + * Function Name: phy_write + * Description : Writes to a PHY register + * Arguments : ether_channel - + * Ethernet channel number + * reg_addr - + * address of the PHY register + * data - + * value + * Return Value : none + ***********************************************************************************************************************/ +static void phy_write (uint32_t ether_channel, uint16_t reg_addr, uint16_t data) +{ + /* + * The value is read from the PHY register by the frame format of MII Management Interface provided + * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2. + */ + phy_preamble(ether_channel); + phy_reg_set(ether_channel, reg_addr, PHY_MII_WRITE); + phy_trans_1to0(ether_channel); + phy_reg_write(ether_channel, data); + phy_trans_zto0(ether_channel); +} /* End of function phy_write() */ + +/*********************************************************************************************************************** + * Function Name: phy_preamble + * Description : As preliminary preparation for access to the PHY module register, + * "1" is output via the MII management interface. + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void phy_preamble (uint32_t ether_channel) +{ + int16_t i; + + /* + * The processing of PRE (preamble) about the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + i = 32; + while (i > 0) { + phy_mii_write1(ether_channel); + i--; + } +} /* End of function phy_preamble() */ + +/*********************************************************************************************************************** + * Function Name: phy_reg_set + * Description : Sets a PHY device to read or write mode + * Arguments : ether_channel - + * Ethernet channel number + * reg_addr - + * address of the PHY register + * option - + * mode + * Return Value : none + ***********************************************************************************************************************/ +static void phy_reg_set (uint32_t ether_channel, uint16_t reg_addr, int32_t option) +{ + int32_t i; + uint16_t data; + uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel); + + /* + * The processing of ST (start of frame),OP (operation code), PHYAD (PHY Address), and + * REGAD (Register Address) about the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + data = 0; + data = (PHY_MII_ST << 14); /* ST code */ + + if (PHY_MII_READ == option) { + data |= (PHY_MII_READ << 12); /* OP code(RD) */ + } else { + data |= (PHY_MII_WRITE << 12); /* OP code(WT) */ + } + + data |= (uint16_t) (g_eth_control_ch[ether_channel_index].phy_address << 7); /* PHY Address */ + + data |= (reg_addr << 2); /* Reg Address */ + + i = 14; + while (i > 0) { + if (0 == (data & 0x8000)) { + phy_mii_write0(ether_channel); + } else { + phy_mii_write1(ether_channel); + } + data <<= 1; + i--; + } +} /* End of function phy_reg_set() */ + +/*********************************************************************************************************************** + * Function Name: phy_reg_read + * Description : Reads PHY register through MII interface + * Arguments : ether_channel - + * Ethernet channel number + * pdata - + * pointer to store the data read + * Return Value : none + ***********************************************************************************************************************/ +static void phy_reg_read (uint32_t ether_channel, uint16_t *pdata) +{ + int32_t i; + int32_t j; + uint16_t reg_data; + int16_t ret; + volatile uint32_t * petherc_pir; + + ret = phy_get_pir_address(ether_channel, &petherc_pir); + if (R_PHY_ERROR == ret) { + return; + } + + /* + * The processing of DATA (data) about reading of the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + reg_data = 0; + i = 16; + while (i > 0) { + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000000; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000001; + } + reg_data <<= 1; + + reg_data |= (uint16_t) (((*petherc_pir) & 0x00000008) >> 3); /* MDI read */ + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000001; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000000; + } + + i--; + } + (*pdata) = reg_data; +} /* End of function phy_reg_read() */ + +/*********************************************************************************************************************** + * Function Name: phy_reg_write + * Description : Writes to PHY register through MII interface + * Arguments : ether_channel - + * Ethernet channel number + * data - + * value to write + * Return Value : none + ***********************************************************************************************************************/ +static void phy_reg_write (uint32_t ether_channel, uint16_t data) +{ + int32_t i; + + /* + * The processing of DATA (data) about writing of the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + i = 16; + while (i > 0) { + if (0 == (data & 0x8000)) { + phy_mii_write0(ether_channel); + } else { + phy_mii_write1(ether_channel); + } + i--; + data <<= 1; + } +} /* End of function phy_reg_write() */ + +/*********************************************************************************************************************** + * Function Name: phy_trans_zto0 + * Description : Performs bus release so that PHY can drive data + * : for read operation + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void phy_trans_zto0 (uint32_t ether_channel) +{ + int32_t j; + int16_t ret; + volatile uint32_t * petherc_pir; + + ret = phy_get_pir_address(ether_channel, &petherc_pir); + if (R_PHY_ERROR == ret) { + return; + } + + /* + * The processing of TA (turnaround) about reading of the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000000; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000001; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000001; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000000; + } + +} /* End of function phy_trans_zto0() */ + +/*********************************************************************************************************************** + * Function Name: phy_trans_1to0 + * Description : Switches data bus so MII interface can drive data + * : for write operation + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void phy_trans_1to0 (uint32_t ether_channel) +{ + /* + * The processing of TA (turnaround) about writing of the frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + phy_mii_write1(ether_channel); + phy_mii_write0(ether_channel); +} /* End of function phy_trans_1to0() */ + +/*********************************************************************************************************************** + * Function Name: phy_mii_write1 + * Description : Outputs 1 to the MII interface + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void phy_mii_write1 (uint32_t ether_channel) +{ + int32_t j; + int16_t ret; + volatile uint32_t * petherc_pir; + + ret = phy_get_pir_address(ether_channel, &petherc_pir); + if (R_PHY_ERROR == ret) { + return; + } + + /* + * The processing of one bit about frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + * The data that 1 is output. + */ + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000006; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000007; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000007; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000006; + } + +} /* End of function phy_mii_write1() */ + +/*********************************************************************************************************************** + * Function Name: phy_mii_write0 + * Description : Outputs 0 to the MII interface + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***********************************************************************************************************************/ +static void phy_mii_write0 (uint32_t ether_channel) +{ + int32_t j; + int16_t ret; + volatile uint32_t * petherc_pir; + + ret = phy_get_pir_address(ether_channel, &petherc_pir); + if (R_PHY_ERROR == ret) { + return; + } + + /* + * The processing of one bit about frame format of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + * The data that 0 is output. + */ + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000002; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000003; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000003; + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) { + (*petherc_pir) = 0x00000002; + } + +} /* End of function phy_mii_write0() */ + +/*********************************************************************************************************************** + * Function Name: phy_get_pir_address + * Description : Get the address of the PHY interface register. + * Arguments : ether_channel - + * Ethernet channel number + * pppir_addr - + * Pointer of the PHY interface register + * Return Value : none + ***********************************************************************************************************************/ +static int16_t phy_get_pir_address (uint32_t ether_channel, volatile uint32_t ** pppir_addr) +{ + volatile uint32_t * petherc_pir; + uint32_t ether_channel_index = phy_get_ctrl_tbl_idx(ether_channel); + + petherc_pir = g_eth_control_ch[ether_channel_index].preg_pir; + + (*pppir_addr) = petherc_pir; + + return R_PHY_OK; +} /* End of function phy_get_pir_address() */ + +/*********************************************************************************************************************** + * Function Name: phy_get_ctrl_tbl_idx + * Description : get index of control table. + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : Index of control table + ***********************************************************************************************************************/ +static uint32_t phy_get_ctrl_tbl_idx (uint32_t ether_channel) +{ +#if (ETHER_CHANNEL_MAX == 1) + return 0; +#else + return ether_channel; +#endif +} /* End of function phy_get_ctrl_tbl_idx() */ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.h new file mode 100644 index 0000000..96d4a76 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/phy/phy.h @@ -0,0 +1,85 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + ***********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*********************************************************************************************************************** + * File Name : phy.h + * Version : 1.00 + * Description : Ethernet PHY device driver + ***********************************************************************************************************************/ + +/* Guards against multiple inclusion */ +#ifndef PHY_H + #define PHY_H + +/*********************************************************************************************************************** + Includes , "Project Includes" + ***********************************************************************************************************************/ + #include + +#ifdef __cplusplus +extern "C" { +#endif +/*********************************************************************************************************************** + Macro definitions + ***********************************************************************************************************************/ +/* PHY return definitions */ + #define R_PHY_OK (0) + #define R_PHY_ERROR (-1) + +/*********************************************************************************************************************** + Typedef definitions + ***********************************************************************************************************************/ +typedef enum LinkStatE +{ + PHY_NO_LINK = 0, PHY_LINK_10H, PHY_LINK_10F, PHY_LINK_100H, PHY_LINK_100F +} linkstat_t; + +/*********************************************************************************************************************** + Exported global variables + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ +extern int16_t phy_init (uint32_t channel); +extern void phy_start_autonegotiate (uint32_t channel, uint8_t pause); +extern int16_t phy_set_autonegotiate (uint32_t channel, uint16_t *pline_speed_duplex, uint16_t *plocal_pause, + uint16_t *ppartner_pause); +extern int16_t phy_get_link_status (uint32_t channel); + +#ifdef __cplusplus +} +#endif + +#endif /* PHY_H */ + diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/r_ether_rza2.c b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/r_ether_rza2.c new file mode 100644 index 0000000..3dedac1 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/r_ether_rza2.c @@ -0,0 +1,2158 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + ***********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*********************************************************************************************************************** + * File Name : r_ether_rza2.c + * Version : 1.0 + * Description : Ethernet module device driver + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Includes , "Project Includes" + ***********************************************************************************************************************/ +#include +#include "iodefine.h" +#include "iobitmask.h" +#include "cmsis.h" + +/* Access to peripherals and board defines. */ +#include "r_ether_rza2_if.h" +#include "src/r_ether_rza2_private.h" + +/*********************************************************************************************************************** + Macro definitions + ***********************************************************************************************************************/ +#define ETHER_CFG_USE_VIRTUAL_ADDRESS 0 /* Since the virtual address is not used in the Mbed, the process is simplified. */ + +/*********************************************************************************************************************** + Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global variables (to be accessed by other files) + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Private global variables and functions + ***********************************************************************************************************************/ + +/* + * Private global function prototypes + */ +static void ether_reset_mac (uint32_t channel); +static void ether_init_descriptors (uint32_t channel); +static void ether_config_ethernet (uint32_t channel, const uint8_t mode); +static void ether_pause_resolution (uint16_t local_ability, uint16_t partner_ability, uint16_t *ptx_pause, + uint16_t *prx_pause); +static void ether_configure_mac (uint32_t channel, const uint8_t mac_addr[], const uint8_t mode); +static ether_return_t ether_do_link (uint32_t channel, const uint8_t mode); +static ether_return_t ether_set_callback (ether_param_t const control); +static ether_return_t ether_set_promiscuous_mode (ether_param_t const control); +static ether_return_t ether_set_int_handler (ether_param_t const control); +static ether_return_t ether_power_on (ether_param_t const control); +static ether_return_t ether_power_off (ether_param_t const control); +static ether_return_t power_on (uint32_t channel); +static void power_off (uint32_t channel); +static ether_return_t ether_set_multicastframe_filter (ether_param_t const control); +static ether_return_t ether_set_broadcastframe_filter (ether_param_t const control); +#if (ETHER_CH0_EN == 1) +static void ether_eint0 (void); +#endif +#if (ETHER_CH1_EN == 1) +static void ether_eint1 (void); +#endif +static void ether_int_common (uint32_t channel); +static ether_return_t power_on_control (uint32_t channel); +static void power_off_control (uint32_t channel); +static uint8_t check_mpde_bit (void); +static uint32_t get_control_tbl_index (uint32_t channel); + +/* + * Private global variables + */ + +/* Pointer to the receive descriptors */ +static descriptor_t * papp_rx_desc[ETHER_CHANNEL_MAX]; + +/* Pointer to the transmit descriptors */ +static descriptor_t * papp_tx_desc[ETHER_CHANNEL_MAX]; + +/* Pointer to the callback function */ +static ether_cb_t cb_func; + +/* + * The flag which control the pause frame. + * + * The value of flag and the situation which is indicatived of by the value. + * ETHER_FLAG_OFF (0): Don't use the pause frame (default). + * ETHER_FLAG_ON (1): Use the pause frame. + */ +static uint8_t pause_frame_enable[ETHER_CHANNEL_MAX]; + +/* + * The flag indicatives of the state that the interrupt of Link Up/Down occur. + * + * Value and state of flag + * ETHER_FLAG_OFF (0): It is not possible to communicate. + * ETHER_FLAG_ON (1): It is possible to communicate. + */ +static uint8_t transfer_enable_flag[ETHER_CHANNEL_MAX]; + +/* + * The flag indicatives of the state that the interrupt of magic packet detection occur. + * + * Value and state of flag + * ETHER_FLAG_OFF (0): The interrupt of the magic packet detection has not been generated. + * ETHER_FLAG_ON (1): The interrupt of the magic packet detection was generated. + * + * If the R_ETHER_LinkProcess function is called, and the interrupt processing of the magic packet detection is done, + * this flag becomes ETHER_FLAG_OFF(0). + */ +static uint8_t mpd_flag[ETHER_CHANNEL_MAX]; + +static uint8_t mac_addr_buf[ETHER_CHANNEL_MAX][6]; + +/* + * The flag indicatives of the state that the interrupt of Link Up/Down occur. + * + * Value and state of flag + * ETHER_FLAG_OFF (0) : The Link up/down interrupt has not been generated. + * ETHER_FLAG_ON_LINK_OFF (2) : The Link down interrupt was generated. + * ETHER_FLAG_ON_LINK_ON (3) : The Link up interrupt was generated. + * + * If the R_ETHER_LinkProcess function is called, and the interrupt processing of Link Up/Down is done, + * this flag becomes ETHER_FLAG_OFF(0). + */ +static uint8_t lchng_flag[ETHER_CHANNEL_MAX]; + +/* + * The flag indicatives of the state that enable/disable multicast frame filtering. + * + * Value and state of flag + * ETHER_MC_FILTER_OFF (0) : Disable multicast frame filtering. + * ETHER_MC_FILTER_ON (1) : Enable multicast frame filtering. + * + * The frame multicast filtering is software filter. If you want to use Hardware filter, + * please use it EPTPC in RX64M/RX71M. + */ +static uint8_t mc_filter_flag[ETHER_CHANNEL_MAX]; + +/* + * The value indicatives of receive count for continuous broadcast frame. + */ +static uint32_t bc_filter_count[ETHER_CHANNEL_MAX]; + +/* + * PAUSE Resolution as documented in IEEE 802.3-2008_section2 Annex + * 28B, Table 28B-3. The following table codify logic that + * determines how the PAUSE is configured for local transmitter + * and receiver and partner transmitter and receiver. + */ +static const pauseresolution_t pause_resolution[PAUSE_TABLE_ENTRIES] = +{ +{ PAUSE_MASKC, PAUSE_VAL0, XMIT_PAUSE_OFF, RECV_PAUSE_OFF }, +{ PAUSE_MASKE, PAUSE_VAL4, XMIT_PAUSE_OFF, RECV_PAUSE_OFF }, +{ PAUSE_MASKF, PAUSE_VAL6, XMIT_PAUSE_OFF, RECV_PAUSE_OFF }, +{ PAUSE_MASKF, PAUSE_VAL7, XMIT_PAUSE_ON, RECV_PAUSE_OFF }, +{ PAUSE_MASKE, PAUSE_VAL8, XMIT_PAUSE_OFF, RECV_PAUSE_OFF }, +{ PAUSE_MASKA, PAUSE_VALA, XMIT_PAUSE_ON, RECV_PAUSE_ON }, +{ PAUSE_MASKF, PAUSE_VALC, XMIT_PAUSE_OFF, RECV_PAUSE_OFF }, +{ PAUSE_MASKF, PAUSE_VALD, XMIT_PAUSE_OFF, RECV_PAUSE_ON } }; + +/* + * Receive, transmit descriptors and their buffer. They are + * defined with section pragma directives to easily locate them + * on the memory map. + */ +static descriptor_t rx_descriptors[ETHER_CHANNEL_MAX][ETHER_CFG_EMAC_RX_DESCRIPTORS] __attribute((section("NC_BSS"),aligned(32))); +static descriptor_t tx_descriptors[ETHER_CHANNEL_MAX][ETHER_CFG_EMAC_TX_DESCRIPTORS] __attribute((section("NC_BSS"),aligned(32))); + +/* + * As for Ethernet buffer, the size of total buffer which are use for transmission and the reception is secured. + * The total buffer's size which the value is integrated from EMAC_NUM_BUFFERS (buffer number) and + * ETHER_CFG_BUFSIZE (the size of one buffer). + * The ETHER_CFG_BUFSIZE and EMAC_NUM_BUFFERS are defined by macro in the file "r_ether_private.h". + * It is sequentially used from the head of the buffer as a receive buffer or a transmission buffer. + */ +static etherbuffer_t ether_buffers[ETHER_CHANNEL_MAX] __attribute((section("NC_BSS"),aligned(32))); + +static uint8_t promiscuous_mode[ETHER_CHANNEL_MAX]; + +static uint8_t etherc_edmac_power_cont[ETHER_CHANNEL_MAX]; + +const ether_control_t g_eth_control_ch[ETHER_CHANNEL_MAX] = +{ +#if (ETHER_CH0_EN == 1) + /* Ether = ch0, Phy access = ch0 */ + { ÐERC0, &EDMAC0, (volatile uint32_t*)ÐERC0.PIR.LONG, ETHER_CFG_CH0_PHY_ADDRESS, PORT_CONNECT_ET0 }, +#endif +#if (ETHER_CH1_EN == 1) + /* Ether = ch1, Phy access = ch1 */ + { ÐERC1, &EDMAC1, (volatile uint32_t*)ÐERC1.PIR.LONG, ETHER_CFG_CH1_PHY_ADDRESS, PORT_CONNECT_ET1 }, +#endif +}; + +#if (ETHER_CFG_USE_LINKSTA == 0) +/* Previous link status */ +static int16_t g_pre_link_stat[ETHER_CHANNEL_MAX]; +#endif + +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) +static uint32_t ether_mmu_uncached_diff; + +static uint32_t ether_mmu_VAtoPA(uint32_t vaddr) +{ + uint32_t *ttb = (uint32_t *)(__get_TTBR0() & 0xFFFFC000); + uint32_t *ttb_l2; + uint32_t paddr = vaddr; + + ttb += (vaddr >> 20); + if ((*ttb & (0x40000 | 0x3)) == 2) { + paddr = (*ttb & 0xfff00000) | (vaddr & 0xfffff); + } else if ((*ttb & 0x3) == 1) { + ttb_l2 = (uint32_t *)(*ttb & 0xFFFFFC00); + if ((*ttb_l2 & 0x3) == 0) { + /* do nothing */ + } else if ((*ttb_l2 & 0x3) == 1) { /* 64k page entry */ + ttb_l2 += ((vaddr & 0x000ff000) >> 12); + paddr = (*ttb_l2 & 0xffff0000) | (vaddr & 0xffff); + } else { /* 4k page entry */ + ttb_l2 += ((vaddr & 0x000ff000) >> 12); + paddr = (*ttb_l2 & 0xfffff000) | (vaddr & 0xfff); + } + } else { + /* do nothing */ + } + + return paddr; +} +#endif + +/* + * Renesas Ethernet API functions + */ +/*********************************************************************************************************************** + * Function Name: R_ETHER_Initial (Implementation to file hwsetup.c) + * Description : Initialization of Ether driver. + * Arguments : none + * Return Value : none + ***********************************************************************************************************************/ +void R_ETHER_Initial (void) +{ + uint32_t i; + + /* Initialize the transmit and receive descriptor */ + memset(&rx_descriptors, 0x00, sizeof(rx_descriptors)); + memset(&tx_descriptors, 0x00, sizeof(tx_descriptors)); + + /* Initialize the Ether buffer */ + memset(ðer_buffers, 0x00, sizeof(ether_buffers)); + + memset(etherc_edmac_power_cont, 0x00, sizeof(etherc_edmac_power_cont)); + + /* Initialize the callback function pointer */ + cb_func.pcb_func = NULL; + + /* Initialize the interrupt handler pointer */ + cb_func.pcb_int_hnd = NULL; + + /* Initialize */ + for (i = 0; i < ETHER_CHANNEL_MAX; i++) { + papp_rx_desc[i] = NULL; + papp_tx_desc[i] = NULL; + pause_frame_enable[i] = ETHER_FLAG_OFF; +#if (ETHER_CFG_USE_LINKSTA == 0) + g_pre_link_stat[i] = ETHER_ERR_OTHER; +#endif + promiscuous_mode[i] = ETHER_PROMISCUOUS_OFF; + mc_filter_flag[i] = ETHER_MC_FILTER_OFF; + bc_filter_count[i] = 0; + } +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) + { + uint32_t vaddress = (uint32_t)&rx_descriptors; + uint32_t paddress; + + paddress = ether_mmu_VAtoPA(vaddress); + ether_mmu_uncached_diff = vaddress - paddress; + } +#endif + +} /* End of function R_ETHER_Initial() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Open_ZC2 + * Description : After ETHERC, EDMAC,0x00000002; and PHY-LSI are reset in software, an auto negotiation of PHY-LSI is + * begun. + * Afterwards, the link signal change interrupt is permitted. + * Arguments : channel - + * ETHERC channel number + * mac_addr - + * The MAC address of ETHERC + * pause - + * Specifies whether flow control functionality is enabled or disabled. + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_INVALID_PTR - + * Value of the pointer is NULL + * ETHER_ERR_INVALID_DATA - + * Value of the argument is out of range + * ETHER_ERR_OTHER - + * Initialization of PHY-LSI failed + ***********************************************************************************************************************/ +ether_return_t R_ETHER_Open_ZC2 (uint32_t channel, const uint8_t mac_addr[], uint8_t pause) +{ + ether_return_t ret; + int16_t phy_ret; + volatile struct st_etherc * petherc_adr; + volatile struct st_edmac * pedmac_adr; + uint32_t channel_index = get_control_tbl_index(channel); + + if (NULL == mac_addr) { + return ETHER_ERR_INVALID_PTR; + } + if ((ETHER_FLAG_OFF != pause) && (ETHER_FLAG_ON != pause)) { + return ETHER_ERR_INVALID_DATA; + } + + petherc_adr = g_eth_control_ch[channel_index].petherc; + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + + /* Initialize the flags */ + transfer_enable_flag[channel_index] = ETHER_FLAG_OFF; + mpd_flag[channel_index] = ETHER_FLAG_OFF; + lchng_flag[channel_index] = ETHER_FLAG_OFF; + + pause_frame_enable[channel_index] = pause; + + mac_addr_buf[channel_index][0] = mac_addr[0]; + mac_addr_buf[channel_index][1] = mac_addr[1]; + mac_addr_buf[channel_index][2] = mac_addr[2]; + mac_addr_buf[channel_index][3] = mac_addr[3]; + mac_addr_buf[channel_index][4] = mac_addr[4]; + mac_addr_buf[channel_index][5] = mac_addr[5]; + +#if (ETHER_CH0_EN == 1) + InterruptHandlerRegister(EINT0_IRQn, ðer_eint0); +#endif +#if (ETHER_CH1_EN == 1) + InterruptHandlerRegister(EINT1_IRQn, ðer_eint1); +#endif + + /* Software reset */ + ether_reset_mac(channel); + + /* Software reset the PHY */ + phy_ret = phy_init(channel); + if (R_PHY_OK == phy_ret) { + phy_start_autonegotiate(channel, pause_frame_enable[channel_index]); + + /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + petherc_adr->ECSR.LONG = 0x00000037; + + /* Clear all EDMAC status bits */ + pedmac_adr->EESR.LONG = 0x47FF0F9F; + +#if (ETHER_CFG_USE_LINKSTA == 1) + /* Enable interrupts of interest only. */ + petherc_adr->ECSIPR.BIT.LCHNGIP = 1; +#endif + + pedmac_adr->EESIPR.BIT.ECIIP = 1; + + /* Set Ethernet interrupt level and enable */ +#if (ETHER_CH0_EN == 1) + GIC_SetPriority(EINT0_IRQn, 0x80); + GIC_EnableIRQ(EINT0_IRQn); +#endif +#if (ETHER_CH1_EN == 1) + GIC_SetPriority(EINT1_IRQn, 0x80); + GIC_EnableIRQ(EINT1_IRQn); +#endif + ret = ETHER_SUCCESS; + } else { + ret = ETHER_ERR_OTHER; + } + + return ret; +} /* End of function R_ETHER_Open_ZC2() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Close_ZC2 + * Description : Disables Ethernet peripheral + * Arguments : channel - + * ETHERC channel number + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + ***********************************************************************************************************************/ +ether_return_t R_ETHER_Close_ZC2 (uint32_t channel) +{ + volatile struct st_etherc * petherc_adr; + volatile struct st_edmac * pedmac_adr; + uint32_t channel_index = get_control_tbl_index(channel); + + petherc_adr = g_eth_control_ch[channel_index].petherc; + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + + /* Disable Ethernet interrupt. */ +#if (ETHER_CH0_EN == 1) + GIC_DisableIRQ(EINT0_IRQn); +#endif +#if (ETHER_CH1_EN == 1) + GIC_DisableIRQ(EINT1_IRQn); +#endif + + petherc_adr->ECSIPR.BIT.LCHNGIP = 0; + pedmac_adr->EESIPR.BIT.ECIIP = 0; + + /* Disable TE and RE */ + petherc_adr->ECMR.LONG = 0x00000000; + + /* Initialize the flags */ + transfer_enable_flag[channel_index] = ETHER_FLAG_OFF; + mpd_flag[channel_index] = ETHER_FLAG_OFF; + lchng_flag[channel_index] = ETHER_FLAG_OFF; +#if (ETHER_CFG_USE_LINKSTA == 0) + g_pre_link_stat[channel_index] = ETHER_ERR_OTHER; +#endif + + return ETHER_SUCCESS; +} /* End of function R_ETHER_Close_ZC2() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Read_ZC2 + * Description : Receives an Ethernet frame. Sets the passed + * buffer pointer to the Ethernet frame buffer + * from the driver. This makes the data available to + * the caller as a zero-copy operation. + * Arguments : channel - + * ETHERC channel number + * pbuf - + * Pointer to buffer that holds the receive data + * Return Value : Returns the number of bytes received. + * ETHER_NO_DATA - + * A zero value indicates no data is received. + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_INVALID_PTR - + * Value of the pointer is NULL + * ETHER_ERR_LINK - + * Auto-negotiation is not completed, and reception is not enabled. + * ETHER_ERR_MPDE - + * As a Magic Packet is being detected, transmission and reception is not enabled. + * ETHER_ERR_MC_FRAME - + * Multicast Frame filter is enable, and Multicast Address Frame is received. + ***********************************************************************************************************************/ +int32_t R_ETHER_Read_ZC2 (uint32_t channel, void **pbuf) +{ + int32_t num_recvd; + int32_t ret; + int32_t complete_flag; + int32_t ret2; + descriptor_t * p_rx_desc; + uint32_t channel_index = get_control_tbl_index(channel); + + p_rx_desc = papp_rx_desc[channel_index]; + + if (NULL == p_rx_desc) { + return ETHER_ERR_INVALID_CHAN; + } + if (NULL == pbuf) { + return ETHER_ERR_INVALID_PTR; + } + + /* When the Link up processing is not completed, return error */ + if (ETHER_FLAG_OFF == transfer_enable_flag[channel_index]) { + return ETHER_ERR_LINK; + } + + /* In case of detection mode of magic packet, return error. */ + if (1 == check_mpde_bit()) { + return ETHER_ERR_MPDE; + } + + /* When the Link up processing is completed */ + ret = ETHER_NO_DATA; + complete_flag = ETHER_ERR_OTHER; + while (ETHER_SUCCESS != complete_flag) { + /* When receive data exists. */ + if (RACT != (p_rx_desc->status & RACT)) { + /* Check multicast is detected when multicast frame filter is enabled */ + if (ETHER_MC_FILTER_ON == mc_filter_flag[channel_index]) { + if (RFS7_RMAF == (p_rx_desc->status & RFS7_RMAF)) { + /* The buffer is released at the multicast frame detect. */ + ret2 = R_ETHER_Read_ZC2_BufRelease(channel); + if (ETHER_SUCCESS != ret2) { + return ret2; + } + + ret = ETHER_ERR_MC_FRAME; + complete_flag = ETHER_SUCCESS; + } + } + + if (ETHER_ERR_MC_FRAME != ret) { + if (RFE == (p_rx_desc->status & RFE)) { + /* The buffer is released at the error. */ + ret2 = R_ETHER_Read_ZC2_BufRelease(channel); + if (ETHER_SUCCESS != ret2) { + return ret2; + } + } else { + /** + * Pass the pointer to received data to application. This is + * zero-copy operation. + */ +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) + (*pbuf) = (void *)(((uint32_t) p_rx_desc->buf_p) + ether_mmu_uncached_diff); +#else + (*pbuf) = (void *) p_rx_desc->buf_p; +#endif + + /* Get bytes received */ + num_recvd = p_rx_desc->size; + ret = num_recvd; + complete_flag = ETHER_SUCCESS; + } + } + } else { + ret = ETHER_NO_DATA; + complete_flag = ETHER_SUCCESS; + } + } + + return ret; +} /* End of function R_ETHER_Read_ZC2() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Read_ZC2_BufRelease + * Description : Release the receive buffer. + * Arguments : channel - + * Specifies the ETHERC channel number. + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_LINK - + * Auto-negotiation is not completed, and reception is not enabled. + * ETHER_ERR_MPDE - + * As a Magic Packet is being detected, transmission and reception is not enabled. + ***********************************************************************************************************************/ +int32_t R_ETHER_Read_ZC2_BufRelease (uint32_t channel) +{ + volatile struct st_edmac * pedmac_adr; + uint32_t status; + descriptor_t * p_rx_desc; + uint32_t channel_index = get_control_tbl_index(channel); + + p_rx_desc = papp_rx_desc[channel_index]; + + if (NULL == p_rx_desc) { + return ETHER_ERR_INVALID_CHAN; + } + + /* When the Link up processing is not completed, return error */ + if (ETHER_FLAG_OFF == transfer_enable_flag[channel_index]) { + return ETHER_ERR_LINK; + } + + /* In case of detection mode of magic packet, return error. */ + if (1 == check_mpde_bit()) { + return ETHER_ERR_MPDE; + } + + /* When the Link up processing is completed */ + /* When receive data exists */ + if (RACT != (p_rx_desc->status & RACT)) { + /* Move to next descriptor */ + p_rx_desc->status |= RACT; + + status = RFP1; + status |= RFP0; + status |= RFE; + status |= RFS9_RFOVER; + status |= RFS8_RAD; + status |= RFS7_RMAF; + status |= RFS4_RRF; + status |= RFS3_RTLF; + status |= RFS2_RTSF; + status |= RFS1_PRE; + status |= RFS0_CERF; + + papp_rx_desc[channel_index]->status &= (~status); + papp_rx_desc[channel_index] = papp_rx_desc[channel_index]->next; + } + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + + if (0x00000000L == pedmac_adr->EDRRR.LONG) { + /* Restart if stopped */ + pedmac_adr->EDRRR.LONG = 0x00000001L; + } + + return ETHER_SUCCESS; +} /* End of function R_ETHER_Read_ZC2_BufRelease() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Write_ZC2_GetBuf + * Description : Get Points to the buffer pointer used by the stack. + * Arguments : channel - + * ETHERC channel number + * pbuf - + * Pointer to the starting address of the transmit data destination + * pbuf_size - + * The Maximum size to write to the buffer + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_INVALID_PTR - + * Value of the pointer is NULL + * ETHER_ERR_LINK - + * Auto-negotiation is not completed, and reception is not enabled. + * ETHER_ERR_MPDE - + * As a Magic Packet is being detected, transmission and reception is not enabled. + * ETHER_ERR_TACT - + * Transmit buffer is not empty. + ***********************************************************************************************************************/ +ether_return_t R_ETHER_Write_ZC2_GetBuf (uint32_t channel, void **pbuf, uint16_t *pbuf_size) +{ + /* Check argument */ + descriptor_t* p_tx_desc; + uint32_t channel_index = get_control_tbl_index(channel); + + p_tx_desc = papp_tx_desc[channel_index]; + if (NULL == p_tx_desc) { + return ETHER_ERR_INVALID_CHAN; + } + if (NULL == pbuf) { + return ETHER_ERR_INVALID_PTR; + } + if (NULL == pbuf_size) { + return ETHER_ERR_INVALID_PTR; + } + + /* When the Link up processing is not completed, return error */ + if (ETHER_FLAG_OFF == transfer_enable_flag[channel_index]) { + return ETHER_ERR_LINK; + } + + /* In case of detection mode of magic packet, return error. */ + if (1 == check_mpde_bit()) { + return ETHER_ERR_MPDE; + } + + /* When the Link up processing is completed */ + /* All transmit buffers are full */ + if (TACT == (p_tx_desc->status & TACT)) { + return ETHER_ERR_TACT; + } + + /* Give application another buffer to work with */ +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) + (*pbuf) = (void*)((p_tx_desc->buf_p) + ether_mmu_uncached_diff); +#else + (*pbuf) = (void*) p_tx_desc->buf_p; +#endif + (*pbuf_size) = ETHER_CFG_BUFSIZE; + + return ETHER_SUCCESS; +} /* End of function R_ETHER_Write_ZC2_GetBuf() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Write_ZC2_SetBuf + * Description : Transmits an Ethernet frame. + * The transmit descriptor points to the data to transmit. + * Data is sent directly from memory as a "zero copy" operation. + * Arguments : channel - + * ETHERC channel number + * len - + * The size (60 to 1,514 bytes) which is the Ethernet frame length minus 4 bytes of CRC + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_INVALID_DATA - + * Value of the argument is out of range + * ETHER_ERR_LINK - + * Auto-negotiation is not completed, and reception is not enabled. + * ETHER_ERR_MPDE - + * As a Magic Packet is being detected, transmission and reception is not enabled. + ***********************************************************************************************************************/ +ether_return_t R_ETHER_Write_ZC2_SetBuf (uint32_t channel, const uint32_t len) +{ + volatile struct st_edmac * pedmac_adr; + descriptor_t* p_tx_desc; + uint32_t channel_index = get_control_tbl_index(channel); + + p_tx_desc = papp_tx_desc[channel_index]; + if (NULL == p_tx_desc) { + return ETHER_ERR_INVALID_CHAN; + } + if ((ETHER_BUFSIZE_MIN > len) || (ETHER_BUFSIZE_MAX < len)) { + return ETHER_ERR_INVALID_DATA; + } + + /* When the Link up processing is not completed, return error */ + if (ETHER_FLAG_OFF == transfer_enable_flag[channel_index]) { + return ETHER_ERR_LINK; + } + + /* In case of detection mode of magic packet, return error. */ + if (1 == check_mpde_bit()) { + return ETHER_ERR_MPDE; + } + + /* When the Link up processing is completed */ + /* The data of the buffer is made active. */ + p_tx_desc->bufsize = len; + p_tx_desc->status &= (~(TFP1 | TFP0)); + p_tx_desc->status |= ((TFP1 | TFP0) | TACT); + papp_tx_desc[channel_index] = p_tx_desc->next; + + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + + if (0x00000000L == pedmac_adr->EDTRR.LONG) { + /* Restart if stopped */ + pedmac_adr->EDTRR.LONG = 0x00000001L; + } + + return ETHER_SUCCESS; +} /* End of function R_ETHER_Write_ZC2_SetBuf() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_CheckLink_ZC + * Description : Verifies the Etherent link is up or not. + * Arguments : channel - + * ETHERC channel number + * Return Value : ETHER_SUCCESS - + * Link is up + * ETHER_ERR_OTHER - + * Link is down + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + ***********************************************************************************************************************/ +ether_return_t R_ETHER_CheckLink_ZC (uint32_t channel) +{ + if (R_PHY_ERROR == phy_get_link_status(channel)) { + /* Link is down */ + return ETHER_ERR_OTHER; + } + + /* Link is up */ + return ETHER_SUCCESS; +} /* End of function R_ETHER_CheckLink_ZC() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_LinkProcess + * Description : The Link up processing, the Link down processing, and the magic packet detection processing are + * executed. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +void R_ETHER_LinkProcess (uint32_t channel) +{ + volatile struct st_etherc * petherc_adr; + + int32_t ret; + ether_cb_arg_t cb_arg; + uint32_t channel_index = get_control_tbl_index(channel); + + /* When the magic packet is detected. */ + if (ETHER_FLAG_ON == mpd_flag[channel_index]) { + mpd_flag[channel_index] = ETHER_FLAG_OFF; + + if (NULL != cb_func.pcb_func) { + cb_arg.channel = channel; + cb_arg.event_id = ETHER_CB_EVENT_ID_WAKEON_LAN; + (*cb_func.pcb_func)((void *) &cb_arg); + } + + /* + * After the close function is called, the open function is called + * to have to set ETHERC to a usual operational mode + * to usually communicate after magic packet is detected. + */ + R_ETHER_Close_ZC2(channel); + R_ETHER_Open_ZC2(channel, mac_addr_buf[channel_index], pause_frame_enable[channel_index]); + } + +#if (ETHER_CFG_USE_LINKSTA == 0) + ret = R_ETHER_CheckLink_ZC(channel); + if (g_pre_link_stat[channel_index] != ret) { + if (ret == ETHER_SUCCESS) { + /* The state of the link status in PHY-LSI is confirmed and Link Up/Down is judged. */ + /* When becoming Link up */ + lchng_flag[channel_index] = ETHER_FLAG_ON_LINK_ON; + } else { + /* When becoming Link down */ + lchng_flag[channel_index] = ETHER_FLAG_ON_LINK_OFF; + } + } + g_pre_link_stat[channel_index] = ret; +#endif + + /* When the link is up */ + if (ETHER_FLAG_ON_LINK_ON == lchng_flag[channel_index]) { +#if (ETHER_CFG_USE_LINKSTA == 1) + /* + * The Link Up/Down is confirmed by the Link Status bit of PHY register1, + * because the LINK signal of PHY-LSI is used for LED indicator, and + * isn't used for notifing the Link Up/Down to external device. + */ + ret = R_ETHER_CheckLink_ZC(channel); + if (ETHER_SUCCESS == ret) { + /* + * The status of the LINK signal became "link-up" even if PHY-LSI did not detect "link-up" + * after a reset. To avoid this wrong detection, processing in R_ETHER_LinkProcess has been modified to + * clear the flag after link-up is confirmed in R_ETHER_CheckLink_ZC. + */ + lchng_flag[channel_index] = ETHER_FLAG_OFF; + + /* Initialize the transmit and receive descriptor */ + memset(&rx_descriptors[channel_index], 0x00, sizeof(rx_descriptors[channel_index])); + memset(&tx_descriptors[channel_index], 0x00, sizeof(tx_descriptors[channel_index])); + + /* Initialize the Ether buffer */ + memset(ðer_buffers[channel_index], 0x00, sizeof(ether_buffers[channel_index])); + + transfer_enable_flag[channel_index] = ETHER_FLAG_ON; + + /* + * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software + * and sending and receiving is permitted. + */ + ether_configure_mac(channel, mac_addr_buf[channel_index], NO_USE_MAGIC_PACKET_DETECT); + ret = ether_do_link(channel, NO_USE_MAGIC_PACKET_DETECT); + if (ETHER_SUCCESS == ret) { + if (NULL != cb_func.pcb_func) { + cb_arg.channel = channel; + cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_ON; + (*cb_func.pcb_func)((void *) &cb_arg); + } + } else { + /* When PHY auto-negotiation is not completed */ + transfer_enable_flag[channel_index] = ETHER_FLAG_OFF; + lchng_flag[channel_index] = ETHER_FLAG_ON_LINK_ON; + } + } else { + /* no process */ + } +#elif (ETHER_CFG_USE_LINKSTA == 0) + /* + * The status of the LINK signal became "link-up" even if PHY-LSI did not detect "link-up" + * after a reset. To avoid this wrong detection, processing in R_ETHER_LinkProcess has been modified to + * clear the flag after link-up is confirmed in R_ETHER_CheckLink_ZC. + */ + lchng_flag[channel_index] = ETHER_FLAG_OFF; + + /* Initialize the transmit and receive descriptor */ + memset(&rx_descriptors[channel_index], 0x00, sizeof(rx_descriptors[channel_index])); + memset(&tx_descriptors[channel_index], 0x00, sizeof(tx_descriptors[channel_index])); + + /* Initialize the Ether buffer */ + memset(ðer_buffers[channel_index], 0x00, sizeof(ether_buffers[channel_index])); + + transfer_enable_flag[channel_index] = ETHER_FLAG_ON; + + /* + * ETHERC and EDMAC are set after ETHERC and EDMAC are reset in software + * and sending and receiving is permitted. + */ + ether_configure_mac(channel, mac_addr_buf[channel_index], NO_USE_MAGIC_PACKET_DETECT); + ret = ether_do_link(channel, NO_USE_MAGIC_PACKET_DETECT); + if (ETHER_SUCCESS == ret) { + if (NULL != cb_func.pcb_func) { + cb_arg.channel = channel; + cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_ON; + (*cb_func.pcb_func)((void *) &cb_arg); + } + } else { + /* When PHY auto-negotiation is not completed */ + transfer_enable_flag[channel_index] = ETHER_FLAG_OFF; + lchng_flag[channel_index] = ETHER_FLAG_ON_LINK_ON; + } +#endif + } + + /* When the link is down */ + else if (ETHER_FLAG_ON_LINK_OFF == lchng_flag[channel_index]) { + lchng_flag[channel_index] = ETHER_FLAG_OFF; + +#if (ETHER_CFG_USE_LINKSTA == 1) + /* + * The Link Up/Down is confirmed by the Link Status bit of PHY register1, + * because the LINK signal of PHY-LSI is used for LED indicator, and + * isn't used for notifying the Link Up/Down to external device. + */ + ret = R_ETHER_CheckLink_ZC(channel); + if (ETHER_ERR_OTHER == ret) { + petherc_adr = g_eth_control_ch[channel_index].petherc; + + /* Disable receive and transmit. */ + petherc_adr->ECMR.BIT.RE = 0; + petherc_adr->ECMR.BIT.TE = 0; + + transfer_enable_flag[channel_index] = ETHER_FLAG_OFF; + + if (NULL != cb_func.pcb_func) { + cb_arg.channel = channel; + cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_OFF; + (*cb_func.pcb_func)((void *) &cb_arg); + } + } +#elif (ETHER_CFG_USE_LINKSTA == 0) + petherc_adr = g_eth_control_ch[channel_index].petherc; + + /* Disable receive and transmit. */ + petherc_adr->ECMR.BIT.RE = 0; + petherc_adr->ECMR.BIT.TE = 0; + + transfer_enable_flag[channel_index] = ETHER_FLAG_OFF; + + if (NULL != cb_func.pcb_func) { + cb_arg.channel = channel; + cb_arg.event_id = ETHER_CB_EVENT_ID_LINK_OFF; + (*cb_func.pcb_func)((void *) &cb_arg); + } +#endif + } else { + /* Do Nothing */ + } +} /* End of function R_ETHER_LinkProcess() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_WakeOnLAN + * Description : The setting of ETHERC is changed from a usual sending and + * receiving mode to the magic packet detection mode. + * Arguments : channel - + * ETHERC channel number + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_LINK - + * Auto-negotiation is not completed, and reception is not enabled. + * ETHER_ERR_OTHER - + * A switch to magic packet detection was performed when the link state was link is down. + ***********************************************************************************************************************/ +ether_return_t R_ETHER_WakeOnLAN (uint32_t channel) +{ +#if (ETHER_CFG_USE_LINKSTA == 1) + volatile struct st_etherc * petherc_adr; +#endif + ether_return_t ret; + uint32_t channel_index = get_control_tbl_index(channel); + + /* When the Link up processing is not completed, return error */ + if (ETHER_FLAG_OFF == transfer_enable_flag[channel_index]) { + return ETHER_ERR_LINK; + } + + /* When the Link up processing is completed */ + /* Change to the magic packet detection mode. */ + ether_configure_mac(channel, mac_addr_buf[channel_index], USE_MAGIC_PACKET_DETECT); + ret = ether_do_link(channel, USE_MAGIC_PACKET_DETECT); + if (ETHER_SUCCESS == ret) { +#if (ETHER_CFG_USE_LINKSTA == 1) + petherc_adr = g_eth_control_ch[channel_index].petherc; + + /* It is confirmed not to become Link down while changing the setting. */ + if (ETHER_CFG_LINK_PRESENT == petherc_adr->PSR.BIT.LMON) { + ret = ETHER_SUCCESS; + } else { + ret = ETHER_ERR_OTHER; + } +#else + /* It is confirmed not to become Link down while changing the setting. */ + ret = R_ETHER_CheckLink_ZC(channel); +#endif + } else { + ret = ETHER_ERR_OTHER; + } + + return ret; +} /* End of function R_ETHER_WakeOnLAN() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Read + * Description : Receive Ethernet frame. Receives data to the location specified by the pointer to the receive buffer, + * using non-zero-copy communication. + * Arguments : channel - + * ETHERC channel number + * pbuf - + * The receive buffer (to store the receive data) + * Return Value : Returns the number of bytes received. + * ETHER_NO_DATA - + * A zero value indicates no data is received. + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_INVALID_PTR - + * Value of the pointer is NULL + * ETHER_ERR_LINK - + * Auto-negotiation is not completed, and reception is not enabled. + * ETHER_ERR_MPDE - + * As a Magic Packet is being detected, transmission and reception is not enabled. + * ETHER_ERR_MC_FRAME - + * Multicast Frame filter is enable, and Multicast Address Frame is received. + ***********************************************************************************************************************/ +int32_t R_ETHER_Read (uint32_t channel, void *pbuf) +{ + int32_t ret; + int32_t ret2; + uint8_t * pread_buffer_address; /* Buffer location controlled by the Ethernet driver */ + + /* Check argument */ + if (NULL == pbuf) { + return ETHER_ERR_INVALID_PTR; + } + + /* (1) Retrieve the receive buffer location controlled by the descriptor. */ + ret = R_ETHER_Read_ZC2(channel, (void **) &pread_buffer_address); + + /* When there is data to receive */ + if (ret > ETHER_NO_DATA) { + /* (2) Copy the data read from the receive buffer which is controlled by the descriptor to + the buffer which is specified by the user (up to 1024 bytes). */ + memcpy(pbuf, pread_buffer_address, (uint32_t )ret); + + /* (3) Read the receive data from the receive buffer controlled by the descriptor, + and then release the receive buffer. */ + ret2 = R_ETHER_Read_ZC2_BufRelease(channel); + if (ETHER_SUCCESS == ret2) { /* When this function is completed successfully */ + /* Do Nothing */ + } + + /* Overwrite the error information */ + else { + ret = ret2; + } + } + + /* When there is no data to receive */ + else { + /* Do Nothing */ + } + + return ret; +} /* End of function R_ETHER_Read() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Write + * Description : Transmit Ethernet frame. Transmits data from the location specified by the pointer to the transmit + * buffer, with the data size equal to the specified frame length, using non-zero-copy communication. + * Arguments : channel - + * ETHERC channel number + * : *pbuf - + * Transmit buffer pointer + * : len - + * The size (60 to 1,514 bytes) which is the Ethernet frame length minus 4 bytes of CRC + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_INVALID_DATA - + * Value of the argument is out of range + * ETHER_ERR_INVALID_PTR - + * Value of the pointer is NULL + * ETHER_ERR_LINK - + * Auto-negotiation is not completed, and reception is not enabled. + * ETHER_ERR_MPDE - + * As a Magic Packet is being detected, transmission and reception is not enabled. + * ETHER_ERR_TACT - + * Transmit buffer is not empty. + ***********************************************************************************************************************/ +ether_return_t R_ETHER_Write (uint32_t channel, void *pbuf, const uint32_t len) +{ + ether_return_t ret; + uint8_t * pwrite_buffer_address; + uint16_t write_buf_size; + + if (NULL == pbuf) { + return ETHER_ERR_INVALID_PTR; + } + if ((ETHER_BUFSIZE_MIN > len) || (ETHER_BUFSIZE_MAX < len)) { + return ETHER_ERR_INVALID_DATA; + } + + /* (1) Retrieve the transmit buffer location controlled by the descriptor. */ + ret = R_ETHER_Write_ZC2_GetBuf(channel, (void **) &pwrite_buffer_address, &write_buf_size); + + /* Writing to the transmit buffer (buf) is enabled. */ + if (ETHER_SUCCESS == ret) { + if (write_buf_size < len) { + ret = ETHER_ERR_TACT; /* Transmit buffer overflow */ + } else { + /* Write the transmit data to the transmit buffer. */ + + /* (2) Write the data to the transmit buffer controlled by the descriptor. */ + memcpy(pwrite_buffer_address, pbuf, len); + + /* (3) Enable the EDMAC to transmit data in the transmit buffer. */ + ret = R_ETHER_Write_ZC2_SetBuf(channel, len); + + /* + * Confirm that the transmission is completed. + * Data written in the transmit buffer is transmitted by the EDMAC. Make sure that the + * transmission is completed after writing data to the transmit buffer. + * If the R_ETHER_Close_ZC2 function is called to stop the Ethernet communication before + * verifying that the transmission is completed, the written data written may not be transmitted. + */ + ret = R_ETHER_CheckWrite(channel); + } + } + + return ret; +} /* End of function R_ETHER_Write() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_CheckWrite + * Description : Checking that the data has been sent. + * Arguments : channel - + * ETHERC channel number + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + ***********************************************************************************************************************/ +ether_return_t R_ETHER_CheckWrite (uint32_t channel) +{ + volatile struct st_edmac * pedmac_adr; + uint32_t channel_index = get_control_tbl_index(channel); + + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + while (0 != pedmac_adr->EDTRR.BIT.TR) { + /* Do Nothing */ + } + + return ETHER_SUCCESS; +} /* End of function R_ETHER_CheckWrite() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_Control + * Description : By command argument is a function to change the settings of Ether driver. + * Arguments : cmd - + * Control code + * control - + * Parameters according to the control code + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_CHAN_OPEN - + * Indicates the Ethernet cannot be opened because it is being used by another application + * ETHER_ERR_INVALID_ARG - + * Invalid argument + * ETHER_ERR_RECV_ENABLE - + * Receive function is enable. + ***********************************************************************************************************************/ +ether_return_t R_ETHER_Control (ether_cmd_t const cmd, ether_param_t const control) +{ + ether_return_t ret; + + switch (cmd) { + /* Set the callback function pointer */ + case CONTROL_SET_CALLBACK : + ret = ether_set_callback(control); + break; + + case CONTROL_SET_PROMISCUOUS_MODE : + ret = ether_set_promiscuous_mode(control); + break; + + case CONTROL_SET_INT_HANDLER : + ret = ether_set_int_handler(control); + break; + + case CONTROL_POWER_ON : + ret = ether_power_on(control); + break; + + case CONTROL_POWER_OFF : + ret = ether_power_off(control); + break; + + case CONTROL_MULTICASTFRAME_FILTER : + ret = ether_set_multicastframe_filter(control); + break; + + case CONTROL_BROADCASTFRAME_FILTER : + ret = ether_set_broadcastframe_filter(control); + break; + + /* Commands not supported */ + default : + ret = ETHER_ERR_INVALID_ARG; + break; + } + + return ret; +} /* End of function R_ETHER_Control() */ + +/*********************************************************************************************************************** + * Function Name: R_ETHER_GetVersion + * Description : Returns this module's version information. + * The version number is encoded where the top 2 bytes are the major version number and the bottom 2 bytes + * are the minor version number. For example, Version 4.25 would be returned as 0x00040019. + * Arguments : none + * Return Value : Version number + ***********************************************************************************************************************/ +//#pragma inline(R_ETHER_GetVersion) +uint32_t R_ETHER_GetVersion (void) +{ + return ((((uint32_t) ETHER_RZA2_VERSION_MAJOR) << 16) | ((uint32_t) ETHER_RZA2_VERSION_MINOR)); +} /* End of function R_ETHER_GetVersion() */ + +/* + * Private functions + */ + +/*********************************************************************************************************************** + * Function Name: ether_reset_mac + * Description : The EDMAC and EtherC are reset through the software reset. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_reset_mac (uint32_t channel) +{ + volatile uint32_t i; + + /* Software reset */ + if (ETHER_CHANNEL_0 == channel) { + EDMAC0.EDMR.BIT.SWR = 1; + } else { + EDMAC1.EDMR.BIT.SWR = 1; + } + + /* + * Waiting time until the initialization of ETHERC and EDMAC is completed is 64 cycles + * in the clock conversion of an internal bus of EDMAC. + */ + for (i = 0; i < 0x00001180; i++) { + ; + } + +} /* End of function ether_reset_mac() */ + +/*********************************************************************************************************************** + * Function Name: ether_init_descriptors + * Description : The EDMAC descriptors and the driver buffers are initialized. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_init_descriptors (uint32_t channel) +{ + descriptor_t * pdescriptor; + uint32_t i; + uint32_t channel_index = get_control_tbl_index(channel); + + /* Initialize the receive descriptors */ + for (i = 0; i < ETHER_CFG_EMAC_RX_DESCRIPTORS; i++) { + pdescriptor = (descriptor_t *) &rx_descriptors[channel_index][i]; +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) + pdescriptor->buf_p = (uint8_t *) ether_mmu_VAtoPA((uint32_t)&(ether_buffers[channel_index].buffer[i][0])); +#else + pdescriptor->buf_p = (uint8_t *) &(ether_buffers[channel_index].buffer[i][0]); +#endif + pdescriptor->bufsize = ETHER_CFG_BUFSIZE; + pdescriptor->size = 0; + pdescriptor->status = RACT; + pdescriptor->next = (descriptor_t *) &rx_descriptors[channel_index][(i + 1)]; + } + + /* The last descriptor points back to the start */ + pdescriptor->status |= RDLE; + pdescriptor->next = (descriptor_t *) &rx_descriptors[channel_index][0]; + + /* Initialize application receive descriptor pointer */ + papp_rx_desc[channel_index] = (descriptor_t *) &rx_descriptors[channel_index][0]; + + /* Initialize the transmit descriptors */ + for (i = 0; i < ETHER_CFG_EMAC_TX_DESCRIPTORS; i++) { + pdescriptor = (descriptor_t *) &tx_descriptors[channel_index][i]; +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) + pdescriptor->buf_p = (uint8_t *) ether_mmu_VAtoPA((uint32_t)&(ether_buffers[channel_index].buffer[(ETHER_CFG_EMAC_RX_DESCRIPTORS + i)][0])); +#else + pdescriptor->buf_p = (uint8_t *) &(ether_buffers[channel_index].buffer[(ETHER_CFG_EMAC_RX_DESCRIPTORS + i)][0]); +#endif + pdescriptor->bufsize = 1; /* Set a value equal to or greater than 1. (reference to UMH) + When transmitting data, the value of size is set to the function argument + R_ETHER_Write_ZC2_SetBuf. */ + pdescriptor->size = 0; /* Reserved : The write value should be 0. (reference to UMH) */ + pdescriptor->status = 0; + pdescriptor->next = (descriptor_t *) &(tx_descriptors[channel_index][(i + 1)]); + } + + /* The last descriptor points back to the start */ + pdescriptor->status |= TDLE; + pdescriptor->next = (descriptor_t *) &tx_descriptors[channel_index][0]; + + /* Initialize application transmit descriptor pointer */ + papp_tx_desc[channel_index] = (descriptor_t *) &tx_descriptors[channel_index][0]; +} /* End of function ether_init_descriptors() */ + +/*********************************************************************************************************************** + * Function Name: ether_config_ethernet + * Description : Configure the Ethernet Controller (EtherC) and the Ethernet + * Direct Memory Access controller (EDMAC). + * Arguments : channel - + * ETHERC channel number + * mode - + * The operational mode is specified. + * NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually + * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode + * Return Value : none + ***********************************************************************************************************************/ +static void ether_config_ethernet (uint32_t channel, const uint8_t mode) +{ + volatile struct st_etherc * petherc_adr; + volatile struct st_edmac * pedmac_adr; + uint32_t channel_index = get_control_tbl_index(channel); + + petherc_adr = g_eth_control_ch[channel_index].petherc; + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + + /* Magic packet detection mode */ + if (USE_MAGIC_PACKET_DETECT == mode) { +#if (ETHER_CFG_USE_LINKSTA == 1) + petherc_adr->ECSIPR.LONG = 0x00000006; +#elif (ETHER_CFG_USE_LINKSTA == 0) + petherc_adr->ECSIPR.LONG = 0x00000002; +#endif + pedmac_adr->EESIPR.LONG = 0x00400000; + } + + /* Normal mode */ + else { +#if (ETHER_CFG_USE_LINKSTA == 1) + /* LINK Signal Change Interrupt Enable */ + petherc_adr->ECSR.BIT.LCHNG = 1; + petherc_adr->ECSIPR.BIT.LCHNGIP = 1; +#endif + pedmac_adr->EESIPR.BIT.ECIIP = 1; + + /* Frame receive interrupt and frame transmit end interrupt */ + pedmac_adr->EESIPR.BIT.FRIP = 1; /* Enable the frame receive interrupt. */ + pedmac_adr->EESIPR.BIT.TCIP = 1; /* Enable the frame transmit end interrupt. */ + } + + /* Ethernet length 1514bytes + CRC and intergap is 96-bit time */ + petherc_adr->RFLR.LONG = 1518; + petherc_adr->IPGR.LONG = 0x00000014; + + /* Continuous reception number of Broadcast frame */ + petherc_adr->BCFRR.LONG = bc_filter_count[channel_index]; + + /* Set little endian mode */ + /* Ethernet length 1514bytes + CRC and intergap is 96-bit time */ + pedmac_adr->EDMR.BIT.DE = 1; + + /* Initialize Rx descriptor list address */ + /* Casting the pointer to a uint32_t type is valid because the Renesas Compiler uses 4 bytes per pointer. */ +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) + pedmac_adr->RDLAR.LONG = ether_mmu_VAtoPA((uint32_t)papp_rx_desc[channel_index]); +#else + pedmac_adr->RDLAR.LONG = (uint32_t)papp_rx_desc[channel_index]; +#endif + + /* Initialize Tx descriptor list address */ + /* Casting the pointer to a uint32_t type is valid because the Renesas Compiler uses 4 bytes per pointer. */ +#if (ETHER_CFG_USE_VIRTUAL_ADDRESS) + pedmac_adr->TDLAR.LONG = ether_mmu_VAtoPA((uint32_t)papp_tx_desc[channel_index]); +#else + pedmac_adr->TDLAR.LONG = (uint32_t)papp_tx_desc[channel_index]; +#endif + + if (ETHER_MC_FILTER_ON == mc_filter_flag[channel_index]) { + /* Reflect the EESR.RMAF bit status in the RD0.RFS bit in the receive descriptor */ + pedmac_adr->TRSCER.LONG = 0x00000000; + } else { + /* Don't reflect the EESR.RMAF bit status in the RD0.RFS bit in the receive descriptor */ + pedmac_adr->TRSCER.LONG = 0x00000080; + } + + /* Threshold of Tx_FIFO */ + /* To prevent a transmit underflow, setting the initial value (store and forward modes) is recommended. */ + pedmac_adr->TFTR.LONG = 0x00000000; + + /* transmit fifo is 2048 bytes, receive fifo is 4096 bytes */ + pedmac_adr->FDR.LONG = 0x0000070F; + + /* Configure receiving method + b0 RNR - Receive Request Bit Reset - Continuous reception of multiple frames is possible. + b31:b1 Reserved set to 0 + */ + pedmac_adr->RMCR.LONG = 0x00000001; + +} /* End of function ether_config_ethernet() */ + +/*********************************************************************************************************************** + * Function Name: ether_pause_resolution + * Description : Determines PAUSE frame generation and handling. Uses + * the resolution Table 28B-3 of IEEE 802.3-2008. + * Arguments : local_ability - + * local PAUSE capability (2 least significant bits) + * partner_ability - + * link partner PAUSE capability (2 least significant bits) + * *ptx_pause - + * pointer to location to store the result of the table lookup for transmit + * PAUSE. 1 is enable, 0 is disable. + * *prx_pause - + * pointer to location to store the result of the table lookup for receive + * PAUSE. 1 is enable, 0 is disable. + * Return Value : none + ***********************************************************************************************************************/ +static void ether_pause_resolution (uint16_t local_ability, uint16_t partner_ability, uint16_t *ptx_pause, + uint16_t *prx_pause) +{ + uint32_t i; + uint32_t ability_compare; + + /* + * Arrange the bits so that they correspond to the Table 28B-3 + * of the IEEE 802.3 values. + */ + ability_compare = (uint32_t) (((local_ability & LINK_RES_ABILITY_MASK) << LINK_RES_LOCAL_ABILITY_BITSHIFT) + | (partner_ability & LINK_RES_ABILITY_MASK)); + + /* Walk through the look up table */ + for (i = 0; i < PAUSE_TABLE_ENTRIES; i++) { + if ((ability_compare & pause_resolution[i].mask) == pause_resolution[i].value) { + (*ptx_pause) = pause_resolution[i].transmit; + (*prx_pause) = pause_resolution[i].receive; + return; + } + } +} /* End of function ether_pause_resolution() */ + +/*********************************************************************************************************************** + * Function Name: ether_configure_mac + * Description : Software reset is executed, and ETHERC and EDMAC are configured. + * Arguments : channel - + * ETHERC channel number + * mac_addr - + * The MAC address of ETHERC + * mode - + * The operational mode is specified. + * NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually + * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode + * Return Value : none + ***********************************************************************************************************************/ +static void ether_configure_mac (uint32_t channel, const uint8_t mac_addr[], const uint8_t mode) +{ + uint32_t mac_h; + uint32_t mac_l; + volatile struct st_etherc * petherc_adr; + uint32_t channel_index = get_control_tbl_index(channel); + + petherc_adr = g_eth_control_ch[channel_index].petherc; + + /* Software reset */ + ether_reset_mac(channel); + + /* Set MAC address */ + mac_h = (((((uint32_t) mac_addr[0] << 24) | ((uint32_t) mac_addr[1] << 16)) | ((uint32_t) mac_addr[2] << 8)) + | (uint32_t) mac_addr[3]); + + mac_l = (((uint32_t) mac_addr[4] << 8) | (uint32_t) mac_addr[5]); + + petherc_adr->MAHR.LONG = mac_h; + petherc_adr->MALR.LONG = mac_l; + + /* Initialize receive and transmit descriptors */ + ether_init_descriptors(channel); + + /* Perform reset of hardware interface configuration */ + ether_config_ethernet(channel, mode); + +} /* End of function ether_configure_mac() */ + +/*********************************************************************************************************************** + * Function Name: ether_do_link + * Description : Determines the partner PHY capability through + * auto-negotiation process. The link abilities + * are handled to determine duplex, speed and flow + * control (PAUSE frames). + * Arguments : channel - + * ETHERC channel number + * mode - + * The operational mode is specified. + * NO_USE_MAGIC_PACKET_DETECT (0) - Communicate mode usually + * USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_OTHER - + * Auto-negotiation of PHY-LSI is not completed or result of Auto-negotiation is abnormal. + ***********************************************************************************************************************/ +static ether_return_t ether_do_link (uint32_t channel, const uint8_t mode) +{ + ether_return_t ret; + uint16_t link_speed_duplex = 0; + uint16_t local_pause_bits = 0; + uint16_t partner_pause_bits = 0; + uint16_t transmit_pause_set = 0; + uint16_t receive_pause_set = 0; + uint16_t full_duplex = 0; + uint16_t link_result = 0; + volatile struct st_etherc * petherc_adr; + volatile struct st_edmac * pedmac_adr; + uint32_t channel_index = get_control_tbl_index(channel); + + petherc_adr = g_eth_control_ch[channel_index].petherc; + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + + /* Set the link status */ + link_result = phy_set_autonegotiate(channel, &link_speed_duplex, &local_pause_bits, &partner_pause_bits); + + if (R_PHY_OK == link_result) { + switch (link_speed_duplex) { + /* Half duplex link */ + case PHY_LINK_100H : + petherc_adr->ECMR.BIT.DM = 0; + petherc_adr->ECMR.BIT.RTM = 1; + ret = ETHER_SUCCESS; + break; + + case PHY_LINK_10H : + petherc_adr->ECMR.BIT.DM = 0; + petherc_adr->ECMR.BIT.RTM = 0; + ret = ETHER_SUCCESS; + break; + + /* Full duplex link */ + case PHY_LINK_100F : + petherc_adr->ECMR.BIT.DM = 1; + petherc_adr->ECMR.BIT.RTM = 1; + full_duplex = 1; + ret = ETHER_SUCCESS; + break; + + case PHY_LINK_10F : + petherc_adr->ECMR.BIT.DM = 1; + petherc_adr->ECMR.BIT.RTM = 0; + full_duplex = 1; + ret = ETHER_SUCCESS; + break; + + default : + ret = ETHER_ERR_OTHER; + break; + } + + /* At the communicate mode usually */ + if (ETHER_SUCCESS == ret) { + if (NO_USE_MAGIC_PACKET_DETECT == mode) { + + /* When pause frame is used */ + if ((full_duplex) && (ETHER_FLAG_ON == pause_frame_enable[channel_index])) { + /* Set automatic PAUSE for 512 bit-time */ + petherc_adr->APR.LONG = 0x0000FFFF; + + /* Set unlimited retransmit of PAUSE frames */ + petherc_adr->TPAUSER.LONG = 0; + + /* PAUSE flow control FIFO settings. */ + pedmac_adr->FCFTR.LONG = 0x00000000; + + /* Control of a PAUSE frame whose TIME parameter value is 0 is enabled. */ + petherc_adr->ECMR.BIT.ZPF = 1; + + /** + * Enable PAUSE for full duplex link depending on + * the pause resolution results + */ + ether_pause_resolution(local_pause_bits, partner_pause_bits, &transmit_pause_set, + &receive_pause_set); + + if (XMIT_PAUSE_ON == transmit_pause_set) { + /* Enable automatic PAUSE frame transmission */ + petherc_adr->ECMR.BIT.TXF = 1; + } else { + /* Disable automatic PAUSE frame transmission */ + petherc_adr->ECMR.BIT.TXF = 0; + } + + if (RECV_PAUSE_ON == receive_pause_set) { + /* Enable reception of PAUSE frames */ + petherc_adr->ECMR.BIT.RXF = 1; + } else { + /* Disable reception of PAUSE frames */ + petherc_adr->ECMR.BIT.RXF = 0; + } + } + + /* When pause frame is not used */ + else { + /* Disable PAUSE for half duplex link */ + petherc_adr->ECMR.BIT.TXF = 0; + petherc_adr->ECMR.BIT.RXF = 0; + } + + /* Set the promiscuous mode bit */ + petherc_adr->ECMR.BIT.PRM = promiscuous_mode[channel_index]; + + /* Enable receive and transmit. */ + petherc_adr->ECMR.BIT.RE = 1; + petherc_adr->ECMR.BIT.TE = 1; + + /* Enable EDMAC receive */ + pedmac_adr->EDRRR.LONG = 0x1; + } + + /* At the magic packet detection mode */ + else { + /* The magic packet detection is permitted. */ + petherc_adr->ECMR.BIT.MPDE = 1; + + /* Because data is not transmitted for the magic packet detection waiting, + only the reception is permitted. */ + petherc_adr->ECMR.BIT.RE = 1; + + /* + * The reception function of EDMAC keep invalidity + * because the receive data don't need to be read when the magic packet detection mode. + */ + } + } + } else { + ret = ETHER_ERR_OTHER; + } + + return ret; +} /* End of function ether_do_link() */ + +/*********************************************************************************************************************** + * Function Name: ether_set_callback + * Description : Set the callback function + * Arguments : control - + * Callback function pointer. + * If you would rather poll for finish then please input NULL for this argument. + * Return Value : ETHER_SUCCESS + * Processing completed successfully + ***********************************************************************************************************************/ +static ether_return_t ether_set_callback (ether_param_t const control) +{ + void (*pcb_func) (void *); + + pcb_func = control.ether_callback.pcb_func; + + /* Check callback function pointer */ + if (NULL != pcb_func) { + cb_func.pcb_func = pcb_func; /* Set the callback function */ + } + + return ETHER_SUCCESS; +} /* End of function ether_set_callback() */ + +/*********************************************************************************************************************** + * Function Name: ether_set_promiscuous_mode + * Description : Set promiscuous mode bit + * Arguments : control - + * Promiscuous mode bit + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + ***********************************************************************************************************************/ +static ether_return_t ether_set_promiscuous_mode (ether_param_t const control) +{ + ether_promiscuous_t * p_arg; + uint32_t channel_index = get_control_tbl_index((uint32_t)control.channel); + + p_arg = control.p_ether_promiscuous; + + promiscuous_mode[channel_index] = p_arg->bit; + + return ETHER_SUCCESS; +} /* End of function ether_set_promiscuous_mode() */ + +/*********************************************************************************************************************** + * Function Name: ether_set_int_handler + * Description : Set the interrupt handler + * Arguments : control - + * Interrupt handler pointer. + * If you would rather poll for finish then please input NULL for this argument. + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_ARG - + * Invalid argument + ***********************************************************************************************************************/ +static ether_return_t ether_set_int_handler (ether_param_t const control) +{ + void (*pcb_int_hnd) (void *); + ether_return_t ret = ETHER_ERR_INVALID_ARG; + + pcb_int_hnd = control.ether_int_hnd.pcb_int_hnd; + if (NULL != pcb_int_hnd) { + cb_func.pcb_int_hnd = pcb_int_hnd; + ret = ETHER_SUCCESS; + } + return ret; +} /* End of function ether_set_int_handler() */ + +/*********************************************************************************************************************** + * Function Name: ether_power_on + * Description : Turns on power to a ETHER channel. + * Arguments : control - + * Ethernet channel number + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_CHAN_OPEN - + * Indicates the Ethernet cannot be opened because it is being used by another application + * ETHER_ERR_INVALID_ARG - + * Invalid argument + ***********************************************************************************************************************/ +static ether_return_t ether_power_on (ether_param_t const control) +{ + uint32_t channel_index = get_control_tbl_index((uint32_t)control.channel); + + /* Set port connect */ + ether_set_phy_mode(g_eth_control_ch[channel_index].port_connect); + + /* ETHERC/EDMAC Power on */ + return power_on_control((uint32_t)control.channel); +} /* End of function ether_power_on() */ + +/*********************************************************************************************************************** + * Function Name: ether_power_off + * Description : Turns on power to a ETHER channel. + * Arguments : control - + * Ethernet channel number + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_ARG - + * Invalid argument + ***********************************************************************************************************************/ +static ether_return_t ether_power_off (ether_param_t const control) +{ + /* ETHERC/EDMAC Power off */ + power_off_control((uint32_t)control.channel); + + return ETHER_SUCCESS; +} /* End of function ether_power_off() */ + +/*********************************************************************************************************************** + * Function Name: power_on + * Description : Turns on power to a ETHER channel. + * Arguments : channel - + * ETHERC channel number + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_CHAN_OPEN - + * Indicates the Ethernet cannot be opened because it is being used by another application + ***********************************************************************************************************************/ +static ether_return_t power_on (uint32_t channel) +{ + volatile uint8_t dummy; + +#if (ETHER_CHANNEL_MAX == 1) + (void)channel; + #if (ETHER_CH0_EN == 1) + CPG.STBCR6.BIT.MSTP65 = 0; + CPG.STBCR6.BIT.MSTP62 = 0; + dummy = CPG.STBCR6.BYTE; + #else + CPG.STBCR6.BIT.MSTP64 = 0; + CPG.STBCR6.BIT.MSTP62 = 0; + dummy = CPG.STBCR6.BYTE; + #endif +#else + /* Check argument */ + if (ETHER_CHANNEL_MAX <= channel) { + /* Should never get here. Valid channel number is checked above. */ + return ETHER_ERR_INVALID_CHAN; + } + + if (ETHER_CHANNEL_0 == channel) { + CPG.STBCR6.BIT.MSTP65 = 0; + CPG.STBCR6.BIT.MSTP62 = 0; + dummy = CPG.STBCR6.BYTE; + } else { + CPG.STBCR6.BIT.MSTP64 = 0; + CPG.STBCR6.BIT.MSTP62 = 0; + dummy = CPG.STBCR6.BYTE; + } +#endif + (void)dummy; + + return ETHER_SUCCESS; +} /* End of function power_on() */ + +/*********************************************************************************************************************** + * Function Name: power_off + * Description : Turns off power to a ETHER channel. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void power_off (uint32_t channel) +{ + volatile uint8_t dummy; + +#if (ETHER_CHANNEL_MAX == 1) + (void)channel; + #if (ETHER_CH0_EN == 1) + CPG.STBCR6.BIT.MSTP65 = 1; + dummy = CPG.STBCR6.BYTE; + CPG.STBCR6.BIT.MSTP62 = 1; + dummy = CPG.STBCR6.BYTE; + #else + CPG.STBCR6.BIT.MSTP64 = 1; + dummy = CPG.STBCR6.BYTE; + CPG.STBCR6.BIT.MSTP62 = 1; + dummy = CPG.STBCR6.BYTE; + #endif +#else + /* Check argument */ + if (ETHER_CHANNEL_MAX <= channel) { + /* Should never get here. Valid channel number is checked above. */ + return; + } + + if (ETHER_CHANNEL_0 == channel) { + CPG.STBCR6.BIT.MSTP65 = 1; + dummy = CPG.STBCR6.BYTE; + if (CPG.STBCR6.BIT.MSTP64 == 1) { + CPG.STBCR6.BIT.MSTP62 = 1; + dummy = CPG.STBCR6.BYTE; + } + } else { + CPG.STBCR6.BIT.MSTP64 = 1; + dummy = CPG.STBCR6.BYTE; + if (CPG.STBCR6.BIT.MSTP65 == 1) { + CPG.STBCR6.BIT.MSTP62 = 1; + dummy = CPG.STBCR6.BYTE; + } + } +#endif + (void)dummy; +} /* End of function power_off() */ + +/*********************************************************************************************************************** + * Function Name: ether_set_multicastframe_filter + * Description : set multicast frame filtering function. + * Arguments : control - + * Ethernet channel number and Multicast Frame filter enable switch + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_ARG - + * Invalid argument + * ETHER_ERR_RECV_ENABLE - + * Receive function is enable. + ***********************************************************************************************************************/ +static ether_return_t ether_set_multicastframe_filter (ether_param_t const control) +{ + ether_multicast_t * p_arg; + ether_mc_filter_t flag; + ether_return_t ret; + + volatile struct st_etherc * petherc_adr; + uint32_t channel_index = get_control_tbl_index((uint32_t)control.channel); + + ret = ETHER_ERR_INVALID_ARG; + p_arg = control.p_ether_multicast; + flag = p_arg->flag; + + if ((ETHER_MC_FILTER_ON != flag) && (ETHER_MC_FILTER_OFF != flag)) { + return ret; + } + + petherc_adr = g_eth_control_ch[channel_index].petherc; + + /* Check receive function is enable in ETHERC */ + if (0 == petherc_adr->ECMR.BIT.RE) { + if (ETHER_MC_FILTER_ON == flag) { + mc_filter_flag[channel_index] = ETHER_MC_FILTER_ON; + } else { + mc_filter_flag[channel_index] = ETHER_MC_FILTER_OFF; + } + + ret = ETHER_SUCCESS; + } else { + ret = ETHER_ERR_RECV_ENABLE; + } + + return ret; +} /* End of function ether_set_multicastframe_filter() */ + +/*********************************************************************************************************************** + * Function Name: ether_set_broadcastframe_filter + * Description : set broadcast frame filtering function. + * Arguments : control - + * ETHERC channel number and receive count for continuous Broadcast Frame + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_ARG - + * Invalid argument + * ETHER_ERR_RECV_ENABLE - + * Receive function is enable. + ***********************************************************************************************************************/ +static ether_return_t ether_set_broadcastframe_filter (ether_param_t const control) +{ + ether_broadcast_t * p_arg; + uint32_t channel_index = get_control_tbl_index((uint32_t)control.channel); + uint32_t counter; + ether_return_t ret; + + volatile struct st_etherc * petherc_adr; + + ret = ETHER_ERR_INVALID_ARG; + p_arg = control.p_ether_broadcast; + counter = p_arg->counter; + + if (0 != (counter & 0x0FFFF0000)) { + return ret; + } + + petherc_adr = g_eth_control_ch[channel_index].petherc; + + /* Check receive function is enable in ETHERC */ + if (0 == petherc_adr->ECMR.BIT.RE) { + bc_filter_count[channel_index] = counter; + ret = ETHER_SUCCESS; + } else { + ret = ETHER_ERR_RECV_ENABLE; + } + + return ret; +} /* End of function ether_set_broadcastframe_filter() */ + +/*********************************************************************************************************************** + * Function Name: power_on_control + * Description : Powers on the channel if the ETHEC channel used and the PHY access channel are different, or if the + * PHY access channel is powered off. + * Arguments : channel - + * ETHERC channel number + * Return Value : ETHER_SUCCESS - + * Processing completed successfully + * ETHER_ERR_INVALID_CHAN - + * Nonexistent channel number + * ETHER_ERR_CHAN_OPEN - + * Indicates the Ethernet cannot be opened because it is being used by another application + * : ETHER_ERR_OTHER - + * + ***********************************************************************************************************************/ +static ether_return_t power_on_control (uint32_t channel) +{ + uint32_t channel_index = get_control_tbl_index(channel); + ether_return_t ret = ETHER_ERR_OTHER; + + etherc_edmac_power_cont[channel_index] = ETHER_MODULE_USE; + ret = power_on(channel); + + return ret; +} /* End of function power_on_control() */ + +/*********************************************************************************************************************** + * Function Name: power_off_control + * Description : Powers off the channel if the ETHEC channel used and the PHY access channel are different, or if the + * PHY access channel is powered off. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void power_off_control (uint32_t channel) +{ + uint32_t channel_index = get_control_tbl_index(channel); + + etherc_edmac_power_cont[channel_index] = ETEHR_MODULE_NOT_USE; + power_off(channel); +} /* End of function power_off_control() */ + +/*********************************************************************************************************************** + * Function Name: check_mpde_bit + * Description : + * Arguments : none + * Return Value : 1: Magic Packet detection is enabled. + * 0: Magic Packet detection is disabled. + ***********************************************************************************************************************/ +static uint8_t check_mpde_bit (void) +{ +#if (ETHER_CHANNEL_MAX == 1) + /* The MPDE bit can be referred to only when ETHERC operates. */ + if ( (ETHER_MODULE_USE == etherc_edmac_power_cont[0]) + #if (ETHER_CH0_EN == 1) + && (1 == ETHERC0.ECMR.BIT.MPDE) + #else + && (1 == ETHERC1.ECMR.BIT.MPDE) + #endif + ) { + return 1; + } else { + return 0; + } + +#else + /* The MPDE bit can be referred to only when ETHERC0 operates. */ + if ( ( (ETHER_MODULE_USE == etherc_edmac_power_cont[ETHER_CHANNEL_0]) + && (1 == ETHERC0.ECMR.BIT.MPDE) + ) + + /* The MPDE bit can be referred to only when ETHERC1 operates. */ + || ( (ETHER_MODULE_USE == etherc_edmac_power_cont[ETHER_CHANNEL_1]) + && (1 == ETHERC1.ECMR.BIT.MPDE) + ) + ) { + return 1; + } else { + return 0; + } +#endif +} /* End of function check_mpde_bit() */ + +#if (ETHER_CH0_EN == 1) +/*********************************************************************************************************************** + * Function Name: ether_eint0 + * Description : EINT0 interrupt processing (A callback function to be called from r_bsp.) + * Arguments : pparam - + * unused + * Return Value : none + ***********************************************************************************************************************/ +static void ether_eint0 (void) +{ + ether_int_common(ETHER_CHANNEL_0); +} /* End of function ether_eint0() */ +#endif + +#if (ETHER_CH1_EN == 1) +/*********************************************************************************************************************** + * Function Name: ether_eint1 + * Description : EINT1 interrupt processing (A callback function to be called from r_bsp.) + * Arguments : pparam - + * unused + * Return Value : none + ***********************************************************************************************************************/ +static void ether_eint1(void) +{ + ether_int_common(ETHER_CHANNEL_1); +} /* End of function ether_eint1() */ +#endif + +/*********************************************************************************************************************** + * Function Name: ether_int_common + * Description : Interrupt handler for Ethernet receive and transmit interrupts. + * Arguments : channel - + * ETHERC channel number + * Return Value : none + ***********************************************************************************************************************/ +static void ether_int_common (uint32_t channel) +{ + uint32_t status_ecsr; + uint32_t status_eesr; + volatile struct st_etherc * petherc_adr; + volatile struct st_edmac * pedmac_adr; + ether_cb_arg_t cb_arg; + uint32_t channel_index = get_control_tbl_index(channel); + + petherc_adr = g_eth_control_ch[channel_index].petherc; + pedmac_adr = g_eth_control_ch[channel_index].pedmac; + + status_ecsr = petherc_adr->ECSR.LONG; + status_eesr = pedmac_adr->EESR.LONG; + + /* Callback : Interrupt handler */ + if (NULL != cb_func.pcb_int_hnd) { + cb_arg.channel = channel; + cb_arg.status_ecsr = status_ecsr; + cb_arg.status_eesr = status_eesr; + (*cb_func.pcb_int_hnd)((void *) &cb_arg); + } + + /* When the ETHERC status interrupt is generated */ + if (status_eesr & EMAC_ECI_INT) { +#if (ETHER_CFG_USE_LINKSTA == 1) + /* When the link signal change interrupt is generated */ + if (EMAC_LCHNG_INT == (status_ecsr & EMAC_LCHNG_INT)) { + /* The state of the link signal is confirmed and Link Up/Down is judged. */ + /* When becoming Link up */ + if (ETHER_CFG_LINK_PRESENT == petherc_adr->PSR.BIT.LMON) { + lchng_flag[channel_index] = ETHER_FLAG_ON_LINK_ON; + } + + /* When Link becomes down */ + else { + lchng_flag[channel_index] = ETHER_FLAG_ON_LINK_OFF; + } + } +#endif + + /* When the Magic Packet detection interrupt is generated */ + if (EMAC_MPD_INT == (status_ecsr & EMAC_MPD_INT)) { + mpd_flag[channel_index] = ETHER_FLAG_ON; + } + + /* + * Because each bit of the ECSR register is cleared when one is written, + * the value read from the register is written and the bit is cleared. + */ + /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + petherc_adr->ECSR.LONG = status_ecsr; + } + + /* + * Because each bit of the EESR register is cleared when one is written, + * the value read from the register is written and the bit is cleared. + */ + pedmac_adr->EESR.LONG = status_eesr; /* Clear EDMAC status bits */ + + /* Whether it is a necessary code is confirmed. */ + +} /* End of function ether_int_common() */ + +/*********************************************************************************************************************** + * Function Name: get_control_tbl_index + * Description : get index of control table. + * Arguments : channel - + * ETHERC channel number + * Return Value : Index of control table + ***********************************************************************************************************************/ +static uint32_t get_control_tbl_index (uint32_t channel) +{ +#if (ETHER_CHANNEL_MAX == 1) + return 0; +#else + return channel; +#endif +} /* End of function get_control_tbl_index() */ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/r_ether_rza2_private.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/r_ether_rza2_private.h new file mode 100644 index 0000000..47ce898 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/r_ether_rza2_private.h @@ -0,0 +1,281 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + ***********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*********************************************************************************************************************** + * File Name : r_ether_rza2_private.h + * Version : 1.00 + * Device : RZA2M + * H/W Platform : + * Description : File that defines macro and structure seen only in "r_ether_rza2.c" file. + ***********************************************************************************************************************/ + +/* Guards against multiple inclusion */ +#ifndef R_ETHER_PRIVATE_H + #define R_ETHER_PRIVATE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*********************************************************************************************************************** + Includes , "Project Includes" + ***********************************************************************************************************************/ + #include "r_ether_rza2_if.h" + #include "r_ether_rza2_config.h" + +/*********************************************************************************************************************** + Macro definitions + ***********************************************************************************************************************/ + +/* Check the setting values is valid. Please review the setting values in r_ether_rza2_config.h if error message is output */ + #if !((ETHER_CFG_MODE_SEL == 0) || (ETHER_CFG_MODE_SEL == 1)) + #error "ERROR- ETHER_CFG_MODE_SEL - Ethernet interface select is out of range defined in r_ether_rza2_config.h." + #endif + + #if !((ETHER_CFG_CH0_PHY_ADDRESS >= 0) && (ETHER_CFG_CH0_PHY_ADDRESS <= 31)) + #error "ERROR- ETHER_CFG_CH0_PHY_ADDRESS - PHY-LSI address is out of range defined in r_ether_rza2_config.h." + #endif + + #if !((ETHER_CFG_CH1_PHY_ADDRESS >= 0) && (ETHER_CFG_CH1_PHY_ADDRESS <= 31)) + #error "ERROR- ETHER_CFG_CH1_PHY_ADDRESS - PHY-LSI address is out of range defined in r_ether_rza2_config.h." + #endif + + #if !(ETHER_CFG_EMAC_RX_DESCRIPTORS >= 1) + #error "ERROR- ETHER_CFG_EMAC_RX_DESCRIPTORS - Transmission descriptors is out of range defined in r_ether_rza2_config.h." + #endif + + #if !(ETHER_CFG_EMAC_TX_DESCRIPTORS >= 1) + #error "ERROR- ETHER_CFG_EMAC_TX_DESCRIPTORS - Receive descriptors is out of range defined in r_ether_rza2_config.h." + #endif + + #if !((ETHER_CFG_BUFSIZE % 32) == 0) + #error "ERROR- ETHER_CFG_BUFSIZE - transmission and receive buffers is not 32-byte aligned in r_ether_rza2_config.h." + #endif + + #if !(ETHER_CFG_PHY_MII_WAIT >= 1) + #error "ERROR- ETHER_CFG_PHY_MII_WAIT - PHY-LSI access timing is out of range defined in r_ether_rza2_config.h." + #endif + + #if !((ETHER_CFG_LINK_PRESENT == 0) || (ETHER_CFG_LINK_PRESENT == 1)) + #error "ERROR- ETHER_CFG_LINK_PRESENT - Link signal polarity of PHY-LSI is out of range defined in r_ether_rza2_config.h." + #endif + + #if !((ETHER_CFG_USE_LINKSTA == 0) || (ETHER_CFG_USE_LINKSTA == 1)) + #error "ERROR- ETHER_CFG_USE_LINKSTA - Use LINKSTA select is out of range defined in r_ether_rza2_config.h." + #endif + + #if !((ETHER_CFG_USE_PHY_KSZ8041NL == 0) || (ETHER_CFG_USE_PHY_KSZ8041NL == 1)) + #error "ERROR- ETHER_CFG_USE_PHY_KSZ8041NL - use KSZ8041NL is out of range defined in r_ether_rza2_config.h." + #endif + +/* + * The total number of EMAC buffers to allocate. The number of + * total buffers is simply the sum of the number of transmit and + * receive buffers. + */ + #define EMAC_NUM_BUFFERS (ETHER_CFG_EMAC_RX_DESCRIPTORS + (ETHER_CFG_EMAC_TX_DESCRIPTORS)) + +/* Definition of the maximum / minimum number of data that can be sent at one time in the Ethernet */ + #define ETHER_BUFSIZE_MAX (1514) /* Maximum number of transmitted data */ + #define ETHER_BUFSIZE_MIN (60) /* Minimum number of transmitted data */ + +/* Bit definition of interrupt factor of Ethernet interrupt */ + #define EMAC_LCHNG_INT (1UL << 2) + #define EMAC_MPD_INT (1UL << 1) + + #define EMAC_RFCOF_INT (1UL << 24) + #define EMAC_ECI_INT (1UL << 22) + #define EMAC_TC_INT (1UL << 21) + #define EMAC_FR_INT (1UL << 18) + #define EMAC_RDE_INT (1UL << 17) + #define EMAC_RFOF_INT (1UL << 16) + +/* Bit definitions of status member of DescriptorS */ + #define TACT (0x80000000) + #define RACT (0x80000000) + #define TDLE (0x40000000) + #define RDLE (0x40000000) + #define TFP1 (0x20000000) + #define RFP1 (0x20000000) + #define TFP0 (0x10000000) + #define RFP0 (0x10000000) + #define TFE (0x08000000) + #define RFE (0x08000000) + + #define RFS9_RFOVER (0x00000200) + #define RFS8_RAD (0x00000100) + #define RFS7_RMAF (0x00000080) + #define RFS4_RRF (0x00000010) + #define RFS3_RTLF (0x00000008) + #define RFS2_RTSF (0x00000004) + #define RFS1_PRE (0x00000002) + #define RFS0_CERF (0x00000001) + + #define TWBI (0x04000000) + #define TFS8_TAD (0x00000100) + #define TFS3_CND (0x00000008) + #define TFS2_DLC (0x00000004) + #define TFS1_CD (0x00000002) + #define TFS0_TRO (0x00000001) + +/* Number of entries in PAUSE resolution table */ + #define PAUSE_TABLE_ENTRIES (8) + +/* Local device and link partner PAUSE settings */ + #define XMIT_PAUSE_OFF (0) /* The pause frame transmission is prohibited. */ + #define RECV_PAUSE_OFF (0) /* The pause frame reception is prohibited. */ + #define XMIT_PAUSE_ON (1) /* The pause frame transmission is permitted. */ + #define RECV_PAUSE_ON (1) /* The pause frame reception is permitted. */ + +/* PAUSE link mask and shift values */ +/* + * The mask value and shift value which are for that shift the bits form a line and + * for comparing the bit information of PAUSE function which support the local device and + * Link partner with the assorted table(pause_resolution) which enable or disable the PAUSE frame. + */ + #define LINK_RES_ABILITY_MASK (3) + #define LINK_RES_LOCAL_ABILITY_BITSHIFT (2) + +/* Etherc mode */ + #define NO_USE_MAGIC_PACKET_DETECT (0) + #define USE_MAGIC_PACKET_DETECT (1) + +/* Defines the port connection to be used in the Ether */ + #define PORT_CONNECT_ET0 (0x01) + #define PORT_CONNECT_ET1 (0x02) + +/** Ethernet module usage status */ + #define ETEHR_MODULE_NOT_USE (0) /* Ethernet module is not used */ + #define ETHER_MODULE_USE (1) /* Ethernet module is used */ + +/*********************************************************************************************************************** + Typedef definitions + ***********************************************************************************************************************/ +/* + * EDMAC descriptor as defined in the hardware manual. It is + * modified to support little endian CPU mode. + */ +typedef struct DescriptorS +{ + volatile uint32_t status; + volatile uint16_t size; + volatile uint16_t bufsize; + volatile uint8_t *buf_p; + struct DescriptorS *next; +} descriptor_t; + +/* + * Ethernet buffer type definition. + */ +typedef struct EtherBufferS +{ + uint8_t buffer[EMAC_NUM_BUFFERS][ETHER_CFG_BUFSIZE]; + +} etherbuffer_t; + +/* + * PauseMaskE, PauseValE and pause_resolutionS are use to create + * PAUSE resolution Table 28B-3 in IEEE 802.3-2008 standard. + */ +typedef enum PauseMaskE +{ + PAUSE_MASK0, + PAUSE_MASK1, + PAUSE_MASK2, + PAUSE_MASK3, + PAUSE_MASK4, + PAUSE_MASK5, + PAUSE_MASK6, + PAUSE_MASK7, + PAUSE_MASK8, + PAUSE_MASK9, + PAUSE_MASKA, + PAUSE_MASKB, + PAUSE_MASKC, + PAUSE_MASKD, + PAUSE_MASKE, + PAUSE_MASKF +} pausemask_t; + +typedef enum PauseValE +{ + PAUSE_VAL0, + PAUSE_VAL1, + PAUSE_VAL2, + PAUSE_VAL3, + PAUSE_VAL4, + PAUSE_VAL5, + PAUSE_VAL6, + PAUSE_VAL7, + PAUSE_VAL8, + PAUSE_VAL9, + PAUSE_VALA, + PAUSE_VALB, + PAUSE_VALC, + PAUSE_VALD, + PAUSE_VALE, + PAUSE_VALF +} pauseval_t; + +typedef struct pause_resolutionS +{ + pausemask_t mask; + pauseval_t value; + uint8_t transmit; + uint8_t receive; +} pauseresolution_t; + +typedef struct +{ + volatile struct st_etherc * petherc; /* ETHERC module */ + volatile struct st_edmac * pedmac; /* EDMAC */ + volatile uint32_t * preg_pir; + uint32_t phy_address; + uint8_t port_connect; +} ether_control_t; + +/*********************************************************************************************************************** + Exported global variables + ***********************************************************************************************************************/ +extern const ether_control_t g_eth_control_ch[]; + +/*********************************************************************************************************************** + Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ +extern void ether_set_phy_mode (uint8_t connect); + +#ifdef __cplusplus +} +#endif + +#endif /* R_ETHER_PRIVATE_H */ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_rza2_config.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_rza2_config.h new file mode 100644 index 0000000..30cc715a --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_rza2_config.h @@ -0,0 +1,118 @@ +/*********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS + * SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + ***********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*********************************************************************************************************************** + * File Name : r_ether_rza2_config.h + * Version : 1.00 + * Description : Ethernet module device driver + ***********************************************************************************************************************/ + +/* Guards against multiple inclusion */ +#ifndef R_ETHER_RZA2_CONFIG_H + #define R_ETHER_RZA2_CONFIG_H + +#ifdef __cplusplus +extern "C" { +#endif +/*********************************************************************************************************************** + Macro definitions + ***********************************************************************************************************************/ +/* Ethernet channel select. + 0 = disable + 1 = enable + If only one of them is enabled, the API argument "channel" value is not referenced. + */ + #define ETHER_CH0_EN (0) + #define ETHER_CH1_EN (1) + +/* Ethernet interface select. + 0 = MII (Media Independent Interface) + 1 = RMII (Reduced Media Independent Interface) + */ + #define ETHER_CFG_MODE_SEL (0) + +/* PHY-LSI address setting for ETHER0/1. + */ + #define ETHER_CFG_CH0_PHY_ADDRESS (0) /* Please define the PHY-LSI address in the range of 0-31. */ + #define ETHER_CFG_CH1_PHY_ADDRESS (0) /* Please define the PHY-LSI address in the range of 0-31. */ + +/* The number of Rx descriptors. */ + #define ETHER_CFG_EMAC_RX_DESCRIPTORS (8) + +/* The number of Tx descriptors. */ + #define ETHER_CFG_EMAC_TX_DESCRIPTORS (8) + +/* Please define the size of the sending and receiving buffer in the value where one frame can surely be stored + because the driver is single-frame/single-buffer processing. */ + #define ETHER_CFG_BUFSIZE (1536) /* Must be 32-byte aligned */ + +/* Define the access timing of MII/RMII register */ + #define ETHER_CFG_PHY_MII_WAIT (8) /* Plese define the value of 1 or more */ + +/* Define the waiting time for reset completion of PHY-LSI */ + #define ETHER_CFG_PHY_DELAY_RESET (0x00020000L) + +/** + * Link status read from LMON bit of ETHERC PSR register. The state is hardware dependent. + */ + #define ETHER_CFG_LINK_PRESENT (0) + +/* Use LINKSTA signal for detect link status changes + 0 = unused (use PHY-LSI status register) + 1 = use (use LINKSTA signal) + */ + #define ETHER_CFG_USE_LINKSTA (0) /* This setting is reflected in all channels */ + +/* Definition of whether or not to use KSZ8041NL of the Micrel Inc. + 0 = unused + 1 = use + */ + #define ETHER_CFG_USE_PHY_KSZ8041NL (0) + +/*********************************************************************************************************************** + Typedef definitions + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global variables + ***********************************************************************************************************************/ + +/*********************************************************************************************************************** + Exported global functions (to be accessed by other files) + ***********************************************************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* R_ETHER_RZA2_CONFIG_H */ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_setting_rza2m.c b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_setting_rza2m.c new file mode 100644 index 0000000..28d8034 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/r_ether_rza2/src/targets/TARGET_GR_MANGO/r_ether_setting_rza2m.c @@ -0,0 +1,119 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/*********************************************************************************************************************** +* File Name : r_ether_setting_rza2m.c +* Version : 1.00 +* Device : RZA2M +* Description : Ethernet module device driver +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "iodefine.h" +#include "iobitmask.h" +#include "cmsis.h" +#include "pinmap.h" + +#include "r_ether_rza2_if.h" +#include "src/r_ether_rza2_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: ether_set_phy_mode +* Description : +* Arguments : connect - +* Ethernet channel number +* Return Value : none +***********************************************************************************************************************/ +void ether_set_phy_mode(uint8_t connect) +{ +#if (ETHER_CH0_EN == 1) +#error "Not support in this board." +#endif + +#if (ETHER_CH1_EN == 1) + if (PORT_CONNECT_ET1 == (connect & PORT_CONNECT_ET1)) { + #if (ETHER_CFG_MODE_SEL == 0) + /* CH1 MII */ + GPIO.PFENET.BIT.PHYMODE1 = 1; + pin_function(P3_3, 1); // ET1_MDC + pin_function(P3_4, 1); // ET1_MDIO + pin_function(PC_0, 3); // ET1_TXCLK + pin_function(PC_4, 3); // ET1_TXER + pin_function(PK_0, 1); // ET1_TXEN + pin_function(PK_1, 1); // ET1_TXD0 + pin_function(PK_2, 1); // ET1_TXD1 + pin_function(PC_1, 3); // ET1_TXD2 + pin_function(PC_2, 3); // ET1_TXD3 + pin_function(PK_3, 1); // ET1_RXCLK + pin_function(P3_1, 1); // ET1_RXER + pin_function(PC_5, 3); // ET1_RXDV + pin_function(PK_4, 1); // ET1_RXD0 + pin_function(P3_5, 1); // ET1_RXD1 + pin_function(PC_6, 3); // ET1_RXD2 + pin_function(PC_7, 3); // ET1_RXD3 + pin_function(P3_2, 1); // ET1_CRS + pin_function(PC_3, 3); // ET1_COL + #elif (ETHER_CFG_MODE_SEL == 1) + /* CH1 RMII */ + GPIO.PFENET.BIT.PHYMODE1 = 0; + GPIO.PMODEPFS.BIT.ET1_EXOUT_SEL = 0; + #error "Not support in this board." + #endif + } +#endif + +} /* End of function ether_set_phy_mode() */ + +/* End of File */ diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.cpp b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.cpp new file mode 100644 index 0000000..d3bd520 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.cpp @@ -0,0 +1,290 @@ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include +#include +#include + +#include "cmsis_os.h" + +#include "mbed_interface.h" +#include "mbed_assert.h" +#include "netsocket/nsapi_types.h" +#include "mbed_shared_queues.h" + +#include "r_ether_rza2_if.h" +#include "rza2_emac.h" +#include "r_ether_rza2_config.h" + +#define RZ_A2_ETH_IF_NAME "en" +#define PHY_TASK_PERIOD 200ms + +using namespace std::chrono; + +// Weak so a module can override +MBED_WEAK EMAC &EMAC::get_default_instance() +{ +#if (ETHER_CH0_EN == 1) + return RZ_A2_EMAC::get_instance(ETHER_CHANNEL_0); +#elif (ETHER_CH1_EN == 1) + return RZ_A2_EMAC::get_instance(ETHER_CHANNEL_1); +#else +#error "Set ETHER_CH0_EN or ETHER_CH1_EN to 1." +#endif +} + +RZ_A2_EMAC &RZ_A2_EMAC::get_instance(uint32_t channel) +{ +#if (ETHER_CH0_EN == 1) && (ETHER_CH1_EN == 1) + static RZ_A2_EMAC emac_0(ETHER_CHANNEL_0); + static RZ_A2_EMAC emac_1(ETHER_CHANNEL_1); + + if (channel == 0) { + return emac_0; + } else { + return emac_1; + } +#else + static RZ_A2_EMAC emac(channel); + return emac; +#endif +} + +RZ_A2_EMAC::RZ_A2_EMAC(uint32_t channel) : _channel(channel), hwaddr(), hwaddr_set(false), power_on(false), + recvThread(osPriorityNormal, 896), sem_recv(0) +{ +} + +uint32_t RZ_A2_EMAC::get_mtu_size() const +{ + return 1500; +} + +uint32_t RZ_A2_EMAC::get_align_preference() const +{ + return 0; +} + +void RZ_A2_EMAC::get_ifname(char *name, uint8_t size) const +{ + memcpy(name, RZ_A2_ETH_IF_NAME, (size < sizeof(RZ_A2_ETH_IF_NAME)) ? size : sizeof(RZ_A2_ETH_IF_NAME)); +} + +uint8_t RZ_A2_EMAC::get_hwaddr_size() const +{ + return 6; +} + +bool RZ_A2_EMAC::get_hwaddr(uint8_t *addr) const +{ + return false; +} + +void RZ_A2_EMAC::set_hwaddr(const uint8_t *addr) +{ + memcpy(hwaddr, addr, sizeof(hwaddr)); + hwaddr_set = true; + + /* Reconnect */ + if (power_on != false) { + R_ETHER_Open_ZC2(_channel, hwaddr, ETHER_FLAG_OFF); + } +} + +bool RZ_A2_EMAC::link_out(emac_mem_buf_t *buf) +{ + emac_mem_buf_t *copy_buf = buf; + uint32_t retry_cnt = 0; + uint16_t write_buf_size; + int total_write_size = 0; + uint8_t * pwrite_buffer_address; + + while (1) { + if (R_ETHER_Write_ZC2_GetBuf(_channel, (void **) &pwrite_buffer_address, &write_buf_size) == ETHER_SUCCESS) { + break; + } + retry_cnt++; + if (retry_cnt > 200) { + memory_manager->free(buf); + return false; + } + osDelay(1); + } + + while ((copy_buf != NULL) && (memory_manager->get_ptr(copy_buf) != NULL) && (memory_manager->get_len(copy_buf) != 0)) { + memcpy(&pwrite_buffer_address[total_write_size], memory_manager->get_ptr(copy_buf), memory_manager->get_len(copy_buf)); + total_write_size += memory_manager->get_len(copy_buf); + copy_buf = memory_manager->get_next(copy_buf); + } + memory_manager->free(buf); + + if (total_write_size > 0) { + if (total_write_size < 60) { + memset(&pwrite_buffer_address[total_write_size], 0, 60 - total_write_size); + total_write_size = 60; + } + if (R_ETHER_Write_ZC2_SetBuf(_channel, total_write_size) == ETHER_SUCCESS) { + return true; + } + } + + return false; +} + +bool RZ_A2_EMAC::power_up() +{ + ether_param_t param; + + if (power_on != false) { + return true; + } + + /* Initialize memory which ETHERC/EDMAC is used */ + R_ETHER_Initial(); + + /* Set the callback function */ + param.ether_callback.pcb_func = &_callback_pcb; + R_ETHER_Control(CONTROL_SET_CALLBACK, param); + + /* Set the callback function */ + param.ether_callback.pcb_int_hnd = &_callback_hnd; + R_ETHER_Control(CONTROL_SET_INT_HANDLER, param); + + param.channel = _channel; + R_ETHER_Control(CONTROL_POWER_ON, param); + + if (hwaddr_set != false) { + R_ETHER_Open_ZC2(_channel, hwaddr, ETHER_FLAG_OFF); + } + + /* task */ + recvThread.start(mbed::callback(this, &RZ_A2_EMAC::recv_task)); + phy_task_handle = mbed::mbed_event_queue()->call_every(PHY_TASK_PERIOD, mbed::callback(this, &RZ_A2_EMAC::phy_task)); + + power_on = true; + return true; +} + +void RZ_A2_EMAC::power_down() +{ + power_on = false; +} + +void RZ_A2_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + emac_link_input_cb = input_cb; +} + +void RZ_A2_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + emac_link_state_cb = state_cb; +} + +void RZ_A2_EMAC::add_multicast_group(const uint8_t *addr) +{ + // Not supported +} + +void RZ_A2_EMAC::remove_multicast_group(const uint8_t *addr) +{ + // Not supported +} + +void RZ_A2_EMAC::set_all_multicast(bool all) +{ + // Not supported +} + +void RZ_A2_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + memory_manager = &mem_mngr; +} + +void RZ_A2_EMAC::_callback_pcb(void* arg) +{ + ether_cb_arg_t * p_cb_arg = (ether_cb_arg_t *)arg; + get_instance(p_cb_arg->channel).callback_pcb(arg); +} + +void RZ_A2_EMAC::_callback_hnd(void* arg) +{ + ether_cb_arg_t * p_cb_arg = (ether_cb_arg_t *)arg; + get_instance(p_cb_arg->channel).callback_hnd(arg); +} + +void RZ_A2_EMAC::callback_pcb(void* arg) +{ + ether_cb_arg_t * p_cb_arg = (ether_cb_arg_t *)arg; + + if (p_cb_arg->event_id == ETHER_CB_EVENT_ID_LINK_ON) { + emac_link_state_cb(true); + } else if (p_cb_arg->event_id == ETHER_CB_EVENT_ID_LINK_OFF) { + emac_link_state_cb(false); + } else { + // do nothing + } +} + +void RZ_A2_EMAC::callback_hnd(void* arg) +{ + ether_cb_arg_t * p_cb_arg = (ether_cb_arg_t *)arg; + + if (p_cb_arg->status_eesr & 0x00040000) { + sem_recv.release(); + } +} + +void RZ_A2_EMAC::recv_task(void) +{ + int32_t ret; + emac_mem_buf_t *buf; + uint8_t * pread_buffer_address; + + while (1) { + sem_recv.acquire(); + while (1) { + /* (1) Retrieve the receive buffer location controlled by the descriptor. */ + ret = R_ETHER_Read_ZC2(_channel, (void **)&pread_buffer_address); + if (ret <= ETHER_NO_DATA) { + break; + } + + /* When there is data to receive */ + while (1) { + buf = memory_manager->alloc_heap(ret, 0); + if (buf != NULL) { + /* (2) Copy the data read from the receive buffer which is controlled by the descriptor to + the buffer which is specified by the user (up to 1024 bytes). */ + memcpy(memory_manager->get_ptr(buf), pread_buffer_address, (uint32_t)memory_manager->get_len(buf)); + + /* (3) Read the receive data from the receive buffer controlled by the descriptor, + and then release the receive buffer. */ + R_ETHER_Read_ZC2_BufRelease(_channel); + + emac_link_input_cb(buf); + break; + } + osDelay(5); + } + } + } +} + +void RZ_A2_EMAC::phy_task(void) +{ + R_ETHER_LinkProcess(_channel); +} + diff --git a/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.h b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.h new file mode 100644 index 0000000..ac53028 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_RENESAS_EMAC/TARGET_RZ_A2XX/rza2_emac.h @@ -0,0 +1,172 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef RZ_A2_EMAC_H +#define RZ_A2_EMAC_H + +#include "EMAC.h" +#include "rtos/Thread.h" +#include "rtos/Semaphore.h" + +class RZ_A2_EMAC : public EMAC { +public: + RZ_A2_EMAC(uint32_t channel); + + static RZ_A2_EMAC &get_instance(uint32_t channel); + + /** + * Return maximum transmission unit + * + * @return MTU in bytes + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets memory buffer alignment preference + * + * Gets preferred memory buffer alignment of the Emac device. IP stack may or may not + * align link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes + */ + virtual uint32_t get_align_preference() const; + + /** + * Return interface name + * + * @param name Pointer to where the name should be written + * @param size Maximum number of character to copy + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns size of the underlying interface HW address size. + * + * @return HW address size in bytes + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Return interface-supplied HW address + * + * Copies HW address to provided memory, @param addr has to be of correct size see @a get_hwaddr_size + * + * HW address need not be provided if this interface does not have its own HW + * address configuration; stack will choose address from central system + * configuration if the function returns false and does not write to addr. + * + * @param addr HW address for underlying interface + * @return true if HW address is available + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for interface + * + * Provided address has to be of correct size, see @a get_hwaddr_size + * + * Called to set the MAC address to actually use - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden, eg for test + * purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * That can not be called from an interrupt context. + * + * @param buf Packet to be send + * @return True if the packet was send successfully, False otherwise + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success, False in case of an error. + */ + virtual bool power_up(); + + /** + * Deinitializes the HW + * + */ + virtual void power_down(); + + /** + * Sets a callback that needs to be called for packets received for that interface + * + * @param input_cb Function to be register as a callback + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that needs to be called on link status changes for given interface + * + * @param state_cb Function to be register as a callback + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Add device to a multicast group + * + * @param address A multicast group hardware address + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Remove device from a multicast group + * + * @param address A multicast group hardware address + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Request reception of all multicast packets + * + * @param all True to receive all multicasts + * False to receive only multicasts addressed to specified groups + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager that is used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + +private: + EMACMemoryManager *memory_manager; /**< Memory manager */ + uint32_t _channel; + uint8_t hwaddr[6]; + bool hwaddr_set; + bool power_on; + emac_link_input_cb_t emac_link_input_cb; /**< Callback for incoming data */ + emac_link_state_change_cb_t emac_link_state_cb; /**< Link state change callback */ + rtos::Thread recvThread; + int phy_task_handle; /**< Handle for phy task event */ + rtos::Semaphore sem_recv; + + static void _callback_pcb(void*); + static void _callback_hnd(void*); + void callback_pcb(void*); + void callback_hnd(void*); + void recv_task(void); + void phy_task(void); +}; + +#endif /* RZ_A2_EMAC_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/PeripheralPins.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/PeripheralPins.h new file mode 100644 index 0000000..73d139a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/PeripheralPins.h @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +typedef struct { + PinName pin; + int function; + int pm; +} PinFunc; + +/************IRQ***************/ +extern const PinMap PinMap_IRQ[]; + +/************PINMAP***************/ +extern const PinFunc PIPC_0_tbl[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************DAC***************/ +extern const PinMap PinMap_DAC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_CTS[]; +extern const PinMap PinMap_UART_RTS[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +/************PWM***************/ +extern const PinMap PinMap_PWM[]; + +/************CAN***************/ +extern const PinMap PinMap_CAN_RD[]; +extern const PinMap PinMap_CAN_TD[]; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralNames.h new file mode 100644 index 0000000..2395ed1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralNames.h @@ -0,0 +1,108 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART0, + UART1, + UART2, + UART3, + UART4, +} UARTName; + +typedef enum { + PWM_GTIOC0A = 0, + PWM_GTIOC0B, + PWM_GTIOC1A, + PWM_GTIOC1B, + PWM_GTIOC2A, + PWM_GTIOC2B, + PWM_GTIOC3A, + PWM_GTIOC3B, + PWM_GTIOC4A, + PWM_GTIOC4B, + PWM_GTIOC5A, + PWM_GTIOC5B, + PWM_GTIOC6A, + PWM_GTIOC6B, + PWM_GTIOC7A, + PWM_GTIOC7B, + + PWM_TIOC0A = 0x100, + PWM_TIOC0C, + PWM_TIOC1A, + PWM_TIOC2A, + PWM_TIOC3A, + PWM_TIOC3C, + PWM_TIOC4A, + PWM_TIOC4C, +} PWMName; + +typedef enum { + AN0= 0, + AN1= 1, + AN2= 2, + AN3= 3, + AN4= 4, + AN5= 5, + AN6= 6, + AN7= 7, +} ADCName; + +typedef enum { + SPI_0 = 0, + SPI_1, + SPI_2, + SPI_3, + SPI_4, +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3, +} I2CName; + +typedef enum { + CAN_0 = 0, + CAN_1, + CAN_2, + CAN_3, + CAN_4, +} CANName; + + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART4 + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralPins.c new file mode 100644 index 0000000..4b2029c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PeripheralPins.c @@ -0,0 +1,212 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +//#define ISEL_BIT (0x40) // use interrupt + +/************IRQ***************/ +enum { + IRQ0,IRQ1, + IRQ2,IRQ3, + IRQ4,IRQ5, + IRQ6,IRQ7, +} IRQNo; + +const PinMap PinMap_IRQ[] = { + {P6_2, IRQ0, 6}, {PL_4, IRQ0, 5}, {PD_0, IRQ0, 2}, + {PJ_6, IRQ0, 5}, {PJ_1, IRQ0, 6}, {P5_4, IRQ0, 2}, + {P1_0, IRQ0, 3}, {P4_0, IRQ0, 6}, {PC_5, IRQ0, 6}, + {PF_4, IRQ1, 6}, {PE_1, IRQ1, 6}, {PD_1, IRQ1, 2}, + {PF_7, IRQ1, 5}, {P1_1, IRQ1, 3}, {PC_4, IRQ1, 6}, + {P5_5, IRQ1, 2}, {P4_1, IRQ1, 6}, {P8_2, IRQ2, 5}, + {PH_1, IRQ2, 6}, {PD_2, IRQ2, 2}, {PH_4, IRQ2, 6}, + {P1_2, IRQ2, 3}, {P5_6, IRQ2, 2}, {PC_0, IRQ2, 5}, + {P4_2, IRQ2, 6}, + {PH_0, IRQ3, 6}, {PD_3, IRQ3, 2}, {P8_1, IRQ3, 5}, + {PH_3, IRQ3, 6}, {P4_3, IRQ3, 6}, {P5_7, IRQ3, 2}, + {P3_0, IRQ3, 5}, {P1_3, IRQ3, 3}, + {PL_0, IRQ4, 5}, {PF_1, IRQ4, 6}, {PD_4, IRQ4, 2}, + {PG_2, IRQ4, 6}, {PH_6, IRQ4, 5}, {PJ_5, IRQ4, 6}, + {P1_4, IRQ4, 3}, {P5_0, IRQ4, 2}, + {PL_1, IRQ5, 5}, {PA_5, IRQ5, 6}, {PK_2, IRQ5, 6}, + {PD_5, IRQ5, 2}, {PH_5, IRQ5, 5}, {PG_6, IRQ5, 6}, + {P2_0, IRQ5, 3}, {P5_1, IRQ5, 2}, + {PL_2, IRQ6, 5}, {PA_1, IRQ6, 6}, {PD_6, IRQ6, 2}, + {PK_4, IRQ6, 6}, {P3_1, IRQ6, 6}, {P5_2, IRQ6, 2}, + {PC_7, IRQ6, 6}, {P2_1, IRQ6, 3}, + {PL_3, IRQ7, 5}, {PD_7, IRQ7, 2}, {P3_3, IRQ7, 6}, + {P2_2, IRQ7, 3}, {PC_6, IRQ7, 6}, {P5_3, IRQ7, 2}, + {NC, NC, 0} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P5_0, AN0, 1}, + {P5_1, AN1, 1}, + {P5_2, AN2, 1}, + {P5_3, AN3, 1}, + {P5_4, AN4, 1}, + {P5_5, AN5, 1}, + {P5_6, AN6, 1}, + {P5_7, AN7, 1}, + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PD_1, I2C_0, 1}, + {PD_3, I2C_1, 1}, + {PD_5, I2C_2, 1}, + {PD_7, I2C_3, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PD_0, I2C_0, 1}, + {PD_2, I2C_1, 1}, + {PD_4, I2C_2, 1}, + {PD_6, I2C_3, 1}, + {NC, NC, 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P8_5, UART0, 5}, + {P4_2, UART0, 1}, + {P7_3, UART1, 4}, + {PJ_2, UART1, 4}, + {PF_5, UART2, 1}, + {PE_2, UART2, 3}, + {P6_3, UART3, 3}, + {PF_2, UART3, 1}, + {P9_0, UART4, 4}, + {P4_6, UART4, 4}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P7_7, UART0, 5}, + {P4_1, UART0, 1}, + {P7_1, UART1, 4}, + {PJ_1, UART1, 4}, + {PF_4, UART2, 1}, + {PE_1, UART2, 3}, + {P6_2, UART3, 3}, + {PF_1, UART3, 1}, + {P9_1, UART4, 4}, + {P4_5, UART4, 4}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PB_3, UART0, 5}, + {P4_4, UART0, 1}, + {P7_5, UART1, 4}, + {PJ_4, UART1, 4}, + {PH_2, UART2, 1}, + {PH_4, UART2, 2}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PB_4, UART0, 5}, + {P4_3, UART0, 1}, + {P7_4, UART1, 4}, + {PJ_3, UART1, 4}, + {PF_6, UART2, 1}, + {PH_3, UART2, 2}, + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P8_7, SPI_0, 4}, + {PG_0, SPI_0, 3}, + {PK_2, SPI_0, 5}, + {PF_0, SPI_1, 5}, + {PG_4, SPI_1, 3}, + {P3_1, SPI_2, 5}, + {PC_0, SPI_2, 4}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P8_6, SPI_0, 4}, + {PK_3, SPI_0, 5}, + {PG_1, SPI_0, 3}, + {PF_1, SPI_1, 5}, + {PG_5, SPI_1, 3}, + {P3_2, SPI_2, 5}, + {PC_1, SPI_2, 4}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P8_5, SPI_0, 4}, + {PG_2, SPI_0, 3}, + {PK_4, SPI_0, 5}, + {PF_2, SPI_1, 5}, + {PG_6, SPI_1, 3}, + {PC_2, SPI_2, 4}, + {P3_3, SPI_2, 5}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P8_4, SPI_0, 4}, + {PG_3, SPI_0, 3}, + {P3_5, SPI_0, 5}, + {PF_3, SPI_1, 5}, + {PG_7, SPI_1, 3}, + {P3_4, SPI_2, 5}, + {PC_3, SPI_2, 4}, + {NC, NC, 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PG_2, PWM_GTIOC0A, 5}, + {PG_3, PWM_GTIOC0B, 5}, + {PG_4, PWM_GTIOC1A, 5}, + {PG_5, PWM_GTIOC1B, 5}, + {PG_6, PWM_GTIOC2A, 5}, + {PG_7, PWM_GTIOC2B, 5}, + {P8_3, PWM_GTIOC3A, 5}, + {P7_6, PWM_GTIOC3A, 4}, + {P7_7, PWM_GTIOC3B, 4}, + {P0_0, PWM_GTIOC3B, 5}, + {PH_0, PWM_GTIOC4A, 3}, + {P0_1, PWM_GTIOC4A, 5}, + {PH_1, PWM_GTIOC4B, 3}, + {P0_2, PWM_GTIOC4B, 5}, + {P8_2, PWM_GTIOC5A, 4}, + {P8_1, PWM_GTIOC5B, 4}, + {PH_3, PWM_GTIOC6A, 3}, + {P0_3, PWM_GTIOC6A, 5}, + {P2_0, PWM_GTIOC6A, 2}, + {PH_4, PWM_GTIOC6B, 3}, + {P0_4, PWM_GTIOC6B, 5}, + {P2_1, PWM_GTIOC6B, 2}, + {P0_5, PWM_GTIOC7A, 5}, + {P2_2, PWM_GTIOC7A, 2}, + {P0_6, PWM_GTIOC7B, 5}, + {P2_3, PWM_GTIOC7B, 2}, + {NC, NC, 0} +}; + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PinNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PinNames.h new file mode 100644 index 0000000..7cd8e1d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PinNames.h @@ -0,0 +1,118 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 4 + +typedef enum { + P0_0 = 0x0000, P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, + P1_0 = 0x0010, P1_1, P1_2, P1_3, P1_4, + P2_0 = 0x0020, P2_1, P2_2, P2_3, + P3_0 = 0x0030, P3_1, P3_2, P3_3, P3_4, P3_5, + P4_0 = 0x0040, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, + P5_0 = 0x0050, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, + P6_0 = 0x0060, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, + P7_0 = 0x0070, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, + P8_0 = 0x0080, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, + P9_0 = 0x0090, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, + PA_0 = 0x00A0, PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, + PB_0 = 0x00B0, PB_1, PB_2, PB_3, PB_4, PB_5, + PC_0 = 0x00C0, PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, + PD_0 = 0x00D0, PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, + PE_0 = 0x00E0, PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, + PF_0 = 0x00F0, PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, + PG_0 = 0x0100, PG_1, PG_2, PG_3, PG_4, PG_5, PG_6, PG_7, + PH_0 = 0x0110, PH_1, PH_2, PH_3, PH_4, PH_5, PH_6, + PJ_0 = 0x0120, PJ_1, PJ_2, PJ_3, PJ_4, PJ_5, PJ_6, PJ_7, + PK_0 = 0x0130, PK_1, PK_2, PK_3, PK_4, PK_5, + PL_0 = 0x0140, PL_1, PL_2, PL_3, PL_4, + JP0_0 = 0x0150, JP0_1, + + NMI = 0x0700, + + // mbed Pin Names + LED1 = P0_1, + LED2 = P0_3, + LED3 = P0_5, + LED4 = P8_2, + + LED_GREEN = LED1, + LED_YELLOW = LED2, + LED_ORANGE = LED3, + LED_RED = LED4, + + USBTX = P9_0, + USBRX = P9_1, + + A0 = P5_0, + A1 = P5_1, + A2 = P5_2, + A3 = P5_3, + A4 = P5_4, + A5 = P5_5, + A6 = P5_6, + A7 = P5_7, + + I2C_SCL = PD_2, + I2C_SDA = PD_3, + + USER_BUTTON0 = PD_6, + USER_BUTTON1 = PD_7, + // Standardized button names + BUTTON1 = USER_BUTTON0, + + // Raspberry Pi Pin Names + SPI_MOSI = P8_6, + SPI_MISO = P8_5, + SPI_SCKL = P8_7, + SPI_SSL = P8_4, + + UART_TXD = P4_2, + UART_RXD = P4_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0xff) +#define PINNO(pin) ((pin)&0x0f) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PortNames.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PortNames.h new file mode 100644 index 0000000..a576098 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/PortNames.h @@ -0,0 +1,52 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4, + Port5 = 5, + Port6 = 6, + Port7 = 7, + Port8 = 8, + Port9 = 9, + PortA = 10, + PortB = 11, + PortC = 12, + PortD = 13, + PortE = 14, + PortF = 15, + PortG = 16, + PortH = 17, + PortJ = 18, + PortK = 19, + PortL = 20, + PortM = 21 /* PortM = JP0 */ +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/TARGET_MBED_MBRZA2M/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/TARGET_MBED_MBRZA2M/reserved_pins.h new file mode 100644 index 0000000..525aa09 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/TARGET_MBED_MBRZA2M/reserved_pins.h @@ -0,0 +1,23 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef RESERVED_PINS_H +#define RESERVED_PINS_H + +#define TARGET_RESERVED_PINS {} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device.h new file mode 100644 index 0000000..dfbefb3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device.h @@ -0,0 +1,51 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +/* ->Take measures about optimization problems of web compiler */ + /* Web compiler has problem that inlining code may not be generated correctly */ + /* when "-O3 -Otime" was specified. */ +#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027) +#pragma Ospace +#endif +/* <-Take measures about optimization problems of web compiler */ + + + + + + +#define TRANSACTION_QUEUE_SIZE_SPI 16 + + + + + +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + + + + + +#include "objects.h" +#include "dma_api.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/MBRZA2M.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/MBRZA2M.h new file mode 100644 index 0000000..bdfd4ec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/MBRZA2M.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "RZ_A2M.h" diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/RZ_A2_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/RZ_A2_Init.c new file mode 100644 index 0000000..73c24fb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/RZ_A2_Init.c @@ -0,0 +1,168 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2012-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/**************************************************************************//** +* @file RZ_A2_Init.c +* $Rev: 624 $ +* $Date:: 2013-04-24 13:37:48 +0900#$ +* @brief RZ_A2 Initialize +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "MBRZA2M.h" +#include "RZ_A2_Init.h" +#include "pinmap.h" +#include "gpio_api.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +/**************************************************************************//** +* Function Name: RZ_A2_SetSramWriteEnable +* @brief Initialize Board settings +* +* Description:
+* Set SRAM write enable +* @param none +* @retval none +******************************************************************************/ +void RZ_A2_SetSramWriteEnable(void) +{ + /* Enable SRAM write access */ + CPG.SYSCR3.BYTE = 0x0F; + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A2_InitClock +* @brief Initialize Board settings +* +* Description:
+* Initialize Clock +* @param none +* @retval none +******************************************************************************/ +void RZ_A2_InitClock(void) +{ + /* WARNING: */ + /* The section area for the .data data or the .bss data is not initialized */ + /* because this function is called by the Peripheral_BasicInit */ + /* function. Do not use the variables allocated to the section area */ + /* for the .data or the .bss data within this function and the user- */ + /* defined function called by this function. */ + + volatile uint32_t dummy_buf_32b; + + /* standby_mode_en bit of Power Control Register setting */ + pl310.REG15_POWER_CTRL.BIT.standby_mode_en = 1; + dummy_buf_32b = pl310.REG15_POWER_CTRL.LONG; + (void)dummy_buf_32b; + + /* ==== CPG Settings ==== */ + CPG.FRQCR.WORD = 0x1012u; /* PLL(x88), I:G:B:P1:P0 = 22:11:5.5:2.75:1.375 */ + /* CKIO:Output at time usually, */ + /* Output when bus right is opened, */ + /* output at standby"L" */ + /* Clockin = 24MHz, */ + /* I Clock = 528MHz, */ + /* G Clock = 264MHz */ + /* B Clock = 132MHz, */ + /* P1 Clock = 66MHz, */ + /* P0 Clock = 33MHz */ + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A2_IsClockMode0 +* @brief Query Clock Mode +* +* Description:
+* Answer ClockMode0 or not +* @param none +* @retval true : clock mode 0 +* @retval false : clock mode 1 +******************************************************************************/ +int RZ_A2_IsClockMode0(void) +{ + /* ClockMode0 */ + return true; +} + +/**************************************************************************//** +* Function Name: RZ_A2_InitBus +* @brief Initialize Bus +* +* Description:
+* Initialize Pin Setting +* @param none +* @retval none +******************************************************************************/ +void RZ_A2_InitBus(void) +{ + /*************************************************************************/ + /* If need Pin Setting before run program, the setting will be wrote here*/ + /*************************************************************************/ + + pin_function(P6_5, 4); // AUDIO_XOUT + + return; +} + +/****************************************************************************** +End of file +******************************************************************************/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct new file mode 100644 index 0000000..928bf8f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct @@ -0,0 +1,139 @@ +#! armcc -E +;************************************************** +; Copyright (c) 2017-2020 ARM Ltd. All rights reserved. +;************************************************** + +; Scatter-file for RTX Example on Versatile Express + +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +; Copyright (c) 2017-2020 Arm Lmimited. +; SPDX-License-Identifier: Apache-2.0 +; +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; +; http://www.apache.org/licenses/LICENSE-2.0 +; +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. +; + +#define __RAM_BASE 0x80000000 +#define __RAM_SIZE 0x00400000 +#define __NV_RAM_BASE 0x80000000 +#define __NV_RAM_SIZE 0x00020000 +#define __TTB_BASE (__NV_RAM_BASE + __NV_RAM_SIZE) +#define __TTB_SIZE (0x4000 + 0x1000) +#define __APP_RAM_START (__TTB_BASE + __TTB_SIZE) + +#define __OCTARAM_BASE 0x60000000 +#define __OCTARAM_SIZE 0x00800000 + +#define __UND_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00008000 +#define __ABT_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x0000F000 +#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x50000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x1000000 +#endif + +#if (MBED_APP_START == 0x50000000) + #define BOOT_LOADER_SIZE (0x00004000) +#else + #define BOOT_LOADER_SIZE (0x00000000) +#endif + +LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM +{ + TTB +0 EMPTY 0x4000 + { } ; Level-1 Translation Table for MMU + + TTB_L2 +0 EMPTY 0x1000 + { } ; Level-2 Translation Table for MMU +} + +LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region +{ +#if (BOOT_LOADER_SIZE != 0x00000000) + BOOT_LOADER_BEGIN MBED_APP_START FIXED + { + * (BOOT_LOADER) + } + + VECTORS (MBED_APP_START + 0x4000) FIXED + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } +#else + VECTORS MBED_APP_START FIXED + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } +#endif + + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) + + NV __NV_RAM_BASE UNINIT __NV_RAM_SIZE ; Page 0 of On-Chip Data Retention RAM + { * (.bss.NoInit) } ; Application RW data Non volatile area + + RAM_CODE __APP_RAM_START + { * (RAM_CODE) } ; Application RAM_CODE + + RW_DATA +0 ALIGN 0x8 + { * (+RW) } ; Application RW data (.data) + + RW_IRAM1 +0 ALIGN 0x10 + { * (+ZI) } ; Application ZI data (.bss) + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; RAM-NC : Internal non-cached RAM region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RW_DATA_NC +0 ALIGN 0x1000 + { * (NC_DATA) } ; Application RW data Non cached area + + ZI_DATA_NC +0 + { * (NC_BSS) } ; Application ZI data Non cached area + + MEMORY_ADJUST +0 ALIGN 0x1000 + { } + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; Heap and Stack + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + ARM_LIB_HEAP +0 EMPTY (__RAM_SIZE - (ImageLimit(MEMORY_ADJUST) - __RAM_BASE) - __STACK_SIZE) + { } + + ARM_LIB_STACK (__RAM_BASE + __RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } + + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; RAM-OCTA : OctaRAM region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RW_DATA_OCTA __OCTARAM_BASE __OCTARAM_SIZE + { * (OCTA_DATA) } ; Application RW data OctaRAM + + ZI_DATA_OCTA +0 + { * (OCTA_BSS) } ; Application ZI data OctaRAM + +} + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/startup_RZ_A2M.S b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/startup_RZ_A2M.S new file mode 100644 index 0000000..02be8ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/startup_RZ_A2M.S @@ -0,0 +1,151 @@ +;/****************************************************************************** +; * @file startup_RZ_A1H.S +; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series +; * +; * @note +; * +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2020 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +__UND_STACK_SIZE EQU 0x00000100 +__SVC_STACK_SIZE EQU 0x00008000 +__ABT_STACK_SIZE EQU 0x00000100 +__FIQ_STACK_SIZE EQU 0x00000100 +__IRQ_STACK_SIZE EQU 0x0000F000 + +USR_MODE EQU 0x10 ; User mode +FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode +IRQ_MODE EQU 0x12 ; Interrupt Request mode +SVC_MODE EQU 0x13 ; Supervisor mode +ABT_MODE EQU 0x17 ; Abort mode +UND_MODE EQU 0x1B ; Undefined Instruction mode +SYS_MODE EQU 0x1F ; System mode + + + PRESERVE8 + ARM + + AREA RESET, CODE, READONLY + +Vectors PROC + EXPORT Vectors + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler + + ENDP + + + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler + IMPORT SystemInit + IMPORT __main + + + ; Mask interrupts + CPSID if + + ; Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + ; Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register + ISB + + ; Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register + + ; Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + ; Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + ;Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + ; Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + ; Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + ; Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + ; Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + ; Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + ; Call SystemInit + IMPORT SystemInit + BL SystemInit + + ; Unmask interrupts + CPSIE if + + ; Call __main + IMPORT __main + BL __main + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/weak_handler.S new file mode 100644 index 0000000..b09ae15 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_ARM_STD/weak_handler.S @@ -0,0 +1,91 @@ +;/* +; * Copyright (c) 2013-2020 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-A Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + +MODE_SVC EQU 0x13 + + PRESERVE8 + THUMB + + AREA |.text|, CODE, READONLY + +IRQ_Handler PROC + EXPORT IRQ_Handler [WEAK] + + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + ENDP + + +Default_Handler PROC + EXPORT Undef_Handler [WEAK] + EXPORT SVC_Handler [WEAK] + EXPORT PAbt_Handler [WEAK] + EXPORT DAbt_Handler [WEAK] + EXPORT FIQ_Handler [WEAK] + +Undef_Handler +SVC_Handler +PAbt_Handler +DAbt_Handler +FIQ_Handler + + B . + + ENDP + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/RZA2M.ld b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/RZA2M.ld new file mode 100644 index 0000000..e073bfa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/RZA2M.ld @@ -0,0 +1,283 @@ +/* Linker script for mbed RZ_A2M */ + +/* Linker script to configure memory regions. */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x50000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x1000000 +#endif + +#define BOOT_LOADER_ADDR (MBED_APP_START) +#if (MBED_APP_START == 0x50000000) + #define BOOT_LOADER_SIZE (0x00004000) +#else + #define BOOT_LOADER_SIZE (0x00000000) +#endif + +#define ROM_ADDR (MBED_APP_START + BOOT_LOADER_SIZE) +#define ROM_SIZE (MBED_APP_SIZE - BOOT_LOADER_SIZE) + +MEMORY +{ + BOOT_LOADER (rx) : ORIGIN = BOOT_LOADER_ADDR, LENGTH = BOOT_LOADER_SIZE + ROM (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE + RAM_NV (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00020000 + L_TTB (rw) : ORIGIN = 0x80020000, LENGTH = 0x00005000 + RAM (rwx) : ORIGIN = 0x80025000, LENGTH = 0x003DB000 + RAM_OCTA (rwx) : ORIGIN = 0x60000000, LENGTH = 0x00800000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ +#if (BOOT_LOADER_SIZE != 0x00000000) + .boot : + { + KEEP(*(.boot_loader)) + } > BOOT_LOADER +#endif + + .text : + { + + Image$$VECTORS$$Base = .; + * (RESET) + + KEEP(*(.isr_vector)) + *(SVC_TABLE) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + Image$$VECTORS$$Limit = .; + + Image$$RO_DATA$$Base = .; + *(.rodata*) + Image$$RO_DATA$$Limit = .; + + KEEP(*(.eh_frame*)) + + __etext = .; + } > ROM + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM + __exidx_end = .; + + .copy.table : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data)) + LONG (LOADADDR(.nc_data)) + LONG (ADDR(.nc_data)) + LONG (SIZEOF(.nc_data)) + LONG (LOADADDR(.octa_data)) + LONG (ADDR(.octa_data)) + LONG (SIZEOF(.octa_data)) + LONG (LOADADDR(.ram_code)) + LONG (ADDR(.ram_code)) + LONG (SIZEOF(.ram_code)) + __copy_table_end__ = .; + } > ROM + + .zero.table : + { + . = ALIGN(8); + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)) + LONG (ADDR(.nc_bss)) + LONG (SIZEOF(.nc_bss)) + LONG (ADDR(.octa_bss)) + LONG (SIZEOF(.octa_bss)) + __zero_table_end__ = .; + } > ROM + + .nv_data (NOLOAD) : + { + *(NV_DATA) + } > RAM_NV + + .ttb : + { + Image$$TTB$$ZI$$Base = .; + . += 0x00004000; + Image$$TTB$$ZI$$Limit = .; + Image$$TTB_L2$$ZI$$Base = .; + . += 0x00001000; + Image$$TTB_L2$$ZI$$Limit = .; + } > L_TTB + + .ram_code : ALIGN( 0x8 ) { + *(RAM_CODE) + *(RAM_CONST) + . = ALIGN( 0x8 ); + } > RAM AT > ROM + Load$$SEC_RAM_CODE$$Base = LOADADDR(.ram_code); + Image$$SEC_RAM_CODE$$Base = ADDR(.ram_code); + Load$$SEC_RAM_CODE$$Length = SIZEOF(.ram_code); + + .data : + { + Image$$RW_DATA$$Base = .; + __data_start__ = .; + *(vtable) + *(.data*) + Image$$RW_DATA$$Limit = .; + + . = ALIGN(8); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + } > RAM AT > ROM + + .bss ALIGN(0x10): + { + Image$$RW_IRAM1$$Base = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$RW_IRAM1$$Limit = .; + } > RAM + + .memory_adjust (NOLOAD): + { + . = ALIGN(0x1000); + } > RAM + + .nc_data : + { + Image$$RW_DATA_NC$$Base = .; + *(NC_DATA) + Image$$RW_DATA_NC$$Limit = .; + } > RAM AT > ROM + + .nc_bss (NOLOAD) : + { + Image$$ZI_DATA_NC$$Base = .; + *(NC_BSS) + Image$$ZI_DATA_NC$$Limit = .; + } > RAM + + .heap ALIGN(0x1000): + { + __end__ = .; + end = __end__; + *(.heap*) + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + __HeapLimit = __StackLimit; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* OctaRAM */ + .octa_data : + { + Image$$RW_DATA_OCTA$$Base = .; + *(OCTA_DATA) + + . = ALIGN(8); + Image$$RW_DATA_OCTA$$Limit = .; + } > RAM_OCTA AT > ROM + + .octa_bss (NOLOAD) : + { + Image$$ZI_DATA_OCTA$$Base = .; + + *(OCTA_BSS) + + . = ALIGN(8); + Image$$ZI_DATA_OCTA$$Limit = .; + } > RAM_OCTA + +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/startup_RZA2M.S b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/startup_RZA2M.S new file mode 100644 index 0000000..5a48ac2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/startup_RZA2M.S @@ -0,0 +1,240 @@ +/* File: startup_ARMCM3.s + * Purpose: startup file for Cortex-M3/M4 devices. Should use with + * GNU Tools for ARM Embedded Processors + * Version: V1.1 + * Date: 17 June 2011 + * + * Copyright (C) 2011-2020 ARM Limited. All rights reserved. + * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + */ +/* Copyright (c) 2011-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ .syntax unified + .extern _start + +@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs + .equ Mode_USR , 0x10 + .equ Mode_FIQ , 0x11 + .equ Mode_IRQ , 0x12 + .equ Mode_SVC , 0x13 + .equ Mode_ABT , 0x17 + .equ Mode_UND , 0x1B + .equ Mode_SYS , 0x1F + + .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled + .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled + .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state + +@ Stack Configuration + + .EQU UND_Stack_Size , 0x00000100 + .EQU SVC_Stack_Size , 0x00008000 + .EQU ABT_Stack_Size , 0x00000100 + .EQU FIQ_Stack_Size , 0x00000100 + .EQU IRQ_Stack_Size , 0x0000F000 + + .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space ISR_Stack_Size +__initial_sp: + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +@ Heap Configuration + + .EQU Heap_Size , 0x00080000 + + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long 0xe59ff018 /* 0x00 */ + .long 0xe59ff018 /* 0x04 */ + .long 0xe59ff018 /* 0x08 */ + .long 0xe59ff018 /* 0x0c */ + .long 0xe59ff018 /* 0x10 */ + .long 0xe59ff018 /* 0x14 */ + .long 0xe59ff018 /* 0x18 */ + .long 0xe59ff018 /* 0x1c */ + + .long Reset_Handler /* 0x20 */ + .long Undef_Handler /* 0x24 */ + .long SVC_Handler /* 0x28 */ + .long PAbt_Handler /* 0x2c */ + .long DAbt_Handler /* 0x30 */ + .long 0 /* Reserved */ + .long IRQ_Handler /* IRQ */ + .long FIQ_Handler /* FIQ */ + + + .size __isr_vector, . - __isr_vector + + .text + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + @ Mask interrupts + CPSID if + + @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + ands r0, r0, #3 +goToSleep: + wfine + bne goToSleep + + @ Reset SCTLR Settings + mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register + isb + + @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register + + @ Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__isr_vector + mcr p15, 0, r0, c12, c0, 0 + +@ Setup Stack for each exceptional mode + ldr r0, =__StackTop + +@ Enter Undefined Instruction Mode and set its Stack Pointer + msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #UND_Stack_Size + +@ Enter Abort Mode and set its Stack Pointer + msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #ABT_Stack_Size + +@ Enter FIQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #FIQ_Stack_Size + +@ Enter IRQ Mode and set its Stack Pointer + msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit) + mov sp, r0 + sub r0, r0, #IRQ_Stack_Size + +@ Enter Supervisor Mode and set its Stack Pointer + msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit) + mov sp, r0 + +@ Enter System Mode to complete initialization and enter kernel + msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) + mov sp, r0 + +@ USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + + @ Unmask interrupts + CPSIE if + +@ data sections copy + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: + +@ bss sections clear + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: + + + ldr r0, =_start + bx r0 + + ldr r0, sf_boot @ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + .word boot_loader + + .pool + .size Reset_Handler, . - Reset_Handler + + .end diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/weak_handler.S new file mode 100644 index 0000000..41f661a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_GCC_ARM/weak_handler.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-A Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + .file "irq_weak.S" + .syntax unified + + .equ MODE_SVC, 0x13 + + .arm + .section ".text" + .align 4 + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler Undef_Handler + def_default_handler SVC_Handler + def_default_handler PAbt_Handler + def_default_handler DAbt_Handler + def_default_handler FIQ_Handler + + + .weak IRQ_Handler + .type IRQ_Handler, %function + .global IRQ_Handler + .fnstart + .cantunwind +IRQ_Handler: + + SUB LR, LR, #4 // Pre-adjust LR + SRSFD SP!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC // Change to SVC mode + PUSH {R0-R3, R12, LR} // Save APCS corruptible registers + + MOV R3, SP // Move SP into R3 + AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 // Adjust stack + PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0 + MOV R4, R0 // Move interrupt ID to R4 + + BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID + CMP R0, #0 // Check if handler address is 0 + BEQ IRQ_End // If 0, end interrupt and return + + CPSIE i // Re-enable interrupts + BLX R0 // Call IRQ handler + CPSID i // Disable interrupts + +IRQ_End: + MOV R0, R4 // Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt // Signal end of interrupt + + POP {R3, R4} // Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 // Unadjust stack + + POP {R0-R3, R12, LR} // Restore stacked APCS registers + RFEFD SP! // Return from IRQ handler + + .fnend + .size IRQ_Handler, .-IRQ_Handler + + .end diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/MBRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/MBRZA1H.icf new file mode 100644 index 0000000..1ab6320 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/MBRZA1H.icf @@ -0,0 +1,81 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = 0x50000000; +} +if (MBED_APP_START == 0x50000000) { + /* No boot loader is used */ + /* define symbol BOOT_LOADER_SIZE = 0x4000; */ + define symbol BOOT_LOADER_SIZE = 0x0; +} else { + define symbol BOOT_LOADER_SIZE = 0x0; +} +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START + BOOT_LOADER_SIZE; + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = 0x1000000; +} +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; + +define symbol __ICFEDIT_region_NvRAM_start__ = 0x80000000; +define symbol __ICFEDIT_region_NvRAM_end__ = 0x8001FFFF; +define symbol __ICFEDIT_region_TTB_start__ = 0x80020000; +define symbol __ICFEDIT_region_TTB_end__ = 0x80023FFF; +define symbol __ICFEDIT_region_TTB_L2_start__ = 0x80024000; +define symbol __ICFEDIT_region_TTB_L2_end__ = 0x80024FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x80025000; +define symbol __ICFEDIT_region_RAM_end__ = 0x803DAFFF; +define symbol __ICFEDIT_region_OctaRAM_start__ = 0x60000000; +define symbol __ICFEDIT_region_OctaRAM_end__ = 0x607FFFFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x00004000; +define symbol __ICFEDIT_size_svcstack__ = 0x00008000; +define symbol __ICFEDIT_size_irqstack__ = 0x00008000; +define symbol __ICFEDIT_size_fiqstack__ = 0x00000100; +define symbol __ICFEDIT_size_undstack__ = 0x00000100; +define symbol __ICFEDIT_size_abtstack__ = 0x00000100; +define symbol __ICFEDIT_size_heap__ = 0x00080000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; + +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region NvRAM_region = mem:[from __ICFEDIT_region_NvRAM_start__ to __ICFEDIT_region_NvRAM_end__]; +define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__]; +define region TTB_L2_region = mem:[from __ICFEDIT_region_TTB_L2_start__ to __ICFEDIT_region_TTB_L2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region OctaRAM_region = mem:[from __ICFEDIT_region_OctaRAM_start__ to __ICFEDIT_region_OctaRAM_end__]; + +define block ROM_FIXED_ORDER with fixed order { ro code, ro data }; +define block NC_RAM with fixed order, alignment = 4K { section NC_DATA, section .mirrorram, section NC_BSS }; +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block C_RAM with alignment = 4K { block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { section NV_DATA }; +do not initialize { section TTB }; +do not initialize { section TTB_L2 }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly, block ROM_FIXED_ORDER }; +place in NvRAM_region { section NV_DATA }; +place in TTB_region { section TTB }; +place in TTB_L2_region { section TTB_L2 }; +place in RAM_region { readwrite, + block NC_RAM, + block C_RAM }; +place in OctaRAM_region { section OCTA_DATA, section OCTA_BSS }; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/startup_RZA2M.S b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/startup_RZA2M.S new file mode 100644 index 0000000..a33c228 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/startup_RZA2M.S @@ -0,0 +1,226 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007-2020 IAR Systems. All rights reserved. +;; +;; $Revision: 49919 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector_table + PUBLIC __RST_Handler + EXTERN Undef_Handler + EXTERN SVC_Handler + EXTERN PAbt_Handler + EXTERN DAbt_Handler + EXTERN IRQ_Handler + PUBLIC FIQ_Handler + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table: ; Make this a DATA label, so that stack usage + ; analysis doesn't consider it an uncalled fun + + ARM + + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + + DATA + +Reset_Addr: DCD __RST_Handler +Undefined_Addr: DCD Undef_Handler +SWI_Addr: DCD SVC_Handler +Prefetch_Addr: DCD PAbt_Handler +Abort_Addr: DCD DAbt_Handler +IRQ_Addr: DCD IRQ_Handler +FIQ_Addr: DCD FIQ_Handler + + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reset execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + EXTERN SystemInit + EXTERN __iar_program_start + REQUIRE __vector_table + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + + + ARM + +__RST_Handler: +?cstartup: + +;;; @ Mask interrupts + CPSID if + +;;; @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR + ands r0, r0, #3 + +goToSleep: + wfine + bne goToSleep + +;;; @ Reset SCTLR Settings + mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register + isb + +;;; @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register + +;; Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__vector_table + mcr p15, 0, r0, c12, c0, 0 + + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR + +#define USR_MODE 0x10 ; User mode +#define FIQ_MODE 0x11 ; Fast Interrupt Request mode +#define IRQ_MODE 0x12 ; Interrupt Request mode +#define SVC_MODE 0x13 ; Supervisor mode +#define ABT_MODE 0x17 ; Abort mode +#define UND_MODE 0x1B ; Undefined Instruction mode +#define SYS_MODE 0x1F ; System mode + + MRS r0, cpsr ; Original PSR value + + ;; Set up the SVC stack pointer. + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the ABT stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #ABT_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the UDF stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #UND_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + +;;; +; USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + +;;; Continue to __cmain for C-level initialization. + + FUNCALL __RST_Handler, __iar_program_start + B __iar_program_start + + + ldr r0, sf_boot ;@ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + DC32 0x00000001 + +FIQ_Handler: + B . + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/weak_handler.S new file mode 100644 index 0000000..c404ba7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/TOOLCHAIN_IAR/weak_handler.S @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-A Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + NAME irq_weak.S + +MODE_SVC EQU 0x13 + + PRESERVE8 + + SECTION .text:CODE:NOROOT(2) + + PUBWEAK Undef_Handler +Undef_Handler + B . + + PUBWEAK SVC_Handler +SVC_Handler + B . + + PUBWEAK PAbt_Handler +PAbt_Handler + B . + + PUBWEAK DAbt_Handler +DAbt_Handler + B . + + PUBWEAK IRQ_Handler +IRQ_Handler + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis.h new file mode 100644 index 0000000..c572e52 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis.h @@ -0,0 +1,29 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2020 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ +/* Copyright (c) 2009-2020 ARM Limited. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MBRZA2M.h" +#include "cmsis_nvic.h" +#include "mbed_rtx.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis_nvic.c new file mode 100644 index 0000000..4010eb6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/cmsis_nvic.c @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015-2020 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +/* Copyright (c) 2015-2020 ARM Limited. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "MBRZA2M.h" +#include "irq_ctrl.h" + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + InterruptHandlerRegister(IRQn, (IRQHandler)vector); +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn); + return vectors; +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/RZ_A2M.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/RZ_A2M.h new file mode 100644 index 0000000..a3aee46 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/RZ_A2M.h @@ -0,0 +1,845 @@ +/****************************************************************************** + * @file RZ_A2M.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version V1.00 + * @data 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __RZ_A2M_H__ +#define __RZ_A2M_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + + /* 16-31 Reserved */ + +/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ + /* 32 - ????? */ + PMUIRQ0_IRQn = 32, + COMMRX0_IRQn = 33, + COMMTX0_IRQn = 34, + CTIIRQ0_IRQn = 35, + + IRQ0_IRQn = 36, + IRQ1_IRQn = 37, + IRQ2_IRQn = 38, + IRQ3_IRQn = 39, + IRQ4_IRQn = 40, + IRQ5_IRQn = 41, + IRQ6_IRQn = 42, + IRQ7_IRQn = 43, + + PL310ERR_IRQn = 44, + + DMAINT0_IRQn = 45, /*!< DMAC Interrupt */ + DMAINT1_IRQn = 46, /*!< DMAC Interrupt */ + DMAINT2_IRQn = 47, /*!< DMAC Interrupt */ + DMAINT3_IRQn = 48, /*!< DMAC Interrupt */ + DMAINT4_IRQn = 49, /*!< DMAC Interrupt */ + DMAINT5_IRQn = 50, /*!< DMAC Interrupt */ + DMAINT6_IRQn = 51, /*!< DMAC Interrupt */ + DMAINT7_IRQn = 52, /*!< DMAC Interrupt */ + DMAINT8_IRQn = 53, /*!< DMAC Interrupt */ + DMAINT9_IRQn = 54, /*!< DMAC Interrupt */ + DMAINT10_IRQn = 55, /*!< DMAC Interrupt */ + DMAINT11_IRQn = 56, /*!< DMAC Interrupt */ + DMAINT12_IRQn = 57, /*!< DMAC Interrupt */ + DMAINT13_IRQn = 58, /*!< DMAC Interrupt */ + DMAINT14_IRQn = 59, /*!< DMAC Interrupt */ + DMAINT15_IRQn = 60, /*!< DMAC Interrupt */ + DMAERR0_IRQn = 61, /*!< DMAC Interrupt */ + DMAERR1_IRQn = 62, /*!< DMAC Interrupt */ + + USBHI0_IRQn = 63, + USBFI0_IRQn = 64, + USBFDMA00_IRQn = 65, + USBFDMA01_IRQn = 66, + USBFDMAERR0_IRQn = 67, + USBHI1_IRQn = 68, + USBFI1_IRQn = 69, + USBFDMA10_IRQn = 70, + USBFDMA11_IRQn = 71, + USBFDMAERR1_IRQn = 72, + + S0_VI_VSYNC0_IRQn = 73, + S0_LO_VSYNC0_IRQn = 74, + S0_VSYNCERR0_IRQn = 75, + GR3_VLINE0_IRQn = 76, + S0_VFIELD0_IRQn = 77, + IV1_VBUFERR0_IRQn = 78, + IV3_VBUFERR0_IRQn = 79, + IV5_VBUFERR0_IRQn = 80, + IV6_VBUFERR0_IRQn = 81, + S0_WLINE0_IRQn = 82, + + IMR2I0_IRQn = 83, + + JEDI_IRQn = 84, + JDTI_IRQn = 85, + + DRWI_IRQn = 86, + + CSII_IRQn = 87, + + OSTMI0_IRQn = 88, /*!< OSTM Interrupt */ + OSTMI1_IRQn = 89, /*!< OSTM Interrupt */ + OSTMI2_IRQn = 90, /*!< OSTM Interrupt */ + + CMI_IRQn = 91, + WTOUT_IRQn = 92, + + ITI_IRQn = 93, + CA9PEI_IRQn = 94, + + TGIA0_IRQn = 95, + TGIB0_IRQn = 96, + TGIC0_IRQn = 97, + TGID0_IRQn = 98, + TGIV0_IRQn = 99, + TGIE0_IRQn = 100, + TGIF0_IRQn = 101, + TGIA1_IRQn = 102, + TGIB1_IRQn = 103, + TGIV1_IRQn = 104, + TGIU1_IRQn = 105, + TGIA2_IRQn = 106, + TGIB2_IRQn = 107, + TGIV2_IRQn = 108, + TGIU2_IRQn = 109, + TGIA3_IRQn = 110, + TGIB3_IRQn = 111, + TGIC3_IRQn = 112, + TGID3_IRQn = 113, + TGIV3_IRQn = 114, + TGIA4_IRQn = 115, + TGIB4_IRQn = 116, + TGIC4_IRQn = 117, + TGID4_IRQn = 118, + TGIV4_IRQn = 119, + TGIU5_IRQn = 120, + TGIV5_IRQn = 121, + TGIW5_IRQn = 122, + TGIA6_IRQn = 123, + TGIB6_IRQn = 124, + TGIC6_IRQn = 125, + TGID6_IRQn = 126, + TGIV6_IRQn = 127, + TGIA7_IRQn = 128, + TGIB7_IRQn = 129, + TGIC7_IRQn = 130, + TGID7_IRQn = 131, + TGIV7_IRQn = 132, + TGIA8_IRQn = 133, + TGIB8_IRQn = 134, + TGIC8_IRQn = 135, + TGID8_IRQn = 136, + TGIV8_IRQn = 137, + + /* 138 Reserved */ + + CCMPA0_IRQn = 139, + CCMPB0_IRQn = 140, + CMPC0_IRQn = 141, + CMPD0_IRQn = 142, + /* 143-145 Reserved */ + CMPE0_IRQn = 146, + CMPF0_IRQn = 147, + ADTRGA0_IRQn = 148, + ADTRGB0_IRQn = 149, + OVF0_IRQn = 150, + UNF0_IRQn = 151, + CCMPA1_IRQn = 152, + CCMPB1_IRQn = 153, + CMPC1_IRQn = 154, + CMPD1_IRQn = 155, + /* 156-158 Reserved */ + CMPE1_IRQn = 159, + CMPF1_IRQn = 160, + ADTRGA1_IRQn = 161, + ADTRGB1_IRQn = 162, + OVF1_IRQn = 163, + UNF1_IRQn = 164, + CCMPA2_IRQn = 165, + CCMPB2_IRQn = 166, + CMPC2_IRQn = 167, + CMPD2_IRQn = 168, + /* 169-171 Reserved */ + CMPE2_IRQn = 172, + CMPF2_IRQn = 173, + ADTRGA2_IRQn = 174, + ADTRGB2_IRQn = 175, + OVF2_IRQn = 176, + UNF2_IRQn = 177, + CCMPA3_IRQn = 178, + CCMPB3_IRQn = 179, + CMPC3_IRQn = 180, + CMPD3_IRQn = 181, + /* 182-184 Reserved */ + CMPE3_IRQn = 185, + CMPF3_IRQn = 186, + ADTRGA3_IRQn = 187, + ADTRGB3_IRQn = 188, + OVF3_IRQn = 189, + UNF3_IRQn = 190, + CCMPA4_IRQn = 191, + CCMPB4_IRQn = 192, + CMPC4_IRQn = 193, + CMPD4_IRQn = 194, + /* 195-197 Reserved */ + CMPE4_IRQn = 198, + CMPF4_IRQn = 199, + ADTRGA4_IRQn = 200, + ADTRGB4_IRQn = 201, + OVF4_IRQn = 202, + UNF4_IRQn = 203, + CCMPA5_IRQn = 204, + CCMPB5_IRQn = 205, + CMPC5_IRQn = 206, + CMPD5_IRQn = 207, + /* 208-210 Reserved */ + CMPE5_IRQn = 211, + CMPF5_IRQn = 212, + ADTRGA5_IRQn = 213, + ADTRGB5_IRQn = 214, + OVF5_IRQn = 215, + UNF5_IRQn = 216, + CCMPA6_IRQn = 217, + CCMPB6_IRQn = 218, + CMPC6_IRQn = 219, + CMPD6_IRQn = 220, + /* 221-223 Reserved */ + CMPE6_IRQn = 224, + CMPF6_IRQn = 225, + ADTRGA6_IRQn = 226, + ADTRGB6_IRQn = 227, + OVF6_IRQn = 228, + UNF6_IRQn = 229, + CCMPA7_IRQn = 230, + CCMPB7_IRQn = 231, + CMPC7_IRQn = 232, + CMPD7_IRQn = 233, + /* 234-236 Reserved */ + CMPE7_IRQn = 237, + CMPF7_IRQn = 238, + ADTRGA7_IRQn = 239, + ADTRGB7_IRQn = 240, + OVF7_IRQn = 241, + UNF7_IRQn = 242, + + OEI1_IRQn = 243, + OEI2_IRQn = 244, + OEI3_IRQn = 245, + OEI4_IRQn = 246, + + S12ADI0_IRQn = 247, + S12GBADI0_IRQn = 248, + S12GCADI0_IRQn = 249, + S12ADCMPAI0_IRQn = 250, + S12ADCMPBI0_IRQn = 251, + + INT_SSIF_INT_REQ_0_IRQn = 252, + INT_SSIF_DMA_RX_0_IRQn = 253, + INT_SSIF_DMA_TX_0_IRQn = 254, + INT_SSIF_INT_REQ_1_IRQn = 255, + INT_SSIF_DMA_RX_1_IRQn = 256, + INT_SSIF_DMA_TX_1_IRQn = 257, + INT_SSIF_INT_REQ_2_IRQn = 258, + INT_SSIF_DMA_RT_2_IRQn = 259, + INT_SSIF_INT_REQ_3_IRQn = 260, + INT_SSIF_DMA_RX_3_IRQn = 261, + INT_SSIF_DMA_TX_3_IRQn = 262, + + SPDIFI_IRQn = 263, + + INTRIICTEI0_IRQn = 264, + INTRIICRI0_IRQn = 265, + INTRIICTI0_IRQn = 266, + INTRIICSPI0_IRQn = 267, + INTRIICSTI0_IRQn = 268, + INTRIICNAKI0_IRQn = 269, + INTRIICALI0_IRQn = 270, + INTRIICTMOI0_IRQn = 271, + INTRIICTEI1_IRQn = 272, + INTRIICRI1_IRQn = 273, + INTRIICTI1_IRQn = 274, + INTRIICSPI1_IRQn = 275, + INTRIICSTI1_IRQn = 276, + INTRIICNAKI1_IRQn = 277, + INTRIICALI1_IRQn = 278, + INTRIICTMOI1_IRQn = 279, + INTRIICTEI2_IRQn = 280, + INTRIICRI2_IRQn = 281, + INTRIICTI2_IRQn = 282, + INTRIICSPI2_IRQn = 283, + INTRIICSTI2_IRQn = 284, + INTRIICNAKI2_IRQn = 285, + INTRIICALI2_IRQn = 286, + INTRIICTMOI2_IRQn = 287, + INTRIICTEI3_IRQn = 288, + INTRIICRI3_IRQn = 289, + INTRIICTI3_IRQn = 290, + INTRIICSPI3_IRQn = 291, + INTRIICSTI3_IRQn = 292, + INTRIICNAKI3_IRQn = 293, + INTRIICALI3_IRQn = 294, + INTRIICTMOI3_IRQn = 295, + + /* 296 Reserved */ + + ERI0_IRQn = 297, + RXI0_IRQn = 298, + TXI0_IRQn = 299, + TEI0_IRQn = 300, + /* 301-302 Reserved */ + ERI1_IRQn = 303, + RXI1_IRQn = 304, + TXI1_IRQn = 305, + TEI1_IRQn = 306, + /* 307-308 Reserved */ + ERI2_IRQn = 309, + RXI2_IRQn = 310, + TXI2_IRQn = 311, + TEI2_IRQn = 312, + /* 313-314 Reserved */ + ERI3_IRQn = 315, + RXI3_IRQn = 316, + TXI3_IRQn = 317, + TEI3_IRQn = 318, + /* 319-320 Reserved */ + ERI4_IRQn = 321, + RXI4_IRQn = 322, + TXI4_IRQn = 323, + TEI4_IRQn = 324, + + /* 325 Reserved */ + + GERI_IRQn = 326, + RFI_IRQn = 327, + CFRXI0_IRQn = 328, + CERI0_IRQn = 329, + CTXI0_IRQn = 330, + CFRXI1_IRQn = 331, + CERI1_IRQn = 332, + CTXI1_IRQn = 333, + + DMA31INT0_IRQn = 334, + DMA31INT1_IRQn = 335, + DMA31INT2_IRQn = 336, + DMA31INT3_IRQn = 337, + DMA31INT4_IRQn = 338, + DMA31INT5_IRQn = 339, + DMA31INT6_IRQn = 340, + DMA31INT7_IRQn = 341, + DMA31INT8_IRQn = 342, + DMA31INT9_IRQn = 343, + + SPEI0_IRQn = 344, + SPRI0_IRQn = 345, + SPTI0_IRQn = 346, + SPEI1_IRQn = 347, + SPRI1_IRQn = 348, + SPTI1_IRQn = 349, + SPEI2_IRQn = 350, + SPRI2_IRQn = 351, + SPTI2_IRQn = 352, + + NAND_IRQn = 353, + + SDHI0_0_IRQn = 354, + /* 355 Reserved */ + SDHI1_0_IRQn = 356, + + /* 357 Reserved */ + + NET_HYPER_IENON_IRQn = 358, + + ARM_IRQn = 359, + PRD_IRQn = 360, + CUP_IRQn = 361, + ARM_S_IRQn = 362, + PRD_S_IRQn = 363, + CUP_S_IRQn = 364, + + SCIM_ERI0_IRQn = 365, + SCIM_RXI0_IRQn = 366, + SCIM_TXI0_IRQn = 367, + SCIM_TEI0_IRQn = 368, + SCIM_ERI1_IRQn = 369, + SCIM_RXI1_IRQn = 370, + SCIM_TXI1_IRQn = 371, + SCIM_TEI1_IRQn = 372, + + EINT0_IRQn = 373, + EINT1_IRQn = 374, + PINT_IRQn = 375, + MINT_IRQn = 376, + IPLS_IRQn = 377, + + CEUI_IRQn = 378, + + H2USB00_ERRINT_IRQn = 379, + H2USB01_ERRINT_IRQn = 380, + H2USB10_ERRINT_IRQn = 381, + H2USB11_ERRINT_IRQn = 382, + H2ETH_ERRINT_IRQn = 383, + X2PERI12_ERRINT_IRQn = 384, + X2PERI34_ERRINT_IRQn = 385, + X2PERI5_ERRINT_IRQn = 386, + X2PERI67_ERRINT_IRQn = 387, + H2IC4_ERRINT_IRQn = 388, + X2DBGR_ERRINT_IRQn = 389, + + DMA31INT10_IRQn = 390, + DMA31INT11_IRQn = 391, + DMA31INT12_IRQn = 392, + DMA31INT13_IRQn = 393, + DMA31INT14_IRQn = 394, + DMA31INT15_IRQn = 395, + + H2XDAV0_ERRINT_IRQn = 396, + H2XDAV1_ERRINT_IRQn = 397, + + ECC0E10_IRQn = 398, + ECC0E20_IRQn = 399, + ECC0OVF0_IRQn = 400, + ECC0E11_IRQn = 401, + ECC0E21_IRQn = 402, + ECC0OVF1_IRQn = 403, + ECC0E12_IRQn = 404, + ECC0E22_IRQn = 405, + ECC0OVF2_IRQn = 406, + ECC0E13_IRQn = 407, + ECC0E23_IRQn = 408, + ECC0OVF3_IRQn = 409, + ECC1E10_IRQn = 410, + ECC1E20_IRQn = 411, + ECC1OVF0_IRQn = 412, + ECC1E11_IRQn = 413, + ECC1E21_IRQn = 414, + ECC1OVF1_IRQn = 415, + ECC1E12_IRQn = 416, + ECC1E22_IRQn = 417, + ECC1OVF2_IRQn = 418, + ECC1E13_IRQn = 419, + ECC1E23_IRQn = 420, + ECC1OVF3_IRQn = 421, + ECC2E10_IRQn = 422, + ECC2E20_IRQn = 423, + ECC2OVF0_IRQn = 424, + ECC2E11_IRQn = 425, + ECC2E21_IRQn = 426, + ECC2OVF1_IRQn = 427, + ECC2E12_IRQn = 428, + ECC2E22_IRQn = 429, + ECC2OVF2_IRQn = 430, + ECC2E13_IRQn = 431, + ECC2E23_IRQn = 432, + ECC2OVF3_IRQn = 433, + + /* 434-445 Reserved */ + + ERRINT_IRQn = 446, + NMLINT_IRQn = 447, + PAE5_IRQn = 448, + PAF5_IRQn = 449, + INTB5_IRQn = 450, + INTA5_IRQn = 451, + PAE4_IRQn = 452, + PAF4_IRQn = 453, + INTB4_IRQn = 454, + INTA4_IRQn = 455, + PAE3_IRQn = 456, + PAF3_IRQn = 457, + INTB3_IRQn = 458, + INTA3_IRQn = 459, + PAE2_IRQn = 460, + PAF2_IRQn = 461, + INTB2_IRQn = 462, + INTA2_IRQn = 463, + PAE1_IRQn = 464, + PAF1_IRQn = 465, + INTB1_IRQn = 466, + INTA1_IRQn = 467, + PAE0_IRQn = 468, + PAF0_IRQn = 469, + INTB0_IRQn = 470, + INTA0_IRQn = 471, + + VINI_IRQn = 472, + + GROUP0_IRQn = 473, + GROUP1_IRQn = 474, + GROUP2_IRQn = 475, + GROUP3_IRQn = 476, + SPIHF_IRQn = 477, + + /* 478-479 Reserved */ + + TINT0_IRQn = 480, + TINT1_IRQn = 481, + TINT2_IRQn = 482, + TINT3_IRQn = 483, + TINT4_IRQn = 484, + TINT5_IRQn = 485, + TINT6_IRQn = 486, + TINT7_IRQn = 487, + TINT8_IRQn = 488, + TINT9_IRQn = 489, + TINT10_IRQn = 490, + TINT11_IRQn = 491, + TINT12_IRQn = 492, + TINT13_IRQn = 493, + TINT14_IRQn = 494, + TINT15_IRQn = 495, + TINT16_IRQn = 496, + TINT17_IRQn = 497, + TINT18_IRQn = 498, + TINT19_IRQn = 499, + TINT20_IRQn = 500, + TINT21_IRQn = 501, + TINT22_IRQn = 502, + TINT23_IRQn = 503, + TINT24_IRQn = 504, + TINT25_IRQn = 505, + TINT26_IRQn = 506, + TINT27_IRQn = 507, + TINT28_IRQn = 508, + TINT29_IRQn = 509, + TINT30_IRQn = 510, + TINT31_IRQn = 511 +} IRQn_Type; + +#define RZ_A2_IRQ_MAX TINT31_IRQn + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +#define RZ_A2_SDRAM (0x0C000000uL) /*!< SDRAM(CS3) area (Cacheable) */ +#define RZ_A2_SPI_IO (0x20000000uL) /*!< SPI multi I/O bus area (Cacheable) */ +#define RZ_A2_HYPER_FLASH (0x30000000uL) /*!< Hyper Flash area (Cacheable) */ +#define RZ_A2_HYPER_RAM (0x40000000uL) /*!< Hyper RAM area (Cacheable) */ +#define RZ_A2_OCTA_FLASH (0x50000000uL) /*!< Octa Flash area (Cacheable) */ +#define RZ_A2_OCTA_RAM (0x60000000uL) /*!< Octa RAM area (Cacheable) */ +#define RZ_A2_ONCHIP_SRAM_BASE (0x80000000UL) /*!< Internal RAM area (Cacheable) */ +#define RZ_A2_PERIPH_BASE0 (0xe8000000UL) /*!< I/O area */ +#define RZ_A2_PERIPH_BASE1 (0x18000000UL) /*!< I/O area */ + +#define RZ_A2_GIC_DISTRIBUTOR_BASE (0xe8221000UL) /*!< (GIC DIST ) Base Address */ +#define RZ_A2_GIC_INTERFACE_BASE (0xe8222000UL) /*!< (GIC CPU IF) Base Address */ +#define RZ_A2_PL310_BASE (0x1F003000uL) /*!< (PL310 ) Base Address */ +//#define RZ_A2_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */ + +/* Virtual address */ +#define RZ_A2_HYPER_FLASH_IO (0xA0000000uL) /*!< Hyper Flash area (I/O area) */ +#define RZ_A2_OCTA_FLASH_NC (0xC0000000uL) /*!< Octa Flash area (Non-Cacheable) */ + +#define GIC_DISTRIBUTOR_BASE RZ_A2_GIC_DISTRIBUTOR_BASE +#define GIC_INTERFACE_BASE RZ_A2_GIC_INTERFACE_BASE +#define L2C_310_BASE RZ_A2_PL310_BASE +//#define TIMER_BASE RZ_A2_PRIVATE_TIMER + +/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ +#define __CA_REV 0x0000U /*!< Core revision r0p0 */ +#define __CORTEX_A 9U /*!< Cortex-A9 Core */ +#if (__FPU_PRESENT != 1) +#undef __FPU_PRESENT +#define __FPU_PRESENT 1U /* FPU present */ +#endif +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ + +#include "core_ca.h" +#include "nvic_wrapper.h" +#include +#include "iodefine.h" + +/******************************************************************************/ +/* Clock Settings */ +/******************************************************************************/ +#define CM0_RENESAS_RZ_A2_CLKIN ( 24000000u) +#define CM0_RENESAS_RZ_A2_I_CLK (528000000u) +#define CM0_RENESAS_RZ_A2_G_CLK (264000000u) +#define CM0_RENESAS_RZ_A2_B_CLK (132000000u) +#define CM0_RENESAS_RZ_A2_P1_CLK ( 66000000u) +#define CM0_RENESAS_RZ_A2_P0_CLK ( 33000000u) + +#define CM1_RENESAS_RZ_A2_CLKIN ( 24000000u) +#define CM1_RENESAS_RZ_A2_I_CLK (528000000u) +#define CM1_RENESAS_RZ_A2_G_CLK (264000000u) +#define CM1_RENESAS_RZ_A2_B_CLK (132000000u) +#define CM1_RENESAS_RZ_A2_P1_CLK ( 66000000u) +#define CM1_RENESAS_RZ_A2_P0_CLK ( 33000000u) + +/******************************************************************************/ +/* CPG Settings */ +/******************************************************************************/ +#define CPG_FRQCR_SHIFT_CKOEN2 (14) +#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) +#define CPG_FRQCR_SHIFT_CKOEN0 (12) +#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) +#define CPG_FRQCR_SHIFT_IFC (8) +#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) + +#define CPG_FRQCR2_SHIFT_GFC (0) +#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) + +#if(0) +#define CPG_STBCR1_BIT_STBY (0x80u) +#define CPG_STBCR1_BIT_DEEP (0x40u) +#define CPG_STBCR2_BIT_HIZ (0x80u) +#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ +#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ +#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ +#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ +#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ +#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ +#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ +#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */ +#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ +#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ +#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ +#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ +#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ +#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ +#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ +#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ +#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ +#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ +#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ +#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ +#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ +#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ +#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ +#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ +#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ +#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */ +#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ +#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ +#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ +#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */ +#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */ +#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ +#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ +#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ +#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ +#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */ +#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ +#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ +#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ +#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ +#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ +#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ +#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ +#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ +#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */ +#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ +#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ +#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ +#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ +#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ +#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ +#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ +#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ +#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ +#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ +#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ +#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ +#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ +#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ +#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ +#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ +#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ +#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ +#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ +#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ +#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ +#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ +#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ +#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ +#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ +#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ +#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ +#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */ +#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */ +#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ +#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ +#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ +#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ +#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ +#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ +#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ +#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ +#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ +#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ +#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ +#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ +#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ +#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ +#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ +#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ +#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ +#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ +#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ +#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ +#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ +#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ +#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ +#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */ +#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */ +#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */ +#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */ +#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */ +#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */ +#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */ +#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */ +#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */ +#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */ +#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */ +#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */ +#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */ +#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */ +#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */ +#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */ +#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */ +#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */ +#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */ +#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */ +#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */ +#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */ +#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */ +#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */ +#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */ +#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */ +#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */ +#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */ +#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */ +#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */ +#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */ +#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */ +#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */ +#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */ +#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */ +#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */ +#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */ +#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */ +#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */ +#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */ +#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */ +#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */ +#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */ +#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */ +#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */ +#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */ +#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */ +#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */ +#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */ +#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */ +#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */ +#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */ +#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */ +#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */ +#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */ +#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */ +#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */ +#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */ +#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */ +#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */ +#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */ +#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */ +#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */ +#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */ +#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */ +#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */ +#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */ +#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */ +#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */ +#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */ +#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */ +#endif + +/******************************************************************************/ +/* GPIO Settings */ +/******************************************************************************/ +#define GPIO_BIT_N0 (1u << 0) +#define GPIO_BIT_N1 (1u << 1) +#define GPIO_BIT_N2 (1u << 2) +#define GPIO_BIT_N3 (1u << 3) +#define GPIO_BIT_N4 (1u << 4) +#define GPIO_BIT_N5 (1u << 5) +#define GPIO_BIT_N6 (1u << 6) +#define GPIO_BIT_N7 (1u << 7) +#define GPIO_BIT_N8 (1u << 8) +#define GPIO_BIT_N9 (1u << 9) +#define GPIO_BIT_N10 (1u << 10) +#define GPIO_BIT_N11 (1u << 11) +#define GPIO_BIT_N12 (1u << 12) +#define GPIO_BIT_N13 (1u << 13) +#define GPIO_BIT_N14 (1u << 14) +#define GPIO_BIT_N15 (1u << 15) + +#define MD_BOOT10_MASK (0x3) + +#define MD_BOOT10_BM0 (0x0) +#define MD_BOOT10_BM1 (0x2) +#define MD_BOOT10_BM3 (0x1) +#define MD_BOOT10_BM4_5 (0x3) + +#define MD_CLK (1u << 2) +#define MD_CLKS (1u << 3) + + +#ifdef __cplusplus +} +#endif + +#endif // __RZ_A1H_H__ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmask.h new file mode 100644 index 0000000..aca950a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmask.h @@ -0,0 +1,94 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef __RZA2M___IOBITMASK_HEADER__ +#define __RZA2M___IOBITMASK_HEADER__ + + +#define IOREG_DIRECT_REG_ACCESS (0xFFFFFFFFuL) +#include "iobitmasks/adc_iobitmask.h" +#include "iobitmasks/bsc_iobitmask.h" +#include "iobitmasks/ceu_iobitmask.h" +#include "iobitmasks/cpg_iobitmask.h" +#include "iobitmasks/csi2link_iobitmask.h" +#include "iobitmasks/dmac_iobitmask.h" +#include "iobitmasks/drpk_iobitmask.h" +#include "iobitmasks/drw_iobitmask.h" +#include "iobitmasks/edmac_iobitmask.h" +#include "iobitmasks/eptpc_iobitmask.h" +#include "iobitmasks/etherc_iobitmask.h" +#include "iobitmasks/gpio_iobitmask.h" +#include "iobitmasks/gpt_iobitmask.h" +#include "iobitmasks/hyper_iobitmask.h" +#include "iobitmasks/imr2_iobitmask.h" +#include "iobitmasks/intc_iobitmask.h" +#include "iobitmasks/irda_iobitmask.h" +#include "iobitmasks/jcu_iobitmask.h" +#include "iobitmasks/lvds_iobitmask.h" +#include "iobitmasks/mtu_iobitmask.h" +#include "iobitmasks/nandc_iobitmask.h" +#include "iobitmasks/octa_iobitmask.h" +#include "iobitmasks/ostm_iobitmask.h" +#include "iobitmasks/pl310_iobitmask.h" +#include "iobitmasks/pmg_iobitmask.h" +#include "iobitmasks/poe3_iobitmask.h" +#include "iobitmasks/poeg_iobitmask.h" +#include "iobitmasks/prr_iobitmask.h" +#include "iobitmasks/ptpedmac_iobitmask.h" +#include "iobitmasks/rcanfd_iobitmask.h" +#include "iobitmasks/rcan_iobitmask.h" +#include "iobitmasks/riic_iobitmask.h" +#include "iobitmasks/rspi_iobitmask.h" +#include "iobitmasks/rtc_iobitmask.h" +#include "iobitmasks/scifa_iobitmask.h" +#include "iobitmasks/scim_iobitmask.h" +#include "iobitmasks/sdmmc_iobitmask.h" +#include "iobitmasks/spdif_iobitmask.h" +#include "iobitmasks/spibsc_iobitmask.h" +#include "iobitmasks/sprite_iobitmask.h" +#include "iobitmasks/ssif_iobitmask.h" +#include "iobitmasks/usb_iobitmask.h" +#include "iobitmasks/vdc6_iobitmask.h" +#include "iobitmasks/vin_iobitmask.h" +#include "iobitmasks/wdt_iobitmask.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/adc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/adc_iobitmask.h new file mode 100644 index 0000000..6b3480a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/adc_iobitmask.h @@ -0,0 +1,186 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef ADC_IOBITMASK_H +#define ADC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define ADC_ADCSR_DBLANS (0x001Fu) +#define ADC_ADCSR_DBLANS_SHIFT (0u) +#define ADC_ADCSR_GBADIE (0x0040u) +#define ADC_ADCSR_GBADIE_SHIFT (6u) +#define ADC_ADCSR_DBLE (0x0080u) +#define ADC_ADCSR_DBLE_SHIFT (7u) +#define ADC_ADCSR_EXTRG (0x0100u) +#define ADC_ADCSR_EXTRG_SHIFT (8u) +#define ADC_ADCSR_TRGE (0x0200u) +#define ADC_ADCSR_TRGE_SHIFT (9u) +#define ADC_ADCSR_ADIE (0x1000u) +#define ADC_ADCSR_ADIE_SHIFT (12u) +#define ADC_ADCSR_ADCS (0x6000u) +#define ADC_ADCSR_ADCS_SHIFT (13u) +#define ADC_ADCSR_ADST (0x8000u) +#define ADC_ADCSR_ADST_SHIFT (15u) +#define ADC_ADANSA0_ANSA0 (0x00FFu) +#define ADC_ADANSA0_ANSA0_SHIFT (0u) +#define ADC_ADADS0_ADS0 (0x00FFu) +#define ADC_ADADS0_ADS0_SHIFT (0u) +#define ADC_ADADC_ADC_2_0 (0x07u) +#define ADC_ADADC_ADC_2_0_SHIFT (0u) +#define ADC_ADADC_AVEE (0x80u) +#define ADC_ADADC_AVEE_SHIFT (7u) +#define ADC_ADCER_ADPRC (0x0006u) +#define ADC_ADCER_ADPRC_SHIFT (1u) +#define ADC_ADCER_ACE (0x0020u) +#define ADC_ADCER_ACE_SHIFT (5u) +#define ADC_ADCER_DIAGVAL (0x0300u) +#define ADC_ADCER_DIAGVAL_SHIFT (8u) +#define ADC_ADCER_DIAGLD (0x0400u) +#define ADC_ADCER_DIAGLD_SHIFT (10u) +#define ADC_ADCER_DIAGM (0x0800u) +#define ADC_ADCER_DIAGM_SHIFT (11u) +#define ADC_ADCER_ADRFMT (0x8000u) +#define ADC_ADCER_ADRFMT_SHIFT (15u) +#define ADC_ADSTRGR_TRSB (0x003Fu) +#define ADC_ADSTRGR_TRSB_SHIFT (0u) +#define ADC_ADSTRGR_TRSA (0x3F00u) +#define ADC_ADSTRGR_TRSA_SHIFT (8u) +#define ADC_ADANSB0_ANSB0 (0x00FFu) +#define ADC_ADANSB0_ANSB0_SHIFT (0u) +#define ADC_ADDBLDR_AD (0xFFFFu) +#define ADC_ADDBLDR_AD_SHIFT (0u) +#define ADC_ADRD_AD (0xFFFFu) +#define ADC_ADRD_AD_SHIFT (0u) +#define ADC_ADDR0_AD (0xFFFFu) +#define ADC_ADDR0_AD_SHIFT (0u) +#define ADC_ADDR1_AD (0xFFFFu) +#define ADC_ADDR1_AD_SHIFT (0u) +#define ADC_ADDR2_AD (0xFFFFu) +#define ADC_ADDR2_AD_SHIFT (0u) +#define ADC_ADDR3_AD (0xFFFFu) +#define ADC_ADDR3_AD_SHIFT (0u) +#define ADC_ADDR4_AD (0xFFFFu) +#define ADC_ADDR4_AD_SHIFT (0u) +#define ADC_ADDR5_AD (0xFFFFu) +#define ADC_ADDR5_AD_SHIFT (0u) +#define ADC_ADDR6_AD (0xFFFFu) +#define ADC_ADDR6_AD_SHIFT (0u) +#define ADC_ADDR7_AD (0xFFFFu) +#define ADC_ADDR7_AD_SHIFT (0u) +#define ADC_ADDISCR_ADNDIS (0x1Fu) +#define ADC_ADDISCR_ADNDIS_SHIFT (0u) +#define ADC_ADGSPCR_PGS (0x0001u) +#define ADC_ADGSPCR_PGS_SHIFT (0u) +#define ADC_ADGSPCR_GBRSCN (0x0002u) +#define ADC_ADGSPCR_GBRSCN_SHIFT (1u) +#define ADC_ADGSPCR_LGRRS (0x4000u) +#define ADC_ADGSPCR_LGRRS_SHIFT (14u) +#define ADC_ADGSPCR_GBRP (0x8000u) +#define ADC_ADGSPCR_GBRP_SHIFT (15u) +#define ADC_ADDBLDRA_AD (0xFFFFu) +#define ADC_ADDBLDRA_AD_SHIFT (0u) +#define ADC_ADDBLDRB_AD (0xFFFFu) +#define ADC_ADDBLDRB_AD_SHIFT (0u) +#define ADC_ADWINMON_MONCOMB (0x01u) +#define ADC_ADWINMON_MONCOMB_SHIFT (0u) +#define ADC_ADWINMON_MONCMPA (0x10u) +#define ADC_ADWINMON_MONCMPA_SHIFT (4u) +#define ADC_ADWINMON_MONCMPB (0x20u) +#define ADC_ADWINMON_MONCMPB_SHIFT (5u) +#define ADC_ADCMPCR_CMPBE (0x0200u) +#define ADC_ADCMPCR_CMPBE_SHIFT (9u) +#define ADC_ADCMPCR_CMPAE (0x0800u) +#define ADC_ADCMPCR_CMPAE_SHIFT (11u) +#define ADC_ADCMPCR_CMPBIE (0x2000u) +#define ADC_ADCMPCR_CMPBIE_SHIFT (13u) +#define ADC_ADCMPCR_WCMPE (0x4000u) +#define ADC_ADCMPCR_WCMPE_SHIFT (14u) +#define ADC_ADCMPCR_CMPAIE (0x8000u) +#define ADC_ADCMPCR_CMPAIE_SHIFT (15u) +#define ADC_ADCMPANSR0_CMPCHA0 (0x00FFu) +#define ADC_ADCMPANSR0_CMPCHA0_SHIFT (0u) +#define ADC_ADCMPLR0_CMPLCHA0 (0x00FFu) +#define ADC_ADCMPLR0_CMPLCHA0_SHIFT (0u) +#define ADC_ADCMPDR0_CMPD0 (0xFFFFu) +#define ADC_ADCMPDR0_CMPD0_SHIFT (0u) +#define ADC_ADCMPDR1_CMPD1 (0xFFFFu) +#define ADC_ADCMPDR1_CMPD1_SHIFT (0u) +#define ADC_ADCMPSR0_CMPSTCHA0 (0x00FFu) +#define ADC_ADCMPSR0_CMPSTCHA0_SHIFT (0u) +#define ADC_ADCMPBNSR_CMPCHB (0x3Fu) +#define ADC_ADCMPBNSR_CMPCHB_SHIFT (0u) +#define ADC_ADCMPBNSR_CMPLB (0x80u) +#define ADC_ADCMPBNSR_CMPLB_SHIFT (7u) +#define ADC_ADWINLLB_CMPLLB (0xFFFFu) +#define ADC_ADWINLLB_CMPLLB_SHIFT (0u) +#define ADC_ADWINULB_CMPULB (0xFFFFu) +#define ADC_ADWINULB_CMPULB_SHIFT (0u) +#define ADC_ADCMPBSR_CMPSTB (0x01u) +#define ADC_ADCMPBSR_CMPSTB_SHIFT (0u) +#define ADC_ADANSC0_ANSC0 (0x00FFu) +#define ADC_ADANSC0_ANSC0_SHIFT (0u) +#define ADC_ADGCTRGR_TRSC (0x3Fu) +#define ADC_ADGCTRGR_TRSC_SHIFT (0u) +#define ADC_ADGCTRGR_GCADIE (0x40u) +#define ADC_ADGCTRGR_GCADIE_SHIFT (6u) +#define ADC_ADGCTRGR_GRCE (0x80u) +#define ADC_ADGCTRGR_GRCE_SHIFT (7u) +#define ADC_ADSSTR0_SST (0xFFu) +#define ADC_ADSSTR0_SST_SHIFT (0u) +#define ADC_ADSSTR1_SST (0xFFu) +#define ADC_ADSSTR1_SST_SHIFT (0u) +#define ADC_ADSSTR2_SST (0xFFu) +#define ADC_ADSSTR2_SST_SHIFT (0u) +#define ADC_ADSSTR3_SST (0xFFu) +#define ADC_ADSSTR3_SST_SHIFT (0u) +#define ADC_ADSSTR4_SST (0xFFu) +#define ADC_ADSSTR4_SST_SHIFT (0u) +#define ADC_ADSSTR5_SST (0xFFu) +#define ADC_ADSSTR5_SST_SHIFT (0u) +#define ADC_ADSSTR6_SST (0xFFu) +#define ADC_ADSSTR6_SST_SHIFT (0u) +#define ADC_ADSSTR7_SST (0xFFu) +#define ADC_ADSSTR7_SST_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/bsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/bsc_iobitmask.h new file mode 100644 index 0000000..828870d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/bsc_iobitmask.h @@ -0,0 +1,296 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef BSC_IOBITMASK_H +#define BSC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define BSC_CMNCR_HIZCNT (0x00000001u) +#define BSC_CMNCR_HIZCNT_SHIFT (0u) +#define BSC_CMNCR_HIZMEM (0x00000002u) +#define BSC_CMNCR_HIZMEM_SHIFT (1u) +#define BSC_CMNCR_DPRTY (0x00000600u) +#define BSC_CMNCR_DPRTY_SHIFT (9u) +#define BSC_CMNCR_AL0 (0x01000000u) +#define BSC_CMNCR_AL0_SHIFT (24u) +#define BSC_CMNCR_TL0 (0x10000000u) +#define BSC_CMNCR_TL0_SHIFT (28u) +#define BSC_CS0BCR_BSZ (0x00000600u) +#define BSC_CS0BCR_BSZ_SHIFT (9u) +#define BSC_CS0BCR_TYPE (0x00007000u) +#define BSC_CS0BCR_TYPE_SHIFT (12u) +#define BSC_CS0BCR_IWRRS (0x00070000u) +#define BSC_CS0BCR_IWRRS_SHIFT (16u) +#define BSC_CS0BCR_IWRRD (0x00380000u) +#define BSC_CS0BCR_IWRRD_SHIFT (19u) +#define BSC_CS0BCR_IWRWS (0x01C00000u) +#define BSC_CS0BCR_IWRWS_SHIFT (22u) +#define BSC_CS0BCR_IWRWD (0x0E000000u) +#define BSC_CS0BCR_IWRWD_SHIFT (25u) +#define BSC_CS0BCR_IWW (0x70000000u) +#define BSC_CS0BCR_IWW_SHIFT (28u) +#define BSC_CS1BCR_BSZ (0x00000600u) +#define BSC_CS1BCR_BSZ_SHIFT (9u) +#define BSC_CS1BCR_TYPE (0x00007000u) +#define BSC_CS1BCR_TYPE_SHIFT (12u) +#define BSC_CS1BCR_IWRRS (0x00070000u) +#define BSC_CS1BCR_IWRRS_SHIFT (16u) +#define BSC_CS1BCR_IWRRD (0x00380000u) +#define BSC_CS1BCR_IWRRD_SHIFT (19u) +#define BSC_CS1BCR_IWRWS (0x01C00000u) +#define BSC_CS1BCR_IWRWS_SHIFT (22u) +#define BSC_CS1BCR_IWRWD (0x0E000000u) +#define BSC_CS1BCR_IWRWD_SHIFT (25u) +#define BSC_CS1BCR_IWW (0x70000000u) +#define BSC_CS1BCR_IWW_SHIFT (28u) +#define BSC_CS2BCR_BSZ (0x00000600u) +#define BSC_CS2BCR_BSZ_SHIFT (9u) +#define BSC_CS2BCR_TYPE (0x00007000u) +#define BSC_CS2BCR_TYPE_SHIFT (12u) +#define BSC_CS2BCR_IWRRS (0x00070000u) +#define BSC_CS2BCR_IWRRS_SHIFT (16u) +#define BSC_CS2BCR_IWRRD (0x00380000u) +#define BSC_CS2BCR_IWRRD_SHIFT (19u) +#define BSC_CS2BCR_IWRWS (0x01C00000u) +#define BSC_CS2BCR_IWRWS_SHIFT (22u) +#define BSC_CS2BCR_IWRWD (0x0E000000u) +#define BSC_CS2BCR_IWRWD_SHIFT (25u) +#define BSC_CS2BCR_IWW (0x70000000u) +#define BSC_CS2BCR_IWW_SHIFT (28u) +#define BSC_CS3BCR_BSZ (0x00000600u) +#define BSC_CS3BCR_BSZ_SHIFT (9u) +#define BSC_CS3BCR_TYPE (0x00007000u) +#define BSC_CS3BCR_TYPE_SHIFT (12u) +#define BSC_CS3BCR_IWRRS (0x00070000u) +#define BSC_CS3BCR_IWRRS_SHIFT (16u) +#define BSC_CS3BCR_IWRRD (0x00380000u) +#define BSC_CS3BCR_IWRRD_SHIFT (19u) +#define BSC_CS3BCR_IWRWS (0x01C00000u) +#define BSC_CS3BCR_IWRWS_SHIFT (22u) +#define BSC_CS3BCR_IWRWD (0x0E000000u) +#define BSC_CS3BCR_IWRWD_SHIFT (25u) +#define BSC_CS3BCR_IWW (0x70000000u) +#define BSC_CS3BCR_IWW_SHIFT (28u) +#define BSC_CS4BCR_BSZ (0x00000600u) +#define BSC_CS4BCR_BSZ_SHIFT (9u) +#define BSC_CS4BCR_TYPE (0x00007000u) +#define BSC_CS4BCR_TYPE_SHIFT (12u) +#define BSC_CS4BCR_IWRRS (0x00070000u) +#define BSC_CS4BCR_IWRRS_SHIFT (16u) +#define BSC_CS4BCR_IWRRD (0x00380000u) +#define BSC_CS4BCR_IWRRD_SHIFT (19u) +#define BSC_CS4BCR_IWRWS (0x01C00000u) +#define BSC_CS4BCR_IWRWS_SHIFT (22u) +#define BSC_CS4BCR_IWRWD (0x0E000000u) +#define BSC_CS4BCR_IWRWD_SHIFT (25u) +#define BSC_CS4BCR_IWW (0x70000000u) +#define BSC_CS4BCR_IWW_SHIFT (28u) +#define BSC_CS5BCR_BSZ (0x00000600u) +#define BSC_CS5BCR_BSZ_SHIFT (9u) +#define BSC_CS5BCR_TYPE (0x00007000u) +#define BSC_CS5BCR_TYPE_SHIFT (12u) +#define BSC_CS5BCR_IWRRS (0x00070000u) +#define BSC_CS5BCR_IWRRS_SHIFT (16u) +#define BSC_CS5BCR_IWRRD (0x00380000u) +#define BSC_CS5BCR_IWRRD_SHIFT (19u) +#define BSC_CS5BCR_IWRWS (0x01C00000u) +#define BSC_CS5BCR_IWRWS_SHIFT (22u) +#define BSC_CS5BCR_IWRWD (0x0E000000u) +#define BSC_CS5BCR_IWRWD_SHIFT (25u) +#define BSC_CS5BCR_IWW (0x70000000u) +#define BSC_CS5BCR_IWW_SHIFT (28u) +#define BSC_CS0WCR_0_HW (0x00000003u) +#define BSC_CS0WCR_0_HW_SHIFT (0u) +#define BSC_CS0WCR_0_WM (0x00000040u) +#define BSC_CS0WCR_0_WM_SHIFT (6u) +#define BSC_CS0WCR_0_WR (0x00000780u) +#define BSC_CS0WCR_0_WR_SHIFT (7u) +#define BSC_CS0WCR_0_SW (0x00001800u) +#define BSC_CS0WCR_0_SW_SHIFT (11u) +#define BSC_CS0WCR_0_BAS (0x00100000u) +#define BSC_CS0WCR_0_BAS_SHIFT (20u) +#define BSC_CS0WCR_1_WM (0x00000040u) +#define BSC_CS0WCR_1_WM_SHIFT (6u) +#define BSC_CS0WCR_1_W (0x00000780u) +#define BSC_CS0WCR_1_W_SHIFT (7u) +#define BSC_CS0WCR_1_BW (0x00030000u) +#define BSC_CS0WCR_1_BW_SHIFT (16u) +#define BSC_CS0WCR_1_BST (0x00300000u) +#define BSC_CS0WCR_1_BST_SHIFT (20u) +#define BSC_CS0WCR_2_WM (0x00000040u) +#define BSC_CS0WCR_2_WM_SHIFT (6u) +#define BSC_CS0WCR_2_W (0x00000780u) +#define BSC_CS0WCR_2_W_SHIFT (7u) +#define BSC_CS0WCR_2_BW (0x00030000u) +#define BSC_CS0WCR_2_BW_SHIFT (16u) +#define BSC_CS1WCR_0_HW (0x00000003u) +#define BSC_CS1WCR_0_HW_SHIFT (0u) +#define BSC_CS1WCR_0_WM (0x00000040u) +#define BSC_CS1WCR_0_WM_SHIFT (6u) +#define BSC_CS1WCR_0_WR (0x00000780u) +#define BSC_CS1WCR_0_WR_SHIFT (7u) +#define BSC_CS1WCR_0_SW (0x00001800u) +#define BSC_CS1WCR_0_SW_SHIFT (11u) +#define BSC_CS1WCR_0_WW (0x00070000u) +#define BSC_CS1WCR_0_WW_SHIFT (16u) +#define BSC_CS1WCR_0_BAS (0x00100000u) +#define BSC_CS1WCR_0_BAS_SHIFT (20u) +#define BSC_CS2WCR_0_WM (0x00000040u) +#define BSC_CS2WCR_0_WM_SHIFT (6u) +#define BSC_CS2WCR_0_WR (0x00000780u) +#define BSC_CS2WCR_0_WR_SHIFT (7u) +#define BSC_CS2WCR_0_BAS (0x00100000u) +#define BSC_CS2WCR_0_BAS_SHIFT (20u) +#define BSC_CS2WCR_1_A2CL (0x00000180u) +#define BSC_CS2WCR_1_A2CL_SHIFT (7u) +#define BSC_CS3WCR_1_WTRC (0x00000003u) +#define BSC_CS3WCR_1_WTRC_SHIFT (0u) +#define BSC_CS3WCR_1_TRWL (0x00000018u) +#define BSC_CS3WCR_1_TRWL_SHIFT (3u) +#define BSC_CS3WCR_1_A3CL (0x00000180u) +#define BSC_CS3WCR_1_A3CL_SHIFT (7u) +#define BSC_CS3WCR_1_WTRCD (0x00000C00u) +#define BSC_CS3WCR_1_WTRCD_SHIFT (10u) +#define BSC_CS3WCR_1_WTRP (0x00006000u) +#define BSC_CS3WCR_1_WTRP_SHIFT (13u) +#define BSC_CS3WCR_0_WM (0x00000040u) +#define BSC_CS3WCR_0_WM_SHIFT (6u) +#define BSC_CS3WCR_0_WR (0x00000780u) +#define BSC_CS3WCR_0_WR_SHIFT (7u) +#define BSC_CS3WCR_0_BAS (0x00100000u) +#define BSC_CS3WCR_0_BAS_SHIFT (20u) +#define BSC_CS4WCR_0_HW (0x00000003u) +#define BSC_CS4WCR_0_HW_SHIFT (0u) +#define BSC_CS4WCR_0_WM (0x00000040u) +#define BSC_CS4WCR_0_WM_SHIFT (6u) +#define BSC_CS4WCR_0_WR (0x00000780u) +#define BSC_CS4WCR_0_WR_SHIFT (7u) +#define BSC_CS4WCR_0_SW (0x00001800u) +#define BSC_CS4WCR_0_SW_SHIFT (11u) +#define BSC_CS4WCR_0_WW (0x00070000u) +#define BSC_CS4WCR_0_WW_SHIFT (16u) +#define BSC_CS4WCR_0_BAS (0x00100000u) +#define BSC_CS4WCR_0_BAS_SHIFT (20u) +#define BSC_CS4WCR_1_HW (0x00000003u) +#define BSC_CS4WCR_1_HW_SHIFT (0u) +#define BSC_CS4WCR_1_WM (0x00000040u) +#define BSC_CS4WCR_1_WM_SHIFT (6u) +#define BSC_CS4WCR_1_W (0x00000780u) +#define BSC_CS4WCR_1_W_SHIFT (7u) +#define BSC_CS4WCR_1_SW (0x00001800u) +#define BSC_CS4WCR_1_SW_SHIFT (11u) +#define BSC_CS4WCR_1_BW (0x00030000u) +#define BSC_CS4WCR_1_BW_SHIFT (16u) +#define BSC_CS4WCR_1_BST (0x00300000u) +#define BSC_CS4WCR_1_BST_SHIFT (20u) +#define BSC_CS5WCR_0_HW (0x00000003u) +#define BSC_CS5WCR_0_HW_SHIFT (0u) +#define BSC_CS5WCR_0_WM (0x00000040u) +#define BSC_CS5WCR_0_WM_SHIFT (6u) +#define BSC_CS5WCR_0_WR (0x00000780u) +#define BSC_CS5WCR_0_WR_SHIFT (7u) +#define BSC_CS5WCR_0_SW (0x00001800u) +#define BSC_CS5WCR_0_SW_SHIFT (11u) +#define BSC_CS5WCR_0_WW (0x00070000u) +#define BSC_CS5WCR_0_WW_SHIFT (16u) +#define BSC_CS5WCR_0_MPXWBAS (0x00100000u) +#define BSC_CS5WCR_0_MPXWBAS_SHIFT (20u) +#define BSC_CS5WCR_0_SZSEL (0x00200000u) +#define BSC_CS5WCR_0_SZSEL_SHIFT (21u) +#define BSC_SDCR_A3COL (0x00000003u) +#define BSC_SDCR_A3COL_SHIFT (0u) +#define BSC_SDCR_A3ROW (0x00000018u) +#define BSC_SDCR_A3ROW_SHIFT (3u) +#define BSC_SDCR_BACTV (0x00000100u) +#define BSC_SDCR_BACTV_SHIFT (8u) +#define BSC_SDCR_PDOWN (0x00000200u) +#define BSC_SDCR_PDOWN_SHIFT (9u) +#define BSC_SDCR_RMODE (0x00000400u) +#define BSC_SDCR_RMODE_SHIFT (10u) +#define BSC_SDCR_RFSH (0x00000800u) +#define BSC_SDCR_RFSH_SHIFT (11u) +#define BSC_SDCR_DEEP (0x00002000u) +#define BSC_SDCR_DEEP_SHIFT (13u) +#define BSC_SDCR_A2COL (0x00030000u) +#define BSC_SDCR_A2COL_SHIFT (16u) +#define BSC_SDCR_A2ROW (0x00180000u) +#define BSC_SDCR_A2ROW_SHIFT (19u) +#define BSC_RTCSR_RRC (0x00000007u) +#define BSC_RTCSR_RRC_SHIFT (0u) +#define BSC_RTCSR_CKS (0x00000038u) +#define BSC_RTCSR_CKS_SHIFT (3u) +#define BSC_RTCSR_CMIE (0x00000040u) +#define BSC_RTCSR_CMIE_SHIFT (6u) +#define BSC_RTCSR_CMF (0x00000080u) +#define BSC_RTCSR_CMF_SHIFT (7u) +#define BSC_TOSTR_CS0TOSTF (0x00000001u) +#define BSC_TOSTR_CS0TOSTF_SHIFT (0u) +#define BSC_TOSTR_CS1TOSTF (0x00000002u) +#define BSC_TOSTR_CS1TOSTF_SHIFT (1u) +#define BSC_TOSTR_CS2TOSTF (0x00000004u) +#define BSC_TOSTR_CS2TOSTF_SHIFT (2u) +#define BSC_TOSTR_CS3TOSTF (0x00000008u) +#define BSC_TOSTR_CS3TOSTF_SHIFT (3u) +#define BSC_TOSTR_CS4TOSTF (0x00000010u) +#define BSC_TOSTR_CS4TOSTF_SHIFT (4u) +#define BSC_TOSTR_CS5TOSTF (0x00000020u) +#define BSC_TOSTR_CS5TOSTF_SHIFT (5u) +#define BSC_TOENR_CS0TOEN (0x00000001u) +#define BSC_TOENR_CS0TOEN_SHIFT (0u) +#define BSC_TOENR_CS1TOEN (0x00000002u) +#define BSC_TOENR_CS1TOEN_SHIFT (1u) +#define BSC_TOENR_CS2TOEN (0x00000004u) +#define BSC_TOENR_CS2TOEN_SHIFT (2u) +#define BSC_TOENR_CS3TOEN (0x00000008u) +#define BSC_TOENR_CS3TOEN_SHIFT (3u) +#define BSC_TOENR_CS4TOEN (0x00000010u) +#define BSC_TOENR_CS4TOEN_SHIFT (4u) +#define BSC_TOENR_CS5TOEN (0x00000020u) +#define BSC_TOENR_CS5TOEN_SHIFT (5u) +#define BSC_ACADJ_SDRIDLY (0x0000000Fu) +#define BSC_ACADJ_SDRIDLY_SHIFT (0u) +#define BSC_ACADJ_SDRODLY (0x000F0000u) +#define BSC_ACADJ_SDRODLY_SHIFT (16u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ceu_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ceu_iobitmask.h new file mode 100644 index 0000000..22eeea5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ceu_iobitmask.h @@ -0,0 +1,330 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef CEU_IOBITMASK_H +#define CEU_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define CEU_CAPSR_CE (0x00000001u) +#define CEU_CAPSR_CE_SHIFT (0u) +#define CEU_CAPSR_CPKIL (0x00010000u) +#define CEU_CAPSR_CPKIL_SHIFT (16u) +#define CEU_CAPCR_CTNCP (0x00010000u) +#define CEU_CAPCR_CTNCP_SHIFT (16u) +#define CEU_CAPCR_MTCM (0x00300000u) +#define CEU_CAPCR_MTCM_SHIFT (20u) +#define CEU_CAPCR_FDRP (0xFF000000u) +#define CEU_CAPCR_FDRP_SHIFT (24u) +#define CEU_CAMCR_HDPOL (0x00000001u) +#define CEU_CAMCR_HDPOL_SHIFT (0u) +#define CEU_CAMCR_VDPOL (0x00000002u) +#define CEU_CAMCR_VDPOL_SHIFT (1u) +#define CEU_CAMCR_JPG (0x00000030u) +#define CEU_CAMCR_JPG_SHIFT (4u) +#define CEU_CAMCR_DTARY (0x00000300u) +#define CEU_CAMCR_DTARY_SHIFT (8u) +#define CEU_CAMCR_DTIF (0x00001000u) +#define CEU_CAMCR_DTIF_SHIFT (12u) +#define CEU_CAMCR_FLDPOL (0x00010000u) +#define CEU_CAMCR_FLDPOL_SHIFT (16u) +#define CEU_CAMCR_DSEL (0x01000000u) +#define CEU_CAMCR_DSEL_SHIFT (24u) +#define CEU_CAMCR_FLDSEL (0x02000000u) +#define CEU_CAMCR_FLDSEL_SHIFT (25u) +#define CEU_CAMCR_HDSEL (0x04000000u) +#define CEU_CAMCR_HDSEL_SHIFT (26u) +#define CEU_CAMCR_VDSEL (0x08000000u) +#define CEU_CAMCR_VDSEL_SHIFT (27u) +#define CEU_CMCYR_HCYL (0x00003FFFu) +#define CEU_CMCYR_HCYL_SHIFT (0u) +#define CEU_CMCYR_VCYL (0x3FFF0000u) +#define CEU_CMCYR_VCYL_SHIFT (16u) +#define CEU_CAMOR_A_HOFST (0x00001FFFu) +#define CEU_CAMOR_A_HOFST_SHIFT (0u) +#define CEU_CAMOR_A_VOFST (0x0FFF0000u) +#define CEU_CAMOR_A_VOFST_SHIFT (16u) +#define CEU_CAPWR_A_HWDTH (0x00001FFFu) +#define CEU_CAPWR_A_HWDTH_SHIFT (0u) +#define CEU_CAPWR_A_VWDTH (0x0FFF0000u) +#define CEU_CAPWR_A_VWDTH_SHIFT (16u) +#define CEU_CAIFR_FCI (0x00000003u) +#define CEU_CAIFR_FCI_SHIFT (0u) +#define CEU_CAIFR_CIM (0x00000010u) +#define CEU_CAIFR_CIM_SHIFT (4u) +#define CEU_CAIFR_IFS (0x00000100u) +#define CEU_CAIFR_IFS_SHIFT (8u) +#define CEU_CRCNTR_RC (0x00000001u) +#define CEU_CRCNTR_RC_SHIFT (0u) +#define CEU_CRCNTR_RS (0x00000002u) +#define CEU_CRCNTR_RS_SHIFT (1u) +#define CEU_CRCNTR_RVS (0x00000010u) +#define CEU_CRCNTR_RVS_SHIFT (4u) +#define CEU_CRCMPR_RA (0x00000001u) +#define CEU_CRCMPR_RA_SHIFT (0u) +#define CEU_CFLCR_A_HFRAC (0x00000FFFu) +#define CEU_CFLCR_A_HFRAC_SHIFT (0u) +#define CEU_CFLCR_A_HMANT (0x0000F000u) +#define CEU_CFLCR_A_HMANT_SHIFT (12u) +#define CEU_CFLCR_A_VFRAC (0x0FFF0000u) +#define CEU_CFLCR_A_VFRAC_SHIFT (16u) +#define CEU_CFLCR_A_VMANT (0xF0000000u) +#define CEU_CFLCR_A_VMANT_SHIFT (28u) +#define CEU_CFSZR_A_HFCLP (0x00000FFFu) +#define CEU_CFSZR_A_HFCLP_SHIFT (0u) +#define CEU_CFSZR_A_VFCLP (0x0FFF0000u) +#define CEU_CFSZR_A_VFCLP_SHIFT (16u) +#define CEU_CDWDR_A_CHDW (0x00001FFFu) +#define CEU_CDWDR_A_CHDW_SHIFT (0u) +#define CEU_CDAYR_A_CAYR (0xFFFFFFFFu) +#define CEU_CDAYR_A_CAYR_SHIFT (0u) +#define CEU_CDACR_A_CACR (0xFFFFFFFFu) +#define CEU_CDACR_A_CACR_SHIFT (0u) +#define CEU_CDBYR_A_CBYR (0xFFFFFFFFu) +#define CEU_CDBYR_A_CBYR_SHIFT (0u) +#define CEU_CDBCR_A_CBCR (0xFFFFFFFFu) +#define CEU_CDBCR_A_CBCR_SHIFT (0u) +#define CEU_CBDSR_A_CBVS (0x007FFFFFu) +#define CEU_CBDSR_A_CBVS_SHIFT (0u) +#define CEU_CFWCR_FWE (0x00000001u) +#define CEU_CFWCR_FWE_SHIFT (0u) +#define CEU_CFWCR_FWV (0xFFFFFFE0u) +#define CEU_CFWCR_FWV_SHIFT (5u) +#define CEU_CLFCR_A_LPF (0x00000001u) +#define CEU_CLFCR_A_LPF_SHIFT (0u) +#define CEU_CDOCR_A_COBS (0x00000001u) +#define CEU_CDOCR_A_COBS_SHIFT (0u) +#define CEU_CDOCR_A_COWS (0x00000002u) +#define CEU_CDOCR_A_COWS_SHIFT (1u) +#define CEU_CDOCR_A_COLS (0x00000004u) +#define CEU_CDOCR_A_COLS_SHIFT (2u) +#define CEU_CDOCR_A_CDS (0x00000010u) +#define CEU_CDOCR_A_CDS_SHIFT (4u) +#define CEU_CDOCR_A_CBE (0x00010000u) +#define CEU_CDOCR_A_CBE_SHIFT (16u) +#define CEU_CEIER_CPEIE (0x00000001u) +#define CEU_CEIER_CPEIE_SHIFT (0u) +#define CEU_CEIER_CFEIE (0x00000002u) +#define CEU_CEIER_CFEIE_SHIFT (1u) +#define CEU_CEIER_IGRWIE (0x00000010u) +#define CEU_CEIER_IGRWIE_SHIFT (4u) +#define CEU_CEIER_HDIE (0x00000100u) +#define CEU_CEIER_HDIE_SHIFT (8u) +#define CEU_CEIER_VDIE (0x00000200u) +#define CEU_CEIER_VDIE_SHIFT (9u) +#define CEU_CEIER_CPBE1IE (0x00001000u) +#define CEU_CEIER_CPBE1IE_SHIFT (12u) +#define CEU_CEIER_CPBE2IE (0x00002000u) +#define CEU_CEIER_CPBE2IE_SHIFT (13u) +#define CEU_CEIER_CPBE3IE (0x00004000u) +#define CEU_CEIER_CPBE3IE_SHIFT (14u) +#define CEU_CEIER_CPBE4IE (0x00008000u) +#define CEU_CEIER_CPBE4IE_SHIFT (15u) +#define CEU_CEIER_CDTOFIE (0x00010000u) +#define CEU_CEIER_CDTOFIE_SHIFT (16u) +#define CEU_CEIER_IGHSIE (0x00020000u) +#define CEU_CEIER_IGHSIE_SHIFT (17u) +#define CEU_CEIER_IGVSIE (0x00040000u) +#define CEU_CEIER_IGVSIE_SHIFT (18u) +#define CEU_CEIER_VBPIE (0x00100000u) +#define CEU_CEIER_VBPIE_SHIFT (20u) +#define CEU_CEIER_FWFIE (0x00800000u) +#define CEU_CEIER_FWFIE_SHIFT (23u) +#define CEU_CEIER_NHDIE (0x01000000u) +#define CEU_CEIER_NHDIE_SHIFT (24u) +#define CEU_CEIER_NVDIE (0x02000000u) +#define CEU_CEIER_NVDIE_SHIFT (25u) +#define CEU_CETCR_CPE (0x00000001u) +#define CEU_CETCR_CPE_SHIFT (0u) +#define CEU_CETCR_CFE (0x00000002u) +#define CEU_CETCR_CFE_SHIFT (1u) +#define CEU_CETCR_IGRW (0x00000010u) +#define CEU_CETCR_IGRW_SHIFT (4u) +#define CEU_CETCR_HD (0x00000100u) +#define CEU_CETCR_HD_SHIFT (8u) +#define CEU_CETCR_VD (0x00000200u) +#define CEU_CETCR_VD_SHIFT (9u) +#define CEU_CETCR_CPBE1 (0x00001000u) +#define CEU_CETCR_CPBE1_SHIFT (12u) +#define CEU_CETCR_CPBE2 (0x00002000u) +#define CEU_CETCR_CPBE2_SHIFT (13u) +#define CEU_CETCR_CPBE3 (0x00004000u) +#define CEU_CETCR_CPBE3_SHIFT (14u) +#define CEU_CETCR_CPBE4 (0x00008000u) +#define CEU_CETCR_CPBE4_SHIFT (15u) +#define CEU_CETCR_CDTOF (0x00010000u) +#define CEU_CETCR_CDTOF_SHIFT (16u) +#define CEU_CETCR_IGHS (0x00020000u) +#define CEU_CETCR_IGHS_SHIFT (17u) +#define CEU_CETCR_IGVS (0x00040000u) +#define CEU_CETCR_IGVS_SHIFT (18u) +#define CEU_CETCR_VBP (0x00100000u) +#define CEU_CETCR_VBP_SHIFT (20u) +#define CEU_CETCR_FWF (0x00800000u) +#define CEU_CETCR_FWF_SHIFT (23u) +#define CEU_CETCR_NHD (0x01000000u) +#define CEU_CETCR_NHD_SHIFT (24u) +#define CEU_CETCR_NVD (0x02000000u) +#define CEU_CETCR_NVD_SHIFT (25u) +#define CEU_CSTSR_CPTON (0x00000001u) +#define CEU_CSTSR_CPTON_SHIFT (0u) +#define CEU_CSTSR_CPFLD (0x00010000u) +#define CEU_CSTSR_CPFLD_SHIFT (16u) +#define CEU_CSTSR_CRST (0x01000000u) +#define CEU_CSTSR_CRST_SHIFT (24u) +#define CEU_CDSSR_CDSS (0xFFFFFFFFu) +#define CEU_CDSSR_CDSS_SHIFT (0u) +#define CEU_CDAYR2_A_CAYR2 (0xFFFFFFFFu) +#define CEU_CDAYR2_A_CAYR2_SHIFT (0u) +#define CEU_CDACR2_A_CACR2 (0xFFFFFFFFu) +#define CEU_CDACR2_A_CACR2_SHIFT (0u) +#define CEU_CDBYR2_A_CBYR2 (0xFFFFFFFFu) +#define CEU_CDBYR2_A_CBYR2_SHIFT (0u) +#define CEU_CDBCR2_A_CBCR2 (0xFFFFFFFFu) +#define CEU_CDBCR2_A_CBCR2_SHIFT (0u) +#define CEU_CAMOR_B_HOFST (0x00001FFFu) +#define CEU_CAMOR_B_HOFST_SHIFT (0u) +#define CEU_CAMOR_B_VOFST (0x0FFF0000u) +#define CEU_CAMOR_B_VOFST_SHIFT (16u) +#define CEU_CAPWR_B_HWDTH (0x00001FFFu) +#define CEU_CAPWR_B_HWDTH_SHIFT (0u) +#define CEU_CAPWR_B_VWDTH (0x0FFF0000u) +#define CEU_CAPWR_B_VWDTH_SHIFT (16u) +#define CEU_CFLCR_B_HFRAC (0x00000FFFu) +#define CEU_CFLCR_B_HFRAC_SHIFT (0u) +#define CEU_CFLCR_B_HMANT (0x0000F000u) +#define CEU_CFLCR_B_HMANT_SHIFT (12u) +#define CEU_CFLCR_B_VFRAC (0x0FFF0000u) +#define CEU_CFLCR_B_VFRAC_SHIFT (16u) +#define CEU_CFLCR_B_VMANT (0xF0000000u) +#define CEU_CFLCR_B_VMANT_SHIFT (28u) +#define CEU_CFSZR_B_HFCLP (0x00000FFFu) +#define CEU_CFSZR_B_HFCLP_SHIFT (0u) +#define CEU_CFSZR_B_VFCLP (0x0FFF0000u) +#define CEU_CFSZR_B_VFCLP_SHIFT (16u) +#define CEU_CDWDR_B_CHDW (0x00001FFFu) +#define CEU_CDWDR_B_CHDW_SHIFT (0u) +#define CEU_CDAYR_B_CAYR (0xFFFFFFFFu) +#define CEU_CDAYR_B_CAYR_SHIFT (0u) +#define CEU_CDACR_B_CACR (0xFFFFFFFFu) +#define CEU_CDACR_B_CACR_SHIFT (0u) +#define CEU_CDBYR_B_CBYR (0xFFFFFFFFu) +#define CEU_CDBYR_B_CBYR_SHIFT (0u) +#define CEU_CDBCR_B_CBCR (0xFFFFFFFFu) +#define CEU_CDBCR_B_CBCR_SHIFT (0u) +#define CEU_CBDSR_B_CBVS (0x007FFFFFu) +#define CEU_CBDSR_B_CBVS_SHIFT (0u) +#define CEU_CLFCR_B_LPF (0x00000001u) +#define CEU_CLFCR_B_LPF_SHIFT (0u) +#define CEU_CDOCR_B_COBS (0x00000001u) +#define CEU_CDOCR_B_COBS_SHIFT (0u) +#define CEU_CDOCR_B_COWS (0x00000002u) +#define CEU_CDOCR_B_COWS_SHIFT (1u) +#define CEU_CDOCR_B_COLS (0x00000004u) +#define CEU_CDOCR_B_COLS_SHIFT (2u) +#define CEU_CDOCR_B_CDS (0x00000010u) +#define CEU_CDOCR_B_CDS_SHIFT (4u) +#define CEU_CDOCR_B_CBE (0x00010000u) +#define CEU_CDOCR_B_CBE_SHIFT (16u) +#define CEU_CDAYR2_B_CAYR2 (0xFFFFFFFFu) +#define CEU_CDAYR2_B_CAYR2_SHIFT (0u) +#define CEU_CDACR2_B_CACR2 (0xFFFFFFFFu) +#define CEU_CDACR2_B_CACR2_SHIFT (0u) +#define CEU_CDBYR2_B_CBYR2 (0xFFFFFFFFu) +#define CEU_CDBYR2_B_CBYR2_SHIFT (0u) +#define CEU_CDBCR2_B_CBCR2 (0xFFFFFFFFu) +#define CEU_CDBCR2_B_CBCR2_SHIFT (0u) +#define CEU_CAMOR_M_HOFST (0x00001FFFu) +#define CEU_CAMOR_M_HOFST_SHIFT (0u) +#define CEU_CAMOR_M_VOFST (0x0FFF0000u) +#define CEU_CAMOR_M_VOFST_SHIFT (16u) +#define CEU_CAPWR_M_HWDTH (0x00001FFFu) +#define CEU_CAPWR_M_HWDTH_SHIFT (0u) +#define CEU_CAPWR_M_VWDTH (0x0FFF0000u) +#define CEU_CAPWR_M_VWDTH_SHIFT (16u) +#define CEU_CFLCR_M_HFRAC (0x00000FFFu) +#define CEU_CFLCR_M_HFRAC_SHIFT (0u) +#define CEU_CFLCR_M_HMANT (0x0000F000u) +#define CEU_CFLCR_M_HMANT_SHIFT (12u) +#define CEU_CFLCR_M_VFRAC (0x0FFF0000u) +#define CEU_CFLCR_M_VFRAC_SHIFT (16u) +#define CEU_CFLCR_M_VMANT (0xF0000000u) +#define CEU_CFLCR_M_VMANT_SHIFT (28u) +#define CEU_CFSZR_M_HFCLP (0x00000FFFu) +#define CEU_CFSZR_M_HFCLP_SHIFT (0u) +#define CEU_CFSZR_M_VFCLP (0x0FFF0000u) +#define CEU_CFSZR_M_VFCLP_SHIFT (16u) +#define CEU_CDWDR_M_CHDW (0x00001FFFu) +#define CEU_CDWDR_M_CHDW_SHIFT (0u) +#define CEU_CDAYR_M_CAYR (0xFFFFFFFFu) +#define CEU_CDAYR_M_CAYR_SHIFT (0u) +#define CEU_CDACR_M_CACR (0xFFFFFFFFu) +#define CEU_CDACR_M_CACR_SHIFT (0u) +#define CEU_CDBYR_M_CBYR (0xFFFFFFFFu) +#define CEU_CDBYR_M_CBYR_SHIFT (0u) +#define CEU_CDBCR_M_CBCR (0xFFFFFFFFu) +#define CEU_CDBCR_M_CBCR_SHIFT (0u) +#define CEU_CBDSR_M_CBVS (0x007FFFFFu) +#define CEU_CBDSR_M_CBVS_SHIFT (0u) +#define CEU_CLFCR_M_LPF (0x00000001u) +#define CEU_CLFCR_M_LPF_SHIFT (0u) +#define CEU_CDOCR_M_COBS (0x00000001u) +#define CEU_CDOCR_M_COBS_SHIFT (0u) +#define CEU_CDOCR_M_COWS (0x00000002u) +#define CEU_CDOCR_M_COWS_SHIFT (1u) +#define CEU_CDOCR_M_COLS (0x00000004u) +#define CEU_CDOCR_M_COLS_SHIFT (2u) +#define CEU_CDOCR_M_CDS (0x00000010u) +#define CEU_CDOCR_M_CDS_SHIFT (4u) +#define CEU_CDOCR_M_CBE (0x00010000u) +#define CEU_CDOCR_M_CBE_SHIFT (16u) +#define CEU_CDAYR2_M_CAYR2 (0xFFFFFFFFu) +#define CEU_CDAYR2_M_CAYR2_SHIFT (0u) +#define CEU_CDACR2_M_CACR2 (0xFFFFFFFFu) +#define CEU_CDACR2_M_CACR2_SHIFT (0u) +#define CEU_CDBYR2_M_CBYR2 (0xFFFFFFFFu) +#define CEU_CDBYR2_M_CBYR2_SHIFT (0u) +#define CEU_CDBCR2_M_CBCR2 (0xFFFFFFFFu) +#define CEU_CDBCR2_M_CBCR2_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/cpg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/cpg_iobitmask.h new file mode 100644 index 0000000..13f60df --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/cpg_iobitmask.h @@ -0,0 +1,302 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef CPG_IOBITMASK_H +#define CPG_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define CPG_FRQCR_PFC (0x0003u) +#define CPG_FRQCR_PFC_SHIFT (0u) +#define CPG_FRQCR_BFC (0x0030u) +#define CPG_FRQCR_BFC_SHIFT (4u) +#define CPG_FRQCR_IFC (0x0300u) +#define CPG_FRQCR_IFC_SHIFT (8u) +#define CPG_FRQCR_CKOEN (0x3000u) +#define CPG_FRQCR_CKOEN_SHIFT (12u) +#define CPG_FRQCR_CKOEN2 (0x4000u) +#define CPG_FRQCR_CKOEN2_SHIFT (14u) +#define CPG_CPUSTS_ISBUSY (0x10u) +#define CPG_CPUSTS_ISBUSY_SHIFT (4u) +#define CPG_STBCR1_DEEP (0x40u) +#define CPG_STBCR1_DEEP_SHIFT (6u) +#define CPG_STBCR1_STBY (0x80u) +#define CPG_STBCR1_STBY_SHIFT (7u) +#define CPG_STBCR2_MSTP20 (0x01u) +#define CPG_STBCR2_MSTP20_SHIFT (0u) +#define CPG_STBCR2_HIZ (0x80u) +#define CPG_STBCR2_HIZ_SHIFT (7u) +#define CPG_STBREQ1_STBRQ10 (0x01u) +#define CPG_STBREQ1_STBRQ10_SHIFT (0u) +#define CPG_STBREQ1_STBRQ11 (0x02u) +#define CPG_STBREQ1_STBRQ11_SHIFT (1u) +#define CPG_STBREQ1_STBRQ12 (0x04u) +#define CPG_STBREQ1_STBRQ12_SHIFT (2u) +#define CPG_STBREQ1_STBRQ13 (0x08u) +#define CPG_STBREQ1_STBRQ13_SHIFT (3u) +#define CPG_STBREQ1_STBRQ15 (0x20u) +#define CPG_STBREQ1_STBRQ15_SHIFT (5u) +#define CPG_STBREQ2_STBRQ20 (0x01u) +#define CPG_STBREQ2_STBRQ20_SHIFT (0u) +#define CPG_STBREQ2_STBRQ21 (0x02u) +#define CPG_STBREQ2_STBRQ21_SHIFT (1u) +#define CPG_STBREQ2_STBRQ22 (0x04u) +#define CPG_STBREQ2_STBRQ22_SHIFT (2u) +#define CPG_STBREQ2_STBRQ23 (0x08u) +#define CPG_STBREQ2_STBRQ23_SHIFT (3u) +#define CPG_STBREQ2_STBRQ24 (0x10u) +#define CPG_STBREQ2_STBRQ24_SHIFT (4u) +#define CPG_STBREQ2_STBRQ25 (0x20u) +#define CPG_STBREQ2_STBRQ25_SHIFT (5u) +#define CPG_STBREQ2_STBRQ26 (0x40u) +#define CPG_STBREQ2_STBRQ26_SHIFT (6u) +#define CPG_STBREQ2_STBRQ27 (0x80u) +#define CPG_STBREQ2_STBRQ27_SHIFT (7u) +#define CPG_STBREQ3_STBRQ30 (0x01u) +#define CPG_STBREQ3_STBRQ30_SHIFT (0u) +#define CPG_STBREQ3_STBRQ31 (0x02u) +#define CPG_STBREQ3_STBRQ31_SHIFT (1u) +#define CPG_STBREQ3_STBRQ32 (0x04u) +#define CPG_STBREQ3_STBRQ32_SHIFT (2u) +#define CPG_STBREQ3_STBRQ33 (0x08u) +#define CPG_STBREQ3_STBRQ33_SHIFT (3u) +#define CPG_STBACK1_STBAK10 (0x01u) +#define CPG_STBACK1_STBAK10_SHIFT (0u) +#define CPG_STBACK1_STBAK11 (0x02u) +#define CPG_STBACK1_STBAK11_SHIFT (1u) +#define CPG_STBACK1_STBAK12 (0x04u) +#define CPG_STBACK1_STBAK12_SHIFT (2u) +#define CPG_STBACK1_STBAK13 (0x08u) +#define CPG_STBACK1_STBAK13_SHIFT (3u) +#define CPG_STBACK1_STBAK15 (0x20u) +#define CPG_STBACK1_STBAK15_SHIFT (5u) +#define CPG_STBACK2_STBAK20 (0x01u) +#define CPG_STBACK2_STBAK20_SHIFT (0u) +#define CPG_STBACK2_STBAK21 (0x02u) +#define CPG_STBACK2_STBAK21_SHIFT (1u) +#define CPG_STBACK2_STBAK22 (0x04u) +#define CPG_STBACK2_STBAK22_SHIFT (2u) +#define CPG_STBACK2_STBAK23 (0x08u) +#define CPG_STBACK2_STBAK23_SHIFT (3u) +#define CPG_STBACK2_STBAK24 (0x10u) +#define CPG_STBACK2_STBAK24_SHIFT (4u) +#define CPG_STBACK2_STBAK25 (0x20u) +#define CPG_STBACK2_STBAK25_SHIFT (5u) +#define CPG_STBACK2_STBAK26 (0x40u) +#define CPG_STBACK2_STBAK26_SHIFT (6u) +#define CPG_STBACK2_STBAK27 (0x80u) +#define CPG_STBACK2_STBAK27_SHIFT (7u) +#define CPG_STBACK3_STBAK30 (0x01u) +#define CPG_STBACK3_STBAK30_SHIFT (0u) +#define CPG_STBACK3_STBAK31 (0x02u) +#define CPG_STBACK3_STBAK31_SHIFT (1u) +#define CPG_STBACK3_STBAK32 (0x04u) +#define CPG_STBACK3_STBAK32_SHIFT (2u) +#define CPG_STBACK3_STBAK33 (0x08u) +#define CPG_STBACK3_STBAK33_SHIFT (3u) +#define CPG_CKIOSEL_CKIOSEL (0x0003u) +#define CPG_CKIOSEL_CKIOSEL_SHIFT (0u) +#define CPG_SCLKSEL_SPICR (0x0003u) +#define CPG_SCLKSEL_SPICR_SHIFT (0u) +#define CPG_SCLKSEL_HYMCR (0x0030u) +#define CPG_SCLKSEL_HYMCR_SHIFT (4u) +#define CPG_SCLKSEL_OCTCR (0x0300u) +#define CPG_SCLKSEL_OCTCR_SHIFT (8u) +#define CPG_SYSCR1_VRAME0 (0x01u) +#define CPG_SYSCR1_VRAME0_SHIFT (0u) +#define CPG_SYSCR1_VRAME1 (0x02u) +#define CPG_SYSCR1_VRAME1_SHIFT (1u) +#define CPG_SYSCR1_VRAME2 (0x04u) +#define CPG_SYSCR1_VRAME2_SHIFT (2u) +#define CPG_SYSCR1_VRAME3 (0x08u) +#define CPG_SYSCR1_VRAME3_SHIFT (3u) +#define CPG_SYSCR1_VRAME4 (0x10u) +#define CPG_SYSCR1_VRAME4_SHIFT (4u) +#define CPG_SYSCR2_VRAMWE0 (0x01u) +#define CPG_SYSCR2_VRAMWE0_SHIFT (0u) +#define CPG_SYSCR2_VRAMWE1 (0x02u) +#define CPG_SYSCR2_VRAMWE1_SHIFT (1u) +#define CPG_SYSCR2_VRAMWE2 (0x04u) +#define CPG_SYSCR2_VRAMWE2_SHIFT (2u) +#define CPG_SYSCR2_VRAMWE3 (0x08u) +#define CPG_SYSCR2_VRAMWE3_SHIFT (3u) +#define CPG_SYSCR2_VRAMWE4 (0x10u) +#define CPG_SYSCR2_VRAMWE4_SHIFT (4u) +#define CPG_SYSCR3_RRAMWE0 (0x01u) +#define CPG_SYSCR3_RRAMWE0_SHIFT (0u) +#define CPG_SYSCR3_RRAMWE1 (0x02u) +#define CPG_SYSCR3_RRAMWE1_SHIFT (1u) +#define CPG_SYSCR3_RRAMWE2 (0x04u) +#define CPG_SYSCR3_RRAMWE2_SHIFT (2u) +#define CPG_SYSCR3_RRAMWE3 (0x08u) +#define CPG_SYSCR3_RRAMWE3_SHIFT (3u) +#define CPG_STBCR3_MSTP30 (0x01u) +#define CPG_STBCR3_MSTP30_SHIFT (0u) +#define CPG_STBCR3_MSTP31 (0x02u) +#define CPG_STBCR3_MSTP31_SHIFT (1u) +#define CPG_STBCR3_MSTP32 (0x04u) +#define CPG_STBCR3_MSTP32_SHIFT (2u) +#define CPG_STBCR3_MSTP33 (0x08u) +#define CPG_STBCR3_MSTP33_SHIFT (3u) +#define CPG_STBCR3_MSTP34 (0x10u) +#define CPG_STBCR3_MSTP34_SHIFT (4u) +#define CPG_STBCR3_MSTP35 (0x20u) +#define CPG_STBCR3_MSTP35_SHIFT (5u) +#define CPG_STBCR3_MSTP36 (0x40u) +#define CPG_STBCR3_MSTP36_SHIFT (6u) +#define CPG_STBCR4_MSTP40 (0x01u) +#define CPG_STBCR4_MSTP40_SHIFT (0u) +#define CPG_STBCR4_MSTP41 (0x02u) +#define CPG_STBCR4_MSTP41_SHIFT (1u) +#define CPG_STBCR4_MSTP42 (0x04u) +#define CPG_STBCR4_MSTP42_SHIFT (2u) +#define CPG_STBCR4_MSTP43 (0x08u) +#define CPG_STBCR4_MSTP43_SHIFT (3u) +#define CPG_STBCR4_MSTP44 (0x10u) +#define CPG_STBCR4_MSTP44_SHIFT (4u) +#define CPG_STBCR4_MSTP45 (0x20u) +#define CPG_STBCR4_MSTP45_SHIFT (5u) +#define CPG_STBCR4_MSTP46 (0x40u) +#define CPG_STBCR4_MSTP46_SHIFT (6u) +#define CPG_STBCR4_MSTP47 (0x80u) +#define CPG_STBCR4_MSTP47_SHIFT (7u) +#define CPG_STBCR5_MSTP51 (0x02u) +#define CPG_STBCR5_MSTP51_SHIFT (1u) +#define CPG_STBCR5_MSTP52 (0x04u) +#define CPG_STBCR5_MSTP52_SHIFT (2u) +#define CPG_STBCR5_MSTP53 (0x08u) +#define CPG_STBCR5_MSTP53_SHIFT (3u) +#define CPG_STBCR5_MSTP56 (0x40u) +#define CPG_STBCR5_MSTP56_SHIFT (6u) +#define CPG_STBCR5_MSTP57 (0x80u) +#define CPG_STBCR5_MSTP57_SHIFT (7u) +#define CPG_STBCR6_MSTP60 (0x01u) +#define CPG_STBCR6_MSTP60_SHIFT (0u) +#define CPG_STBCR6_MSTP61 (0x02u) +#define CPG_STBCR6_MSTP61_SHIFT (1u) +#define CPG_STBCR6_MSTP62 (0x04u) +#define CPG_STBCR6_MSTP62_SHIFT (2u) +#define CPG_STBCR6_MSTP63 (0x08u) +#define CPG_STBCR6_MSTP63_SHIFT (3u) +#define CPG_STBCR6_MSTP64 (0x10u) +#define CPG_STBCR6_MSTP64_SHIFT (4u) +#define CPG_STBCR6_MSTP65 (0x20u) +#define CPG_STBCR6_MSTP65_SHIFT (5u) +#define CPG_STBCR6_MSTP66 (0x40u) +#define CPG_STBCR6_MSTP66_SHIFT (6u) +#define CPG_STBCR7_MSTP70 (0x01u) +#define CPG_STBCR7_MSTP70_SHIFT (0u) +#define CPG_STBCR7_MSTP71 (0x02u) +#define CPG_STBCR7_MSTP71_SHIFT (1u) +#define CPG_STBCR7_MSTP72 (0x04u) +#define CPG_STBCR7_MSTP72_SHIFT (2u) +#define CPG_STBCR7_MSTP73 (0x08u) +#define CPG_STBCR7_MSTP73_SHIFT (3u) +#define CPG_STBCR7_MSTP75 (0x20u) +#define CPG_STBCR7_MSTP75_SHIFT (5u) +#define CPG_STBCR7_MSTP76 (0x40u) +#define CPG_STBCR7_MSTP76_SHIFT (6u) +#define CPG_STBCR7_MSTP77 (0x80u) +#define CPG_STBCR7_MSTP77_SHIFT (7u) +#define CPG_STBCR8_MSTP81 (0x02u) +#define CPG_STBCR8_MSTP81_SHIFT (1u) +#define CPG_STBCR8_MSTP83 (0x08u) +#define CPG_STBCR8_MSTP83_SHIFT (3u) +#define CPG_STBCR8_MSTP84 (0x10u) +#define CPG_STBCR8_MSTP84_SHIFT (4u) +#define CPG_STBCR8_MSTP85 (0x20u) +#define CPG_STBCR8_MSTP85_SHIFT (5u) +#define CPG_STBCR8_MSTP86 (0x40u) +#define CPG_STBCR8_MSTP86_SHIFT (6u) +#define CPG_STBCR8_MSTP87 (0x80u) +#define CPG_STBCR8_MSTP87_SHIFT (7u) +#define CPG_STBCR9_MSTP90 (0x01u) +#define CPG_STBCR9_MSTP90_SHIFT (0u) +#define CPG_STBCR9_MSTP91 (0x02u) +#define CPG_STBCR9_MSTP91_SHIFT (1u) +#define CPG_STBCR9_MSTP92 (0x04u) +#define CPG_STBCR9_MSTP92_SHIFT (2u) +#define CPG_STBCR9_MSTP93 (0x08u) +#define CPG_STBCR9_MSTP93_SHIFT (3u) +#define CPG_STBCR9_MSTP95 (0x20u) +#define CPG_STBCR9_MSTP95_SHIFT (5u) +#define CPG_STBCR9_MSTP96 (0x40u) +#define CPG_STBCR9_MSTP96_SHIFT (6u) +#define CPG_STBCR9_MSTP97 (0x80u) +#define CPG_STBCR9_MSTP97_SHIFT (7u) +#define CPG_STBCR10_MSTP100 (0x01u) +#define CPG_STBCR10_MSTP100_SHIFT (0u) +#define CPG_STBCR10_MSTP101 (0x02u) +#define CPG_STBCR10_MSTP101_SHIFT (1u) +#define CPG_STBCR10_MSTP102 (0x04u) +#define CPG_STBCR10_MSTP102_SHIFT (2u) +#define CPG_STBCR10_MSTP103 (0x08u) +#define CPG_STBCR10_MSTP103_SHIFT (3u) +#define CPG_STBCR10_MSTP104 (0x10u) +#define CPG_STBCR10_MSTP104_SHIFT (4u) +#define CPG_STBCR10_MSTP107 (0x80u) +#define CPG_STBCR10_MSTP107_SHIFT (7u) +#define CPG_SWRSTCR1_SRST10 (0x01u) +#define CPG_SWRSTCR1_SRST10_SHIFT (0u) +#define CPG_SWRSTCR1_SRST11 (0x02u) +#define CPG_SWRSTCR1_SRST11_SHIFT (1u) +#define CPG_SWRSTCR1_SRST12 (0x04u) +#define CPG_SWRSTCR1_SRST12_SHIFT (2u) +#define CPG_SWRSTCR1_SRST13 (0x08u) +#define CPG_SWRSTCR1_SRST13_SHIFT (3u) +#define CPG_SWRSTCR1_AXTALE (0x80u) +#define CPG_SWRSTCR1_AXTALE_SHIFT (7u) +#define CPG_SWRSTCR2_SRST21 (0x02u) +#define CPG_SWRSTCR2_SRST21_SHIFT (1u) +#define CPG_SWRSTCR2_SRST22 (0x04u) +#define CPG_SWRSTCR2_SRST22_SHIFT (2u) +#define CPG_SWRSTCR2_SRST23 (0x08u) +#define CPG_SWRSTCR2_SRST23_SHIFT (3u) +#define CPG_SWRSTCR2_SRST24 (0x10u) +#define CPG_SWRSTCR2_SRST24_SHIFT (4u) +#define CPG_SWRSTCR2_SRST25 (0x20u) +#define CPG_SWRSTCR2_SRST25_SHIFT (5u) +#define CPG_SWRSTCR2_SRST26 (0x40u) +#define CPG_SWRSTCR2_SRST26_SHIFT (6u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/csi2link_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/csi2link_iobitmask.h new file mode 100644 index 0000000..7da6978 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/csi2link_iobitmask.h @@ -0,0 +1,368 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef CSI2LINK_IOBITMASK_H +#define CSI2LINK_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define CSI2LINK_TREF_TREF (0x00000001u) +#define CSI2LINK_TREF_TREF_SHIFT (0u) +#define CSI2LINK_SRST_SRST (0x00000001u) +#define CSI2LINK_SRST_SRST_SHIFT (0u) +#define CSI2LINK_PHYCNT_ENABLE_0 (0x00000001u) +#define CSI2LINK_PHYCNT_ENABLE_0_SHIFT (0u) +#define CSI2LINK_PHYCNT_ENABLE_1 (0x00000002u) +#define CSI2LINK_PHYCNT_ENABLE_1_SHIFT (1u) +#define CSI2LINK_PHYCNT_ENABLECLK (0x00000010u) +#define CSI2LINK_PHYCNT_ENABLECLK_SHIFT (4u) +#define CSI2LINK_PHYCNT_RSTZ (0x00010000u) +#define CSI2LINK_PHYCNT_RSTZ_SHIFT (16u) +#define CSI2LINK_PHYCNT_SHUTDOWNZ (0x00020000u) +#define CSI2LINK_PHYCNT_SHUTDOWNZ_SHIFT (17u) +#define CSI2LINK_CHKSUM_CRC_EN (0x00000001u) +#define CSI2LINK_CHKSUM_CRC_EN_SHIFT (0u) +#define CSI2LINK_CHKSUM_ECC_EN (0x00000002u) +#define CSI2LINK_CHKSUM_ECC_EN_SHIFT (1u) +#define CSI2LINK_VCDT_SEL_DT (0x0000003Fu) +#define CSI2LINK_VCDT_SEL_DT_SHIFT (0u) +#define CSI2LINK_VCDT_SEL_DT_ON (0x00000040u) +#define CSI2LINK_VCDT_SEL_DT_ON_SHIFT (6u) +#define CSI2LINK_VCDT_SEL_VC (0x00000300u) +#define CSI2LINK_VCDT_SEL_VC_SHIFT (8u) +#define CSI2LINK_VCDT_VCDT_EN (0x00008000u) +#define CSI2LINK_VCDT_VCDT_EN_SHIFT (15u) +#define CSI2LINK_FRDT_DT_FE (0x003F0000u) +#define CSI2LINK_FRDT_DT_FE_SHIFT (16u) +#define CSI2LINK_FRDT_DT_FS (0x3F000000u) +#define CSI2LINK_FRDT_DT_FS_SHIFT (24u) +#define CSI2LINK_FLD_FLD_EN (0x00000001u) +#define CSI2LINK_FLD_FLD_EN_SHIFT (0u) +#define CSI2LINK_FLD_FLD_DET_SEL (0x00000030u) +#define CSI2LINK_FLD_FLD_DET_SEL_SHIFT (4u) +#define CSI2LINK_FLD_FLD_NUM (0xFFFF0000u) +#define CSI2LINK_FLD_FLD_NUM_SHIFT (16u) +#define CSI2LINK_ASTBY_AUTO_STANDBY_EN (0x0000001Fu) +#define CSI2LINK_ASTBY_AUTO_STANDBY_EN_SHIFT (0u) +#define CSI2LINK_ASTBY_VD_MSK_EN (0x00000020u) +#define CSI2LINK_ASTBY_VD_MSK_EN_SHIFT (5u) +#define CSI2LINK_ASTBY_VD_MSK_CYCLE (0x00003F00u) +#define CSI2LINK_ASTBY_VD_MSK_CYCLE_SHIFT (8u) +#define CSI2LINK_LNGDT0_LNGDT0 (0xFFFFFFFFu) +#define CSI2LINK_LNGDT0_LNGDT0_SHIFT (0u) +#define CSI2LINK_LNGDT1_LNGDT1 (0xFFFFFFFFu) +#define CSI2LINK_LNGDT1_LNGDT1_SHIFT (0u) +#define CSI2LINK_INTEN_IEN (0xFFFFFFFFu) +#define CSI2LINK_INTEN_IEN_SHIFT (0u) +#define CSI2LINK_INTCLOSE_ICL (0xFFFFFFFFu) +#define CSI2LINK_INTCLOSE_ICL_SHIFT (0u) +#define CSI2LINK_INTSTATE_IST (0xFFFFFFFFu) +#define CSI2LINK_INTSTATE_IST_SHIFT (0u) +#define CSI2LINK_INTERRSTATE_IEST (0x0000FFFFu) +#define CSI2LINK_INTERRSTATE_IEST_SHIFT (0u) +#define CSI2LINK_SHPDAT_DT (0x0000003Fu) +#define CSI2LINK_SHPDAT_DT_SHIFT (0u) +#define CSI2LINK_SHPDAT_VC (0x000000C0u) +#define CSI2LINK_SHPDAT_VC_SHIFT (6u) +#define CSI2LINK_SHPDAT_DATA (0x00FFFF00u) +#define CSI2LINK_SHPDAT_DATA_SHIFT (8u) +#define CSI2LINK_SHPDAT_ECC (0xFF000000u) +#define CSI2LINK_SHPDAT_ECC_SHIFT (24u) +#define CSI2LINK_SHPCNT_NUM (0x0000000Fu) +#define CSI2LINK_SHPCNT_NUM_SHIFT (0u) +#define CSI2LINK_SHPCNT_OVF (0x00010000u) +#define CSI2LINK_SHPCNT_OVF_SHIFT (16u) +#define CSI2LINK_LINKCNT_REG_MONI_PACT_EN (0x02000000u) +#define CSI2LINK_LINKCNT_REG_MONI_PACT_EN_SHIFT (25u) +#define CSI2LINK_LINKCNT_MONITOR_EN (0x80000000u) +#define CSI2LINK_LINKCNT_MONITOR_EN_SHIFT (31u) +#define CSI2LINK_LSWAP_L0SEL (0x00000003u) +#define CSI2LINK_LSWAP_L0SEL_SHIFT (0u) +#define CSI2LINK_LSWAP_L1SEL (0x0000000Cu) +#define CSI2LINK_LSWAP_L1SEL_SHIFT (2u) +#define CSI2LINK_PHEERM_ERRCONTROL_0 (0x00000001u) +#define CSI2LINK_PHEERM_ERRCONTROL_0_SHIFT (0u) +#define CSI2LINK_PHEERM_ERRCONTROL_1 (0x00000002u) +#define CSI2LINK_PHEERM_ERRCONTROL_1_SHIFT (1u) +#define CSI2LINK_PHEERM_ERRESC_0 (0x00000100u) +#define CSI2LINK_PHEERM_ERRESC_0_SHIFT (8u) +#define CSI2LINK_PHEERM_ERRESC_1 (0x00000200u) +#define CSI2LINK_PHEERM_ERRESC_1_SHIFT (9u) +#define CSI2LINK_PHEERM_CL_ERRCONTROL (0x00001000u) +#define CSI2LINK_PHEERM_CL_ERRCONTROL_SHIFT (12u) +#define CSI2LINK_PHCLM_STOPSTATECLK (0x00000001u) +#define CSI2LINK_PHCLM_STOPSTATECLK_SHIFT (0u) +#define CSI2LINK_PHCLM_RXCLKACTIVEHS (0x00000002u) +#define CSI2LINK_PHCLM_RXCLKACTIVEHS_SHIFT (1u) +#define CSI2LINK_PHCLM_RXULPSCLKNOT (0x00000004u) +#define CSI2LINK_PHCLM_RXULPSCLKNOT_SHIFT (2u) +#define CSI2LINK_PHCLM_ULPSACTIVENOTCLK (0x00000008u) +#define CSI2LINK_PHCLM_ULPSACTIVENOTCLK_SHIFT (3u) +#define CSI2LINK_PHDLM_STOPSTATEDATA_0 (0x00000001u) +#define CSI2LINK_PHDLM_STOPSTATEDATA_0_SHIFT (0u) +#define CSI2LINK_PHDLM_STOPSTATEDATA_1 (0x00000002u) +#define CSI2LINK_PHDLM_STOPSTATEDATA_1_SHIFT (1u) +#define CSI2LINK_PHDLM_RXULPSESC_0 (0x00000100u) +#define CSI2LINK_PHDLM_RXULPSESC_0_SHIFT (8u) +#define CSI2LINK_PHDLM_RXULPSESC_1 (0x00000200u) +#define CSI2LINK_PHDLM_RXULPSESC_1_SHIFT (9u) +#define CSI2LINK_PHDLM_ULPSACTIVENOT_0 (0x00001000u) +#define CSI2LINK_PHDLM_ULPSACTIVENOT_0_SHIFT (12u) +#define CSI2LINK_PHDLM_ULPSACTIVENOT_1 (0x00002000u) +#define CSI2LINK_PHDLM_ULPSACTIVENOT_1_SHIFT (13u) +#define CSI2LINK_PH0M0_DT (0x0000003Fu) +#define CSI2LINK_PH0M0_DT_SHIFT (0u) +#define CSI2LINK_PH0M0_VC (0x000000C0u) +#define CSI2LINK_PH0M0_VC_SHIFT (6u) +#define CSI2LINK_PH0M0_WC (0x00FFFF00u) +#define CSI2LINK_PH0M0_WC_SHIFT (8u) +#define CSI2LINK_PH0M1_PH_CNT (0x0000FFFFu) +#define CSI2LINK_PH0M1_PH_CNT_SHIFT (0u) +#define CSI2LINK_PH1M0_DT (0x0000003Fu) +#define CSI2LINK_PH1M0_DT_SHIFT (0u) +#define CSI2LINK_PH1M0_VC (0x000000C0u) +#define CSI2LINK_PH1M0_VC_SHIFT (6u) +#define CSI2LINK_PH1M0_WC (0x00FFFF00u) +#define CSI2LINK_PH1M0_WC_SHIFT (8u) +#define CSI2LINK_PH1M1_PH_CNT (0x0000FFFFu) +#define CSI2LINK_PH1M1_PH_CNT_SHIFT (0u) +#define CSI2LINK_PH2M0_DT (0x0000003Fu) +#define CSI2LINK_PH2M0_DT_SHIFT (0u) +#define CSI2LINK_PH2M0_VC (0x000000C0u) +#define CSI2LINK_PH2M0_VC_SHIFT (6u) +#define CSI2LINK_PH2M0_WC (0x00FFFF00u) +#define CSI2LINK_PH2M0_WC_SHIFT (8u) +#define CSI2LINK_PH2M1_PH_CNT (0x0000FFFFu) +#define CSI2LINK_PH2M1_PH_CNT_SHIFT (0u) +#define CSI2LINK_PH3M0_DT (0x0000003Fu) +#define CSI2LINK_PH3M0_DT_SHIFT (0u) +#define CSI2LINK_PH3M0_VC (0x000000C0u) +#define CSI2LINK_PH3M0_VC_SHIFT (6u) +#define CSI2LINK_PH3M0_WC (0x00FFFF00u) +#define CSI2LINK_PH3M0_WC_SHIFT (8u) +#define CSI2LINK_PH3M1_PH_CNT (0x0000FFFFu) +#define CSI2LINK_PH3M1_PH_CNT_SHIFT (0u) +#define CSI2LINK_PHRM0_DT (0x0000003Fu) +#define CSI2LINK_PHRM0_DT_SHIFT (0u) +#define CSI2LINK_PHRM0_VC (0x000000C0u) +#define CSI2LINK_PHRM0_VC_SHIFT (6u) +#define CSI2LINK_PHRM0_WC (0x00FFFF00u) +#define CSI2LINK_PHRM0_WC_SHIFT (8u) +#define CSI2LINK_PHRM0_ECC (0xFF000000u) +#define CSI2LINK_PHRM0_ECC_SHIFT (24u) +#define CSI2LINK_PHRM1_DT (0x0000003Fu) +#define CSI2LINK_PHRM1_DT_SHIFT (0u) +#define CSI2LINK_PHRM1_VC (0x000000C0u) +#define CSI2LINK_PHRM1_VC_SHIFT (6u) +#define CSI2LINK_PHRM1_WC (0x00FFFF00u) +#define CSI2LINK_PHRM1_WC_SHIFT (8u) +#define CSI2LINK_PHRM1_ECC (0xFF000000u) +#define CSI2LINK_PHRM1_ECC_SHIFT (24u) +#define CSI2LINK_PHRM2_DT (0x0000003Fu) +#define CSI2LINK_PHRM2_DT_SHIFT (0u) +#define CSI2LINK_PHRM2_VC (0x000000C0u) +#define CSI2LINK_PHRM2_VC_SHIFT (6u) +#define CSI2LINK_PHRM2_WC (0x00FFFF00u) +#define CSI2LINK_PHRM2_WC_SHIFT (8u) +#define CSI2LINK_PHRM2_ECC (0xFF000000u) +#define CSI2LINK_PHRM2_ECC_SHIFT (24u) +#define CSI2LINK_PHCM0_DT (0x0000003Fu) +#define CSI2LINK_PHCM0_DT_SHIFT (0u) +#define CSI2LINK_PHCM0_VC (0x000000C0u) +#define CSI2LINK_PHCM0_VC_SHIFT (6u) +#define CSI2LINK_PHCM0_WC (0x00FFFF00u) +#define CSI2LINK_PHCM0_WC_SHIFT (8u) +#define CSI2LINK_PHCM0_CAL_PARITY (0xFF000000u) +#define CSI2LINK_PHCM0_CAL_PARITY_SHIFT (24u) +#define CSI2LINK_PHCM1_DT (0x0000003Fu) +#define CSI2LINK_PHCM1_DT_SHIFT (0u) +#define CSI2LINK_PHCM1_VC (0x000000C0u) +#define CSI2LINK_PHCM1_VC_SHIFT (6u) +#define CSI2LINK_PHCM1_WC (0x00FFFF00u) +#define CSI2LINK_PHCM1_WC_SHIFT (8u) +#define CSI2LINK_PHCM1_CAL_PARITY (0xFF000000u) +#define CSI2LINK_PHCM1_CAL_PARITY_SHIFT (24u) +#define CSI2LINK_CRCM0_CAL_CRC (0x0000FFFFu) +#define CSI2LINK_CRCM0_CAL_CRC_SHIFT (0u) +#define CSI2LINK_CRCM0_CRC (0xFFFF0000u) +#define CSI2LINK_CRCM0_CRC_SHIFT (16u) +#define CSI2LINK_CRCM1_CAL_CRC (0x0000FFFFu) +#define CSI2LINK_CRCM1_CAL_CRC_SHIFT (0u) +#define CSI2LINK_CRCM1_CRC (0xFFFF0000u) +#define CSI2LINK_CRCM1_CRC_SHIFT (16u) +#define CSI2LINK_SERRCNT_ERRSOTHS_CNT (0x000000FFu) +#define CSI2LINK_SERRCNT_ERRSOTHS_CNT_SHIFT (0u) +#define CSI2LINK_SSERRCNT_ERRSOTSYNCHS (0x0000000Fu) +#define CSI2LINK_SSERRCNT_ERRSOTSYNCHS_SHIFT (0u) +#define CSI2LINK_ECCCM_ECC_CRCT_CNT (0x000000FFu) +#define CSI2LINK_ECCCM_ECC_CRCT_CNT_SHIFT (0u) +#define CSI2LINK_ECECM_ECC_ERR_CNT (0x000000FFu) +#define CSI2LINK_ECECM_ECC_ERR_CNT_SHIFT (0u) +#define CSI2LINK_CRCECM_CRC_ERR_CNT (0x000000FFu) +#define CSI2LINK_CRCECM_CRC_ERR_CNT_SHIFT (0u) +#define CSI2LINK_LCNT_LINE_CNT (0x0000FFFFu) +#define CSI2LINK_LCNT_LINE_CNT_SHIFT (0u) +#define CSI2LINK_LCNTM_MONI_LINECNT (0x0000FFFFu) +#define CSI2LINK_LCNTM_MONI_LINECNT_SHIFT (0u) +#define CSI2LINK_FCNTM_MONI_FCOUNT (0x0000FFFFu) +#define CSI2LINK_FCNTM_MONI_FCOUNT_SHIFT (0u) +#define CSI2LINK_PHYDIM_RXDATAHS_0 (0x000000FFu) +#define CSI2LINK_PHYDIM_RXDATAHS_0_SHIFT (0u) +#define CSI2LINK_PHYDIM_RXDATAHS_1 (0x0000FF00u) +#define CSI2LINK_PHYDIM_RXDATAHS_1_SHIFT (8u) +#define CSI2LINK_PHYIM_RXSYNCHS_0_CNT (0x0000000Fu) +#define CSI2LINK_PHYIM_RXSYNCHS_0_CNT_SHIFT (0u) +#define CSI2LINK_PHYIM_RXSYNCHS_1_CNT (0x000000F0u) +#define CSI2LINK_PHYIM_RXSYNCHS_1_CNT_SHIFT (4u) +#define CSI2LINK_PHYIM_RXACTIVEHS_0 (0x00010000u) +#define CSI2LINK_PHYIM_RXACTIVEHS_0_SHIFT (16u) +#define CSI2LINK_PHYIM_RXACTIVEHS_1 (0x00020000u) +#define CSI2LINK_PHYIM_RXACTIVEHS_1_SHIFT (17u) +#define CSI2LINK_PHYIM_RXVALIDHS_0 (0x00100000u) +#define CSI2LINK_PHYIM_RXVALIDHS_0_SHIFT (20u) +#define CSI2LINK_PHYIM_RXVALIDHS_1 (0x00200000u) +#define CSI2LINK_PHYIM_RXVALIDHS_1_SHIFT (21u) +#define CSI2LINK_PHYIM_RXCLK_CNT (0x80000000u) +#define CSI2LINK_PHYIM_RXCLK_CNT_SHIFT (31u) +#define CSI2LINK_VINDM_CSIR_DAT (0xFFFFFFFFu) +#define CSI2LINK_VINDM_CSIR_DAT_SHIFT (0u) +#define CSI2LINK_VINSM1_CSIR_HD_CNT (0x00000FFFu) +#define CSI2LINK_VINSM1_CSIR_HD_CNT_SHIFT (0u) +#define CSI2LINK_VINSM1_CSIR_VD_CNT (0x0000F000u) +#define CSI2LINK_VINSM1_CSIR_VD_CNT_SHIFT (12u) +#define CSI2LINK_VINSM3_CSIR_PE (0x00000001u) +#define CSI2LINK_VINSM3_CSIR_PE_SHIFT (0u) +#define CSI2LINK_VINSM3_CSIR_PEB (0x000000F0u) +#define CSI2LINK_VINSM3_CSIR_PEB_SHIFT (4u) +#define CSI2LINK_VINSM3_CSIR_FLD (0x00000F00u) +#define CSI2LINK_VINSM3_CSIR_FLD_SHIFT (8u) +#define CSI2LINK_VINSM3_CSIR_TAG (0x00003000u) +#define CSI2LINK_VINSM3_CSIR_TAG_SHIFT (12u) +#define CSI2LINK_VINSM3_CSIR_ERRC (0x00004000u) +#define CSI2LINK_VINSM3_CSIR_ERRC_SHIFT (14u) +#define CSI2LINK_VINSM3_CSIR_ERRE (0x00008000u) +#define CSI2LINK_VINSM3_CSIR_ERRE_SHIFT (15u) +#define CSI2LINK_PHYOM_ENABLE_0 (0x00000001u) +#define CSI2LINK_PHYOM_ENABLE_0_SHIFT (0u) +#define CSI2LINK_PHYOM_ENABLE_1 (0x00000002u) +#define CSI2LINK_PHYOM_ENABLE_1_SHIFT (1u) +#define CSI2LINK_PHYOM_ENABLECLK (0x00000010u) +#define CSI2LINK_PHYOM_ENABLECLK_SHIFT (4u) +#define CSI2LINK_PHM1_DT (0x0000003Fu) +#define CSI2LINK_PHM1_DT_SHIFT (0u) +#define CSI2LINK_PHM1_VC (0x000000C0u) +#define CSI2LINK_PHM1_VC_SHIFT (6u) +#define CSI2LINK_PHM1_WC (0x00FFFF00u) +#define CSI2LINK_PHM1_WC_SHIFT (8u) +#define CSI2LINK_PHM1_ECC (0xFF000000u) +#define CSI2LINK_PHM1_ECC_SHIFT (24u) +#define CSI2LINK_PHM2_DT (0x0000003Fu) +#define CSI2LINK_PHM2_DT_SHIFT (0u) +#define CSI2LINK_PHM2_VC (0x000000C0u) +#define CSI2LINK_PHM2_VC_SHIFT (6u) +#define CSI2LINK_PHM2_WC (0x00FFFF00u) +#define CSI2LINK_PHM2_WC_SHIFT (8u) +#define CSI2LINK_PHM2_ECC (0xFF000000u) +#define CSI2LINK_PHM2_ECC_SHIFT (24u) +#define CSI2LINK_PHM3_DT (0x0000003Fu) +#define CSI2LINK_PHM3_DT_SHIFT (0u) +#define CSI2LINK_PHM3_VC (0x000000C0u) +#define CSI2LINK_PHM3_VC_SHIFT (6u) +#define CSI2LINK_PHM3_WC (0x00FFFF00u) +#define CSI2LINK_PHM3_WC_SHIFT (8u) +#define CSI2LINK_PHM3_ECC (0xFF000000u) +#define CSI2LINK_PHM3_ECC_SHIFT (24u) +#define CSI2LINK_PHM4_DT (0x0000003Fu) +#define CSI2LINK_PHM4_DT_SHIFT (0u) +#define CSI2LINK_PHM4_VC (0x000000C0u) +#define CSI2LINK_PHM4_VC_SHIFT (6u) +#define CSI2LINK_PHM4_WC (0x00FFFF00u) +#define CSI2LINK_PHM4_WC_SHIFT (8u) +#define CSI2LINK_PHM4_ECC (0xFF000000u) +#define CSI2LINK_PHM4_ECC_SHIFT (24u) +#define CSI2LINK_PHM5_DT (0x0000003Fu) +#define CSI2LINK_PHM5_DT_SHIFT (0u) +#define CSI2LINK_PHM5_VC (0x000000C0u) +#define CSI2LINK_PHM5_VC_SHIFT (6u) +#define CSI2LINK_PHM5_WC (0x00FFFF00u) +#define CSI2LINK_PHM5_WC_SHIFT (8u) +#define CSI2LINK_PHM5_ECC (0xFF000000u) +#define CSI2LINK_PHM5_ECC_SHIFT (24u) +#define CSI2LINK_PHM6_DT (0x0000003Fu) +#define CSI2LINK_PHM6_DT_SHIFT (0u) +#define CSI2LINK_PHM6_VC (0x000000C0u) +#define CSI2LINK_PHM6_VC_SHIFT (6u) +#define CSI2LINK_PHM6_WC (0x00FFFF00u) +#define CSI2LINK_PHM6_WC_SHIFT (8u) +#define CSI2LINK_PHM6_ECC (0xFF000000u) +#define CSI2LINK_PHM6_ECC_SHIFT (24u) +#define CSI2LINK_PHM7_DT (0x0000003Fu) +#define CSI2LINK_PHM7_DT_SHIFT (0u) +#define CSI2LINK_PHM7_VC (0x000000C0u) +#define CSI2LINK_PHM7_VC_SHIFT (6u) +#define CSI2LINK_PHM7_WC (0x00FFFF00u) +#define CSI2LINK_PHM7_WC_SHIFT (8u) +#define CSI2LINK_PHM7_ECC (0xFF000000u) +#define CSI2LINK_PHM7_ECC_SHIFT (24u) +#define CSI2LINK_PHM8_DT (0x0000003Fu) +#define CSI2LINK_PHM8_DT_SHIFT (0u) +#define CSI2LINK_PHM8_VC (0x000000C0u) +#define CSI2LINK_PHM8_VC_SHIFT (6u) +#define CSI2LINK_PHM8_WC (0x00FFFF00u) +#define CSI2LINK_PHM8_WC_SHIFT (8u) +#define CSI2LINK_PHM8_ECC (0xFF000000u) +#define CSI2LINK_PHM8_ECC_SHIFT (24u) +#define CSI2LINK_PHYTIM1_T_INIT_SLAVE (0x0000FFFFu) +#define CSI2LINK_PHYTIM1_T_INIT_SLAVE_SHIFT (0u) +#define CSI2LINK_PHYTIM2_TCLK_PREPARE (0x0000001Fu) +#define CSI2LINK_PHYTIM2_TCLK_PREPARE_SHIFT (0u) +#define CSI2LINK_PHYTIM2_TCLK_SETTLE (0x00003F00u) +#define CSI2LINK_PHYTIM2_TCLK_SETTLE_SHIFT (8u) +#define CSI2LINK_PHYTIM2_TCLK_MISS (0x001F0000u) +#define CSI2LINK_PHYTIM2_TCLK_MISS_SHIFT (16u) +#define CSI2LINK_PHYTIM3_THS_PREPARE (0x0000003Fu) +#define CSI2LINK_PHYTIM3_THS_PREPARE_SHIFT (0u) +#define CSI2LINK_PHYTIM3_THS_SETTLE (0x00003F00u) +#define CSI2LINK_PHYTIM3_THS_SETTLE_SHIFT (8u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/dmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/dmac_iobitmask.h new file mode 100644 index 0000000..f0771b5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/dmac_iobitmask.h @@ -0,0 +1,4194 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef DMAC_IOBITMASK_H +#define DMAC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define DMAC_N0SA_0S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_0S_SA_SHIFT (0u) +#define DMAC_N0DA_0S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_0S_DA_SHIFT (0u) +#define DMAC_N0TB_0S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_0S_TB_SHIFT (0u) +#define DMAC_N1SA_0S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_0S_SA_SHIFT (0u) +#define DMAC_N1DA_0S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_0S_DA_SHIFT (0u) +#define DMAC_N1TB_0S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_0S_TB_SHIFT (0u) +#define DMAC_CRSA_0S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_0S_CRSA_SHIFT (0u) +#define DMAC_CRDA_0S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_0S_CRDA_SHIFT (0u) +#define DMAC_CRTB_0S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_0S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_0S_EN (0x00000001u) +#define DMAC_CHSTAT_0S_EN_SHIFT (0u) +#define DMAC_CHSTAT_0S_RQST (0x00000002u) +#define DMAC_CHSTAT_0S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_0S_TACT (0x00000004u) +#define DMAC_CHSTAT_0S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_0S_SUS (0x00000008u) +#define DMAC_CHSTAT_0S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_0S_ER (0x00000010u) +#define DMAC_CHSTAT_0S_ER_SHIFT (4u) +#define DMAC_CHSTAT_0S_END (0x00000020u) +#define DMAC_CHSTAT_0S_END_SHIFT (5u) +#define DMAC_CHSTAT_0S_TC (0x00000040u) +#define DMAC_CHSTAT_0S_TC_SHIFT (6u) +#define DMAC_CHSTAT_0S_SR (0x00000080u) +#define DMAC_CHSTAT_0S_SR_SHIFT (7u) +#define DMAC_CHSTAT_0S_DL (0x00000100u) +#define DMAC_CHSTAT_0S_DL_SHIFT (8u) +#define DMAC_CHSTAT_0S_DW (0x00000200u) +#define DMAC_CHSTAT_0S_DW_SHIFT (9u) +#define DMAC_CHSTAT_0S_DER (0x00000400u) +#define DMAC_CHSTAT_0S_DER_SHIFT (10u) +#define DMAC_CHSTAT_0S_MODE (0x00000800u) +#define DMAC_CHSTAT_0S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_0S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_0S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_0S_SETEN (0x00000001u) +#define DMAC_CHCTRL_0S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_0S_CLREN (0x00000002u) +#define DMAC_CHCTRL_0S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_0S_STG (0x00000004u) +#define DMAC_CHCTRL_0S_STG_SHIFT (2u) +#define DMAC_CHCTRL_0S_SWRST (0x00000008u) +#define DMAC_CHCTRL_0S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_0S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_0S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_0S_CLREND (0x00000020u) +#define DMAC_CHCTRL_0S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_0S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_0S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_0S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_0S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_0S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_0S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_0S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_0S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_0S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_0S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_0S_SEL (0x00000007u) +#define DMAC_CHCFG_0S_SEL_SHIFT (0u) +#define DMAC_CHCFG_0S_REQD (0x00000008u) +#define DMAC_CHCFG_0S_REQD_SHIFT (3u) +#define DMAC_CHCFG_0S_LOEN (0x00000010u) +#define DMAC_CHCFG_0S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_0S_HIEN (0x00000020u) +#define DMAC_CHCFG_0S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_0S_LVL (0x00000040u) +#define DMAC_CHCFG_0S_LVL_SHIFT (6u) +#define DMAC_CHCFG_0S_AM (0x00000700u) +#define DMAC_CHCFG_0S_AM_SHIFT (8u) +#define DMAC_CHCFG_0S_SDS (0x0000F000u) +#define DMAC_CHCFG_0S_SDS_SHIFT (12u) +#define DMAC_CHCFG_0S_DDS (0x000F0000u) +#define DMAC_CHCFG_0S_DDS_SHIFT (16u) +#define DMAC_CHCFG_0S_SAD (0x00100000u) +#define DMAC_CHCFG_0S_SAD_SHIFT (20u) +#define DMAC_CHCFG_0S_DAD (0x00200000u) +#define DMAC_CHCFG_0S_DAD_SHIFT (21u) +#define DMAC_CHCFG_0S_TM (0x00400000u) +#define DMAC_CHCFG_0S_TM_SHIFT (22u) +#define DMAC_CHCFG_0S_DEM (0x01000000u) +#define DMAC_CHCFG_0S_DEM_SHIFT (24u) +#define DMAC_CHCFG_0S_SBE (0x08000000u) +#define DMAC_CHCFG_0S_SBE_SHIFT (27u) +#define DMAC_CHCFG_0S_RSEL (0x10000000u) +#define DMAC_CHCFG_0S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_0S_RSW (0x20000000u) +#define DMAC_CHCFG_0S_RSW_SHIFT (29u) +#define DMAC_CHCFG_0S_REN (0x40000000u) +#define DMAC_CHCFG_0S_REN_SHIFT (30u) +#define DMAC_CHCFG_0S_DMS (0x80000000u) +#define DMAC_CHCFG_0S_DMS_SHIFT (31u) +#define DMAC_CHITVL_0S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_0S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_0S_SPR (0x00000007u) +#define DMAC_CHEXT_0S_SPR_SHIFT (0u) +#define DMAC_CHEXT_0S_SCA (0x000000F0u) +#define DMAC_CHEXT_0S_SCA_SHIFT (4u) +#define DMAC_CHEXT_0S_DPR (0x00000700u) +#define DMAC_CHEXT_0S_DPR_SHIFT (8u) +#define DMAC_CHEXT_0S_DCA (0x0000F000u) +#define DMAC_CHEXT_0S_DCA_SHIFT (12u) +#define DMAC_NXLA_0S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_0S_NXLA_SHIFT (0u) +#define DMAC_CRLA_0S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_0S_CRLA_SHIFT (0u) +#define DMAC_N0SA_1S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_1S_SA_SHIFT (0u) +#define DMAC_N0DA_1S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_1S_DA_SHIFT (0u) +#define DMAC_N0TB_1S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_1S_TB_SHIFT (0u) +#define DMAC_N1SA_1S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_1S_SA_SHIFT (0u) +#define DMAC_N1DA_1S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_1S_DA_SHIFT (0u) +#define DMAC_N1TB_1S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_1S_TB_SHIFT (0u) +#define DMAC_CRSA_1S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_1S_CRSA_SHIFT (0u) +#define DMAC_CRDA_1S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_1S_CRDA_SHIFT (0u) +#define DMAC_CRTB_1S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_1S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_1S_EN (0x00000001u) +#define DMAC_CHSTAT_1S_EN_SHIFT (0u) +#define DMAC_CHSTAT_1S_RQST (0x00000002u) +#define DMAC_CHSTAT_1S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_1S_TACT (0x00000004u) +#define DMAC_CHSTAT_1S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_1S_SUS (0x00000008u) +#define DMAC_CHSTAT_1S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_1S_ER (0x00000010u) +#define DMAC_CHSTAT_1S_ER_SHIFT (4u) +#define DMAC_CHSTAT_1S_END (0x00000020u) +#define DMAC_CHSTAT_1S_END_SHIFT (5u) +#define DMAC_CHSTAT_1S_TC (0x00000040u) +#define DMAC_CHSTAT_1S_TC_SHIFT (6u) +#define DMAC_CHSTAT_1S_SR (0x00000080u) +#define DMAC_CHSTAT_1S_SR_SHIFT (7u) +#define DMAC_CHSTAT_1S_DL (0x00000100u) +#define DMAC_CHSTAT_1S_DL_SHIFT (8u) +#define DMAC_CHSTAT_1S_DW (0x00000200u) +#define DMAC_CHSTAT_1S_DW_SHIFT (9u) +#define DMAC_CHSTAT_1S_DER (0x00000400u) +#define DMAC_CHSTAT_1S_DER_SHIFT (10u) +#define DMAC_CHSTAT_1S_MODE (0x00000800u) +#define DMAC_CHSTAT_1S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_1S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_1S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_1S_SETEN (0x00000001u) +#define DMAC_CHCTRL_1S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_1S_CLREN (0x00000002u) +#define DMAC_CHCTRL_1S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_1S_STG (0x00000004u) +#define DMAC_CHCTRL_1S_STG_SHIFT (2u) +#define DMAC_CHCTRL_1S_SWRST (0x00000008u) +#define DMAC_CHCTRL_1S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_1S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_1S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_1S_CLREND (0x00000020u) +#define DMAC_CHCTRL_1S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_1S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_1S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_1S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_1S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_1S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_1S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_1S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_1S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_1S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_1S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_1S_SEL (0x00000007u) +#define DMAC_CHCFG_1S_SEL_SHIFT (0u) +#define DMAC_CHCFG_1S_REQD (0x00000008u) +#define DMAC_CHCFG_1S_REQD_SHIFT (3u) +#define DMAC_CHCFG_1S_LOEN (0x00000010u) +#define DMAC_CHCFG_1S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_1S_HIEN (0x00000020u) +#define DMAC_CHCFG_1S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_1S_LVL (0x00000040u) +#define DMAC_CHCFG_1S_LVL_SHIFT (6u) +#define DMAC_CHCFG_1S_AM (0x00000700u) +#define DMAC_CHCFG_1S_AM_SHIFT (8u) +#define DMAC_CHCFG_1S_SDS (0x0000F000u) +#define DMAC_CHCFG_1S_SDS_SHIFT (12u) +#define DMAC_CHCFG_1S_DDS (0x000F0000u) +#define DMAC_CHCFG_1S_DDS_SHIFT (16u) +#define DMAC_CHCFG_1S_SAD (0x00100000u) +#define DMAC_CHCFG_1S_SAD_SHIFT (20u) +#define DMAC_CHCFG_1S_DAD (0x00200000u) +#define DMAC_CHCFG_1S_DAD_SHIFT (21u) +#define DMAC_CHCFG_1S_TM (0x00400000u) +#define DMAC_CHCFG_1S_TM_SHIFT (22u) +#define DMAC_CHCFG_1S_DEM (0x01000000u) +#define DMAC_CHCFG_1S_DEM_SHIFT (24u) +#define DMAC_CHCFG_1S_SBE (0x08000000u) +#define DMAC_CHCFG_1S_SBE_SHIFT (27u) +#define DMAC_CHCFG_1S_RSEL (0x10000000u) +#define DMAC_CHCFG_1S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_1S_RSW (0x20000000u) +#define DMAC_CHCFG_1S_RSW_SHIFT (29u) +#define DMAC_CHCFG_1S_REN (0x40000000u) +#define DMAC_CHCFG_1S_REN_SHIFT (30u) +#define DMAC_CHCFG_1S_DMS (0x80000000u) +#define DMAC_CHCFG_1S_DMS_SHIFT (31u) +#define DMAC_CHITVL_1S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_1S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_1S_SPR (0x00000007u) +#define DMAC_CHEXT_1S_SPR_SHIFT (0u) +#define DMAC_CHEXT_1S_SCA (0x000000F0u) +#define DMAC_CHEXT_1S_SCA_SHIFT (4u) +#define DMAC_CHEXT_1S_DPR (0x00000700u) +#define DMAC_CHEXT_1S_DPR_SHIFT (8u) +#define DMAC_CHEXT_1S_DCA (0x0000F000u) +#define DMAC_CHEXT_1S_DCA_SHIFT (12u) +#define DMAC_NXLA_1S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_1S_NXLA_SHIFT (0u) +#define DMAC_CRLA_1S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_1S_CRLA_SHIFT (0u) +#define DMAC_N0SA_2S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_2S_SA_SHIFT (0u) +#define DMAC_N0DA_2S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_2S_DA_SHIFT (0u) +#define DMAC_N0TB_2S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_2S_TB_SHIFT (0u) +#define DMAC_N1SA_2S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_2S_SA_SHIFT (0u) +#define DMAC_N1DA_2S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_2S_DA_SHIFT (0u) +#define DMAC_N1TB_2S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_2S_TB_SHIFT (0u) +#define DMAC_CRSA_2S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_2S_CRSA_SHIFT (0u) +#define DMAC_CRDA_2S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_2S_CRDA_SHIFT (0u) +#define DMAC_CRTB_2S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_2S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_2S_EN (0x00000001u) +#define DMAC_CHSTAT_2S_EN_SHIFT (0u) +#define DMAC_CHSTAT_2S_RQST (0x00000002u) +#define DMAC_CHSTAT_2S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_2S_TACT (0x00000004u) +#define DMAC_CHSTAT_2S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_2S_SUS (0x00000008u) +#define DMAC_CHSTAT_2S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_2S_ER (0x00000010u) +#define DMAC_CHSTAT_2S_ER_SHIFT (4u) +#define DMAC_CHSTAT_2S_END (0x00000020u) +#define DMAC_CHSTAT_2S_END_SHIFT (5u) +#define DMAC_CHSTAT_2S_TC (0x00000040u) +#define DMAC_CHSTAT_2S_TC_SHIFT (6u) +#define DMAC_CHSTAT_2S_SR (0x00000080u) +#define DMAC_CHSTAT_2S_SR_SHIFT (7u) +#define DMAC_CHSTAT_2S_DL (0x00000100u) +#define DMAC_CHSTAT_2S_DL_SHIFT (8u) +#define DMAC_CHSTAT_2S_DW (0x00000200u) +#define DMAC_CHSTAT_2S_DW_SHIFT (9u) +#define DMAC_CHSTAT_2S_DER (0x00000400u) +#define DMAC_CHSTAT_2S_DER_SHIFT (10u) +#define DMAC_CHSTAT_2S_MODE (0x00000800u) +#define DMAC_CHSTAT_2S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_2S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_2S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_2S_SETEN (0x00000001u) +#define DMAC_CHCTRL_2S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_2S_CLREN (0x00000002u) +#define DMAC_CHCTRL_2S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_2S_STG (0x00000004u) +#define DMAC_CHCTRL_2S_STG_SHIFT (2u) +#define DMAC_CHCTRL_2S_SWRST (0x00000008u) +#define DMAC_CHCTRL_2S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_2S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_2S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_2S_CLREND (0x00000020u) +#define DMAC_CHCTRL_2S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_2S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_2S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_2S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_2S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_2S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_2S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_2S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_2S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_2S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_2S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_2S_SEL (0x00000007u) +#define DMAC_CHCFG_2S_SEL_SHIFT (0u) +#define DMAC_CHCFG_2S_REQD (0x00000008u) +#define DMAC_CHCFG_2S_REQD_SHIFT (3u) +#define DMAC_CHCFG_2S_LOEN (0x00000010u) +#define DMAC_CHCFG_2S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_2S_HIEN (0x00000020u) +#define DMAC_CHCFG_2S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_2S_LVL (0x00000040u) +#define DMAC_CHCFG_2S_LVL_SHIFT (6u) +#define DMAC_CHCFG_2S_AM (0x00000700u) +#define DMAC_CHCFG_2S_AM_SHIFT (8u) +#define DMAC_CHCFG_2S_SDS (0x0000F000u) +#define DMAC_CHCFG_2S_SDS_SHIFT (12u) +#define DMAC_CHCFG_2S_DDS (0x000F0000u) +#define DMAC_CHCFG_2S_DDS_SHIFT (16u) +#define DMAC_CHCFG_2S_SAD (0x00100000u) +#define DMAC_CHCFG_2S_SAD_SHIFT (20u) +#define DMAC_CHCFG_2S_DAD (0x00200000u) +#define DMAC_CHCFG_2S_DAD_SHIFT (21u) +#define DMAC_CHCFG_2S_TM (0x00400000u) +#define DMAC_CHCFG_2S_TM_SHIFT (22u) +#define DMAC_CHCFG_2S_DEM (0x01000000u) +#define DMAC_CHCFG_2S_DEM_SHIFT (24u) +#define DMAC_CHCFG_2S_SBE (0x08000000u) +#define DMAC_CHCFG_2S_SBE_SHIFT (27u) +#define DMAC_CHCFG_2S_RSEL (0x10000000u) +#define DMAC_CHCFG_2S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_2S_RSW (0x20000000u) +#define DMAC_CHCFG_2S_RSW_SHIFT (29u) +#define DMAC_CHCFG_2S_REN (0x40000000u) +#define DMAC_CHCFG_2S_REN_SHIFT (30u) +#define DMAC_CHCFG_2S_DMS (0x80000000u) +#define DMAC_CHCFG_2S_DMS_SHIFT (31u) +#define DMAC_CHITVL_2S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_2S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_2S_SPR (0x00000007u) +#define DMAC_CHEXT_2S_SPR_SHIFT (0u) +#define DMAC_CHEXT_2S_SCA (0x000000F0u) +#define DMAC_CHEXT_2S_SCA_SHIFT (4u) +#define DMAC_CHEXT_2S_DPR (0x00000700u) +#define DMAC_CHEXT_2S_DPR_SHIFT (8u) +#define DMAC_CHEXT_2S_DCA (0x0000F000u) +#define DMAC_CHEXT_2S_DCA_SHIFT (12u) +#define DMAC_NXLA_2S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_2S_NXLA_SHIFT (0u) +#define DMAC_CRLA_2S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_2S_CRLA_SHIFT (0u) +#define DMAC_N0SA_3S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_3S_SA_SHIFT (0u) +#define DMAC_N0DA_3S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_3S_DA_SHIFT (0u) +#define DMAC_N0TB_3S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_3S_TB_SHIFT (0u) +#define DMAC_N1SA_3S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_3S_SA_SHIFT (0u) +#define DMAC_N1DA_3S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_3S_DA_SHIFT (0u) +#define DMAC_N1TB_3S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_3S_TB_SHIFT (0u) +#define DMAC_CRSA_3S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_3S_CRSA_SHIFT (0u) +#define DMAC_CRDA_3S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_3S_CRDA_SHIFT (0u) +#define DMAC_CRTB_3S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_3S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_3S_EN (0x00000001u) +#define DMAC_CHSTAT_3S_EN_SHIFT (0u) +#define DMAC_CHSTAT_3S_RQST (0x00000002u) +#define DMAC_CHSTAT_3S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_3S_TACT (0x00000004u) +#define DMAC_CHSTAT_3S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_3S_SUS (0x00000008u) +#define DMAC_CHSTAT_3S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_3S_ER (0x00000010u) +#define DMAC_CHSTAT_3S_ER_SHIFT (4u) +#define DMAC_CHSTAT_3S_END (0x00000020u) +#define DMAC_CHSTAT_3S_END_SHIFT (5u) +#define DMAC_CHSTAT_3S_TC (0x00000040u) +#define DMAC_CHSTAT_3S_TC_SHIFT (6u) +#define DMAC_CHSTAT_3S_SR (0x00000080u) +#define DMAC_CHSTAT_3S_SR_SHIFT (7u) +#define DMAC_CHSTAT_3S_DL (0x00000100u) +#define DMAC_CHSTAT_3S_DL_SHIFT (8u) +#define DMAC_CHSTAT_3S_DW (0x00000200u) +#define DMAC_CHSTAT_3S_DW_SHIFT (9u) +#define DMAC_CHSTAT_3S_DER (0x00000400u) +#define DMAC_CHSTAT_3S_DER_SHIFT (10u) +#define DMAC_CHSTAT_3S_MODE (0x00000800u) +#define DMAC_CHSTAT_3S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_3S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_3S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_3S_SETEN (0x00000001u) +#define DMAC_CHCTRL_3S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_3S_CLREN (0x00000002u) +#define DMAC_CHCTRL_3S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_3S_STG (0x00000004u) +#define DMAC_CHCTRL_3S_STG_SHIFT (2u) +#define DMAC_CHCTRL_3S_SWRST (0x00000008u) +#define DMAC_CHCTRL_3S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_3S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_3S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_3S_CLREND (0x00000020u) +#define DMAC_CHCTRL_3S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_3S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_3S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_3S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_3S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_3S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_3S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_3S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_3S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_3S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_3S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_3S_SEL (0x00000007u) +#define DMAC_CHCFG_3S_SEL_SHIFT (0u) +#define DMAC_CHCFG_3S_REQD (0x00000008u) +#define DMAC_CHCFG_3S_REQD_SHIFT (3u) +#define DMAC_CHCFG_3S_LOEN (0x00000010u) +#define DMAC_CHCFG_3S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_3S_HIEN (0x00000020u) +#define DMAC_CHCFG_3S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_3S_LVL (0x00000040u) +#define DMAC_CHCFG_3S_LVL_SHIFT (6u) +#define DMAC_CHCFG_3S_AM (0x00000700u) +#define DMAC_CHCFG_3S_AM_SHIFT (8u) +#define DMAC_CHCFG_3S_SDS (0x0000F000u) +#define DMAC_CHCFG_3S_SDS_SHIFT (12u) +#define DMAC_CHCFG_3S_DDS (0x000F0000u) +#define DMAC_CHCFG_3S_DDS_SHIFT (16u) +#define DMAC_CHCFG_3S_SAD (0x00100000u) +#define DMAC_CHCFG_3S_SAD_SHIFT (20u) +#define DMAC_CHCFG_3S_DAD (0x00200000u) +#define DMAC_CHCFG_3S_DAD_SHIFT (21u) +#define DMAC_CHCFG_3S_TM (0x00400000u) +#define DMAC_CHCFG_3S_TM_SHIFT (22u) +#define DMAC_CHCFG_3S_DEM (0x01000000u) +#define DMAC_CHCFG_3S_DEM_SHIFT (24u) +#define DMAC_CHCFG_3S_SBE (0x08000000u) +#define DMAC_CHCFG_3S_SBE_SHIFT (27u) +#define DMAC_CHCFG_3S_RSEL (0x10000000u) +#define DMAC_CHCFG_3S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_3S_RSW (0x20000000u) +#define DMAC_CHCFG_3S_RSW_SHIFT (29u) +#define DMAC_CHCFG_3S_REN (0x40000000u) +#define DMAC_CHCFG_3S_REN_SHIFT (30u) +#define DMAC_CHCFG_3S_DMS (0x80000000u) +#define DMAC_CHCFG_3S_DMS_SHIFT (31u) +#define DMAC_CHITVL_3S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_3S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_3S_SPR (0x00000007u) +#define DMAC_CHEXT_3S_SPR_SHIFT (0u) +#define DMAC_CHEXT_3S_SCA (0x000000F0u) +#define DMAC_CHEXT_3S_SCA_SHIFT (4u) +#define DMAC_CHEXT_3S_DPR (0x00000700u) +#define DMAC_CHEXT_3S_DPR_SHIFT (8u) +#define DMAC_CHEXT_3S_DCA (0x0000F000u) +#define DMAC_CHEXT_3S_DCA_SHIFT (12u) +#define DMAC_NXLA_3S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_3S_NXLA_SHIFT (0u) +#define DMAC_CRLA_3S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_3S_CRLA_SHIFT (0u) +#define DMAC_N0SA_4S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_4S_SA_SHIFT (0u) +#define DMAC_N0DA_4S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_4S_DA_SHIFT (0u) +#define DMAC_N0TB_4S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_4S_TB_SHIFT (0u) +#define DMAC_N1SA_4S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_4S_SA_SHIFT (0u) +#define DMAC_N1DA_4S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_4S_DA_SHIFT (0u) +#define DMAC_N1TB_4S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_4S_TB_SHIFT (0u) +#define DMAC_CRSA_4S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_4S_CRSA_SHIFT (0u) +#define DMAC_CRDA_4S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_4S_CRDA_SHIFT (0u) +#define DMAC_CRTB_4S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_4S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_4S_EN (0x00000001u) +#define DMAC_CHSTAT_4S_EN_SHIFT (0u) +#define DMAC_CHSTAT_4S_RQST (0x00000002u) +#define DMAC_CHSTAT_4S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_4S_TACT (0x00000004u) +#define DMAC_CHSTAT_4S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_4S_SUS (0x00000008u) +#define DMAC_CHSTAT_4S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_4S_ER (0x00000010u) +#define DMAC_CHSTAT_4S_ER_SHIFT (4u) +#define DMAC_CHSTAT_4S_END (0x00000020u) +#define DMAC_CHSTAT_4S_END_SHIFT (5u) +#define DMAC_CHSTAT_4S_TC (0x00000040u) +#define DMAC_CHSTAT_4S_TC_SHIFT (6u) +#define DMAC_CHSTAT_4S_SR (0x00000080u) +#define DMAC_CHSTAT_4S_SR_SHIFT (7u) +#define DMAC_CHSTAT_4S_DL (0x00000100u) +#define DMAC_CHSTAT_4S_DL_SHIFT (8u) +#define DMAC_CHSTAT_4S_DW (0x00000200u) +#define DMAC_CHSTAT_4S_DW_SHIFT (9u) +#define DMAC_CHSTAT_4S_DER (0x00000400u) +#define DMAC_CHSTAT_4S_DER_SHIFT (10u) +#define DMAC_CHSTAT_4S_MODE (0x00000800u) +#define DMAC_CHSTAT_4S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_4S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_4S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_4S_SETEN (0x00000001u) +#define DMAC_CHCTRL_4S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_4S_CLREN (0x00000002u) +#define DMAC_CHCTRL_4S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_4S_STG (0x00000004u) +#define DMAC_CHCTRL_4S_STG_SHIFT (2u) +#define DMAC_CHCTRL_4S_SWRST (0x00000008u) +#define DMAC_CHCTRL_4S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_4S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_4S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_4S_CLREND (0x00000020u) +#define DMAC_CHCTRL_4S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_4S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_4S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_4S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_4S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_4S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_4S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_4S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_4S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_4S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_4S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_4S_SEL (0x00000007u) +#define DMAC_CHCFG_4S_SEL_SHIFT (0u) +#define DMAC_CHCFG_4S_REQD (0x00000008u) +#define DMAC_CHCFG_4S_REQD_SHIFT (3u) +#define DMAC_CHCFG_4S_LOEN (0x00000010u) +#define DMAC_CHCFG_4S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_4S_HIEN (0x00000020u) +#define DMAC_CHCFG_4S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_4S_LVL (0x00000040u) +#define DMAC_CHCFG_4S_LVL_SHIFT (6u) +#define DMAC_CHCFG_4S_AM (0x00000700u) +#define DMAC_CHCFG_4S_AM_SHIFT (8u) +#define DMAC_CHCFG_4S_SDS (0x0000F000u) +#define DMAC_CHCFG_4S_SDS_SHIFT (12u) +#define DMAC_CHCFG_4S_DDS (0x000F0000u) +#define DMAC_CHCFG_4S_DDS_SHIFT (16u) +#define DMAC_CHCFG_4S_SAD (0x00100000u) +#define DMAC_CHCFG_4S_SAD_SHIFT (20u) +#define DMAC_CHCFG_4S_DAD (0x00200000u) +#define DMAC_CHCFG_4S_DAD_SHIFT (21u) +#define DMAC_CHCFG_4S_TM (0x00400000u) +#define DMAC_CHCFG_4S_TM_SHIFT (22u) +#define DMAC_CHCFG_4S_DEM (0x01000000u) +#define DMAC_CHCFG_4S_DEM_SHIFT (24u) +#define DMAC_CHCFG_4S_SBE (0x08000000u) +#define DMAC_CHCFG_4S_SBE_SHIFT (27u) +#define DMAC_CHCFG_4S_RSEL (0x10000000u) +#define DMAC_CHCFG_4S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_4S_RSW (0x20000000u) +#define DMAC_CHCFG_4S_RSW_SHIFT (29u) +#define DMAC_CHCFG_4S_REN (0x40000000u) +#define DMAC_CHCFG_4S_REN_SHIFT (30u) +#define DMAC_CHCFG_4S_DMS (0x80000000u) +#define DMAC_CHCFG_4S_DMS_SHIFT (31u) +#define DMAC_CHITVL_4S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_4S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_4S_SPR (0x00000007u) +#define DMAC_CHEXT_4S_SPR_SHIFT (0u) +#define DMAC_CHEXT_4S_SCA (0x000000F0u) +#define DMAC_CHEXT_4S_SCA_SHIFT (4u) +#define DMAC_CHEXT_4S_DPR (0x00000700u) +#define DMAC_CHEXT_4S_DPR_SHIFT (8u) +#define DMAC_CHEXT_4S_DCA (0x0000F000u) +#define DMAC_CHEXT_4S_DCA_SHIFT (12u) +#define DMAC_NXLA_4S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_4S_NXLA_SHIFT (0u) +#define DMAC_CRLA_4S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_4S_CRLA_SHIFT (0u) +#define DMAC_N0SA_5S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_5S_SA_SHIFT (0u) +#define DMAC_N0DA_5S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_5S_DA_SHIFT (0u) +#define DMAC_N0TB_5S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_5S_TB_SHIFT (0u) +#define DMAC_N1SA_5S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_5S_SA_SHIFT (0u) +#define DMAC_N1DA_5S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_5S_DA_SHIFT (0u) +#define DMAC_N1TB_5S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_5S_TB_SHIFT (0u) +#define DMAC_CRSA_5S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_5S_CRSA_SHIFT (0u) +#define DMAC_CRDA_5S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_5S_CRDA_SHIFT (0u) +#define DMAC_CRTB_5S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_5S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_5S_EN (0x00000001u) +#define DMAC_CHSTAT_5S_EN_SHIFT (0u) +#define DMAC_CHSTAT_5S_RQST (0x00000002u) +#define DMAC_CHSTAT_5S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_5S_TACT (0x00000004u) +#define DMAC_CHSTAT_5S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_5S_SUS (0x00000008u) +#define DMAC_CHSTAT_5S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_5S_ER (0x00000010u) +#define DMAC_CHSTAT_5S_ER_SHIFT (4u) +#define DMAC_CHSTAT_5S_END (0x00000020u) +#define DMAC_CHSTAT_5S_END_SHIFT (5u) +#define DMAC_CHSTAT_5S_TC (0x00000040u) +#define DMAC_CHSTAT_5S_TC_SHIFT (6u) +#define DMAC_CHSTAT_5S_SR (0x00000080u) +#define DMAC_CHSTAT_5S_SR_SHIFT (7u) +#define DMAC_CHSTAT_5S_DL (0x00000100u) +#define DMAC_CHSTAT_5S_DL_SHIFT (8u) +#define DMAC_CHSTAT_5S_DW (0x00000200u) +#define DMAC_CHSTAT_5S_DW_SHIFT (9u) +#define DMAC_CHSTAT_5S_DER (0x00000400u) +#define DMAC_CHSTAT_5S_DER_SHIFT (10u) +#define DMAC_CHSTAT_5S_MODE (0x00000800u) +#define DMAC_CHSTAT_5S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_5S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_5S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_5S_SETEN (0x00000001u) +#define DMAC_CHCTRL_5S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_5S_CLREN (0x00000002u) +#define DMAC_CHCTRL_5S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_5S_STG (0x00000004u) +#define DMAC_CHCTRL_5S_STG_SHIFT (2u) +#define DMAC_CHCTRL_5S_SWRST (0x00000008u) +#define DMAC_CHCTRL_5S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_5S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_5S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_5S_CLREND (0x00000020u) +#define DMAC_CHCTRL_5S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_5S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_5S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_5S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_5S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_5S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_5S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_5S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_5S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_5S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_5S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_5S_SEL (0x00000007u) +#define DMAC_CHCFG_5S_SEL_SHIFT (0u) +#define DMAC_CHCFG_5S_REQD (0x00000008u) +#define DMAC_CHCFG_5S_REQD_SHIFT (3u) +#define DMAC_CHCFG_5S_LOEN (0x00000010u) +#define DMAC_CHCFG_5S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_5S_HIEN (0x00000020u) +#define DMAC_CHCFG_5S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_5S_LVL (0x00000040u) +#define DMAC_CHCFG_5S_LVL_SHIFT (6u) +#define DMAC_CHCFG_5S_AM (0x00000700u) +#define DMAC_CHCFG_5S_AM_SHIFT (8u) +#define DMAC_CHCFG_5S_SDS (0x0000F000u) +#define DMAC_CHCFG_5S_SDS_SHIFT (12u) +#define DMAC_CHCFG_5S_DDS (0x000F0000u) +#define DMAC_CHCFG_5S_DDS_SHIFT (16u) +#define DMAC_CHCFG_5S_SAD (0x00100000u) +#define DMAC_CHCFG_5S_SAD_SHIFT (20u) +#define DMAC_CHCFG_5S_DAD (0x00200000u) +#define DMAC_CHCFG_5S_DAD_SHIFT (21u) +#define DMAC_CHCFG_5S_TM (0x00400000u) +#define DMAC_CHCFG_5S_TM_SHIFT (22u) +#define DMAC_CHCFG_5S_DEM (0x01000000u) +#define DMAC_CHCFG_5S_DEM_SHIFT (24u) +#define DMAC_CHCFG_5S_SBE (0x08000000u) +#define DMAC_CHCFG_5S_SBE_SHIFT (27u) +#define DMAC_CHCFG_5S_RSEL (0x10000000u) +#define DMAC_CHCFG_5S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_5S_RSW (0x20000000u) +#define DMAC_CHCFG_5S_RSW_SHIFT (29u) +#define DMAC_CHCFG_5S_REN (0x40000000u) +#define DMAC_CHCFG_5S_REN_SHIFT (30u) +#define DMAC_CHCFG_5S_DMS (0x80000000u) +#define DMAC_CHCFG_5S_DMS_SHIFT (31u) +#define DMAC_CHITVL_5S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_5S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_5S_SPR (0x00000007u) +#define DMAC_CHEXT_5S_SPR_SHIFT (0u) +#define DMAC_CHEXT_5S_SCA (0x000000F0u) +#define DMAC_CHEXT_5S_SCA_SHIFT (4u) +#define DMAC_CHEXT_5S_DPR (0x00000700u) +#define DMAC_CHEXT_5S_DPR_SHIFT (8u) +#define DMAC_CHEXT_5S_DCA (0x0000F000u) +#define DMAC_CHEXT_5S_DCA_SHIFT (12u) +#define DMAC_NXLA_5S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_5S_NXLA_SHIFT (0u) +#define DMAC_CRLA_5S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_5S_CRLA_SHIFT (0u) +#define DMAC_N0SA_6S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_6S_SA_SHIFT (0u) +#define DMAC_N0DA_6S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_6S_DA_SHIFT (0u) +#define DMAC_N0TB_6S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_6S_TB_SHIFT (0u) +#define DMAC_N1SA_6S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_6S_SA_SHIFT (0u) +#define DMAC_N1DA_6S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_6S_DA_SHIFT (0u) +#define DMAC_N1TB_6S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_6S_TB_SHIFT (0u) +#define DMAC_CRSA_6S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_6S_CRSA_SHIFT (0u) +#define DMAC_CRDA_6S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_6S_CRDA_SHIFT (0u) +#define DMAC_CRTB_6S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_6S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_6S_EN (0x00000001u) +#define DMAC_CHSTAT_6S_EN_SHIFT (0u) +#define DMAC_CHSTAT_6S_RQST (0x00000002u) +#define DMAC_CHSTAT_6S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_6S_TACT (0x00000004u) +#define DMAC_CHSTAT_6S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_6S_SUS (0x00000008u) +#define DMAC_CHSTAT_6S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_6S_ER (0x00000010u) +#define DMAC_CHSTAT_6S_ER_SHIFT (4u) +#define DMAC_CHSTAT_6S_END (0x00000020u) +#define DMAC_CHSTAT_6S_END_SHIFT (5u) +#define DMAC_CHSTAT_6S_TC (0x00000040u) +#define DMAC_CHSTAT_6S_TC_SHIFT (6u) +#define DMAC_CHSTAT_6S_SR (0x00000080u) +#define DMAC_CHSTAT_6S_SR_SHIFT (7u) +#define DMAC_CHSTAT_6S_DL (0x00000100u) +#define DMAC_CHSTAT_6S_DL_SHIFT (8u) +#define DMAC_CHSTAT_6S_DW (0x00000200u) +#define DMAC_CHSTAT_6S_DW_SHIFT (9u) +#define DMAC_CHSTAT_6S_DER (0x00000400u) +#define DMAC_CHSTAT_6S_DER_SHIFT (10u) +#define DMAC_CHSTAT_6S_MODE (0x00000800u) +#define DMAC_CHSTAT_6S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_6S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_6S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_6S_SETEN (0x00000001u) +#define DMAC_CHCTRL_6S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_6S_CLREN (0x00000002u) +#define DMAC_CHCTRL_6S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_6S_STG (0x00000004u) +#define DMAC_CHCTRL_6S_STG_SHIFT (2u) +#define DMAC_CHCTRL_6S_SWRST (0x00000008u) +#define DMAC_CHCTRL_6S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_6S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_6S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_6S_CLREND (0x00000020u) +#define DMAC_CHCTRL_6S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_6S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_6S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_6S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_6S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_6S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_6S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_6S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_6S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_6S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_6S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_6S_SEL (0x00000007u) +#define DMAC_CHCFG_6S_SEL_SHIFT (0u) +#define DMAC_CHCFG_6S_REQD (0x00000008u) +#define DMAC_CHCFG_6S_REQD_SHIFT (3u) +#define DMAC_CHCFG_6S_LOEN (0x00000010u) +#define DMAC_CHCFG_6S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_6S_HIEN (0x00000020u) +#define DMAC_CHCFG_6S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_6S_LVL (0x00000040u) +#define DMAC_CHCFG_6S_LVL_SHIFT (6u) +#define DMAC_CHCFG_6S_AM (0x00000700u) +#define DMAC_CHCFG_6S_AM_SHIFT (8u) +#define DMAC_CHCFG_6S_SDS (0x0000F000u) +#define DMAC_CHCFG_6S_SDS_SHIFT (12u) +#define DMAC_CHCFG_6S_DDS (0x000F0000u) +#define DMAC_CHCFG_6S_DDS_SHIFT (16u) +#define DMAC_CHCFG_6S_SAD (0x00100000u) +#define DMAC_CHCFG_6S_SAD_SHIFT (20u) +#define DMAC_CHCFG_6S_DAD (0x00200000u) +#define DMAC_CHCFG_6S_DAD_SHIFT (21u) +#define DMAC_CHCFG_6S_TM (0x00400000u) +#define DMAC_CHCFG_6S_TM_SHIFT (22u) +#define DMAC_CHCFG_6S_DEM (0x01000000u) +#define DMAC_CHCFG_6S_DEM_SHIFT (24u) +#define DMAC_CHCFG_6S_SBE (0x08000000u) +#define DMAC_CHCFG_6S_SBE_SHIFT (27u) +#define DMAC_CHCFG_6S_RSEL (0x10000000u) +#define DMAC_CHCFG_6S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_6S_RSW (0x20000000u) +#define DMAC_CHCFG_6S_RSW_SHIFT (29u) +#define DMAC_CHCFG_6S_REN (0x40000000u) +#define DMAC_CHCFG_6S_REN_SHIFT (30u) +#define DMAC_CHCFG_6S_DMS (0x80000000u) +#define DMAC_CHCFG_6S_DMS_SHIFT (31u) +#define DMAC_CHITVL_6S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_6S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_6S_SPR (0x00000007u) +#define DMAC_CHEXT_6S_SPR_SHIFT (0u) +#define DMAC_CHEXT_6S_SCA (0x000000F0u) +#define DMAC_CHEXT_6S_SCA_SHIFT (4u) +#define DMAC_CHEXT_6S_DPR (0x00000700u) +#define DMAC_CHEXT_6S_DPR_SHIFT (8u) +#define DMAC_CHEXT_6S_DCA (0x0000F000u) +#define DMAC_CHEXT_6S_DCA_SHIFT (12u) +#define DMAC_NXLA_6S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_6S_NXLA_SHIFT (0u) +#define DMAC_CRLA_6S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_6S_CRLA_SHIFT (0u) +#define DMAC_N0SA_7S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_7S_SA_SHIFT (0u) +#define DMAC_N0DA_7S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_7S_DA_SHIFT (0u) +#define DMAC_N0TB_7S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_7S_TB_SHIFT (0u) +#define DMAC_N1SA_7S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_7S_SA_SHIFT (0u) +#define DMAC_N1DA_7S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_7S_DA_SHIFT (0u) +#define DMAC_N1TB_7S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_7S_TB_SHIFT (0u) +#define DMAC_CRSA_7S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_7S_CRSA_SHIFT (0u) +#define DMAC_CRDA_7S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_7S_CRDA_SHIFT (0u) +#define DMAC_CRTB_7S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_7S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_7S_EN (0x00000001u) +#define DMAC_CHSTAT_7S_EN_SHIFT (0u) +#define DMAC_CHSTAT_7S_RQST (0x00000002u) +#define DMAC_CHSTAT_7S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_7S_TACT (0x00000004u) +#define DMAC_CHSTAT_7S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_7S_SUS (0x00000008u) +#define DMAC_CHSTAT_7S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_7S_ER (0x00000010u) +#define DMAC_CHSTAT_7S_ER_SHIFT (4u) +#define DMAC_CHSTAT_7S_END (0x00000020u) +#define DMAC_CHSTAT_7S_END_SHIFT (5u) +#define DMAC_CHSTAT_7S_TC (0x00000040u) +#define DMAC_CHSTAT_7S_TC_SHIFT (6u) +#define DMAC_CHSTAT_7S_SR (0x00000080u) +#define DMAC_CHSTAT_7S_SR_SHIFT (7u) +#define DMAC_CHSTAT_7S_DL (0x00000100u) +#define DMAC_CHSTAT_7S_DL_SHIFT (8u) +#define DMAC_CHSTAT_7S_DW (0x00000200u) +#define DMAC_CHSTAT_7S_DW_SHIFT (9u) +#define DMAC_CHSTAT_7S_DER (0x00000400u) +#define DMAC_CHSTAT_7S_DER_SHIFT (10u) +#define DMAC_CHSTAT_7S_MODE (0x00000800u) +#define DMAC_CHSTAT_7S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_7S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_7S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_7S_SETEN (0x00000001u) +#define DMAC_CHCTRL_7S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_7S_CLREN (0x00000002u) +#define DMAC_CHCTRL_7S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_7S_STG (0x00000004u) +#define DMAC_CHCTRL_7S_STG_SHIFT (2u) +#define DMAC_CHCTRL_7S_SWRST (0x00000008u) +#define DMAC_CHCTRL_7S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_7S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_7S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_7S_CLREND (0x00000020u) +#define DMAC_CHCTRL_7S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_7S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_7S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_7S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_7S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_7S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_7S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_7S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_7S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_7S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_7S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_7S_SEL (0x00000007u) +#define DMAC_CHCFG_7S_SEL_SHIFT (0u) +#define DMAC_CHCFG_7S_REQD (0x00000008u) +#define DMAC_CHCFG_7S_REQD_SHIFT (3u) +#define DMAC_CHCFG_7S_LOEN (0x00000010u) +#define DMAC_CHCFG_7S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_7S_HIEN (0x00000020u) +#define DMAC_CHCFG_7S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_7S_LVL (0x00000040u) +#define DMAC_CHCFG_7S_LVL_SHIFT (6u) +#define DMAC_CHCFG_7S_AM (0x00000700u) +#define DMAC_CHCFG_7S_AM_SHIFT (8u) +#define DMAC_CHCFG_7S_SDS (0x0000F000u) +#define DMAC_CHCFG_7S_SDS_SHIFT (12u) +#define DMAC_CHCFG_7S_DDS (0x000F0000u) +#define DMAC_CHCFG_7S_DDS_SHIFT (16u) +#define DMAC_CHCFG_7S_SAD (0x00100000u) +#define DMAC_CHCFG_7S_SAD_SHIFT (20u) +#define DMAC_CHCFG_7S_DAD (0x00200000u) +#define DMAC_CHCFG_7S_DAD_SHIFT (21u) +#define DMAC_CHCFG_7S_TM (0x00400000u) +#define DMAC_CHCFG_7S_TM_SHIFT (22u) +#define DMAC_CHCFG_7S_DEM (0x01000000u) +#define DMAC_CHCFG_7S_DEM_SHIFT (24u) +#define DMAC_CHCFG_7S_SBE (0x08000000u) +#define DMAC_CHCFG_7S_SBE_SHIFT (27u) +#define DMAC_CHCFG_7S_RSEL (0x10000000u) +#define DMAC_CHCFG_7S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_7S_RSW (0x20000000u) +#define DMAC_CHCFG_7S_RSW_SHIFT (29u) +#define DMAC_CHCFG_7S_REN (0x40000000u) +#define DMAC_CHCFG_7S_REN_SHIFT (30u) +#define DMAC_CHCFG_7S_DMS (0x80000000u) +#define DMAC_CHCFG_7S_DMS_SHIFT (31u) +#define DMAC_CHITVL_7S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_7S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_7S_SPR (0x00000007u) +#define DMAC_CHEXT_7S_SPR_SHIFT (0u) +#define DMAC_CHEXT_7S_SCA (0x000000F0u) +#define DMAC_CHEXT_7S_SCA_SHIFT (4u) +#define DMAC_CHEXT_7S_DPR (0x00000700u) +#define DMAC_CHEXT_7S_DPR_SHIFT (8u) +#define DMAC_CHEXT_7S_DCA (0x0000F000u) +#define DMAC_CHEXT_7S_DCA_SHIFT (12u) +#define DMAC_NXLA_7S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_7S_NXLA_SHIFT (0u) +#define DMAC_CRLA_7S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_7S_CRLA_SHIFT (0u) +#define DMAC_DCTRL_0_7S_PR (0x00000001u) +#define DMAC_DCTRL_0_7S_PR_SHIFT (0u) +#define DMAC_DCTRL_0_7S_LVINT (0x00000002u) +#define DMAC_DCTRL_0_7S_LVINT_SHIFT (1u) +#define DMAC_DCTRL_0_7S_LDPR (0x00070000u) +#define DMAC_DCTRL_0_7S_LDPR_SHIFT (16u) +#define DMAC_DCTRL_0_7S_LDCA (0x00F00000u) +#define DMAC_DCTRL_0_7S_LDCA_SHIFT (20u) +#define DMAC_DCTRL_0_7S_LWPR (0x07000000u) +#define DMAC_DCTRL_0_7S_LWPR_SHIFT (24u) +#define DMAC_DCTRL_0_7S_LWCA (0xF0000000u) +#define DMAC_DCTRL_0_7S_LWCA_SHIFT (28u) +#define DMAC_DSTAT_EN_0_7S_EN0 (0x00000001u) +#define DMAC_DSTAT_EN_0_7S_EN0_SHIFT (0u) +#define DMAC_DSTAT_EN_0_7S_EN1 (0x00000002u) +#define DMAC_DSTAT_EN_0_7S_EN1_SHIFT (1u) +#define DMAC_DSTAT_EN_0_7S_EN2 (0x00000004u) +#define DMAC_DSTAT_EN_0_7S_EN2_SHIFT (2u) +#define DMAC_DSTAT_EN_0_7S_EN3 (0x00000008u) +#define DMAC_DSTAT_EN_0_7S_EN3_SHIFT (3u) +#define DMAC_DSTAT_EN_0_7S_EN4 (0x00000010u) +#define DMAC_DSTAT_EN_0_7S_EN4_SHIFT (4u) +#define DMAC_DSTAT_EN_0_7S_EN5 (0x00000020u) +#define DMAC_DSTAT_EN_0_7S_EN5_SHIFT (5u) +#define DMAC_DSTAT_EN_0_7S_EN6 (0x00000040u) +#define DMAC_DSTAT_EN_0_7S_EN6_SHIFT (6u) +#define DMAC_DSTAT_EN_0_7S_EN7 (0x00000080u) +#define DMAC_DSTAT_EN_0_7S_EN7_SHIFT (7u) +#define DMAC_DSTAT_ER_0_7S_ER0 (0x00000001u) +#define DMAC_DSTAT_ER_0_7S_ER0_SHIFT (0u) +#define DMAC_DSTAT_ER_0_7S_ER1 (0x00000002u) +#define DMAC_DSTAT_ER_0_7S_ER1_SHIFT (1u) +#define DMAC_DSTAT_ER_0_7S_ER2 (0x00000004u) +#define DMAC_DSTAT_ER_0_7S_ER2_SHIFT (2u) +#define DMAC_DSTAT_ER_0_7S_ER3 (0x00000008u) +#define DMAC_DSTAT_ER_0_7S_ER3_SHIFT (3u) +#define DMAC_DSTAT_ER_0_7S_ER4 (0x00000010u) +#define DMAC_DSTAT_ER_0_7S_ER4_SHIFT (4u) +#define DMAC_DSTAT_ER_0_7S_ER5 (0x00000020u) +#define DMAC_DSTAT_ER_0_7S_ER5_SHIFT (5u) +#define DMAC_DSTAT_ER_0_7S_ER6 (0x00000040u) +#define DMAC_DSTAT_ER_0_7S_ER6_SHIFT (6u) +#define DMAC_DSTAT_ER_0_7S_ER7 (0x00000080u) +#define DMAC_DSTAT_ER_0_7S_ER7_SHIFT (7u) +#define DMAC_DSTAT_END_0_7S_END0 (0x00000001u) +#define DMAC_DSTAT_END_0_7S_END0_SHIFT (0u) +#define DMAC_DSTAT_END_0_7S_END1 (0x00000002u) +#define DMAC_DSTAT_END_0_7S_END1_SHIFT (1u) +#define DMAC_DSTAT_END_0_7S_END2 (0x00000004u) +#define DMAC_DSTAT_END_0_7S_END2_SHIFT (2u) +#define DMAC_DSTAT_END_0_7S_END3 (0x00000008u) +#define DMAC_DSTAT_END_0_7S_END3_SHIFT (3u) +#define DMAC_DSTAT_END_0_7S_END4 (0x00000010u) +#define DMAC_DSTAT_END_0_7S_END4_SHIFT (4u) +#define DMAC_DSTAT_END_0_7S_END5 (0x00000020u) +#define DMAC_DSTAT_END_0_7S_END5_SHIFT (5u) +#define DMAC_DSTAT_END_0_7S_END6 (0x00000040u) +#define DMAC_DSTAT_END_0_7S_END6_SHIFT (6u) +#define DMAC_DSTAT_END_0_7S_END7 (0x00000080u) +#define DMAC_DSTAT_END_0_7S_END7_SHIFT (7u) +#define DMAC_DSTAT_TC_0_7S_TC0 (0x00000001u) +#define DMAC_DSTAT_TC_0_7S_TC0_SHIFT (0u) +#define DMAC_DSTAT_TC_0_7S_TC1 (0x00000002u) +#define DMAC_DSTAT_TC_0_7S_TC1_SHIFT (1u) +#define DMAC_DSTAT_TC_0_7S_TC2 (0x00000004u) +#define DMAC_DSTAT_TC_0_7S_TC2_SHIFT (2u) +#define DMAC_DSTAT_TC_0_7S_TC3 (0x00000008u) +#define DMAC_DSTAT_TC_0_7S_TC3_SHIFT (3u) +#define DMAC_DSTAT_TC_0_7S_TC4 (0x00000010u) +#define DMAC_DSTAT_TC_0_7S_TC4_SHIFT (4u) +#define DMAC_DSTAT_TC_0_7S_TC5 (0x00000020u) +#define DMAC_DSTAT_TC_0_7S_TC5_SHIFT (5u) +#define DMAC_DSTAT_TC_0_7S_TC6 (0x00000040u) +#define DMAC_DSTAT_TC_0_7S_TC6_SHIFT (6u) +#define DMAC_DSTAT_TC_0_7S_TC7 (0x00000080u) +#define DMAC_DSTAT_TC_0_7S_TC7_SHIFT (7u) +#define DMAC_DSTAT_SUS_0_7S_SUS0 (0x00000001u) +#define DMAC_DSTAT_SUS_0_7S_SUS0_SHIFT (0u) +#define DMAC_DSTAT_SUS_0_7S_SUS1 (0x00000002u) +#define DMAC_DSTAT_SUS_0_7S_SUS1_SHIFT (1u) +#define DMAC_DSTAT_SUS_0_7S_SUS2 (0x00000004u) +#define DMAC_DSTAT_SUS_0_7S_SUS2_SHIFT (2u) +#define DMAC_DSTAT_SUS_0_7S_SUS3 (0x00000008u) +#define DMAC_DSTAT_SUS_0_7S_SUS3_SHIFT (3u) +#define DMAC_DSTAT_SUS_0_7S_SUS4 (0x00000010u) +#define DMAC_DSTAT_SUS_0_7S_SUS4_SHIFT (4u) +#define DMAC_DSTAT_SUS_0_7S_SUS5 (0x00000020u) +#define DMAC_DSTAT_SUS_0_7S_SUS5_SHIFT (5u) +#define DMAC_DSTAT_SUS_0_7S_SUS6 (0x00000040u) +#define DMAC_DSTAT_SUS_0_7S_SUS6_SHIFT (6u) +#define DMAC_DSTAT_SUS_0_7S_SUS7 (0x00000080u) +#define DMAC_DSTAT_SUS_0_7S_SUS7_SHIFT (7u) +#define DMAC_N0SA_8S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_8S_SA_SHIFT (0u) +#define DMAC_N0DA_8S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_8S_DA_SHIFT (0u) +#define DMAC_N0TB_8S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_8S_TB_SHIFT (0u) +#define DMAC_N1SA_8S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_8S_SA_SHIFT (0u) +#define DMAC_N1DA_8S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_8S_DA_SHIFT (0u) +#define DMAC_N1TB_8S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_8S_TB_SHIFT (0u) +#define DMAC_CRSA_8S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_8S_CRSA_SHIFT (0u) +#define DMAC_CRDA_8S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_8S_CRDA_SHIFT (0u) +#define DMAC_CRTB_8S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_8S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_8S_EN (0x00000001u) +#define DMAC_CHSTAT_8S_EN_SHIFT (0u) +#define DMAC_CHSTAT_8S_RQST (0x00000002u) +#define DMAC_CHSTAT_8S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_8S_TACT (0x00000004u) +#define DMAC_CHSTAT_8S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_8S_SUS (0x00000008u) +#define DMAC_CHSTAT_8S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_8S_ER (0x00000010u) +#define DMAC_CHSTAT_8S_ER_SHIFT (4u) +#define DMAC_CHSTAT_8S_END (0x00000020u) +#define DMAC_CHSTAT_8S_END_SHIFT (5u) +#define DMAC_CHSTAT_8S_TC (0x00000040u) +#define DMAC_CHSTAT_8S_TC_SHIFT (6u) +#define DMAC_CHSTAT_8S_SR (0x00000080u) +#define DMAC_CHSTAT_8S_SR_SHIFT (7u) +#define DMAC_CHSTAT_8S_DL (0x00000100u) +#define DMAC_CHSTAT_8S_DL_SHIFT (8u) +#define DMAC_CHSTAT_8S_DW (0x00000200u) +#define DMAC_CHSTAT_8S_DW_SHIFT (9u) +#define DMAC_CHSTAT_8S_DER (0x00000400u) +#define DMAC_CHSTAT_8S_DER_SHIFT (10u) +#define DMAC_CHSTAT_8S_MODE (0x00000800u) +#define DMAC_CHSTAT_8S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_8S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_8S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_8S_SETEN (0x00000001u) +#define DMAC_CHCTRL_8S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_8S_CLREN (0x00000002u) +#define DMAC_CHCTRL_8S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_8S_STG (0x00000004u) +#define DMAC_CHCTRL_8S_STG_SHIFT (2u) +#define DMAC_CHCTRL_8S_SWRST (0x00000008u) +#define DMAC_CHCTRL_8S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_8S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_8S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_8S_CLREND (0x00000020u) +#define DMAC_CHCTRL_8S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_8S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_8S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_8S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_8S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_8S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_8S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_8S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_8S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_8S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_8S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_8S_SEL (0x00000007u) +#define DMAC_CHCFG_8S_SEL_SHIFT (0u) +#define DMAC_CHCFG_8S_REQD (0x00000008u) +#define DMAC_CHCFG_8S_REQD_SHIFT (3u) +#define DMAC_CHCFG_8S_LOEN (0x00000010u) +#define DMAC_CHCFG_8S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_8S_HIEN (0x00000020u) +#define DMAC_CHCFG_8S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_8S_LVL (0x00000040u) +#define DMAC_CHCFG_8S_LVL_SHIFT (6u) +#define DMAC_CHCFG_8S_AM (0x00000700u) +#define DMAC_CHCFG_8S_AM_SHIFT (8u) +#define DMAC_CHCFG_8S_SDS (0x0000F000u) +#define DMAC_CHCFG_8S_SDS_SHIFT (12u) +#define DMAC_CHCFG_8S_DDS (0x000F0000u) +#define DMAC_CHCFG_8S_DDS_SHIFT (16u) +#define DMAC_CHCFG_8S_SAD (0x00100000u) +#define DMAC_CHCFG_8S_SAD_SHIFT (20u) +#define DMAC_CHCFG_8S_DAD (0x00200000u) +#define DMAC_CHCFG_8S_DAD_SHIFT (21u) +#define DMAC_CHCFG_8S_TM (0x00400000u) +#define DMAC_CHCFG_8S_TM_SHIFT (22u) +#define DMAC_CHCFG_8S_DEM (0x01000000u) +#define DMAC_CHCFG_8S_DEM_SHIFT (24u) +#define DMAC_CHCFG_8S_SBE (0x08000000u) +#define DMAC_CHCFG_8S_SBE_SHIFT (27u) +#define DMAC_CHCFG_8S_RSEL (0x10000000u) +#define DMAC_CHCFG_8S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_8S_RSW (0x20000000u) +#define DMAC_CHCFG_8S_RSW_SHIFT (29u) +#define DMAC_CHCFG_8S_REN (0x40000000u) +#define DMAC_CHCFG_8S_REN_SHIFT (30u) +#define DMAC_CHCFG_8S_DMS (0x80000000u) +#define DMAC_CHCFG_8S_DMS_SHIFT (31u) +#define DMAC_CHITVL_8S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_8S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_8S_SPR (0x00000007u) +#define DMAC_CHEXT_8S_SPR_SHIFT (0u) +#define DMAC_CHEXT_8S_SCA (0x000000F0u) +#define DMAC_CHEXT_8S_SCA_SHIFT (4u) +#define DMAC_CHEXT_8S_DPR (0x00000700u) +#define DMAC_CHEXT_8S_DPR_SHIFT (8u) +#define DMAC_CHEXT_8S_DCA (0x0000F000u) +#define DMAC_CHEXT_8S_DCA_SHIFT (12u) +#define DMAC_NXLA_8S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_8S_NXLA_SHIFT (0u) +#define DMAC_CRLA_8S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_8S_CRLA_SHIFT (0u) +#define DMAC_N0SA_9S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_9S_SA_SHIFT (0u) +#define DMAC_N0DA_9S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_9S_DA_SHIFT (0u) +#define DMAC_N0TB_9S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_9S_TB_SHIFT (0u) +#define DMAC_N1SA_9S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_9S_SA_SHIFT (0u) +#define DMAC_N1DA_9S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_9S_DA_SHIFT (0u) +#define DMAC_N1TB_9S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_9S_TB_SHIFT (0u) +#define DMAC_CRSA_9S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_9S_CRSA_SHIFT (0u) +#define DMAC_CRDA_9S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_9S_CRDA_SHIFT (0u) +#define DMAC_CRTB_9S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_9S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_9S_EN (0x00000001u) +#define DMAC_CHSTAT_9S_EN_SHIFT (0u) +#define DMAC_CHSTAT_9S_RQST (0x00000002u) +#define DMAC_CHSTAT_9S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_9S_TACT (0x00000004u) +#define DMAC_CHSTAT_9S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_9S_SUS (0x00000008u) +#define DMAC_CHSTAT_9S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_9S_ER (0x00000010u) +#define DMAC_CHSTAT_9S_ER_SHIFT (4u) +#define DMAC_CHSTAT_9S_END (0x00000020u) +#define DMAC_CHSTAT_9S_END_SHIFT (5u) +#define DMAC_CHSTAT_9S_TC (0x00000040u) +#define DMAC_CHSTAT_9S_TC_SHIFT (6u) +#define DMAC_CHSTAT_9S_SR (0x00000080u) +#define DMAC_CHSTAT_9S_SR_SHIFT (7u) +#define DMAC_CHSTAT_9S_DL (0x00000100u) +#define DMAC_CHSTAT_9S_DL_SHIFT (8u) +#define DMAC_CHSTAT_9S_DW (0x00000200u) +#define DMAC_CHSTAT_9S_DW_SHIFT (9u) +#define DMAC_CHSTAT_9S_DER (0x00000400u) +#define DMAC_CHSTAT_9S_DER_SHIFT (10u) +#define DMAC_CHSTAT_9S_MODE (0x00000800u) +#define DMAC_CHSTAT_9S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_9S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_9S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_9S_SETEN (0x00000001u) +#define DMAC_CHCTRL_9S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_9S_CLREN (0x00000002u) +#define DMAC_CHCTRL_9S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_9S_STG (0x00000004u) +#define DMAC_CHCTRL_9S_STG_SHIFT (2u) +#define DMAC_CHCTRL_9S_SWRST (0x00000008u) +#define DMAC_CHCTRL_9S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_9S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_9S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_9S_CLREND (0x00000020u) +#define DMAC_CHCTRL_9S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_9S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_9S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_9S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_9S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_9S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_9S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_9S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_9S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_9S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_9S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_9S_SEL (0x00000007u) +#define DMAC_CHCFG_9S_SEL_SHIFT (0u) +#define DMAC_CHCFG_9S_REQD (0x00000008u) +#define DMAC_CHCFG_9S_REQD_SHIFT (3u) +#define DMAC_CHCFG_9S_LOEN (0x00000010u) +#define DMAC_CHCFG_9S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_9S_HIEN (0x00000020u) +#define DMAC_CHCFG_9S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_9S_LVL (0x00000040u) +#define DMAC_CHCFG_9S_LVL_SHIFT (6u) +#define DMAC_CHCFG_9S_AM (0x00000700u) +#define DMAC_CHCFG_9S_AM_SHIFT (8u) +#define DMAC_CHCFG_9S_SDS (0x0000F000u) +#define DMAC_CHCFG_9S_SDS_SHIFT (12u) +#define DMAC_CHCFG_9S_DDS (0x000F0000u) +#define DMAC_CHCFG_9S_DDS_SHIFT (16u) +#define DMAC_CHCFG_9S_SAD (0x00100000u) +#define DMAC_CHCFG_9S_SAD_SHIFT (20u) +#define DMAC_CHCFG_9S_DAD (0x00200000u) +#define DMAC_CHCFG_9S_DAD_SHIFT (21u) +#define DMAC_CHCFG_9S_TM (0x00400000u) +#define DMAC_CHCFG_9S_TM_SHIFT (22u) +#define DMAC_CHCFG_9S_DEM (0x01000000u) +#define DMAC_CHCFG_9S_DEM_SHIFT (24u) +#define DMAC_CHCFG_9S_SBE (0x08000000u) +#define DMAC_CHCFG_9S_SBE_SHIFT (27u) +#define DMAC_CHCFG_9S_RSEL (0x10000000u) +#define DMAC_CHCFG_9S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_9S_RSW (0x20000000u) +#define DMAC_CHCFG_9S_RSW_SHIFT (29u) +#define DMAC_CHCFG_9S_REN (0x40000000u) +#define DMAC_CHCFG_9S_REN_SHIFT (30u) +#define DMAC_CHCFG_9S_DMS (0x80000000u) +#define DMAC_CHCFG_9S_DMS_SHIFT (31u) +#define DMAC_CHITVL_9S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_9S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_9S_SPR (0x00000007u) +#define DMAC_CHEXT_9S_SPR_SHIFT (0u) +#define DMAC_CHEXT_9S_SCA (0x000000F0u) +#define DMAC_CHEXT_9S_SCA_SHIFT (4u) +#define DMAC_CHEXT_9S_DPR (0x00000700u) +#define DMAC_CHEXT_9S_DPR_SHIFT (8u) +#define DMAC_CHEXT_9S_DCA (0x0000F000u) +#define DMAC_CHEXT_9S_DCA_SHIFT (12u) +#define DMAC_NXLA_9S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_9S_NXLA_SHIFT (0u) +#define DMAC_CRLA_9S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_9S_CRLA_SHIFT (0u) +#define DMAC_N0SA_10S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_10S_SA_SHIFT (0u) +#define DMAC_N0DA_10S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_10S_DA_SHIFT (0u) +#define DMAC_N0TB_10S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_10S_TB_SHIFT (0u) +#define DMAC_N1SA_10S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_10S_SA_SHIFT (0u) +#define DMAC_N1DA_10S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_10S_DA_SHIFT (0u) +#define DMAC_N1TB_10S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_10S_TB_SHIFT (0u) +#define DMAC_CRSA_10S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_10S_CRSA_SHIFT (0u) +#define DMAC_CRDA_10S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_10S_CRDA_SHIFT (0u) +#define DMAC_CRTB_10S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_10S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_10S_EN (0x00000001u) +#define DMAC_CHSTAT_10S_EN_SHIFT (0u) +#define DMAC_CHSTAT_10S_RQST (0x00000002u) +#define DMAC_CHSTAT_10S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_10S_TACT (0x00000004u) +#define DMAC_CHSTAT_10S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_10S_SUS (0x00000008u) +#define DMAC_CHSTAT_10S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_10S_ER (0x00000010u) +#define DMAC_CHSTAT_10S_ER_SHIFT (4u) +#define DMAC_CHSTAT_10S_END (0x00000020u) +#define DMAC_CHSTAT_10S_END_SHIFT (5u) +#define DMAC_CHSTAT_10S_TC (0x00000040u) +#define DMAC_CHSTAT_10S_TC_SHIFT (6u) +#define DMAC_CHSTAT_10S_SR (0x00000080u) +#define DMAC_CHSTAT_10S_SR_SHIFT (7u) +#define DMAC_CHSTAT_10S_DL (0x00000100u) +#define DMAC_CHSTAT_10S_DL_SHIFT (8u) +#define DMAC_CHSTAT_10S_DW (0x00000200u) +#define DMAC_CHSTAT_10S_DW_SHIFT (9u) +#define DMAC_CHSTAT_10S_DER (0x00000400u) +#define DMAC_CHSTAT_10S_DER_SHIFT (10u) +#define DMAC_CHSTAT_10S_MODE (0x00000800u) +#define DMAC_CHSTAT_10S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_10S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_10S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_10S_SETEN (0x00000001u) +#define DMAC_CHCTRL_10S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_10S_CLREN (0x00000002u) +#define DMAC_CHCTRL_10S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_10S_STG (0x00000004u) +#define DMAC_CHCTRL_10S_STG_SHIFT (2u) +#define DMAC_CHCTRL_10S_SWRST (0x00000008u) +#define DMAC_CHCTRL_10S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_10S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_10S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_10S_CLREND (0x00000020u) +#define DMAC_CHCTRL_10S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_10S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_10S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_10S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_10S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_10S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_10S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_10S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_10S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_10S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_10S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_10S_SEL (0x00000007u) +#define DMAC_CHCFG_10S_SEL_SHIFT (0u) +#define DMAC_CHCFG_10S_REQD (0x00000008u) +#define DMAC_CHCFG_10S_REQD_SHIFT (3u) +#define DMAC_CHCFG_10S_LOEN (0x00000010u) +#define DMAC_CHCFG_10S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_10S_HIEN (0x00000020u) +#define DMAC_CHCFG_10S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_10S_LVL (0x00000040u) +#define DMAC_CHCFG_10S_LVL_SHIFT (6u) +#define DMAC_CHCFG_10S_AM (0x00000700u) +#define DMAC_CHCFG_10S_AM_SHIFT (8u) +#define DMAC_CHCFG_10S_SDS (0x0000F000u) +#define DMAC_CHCFG_10S_SDS_SHIFT (12u) +#define DMAC_CHCFG_10S_DDS (0x000F0000u) +#define DMAC_CHCFG_10S_DDS_SHIFT (16u) +#define DMAC_CHCFG_10S_SAD (0x00100000u) +#define DMAC_CHCFG_10S_SAD_SHIFT (20u) +#define DMAC_CHCFG_10S_DAD (0x00200000u) +#define DMAC_CHCFG_10S_DAD_SHIFT (21u) +#define DMAC_CHCFG_10S_TM (0x00400000u) +#define DMAC_CHCFG_10S_TM_SHIFT (22u) +#define DMAC_CHCFG_10S_DEM (0x01000000u) +#define DMAC_CHCFG_10S_DEM_SHIFT (24u) +#define DMAC_CHCFG_10S_SBE (0x08000000u) +#define DMAC_CHCFG_10S_SBE_SHIFT (27u) +#define DMAC_CHCFG_10S_RSEL (0x10000000u) +#define DMAC_CHCFG_10S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_10S_RSW (0x20000000u) +#define DMAC_CHCFG_10S_RSW_SHIFT (29u) +#define DMAC_CHCFG_10S_REN (0x40000000u) +#define DMAC_CHCFG_10S_REN_SHIFT (30u) +#define DMAC_CHCFG_10S_DMS (0x80000000u) +#define DMAC_CHCFG_10S_DMS_SHIFT (31u) +#define DMAC_CHITVL_10S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_10S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_10S_SPR (0x00000007u) +#define DMAC_CHEXT_10S_SPR_SHIFT (0u) +#define DMAC_CHEXT_10S_SCA (0x000000F0u) +#define DMAC_CHEXT_10S_SCA_SHIFT (4u) +#define DMAC_CHEXT_10S_DPR (0x00000700u) +#define DMAC_CHEXT_10S_DPR_SHIFT (8u) +#define DMAC_CHEXT_10S_DCA (0x0000F000u) +#define DMAC_CHEXT_10S_DCA_SHIFT (12u) +#define DMAC_NXLA_10S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_10S_NXLA_SHIFT (0u) +#define DMAC_CRLA_10S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_10S_CRLA_SHIFT (0u) +#define DMAC_N0SA_11S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_11S_SA_SHIFT (0u) +#define DMAC_N0DA_11S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_11S_DA_SHIFT (0u) +#define DMAC_N0TB_11S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_11S_TB_SHIFT (0u) +#define DMAC_N1SA_11S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_11S_SA_SHIFT (0u) +#define DMAC_N1DA_11S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_11S_DA_SHIFT (0u) +#define DMAC_N1TB_11S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_11S_TB_SHIFT (0u) +#define DMAC_CRSA_11S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_11S_CRSA_SHIFT (0u) +#define DMAC_CRDA_11S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_11S_CRDA_SHIFT (0u) +#define DMAC_CRTB_11S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_11S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_11S_EN (0x00000001u) +#define DMAC_CHSTAT_11S_EN_SHIFT (0u) +#define DMAC_CHSTAT_11S_RQST (0x00000002u) +#define DMAC_CHSTAT_11S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_11S_TACT (0x00000004u) +#define DMAC_CHSTAT_11S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_11S_SUS (0x00000008u) +#define DMAC_CHSTAT_11S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_11S_ER (0x00000010u) +#define DMAC_CHSTAT_11S_ER_SHIFT (4u) +#define DMAC_CHSTAT_11S_END (0x00000020u) +#define DMAC_CHSTAT_11S_END_SHIFT (5u) +#define DMAC_CHSTAT_11S_TC (0x00000040u) +#define DMAC_CHSTAT_11S_TC_SHIFT (6u) +#define DMAC_CHSTAT_11S_SR (0x00000080u) +#define DMAC_CHSTAT_11S_SR_SHIFT (7u) +#define DMAC_CHSTAT_11S_DL (0x00000100u) +#define DMAC_CHSTAT_11S_DL_SHIFT (8u) +#define DMAC_CHSTAT_11S_DW (0x00000200u) +#define DMAC_CHSTAT_11S_DW_SHIFT (9u) +#define DMAC_CHSTAT_11S_DER (0x00000400u) +#define DMAC_CHSTAT_11S_DER_SHIFT (10u) +#define DMAC_CHSTAT_11S_MODE (0x00000800u) +#define DMAC_CHSTAT_11S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_11S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_11S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_11S_SETEN (0x00000001u) +#define DMAC_CHCTRL_11S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_11S_CLREN (0x00000002u) +#define DMAC_CHCTRL_11S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_11S_STG (0x00000004u) +#define DMAC_CHCTRL_11S_STG_SHIFT (2u) +#define DMAC_CHCTRL_11S_SWRST (0x00000008u) +#define DMAC_CHCTRL_11S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_11S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_11S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_11S_CLREND (0x00000020u) +#define DMAC_CHCTRL_11S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_11S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_11S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_11S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_11S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_11S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_11S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_11S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_11S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_11S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_11S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_11S_SEL (0x00000007u) +#define DMAC_CHCFG_11S_SEL_SHIFT (0u) +#define DMAC_CHCFG_11S_REQD (0x00000008u) +#define DMAC_CHCFG_11S_REQD_SHIFT (3u) +#define DMAC_CHCFG_11S_LOEN (0x00000010u) +#define DMAC_CHCFG_11S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_11S_HIEN (0x00000020u) +#define DMAC_CHCFG_11S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_11S_LVL (0x00000040u) +#define DMAC_CHCFG_11S_LVL_SHIFT (6u) +#define DMAC_CHCFG_11S_AM (0x00000700u) +#define DMAC_CHCFG_11S_AM_SHIFT (8u) +#define DMAC_CHCFG_11S_SDS (0x0000F000u) +#define DMAC_CHCFG_11S_SDS_SHIFT (12u) +#define DMAC_CHCFG_11S_DDS (0x000F0000u) +#define DMAC_CHCFG_11S_DDS_SHIFT (16u) +#define DMAC_CHCFG_11S_SAD (0x00100000u) +#define DMAC_CHCFG_11S_SAD_SHIFT (20u) +#define DMAC_CHCFG_11S_DAD (0x00200000u) +#define DMAC_CHCFG_11S_DAD_SHIFT (21u) +#define DMAC_CHCFG_11S_TM (0x00400000u) +#define DMAC_CHCFG_11S_TM_SHIFT (22u) +#define DMAC_CHCFG_11S_DEM (0x01000000u) +#define DMAC_CHCFG_11S_DEM_SHIFT (24u) +#define DMAC_CHCFG_11S_SBE (0x08000000u) +#define DMAC_CHCFG_11S_SBE_SHIFT (27u) +#define DMAC_CHCFG_11S_RSEL (0x10000000u) +#define DMAC_CHCFG_11S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_11S_RSW (0x20000000u) +#define DMAC_CHCFG_11S_RSW_SHIFT (29u) +#define DMAC_CHCFG_11S_REN (0x40000000u) +#define DMAC_CHCFG_11S_REN_SHIFT (30u) +#define DMAC_CHCFG_11S_DMS (0x80000000u) +#define DMAC_CHCFG_11S_DMS_SHIFT (31u) +#define DMAC_CHITVL_11S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_11S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_11S_SPR (0x00000007u) +#define DMAC_CHEXT_11S_SPR_SHIFT (0u) +#define DMAC_CHEXT_11S_SCA (0x000000F0u) +#define DMAC_CHEXT_11S_SCA_SHIFT (4u) +#define DMAC_CHEXT_11S_DPR (0x00000700u) +#define DMAC_CHEXT_11S_DPR_SHIFT (8u) +#define DMAC_CHEXT_11S_DCA (0x0000F000u) +#define DMAC_CHEXT_11S_DCA_SHIFT (12u) +#define DMAC_NXLA_11S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_11S_NXLA_SHIFT (0u) +#define DMAC_CRLA_11S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_11S_CRLA_SHIFT (0u) +#define DMAC_N0SA_12S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_12S_SA_SHIFT (0u) +#define DMAC_N0DA_12S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_12S_DA_SHIFT (0u) +#define DMAC_N0TB_12S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_12S_TB_SHIFT (0u) +#define DMAC_N1SA_12S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_12S_SA_SHIFT (0u) +#define DMAC_N1DA_12S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_12S_DA_SHIFT (0u) +#define DMAC_N1TB_12S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_12S_TB_SHIFT (0u) +#define DMAC_CRSA_12S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_12S_CRSA_SHIFT (0u) +#define DMAC_CRDA_12S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_12S_CRDA_SHIFT (0u) +#define DMAC_CRTB_12S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_12S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_12S_EN (0x00000001u) +#define DMAC_CHSTAT_12S_EN_SHIFT (0u) +#define DMAC_CHSTAT_12S_RQST (0x00000002u) +#define DMAC_CHSTAT_12S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_12S_TACT (0x00000004u) +#define DMAC_CHSTAT_12S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_12S_SUS (0x00000008u) +#define DMAC_CHSTAT_12S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_12S_ER (0x00000010u) +#define DMAC_CHSTAT_12S_ER_SHIFT (4u) +#define DMAC_CHSTAT_12S_END (0x00000020u) +#define DMAC_CHSTAT_12S_END_SHIFT (5u) +#define DMAC_CHSTAT_12S_TC (0x00000040u) +#define DMAC_CHSTAT_12S_TC_SHIFT (6u) +#define DMAC_CHSTAT_12S_SR (0x00000080u) +#define DMAC_CHSTAT_12S_SR_SHIFT (7u) +#define DMAC_CHSTAT_12S_DL (0x00000100u) +#define DMAC_CHSTAT_12S_DL_SHIFT (8u) +#define DMAC_CHSTAT_12S_DW (0x00000200u) +#define DMAC_CHSTAT_12S_DW_SHIFT (9u) +#define DMAC_CHSTAT_12S_DER (0x00000400u) +#define DMAC_CHSTAT_12S_DER_SHIFT (10u) +#define DMAC_CHSTAT_12S_MODE (0x00000800u) +#define DMAC_CHSTAT_12S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_12S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_12S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_12S_SETEN (0x00000001u) +#define DMAC_CHCTRL_12S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_12S_CLREN (0x00000002u) +#define DMAC_CHCTRL_12S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_12S_STG (0x00000004u) +#define DMAC_CHCTRL_12S_STG_SHIFT (2u) +#define DMAC_CHCTRL_12S_SWRST (0x00000008u) +#define DMAC_CHCTRL_12S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_12S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_12S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_12S_CLREND (0x00000020u) +#define DMAC_CHCTRL_12S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_12S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_12S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_12S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_12S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_12S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_12S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_12S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_12S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_12S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_12S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_12S_SEL (0x00000007u) +#define DMAC_CHCFG_12S_SEL_SHIFT (0u) +#define DMAC_CHCFG_12S_REQD (0x00000008u) +#define DMAC_CHCFG_12S_REQD_SHIFT (3u) +#define DMAC_CHCFG_12S_LOEN (0x00000010u) +#define DMAC_CHCFG_12S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_12S_HIEN (0x00000020u) +#define DMAC_CHCFG_12S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_12S_LVL (0x00000040u) +#define DMAC_CHCFG_12S_LVL_SHIFT (6u) +#define DMAC_CHCFG_12S_AM (0x00000700u) +#define DMAC_CHCFG_12S_AM_SHIFT (8u) +#define DMAC_CHCFG_12S_SDS (0x0000F000u) +#define DMAC_CHCFG_12S_SDS_SHIFT (12u) +#define DMAC_CHCFG_12S_DDS (0x000F0000u) +#define DMAC_CHCFG_12S_DDS_SHIFT (16u) +#define DMAC_CHCFG_12S_SAD (0x00100000u) +#define DMAC_CHCFG_12S_SAD_SHIFT (20u) +#define DMAC_CHCFG_12S_DAD (0x00200000u) +#define DMAC_CHCFG_12S_DAD_SHIFT (21u) +#define DMAC_CHCFG_12S_TM (0x00400000u) +#define DMAC_CHCFG_12S_TM_SHIFT (22u) +#define DMAC_CHCFG_12S_DEM (0x01000000u) +#define DMAC_CHCFG_12S_DEM_SHIFT (24u) +#define DMAC_CHCFG_12S_SBE (0x08000000u) +#define DMAC_CHCFG_12S_SBE_SHIFT (27u) +#define DMAC_CHCFG_12S_RSEL (0x10000000u) +#define DMAC_CHCFG_12S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_12S_RSW (0x20000000u) +#define DMAC_CHCFG_12S_RSW_SHIFT (29u) +#define DMAC_CHCFG_12S_REN (0x40000000u) +#define DMAC_CHCFG_12S_REN_SHIFT (30u) +#define DMAC_CHCFG_12S_DMS (0x80000000u) +#define DMAC_CHCFG_12S_DMS_SHIFT (31u) +#define DMAC_CHITVL_12S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_12S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_12S_SPR (0x00000007u) +#define DMAC_CHEXT_12S_SPR_SHIFT (0u) +#define DMAC_CHEXT_12S_SCA (0x000000F0u) +#define DMAC_CHEXT_12S_SCA_SHIFT (4u) +#define DMAC_CHEXT_12S_DPR (0x00000700u) +#define DMAC_CHEXT_12S_DPR_SHIFT (8u) +#define DMAC_CHEXT_12S_DCA (0x0000F000u) +#define DMAC_CHEXT_12S_DCA_SHIFT (12u) +#define DMAC_NXLA_12S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_12S_NXLA_SHIFT (0u) +#define DMAC_CRLA_12S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_12S_CRLA_SHIFT (0u) +#define DMAC_N0SA_13S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_13S_SA_SHIFT (0u) +#define DMAC_N0DA_13S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_13S_DA_SHIFT (0u) +#define DMAC_N0TB_13S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_13S_TB_SHIFT (0u) +#define DMAC_N1SA_13S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_13S_SA_SHIFT (0u) +#define DMAC_N1DA_13S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_13S_DA_SHIFT (0u) +#define DMAC_N1TB_13S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_13S_TB_SHIFT (0u) +#define DMAC_CRSA_13S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_13S_CRSA_SHIFT (0u) +#define DMAC_CRDA_13S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_13S_CRDA_SHIFT (0u) +#define DMAC_CRTB_13S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_13S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_13S_EN (0x00000001u) +#define DMAC_CHSTAT_13S_EN_SHIFT (0u) +#define DMAC_CHSTAT_13S_RQST (0x00000002u) +#define DMAC_CHSTAT_13S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_13S_TACT (0x00000004u) +#define DMAC_CHSTAT_13S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_13S_SUS (0x00000008u) +#define DMAC_CHSTAT_13S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_13S_ER (0x00000010u) +#define DMAC_CHSTAT_13S_ER_SHIFT (4u) +#define DMAC_CHSTAT_13S_END (0x00000020u) +#define DMAC_CHSTAT_13S_END_SHIFT (5u) +#define DMAC_CHSTAT_13S_TC (0x00000040u) +#define DMAC_CHSTAT_13S_TC_SHIFT (6u) +#define DMAC_CHSTAT_13S_SR (0x00000080u) +#define DMAC_CHSTAT_13S_SR_SHIFT (7u) +#define DMAC_CHSTAT_13S_DL (0x00000100u) +#define DMAC_CHSTAT_13S_DL_SHIFT (8u) +#define DMAC_CHSTAT_13S_DW (0x00000200u) +#define DMAC_CHSTAT_13S_DW_SHIFT (9u) +#define DMAC_CHSTAT_13S_DER (0x00000400u) +#define DMAC_CHSTAT_13S_DER_SHIFT (10u) +#define DMAC_CHSTAT_13S_MODE (0x00000800u) +#define DMAC_CHSTAT_13S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_13S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_13S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_13S_SETEN (0x00000001u) +#define DMAC_CHCTRL_13S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_13S_CLREN (0x00000002u) +#define DMAC_CHCTRL_13S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_13S_STG (0x00000004u) +#define DMAC_CHCTRL_13S_STG_SHIFT (2u) +#define DMAC_CHCTRL_13S_SWRST (0x00000008u) +#define DMAC_CHCTRL_13S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_13S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_13S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_13S_CLREND (0x00000020u) +#define DMAC_CHCTRL_13S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_13S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_13S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_13S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_13S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_13S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_13S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_13S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_13S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_13S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_13S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_13S_SEL (0x00000007u) +#define DMAC_CHCFG_13S_SEL_SHIFT (0u) +#define DMAC_CHCFG_13S_REQD (0x00000008u) +#define DMAC_CHCFG_13S_REQD_SHIFT (3u) +#define DMAC_CHCFG_13S_LOEN (0x00000010u) +#define DMAC_CHCFG_13S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_13S_HIEN (0x00000020u) +#define DMAC_CHCFG_13S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_13S_LVL (0x00000040u) +#define DMAC_CHCFG_13S_LVL_SHIFT (6u) +#define DMAC_CHCFG_13S_AM (0x00000700u) +#define DMAC_CHCFG_13S_AM_SHIFT (8u) +#define DMAC_CHCFG_13S_SDS (0x0000F000u) +#define DMAC_CHCFG_13S_SDS_SHIFT (12u) +#define DMAC_CHCFG_13S_DDS (0x000F0000u) +#define DMAC_CHCFG_13S_DDS_SHIFT (16u) +#define DMAC_CHCFG_13S_SAD (0x00100000u) +#define DMAC_CHCFG_13S_SAD_SHIFT (20u) +#define DMAC_CHCFG_13S_DAD (0x00200000u) +#define DMAC_CHCFG_13S_DAD_SHIFT (21u) +#define DMAC_CHCFG_13S_TM (0x00400000u) +#define DMAC_CHCFG_13S_TM_SHIFT (22u) +#define DMAC_CHCFG_13S_DEM (0x01000000u) +#define DMAC_CHCFG_13S_DEM_SHIFT (24u) +#define DMAC_CHCFG_13S_SBE (0x08000000u) +#define DMAC_CHCFG_13S_SBE_SHIFT (27u) +#define DMAC_CHCFG_13S_RSEL (0x10000000u) +#define DMAC_CHCFG_13S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_13S_RSW (0x20000000u) +#define DMAC_CHCFG_13S_RSW_SHIFT (29u) +#define DMAC_CHCFG_13S_REN (0x40000000u) +#define DMAC_CHCFG_13S_REN_SHIFT (30u) +#define DMAC_CHCFG_13S_DMS (0x80000000u) +#define DMAC_CHCFG_13S_DMS_SHIFT (31u) +#define DMAC_CHITVL_13S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_13S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_13S_SPR (0x00000007u) +#define DMAC_CHEXT_13S_SPR_SHIFT (0u) +#define DMAC_CHEXT_13S_SCA (0x000000F0u) +#define DMAC_CHEXT_13S_SCA_SHIFT (4u) +#define DMAC_CHEXT_13S_DPR (0x00000700u) +#define DMAC_CHEXT_13S_DPR_SHIFT (8u) +#define DMAC_CHEXT_13S_DCA (0x0000F000u) +#define DMAC_CHEXT_13S_DCA_SHIFT (12u) +#define DMAC_NXLA_13S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_13S_NXLA_SHIFT (0u) +#define DMAC_CRLA_13S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_13S_CRLA_SHIFT (0u) +#define DMAC_N0SA_14S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_14S_SA_SHIFT (0u) +#define DMAC_N0DA_14S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_14S_DA_SHIFT (0u) +#define DMAC_N0TB_14S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_14S_TB_SHIFT (0u) +#define DMAC_N1SA_14S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_14S_SA_SHIFT (0u) +#define DMAC_N1DA_14S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_14S_DA_SHIFT (0u) +#define DMAC_N1TB_14S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_14S_TB_SHIFT (0u) +#define DMAC_CRSA_14S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_14S_CRSA_SHIFT (0u) +#define DMAC_CRDA_14S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_14S_CRDA_SHIFT (0u) +#define DMAC_CRTB_14S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_14S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_14S_EN (0x00000001u) +#define DMAC_CHSTAT_14S_EN_SHIFT (0u) +#define DMAC_CHSTAT_14S_RQST (0x00000002u) +#define DMAC_CHSTAT_14S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_14S_TACT (0x00000004u) +#define DMAC_CHSTAT_14S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_14S_SUS (0x00000008u) +#define DMAC_CHSTAT_14S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_14S_ER (0x00000010u) +#define DMAC_CHSTAT_14S_ER_SHIFT (4u) +#define DMAC_CHSTAT_14S_END (0x00000020u) +#define DMAC_CHSTAT_14S_END_SHIFT (5u) +#define DMAC_CHSTAT_14S_TC (0x00000040u) +#define DMAC_CHSTAT_14S_TC_SHIFT (6u) +#define DMAC_CHSTAT_14S_SR (0x00000080u) +#define DMAC_CHSTAT_14S_SR_SHIFT (7u) +#define DMAC_CHSTAT_14S_DL (0x00000100u) +#define DMAC_CHSTAT_14S_DL_SHIFT (8u) +#define DMAC_CHSTAT_14S_DW (0x00000200u) +#define DMAC_CHSTAT_14S_DW_SHIFT (9u) +#define DMAC_CHSTAT_14S_DER (0x00000400u) +#define DMAC_CHSTAT_14S_DER_SHIFT (10u) +#define DMAC_CHSTAT_14S_MODE (0x00000800u) +#define DMAC_CHSTAT_14S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_14S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_14S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_14S_SETEN (0x00000001u) +#define DMAC_CHCTRL_14S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_14S_CLREN (0x00000002u) +#define DMAC_CHCTRL_14S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_14S_STG (0x00000004u) +#define DMAC_CHCTRL_14S_STG_SHIFT (2u) +#define DMAC_CHCTRL_14S_SWRST (0x00000008u) +#define DMAC_CHCTRL_14S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_14S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_14S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_14S_CLREND (0x00000020u) +#define DMAC_CHCTRL_14S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_14S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_14S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_14S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_14S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_14S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_14S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_14S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_14S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_14S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_14S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_14S_SEL (0x00000007u) +#define DMAC_CHCFG_14S_SEL_SHIFT (0u) +#define DMAC_CHCFG_14S_REQD (0x00000008u) +#define DMAC_CHCFG_14S_REQD_SHIFT (3u) +#define DMAC_CHCFG_14S_LOEN (0x00000010u) +#define DMAC_CHCFG_14S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_14S_HIEN (0x00000020u) +#define DMAC_CHCFG_14S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_14S_LVL (0x00000040u) +#define DMAC_CHCFG_14S_LVL_SHIFT (6u) +#define DMAC_CHCFG_14S_AM (0x00000700u) +#define DMAC_CHCFG_14S_AM_SHIFT (8u) +#define DMAC_CHCFG_14S_SDS (0x0000F000u) +#define DMAC_CHCFG_14S_SDS_SHIFT (12u) +#define DMAC_CHCFG_14S_DDS (0x000F0000u) +#define DMAC_CHCFG_14S_DDS_SHIFT (16u) +#define DMAC_CHCFG_14S_SAD (0x00100000u) +#define DMAC_CHCFG_14S_SAD_SHIFT (20u) +#define DMAC_CHCFG_14S_DAD (0x00200000u) +#define DMAC_CHCFG_14S_DAD_SHIFT (21u) +#define DMAC_CHCFG_14S_TM (0x00400000u) +#define DMAC_CHCFG_14S_TM_SHIFT (22u) +#define DMAC_CHCFG_14S_DEM (0x01000000u) +#define DMAC_CHCFG_14S_DEM_SHIFT (24u) +#define DMAC_CHCFG_14S_SBE (0x08000000u) +#define DMAC_CHCFG_14S_SBE_SHIFT (27u) +#define DMAC_CHCFG_14S_RSEL (0x10000000u) +#define DMAC_CHCFG_14S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_14S_RSW (0x20000000u) +#define DMAC_CHCFG_14S_RSW_SHIFT (29u) +#define DMAC_CHCFG_14S_REN (0x40000000u) +#define DMAC_CHCFG_14S_REN_SHIFT (30u) +#define DMAC_CHCFG_14S_DMS (0x80000000u) +#define DMAC_CHCFG_14S_DMS_SHIFT (31u) +#define DMAC_CHITVL_14S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_14S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_14S_SPR (0x00000007u) +#define DMAC_CHEXT_14S_SPR_SHIFT (0u) +#define DMAC_CHEXT_14S_SCA (0x000000F0u) +#define DMAC_CHEXT_14S_SCA_SHIFT (4u) +#define DMAC_CHEXT_14S_DPR (0x00000700u) +#define DMAC_CHEXT_14S_DPR_SHIFT (8u) +#define DMAC_CHEXT_14S_DCA (0x0000F000u) +#define DMAC_CHEXT_14S_DCA_SHIFT (12u) +#define DMAC_NXLA_14S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_14S_NXLA_SHIFT (0u) +#define DMAC_CRLA_14S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_14S_CRLA_SHIFT (0u) +#define DMAC_N0SA_15S_SA (0xFFFFFFFFu) +#define DMAC_N0SA_15S_SA_SHIFT (0u) +#define DMAC_N0DA_15S_DA (0xFFFFFFFFu) +#define DMAC_N0DA_15S_DA_SHIFT (0u) +#define DMAC_N0TB_15S_TB (0xFFFFFFFFu) +#define DMAC_N0TB_15S_TB_SHIFT (0u) +#define DMAC_N1SA_15S_SA (0xFFFFFFFFu) +#define DMAC_N1SA_15S_SA_SHIFT (0u) +#define DMAC_N1DA_15S_DA (0xFFFFFFFFu) +#define DMAC_N1DA_15S_DA_SHIFT (0u) +#define DMAC_N1TB_15S_TB (0xFFFFFFFFu) +#define DMAC_N1TB_15S_TB_SHIFT (0u) +#define DMAC_CRSA_15S_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_15S_CRSA_SHIFT (0u) +#define DMAC_CRDA_15S_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_15S_CRDA_SHIFT (0u) +#define DMAC_CRTB_15S_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_15S_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_15S_EN (0x00000001u) +#define DMAC_CHSTAT_15S_EN_SHIFT (0u) +#define DMAC_CHSTAT_15S_RQST (0x00000002u) +#define DMAC_CHSTAT_15S_RQST_SHIFT (1u) +#define DMAC_CHSTAT_15S_TACT (0x00000004u) +#define DMAC_CHSTAT_15S_TACT_SHIFT (2u) +#define DMAC_CHSTAT_15S_SUS (0x00000008u) +#define DMAC_CHSTAT_15S_SUS_SHIFT (3u) +#define DMAC_CHSTAT_15S_ER (0x00000010u) +#define DMAC_CHSTAT_15S_ER_SHIFT (4u) +#define DMAC_CHSTAT_15S_END (0x00000020u) +#define DMAC_CHSTAT_15S_END_SHIFT (5u) +#define DMAC_CHSTAT_15S_TC (0x00000040u) +#define DMAC_CHSTAT_15S_TC_SHIFT (6u) +#define DMAC_CHSTAT_15S_SR (0x00000080u) +#define DMAC_CHSTAT_15S_SR_SHIFT (7u) +#define DMAC_CHSTAT_15S_DL (0x00000100u) +#define DMAC_CHSTAT_15S_DL_SHIFT (8u) +#define DMAC_CHSTAT_15S_DW (0x00000200u) +#define DMAC_CHSTAT_15S_DW_SHIFT (9u) +#define DMAC_CHSTAT_15S_DER (0x00000400u) +#define DMAC_CHSTAT_15S_DER_SHIFT (10u) +#define DMAC_CHSTAT_15S_MODE (0x00000800u) +#define DMAC_CHSTAT_15S_MODE_SHIFT (11u) +#define DMAC_CHSTAT_15S_INTMSK (0x00010000u) +#define DMAC_CHSTAT_15S_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_15S_SETEN (0x00000001u) +#define DMAC_CHCTRL_15S_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_15S_CLREN (0x00000002u) +#define DMAC_CHCTRL_15S_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_15S_STG (0x00000004u) +#define DMAC_CHCTRL_15S_STG_SHIFT (2u) +#define DMAC_CHCTRL_15S_SWRST (0x00000008u) +#define DMAC_CHCTRL_15S_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_15S_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_15S_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_15S_CLREND (0x00000020u) +#define DMAC_CHCTRL_15S_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_15S_CLRTC (0x00000040u) +#define DMAC_CHCTRL_15S_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_15S_SETSUS (0x00000100u) +#define DMAC_CHCTRL_15S_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_15S_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_15S_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_15S_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_15S_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_15S_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_15S_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_15S_SEL (0x00000007u) +#define DMAC_CHCFG_15S_SEL_SHIFT (0u) +#define DMAC_CHCFG_15S_REQD (0x00000008u) +#define DMAC_CHCFG_15S_REQD_SHIFT (3u) +#define DMAC_CHCFG_15S_LOEN (0x00000010u) +#define DMAC_CHCFG_15S_LOEN_SHIFT (4u) +#define DMAC_CHCFG_15S_HIEN (0x00000020u) +#define DMAC_CHCFG_15S_HIEN_SHIFT (5u) +#define DMAC_CHCFG_15S_LVL (0x00000040u) +#define DMAC_CHCFG_15S_LVL_SHIFT (6u) +#define DMAC_CHCFG_15S_AM (0x00000700u) +#define DMAC_CHCFG_15S_AM_SHIFT (8u) +#define DMAC_CHCFG_15S_SDS (0x0000F000u) +#define DMAC_CHCFG_15S_SDS_SHIFT (12u) +#define DMAC_CHCFG_15S_DDS (0x000F0000u) +#define DMAC_CHCFG_15S_DDS_SHIFT (16u) +#define DMAC_CHCFG_15S_SAD (0x00100000u) +#define DMAC_CHCFG_15S_SAD_SHIFT (20u) +#define DMAC_CHCFG_15S_DAD (0x00200000u) +#define DMAC_CHCFG_15S_DAD_SHIFT (21u) +#define DMAC_CHCFG_15S_TM (0x00400000u) +#define DMAC_CHCFG_15S_TM_SHIFT (22u) +#define DMAC_CHCFG_15S_DEM (0x01000000u) +#define DMAC_CHCFG_15S_DEM_SHIFT (24u) +#define DMAC_CHCFG_15S_SBE (0x08000000u) +#define DMAC_CHCFG_15S_SBE_SHIFT (27u) +#define DMAC_CHCFG_15S_RSEL (0x10000000u) +#define DMAC_CHCFG_15S_RSEL_SHIFT (28u) +#define DMAC_CHCFG_15S_RSW (0x20000000u) +#define DMAC_CHCFG_15S_RSW_SHIFT (29u) +#define DMAC_CHCFG_15S_REN (0x40000000u) +#define DMAC_CHCFG_15S_REN_SHIFT (30u) +#define DMAC_CHCFG_15S_DMS (0x80000000u) +#define DMAC_CHCFG_15S_DMS_SHIFT (31u) +#define DMAC_CHITVL_15S_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_15S_ITVL_SHIFT (0u) +#define DMAC_CHEXT_15S_SPR (0x00000007u) +#define DMAC_CHEXT_15S_SPR_SHIFT (0u) +#define DMAC_CHEXT_15S_SCA (0x000000F0u) +#define DMAC_CHEXT_15S_SCA_SHIFT (4u) +#define DMAC_CHEXT_15S_DPR (0x00000700u) +#define DMAC_CHEXT_15S_DPR_SHIFT (8u) +#define DMAC_CHEXT_15S_DCA (0x0000F000u) +#define DMAC_CHEXT_15S_DCA_SHIFT (12u) +#define DMAC_NXLA_15S_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_15S_NXLA_SHIFT (0u) +#define DMAC_CRLA_15S_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_15S_CRLA_SHIFT (0u) +#define DMAC_DCTRL_8_15S_PR (0x00000001u) +#define DMAC_DCTRL_8_15S_PR_SHIFT (0u) +#define DMAC_DCTRL_8_15S_LVINT (0x00000002u) +#define DMAC_DCTRL_8_15S_LVINT_SHIFT (1u) +#define DMAC_DCTRL_8_15S_LDPR (0x00070000u) +#define DMAC_DCTRL_8_15S_LDPR_SHIFT (16u) +#define DMAC_DCTRL_8_15S_LDCA (0x00F00000u) +#define DMAC_DCTRL_8_15S_LDCA_SHIFT (20u) +#define DMAC_DCTRL_8_15S_LWPR (0x07000000u) +#define DMAC_DCTRL_8_15S_LWPR_SHIFT (24u) +#define DMAC_DCTRL_8_15S_LWCA (0xF0000000u) +#define DMAC_DCTRL_8_15S_LWCA_SHIFT (28u) +#define DMAC_DSTAT_EN_8_15S_EN8 (0x00000001u) +#define DMAC_DSTAT_EN_8_15S_EN8_SHIFT (0u) +#define DMAC_DSTAT_EN_8_15S_EN9 (0x00000002u) +#define DMAC_DSTAT_EN_8_15S_EN9_SHIFT (1u) +#define DMAC_DSTAT_EN_8_15S_EN10 (0x00000004u) +#define DMAC_DSTAT_EN_8_15S_EN10_SHIFT (2u) +#define DMAC_DSTAT_EN_8_15S_EN11 (0x00000008u) +#define DMAC_DSTAT_EN_8_15S_EN11_SHIFT (3u) +#define DMAC_DSTAT_EN_8_15S_EN12 (0x00000010u) +#define DMAC_DSTAT_EN_8_15S_EN12_SHIFT (4u) +#define DMAC_DSTAT_EN_8_15S_EN13 (0x00000020u) +#define DMAC_DSTAT_EN_8_15S_EN13_SHIFT (5u) +#define DMAC_DSTAT_EN_8_15S_EN14 (0x00000040u) +#define DMAC_DSTAT_EN_8_15S_EN14_SHIFT (6u) +#define DMAC_DSTAT_EN_8_15S_EN15 (0x00000080u) +#define DMAC_DSTAT_EN_8_15S_EN15_SHIFT (7u) +#define DMAC_DSTAT_ER_8_15S_ER8 (0x00000001u) +#define DMAC_DSTAT_ER_8_15S_ER8_SHIFT (0u) +#define DMAC_DSTAT_ER_8_15S_ER9 (0x00000002u) +#define DMAC_DSTAT_ER_8_15S_ER9_SHIFT (1u) +#define DMAC_DSTAT_ER_8_15S_ER10 (0x00000004u) +#define DMAC_DSTAT_ER_8_15S_ER10_SHIFT (2u) +#define DMAC_DSTAT_ER_8_15S_ER11 (0x00000008u) +#define DMAC_DSTAT_ER_8_15S_ER11_SHIFT (3u) +#define DMAC_DSTAT_ER_8_15S_ER12 (0x00000010u) +#define DMAC_DSTAT_ER_8_15S_ER12_SHIFT (4u) +#define DMAC_DSTAT_ER_8_15S_ER13 (0x00000020u) +#define DMAC_DSTAT_ER_8_15S_ER13_SHIFT (5u) +#define DMAC_DSTAT_ER_8_15S_ER14 (0x00000040u) +#define DMAC_DSTAT_ER_8_15S_ER14_SHIFT (6u) +#define DMAC_DSTAT_ER_8_15S_ER15 (0x00000080u) +#define DMAC_DSTAT_ER_8_15S_ER15_SHIFT (7u) +#define DMAC_DSTAT_END_8_15S_END8 (0x00000001u) +#define DMAC_DSTAT_END_8_15S_END8_SHIFT (0u) +#define DMAC_DSTAT_END_8_15S_END9 (0x00000002u) +#define DMAC_DSTAT_END_8_15S_END9_SHIFT (1u) +#define DMAC_DSTAT_END_8_15S_END10 (0x00000004u) +#define DMAC_DSTAT_END_8_15S_END10_SHIFT (2u) +#define DMAC_DSTAT_END_8_15S_END11 (0x00000008u) +#define DMAC_DSTAT_END_8_15S_END11_SHIFT (3u) +#define DMAC_DSTAT_END_8_15S_END12 (0x00000010u) +#define DMAC_DSTAT_END_8_15S_END12_SHIFT (4u) +#define DMAC_DSTAT_END_8_15S_END13 (0x00000020u) +#define DMAC_DSTAT_END_8_15S_END13_SHIFT (5u) +#define DMAC_DSTAT_END_8_15S_END14 (0x00000040u) +#define DMAC_DSTAT_END_8_15S_END14_SHIFT (6u) +#define DMAC_DSTAT_END_8_15S_END15 (0x00000080u) +#define DMAC_DSTAT_END_8_15S_END15_SHIFT (7u) +#define DMAC_DSTAT_TC_8_15S_TC8 (0x00000001u) +#define DMAC_DSTAT_TC_8_15S_TC8_SHIFT (0u) +#define DMAC_DSTAT_TC_8_15S_TC9 (0x00000002u) +#define DMAC_DSTAT_TC_8_15S_TC9_SHIFT (1u) +#define DMAC_DSTAT_TC_8_15S_TC10 (0x00000004u) +#define DMAC_DSTAT_TC_8_15S_TC10_SHIFT (2u) +#define DMAC_DSTAT_TC_8_15S_TC11 (0x00000008u) +#define DMAC_DSTAT_TC_8_15S_TC11_SHIFT (3u) +#define DMAC_DSTAT_TC_8_15S_TC12 (0x00000010u) +#define DMAC_DSTAT_TC_8_15S_TC12_SHIFT (4u) +#define DMAC_DSTAT_TC_8_15S_TC13 (0x00000020u) +#define DMAC_DSTAT_TC_8_15S_TC13_SHIFT (5u) +#define DMAC_DSTAT_TC_8_15S_TC14 (0x00000040u) +#define DMAC_DSTAT_TC_8_15S_TC14_SHIFT (6u) +#define DMAC_DSTAT_TC_8_15S_TC15 (0x00000080u) +#define DMAC_DSTAT_TC_8_15S_TC15_SHIFT (7u) +#define DMAC_DSTAT_SUS_8_15S_SUS8 (0x00000001u) +#define DMAC_DSTAT_SUS_8_15S_SUS8_SHIFT (0u) +#define DMAC_DSTAT_SUS_8_15S_SUS9 (0x00000002u) +#define DMAC_DSTAT_SUS_8_15S_SUS9_SHIFT (1u) +#define DMAC_DSTAT_SUS_8_15S_SUS10 (0x00000004u) +#define DMAC_DSTAT_SUS_8_15S_SUS10_SHIFT (2u) +#define DMAC_DSTAT_SUS_8_15S_SUS11 (0x00000008u) +#define DMAC_DSTAT_SUS_8_15S_SUS11_SHIFT (3u) +#define DMAC_DSTAT_SUS_8_15S_SUS12 (0x00000010u) +#define DMAC_DSTAT_SUS_8_15S_SUS12_SHIFT (4u) +#define DMAC_DSTAT_SUS_8_15S_SUS13 (0x00000020u) +#define DMAC_DSTAT_SUS_8_15S_SUS13_SHIFT (5u) +#define DMAC_DSTAT_SUS_8_15S_SUS14 (0x00000040u) +#define DMAC_DSTAT_SUS_8_15S_SUS14_SHIFT (6u) +#define DMAC_DSTAT_SUS_8_15S_SUS15 (0x00000080u) +#define DMAC_DSTAT_SUS_8_15S_SUS15_SHIFT (7u) +#define DMAC_DMARS0S_CH0_RID (0x00000003u) +#define DMAC_DMARS0S_CH0_RID_SHIFT (0u) +#define DMAC_DMARS0S_CH0_MID (0x000003FCu) +#define DMAC_DMARS0S_CH0_MID_SHIFT (2u) +#define DMAC_DMARS0S_CH1_RID (0x00030000u) +#define DMAC_DMARS0S_CH1_RID_SHIFT (16u) +#define DMAC_DMARS0S_CH1_MID (0x03FC0000u) +#define DMAC_DMARS0S_CH1_MID_SHIFT (18u) +#define DMAC_DMARS1S_CH2_RID (0x00000003u) +#define DMAC_DMARS1S_CH2_RID_SHIFT (0u) +#define DMAC_DMARS1S_CH2_MID (0x000003FCu) +#define DMAC_DMARS1S_CH2_MID_SHIFT (2u) +#define DMAC_DMARS1S_CH3_RID (0x00030000u) +#define DMAC_DMARS1S_CH3_RID_SHIFT (16u) +#define DMAC_DMARS1S_CH3_MID (0x03FC0000u) +#define DMAC_DMARS1S_CH3_MID_SHIFT (18u) +#define DMAC_DMARS2S_CH4_RID (0x00000003u) +#define DMAC_DMARS2S_CH4_RID_SHIFT (0u) +#define DMAC_DMARS2S_CH4_MID (0x000003FCu) +#define DMAC_DMARS2S_CH4_MID_SHIFT (2u) +#define DMAC_DMARS2S_CH5_RID (0x00030000u) +#define DMAC_DMARS2S_CH5_RID_SHIFT (16u) +#define DMAC_DMARS2S_CH5_MID (0x03FC0000u) +#define DMAC_DMARS2S_CH5_MID_SHIFT (18u) +#define DMAC_DMARS3S_CH6_RID (0x00000003u) +#define DMAC_DMARS3S_CH6_RID_SHIFT (0u) +#define DMAC_DMARS3S_CH6_MID (0x000003FCu) +#define DMAC_DMARS3S_CH6_MID_SHIFT (2u) +#define DMAC_DMARS3S_CH7_RID (0x00030000u) +#define DMAC_DMARS3S_CH7_RID_SHIFT (16u) +#define DMAC_DMARS3S_CH7_MID (0x03FC0000u) +#define DMAC_DMARS3S_CH7_MID_SHIFT (18u) +#define DMAC_DMARS4S_CH8_RID (0x00000003u) +#define DMAC_DMARS4S_CH8_RID_SHIFT (0u) +#define DMAC_DMARS4S_CH8_MID (0x000003FCu) +#define DMAC_DMARS4S_CH8_MID_SHIFT (2u) +#define DMAC_DMARS4S_CH9_RID (0x00030000u) +#define DMAC_DMARS4S_CH9_RID_SHIFT (16u) +#define DMAC_DMARS4S_CH9_MID (0x03FC0000u) +#define DMAC_DMARS4S_CH9_MID_SHIFT (18u) +#define DMAC_DMARS5S_CH10_RID (0x00000003u) +#define DMAC_DMARS5S_CH10_RID_SHIFT (0u) +#define DMAC_DMARS5S_CH10_MID (0x000003FCu) +#define DMAC_DMARS5S_CH10_MID_SHIFT (2u) +#define DMAC_DMARS5S_CH11_RID (0x00030000u) +#define DMAC_DMARS5S_CH11_RID_SHIFT (16u) +#define DMAC_DMARS5S_CH11_MID (0x03FC0000u) +#define DMAC_DMARS5S_CH11_MID_SHIFT (18u) +#define DMAC_DMARS6S_CH12_RID (0x00000003u) +#define DMAC_DMARS6S_CH12_RID_SHIFT (0u) +#define DMAC_DMARS6S_CH12_MID (0x000003FCu) +#define DMAC_DMARS6S_CH12_MID_SHIFT (2u) +#define DMAC_DMARS6S_CH13_RID (0x00030000u) +#define DMAC_DMARS6S_CH13_RID_SHIFT (16u) +#define DMAC_DMARS6S_CH13_MID (0x03FC0000u) +#define DMAC_DMARS6S_CH13_MID_SHIFT (18u) +#define DMAC_DMARS7S_CH14_RID (0x00000003u) +#define DMAC_DMARS7S_CH14_RID_SHIFT (0u) +#define DMAC_DMARS7S_CH14_MID (0x000003FCu) +#define DMAC_DMARS7S_CH14_MID_SHIFT (2u) +#define DMAC_DMARS7S_CH15_RID (0x00030000u) +#define DMAC_DMARS7S_CH15_RID_SHIFT (16u) +#define DMAC_DMARS7S_CH15_MID (0x03FC0000u) +#define DMAC_DMARS7S_CH15_MID_SHIFT (18u) +#define DMAC_N0SA_0_SA (0xFFFFFFFFu) +#define DMAC_N0SA_0_SA_SHIFT (0u) +#define DMAC_N0DA_0_DA (0xFFFFFFFFu) +#define DMAC_N0DA_0_DA_SHIFT (0u) +#define DMAC_N0TB_0_TB (0xFFFFFFFFu) +#define DMAC_N0TB_0_TB_SHIFT (0u) +#define DMAC_N1SA_0_SA (0xFFFFFFFFu) +#define DMAC_N1SA_0_SA_SHIFT (0u) +#define DMAC_N1DA_0_DA (0xFFFFFFFFu) +#define DMAC_N1DA_0_DA_SHIFT (0u) +#define DMAC_N1TB_0_TB (0xFFFFFFFFu) +#define DMAC_N1TB_0_TB_SHIFT (0u) +#define DMAC_CRSA_0_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_0_CRSA_SHIFT (0u) +#define DMAC_CRDA_0_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_0_CRDA_SHIFT (0u) +#define DMAC_CRTB_0_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_0_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_0_EN (0x00000001u) +#define DMAC_CHSTAT_0_EN_SHIFT (0u) +#define DMAC_CHSTAT_0_RQST (0x00000002u) +#define DMAC_CHSTAT_0_RQST_SHIFT (1u) +#define DMAC_CHSTAT_0_TACT (0x00000004u) +#define DMAC_CHSTAT_0_TACT_SHIFT (2u) +#define DMAC_CHSTAT_0_SUS (0x00000008u) +#define DMAC_CHSTAT_0_SUS_SHIFT (3u) +#define DMAC_CHSTAT_0_ER (0x00000010u) +#define DMAC_CHSTAT_0_ER_SHIFT (4u) +#define DMAC_CHSTAT_0_END (0x00000020u) +#define DMAC_CHSTAT_0_END_SHIFT (5u) +#define DMAC_CHSTAT_0_TC (0x00000040u) +#define DMAC_CHSTAT_0_TC_SHIFT (6u) +#define DMAC_CHSTAT_0_SR (0x00000080u) +#define DMAC_CHSTAT_0_SR_SHIFT (7u) +#define DMAC_CHSTAT_0_DL (0x00000100u) +#define DMAC_CHSTAT_0_DL_SHIFT (8u) +#define DMAC_CHSTAT_0_DW (0x00000200u) +#define DMAC_CHSTAT_0_DW_SHIFT (9u) +#define DMAC_CHSTAT_0_DER (0x00000400u) +#define DMAC_CHSTAT_0_DER_SHIFT (10u) +#define DMAC_CHSTAT_0_MODE (0x00000800u) +#define DMAC_CHSTAT_0_MODE_SHIFT (11u) +#define DMAC_CHSTAT_0_INTMSK (0x00010000u) +#define DMAC_CHSTAT_0_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_0_SETEN (0x00000001u) +#define DMAC_CHCTRL_0_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_0_CLREN (0x00000002u) +#define DMAC_CHCTRL_0_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_0_STG (0x00000004u) +#define DMAC_CHCTRL_0_STG_SHIFT (2u) +#define DMAC_CHCTRL_0_SWRST (0x00000008u) +#define DMAC_CHCTRL_0_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_0_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_0_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_0_CLREND (0x00000020u) +#define DMAC_CHCTRL_0_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_0_CLRTC (0x00000040u) +#define DMAC_CHCTRL_0_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_0_SETSUS (0x00000100u) +#define DMAC_CHCTRL_0_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_0_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_0_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_0_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_0_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_0_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_0_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_0_SEL (0x00000007u) +#define DMAC_CHCFG_0_SEL_SHIFT (0u) +#define DMAC_CHCFG_0_REQD (0x00000008u) +#define DMAC_CHCFG_0_REQD_SHIFT (3u) +#define DMAC_CHCFG_0_LOEN (0x00000010u) +#define DMAC_CHCFG_0_LOEN_SHIFT (4u) +#define DMAC_CHCFG_0_HIEN (0x00000020u) +#define DMAC_CHCFG_0_HIEN_SHIFT (5u) +#define DMAC_CHCFG_0_LVL (0x00000040u) +#define DMAC_CHCFG_0_LVL_SHIFT (6u) +#define DMAC_CHCFG_0_AM (0x00000700u) +#define DMAC_CHCFG_0_AM_SHIFT (8u) +#define DMAC_CHCFG_0_SDS (0x0000F000u) +#define DMAC_CHCFG_0_SDS_SHIFT (12u) +#define DMAC_CHCFG_0_DDS (0x000F0000u) +#define DMAC_CHCFG_0_DDS_SHIFT (16u) +#define DMAC_CHCFG_0_SAD (0x00100000u) +#define DMAC_CHCFG_0_SAD_SHIFT (20u) +#define DMAC_CHCFG_0_DAD (0x00200000u) +#define DMAC_CHCFG_0_DAD_SHIFT (21u) +#define DMAC_CHCFG_0_TM (0x00400000u) +#define DMAC_CHCFG_0_TM_SHIFT (22u) +#define DMAC_CHCFG_0_DEM (0x01000000u) +#define DMAC_CHCFG_0_DEM_SHIFT (24u) +#define DMAC_CHCFG_0_SBE (0x08000000u) +#define DMAC_CHCFG_0_SBE_SHIFT (27u) +#define DMAC_CHCFG_0_RSEL (0x10000000u) +#define DMAC_CHCFG_0_RSEL_SHIFT (28u) +#define DMAC_CHCFG_0_RSW (0x20000000u) +#define DMAC_CHCFG_0_RSW_SHIFT (29u) +#define DMAC_CHCFG_0_REN (0x40000000u) +#define DMAC_CHCFG_0_REN_SHIFT (30u) +#define DMAC_CHCFG_0_DMS (0x80000000u) +#define DMAC_CHCFG_0_DMS_SHIFT (31u) +#define DMAC_CHITVL_0_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_0_ITVL_SHIFT (0u) +#define DMAC_CHEXT_0_SPR (0x00000007u) +#define DMAC_CHEXT_0_SPR_SHIFT (0u) +#define DMAC_CHEXT_0_SCA (0x000000F0u) +#define DMAC_CHEXT_0_SCA_SHIFT (4u) +#define DMAC_CHEXT_0_DPR (0x00000700u) +#define DMAC_CHEXT_0_DPR_SHIFT (8u) +#define DMAC_CHEXT_0_DCA (0x0000F000u) +#define DMAC_CHEXT_0_DCA_SHIFT (12u) +#define DMAC_NXLA_0_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_0_NXLA_SHIFT (0u) +#define DMAC_CRLA_0_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_0_CRLA_SHIFT (0u) +#define DMAC_N0SA_1_SA (0xFFFFFFFFu) +#define DMAC_N0SA_1_SA_SHIFT (0u) +#define DMAC_N0DA_1_DA (0xFFFFFFFFu) +#define DMAC_N0DA_1_DA_SHIFT (0u) +#define DMAC_N0TB_1_TB (0xFFFFFFFFu) +#define DMAC_N0TB_1_TB_SHIFT (0u) +#define DMAC_N1SA_1_SA (0xFFFFFFFFu) +#define DMAC_N1SA_1_SA_SHIFT (0u) +#define DMAC_N1DA_1_DA (0xFFFFFFFFu) +#define DMAC_N1DA_1_DA_SHIFT (0u) +#define DMAC_N1TB_1_TB (0xFFFFFFFFu) +#define DMAC_N1TB_1_TB_SHIFT (0u) +#define DMAC_CRSA_1_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_1_CRSA_SHIFT (0u) +#define DMAC_CRDA_1_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_1_CRDA_SHIFT (0u) +#define DMAC_CRTB_1_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_1_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_1_EN (0x00000001u) +#define DMAC_CHSTAT_1_EN_SHIFT (0u) +#define DMAC_CHSTAT_1_RQST (0x00000002u) +#define DMAC_CHSTAT_1_RQST_SHIFT (1u) +#define DMAC_CHSTAT_1_TACT (0x00000004u) +#define DMAC_CHSTAT_1_TACT_SHIFT (2u) +#define DMAC_CHSTAT_1_SUS (0x00000008u) +#define DMAC_CHSTAT_1_SUS_SHIFT (3u) +#define DMAC_CHSTAT_1_ER (0x00000010u) +#define DMAC_CHSTAT_1_ER_SHIFT (4u) +#define DMAC_CHSTAT_1_END (0x00000020u) +#define DMAC_CHSTAT_1_END_SHIFT (5u) +#define DMAC_CHSTAT_1_TC (0x00000040u) +#define DMAC_CHSTAT_1_TC_SHIFT (6u) +#define DMAC_CHSTAT_1_SR (0x00000080u) +#define DMAC_CHSTAT_1_SR_SHIFT (7u) +#define DMAC_CHSTAT_1_DL (0x00000100u) +#define DMAC_CHSTAT_1_DL_SHIFT (8u) +#define DMAC_CHSTAT_1_DW (0x00000200u) +#define DMAC_CHSTAT_1_DW_SHIFT (9u) +#define DMAC_CHSTAT_1_DER (0x00000400u) +#define DMAC_CHSTAT_1_DER_SHIFT (10u) +#define DMAC_CHSTAT_1_MODE (0x00000800u) +#define DMAC_CHSTAT_1_MODE_SHIFT (11u) +#define DMAC_CHSTAT_1_INTMSK (0x00010000u) +#define DMAC_CHSTAT_1_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_1_SETEN (0x00000001u) +#define DMAC_CHCTRL_1_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_1_CLREN (0x00000002u) +#define DMAC_CHCTRL_1_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_1_STG (0x00000004u) +#define DMAC_CHCTRL_1_STG_SHIFT (2u) +#define DMAC_CHCTRL_1_SWRST (0x00000008u) +#define DMAC_CHCTRL_1_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_1_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_1_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_1_CLREND (0x00000020u) +#define DMAC_CHCTRL_1_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_1_CLRTC (0x00000040u) +#define DMAC_CHCTRL_1_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_1_SETSUS (0x00000100u) +#define DMAC_CHCTRL_1_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_1_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_1_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_1_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_1_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_1_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_1_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_1_SEL (0x00000007u) +#define DMAC_CHCFG_1_SEL_SHIFT (0u) +#define DMAC_CHCFG_1_REQD (0x00000008u) +#define DMAC_CHCFG_1_REQD_SHIFT (3u) +#define DMAC_CHCFG_1_LOEN (0x00000010u) +#define DMAC_CHCFG_1_LOEN_SHIFT (4u) +#define DMAC_CHCFG_1_HIEN (0x00000020u) +#define DMAC_CHCFG_1_HIEN_SHIFT (5u) +#define DMAC_CHCFG_1_LVL (0x00000040u) +#define DMAC_CHCFG_1_LVL_SHIFT (6u) +#define DMAC_CHCFG_1_AM (0x00000700u) +#define DMAC_CHCFG_1_AM_SHIFT (8u) +#define DMAC_CHCFG_1_SDS (0x0000F000u) +#define DMAC_CHCFG_1_SDS_SHIFT (12u) +#define DMAC_CHCFG_1_DDS (0x000F0000u) +#define DMAC_CHCFG_1_DDS_SHIFT (16u) +#define DMAC_CHCFG_1_SAD (0x00100000u) +#define DMAC_CHCFG_1_SAD_SHIFT (20u) +#define DMAC_CHCFG_1_DAD (0x00200000u) +#define DMAC_CHCFG_1_DAD_SHIFT (21u) +#define DMAC_CHCFG_1_TM (0x00400000u) +#define DMAC_CHCFG_1_TM_SHIFT (22u) +#define DMAC_CHCFG_1_DEM (0x01000000u) +#define DMAC_CHCFG_1_DEM_SHIFT (24u) +#define DMAC_CHCFG_1_SBE (0x08000000u) +#define DMAC_CHCFG_1_SBE_SHIFT (27u) +#define DMAC_CHCFG_1_RSEL (0x10000000u) +#define DMAC_CHCFG_1_RSEL_SHIFT (28u) +#define DMAC_CHCFG_1_RSW (0x20000000u) +#define DMAC_CHCFG_1_RSW_SHIFT (29u) +#define DMAC_CHCFG_1_REN (0x40000000u) +#define DMAC_CHCFG_1_REN_SHIFT (30u) +#define DMAC_CHCFG_1_DMS (0x80000000u) +#define DMAC_CHCFG_1_DMS_SHIFT (31u) +#define DMAC_CHITVL_1_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_1_ITVL_SHIFT (0u) +#define DMAC_CHEXT_1_SPR (0x00000007u) +#define DMAC_CHEXT_1_SPR_SHIFT (0u) +#define DMAC_CHEXT_1_SCA (0x000000F0u) +#define DMAC_CHEXT_1_SCA_SHIFT (4u) +#define DMAC_CHEXT_1_DPR (0x00000700u) +#define DMAC_CHEXT_1_DPR_SHIFT (8u) +#define DMAC_CHEXT_1_DCA (0x0000F000u) +#define DMAC_CHEXT_1_DCA_SHIFT (12u) +#define DMAC_NXLA_1_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_1_NXLA_SHIFT (0u) +#define DMAC_CRLA_1_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_1_CRLA_SHIFT (0u) +#define DMAC_N0SA_2_SA (0xFFFFFFFFu) +#define DMAC_N0SA_2_SA_SHIFT (0u) +#define DMAC_N0DA_2_DA (0xFFFFFFFFu) +#define DMAC_N0DA_2_DA_SHIFT (0u) +#define DMAC_N0TB_2_TB (0xFFFFFFFFu) +#define DMAC_N0TB_2_TB_SHIFT (0u) +#define DMAC_N1SA_2_SA (0xFFFFFFFFu) +#define DMAC_N1SA_2_SA_SHIFT (0u) +#define DMAC_N1DA_2_DA (0xFFFFFFFFu) +#define DMAC_N1DA_2_DA_SHIFT (0u) +#define DMAC_N1TB_2_TB (0xFFFFFFFFu) +#define DMAC_N1TB_2_TB_SHIFT (0u) +#define DMAC_CRSA_2_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_2_CRSA_SHIFT (0u) +#define DMAC_CRDA_2_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_2_CRDA_SHIFT (0u) +#define DMAC_CRTB_2_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_2_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_2_EN (0x00000001u) +#define DMAC_CHSTAT_2_EN_SHIFT (0u) +#define DMAC_CHSTAT_2_RQST (0x00000002u) +#define DMAC_CHSTAT_2_RQST_SHIFT (1u) +#define DMAC_CHSTAT_2_TACT (0x00000004u) +#define DMAC_CHSTAT_2_TACT_SHIFT (2u) +#define DMAC_CHSTAT_2_SUS (0x00000008u) +#define DMAC_CHSTAT_2_SUS_SHIFT (3u) +#define DMAC_CHSTAT_2_ER (0x00000010u) +#define DMAC_CHSTAT_2_ER_SHIFT (4u) +#define DMAC_CHSTAT_2_END (0x00000020u) +#define DMAC_CHSTAT_2_END_SHIFT (5u) +#define DMAC_CHSTAT_2_TC (0x00000040u) +#define DMAC_CHSTAT_2_TC_SHIFT (6u) +#define DMAC_CHSTAT_2_SR (0x00000080u) +#define DMAC_CHSTAT_2_SR_SHIFT (7u) +#define DMAC_CHSTAT_2_DL (0x00000100u) +#define DMAC_CHSTAT_2_DL_SHIFT (8u) +#define DMAC_CHSTAT_2_DW (0x00000200u) +#define DMAC_CHSTAT_2_DW_SHIFT (9u) +#define DMAC_CHSTAT_2_DER (0x00000400u) +#define DMAC_CHSTAT_2_DER_SHIFT (10u) +#define DMAC_CHSTAT_2_MODE (0x00000800u) +#define DMAC_CHSTAT_2_MODE_SHIFT (11u) +#define DMAC_CHSTAT_2_INTMSK (0x00010000u) +#define DMAC_CHSTAT_2_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_2_SETEN (0x00000001u) +#define DMAC_CHCTRL_2_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_2_CLREN (0x00000002u) +#define DMAC_CHCTRL_2_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_2_STG (0x00000004u) +#define DMAC_CHCTRL_2_STG_SHIFT (2u) +#define DMAC_CHCTRL_2_SWRST (0x00000008u) +#define DMAC_CHCTRL_2_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_2_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_2_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_2_CLREND (0x00000020u) +#define DMAC_CHCTRL_2_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_2_CLRTC (0x00000040u) +#define DMAC_CHCTRL_2_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_2_SETSUS (0x00000100u) +#define DMAC_CHCTRL_2_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_2_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_2_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_2_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_2_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_2_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_2_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_2_SEL (0x00000007u) +#define DMAC_CHCFG_2_SEL_SHIFT (0u) +#define DMAC_CHCFG_2_REQD (0x00000008u) +#define DMAC_CHCFG_2_REQD_SHIFT (3u) +#define DMAC_CHCFG_2_LOEN (0x00000010u) +#define DMAC_CHCFG_2_LOEN_SHIFT (4u) +#define DMAC_CHCFG_2_HIEN (0x00000020u) +#define DMAC_CHCFG_2_HIEN_SHIFT (5u) +#define DMAC_CHCFG_2_LVL (0x00000040u) +#define DMAC_CHCFG_2_LVL_SHIFT (6u) +#define DMAC_CHCFG_2_AM (0x00000700u) +#define DMAC_CHCFG_2_AM_SHIFT (8u) +#define DMAC_CHCFG_2_SDS (0x0000F000u) +#define DMAC_CHCFG_2_SDS_SHIFT (12u) +#define DMAC_CHCFG_2_DDS (0x000F0000u) +#define DMAC_CHCFG_2_DDS_SHIFT (16u) +#define DMAC_CHCFG_2_SAD (0x00100000u) +#define DMAC_CHCFG_2_SAD_SHIFT (20u) +#define DMAC_CHCFG_2_DAD (0x00200000u) +#define DMAC_CHCFG_2_DAD_SHIFT (21u) +#define DMAC_CHCFG_2_TM (0x00400000u) +#define DMAC_CHCFG_2_TM_SHIFT (22u) +#define DMAC_CHCFG_2_DEM (0x01000000u) +#define DMAC_CHCFG_2_DEM_SHIFT (24u) +#define DMAC_CHCFG_2_SBE (0x08000000u) +#define DMAC_CHCFG_2_SBE_SHIFT (27u) +#define DMAC_CHCFG_2_RSEL (0x10000000u) +#define DMAC_CHCFG_2_RSEL_SHIFT (28u) +#define DMAC_CHCFG_2_RSW (0x20000000u) +#define DMAC_CHCFG_2_RSW_SHIFT (29u) +#define DMAC_CHCFG_2_REN (0x40000000u) +#define DMAC_CHCFG_2_REN_SHIFT (30u) +#define DMAC_CHCFG_2_DMS (0x80000000u) +#define DMAC_CHCFG_2_DMS_SHIFT (31u) +#define DMAC_CHITVL_2_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_2_ITVL_SHIFT (0u) +#define DMAC_CHEXT_2_SPR (0x00000007u) +#define DMAC_CHEXT_2_SPR_SHIFT (0u) +#define DMAC_CHEXT_2_SCA (0x000000F0u) +#define DMAC_CHEXT_2_SCA_SHIFT (4u) +#define DMAC_CHEXT_2_DPR (0x00000700u) +#define DMAC_CHEXT_2_DPR_SHIFT (8u) +#define DMAC_CHEXT_2_DCA (0x0000F000u) +#define DMAC_CHEXT_2_DCA_SHIFT (12u) +#define DMAC_NXLA_2_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_2_NXLA_SHIFT (0u) +#define DMAC_CRLA_2_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_2_CRLA_SHIFT (0u) +#define DMAC_N0SA_3_SA (0xFFFFFFFFu) +#define DMAC_N0SA_3_SA_SHIFT (0u) +#define DMAC_N0DA_3_DA (0xFFFFFFFFu) +#define DMAC_N0DA_3_DA_SHIFT (0u) +#define DMAC_N0TB_3_TB (0xFFFFFFFFu) +#define DMAC_N0TB_3_TB_SHIFT (0u) +#define DMAC_N1SA_3_SA (0xFFFFFFFFu) +#define DMAC_N1SA_3_SA_SHIFT (0u) +#define DMAC_N1DA_3_DA (0xFFFFFFFFu) +#define DMAC_N1DA_3_DA_SHIFT (0u) +#define DMAC_N1TB_3_TB (0xFFFFFFFFu) +#define DMAC_N1TB_3_TB_SHIFT (0u) +#define DMAC_CRSA_3_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_3_CRSA_SHIFT (0u) +#define DMAC_CRDA_3_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_3_CRDA_SHIFT (0u) +#define DMAC_CRTB_3_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_3_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_3_EN (0x00000001u) +#define DMAC_CHSTAT_3_EN_SHIFT (0u) +#define DMAC_CHSTAT_3_RQST (0x00000002u) +#define DMAC_CHSTAT_3_RQST_SHIFT (1u) +#define DMAC_CHSTAT_3_TACT (0x00000004u) +#define DMAC_CHSTAT_3_TACT_SHIFT (2u) +#define DMAC_CHSTAT_3_SUS (0x00000008u) +#define DMAC_CHSTAT_3_SUS_SHIFT (3u) +#define DMAC_CHSTAT_3_ER (0x00000010u) +#define DMAC_CHSTAT_3_ER_SHIFT (4u) +#define DMAC_CHSTAT_3_END (0x00000020u) +#define DMAC_CHSTAT_3_END_SHIFT (5u) +#define DMAC_CHSTAT_3_TC (0x00000040u) +#define DMAC_CHSTAT_3_TC_SHIFT (6u) +#define DMAC_CHSTAT_3_SR (0x00000080u) +#define DMAC_CHSTAT_3_SR_SHIFT (7u) +#define DMAC_CHSTAT_3_DL (0x00000100u) +#define DMAC_CHSTAT_3_DL_SHIFT (8u) +#define DMAC_CHSTAT_3_DW (0x00000200u) +#define DMAC_CHSTAT_3_DW_SHIFT (9u) +#define DMAC_CHSTAT_3_DER (0x00000400u) +#define DMAC_CHSTAT_3_DER_SHIFT (10u) +#define DMAC_CHSTAT_3_MODE (0x00000800u) +#define DMAC_CHSTAT_3_MODE_SHIFT (11u) +#define DMAC_CHSTAT_3_INTMSK (0x00010000u) +#define DMAC_CHSTAT_3_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_3_SETEN (0x00000001u) +#define DMAC_CHCTRL_3_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_3_CLREN (0x00000002u) +#define DMAC_CHCTRL_3_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_3_STG (0x00000004u) +#define DMAC_CHCTRL_3_STG_SHIFT (2u) +#define DMAC_CHCTRL_3_SWRST (0x00000008u) +#define DMAC_CHCTRL_3_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_3_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_3_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_3_CLREND (0x00000020u) +#define DMAC_CHCTRL_3_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_3_CLRTC (0x00000040u) +#define DMAC_CHCTRL_3_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_3_SETSUS (0x00000100u) +#define DMAC_CHCTRL_3_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_3_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_3_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_3_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_3_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_3_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_3_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_3_SEL (0x00000007u) +#define DMAC_CHCFG_3_SEL_SHIFT (0u) +#define DMAC_CHCFG_3_REQD (0x00000008u) +#define DMAC_CHCFG_3_REQD_SHIFT (3u) +#define DMAC_CHCFG_3_LOEN (0x00000010u) +#define DMAC_CHCFG_3_LOEN_SHIFT (4u) +#define DMAC_CHCFG_3_HIEN (0x00000020u) +#define DMAC_CHCFG_3_HIEN_SHIFT (5u) +#define DMAC_CHCFG_3_LVL (0x00000040u) +#define DMAC_CHCFG_3_LVL_SHIFT (6u) +#define DMAC_CHCFG_3_AM (0x00000700u) +#define DMAC_CHCFG_3_AM_SHIFT (8u) +#define DMAC_CHCFG_3_SDS (0x0000F000u) +#define DMAC_CHCFG_3_SDS_SHIFT (12u) +#define DMAC_CHCFG_3_DDS (0x000F0000u) +#define DMAC_CHCFG_3_DDS_SHIFT (16u) +#define DMAC_CHCFG_3_SAD (0x00100000u) +#define DMAC_CHCFG_3_SAD_SHIFT (20u) +#define DMAC_CHCFG_3_DAD (0x00200000u) +#define DMAC_CHCFG_3_DAD_SHIFT (21u) +#define DMAC_CHCFG_3_TM (0x00400000u) +#define DMAC_CHCFG_3_TM_SHIFT (22u) +#define DMAC_CHCFG_3_DEM (0x01000000u) +#define DMAC_CHCFG_3_DEM_SHIFT (24u) +#define DMAC_CHCFG_3_SBE (0x08000000u) +#define DMAC_CHCFG_3_SBE_SHIFT (27u) +#define DMAC_CHCFG_3_RSEL (0x10000000u) +#define DMAC_CHCFG_3_RSEL_SHIFT (28u) +#define DMAC_CHCFG_3_RSW (0x20000000u) +#define DMAC_CHCFG_3_RSW_SHIFT (29u) +#define DMAC_CHCFG_3_REN (0x40000000u) +#define DMAC_CHCFG_3_REN_SHIFT (30u) +#define DMAC_CHCFG_3_DMS (0x80000000u) +#define DMAC_CHCFG_3_DMS_SHIFT (31u) +#define DMAC_CHITVL_3_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_3_ITVL_SHIFT (0u) +#define DMAC_CHEXT_3_SPR (0x00000007u) +#define DMAC_CHEXT_3_SPR_SHIFT (0u) +#define DMAC_CHEXT_3_SCA (0x000000F0u) +#define DMAC_CHEXT_3_SCA_SHIFT (4u) +#define DMAC_CHEXT_3_DPR (0x00000700u) +#define DMAC_CHEXT_3_DPR_SHIFT (8u) +#define DMAC_CHEXT_3_DCA (0x0000F000u) +#define DMAC_CHEXT_3_DCA_SHIFT (12u) +#define DMAC_NXLA_3_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_3_NXLA_SHIFT (0u) +#define DMAC_CRLA_3_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_3_CRLA_SHIFT (0u) +#define DMAC_N0SA_4_SA (0xFFFFFFFFu) +#define DMAC_N0SA_4_SA_SHIFT (0u) +#define DMAC_N0DA_4_DA (0xFFFFFFFFu) +#define DMAC_N0DA_4_DA_SHIFT (0u) +#define DMAC_N0TB_4_TB (0xFFFFFFFFu) +#define DMAC_N0TB_4_TB_SHIFT (0u) +#define DMAC_N1SA_4_SA (0xFFFFFFFFu) +#define DMAC_N1SA_4_SA_SHIFT (0u) +#define DMAC_N1DA_4_DA (0xFFFFFFFFu) +#define DMAC_N1DA_4_DA_SHIFT (0u) +#define DMAC_N1TB_4_TB (0xFFFFFFFFu) +#define DMAC_N1TB_4_TB_SHIFT (0u) +#define DMAC_CRSA_4_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_4_CRSA_SHIFT (0u) +#define DMAC_CRDA_4_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_4_CRDA_SHIFT (0u) +#define DMAC_CRTB_4_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_4_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_4_EN (0x00000001u) +#define DMAC_CHSTAT_4_EN_SHIFT (0u) +#define DMAC_CHSTAT_4_RQST (0x00000002u) +#define DMAC_CHSTAT_4_RQST_SHIFT (1u) +#define DMAC_CHSTAT_4_TACT (0x00000004u) +#define DMAC_CHSTAT_4_TACT_SHIFT (2u) +#define DMAC_CHSTAT_4_SUS (0x00000008u) +#define DMAC_CHSTAT_4_SUS_SHIFT (3u) +#define DMAC_CHSTAT_4_ER (0x00000010u) +#define DMAC_CHSTAT_4_ER_SHIFT (4u) +#define DMAC_CHSTAT_4_END (0x00000020u) +#define DMAC_CHSTAT_4_END_SHIFT (5u) +#define DMAC_CHSTAT_4_TC (0x00000040u) +#define DMAC_CHSTAT_4_TC_SHIFT (6u) +#define DMAC_CHSTAT_4_SR (0x00000080u) +#define DMAC_CHSTAT_4_SR_SHIFT (7u) +#define DMAC_CHSTAT_4_DL (0x00000100u) +#define DMAC_CHSTAT_4_DL_SHIFT (8u) +#define DMAC_CHSTAT_4_DW (0x00000200u) +#define DMAC_CHSTAT_4_DW_SHIFT (9u) +#define DMAC_CHSTAT_4_DER (0x00000400u) +#define DMAC_CHSTAT_4_DER_SHIFT (10u) +#define DMAC_CHSTAT_4_MODE (0x00000800u) +#define DMAC_CHSTAT_4_MODE_SHIFT (11u) +#define DMAC_CHSTAT_4_INTMSK (0x00010000u) +#define DMAC_CHSTAT_4_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_4_SETEN (0x00000001u) +#define DMAC_CHCTRL_4_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_4_CLREN (0x00000002u) +#define DMAC_CHCTRL_4_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_4_STG (0x00000004u) +#define DMAC_CHCTRL_4_STG_SHIFT (2u) +#define DMAC_CHCTRL_4_SWRST (0x00000008u) +#define DMAC_CHCTRL_4_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_4_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_4_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_4_CLREND (0x00000020u) +#define DMAC_CHCTRL_4_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_4_CLRTC (0x00000040u) +#define DMAC_CHCTRL_4_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_4_SETSUS (0x00000100u) +#define DMAC_CHCTRL_4_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_4_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_4_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_4_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_4_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_4_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_4_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_4_SEL (0x00000007u) +#define DMAC_CHCFG_4_SEL_SHIFT (0u) +#define DMAC_CHCFG_4_REQD (0x00000008u) +#define DMAC_CHCFG_4_REQD_SHIFT (3u) +#define DMAC_CHCFG_4_LOEN (0x00000010u) +#define DMAC_CHCFG_4_LOEN_SHIFT (4u) +#define DMAC_CHCFG_4_HIEN (0x00000020u) +#define DMAC_CHCFG_4_HIEN_SHIFT (5u) +#define DMAC_CHCFG_4_LVL (0x00000040u) +#define DMAC_CHCFG_4_LVL_SHIFT (6u) +#define DMAC_CHCFG_4_AM (0x00000700u) +#define DMAC_CHCFG_4_AM_SHIFT (8u) +#define DMAC_CHCFG_4_SDS (0x0000F000u) +#define DMAC_CHCFG_4_SDS_SHIFT (12u) +#define DMAC_CHCFG_4_DDS (0x000F0000u) +#define DMAC_CHCFG_4_DDS_SHIFT (16u) +#define DMAC_CHCFG_4_SAD (0x00100000u) +#define DMAC_CHCFG_4_SAD_SHIFT (20u) +#define DMAC_CHCFG_4_DAD (0x00200000u) +#define DMAC_CHCFG_4_DAD_SHIFT (21u) +#define DMAC_CHCFG_4_TM (0x00400000u) +#define DMAC_CHCFG_4_TM_SHIFT (22u) +#define DMAC_CHCFG_4_DEM (0x01000000u) +#define DMAC_CHCFG_4_DEM_SHIFT (24u) +#define DMAC_CHCFG_4_SBE (0x08000000u) +#define DMAC_CHCFG_4_SBE_SHIFT (27u) +#define DMAC_CHCFG_4_RSEL (0x10000000u) +#define DMAC_CHCFG_4_RSEL_SHIFT (28u) +#define DMAC_CHCFG_4_RSW (0x20000000u) +#define DMAC_CHCFG_4_RSW_SHIFT (29u) +#define DMAC_CHCFG_4_REN (0x40000000u) +#define DMAC_CHCFG_4_REN_SHIFT (30u) +#define DMAC_CHCFG_4_DMS (0x80000000u) +#define DMAC_CHCFG_4_DMS_SHIFT (31u) +#define DMAC_CHITVL_4_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_4_ITVL_SHIFT (0u) +#define DMAC_CHEXT_4_SPR (0x00000007u) +#define DMAC_CHEXT_4_SPR_SHIFT (0u) +#define DMAC_CHEXT_4_SCA (0x000000F0u) +#define DMAC_CHEXT_4_SCA_SHIFT (4u) +#define DMAC_CHEXT_4_DPR (0x00000700u) +#define DMAC_CHEXT_4_DPR_SHIFT (8u) +#define DMAC_CHEXT_4_DCA (0x0000F000u) +#define DMAC_CHEXT_4_DCA_SHIFT (12u) +#define DMAC_NXLA_4_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_4_NXLA_SHIFT (0u) +#define DMAC_CRLA_4_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_4_CRLA_SHIFT (0u) +#define DMAC_N0SA_5_SA (0xFFFFFFFFu) +#define DMAC_N0SA_5_SA_SHIFT (0u) +#define DMAC_N0DA_5_DA (0xFFFFFFFFu) +#define DMAC_N0DA_5_DA_SHIFT (0u) +#define DMAC_N0TB_5_TB (0xFFFFFFFFu) +#define DMAC_N0TB_5_TB_SHIFT (0u) +#define DMAC_N1SA_5_SA (0xFFFFFFFFu) +#define DMAC_N1SA_5_SA_SHIFT (0u) +#define DMAC_N1DA_5_DA (0xFFFFFFFFu) +#define DMAC_N1DA_5_DA_SHIFT (0u) +#define DMAC_N1TB_5_TB (0xFFFFFFFFu) +#define DMAC_N1TB_5_TB_SHIFT (0u) +#define DMAC_CRSA_5_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_5_CRSA_SHIFT (0u) +#define DMAC_CRDA_5_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_5_CRDA_SHIFT (0u) +#define DMAC_CRTB_5_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_5_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_5_EN (0x00000001u) +#define DMAC_CHSTAT_5_EN_SHIFT (0u) +#define DMAC_CHSTAT_5_RQST (0x00000002u) +#define DMAC_CHSTAT_5_RQST_SHIFT (1u) +#define DMAC_CHSTAT_5_TACT (0x00000004u) +#define DMAC_CHSTAT_5_TACT_SHIFT (2u) +#define DMAC_CHSTAT_5_SUS (0x00000008u) +#define DMAC_CHSTAT_5_SUS_SHIFT (3u) +#define DMAC_CHSTAT_5_ER (0x00000010u) +#define DMAC_CHSTAT_5_ER_SHIFT (4u) +#define DMAC_CHSTAT_5_END (0x00000020u) +#define DMAC_CHSTAT_5_END_SHIFT (5u) +#define DMAC_CHSTAT_5_TC (0x00000040u) +#define DMAC_CHSTAT_5_TC_SHIFT (6u) +#define DMAC_CHSTAT_5_SR (0x00000080u) +#define DMAC_CHSTAT_5_SR_SHIFT (7u) +#define DMAC_CHSTAT_5_DL (0x00000100u) +#define DMAC_CHSTAT_5_DL_SHIFT (8u) +#define DMAC_CHSTAT_5_DW (0x00000200u) +#define DMAC_CHSTAT_5_DW_SHIFT (9u) +#define DMAC_CHSTAT_5_DER (0x00000400u) +#define DMAC_CHSTAT_5_DER_SHIFT (10u) +#define DMAC_CHSTAT_5_MODE (0x00000800u) +#define DMAC_CHSTAT_5_MODE_SHIFT (11u) +#define DMAC_CHSTAT_5_INTMSK (0x00010000u) +#define DMAC_CHSTAT_5_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_5_SETEN (0x00000001u) +#define DMAC_CHCTRL_5_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_5_CLREN (0x00000002u) +#define DMAC_CHCTRL_5_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_5_STG (0x00000004u) +#define DMAC_CHCTRL_5_STG_SHIFT (2u) +#define DMAC_CHCTRL_5_SWRST (0x00000008u) +#define DMAC_CHCTRL_5_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_5_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_5_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_5_CLREND (0x00000020u) +#define DMAC_CHCTRL_5_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_5_CLRTC (0x00000040u) +#define DMAC_CHCTRL_5_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_5_SETSUS (0x00000100u) +#define DMAC_CHCTRL_5_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_5_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_5_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_5_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_5_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_5_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_5_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_5_SEL (0x00000007u) +#define DMAC_CHCFG_5_SEL_SHIFT (0u) +#define DMAC_CHCFG_5_REQD (0x00000008u) +#define DMAC_CHCFG_5_REQD_SHIFT (3u) +#define DMAC_CHCFG_5_LOEN (0x00000010u) +#define DMAC_CHCFG_5_LOEN_SHIFT (4u) +#define DMAC_CHCFG_5_HIEN (0x00000020u) +#define DMAC_CHCFG_5_HIEN_SHIFT (5u) +#define DMAC_CHCFG_5_LVL (0x00000040u) +#define DMAC_CHCFG_5_LVL_SHIFT (6u) +#define DMAC_CHCFG_5_AM (0x00000700u) +#define DMAC_CHCFG_5_AM_SHIFT (8u) +#define DMAC_CHCFG_5_SDS (0x0000F000u) +#define DMAC_CHCFG_5_SDS_SHIFT (12u) +#define DMAC_CHCFG_5_DDS (0x000F0000u) +#define DMAC_CHCFG_5_DDS_SHIFT (16u) +#define DMAC_CHCFG_5_SAD (0x00100000u) +#define DMAC_CHCFG_5_SAD_SHIFT (20u) +#define DMAC_CHCFG_5_DAD (0x00200000u) +#define DMAC_CHCFG_5_DAD_SHIFT (21u) +#define DMAC_CHCFG_5_TM (0x00400000u) +#define DMAC_CHCFG_5_TM_SHIFT (22u) +#define DMAC_CHCFG_5_DEM (0x01000000u) +#define DMAC_CHCFG_5_DEM_SHIFT (24u) +#define DMAC_CHCFG_5_SBE (0x08000000u) +#define DMAC_CHCFG_5_SBE_SHIFT (27u) +#define DMAC_CHCFG_5_RSEL (0x10000000u) +#define DMAC_CHCFG_5_RSEL_SHIFT (28u) +#define DMAC_CHCFG_5_RSW (0x20000000u) +#define DMAC_CHCFG_5_RSW_SHIFT (29u) +#define DMAC_CHCFG_5_REN (0x40000000u) +#define DMAC_CHCFG_5_REN_SHIFT (30u) +#define DMAC_CHCFG_5_DMS (0x80000000u) +#define DMAC_CHCFG_5_DMS_SHIFT (31u) +#define DMAC_CHITVL_5_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_5_ITVL_SHIFT (0u) +#define DMAC_CHEXT_5_SPR (0x00000007u) +#define DMAC_CHEXT_5_SPR_SHIFT (0u) +#define DMAC_CHEXT_5_SCA (0x000000F0u) +#define DMAC_CHEXT_5_SCA_SHIFT (4u) +#define DMAC_CHEXT_5_DPR (0x00000700u) +#define DMAC_CHEXT_5_DPR_SHIFT (8u) +#define DMAC_CHEXT_5_DCA (0x0000F000u) +#define DMAC_CHEXT_5_DCA_SHIFT (12u) +#define DMAC_NXLA_5_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_5_NXLA_SHIFT (0u) +#define DMAC_CRLA_5_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_5_CRLA_SHIFT (0u) +#define DMAC_N0SA_6_SA (0xFFFFFFFFu) +#define DMAC_N0SA_6_SA_SHIFT (0u) +#define DMAC_N0DA_6_DA (0xFFFFFFFFu) +#define DMAC_N0DA_6_DA_SHIFT (0u) +#define DMAC_N0TB_6_TB (0xFFFFFFFFu) +#define DMAC_N0TB_6_TB_SHIFT (0u) +#define DMAC_N1SA_6_SA (0xFFFFFFFFu) +#define DMAC_N1SA_6_SA_SHIFT (0u) +#define DMAC_N1DA_6_DA (0xFFFFFFFFu) +#define DMAC_N1DA_6_DA_SHIFT (0u) +#define DMAC_N1TB_6_TB (0xFFFFFFFFu) +#define DMAC_N1TB_6_TB_SHIFT (0u) +#define DMAC_CRSA_6_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_6_CRSA_SHIFT (0u) +#define DMAC_CRDA_6_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_6_CRDA_SHIFT (0u) +#define DMAC_CRTB_6_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_6_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_6_EN (0x00000001u) +#define DMAC_CHSTAT_6_EN_SHIFT (0u) +#define DMAC_CHSTAT_6_RQST (0x00000002u) +#define DMAC_CHSTAT_6_RQST_SHIFT (1u) +#define DMAC_CHSTAT_6_TACT (0x00000004u) +#define DMAC_CHSTAT_6_TACT_SHIFT (2u) +#define DMAC_CHSTAT_6_SUS (0x00000008u) +#define DMAC_CHSTAT_6_SUS_SHIFT (3u) +#define DMAC_CHSTAT_6_ER (0x00000010u) +#define DMAC_CHSTAT_6_ER_SHIFT (4u) +#define DMAC_CHSTAT_6_END (0x00000020u) +#define DMAC_CHSTAT_6_END_SHIFT (5u) +#define DMAC_CHSTAT_6_TC (0x00000040u) +#define DMAC_CHSTAT_6_TC_SHIFT (6u) +#define DMAC_CHSTAT_6_SR (0x00000080u) +#define DMAC_CHSTAT_6_SR_SHIFT (7u) +#define DMAC_CHSTAT_6_DL (0x00000100u) +#define DMAC_CHSTAT_6_DL_SHIFT (8u) +#define DMAC_CHSTAT_6_DW (0x00000200u) +#define DMAC_CHSTAT_6_DW_SHIFT (9u) +#define DMAC_CHSTAT_6_DER (0x00000400u) +#define DMAC_CHSTAT_6_DER_SHIFT (10u) +#define DMAC_CHSTAT_6_MODE (0x00000800u) +#define DMAC_CHSTAT_6_MODE_SHIFT (11u) +#define DMAC_CHSTAT_6_INTMSK (0x00010000u) +#define DMAC_CHSTAT_6_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_6_SETEN (0x00000001u) +#define DMAC_CHCTRL_6_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_6_CLREN (0x00000002u) +#define DMAC_CHCTRL_6_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_6_STG (0x00000004u) +#define DMAC_CHCTRL_6_STG_SHIFT (2u) +#define DMAC_CHCTRL_6_SWRST (0x00000008u) +#define DMAC_CHCTRL_6_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_6_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_6_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_6_CLREND (0x00000020u) +#define DMAC_CHCTRL_6_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_6_CLRTC (0x00000040u) +#define DMAC_CHCTRL_6_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_6_SETSUS (0x00000100u) +#define DMAC_CHCTRL_6_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_6_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_6_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_6_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_6_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_6_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_6_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_6_SEL (0x00000007u) +#define DMAC_CHCFG_6_SEL_SHIFT (0u) +#define DMAC_CHCFG_6_REQD (0x00000008u) +#define DMAC_CHCFG_6_REQD_SHIFT (3u) +#define DMAC_CHCFG_6_LOEN (0x00000010u) +#define DMAC_CHCFG_6_LOEN_SHIFT (4u) +#define DMAC_CHCFG_6_HIEN (0x00000020u) +#define DMAC_CHCFG_6_HIEN_SHIFT (5u) +#define DMAC_CHCFG_6_LVL (0x00000040u) +#define DMAC_CHCFG_6_LVL_SHIFT (6u) +#define DMAC_CHCFG_6_AM (0x00000700u) +#define DMAC_CHCFG_6_AM_SHIFT (8u) +#define DMAC_CHCFG_6_SDS (0x0000F000u) +#define DMAC_CHCFG_6_SDS_SHIFT (12u) +#define DMAC_CHCFG_6_DDS (0x000F0000u) +#define DMAC_CHCFG_6_DDS_SHIFT (16u) +#define DMAC_CHCFG_6_SAD (0x00100000u) +#define DMAC_CHCFG_6_SAD_SHIFT (20u) +#define DMAC_CHCFG_6_DAD (0x00200000u) +#define DMAC_CHCFG_6_DAD_SHIFT (21u) +#define DMAC_CHCFG_6_TM (0x00400000u) +#define DMAC_CHCFG_6_TM_SHIFT (22u) +#define DMAC_CHCFG_6_DEM (0x01000000u) +#define DMAC_CHCFG_6_DEM_SHIFT (24u) +#define DMAC_CHCFG_6_SBE (0x08000000u) +#define DMAC_CHCFG_6_SBE_SHIFT (27u) +#define DMAC_CHCFG_6_RSEL (0x10000000u) +#define DMAC_CHCFG_6_RSEL_SHIFT (28u) +#define DMAC_CHCFG_6_RSW (0x20000000u) +#define DMAC_CHCFG_6_RSW_SHIFT (29u) +#define DMAC_CHCFG_6_REN (0x40000000u) +#define DMAC_CHCFG_6_REN_SHIFT (30u) +#define DMAC_CHCFG_6_DMS (0x80000000u) +#define DMAC_CHCFG_6_DMS_SHIFT (31u) +#define DMAC_CHITVL_6_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_6_ITVL_SHIFT (0u) +#define DMAC_CHEXT_6_SPR (0x00000007u) +#define DMAC_CHEXT_6_SPR_SHIFT (0u) +#define DMAC_CHEXT_6_SCA (0x000000F0u) +#define DMAC_CHEXT_6_SCA_SHIFT (4u) +#define DMAC_CHEXT_6_DPR (0x00000700u) +#define DMAC_CHEXT_6_DPR_SHIFT (8u) +#define DMAC_CHEXT_6_DCA (0x0000F000u) +#define DMAC_CHEXT_6_DCA_SHIFT (12u) +#define DMAC_NXLA_6_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_6_NXLA_SHIFT (0u) +#define DMAC_CRLA_6_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_6_CRLA_SHIFT (0u) +#define DMAC_N0SA_7_SA (0xFFFFFFFFu) +#define DMAC_N0SA_7_SA_SHIFT (0u) +#define DMAC_N0DA_7_DA (0xFFFFFFFFu) +#define DMAC_N0DA_7_DA_SHIFT (0u) +#define DMAC_N0TB_7_TB (0xFFFFFFFFu) +#define DMAC_N0TB_7_TB_SHIFT (0u) +#define DMAC_N1SA_7_SA (0xFFFFFFFFu) +#define DMAC_N1SA_7_SA_SHIFT (0u) +#define DMAC_N1DA_7_DA (0xFFFFFFFFu) +#define DMAC_N1DA_7_DA_SHIFT (0u) +#define DMAC_N1TB_7_TB (0xFFFFFFFFu) +#define DMAC_N1TB_7_TB_SHIFT (0u) +#define DMAC_CRSA_7_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_7_CRSA_SHIFT (0u) +#define DMAC_CRDA_7_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_7_CRDA_SHIFT (0u) +#define DMAC_CRTB_7_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_7_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_7_EN (0x00000001u) +#define DMAC_CHSTAT_7_EN_SHIFT (0u) +#define DMAC_CHSTAT_7_RQST (0x00000002u) +#define DMAC_CHSTAT_7_RQST_SHIFT (1u) +#define DMAC_CHSTAT_7_TACT (0x00000004u) +#define DMAC_CHSTAT_7_TACT_SHIFT (2u) +#define DMAC_CHSTAT_7_SUS (0x00000008u) +#define DMAC_CHSTAT_7_SUS_SHIFT (3u) +#define DMAC_CHSTAT_7_ER (0x00000010u) +#define DMAC_CHSTAT_7_ER_SHIFT (4u) +#define DMAC_CHSTAT_7_END (0x00000020u) +#define DMAC_CHSTAT_7_END_SHIFT (5u) +#define DMAC_CHSTAT_7_TC (0x00000040u) +#define DMAC_CHSTAT_7_TC_SHIFT (6u) +#define DMAC_CHSTAT_7_SR (0x00000080u) +#define DMAC_CHSTAT_7_SR_SHIFT (7u) +#define DMAC_CHSTAT_7_DL (0x00000100u) +#define DMAC_CHSTAT_7_DL_SHIFT (8u) +#define DMAC_CHSTAT_7_DW (0x00000200u) +#define DMAC_CHSTAT_7_DW_SHIFT (9u) +#define DMAC_CHSTAT_7_DER (0x00000400u) +#define DMAC_CHSTAT_7_DER_SHIFT (10u) +#define DMAC_CHSTAT_7_MODE (0x00000800u) +#define DMAC_CHSTAT_7_MODE_SHIFT (11u) +#define DMAC_CHSTAT_7_INTMSK (0x00010000u) +#define DMAC_CHSTAT_7_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_7_SETEN (0x00000001u) +#define DMAC_CHCTRL_7_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_7_CLREN (0x00000002u) +#define DMAC_CHCTRL_7_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_7_STG (0x00000004u) +#define DMAC_CHCTRL_7_STG_SHIFT (2u) +#define DMAC_CHCTRL_7_SWRST (0x00000008u) +#define DMAC_CHCTRL_7_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_7_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_7_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_7_CLREND (0x00000020u) +#define DMAC_CHCTRL_7_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_7_CLRTC (0x00000040u) +#define DMAC_CHCTRL_7_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_7_SETSUS (0x00000100u) +#define DMAC_CHCTRL_7_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_7_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_7_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_7_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_7_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_7_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_7_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_7_SEL (0x00000007u) +#define DMAC_CHCFG_7_SEL_SHIFT (0u) +#define DMAC_CHCFG_7_REQD (0x00000008u) +#define DMAC_CHCFG_7_REQD_SHIFT (3u) +#define DMAC_CHCFG_7_LOEN (0x00000010u) +#define DMAC_CHCFG_7_LOEN_SHIFT (4u) +#define DMAC_CHCFG_7_HIEN (0x00000020u) +#define DMAC_CHCFG_7_HIEN_SHIFT (5u) +#define DMAC_CHCFG_7_LVL (0x00000040u) +#define DMAC_CHCFG_7_LVL_SHIFT (6u) +#define DMAC_CHCFG_7_AM (0x00000700u) +#define DMAC_CHCFG_7_AM_SHIFT (8u) +#define DMAC_CHCFG_7_SDS (0x0000F000u) +#define DMAC_CHCFG_7_SDS_SHIFT (12u) +#define DMAC_CHCFG_7_DDS (0x000F0000u) +#define DMAC_CHCFG_7_DDS_SHIFT (16u) +#define DMAC_CHCFG_7_SAD (0x00100000u) +#define DMAC_CHCFG_7_SAD_SHIFT (20u) +#define DMAC_CHCFG_7_DAD (0x00200000u) +#define DMAC_CHCFG_7_DAD_SHIFT (21u) +#define DMAC_CHCFG_7_TM (0x00400000u) +#define DMAC_CHCFG_7_TM_SHIFT (22u) +#define DMAC_CHCFG_7_DEM (0x01000000u) +#define DMAC_CHCFG_7_DEM_SHIFT (24u) +#define DMAC_CHCFG_7_SBE (0x08000000u) +#define DMAC_CHCFG_7_SBE_SHIFT (27u) +#define DMAC_CHCFG_7_RSEL (0x10000000u) +#define DMAC_CHCFG_7_RSEL_SHIFT (28u) +#define DMAC_CHCFG_7_RSW (0x20000000u) +#define DMAC_CHCFG_7_RSW_SHIFT (29u) +#define DMAC_CHCFG_7_REN (0x40000000u) +#define DMAC_CHCFG_7_REN_SHIFT (30u) +#define DMAC_CHCFG_7_DMS (0x80000000u) +#define DMAC_CHCFG_7_DMS_SHIFT (31u) +#define DMAC_CHITVL_7_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_7_ITVL_SHIFT (0u) +#define DMAC_CHEXT_7_SPR (0x00000007u) +#define DMAC_CHEXT_7_SPR_SHIFT (0u) +#define DMAC_CHEXT_7_SCA (0x000000F0u) +#define DMAC_CHEXT_7_SCA_SHIFT (4u) +#define DMAC_CHEXT_7_DPR (0x00000700u) +#define DMAC_CHEXT_7_DPR_SHIFT (8u) +#define DMAC_CHEXT_7_DCA (0x0000F000u) +#define DMAC_CHEXT_7_DCA_SHIFT (12u) +#define DMAC_NXLA_7_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_7_NXLA_SHIFT (0u) +#define DMAC_CRLA_7_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_7_CRLA_SHIFT (0u) +#define DMAC_DCTRL_0_7_PR (0x00000001u) +#define DMAC_DCTRL_0_7_PR_SHIFT (0u) +#define DMAC_DCTRL_0_7_LVINT (0x00000002u) +#define DMAC_DCTRL_0_7_LVINT_SHIFT (1u) +#define DMAC_DCTRL_0_7_LDPR (0x00070000u) +#define DMAC_DCTRL_0_7_LDPR_SHIFT (16u) +#define DMAC_DCTRL_0_7_LDCA (0x00F00000u) +#define DMAC_DCTRL_0_7_LDCA_SHIFT (20u) +#define DMAC_DCTRL_0_7_LWPR (0x07000000u) +#define DMAC_DCTRL_0_7_LWPR_SHIFT (24u) +#define DMAC_DCTRL_0_7_LWCA (0xF0000000u) +#define DMAC_DCTRL_0_7_LWCA_SHIFT (28u) +#define DMAC_DSTAT_EN_0_7_EN0 (0x00000001u) +#define DMAC_DSTAT_EN_0_7_EN0_SHIFT (0u) +#define DMAC_DSTAT_EN_0_7_EN1 (0x00000002u) +#define DMAC_DSTAT_EN_0_7_EN1_SHIFT (1u) +#define DMAC_DSTAT_EN_0_7_EN2 (0x00000004u) +#define DMAC_DSTAT_EN_0_7_EN2_SHIFT (2u) +#define DMAC_DSTAT_EN_0_7_EN3 (0x00000008u) +#define DMAC_DSTAT_EN_0_7_EN3_SHIFT (3u) +#define DMAC_DSTAT_EN_0_7_EN4 (0x00000010u) +#define DMAC_DSTAT_EN_0_7_EN4_SHIFT (4u) +#define DMAC_DSTAT_EN_0_7_EN5 (0x00000020u) +#define DMAC_DSTAT_EN_0_7_EN5_SHIFT (5u) +#define DMAC_DSTAT_EN_0_7_EN6 (0x00000040u) +#define DMAC_DSTAT_EN_0_7_EN6_SHIFT (6u) +#define DMAC_DSTAT_EN_0_7_EN7 (0x00000080u) +#define DMAC_DSTAT_EN_0_7_EN7_SHIFT (7u) +#define DMAC_DSTAT_ER_0_7_ER0 (0x00000001u) +#define DMAC_DSTAT_ER_0_7_ER0_SHIFT (0u) +#define DMAC_DSTAT_ER_0_7_ER1 (0x00000002u) +#define DMAC_DSTAT_ER_0_7_ER1_SHIFT (1u) +#define DMAC_DSTAT_ER_0_7_ER2 (0x00000004u) +#define DMAC_DSTAT_ER_0_7_ER2_SHIFT (2u) +#define DMAC_DSTAT_ER_0_7_ER3 (0x00000008u) +#define DMAC_DSTAT_ER_0_7_ER3_SHIFT (3u) +#define DMAC_DSTAT_ER_0_7_ER4 (0x00000010u) +#define DMAC_DSTAT_ER_0_7_ER4_SHIFT (4u) +#define DMAC_DSTAT_ER_0_7_ER5 (0x00000020u) +#define DMAC_DSTAT_ER_0_7_ER5_SHIFT (5u) +#define DMAC_DSTAT_ER_0_7_ER6 (0x00000040u) +#define DMAC_DSTAT_ER_0_7_ER6_SHIFT (6u) +#define DMAC_DSTAT_ER_0_7_ER7 (0x00000080u) +#define DMAC_DSTAT_ER_0_7_ER7_SHIFT (7u) +#define DMAC_DSTAT_END_0_7_END0 (0x00000001u) +#define DMAC_DSTAT_END_0_7_END0_SHIFT (0u) +#define DMAC_DSTAT_END_0_7_END1 (0x00000002u) +#define DMAC_DSTAT_END_0_7_END1_SHIFT (1u) +#define DMAC_DSTAT_END_0_7_END2 (0x00000004u) +#define DMAC_DSTAT_END_0_7_END2_SHIFT (2u) +#define DMAC_DSTAT_END_0_7_END3 (0x00000008u) +#define DMAC_DSTAT_END_0_7_END3_SHIFT (3u) +#define DMAC_DSTAT_END_0_7_END4 (0x00000010u) +#define DMAC_DSTAT_END_0_7_END4_SHIFT (4u) +#define DMAC_DSTAT_END_0_7_END5 (0x00000020u) +#define DMAC_DSTAT_END_0_7_END5_SHIFT (5u) +#define DMAC_DSTAT_END_0_7_END6 (0x00000040u) +#define DMAC_DSTAT_END_0_7_END6_SHIFT (6u) +#define DMAC_DSTAT_END_0_7_END7 (0x00000080u) +#define DMAC_DSTAT_END_0_7_END7_SHIFT (7u) +#define DMAC_DSTAT_TC_0_7_TC0 (0x00000001u) +#define DMAC_DSTAT_TC_0_7_TC0_SHIFT (0u) +#define DMAC_DSTAT_TC_0_7_TC1 (0x00000002u) +#define DMAC_DSTAT_TC_0_7_TC1_SHIFT (1u) +#define DMAC_DSTAT_TC_0_7_TC2 (0x00000004u) +#define DMAC_DSTAT_TC_0_7_TC2_SHIFT (2u) +#define DMAC_DSTAT_TC_0_7_TC3 (0x00000008u) +#define DMAC_DSTAT_TC_0_7_TC3_SHIFT (3u) +#define DMAC_DSTAT_TC_0_7_TC4 (0x00000010u) +#define DMAC_DSTAT_TC_0_7_TC4_SHIFT (4u) +#define DMAC_DSTAT_TC_0_7_TC5 (0x00000020u) +#define DMAC_DSTAT_TC_0_7_TC5_SHIFT (5u) +#define DMAC_DSTAT_TC_0_7_TC6 (0x00000040u) +#define DMAC_DSTAT_TC_0_7_TC6_SHIFT (6u) +#define DMAC_DSTAT_TC_0_7_TC7 (0x00000080u) +#define DMAC_DSTAT_TC_0_7_TC7_SHIFT (7u) +#define DMAC_DSTAT_SUS_0_7_SUS0 (0x00000001u) +#define DMAC_DSTAT_SUS_0_7_SUS0_SHIFT (0u) +#define DMAC_DSTAT_SUS_0_7_SUS1 (0x00000002u) +#define DMAC_DSTAT_SUS_0_7_SUS1_SHIFT (1u) +#define DMAC_DSTAT_SUS_0_7_SUS2 (0x00000004u) +#define DMAC_DSTAT_SUS_0_7_SUS2_SHIFT (2u) +#define DMAC_DSTAT_SUS_0_7_SUS3 (0x00000008u) +#define DMAC_DSTAT_SUS_0_7_SUS3_SHIFT (3u) +#define DMAC_DSTAT_SUS_0_7_SUS4 (0x00000010u) +#define DMAC_DSTAT_SUS_0_7_SUS4_SHIFT (4u) +#define DMAC_DSTAT_SUS_0_7_SUS5 (0x00000020u) +#define DMAC_DSTAT_SUS_0_7_SUS5_SHIFT (5u) +#define DMAC_DSTAT_SUS_0_7_SUS6 (0x00000040u) +#define DMAC_DSTAT_SUS_0_7_SUS6_SHIFT (6u) +#define DMAC_DSTAT_SUS_0_7_SUS7 (0x00000080u) +#define DMAC_DSTAT_SUS_0_7_SUS7_SHIFT (7u) +#define DMAC_N0SA_8_SA (0xFFFFFFFFu) +#define DMAC_N0SA_8_SA_SHIFT (0u) +#define DMAC_N0DA_8_DA (0xFFFFFFFFu) +#define DMAC_N0DA_8_DA_SHIFT (0u) +#define DMAC_N0TB_8_TB (0xFFFFFFFFu) +#define DMAC_N0TB_8_TB_SHIFT (0u) +#define DMAC_N1SA_8_SA (0xFFFFFFFFu) +#define DMAC_N1SA_8_SA_SHIFT (0u) +#define DMAC_N1DA_8_DA (0xFFFFFFFFu) +#define DMAC_N1DA_8_DA_SHIFT (0u) +#define DMAC_N1TB_8_TB (0xFFFFFFFFu) +#define DMAC_N1TB_8_TB_SHIFT (0u) +#define DMAC_CRSA_8_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_8_CRSA_SHIFT (0u) +#define DMAC_CRDA_8_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_8_CRDA_SHIFT (0u) +#define DMAC_CRTB_8_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_8_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_8_EN (0x00000001u) +#define DMAC_CHSTAT_8_EN_SHIFT (0u) +#define DMAC_CHSTAT_8_RQST (0x00000002u) +#define DMAC_CHSTAT_8_RQST_SHIFT (1u) +#define DMAC_CHSTAT_8_TACT (0x00000004u) +#define DMAC_CHSTAT_8_TACT_SHIFT (2u) +#define DMAC_CHSTAT_8_SUS (0x00000008u) +#define DMAC_CHSTAT_8_SUS_SHIFT (3u) +#define DMAC_CHSTAT_8_ER (0x00000010u) +#define DMAC_CHSTAT_8_ER_SHIFT (4u) +#define DMAC_CHSTAT_8_END (0x00000020u) +#define DMAC_CHSTAT_8_END_SHIFT (5u) +#define DMAC_CHSTAT_8_TC (0x00000040u) +#define DMAC_CHSTAT_8_TC_SHIFT (6u) +#define DMAC_CHSTAT_8_SR (0x00000080u) +#define DMAC_CHSTAT_8_SR_SHIFT (7u) +#define DMAC_CHSTAT_8_DL (0x00000100u) +#define DMAC_CHSTAT_8_DL_SHIFT (8u) +#define DMAC_CHSTAT_8_DW (0x00000200u) +#define DMAC_CHSTAT_8_DW_SHIFT (9u) +#define DMAC_CHSTAT_8_DER (0x00000400u) +#define DMAC_CHSTAT_8_DER_SHIFT (10u) +#define DMAC_CHSTAT_8_MODE (0x00000800u) +#define DMAC_CHSTAT_8_MODE_SHIFT (11u) +#define DMAC_CHSTAT_8_INTMSK (0x00010000u) +#define DMAC_CHSTAT_8_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_8_SETEN (0x00000001u) +#define DMAC_CHCTRL_8_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_8_CLREN (0x00000002u) +#define DMAC_CHCTRL_8_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_8_STG (0x00000004u) +#define DMAC_CHCTRL_8_STG_SHIFT (2u) +#define DMAC_CHCTRL_8_SWRST (0x00000008u) +#define DMAC_CHCTRL_8_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_8_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_8_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_8_CLREND (0x00000020u) +#define DMAC_CHCTRL_8_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_8_CLRTC (0x00000040u) +#define DMAC_CHCTRL_8_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_8_SETSUS (0x00000100u) +#define DMAC_CHCTRL_8_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_8_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_8_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_8_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_8_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_8_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_8_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_8_SEL (0x00000007u) +#define DMAC_CHCFG_8_SEL_SHIFT (0u) +#define DMAC_CHCFG_8_REQD (0x00000008u) +#define DMAC_CHCFG_8_REQD_SHIFT (3u) +#define DMAC_CHCFG_8_LOEN (0x00000010u) +#define DMAC_CHCFG_8_LOEN_SHIFT (4u) +#define DMAC_CHCFG_8_HIEN (0x00000020u) +#define DMAC_CHCFG_8_HIEN_SHIFT (5u) +#define DMAC_CHCFG_8_LVL (0x00000040u) +#define DMAC_CHCFG_8_LVL_SHIFT (6u) +#define DMAC_CHCFG_8_AM (0x00000700u) +#define DMAC_CHCFG_8_AM_SHIFT (8u) +#define DMAC_CHCFG_8_SDS (0x0000F000u) +#define DMAC_CHCFG_8_SDS_SHIFT (12u) +#define DMAC_CHCFG_8_DDS (0x000F0000u) +#define DMAC_CHCFG_8_DDS_SHIFT (16u) +#define DMAC_CHCFG_8_SAD (0x00100000u) +#define DMAC_CHCFG_8_SAD_SHIFT (20u) +#define DMAC_CHCFG_8_DAD (0x00200000u) +#define DMAC_CHCFG_8_DAD_SHIFT (21u) +#define DMAC_CHCFG_8_TM (0x00400000u) +#define DMAC_CHCFG_8_TM_SHIFT (22u) +#define DMAC_CHCFG_8_DEM (0x01000000u) +#define DMAC_CHCFG_8_DEM_SHIFT (24u) +#define DMAC_CHCFG_8_SBE (0x08000000u) +#define DMAC_CHCFG_8_SBE_SHIFT (27u) +#define DMAC_CHCFG_8_RSEL (0x10000000u) +#define DMAC_CHCFG_8_RSEL_SHIFT (28u) +#define DMAC_CHCFG_8_RSW (0x20000000u) +#define DMAC_CHCFG_8_RSW_SHIFT (29u) +#define DMAC_CHCFG_8_REN (0x40000000u) +#define DMAC_CHCFG_8_REN_SHIFT (30u) +#define DMAC_CHCFG_8_DMS (0x80000000u) +#define DMAC_CHCFG_8_DMS_SHIFT (31u) +#define DMAC_CHITVL_8_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_8_ITVL_SHIFT (0u) +#define DMAC_CHEXT_8_SPR (0x00000007u) +#define DMAC_CHEXT_8_SPR_SHIFT (0u) +#define DMAC_CHEXT_8_SCA (0x000000F0u) +#define DMAC_CHEXT_8_SCA_SHIFT (4u) +#define DMAC_CHEXT_8_DPR (0x00000700u) +#define DMAC_CHEXT_8_DPR_SHIFT (8u) +#define DMAC_CHEXT_8_DCA (0x0000F000u) +#define DMAC_CHEXT_8_DCA_SHIFT (12u) +#define DMAC_NXLA_8_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_8_NXLA_SHIFT (0u) +#define DMAC_CRLA_8_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_8_CRLA_SHIFT (0u) +#define DMAC_N0SA_9_SA (0xFFFFFFFFu) +#define DMAC_N0SA_9_SA_SHIFT (0u) +#define DMAC_N0DA_9_DA (0xFFFFFFFFu) +#define DMAC_N0DA_9_DA_SHIFT (0u) +#define DMAC_N0TB_9_TB (0xFFFFFFFFu) +#define DMAC_N0TB_9_TB_SHIFT (0u) +#define DMAC_N1SA_9_SA (0xFFFFFFFFu) +#define DMAC_N1SA_9_SA_SHIFT (0u) +#define DMAC_N1DA_9_DA (0xFFFFFFFFu) +#define DMAC_N1DA_9_DA_SHIFT (0u) +#define DMAC_N1TB_9_TB (0xFFFFFFFFu) +#define DMAC_N1TB_9_TB_SHIFT (0u) +#define DMAC_CRSA_9_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_9_CRSA_SHIFT (0u) +#define DMAC_CRDA_9_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_9_CRDA_SHIFT (0u) +#define DMAC_CRTB_9_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_9_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_9_EN (0x00000001u) +#define DMAC_CHSTAT_9_EN_SHIFT (0u) +#define DMAC_CHSTAT_9_RQST (0x00000002u) +#define DMAC_CHSTAT_9_RQST_SHIFT (1u) +#define DMAC_CHSTAT_9_TACT (0x00000004u) +#define DMAC_CHSTAT_9_TACT_SHIFT (2u) +#define DMAC_CHSTAT_9_SUS (0x00000008u) +#define DMAC_CHSTAT_9_SUS_SHIFT (3u) +#define DMAC_CHSTAT_9_ER (0x00000010u) +#define DMAC_CHSTAT_9_ER_SHIFT (4u) +#define DMAC_CHSTAT_9_END (0x00000020u) +#define DMAC_CHSTAT_9_END_SHIFT (5u) +#define DMAC_CHSTAT_9_TC (0x00000040u) +#define DMAC_CHSTAT_9_TC_SHIFT (6u) +#define DMAC_CHSTAT_9_SR (0x00000080u) +#define DMAC_CHSTAT_9_SR_SHIFT (7u) +#define DMAC_CHSTAT_9_DL (0x00000100u) +#define DMAC_CHSTAT_9_DL_SHIFT (8u) +#define DMAC_CHSTAT_9_DW (0x00000200u) +#define DMAC_CHSTAT_9_DW_SHIFT (9u) +#define DMAC_CHSTAT_9_DER (0x00000400u) +#define DMAC_CHSTAT_9_DER_SHIFT (10u) +#define DMAC_CHSTAT_9_MODE (0x00000800u) +#define DMAC_CHSTAT_9_MODE_SHIFT (11u) +#define DMAC_CHSTAT_9_INTMSK (0x00010000u) +#define DMAC_CHSTAT_9_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_9_SETEN (0x00000001u) +#define DMAC_CHCTRL_9_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_9_CLREN (0x00000002u) +#define DMAC_CHCTRL_9_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_9_STG (0x00000004u) +#define DMAC_CHCTRL_9_STG_SHIFT (2u) +#define DMAC_CHCTRL_9_SWRST (0x00000008u) +#define DMAC_CHCTRL_9_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_9_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_9_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_9_CLREND (0x00000020u) +#define DMAC_CHCTRL_9_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_9_CLRTC (0x00000040u) +#define DMAC_CHCTRL_9_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_9_SETSUS (0x00000100u) +#define DMAC_CHCTRL_9_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_9_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_9_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_9_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_9_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_9_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_9_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_9_SEL (0x00000007u) +#define DMAC_CHCFG_9_SEL_SHIFT (0u) +#define DMAC_CHCFG_9_REQD (0x00000008u) +#define DMAC_CHCFG_9_REQD_SHIFT (3u) +#define DMAC_CHCFG_9_LOEN (0x00000010u) +#define DMAC_CHCFG_9_LOEN_SHIFT (4u) +#define DMAC_CHCFG_9_HIEN (0x00000020u) +#define DMAC_CHCFG_9_HIEN_SHIFT (5u) +#define DMAC_CHCFG_9_LVL (0x00000040u) +#define DMAC_CHCFG_9_LVL_SHIFT (6u) +#define DMAC_CHCFG_9_AM (0x00000700u) +#define DMAC_CHCFG_9_AM_SHIFT (8u) +#define DMAC_CHCFG_9_SDS (0x0000F000u) +#define DMAC_CHCFG_9_SDS_SHIFT (12u) +#define DMAC_CHCFG_9_DDS (0x000F0000u) +#define DMAC_CHCFG_9_DDS_SHIFT (16u) +#define DMAC_CHCFG_9_SAD (0x00100000u) +#define DMAC_CHCFG_9_SAD_SHIFT (20u) +#define DMAC_CHCFG_9_DAD (0x00200000u) +#define DMAC_CHCFG_9_DAD_SHIFT (21u) +#define DMAC_CHCFG_9_TM (0x00400000u) +#define DMAC_CHCFG_9_TM_SHIFT (22u) +#define DMAC_CHCFG_9_DEM (0x01000000u) +#define DMAC_CHCFG_9_DEM_SHIFT (24u) +#define DMAC_CHCFG_9_SBE (0x08000000u) +#define DMAC_CHCFG_9_SBE_SHIFT (27u) +#define DMAC_CHCFG_9_RSEL (0x10000000u) +#define DMAC_CHCFG_9_RSEL_SHIFT (28u) +#define DMAC_CHCFG_9_RSW (0x20000000u) +#define DMAC_CHCFG_9_RSW_SHIFT (29u) +#define DMAC_CHCFG_9_REN (0x40000000u) +#define DMAC_CHCFG_9_REN_SHIFT (30u) +#define DMAC_CHCFG_9_DMS (0x80000000u) +#define DMAC_CHCFG_9_DMS_SHIFT (31u) +#define DMAC_CHITVL_9_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_9_ITVL_SHIFT (0u) +#define DMAC_CHEXT_9_SPR (0x00000007u) +#define DMAC_CHEXT_9_SPR_SHIFT (0u) +#define DMAC_CHEXT_9_SCA (0x000000F0u) +#define DMAC_CHEXT_9_SCA_SHIFT (4u) +#define DMAC_CHEXT_9_DPR (0x00000700u) +#define DMAC_CHEXT_9_DPR_SHIFT (8u) +#define DMAC_CHEXT_9_DCA (0x0000F000u) +#define DMAC_CHEXT_9_DCA_SHIFT (12u) +#define DMAC_NXLA_9_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_9_NXLA_SHIFT (0u) +#define DMAC_CRLA_9_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_9_CRLA_SHIFT (0u) +#define DMAC_N0SA_10_SA (0xFFFFFFFFu) +#define DMAC_N0SA_10_SA_SHIFT (0u) +#define DMAC_N0DA_10_DA (0xFFFFFFFFu) +#define DMAC_N0DA_10_DA_SHIFT (0u) +#define DMAC_N0TB_10_TB (0xFFFFFFFFu) +#define DMAC_N0TB_10_TB_SHIFT (0u) +#define DMAC_N1SA_10_SA (0xFFFFFFFFu) +#define DMAC_N1SA_10_SA_SHIFT (0u) +#define DMAC_N1DA_10_DA (0xFFFFFFFFu) +#define DMAC_N1DA_10_DA_SHIFT (0u) +#define DMAC_N1TB_10_TB (0xFFFFFFFFu) +#define DMAC_N1TB_10_TB_SHIFT (0u) +#define DMAC_CRSA_10_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_10_CRSA_SHIFT (0u) +#define DMAC_CRDA_10_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_10_CRDA_SHIFT (0u) +#define DMAC_CRTB_10_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_10_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_10_EN (0x00000001u) +#define DMAC_CHSTAT_10_EN_SHIFT (0u) +#define DMAC_CHSTAT_10_RQST (0x00000002u) +#define DMAC_CHSTAT_10_RQST_SHIFT (1u) +#define DMAC_CHSTAT_10_TACT (0x00000004u) +#define DMAC_CHSTAT_10_TACT_SHIFT (2u) +#define DMAC_CHSTAT_10_SUS (0x00000008u) +#define DMAC_CHSTAT_10_SUS_SHIFT (3u) +#define DMAC_CHSTAT_10_ER (0x00000010u) +#define DMAC_CHSTAT_10_ER_SHIFT (4u) +#define DMAC_CHSTAT_10_END (0x00000020u) +#define DMAC_CHSTAT_10_END_SHIFT (5u) +#define DMAC_CHSTAT_10_TC (0x00000040u) +#define DMAC_CHSTAT_10_TC_SHIFT (6u) +#define DMAC_CHSTAT_10_SR (0x00000080u) +#define DMAC_CHSTAT_10_SR_SHIFT (7u) +#define DMAC_CHSTAT_10_DL (0x00000100u) +#define DMAC_CHSTAT_10_DL_SHIFT (8u) +#define DMAC_CHSTAT_10_DW (0x00000200u) +#define DMAC_CHSTAT_10_DW_SHIFT (9u) +#define DMAC_CHSTAT_10_DER (0x00000400u) +#define DMAC_CHSTAT_10_DER_SHIFT (10u) +#define DMAC_CHSTAT_10_MODE (0x00000800u) +#define DMAC_CHSTAT_10_MODE_SHIFT (11u) +#define DMAC_CHSTAT_10_INTMSK (0x00010000u) +#define DMAC_CHSTAT_10_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_10_SETEN (0x00000001u) +#define DMAC_CHCTRL_10_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_10_CLREN (0x00000002u) +#define DMAC_CHCTRL_10_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_10_STG (0x00000004u) +#define DMAC_CHCTRL_10_STG_SHIFT (2u) +#define DMAC_CHCTRL_10_SWRST (0x00000008u) +#define DMAC_CHCTRL_10_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_10_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_10_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_10_CLREND (0x00000020u) +#define DMAC_CHCTRL_10_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_10_CLRTC (0x00000040u) +#define DMAC_CHCTRL_10_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_10_SETSUS (0x00000100u) +#define DMAC_CHCTRL_10_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_10_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_10_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_10_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_10_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_10_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_10_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_10_SEL (0x00000007u) +#define DMAC_CHCFG_10_SEL_SHIFT (0u) +#define DMAC_CHCFG_10_REQD (0x00000008u) +#define DMAC_CHCFG_10_REQD_SHIFT (3u) +#define DMAC_CHCFG_10_LOEN (0x00000010u) +#define DMAC_CHCFG_10_LOEN_SHIFT (4u) +#define DMAC_CHCFG_10_HIEN (0x00000020u) +#define DMAC_CHCFG_10_HIEN_SHIFT (5u) +#define DMAC_CHCFG_10_LVL (0x00000040u) +#define DMAC_CHCFG_10_LVL_SHIFT (6u) +#define DMAC_CHCFG_10_AM (0x00000700u) +#define DMAC_CHCFG_10_AM_SHIFT (8u) +#define DMAC_CHCFG_10_SDS (0x0000F000u) +#define DMAC_CHCFG_10_SDS_SHIFT (12u) +#define DMAC_CHCFG_10_DDS (0x000F0000u) +#define DMAC_CHCFG_10_DDS_SHIFT (16u) +#define DMAC_CHCFG_10_SAD (0x00100000u) +#define DMAC_CHCFG_10_SAD_SHIFT (20u) +#define DMAC_CHCFG_10_DAD (0x00200000u) +#define DMAC_CHCFG_10_DAD_SHIFT (21u) +#define DMAC_CHCFG_10_TM (0x00400000u) +#define DMAC_CHCFG_10_TM_SHIFT (22u) +#define DMAC_CHCFG_10_DEM (0x01000000u) +#define DMAC_CHCFG_10_DEM_SHIFT (24u) +#define DMAC_CHCFG_10_SBE (0x08000000u) +#define DMAC_CHCFG_10_SBE_SHIFT (27u) +#define DMAC_CHCFG_10_RSEL (0x10000000u) +#define DMAC_CHCFG_10_RSEL_SHIFT (28u) +#define DMAC_CHCFG_10_RSW (0x20000000u) +#define DMAC_CHCFG_10_RSW_SHIFT (29u) +#define DMAC_CHCFG_10_REN (0x40000000u) +#define DMAC_CHCFG_10_REN_SHIFT (30u) +#define DMAC_CHCFG_10_DMS (0x80000000u) +#define DMAC_CHCFG_10_DMS_SHIFT (31u) +#define DMAC_CHITVL_10_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_10_ITVL_SHIFT (0u) +#define DMAC_CHEXT_10_SPR (0x00000007u) +#define DMAC_CHEXT_10_SPR_SHIFT (0u) +#define DMAC_CHEXT_10_SCA (0x000000F0u) +#define DMAC_CHEXT_10_SCA_SHIFT (4u) +#define DMAC_CHEXT_10_DPR (0x00000700u) +#define DMAC_CHEXT_10_DPR_SHIFT (8u) +#define DMAC_CHEXT_10_DCA (0x0000F000u) +#define DMAC_CHEXT_10_DCA_SHIFT (12u) +#define DMAC_NXLA_10_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_10_NXLA_SHIFT (0u) +#define DMAC_CRLA_10_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_10_CRLA_SHIFT (0u) +#define DMAC_N0SA_11_SA (0xFFFFFFFFu) +#define DMAC_N0SA_11_SA_SHIFT (0u) +#define DMAC_N0DA_11_DA (0xFFFFFFFFu) +#define DMAC_N0DA_11_DA_SHIFT (0u) +#define DMAC_N0TB_11_TB (0xFFFFFFFFu) +#define DMAC_N0TB_11_TB_SHIFT (0u) +#define DMAC_N1SA_11_SA (0xFFFFFFFFu) +#define DMAC_N1SA_11_SA_SHIFT (0u) +#define DMAC_N1DA_11_DA (0xFFFFFFFFu) +#define DMAC_N1DA_11_DA_SHIFT (0u) +#define DMAC_N1TB_11_TB (0xFFFFFFFFu) +#define DMAC_N1TB_11_TB_SHIFT (0u) +#define DMAC_CRSA_11_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_11_CRSA_SHIFT (0u) +#define DMAC_CRDA_11_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_11_CRDA_SHIFT (0u) +#define DMAC_CRTB_11_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_11_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_11_EN (0x00000001u) +#define DMAC_CHSTAT_11_EN_SHIFT (0u) +#define DMAC_CHSTAT_11_RQST (0x00000002u) +#define DMAC_CHSTAT_11_RQST_SHIFT (1u) +#define DMAC_CHSTAT_11_TACT (0x00000004u) +#define DMAC_CHSTAT_11_TACT_SHIFT (2u) +#define DMAC_CHSTAT_11_SUS (0x00000008u) +#define DMAC_CHSTAT_11_SUS_SHIFT (3u) +#define DMAC_CHSTAT_11_ER (0x00000010u) +#define DMAC_CHSTAT_11_ER_SHIFT (4u) +#define DMAC_CHSTAT_11_END (0x00000020u) +#define DMAC_CHSTAT_11_END_SHIFT (5u) +#define DMAC_CHSTAT_11_TC (0x00000040u) +#define DMAC_CHSTAT_11_TC_SHIFT (6u) +#define DMAC_CHSTAT_11_SR (0x00000080u) +#define DMAC_CHSTAT_11_SR_SHIFT (7u) +#define DMAC_CHSTAT_11_DL (0x00000100u) +#define DMAC_CHSTAT_11_DL_SHIFT (8u) +#define DMAC_CHSTAT_11_DW (0x00000200u) +#define DMAC_CHSTAT_11_DW_SHIFT (9u) +#define DMAC_CHSTAT_11_DER (0x00000400u) +#define DMAC_CHSTAT_11_DER_SHIFT (10u) +#define DMAC_CHSTAT_11_MODE (0x00000800u) +#define DMAC_CHSTAT_11_MODE_SHIFT (11u) +#define DMAC_CHSTAT_11_INTMSK (0x00010000u) +#define DMAC_CHSTAT_11_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_11_SETEN (0x00000001u) +#define DMAC_CHCTRL_11_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_11_CLREN (0x00000002u) +#define DMAC_CHCTRL_11_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_11_STG (0x00000004u) +#define DMAC_CHCTRL_11_STG_SHIFT (2u) +#define DMAC_CHCTRL_11_SWRST (0x00000008u) +#define DMAC_CHCTRL_11_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_11_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_11_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_11_CLREND (0x00000020u) +#define DMAC_CHCTRL_11_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_11_CLRTC (0x00000040u) +#define DMAC_CHCTRL_11_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_11_SETSUS (0x00000100u) +#define DMAC_CHCTRL_11_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_11_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_11_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_11_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_11_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_11_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_11_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_11_SEL (0x00000007u) +#define DMAC_CHCFG_11_SEL_SHIFT (0u) +#define DMAC_CHCFG_11_REQD (0x00000008u) +#define DMAC_CHCFG_11_REQD_SHIFT (3u) +#define DMAC_CHCFG_11_LOEN (0x00000010u) +#define DMAC_CHCFG_11_LOEN_SHIFT (4u) +#define DMAC_CHCFG_11_HIEN (0x00000020u) +#define DMAC_CHCFG_11_HIEN_SHIFT (5u) +#define DMAC_CHCFG_11_LVL (0x00000040u) +#define DMAC_CHCFG_11_LVL_SHIFT (6u) +#define DMAC_CHCFG_11_AM (0x00000700u) +#define DMAC_CHCFG_11_AM_SHIFT (8u) +#define DMAC_CHCFG_11_SDS (0x0000F000u) +#define DMAC_CHCFG_11_SDS_SHIFT (12u) +#define DMAC_CHCFG_11_DDS (0x000F0000u) +#define DMAC_CHCFG_11_DDS_SHIFT (16u) +#define DMAC_CHCFG_11_SAD (0x00100000u) +#define DMAC_CHCFG_11_SAD_SHIFT (20u) +#define DMAC_CHCFG_11_DAD (0x00200000u) +#define DMAC_CHCFG_11_DAD_SHIFT (21u) +#define DMAC_CHCFG_11_TM (0x00400000u) +#define DMAC_CHCFG_11_TM_SHIFT (22u) +#define DMAC_CHCFG_11_DEM (0x01000000u) +#define DMAC_CHCFG_11_DEM_SHIFT (24u) +#define DMAC_CHCFG_11_SBE (0x08000000u) +#define DMAC_CHCFG_11_SBE_SHIFT (27u) +#define DMAC_CHCFG_11_RSEL (0x10000000u) +#define DMAC_CHCFG_11_RSEL_SHIFT (28u) +#define DMAC_CHCFG_11_RSW (0x20000000u) +#define DMAC_CHCFG_11_RSW_SHIFT (29u) +#define DMAC_CHCFG_11_REN (0x40000000u) +#define DMAC_CHCFG_11_REN_SHIFT (30u) +#define DMAC_CHCFG_11_DMS (0x80000000u) +#define DMAC_CHCFG_11_DMS_SHIFT (31u) +#define DMAC_CHITVL_11_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_11_ITVL_SHIFT (0u) +#define DMAC_CHEXT_11_SPR (0x00000007u) +#define DMAC_CHEXT_11_SPR_SHIFT (0u) +#define DMAC_CHEXT_11_SCA (0x000000F0u) +#define DMAC_CHEXT_11_SCA_SHIFT (4u) +#define DMAC_CHEXT_11_DPR (0x00000700u) +#define DMAC_CHEXT_11_DPR_SHIFT (8u) +#define DMAC_CHEXT_11_DCA (0x0000F000u) +#define DMAC_CHEXT_11_DCA_SHIFT (12u) +#define DMAC_NXLA_11_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_11_NXLA_SHIFT (0u) +#define DMAC_CRLA_11_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_11_CRLA_SHIFT (0u) +#define DMAC_N0SA_12_SA (0xFFFFFFFFu) +#define DMAC_N0SA_12_SA_SHIFT (0u) +#define DMAC_N0DA_12_DA (0xFFFFFFFFu) +#define DMAC_N0DA_12_DA_SHIFT (0u) +#define DMAC_N0TB_12_TB (0xFFFFFFFFu) +#define DMAC_N0TB_12_TB_SHIFT (0u) +#define DMAC_N1SA_12_SA (0xFFFFFFFFu) +#define DMAC_N1SA_12_SA_SHIFT (0u) +#define DMAC_N1DA_12_DA (0xFFFFFFFFu) +#define DMAC_N1DA_12_DA_SHIFT (0u) +#define DMAC_N1TB_12_TB (0xFFFFFFFFu) +#define DMAC_N1TB_12_TB_SHIFT (0u) +#define DMAC_CRSA_12_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_12_CRSA_SHIFT (0u) +#define DMAC_CRDA_12_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_12_CRDA_SHIFT (0u) +#define DMAC_CRTB_12_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_12_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_12_EN (0x00000001u) +#define DMAC_CHSTAT_12_EN_SHIFT (0u) +#define DMAC_CHSTAT_12_RQST (0x00000002u) +#define DMAC_CHSTAT_12_RQST_SHIFT (1u) +#define DMAC_CHSTAT_12_TACT (0x00000004u) +#define DMAC_CHSTAT_12_TACT_SHIFT (2u) +#define DMAC_CHSTAT_12_SUS (0x00000008u) +#define DMAC_CHSTAT_12_SUS_SHIFT (3u) +#define DMAC_CHSTAT_12_ER (0x00000010u) +#define DMAC_CHSTAT_12_ER_SHIFT (4u) +#define DMAC_CHSTAT_12_END (0x00000020u) +#define DMAC_CHSTAT_12_END_SHIFT (5u) +#define DMAC_CHSTAT_12_TC (0x00000040u) +#define DMAC_CHSTAT_12_TC_SHIFT (6u) +#define DMAC_CHSTAT_12_SR (0x00000080u) +#define DMAC_CHSTAT_12_SR_SHIFT (7u) +#define DMAC_CHSTAT_12_DL (0x00000100u) +#define DMAC_CHSTAT_12_DL_SHIFT (8u) +#define DMAC_CHSTAT_12_DW (0x00000200u) +#define DMAC_CHSTAT_12_DW_SHIFT (9u) +#define DMAC_CHSTAT_12_DER (0x00000400u) +#define DMAC_CHSTAT_12_DER_SHIFT (10u) +#define DMAC_CHSTAT_12_MODE (0x00000800u) +#define DMAC_CHSTAT_12_MODE_SHIFT (11u) +#define DMAC_CHSTAT_12_INTMSK (0x00010000u) +#define DMAC_CHSTAT_12_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_12_SETEN (0x00000001u) +#define DMAC_CHCTRL_12_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_12_CLREN (0x00000002u) +#define DMAC_CHCTRL_12_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_12_STG (0x00000004u) +#define DMAC_CHCTRL_12_STG_SHIFT (2u) +#define DMAC_CHCTRL_12_SWRST (0x00000008u) +#define DMAC_CHCTRL_12_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_12_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_12_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_12_CLREND (0x00000020u) +#define DMAC_CHCTRL_12_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_12_CLRTC (0x00000040u) +#define DMAC_CHCTRL_12_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_12_SETSUS (0x00000100u) +#define DMAC_CHCTRL_12_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_12_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_12_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_12_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_12_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_12_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_12_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_12_SEL (0x00000007u) +#define DMAC_CHCFG_12_SEL_SHIFT (0u) +#define DMAC_CHCFG_12_REQD (0x00000008u) +#define DMAC_CHCFG_12_REQD_SHIFT (3u) +#define DMAC_CHCFG_12_LOEN (0x00000010u) +#define DMAC_CHCFG_12_LOEN_SHIFT (4u) +#define DMAC_CHCFG_12_HIEN (0x00000020u) +#define DMAC_CHCFG_12_HIEN_SHIFT (5u) +#define DMAC_CHCFG_12_LVL (0x00000040u) +#define DMAC_CHCFG_12_LVL_SHIFT (6u) +#define DMAC_CHCFG_12_AM (0x00000700u) +#define DMAC_CHCFG_12_AM_SHIFT (8u) +#define DMAC_CHCFG_12_SDS (0x0000F000u) +#define DMAC_CHCFG_12_SDS_SHIFT (12u) +#define DMAC_CHCFG_12_DDS (0x000F0000u) +#define DMAC_CHCFG_12_DDS_SHIFT (16u) +#define DMAC_CHCFG_12_SAD (0x00100000u) +#define DMAC_CHCFG_12_SAD_SHIFT (20u) +#define DMAC_CHCFG_12_DAD (0x00200000u) +#define DMAC_CHCFG_12_DAD_SHIFT (21u) +#define DMAC_CHCFG_12_TM (0x00400000u) +#define DMAC_CHCFG_12_TM_SHIFT (22u) +#define DMAC_CHCFG_12_DEM (0x01000000u) +#define DMAC_CHCFG_12_DEM_SHIFT (24u) +#define DMAC_CHCFG_12_SBE (0x08000000u) +#define DMAC_CHCFG_12_SBE_SHIFT (27u) +#define DMAC_CHCFG_12_RSEL (0x10000000u) +#define DMAC_CHCFG_12_RSEL_SHIFT (28u) +#define DMAC_CHCFG_12_RSW (0x20000000u) +#define DMAC_CHCFG_12_RSW_SHIFT (29u) +#define DMAC_CHCFG_12_REN (0x40000000u) +#define DMAC_CHCFG_12_REN_SHIFT (30u) +#define DMAC_CHCFG_12_DMS (0x80000000u) +#define DMAC_CHCFG_12_DMS_SHIFT (31u) +#define DMAC_CHITVL_12_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_12_ITVL_SHIFT (0u) +#define DMAC_CHEXT_12_SPR (0x00000007u) +#define DMAC_CHEXT_12_SPR_SHIFT (0u) +#define DMAC_CHEXT_12_SCA (0x000000F0u) +#define DMAC_CHEXT_12_SCA_SHIFT (4u) +#define DMAC_CHEXT_12_DPR (0x00000700u) +#define DMAC_CHEXT_12_DPR_SHIFT (8u) +#define DMAC_CHEXT_12_DCA (0x0000F000u) +#define DMAC_CHEXT_12_DCA_SHIFT (12u) +#define DMAC_NXLA_12_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_12_NXLA_SHIFT (0u) +#define DMAC_CRLA_12_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_12_CRLA_SHIFT (0u) +#define DMAC_N0SA_13_SA (0xFFFFFFFFu) +#define DMAC_N0SA_13_SA_SHIFT (0u) +#define DMAC_N0DA_13_DA (0xFFFFFFFFu) +#define DMAC_N0DA_13_DA_SHIFT (0u) +#define DMAC_N0TB_13_TB (0xFFFFFFFFu) +#define DMAC_N0TB_13_TB_SHIFT (0u) +#define DMAC_N1SA_13_SA (0xFFFFFFFFu) +#define DMAC_N1SA_13_SA_SHIFT (0u) +#define DMAC_N1DA_13_DA (0xFFFFFFFFu) +#define DMAC_N1DA_13_DA_SHIFT (0u) +#define DMAC_N1TB_13_TB (0xFFFFFFFFu) +#define DMAC_N1TB_13_TB_SHIFT (0u) +#define DMAC_CRSA_13_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_13_CRSA_SHIFT (0u) +#define DMAC_CRDA_13_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_13_CRDA_SHIFT (0u) +#define DMAC_CRTB_13_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_13_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_13_EN (0x00000001u) +#define DMAC_CHSTAT_13_EN_SHIFT (0u) +#define DMAC_CHSTAT_13_RQST (0x00000002u) +#define DMAC_CHSTAT_13_RQST_SHIFT (1u) +#define DMAC_CHSTAT_13_TACT (0x00000004u) +#define DMAC_CHSTAT_13_TACT_SHIFT (2u) +#define DMAC_CHSTAT_13_SUS (0x00000008u) +#define DMAC_CHSTAT_13_SUS_SHIFT (3u) +#define DMAC_CHSTAT_13_ER (0x00000010u) +#define DMAC_CHSTAT_13_ER_SHIFT (4u) +#define DMAC_CHSTAT_13_END (0x00000020u) +#define DMAC_CHSTAT_13_END_SHIFT (5u) +#define DMAC_CHSTAT_13_TC (0x00000040u) +#define DMAC_CHSTAT_13_TC_SHIFT (6u) +#define DMAC_CHSTAT_13_SR (0x00000080u) +#define DMAC_CHSTAT_13_SR_SHIFT (7u) +#define DMAC_CHSTAT_13_DL (0x00000100u) +#define DMAC_CHSTAT_13_DL_SHIFT (8u) +#define DMAC_CHSTAT_13_DW (0x00000200u) +#define DMAC_CHSTAT_13_DW_SHIFT (9u) +#define DMAC_CHSTAT_13_DER (0x00000400u) +#define DMAC_CHSTAT_13_DER_SHIFT (10u) +#define DMAC_CHSTAT_13_MODE (0x00000800u) +#define DMAC_CHSTAT_13_MODE_SHIFT (11u) +#define DMAC_CHSTAT_13_INTMSK (0x00010000u) +#define DMAC_CHSTAT_13_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_13_SETEN (0x00000001u) +#define DMAC_CHCTRL_13_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_13_CLREN (0x00000002u) +#define DMAC_CHCTRL_13_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_13_STG (0x00000004u) +#define DMAC_CHCTRL_13_STG_SHIFT (2u) +#define DMAC_CHCTRL_13_SWRST (0x00000008u) +#define DMAC_CHCTRL_13_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_13_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_13_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_13_CLREND (0x00000020u) +#define DMAC_CHCTRL_13_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_13_CLRTC (0x00000040u) +#define DMAC_CHCTRL_13_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_13_SETSUS (0x00000100u) +#define DMAC_CHCTRL_13_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_13_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_13_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_13_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_13_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_13_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_13_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_13_SEL (0x00000007u) +#define DMAC_CHCFG_13_SEL_SHIFT (0u) +#define DMAC_CHCFG_13_REQD (0x00000008u) +#define DMAC_CHCFG_13_REQD_SHIFT (3u) +#define DMAC_CHCFG_13_LOEN (0x00000010u) +#define DMAC_CHCFG_13_LOEN_SHIFT (4u) +#define DMAC_CHCFG_13_HIEN (0x00000020u) +#define DMAC_CHCFG_13_HIEN_SHIFT (5u) +#define DMAC_CHCFG_13_LVL (0x00000040u) +#define DMAC_CHCFG_13_LVL_SHIFT (6u) +#define DMAC_CHCFG_13_AM (0x00000700u) +#define DMAC_CHCFG_13_AM_SHIFT (8u) +#define DMAC_CHCFG_13_SDS (0x0000F000u) +#define DMAC_CHCFG_13_SDS_SHIFT (12u) +#define DMAC_CHCFG_13_DDS (0x000F0000u) +#define DMAC_CHCFG_13_DDS_SHIFT (16u) +#define DMAC_CHCFG_13_SAD (0x00100000u) +#define DMAC_CHCFG_13_SAD_SHIFT (20u) +#define DMAC_CHCFG_13_DAD (0x00200000u) +#define DMAC_CHCFG_13_DAD_SHIFT (21u) +#define DMAC_CHCFG_13_TM (0x00400000u) +#define DMAC_CHCFG_13_TM_SHIFT (22u) +#define DMAC_CHCFG_13_DEM (0x01000000u) +#define DMAC_CHCFG_13_DEM_SHIFT (24u) +#define DMAC_CHCFG_13_SBE (0x08000000u) +#define DMAC_CHCFG_13_SBE_SHIFT (27u) +#define DMAC_CHCFG_13_RSEL (0x10000000u) +#define DMAC_CHCFG_13_RSEL_SHIFT (28u) +#define DMAC_CHCFG_13_RSW (0x20000000u) +#define DMAC_CHCFG_13_RSW_SHIFT (29u) +#define DMAC_CHCFG_13_REN (0x40000000u) +#define DMAC_CHCFG_13_REN_SHIFT (30u) +#define DMAC_CHCFG_13_DMS (0x80000000u) +#define DMAC_CHCFG_13_DMS_SHIFT (31u) +#define DMAC_CHITVL_13_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_13_ITVL_SHIFT (0u) +#define DMAC_CHEXT_13_SPR (0x00000007u) +#define DMAC_CHEXT_13_SPR_SHIFT (0u) +#define DMAC_CHEXT_13_SCA (0x000000F0u) +#define DMAC_CHEXT_13_SCA_SHIFT (4u) +#define DMAC_CHEXT_13_DPR (0x00000700u) +#define DMAC_CHEXT_13_DPR_SHIFT (8u) +#define DMAC_CHEXT_13_DCA (0x0000F000u) +#define DMAC_CHEXT_13_DCA_SHIFT (12u) +#define DMAC_NXLA_13_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_13_NXLA_SHIFT (0u) +#define DMAC_CRLA_13_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_13_CRLA_SHIFT (0u) +#define DMAC_N0SA_14_SA (0xFFFFFFFFu) +#define DMAC_N0SA_14_SA_SHIFT (0u) +#define DMAC_N0DA_14_DA (0xFFFFFFFFu) +#define DMAC_N0DA_14_DA_SHIFT (0u) +#define DMAC_N0TB_14_TB (0xFFFFFFFFu) +#define DMAC_N0TB_14_TB_SHIFT (0u) +#define DMAC_N1SA_14_SA (0xFFFFFFFFu) +#define DMAC_N1SA_14_SA_SHIFT (0u) +#define DMAC_N1DA_14_DA (0xFFFFFFFFu) +#define DMAC_N1DA_14_DA_SHIFT (0u) +#define DMAC_N1TB_14_TB (0xFFFFFFFFu) +#define DMAC_N1TB_14_TB_SHIFT (0u) +#define DMAC_CRSA_14_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_14_CRSA_SHIFT (0u) +#define DMAC_CRDA_14_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_14_CRDA_SHIFT (0u) +#define DMAC_CRTB_14_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_14_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_14_EN (0x00000001u) +#define DMAC_CHSTAT_14_EN_SHIFT (0u) +#define DMAC_CHSTAT_14_RQST (0x00000002u) +#define DMAC_CHSTAT_14_RQST_SHIFT (1u) +#define DMAC_CHSTAT_14_TACT (0x00000004u) +#define DMAC_CHSTAT_14_TACT_SHIFT (2u) +#define DMAC_CHSTAT_14_SUS (0x00000008u) +#define DMAC_CHSTAT_14_SUS_SHIFT (3u) +#define DMAC_CHSTAT_14_ER (0x00000010u) +#define DMAC_CHSTAT_14_ER_SHIFT (4u) +#define DMAC_CHSTAT_14_END (0x00000020u) +#define DMAC_CHSTAT_14_END_SHIFT (5u) +#define DMAC_CHSTAT_14_TC (0x00000040u) +#define DMAC_CHSTAT_14_TC_SHIFT (6u) +#define DMAC_CHSTAT_14_SR (0x00000080u) +#define DMAC_CHSTAT_14_SR_SHIFT (7u) +#define DMAC_CHSTAT_14_DL (0x00000100u) +#define DMAC_CHSTAT_14_DL_SHIFT (8u) +#define DMAC_CHSTAT_14_DW (0x00000200u) +#define DMAC_CHSTAT_14_DW_SHIFT (9u) +#define DMAC_CHSTAT_14_DER (0x00000400u) +#define DMAC_CHSTAT_14_DER_SHIFT (10u) +#define DMAC_CHSTAT_14_MODE (0x00000800u) +#define DMAC_CHSTAT_14_MODE_SHIFT (11u) +#define DMAC_CHSTAT_14_INTMSK (0x00010000u) +#define DMAC_CHSTAT_14_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_14_SETEN (0x00000001u) +#define DMAC_CHCTRL_14_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_14_CLREN (0x00000002u) +#define DMAC_CHCTRL_14_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_14_STG (0x00000004u) +#define DMAC_CHCTRL_14_STG_SHIFT (2u) +#define DMAC_CHCTRL_14_SWRST (0x00000008u) +#define DMAC_CHCTRL_14_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_14_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_14_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_14_CLREND (0x00000020u) +#define DMAC_CHCTRL_14_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_14_CLRTC (0x00000040u) +#define DMAC_CHCTRL_14_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_14_SETSUS (0x00000100u) +#define DMAC_CHCTRL_14_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_14_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_14_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_14_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_14_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_14_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_14_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_14_SEL (0x00000007u) +#define DMAC_CHCFG_14_SEL_SHIFT (0u) +#define DMAC_CHCFG_14_REQD (0x00000008u) +#define DMAC_CHCFG_14_REQD_SHIFT (3u) +#define DMAC_CHCFG_14_LOEN (0x00000010u) +#define DMAC_CHCFG_14_LOEN_SHIFT (4u) +#define DMAC_CHCFG_14_HIEN (0x00000020u) +#define DMAC_CHCFG_14_HIEN_SHIFT (5u) +#define DMAC_CHCFG_14_LVL (0x00000040u) +#define DMAC_CHCFG_14_LVL_SHIFT (6u) +#define DMAC_CHCFG_14_AM (0x00000700u) +#define DMAC_CHCFG_14_AM_SHIFT (8u) +#define DMAC_CHCFG_14_SDS (0x0000F000u) +#define DMAC_CHCFG_14_SDS_SHIFT (12u) +#define DMAC_CHCFG_14_DDS (0x000F0000u) +#define DMAC_CHCFG_14_DDS_SHIFT (16u) +#define DMAC_CHCFG_14_SAD (0x00100000u) +#define DMAC_CHCFG_14_SAD_SHIFT (20u) +#define DMAC_CHCFG_14_DAD (0x00200000u) +#define DMAC_CHCFG_14_DAD_SHIFT (21u) +#define DMAC_CHCFG_14_TM (0x00400000u) +#define DMAC_CHCFG_14_TM_SHIFT (22u) +#define DMAC_CHCFG_14_DEM (0x01000000u) +#define DMAC_CHCFG_14_DEM_SHIFT (24u) +#define DMAC_CHCFG_14_SBE (0x08000000u) +#define DMAC_CHCFG_14_SBE_SHIFT (27u) +#define DMAC_CHCFG_14_RSEL (0x10000000u) +#define DMAC_CHCFG_14_RSEL_SHIFT (28u) +#define DMAC_CHCFG_14_RSW (0x20000000u) +#define DMAC_CHCFG_14_RSW_SHIFT (29u) +#define DMAC_CHCFG_14_REN (0x40000000u) +#define DMAC_CHCFG_14_REN_SHIFT (30u) +#define DMAC_CHCFG_14_DMS (0x80000000u) +#define DMAC_CHCFG_14_DMS_SHIFT (31u) +#define DMAC_CHITVL_14_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_14_ITVL_SHIFT (0u) +#define DMAC_CHEXT_14_SPR (0x00000007u) +#define DMAC_CHEXT_14_SPR_SHIFT (0u) +#define DMAC_CHEXT_14_SCA (0x000000F0u) +#define DMAC_CHEXT_14_SCA_SHIFT (4u) +#define DMAC_CHEXT_14_DPR (0x00000700u) +#define DMAC_CHEXT_14_DPR_SHIFT (8u) +#define DMAC_CHEXT_14_DCA (0x0000F000u) +#define DMAC_CHEXT_14_DCA_SHIFT (12u) +#define DMAC_NXLA_14_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_14_NXLA_SHIFT (0u) +#define DMAC_CRLA_14_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_14_CRLA_SHIFT (0u) +#define DMAC_N0SA_15_SA (0xFFFFFFFFu) +#define DMAC_N0SA_15_SA_SHIFT (0u) +#define DMAC_N0DA_15_DA (0xFFFFFFFFu) +#define DMAC_N0DA_15_DA_SHIFT (0u) +#define DMAC_N0TB_15_TB (0xFFFFFFFFu) +#define DMAC_N0TB_15_TB_SHIFT (0u) +#define DMAC_N1SA_15_SA (0xFFFFFFFFu) +#define DMAC_N1SA_15_SA_SHIFT (0u) +#define DMAC_N1DA_15_DA (0xFFFFFFFFu) +#define DMAC_N1DA_15_DA_SHIFT (0u) +#define DMAC_N1TB_15_TB (0xFFFFFFFFu) +#define DMAC_N1TB_15_TB_SHIFT (0u) +#define DMAC_CRSA_15_CRSA (0xFFFFFFFFu) +#define DMAC_CRSA_15_CRSA_SHIFT (0u) +#define DMAC_CRDA_15_CRDA (0xFFFFFFFFu) +#define DMAC_CRDA_15_CRDA_SHIFT (0u) +#define DMAC_CRTB_15_CRTB (0xFFFFFFFFu) +#define DMAC_CRTB_15_CRTB_SHIFT (0u) +#define DMAC_CHSTAT_15_EN (0x00000001u) +#define DMAC_CHSTAT_15_EN_SHIFT (0u) +#define DMAC_CHSTAT_15_RQST (0x00000002u) +#define DMAC_CHSTAT_15_RQST_SHIFT (1u) +#define DMAC_CHSTAT_15_TACT (0x00000004u) +#define DMAC_CHSTAT_15_TACT_SHIFT (2u) +#define DMAC_CHSTAT_15_SUS (0x00000008u) +#define DMAC_CHSTAT_15_SUS_SHIFT (3u) +#define DMAC_CHSTAT_15_ER (0x00000010u) +#define DMAC_CHSTAT_15_ER_SHIFT (4u) +#define DMAC_CHSTAT_15_END (0x00000020u) +#define DMAC_CHSTAT_15_END_SHIFT (5u) +#define DMAC_CHSTAT_15_TC (0x00000040u) +#define DMAC_CHSTAT_15_TC_SHIFT (6u) +#define DMAC_CHSTAT_15_SR (0x00000080u) +#define DMAC_CHSTAT_15_SR_SHIFT (7u) +#define DMAC_CHSTAT_15_DL (0x00000100u) +#define DMAC_CHSTAT_15_DL_SHIFT (8u) +#define DMAC_CHSTAT_15_DW (0x00000200u) +#define DMAC_CHSTAT_15_DW_SHIFT (9u) +#define DMAC_CHSTAT_15_DER (0x00000400u) +#define DMAC_CHSTAT_15_DER_SHIFT (10u) +#define DMAC_CHSTAT_15_MODE (0x00000800u) +#define DMAC_CHSTAT_15_MODE_SHIFT (11u) +#define DMAC_CHSTAT_15_INTMSK (0x00010000u) +#define DMAC_CHSTAT_15_INTMSK_SHIFT (16u) +#define DMAC_CHCTRL_15_SETEN (0x00000001u) +#define DMAC_CHCTRL_15_SETEN_SHIFT (0u) +#define DMAC_CHCTRL_15_CLREN (0x00000002u) +#define DMAC_CHCTRL_15_CLREN_SHIFT (1u) +#define DMAC_CHCTRL_15_STG (0x00000004u) +#define DMAC_CHCTRL_15_STG_SHIFT (2u) +#define DMAC_CHCTRL_15_SWRST (0x00000008u) +#define DMAC_CHCTRL_15_SWRST_SHIFT (3u) +#define DMAC_CHCTRL_15_CLRRQ (0x00000010u) +#define DMAC_CHCTRL_15_CLRRQ_SHIFT (4u) +#define DMAC_CHCTRL_15_CLREND (0x00000020u) +#define DMAC_CHCTRL_15_CLREND_SHIFT (5u) +#define DMAC_CHCTRL_15_CLRTC (0x00000040u) +#define DMAC_CHCTRL_15_CLRTC_SHIFT (6u) +#define DMAC_CHCTRL_15_SETSUS (0x00000100u) +#define DMAC_CHCTRL_15_SETSUS_SHIFT (8u) +#define DMAC_CHCTRL_15_CLRSUS (0x00000200u) +#define DMAC_CHCTRL_15_CLRSUS_SHIFT (9u) +#define DMAC_CHCTRL_15_SETINTMSK (0x00010000u) +#define DMAC_CHCTRL_15_SETINTMSK_SHIFT (16u) +#define DMAC_CHCTRL_15_CLRINTMSK (0x00020000u) +#define DMAC_CHCTRL_15_CLRINTMSK_SHIFT (17u) +#define DMAC_CHCFG_15_SEL (0x00000007u) +#define DMAC_CHCFG_15_SEL_SHIFT (0u) +#define DMAC_CHCFG_15_REQD (0x00000008u) +#define DMAC_CHCFG_15_REQD_SHIFT (3u) +#define DMAC_CHCFG_15_LOEN (0x00000010u) +#define DMAC_CHCFG_15_LOEN_SHIFT (4u) +#define DMAC_CHCFG_15_HIEN (0x00000020u) +#define DMAC_CHCFG_15_HIEN_SHIFT (5u) +#define DMAC_CHCFG_15_LVL (0x00000040u) +#define DMAC_CHCFG_15_LVL_SHIFT (6u) +#define DMAC_CHCFG_15_AM (0x00000700u) +#define DMAC_CHCFG_15_AM_SHIFT (8u) +#define DMAC_CHCFG_15_SDS (0x0000F000u) +#define DMAC_CHCFG_15_SDS_SHIFT (12u) +#define DMAC_CHCFG_15_DDS (0x000F0000u) +#define DMAC_CHCFG_15_DDS_SHIFT (16u) +#define DMAC_CHCFG_15_SAD (0x00100000u) +#define DMAC_CHCFG_15_SAD_SHIFT (20u) +#define DMAC_CHCFG_15_DAD (0x00200000u) +#define DMAC_CHCFG_15_DAD_SHIFT (21u) +#define DMAC_CHCFG_15_TM (0x00400000u) +#define DMAC_CHCFG_15_TM_SHIFT (22u) +#define DMAC_CHCFG_15_DEM (0x01000000u) +#define DMAC_CHCFG_15_DEM_SHIFT (24u) +#define DMAC_CHCFG_15_SBE (0x08000000u) +#define DMAC_CHCFG_15_SBE_SHIFT (27u) +#define DMAC_CHCFG_15_RSEL (0x10000000u) +#define DMAC_CHCFG_15_RSEL_SHIFT (28u) +#define DMAC_CHCFG_15_RSW (0x20000000u) +#define DMAC_CHCFG_15_RSW_SHIFT (29u) +#define DMAC_CHCFG_15_REN (0x40000000u) +#define DMAC_CHCFG_15_REN_SHIFT (30u) +#define DMAC_CHCFG_15_DMS (0x80000000u) +#define DMAC_CHCFG_15_DMS_SHIFT (31u) +#define DMAC_CHITVL_15_ITVL (0x0000FFFFu) +#define DMAC_CHITVL_15_ITVL_SHIFT (0u) +#define DMAC_CHEXT_15_SPR (0x00000007u) +#define DMAC_CHEXT_15_SPR_SHIFT (0u) +#define DMAC_CHEXT_15_SCA (0x000000F0u) +#define DMAC_CHEXT_15_SCA_SHIFT (4u) +#define DMAC_CHEXT_15_DPR (0x00000700u) +#define DMAC_CHEXT_15_DPR_SHIFT (8u) +#define DMAC_CHEXT_15_DCA (0x0000F000u) +#define DMAC_CHEXT_15_DCA_SHIFT (12u) +#define DMAC_NXLA_15_NXLA (0xFFFFFFFFu) +#define DMAC_NXLA_15_NXLA_SHIFT (0u) +#define DMAC_CRLA_15_CRLA (0xFFFFFFFFu) +#define DMAC_CRLA_15_CRLA_SHIFT (0u) +#define DMAC_DCTRL_8_15_PR (0x00000001u) +#define DMAC_DCTRL_8_15_PR_SHIFT (0u) +#define DMAC_DCTRL_8_15_LVINT (0x00000002u) +#define DMAC_DCTRL_8_15_LVINT_SHIFT (1u) +#define DMAC_DCTRL_8_15_LDPR (0x00070000u) +#define DMAC_DCTRL_8_15_LDPR_SHIFT (16u) +#define DMAC_DCTRL_8_15_LDCA (0x00F00000u) +#define DMAC_DCTRL_8_15_LDCA_SHIFT (20u) +#define DMAC_DCTRL_8_15_LWPR (0x07000000u) +#define DMAC_DCTRL_8_15_LWPR_SHIFT (24u) +#define DMAC_DCTRL_8_15_LWCA (0xF0000000u) +#define DMAC_DCTRL_8_15_LWCA_SHIFT (28u) +#define DMAC_DSTAT_EN_8_15_EN8 (0x00000001u) +#define DMAC_DSTAT_EN_8_15_EN8_SHIFT (0u) +#define DMAC_DSTAT_EN_8_15_EN9 (0x00000002u) +#define DMAC_DSTAT_EN_8_15_EN9_SHIFT (1u) +#define DMAC_DSTAT_EN_8_15_EN10 (0x00000004u) +#define DMAC_DSTAT_EN_8_15_EN10_SHIFT (2u) +#define DMAC_DSTAT_EN_8_15_EN11 (0x00000008u) +#define DMAC_DSTAT_EN_8_15_EN11_SHIFT (3u) +#define DMAC_DSTAT_EN_8_15_EN12 (0x00000010u) +#define DMAC_DSTAT_EN_8_15_EN12_SHIFT (4u) +#define DMAC_DSTAT_EN_8_15_EN13 (0x00000020u) +#define DMAC_DSTAT_EN_8_15_EN13_SHIFT (5u) +#define DMAC_DSTAT_EN_8_15_EN14 (0x00000040u) +#define DMAC_DSTAT_EN_8_15_EN14_SHIFT (6u) +#define DMAC_DSTAT_EN_8_15_EN15 (0x00000080u) +#define DMAC_DSTAT_EN_8_15_EN15_SHIFT (7u) +#define DMAC_DSTAT_ER_8_15_ER8 (0x00000001u) +#define DMAC_DSTAT_ER_8_15_ER8_SHIFT (0u) +#define DMAC_DSTAT_ER_8_15_ER9 (0x00000002u) +#define DMAC_DSTAT_ER_8_15_ER9_SHIFT (1u) +#define DMAC_DSTAT_ER_8_15_ER10 (0x00000004u) +#define DMAC_DSTAT_ER_8_15_ER10_SHIFT (2u) +#define DMAC_DSTAT_ER_8_15_ER11 (0x00000008u) +#define DMAC_DSTAT_ER_8_15_ER11_SHIFT (3u) +#define DMAC_DSTAT_ER_8_15_ER12 (0x00000010u) +#define DMAC_DSTAT_ER_8_15_ER12_SHIFT (4u) +#define DMAC_DSTAT_ER_8_15_ER13 (0x00000020u) +#define DMAC_DSTAT_ER_8_15_ER13_SHIFT (5u) +#define DMAC_DSTAT_ER_8_15_ER14 (0x00000040u) +#define DMAC_DSTAT_ER_8_15_ER14_SHIFT (6u) +#define DMAC_DSTAT_ER_8_15_ER15 (0x00000080u) +#define DMAC_DSTAT_ER_8_15_ER15_SHIFT (7u) +#define DMAC_DSTAT_END_8_15_END8 (0x00000001u) +#define DMAC_DSTAT_END_8_15_END8_SHIFT (0u) +#define DMAC_DSTAT_END_8_15_END9 (0x00000002u) +#define DMAC_DSTAT_END_8_15_END9_SHIFT (1u) +#define DMAC_DSTAT_END_8_15_END10 (0x00000004u) +#define DMAC_DSTAT_END_8_15_END10_SHIFT (2u) +#define DMAC_DSTAT_END_8_15_END11 (0x00000008u) +#define DMAC_DSTAT_END_8_15_END11_SHIFT (3u) +#define DMAC_DSTAT_END_8_15_END12 (0x00000010u) +#define DMAC_DSTAT_END_8_15_END12_SHIFT (4u) +#define DMAC_DSTAT_END_8_15_END13 (0x00000020u) +#define DMAC_DSTAT_END_8_15_END13_SHIFT (5u) +#define DMAC_DSTAT_END_8_15_END14 (0x00000040u) +#define DMAC_DSTAT_END_8_15_END14_SHIFT (6u) +#define DMAC_DSTAT_END_8_15_END15 (0x00000080u) +#define DMAC_DSTAT_END_8_15_END15_SHIFT (7u) +#define DMAC_DSTAT_TC_8_15_TC8 (0x00000001u) +#define DMAC_DSTAT_TC_8_15_TC8_SHIFT (0u) +#define DMAC_DSTAT_TC_8_15_TC9 (0x00000002u) +#define DMAC_DSTAT_TC_8_15_TC9_SHIFT (1u) +#define DMAC_DSTAT_TC_8_15_TC10 (0x00000004u) +#define DMAC_DSTAT_TC_8_15_TC10_SHIFT (2u) +#define DMAC_DSTAT_TC_8_15_TC11 (0x00000008u) +#define DMAC_DSTAT_TC_8_15_TC11_SHIFT (3u) +#define DMAC_DSTAT_TC_8_15_TC12 (0x00000010u) +#define DMAC_DSTAT_TC_8_15_TC12_SHIFT (4u) +#define DMAC_DSTAT_TC_8_15_TC13 (0x00000020u) +#define DMAC_DSTAT_TC_8_15_TC13_SHIFT (5u) +#define DMAC_DSTAT_TC_8_15_TC14 (0x00000040u) +#define DMAC_DSTAT_TC_8_15_TC14_SHIFT (6u) +#define DMAC_DSTAT_TC_8_15_TC15 (0x00000080u) +#define DMAC_DSTAT_TC_8_15_TC15_SHIFT (7u) +#define DMAC_DSTAT_SUS_8_15_SUS8 (0x00000001u) +#define DMAC_DSTAT_SUS_8_15_SUS8_SHIFT (0u) +#define DMAC_DSTAT_SUS_8_15_SUS9 (0x00000002u) +#define DMAC_DSTAT_SUS_8_15_SUS9_SHIFT (1u) +#define DMAC_DSTAT_SUS_8_15_SUS10 (0x00000004u) +#define DMAC_DSTAT_SUS_8_15_SUS10_SHIFT (2u) +#define DMAC_DSTAT_SUS_8_15_SUS11 (0x00000008u) +#define DMAC_DSTAT_SUS_8_15_SUS11_SHIFT (3u) +#define DMAC_DSTAT_SUS_8_15_SUS12 (0x00000010u) +#define DMAC_DSTAT_SUS_8_15_SUS12_SHIFT (4u) +#define DMAC_DSTAT_SUS_8_15_SUS13 (0x00000020u) +#define DMAC_DSTAT_SUS_8_15_SUS13_SHIFT (5u) +#define DMAC_DSTAT_SUS_8_15_SUS14 (0x00000040u) +#define DMAC_DSTAT_SUS_8_15_SUS14_SHIFT (6u) +#define DMAC_DSTAT_SUS_8_15_SUS15 (0x00000080u) +#define DMAC_DSTAT_SUS_8_15_SUS15_SHIFT (7u) +#define DMAC_DMARS0_CH0_RID (0x00000003u) +#define DMAC_DMARS0_CH0_RID_SHIFT (0u) +#define DMAC_DMARS0_CH0_MID (0x000003FCu) +#define DMAC_DMARS0_CH0_MID_SHIFT (2u) +#define DMAC_DMARS0_CH1_RID (0x00030000u) +#define DMAC_DMARS0_CH1_RID_SHIFT (16u) +#define DMAC_DMARS0_CH1_MID (0x03FC0000u) +#define DMAC_DMARS0_CH1_MID_SHIFT (18u) +#define DMAC_DMARS1_CH2_RID (0x00000003u) +#define DMAC_DMARS1_CH2_RID_SHIFT (0u) +#define DMAC_DMARS1_CH2_MID (0x000003FCu) +#define DMAC_DMARS1_CH2_MID_SHIFT (2u) +#define DMAC_DMARS1_CH3_RID (0x00030000u) +#define DMAC_DMARS1_CH3_RID_SHIFT (16u) +#define DMAC_DMARS1_CH3_MID (0x03FC0000u) +#define DMAC_DMARS1_CH3_MID_SHIFT (18u) +#define DMAC_DMARS2_CH4_RID (0x00000003u) +#define DMAC_DMARS2_CH4_RID_SHIFT (0u) +#define DMAC_DMARS2_CH4_MID (0x000003FCu) +#define DMAC_DMARS2_CH4_MID_SHIFT (2u) +#define DMAC_DMARS2_CH5_RID (0x00030000u) +#define DMAC_DMARS2_CH5_RID_SHIFT (16u) +#define DMAC_DMARS2_CH5_MID (0x03FC0000u) +#define DMAC_DMARS2_CH5_MID_SHIFT (18u) +#define DMAC_DMARS3_CH6_RID (0x00000003u) +#define DMAC_DMARS3_CH6_RID_SHIFT (0u) +#define DMAC_DMARS3_CH6_MID (0x000003FCu) +#define DMAC_DMARS3_CH6_MID_SHIFT (2u) +#define DMAC_DMARS3_CH7_RID (0x00030000u) +#define DMAC_DMARS3_CH7_RID_SHIFT (16u) +#define DMAC_DMARS3_CH7_MID (0x03FC0000u) +#define DMAC_DMARS3_CH7_MID_SHIFT (18u) +#define DMAC_DMARS4_CH8_RID (0x00000003u) +#define DMAC_DMARS4_CH8_RID_SHIFT (0u) +#define DMAC_DMARS4_CH8_MID (0x000003FCu) +#define DMAC_DMARS4_CH8_MID_SHIFT (2u) +#define DMAC_DMARS4_CH9_RID (0x00030000u) +#define DMAC_DMARS4_CH9_RID_SHIFT (16u) +#define DMAC_DMARS4_CH9_MID (0x03FC0000u) +#define DMAC_DMARS4_CH9_MID_SHIFT (18u) +#define DMAC_DMARS5_CH10_RID (0x00000003u) +#define DMAC_DMARS5_CH10_RID_SHIFT (0u) +#define DMAC_DMARS5_CH10_MID (0x000003FCu) +#define DMAC_DMARS5_CH10_MID_SHIFT (2u) +#define DMAC_DMARS5_CH11_RID (0x00030000u) +#define DMAC_DMARS5_CH11_RID_SHIFT (16u) +#define DMAC_DMARS5_CH11_MID (0x03FC0000u) +#define DMAC_DMARS5_CH11_MID_SHIFT (18u) +#define DMAC_DMARS6_CH12_RID (0x00000003u) +#define DMAC_DMARS6_CH12_RID_SHIFT (0u) +#define DMAC_DMARS6_CH12_MID (0x000003FCu) +#define DMAC_DMARS6_CH12_MID_SHIFT (2u) +#define DMAC_DMARS6_CH13_RID (0x00030000u) +#define DMAC_DMARS6_CH13_RID_SHIFT (16u) +#define DMAC_DMARS6_CH13_MID (0x03FC0000u) +#define DMAC_DMARS6_CH13_MID_SHIFT (18u) +#define DMAC_DMARS7_CH14_RID (0x00000003u) +#define DMAC_DMARS7_CH14_RID_SHIFT (0u) +#define DMAC_DMARS7_CH14_MID (0x000003FCu) +#define DMAC_DMARS7_CH14_MID_SHIFT (2u) +#define DMAC_DMARS7_CH15_RID (0x00030000u) +#define DMAC_DMARS7_CH15_RID_SHIFT (16u) +#define DMAC_DMARS7_CH15_MID (0x03FC0000u) +#define DMAC_DMARS7_CH15_MID_SHIFT (18u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drpk_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drpk_iobitmask.h new file mode 100644 index 0000000..b846504 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drpk_iobitmask.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef DRPK_IOBITMASK_H +#define DRPK_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define DRPK_FIFODATA0_FIFODATA (0xFFFFFFFFu) +#define DRPK_FIFODATA0_FIFODATA_SHIFT (0u) +#define DRPK_FIFODATA1_FIFODATA (0xFFFFFFFFu) +#define DRPK_FIFODATA1_FIFODATA_SHIFT (0u) +#define DRPK_FIFODATA2_FIFODATA (0xFFFFFFFFu) +#define DRPK_FIFODATA2_FIFODATA_SHIFT (0u) +#define DRPK_FIFODATA3_FIFODATA (0xFFFFFFFFu) +#define DRPK_FIFODATA3_FIFODATA_SHIFT (0u) +#define DRPK_FIFODATA4_FIFODATA (0xFFFFFFFFu) +#define DRPK_FIFODATA4_FIFODATA_SHIFT (0u) +#define DRPK_FIFODATA5_FIFODATA (0xFFFFFFFFu) +#define DRPK_FIFODATA5_FIFODATA_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drw_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drw_iobitmask.h new file mode 100644 index 0000000..e46f877 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/drw_iobitmask.h @@ -0,0 +1,288 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef DRW_IOBITMASK_H +#define DRW_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define DRW_CONTROL_LIM1ENABLE (0x00000001u) +#define DRW_CONTROL_LIM1ENABLE_SHIFT (0u) +#define DRW_CONTROL_LIM2ENABLE (0x00000002u) +#define DRW_CONTROL_LIM2ENABLE_SHIFT (1u) +#define DRW_CONTROL_LIM3ENABLE (0x00000004u) +#define DRW_CONTROL_LIM3ENABLE_SHIFT (2u) +#define DRW_CONTROL_LIM4ENABLE (0x00000008u) +#define DRW_CONTROL_LIM4ENABLE_SHIFT (3u) +#define DRW_CONTROL_LIM5ENABLE (0x00000010u) +#define DRW_CONTROL_LIM5ENABLE_SHIFT (4u) +#define DRW_CONTROL_LIM6ENABLE (0x00000020u) +#define DRW_CONTROL_LIM6ENABLE_SHIFT (5u) +#define DRW_CONTROL_QUAD1ENABLE (0x00000040u) +#define DRW_CONTROL_QUAD1ENABLE_SHIFT (6u) +#define DRW_CONTROL_QUAD2ENABLE (0x00000080u) +#define DRW_CONTROL_QUAD2ENABLE_SHIFT (7u) +#define DRW_CONTROL_QUAD3ENABLE (0x00000100u) +#define DRW_CONTROL_QUAD3ENABLE_SHIFT (8u) +#define DRW_CONTROL_LIM1THRESHOLD (0x00000200u) +#define DRW_CONTROL_LIM1THRESHOLD_SHIFT (9u) +#define DRW_CONTROL_LIM2THRESHOLD (0x00000400u) +#define DRW_CONTROL_LIM2THRESHOLD_SHIFT (10u) +#define DRW_CONTROL_LIM3THRESHOLD (0x00000800u) +#define DRW_CONTROL_LIM3THRESHOLD_SHIFT (11u) +#define DRW_CONTROL_LIM4THRESHOLD (0x00001000u) +#define DRW_CONTROL_LIM4THRESHOLD_SHIFT (12u) +#define DRW_CONTROL_LIM5THRESHOLD (0x00002000u) +#define DRW_CONTROL_LIM5THRESHOLD_SHIFT (13u) +#define DRW_CONTROL_LIM6THRESHOLD (0x00004000u) +#define DRW_CONTROL_LIM6THRESHOLD_SHIFT (14u) +#define DRW_CONTROL_BAND1ENABLE (0x00008000u) +#define DRW_CONTROL_BAND1ENABLE_SHIFT (15u) +#define DRW_CONTROL_BAND2ENABLE (0x00010000u) +#define DRW_CONTROL_BAND2ENABLE_SHIFT (16u) +#define DRW_CONTROL_UNION12 (0x00020000u) +#define DRW_CONTROL_UNION12_SHIFT (17u) +#define DRW_CONTROL_UNION34 (0x00040000u) +#define DRW_CONTROL_UNION34_SHIFT (18u) +#define DRW_CONTROL_UNION56 (0x00080000u) +#define DRW_CONTROL_UNION56_SHIFT (19u) +#define DRW_CONTROL_UNIONAB (0x00100000u) +#define DRW_CONTROL_UNIONAB_SHIFT (20u) +#define DRW_CONTROL_UNIONCD (0x00200000u) +#define DRW_CONTROL_UNIONCD_SHIFT (21u) +#define DRW_CONTROL_SPANABORT (0x00400000u) +#define DRW_CONTROL_SPANABORT_SHIFT (22u) +#define DRW_CONTROL_SPANSTORE (0x00800000u) +#define DRW_CONTROL_SPANSTORE_SHIFT (23u) +#define DRW_CONTROL2_PATTERNENABLE (0x00000001u) +#define DRW_CONTROL2_PATTERNENABLE_SHIFT (0u) +#define DRW_CONTROL2_TEXTUREENABLE (0x00000002u) +#define DRW_CONTROL2_TEXTUREENABLE_SHIFT (1u) +#define DRW_CONTROL2_PATTERNSOURCEL5 (0x00000004u) +#define DRW_CONTROL2_PATTERNSOURCEL5_SHIFT (2u) +#define DRW_CONTROL2_USEACB (0x00000008u) +#define DRW_CONTROL2_USEACB_SHIFT (3u) +#define DRW_CONTROL2_READFORMAT_3_2 (0x00000030u) +#define DRW_CONTROL2_READFORMAT_3_2_SHIFT (4u) +#define DRW_CONTROL2_BSFA (0x00000040u) +#define DRW_CONTROL2_BSFA_SHIFT (6u) +#define DRW_CONTROL2_BDFA (0x00000080u) +#define DRW_CONTROL2_BDFA_SHIFT (7u) +#define DRW_CONTROL2_WRITEFORMAT_2 (0x00000100u) +#define DRW_CONTROL2_WRITEFORMAT_2_SHIFT (8u) +#define DRW_CONTROL2_BSF (0x00000200u) +#define DRW_CONTROL2_BSF_SHIFT (9u) +#define DRW_CONTROL2_BDF (0x00000400u) +#define DRW_CONTROL2_BDF_SHIFT (10u) +#define DRW_CONTROL2_BSI (0x00000800u) +#define DRW_CONTROL2_BSI_SHIFT (11u) +#define DRW_CONTROL2_BDI (0x00001000u) +#define DRW_CONTROL2_BDI_SHIFT (12u) +#define DRW_CONTROL2_BC2 (0x00002000u) +#define DRW_CONTROL2_BC2_SHIFT (13u) +#define DRW_CONTROL2_TEXTURECLAMPX (0x00004000u) +#define DRW_CONTROL2_TEXTURECLAMPX_SHIFT (14u) +#define DRW_CONTROL2_TEXTURECLAMPY (0x00008000u) +#define DRW_CONTROL2_TEXTURECLAMPY_SHIFT (15u) +#define DRW_CONTROL2_TEXTUREFILTERX (0x00010000u) +#define DRW_CONTROL2_TEXTUREFILTERX_SHIFT (16u) +#define DRW_CONTROL2_TEXTUREFILTERY (0x00020000u) +#define DRW_CONTROL2_TEXTUREFILTERY_SHIFT (17u) +#define DRW_CONTROL2_READFORMAT_1_0 (0x000C0000u) +#define DRW_CONTROL2_READFORMAT_1_0_SHIFT (18u) +#define DRW_CONTROL2_WRITEFORMAT_1_0 (0x00300000u) +#define DRW_CONTROL2_WRITEFORMAT_1_0_SHIFT (20u) +#define DRW_CONTROL2_WRITEALPHA (0x00C00000u) +#define DRW_CONTROL2_WRITEALPHA_SHIFT (22u) +#define DRW_CONTROL2_RLEENABLE (0x01000000u) +#define DRW_CONTROL2_RLEENABLE_SHIFT (24u) +#define DRW_CONTROL2_CLUTENABLE (0x02000000u) +#define DRW_CONTROL2_CLUTENABLE_SHIFT (25u) +#define DRW_CONTROL2_COLKEYENABLE (0x04000000u) +#define DRW_CONTROL2_COLKEYENABLE_SHIFT (26u) +#define DRW_CONTROL2_CLUTFORMAT (0x08000000u) +#define DRW_CONTROL2_CLUTFORMAT_SHIFT (27u) +#define DRW_CONTROL2_BSIA (0x10000000u) +#define DRW_CONTROL2_BSIA_SHIFT (28u) +#define DRW_CONTROL2_BDIA (0x20000000u) +#define DRW_CONTROL2_BDIA_SHIFT (29u) +#define DRW_CONTROL2_RLEPIXELWIDTH (0xC0000000u) +#define DRW_CONTROL2_RLEPIXELWIDTH_SHIFT (30u) +#define DRW_L1START_LSTART (0xFFFFFFFFu) +#define DRW_L1START_LSTART_SHIFT (0u) +#define DRW_L2START_LSTART (0xFFFFFFFFu) +#define DRW_L2START_LSTART_SHIFT (0u) +#define DRW_L3START_LSTART (0xFFFFFFFFu) +#define DRW_L3START_LSTART_SHIFT (0u) +#define DRW_L4START_LSTART (0xFFFFFFFFu) +#define DRW_L4START_LSTART_SHIFT (0u) +#define DRW_L5START_LSTART (0xFFFFFFFFu) +#define DRW_L5START_LSTART_SHIFT (0u) +#define DRW_L6START_LSTART (0xFFFFFFFFu) +#define DRW_L6START_LSTART_SHIFT (0u) +#define DRW_L1XADD_LXADD (0xFFFFFFFFu) +#define DRW_L1XADD_LXADD_SHIFT (0u) +#define DRW_L2XADD_LXADD (0xFFFFFFFFu) +#define DRW_L2XADD_LXADD_SHIFT (0u) +#define DRW_L3XADD_LXADD (0xFFFFFFFFu) +#define DRW_L3XADD_LXADD_SHIFT (0u) +#define DRW_L4XADD_LXADD (0xFFFFFFFFu) +#define DRW_L4XADD_LXADD_SHIFT (0u) +#define DRW_L5XADD_LXADD (0xFFFFFFFFu) +#define DRW_L5XADD_LXADD_SHIFT (0u) +#define DRW_L6XADD_LXADD (0xFFFFFFFFu) +#define DRW_L6XADD_LXADD_SHIFT (0u) +#define DRW_L1YADD_LYADD (0xFFFFFFFFu) +#define DRW_L1YADD_LYADD_SHIFT (0u) +#define DRW_L2YADD_LYADD (0xFFFFFFFFu) +#define DRW_L2YADD_LYADD_SHIFT (0u) +#define DRW_L3YADD_LYADD (0xFFFFFFFFu) +#define DRW_L3YADD_LYADD_SHIFT (0u) +#define DRW_L4YADD_LYADD (0xFFFFFFFFu) +#define DRW_L4YADD_LYADD_SHIFT (0u) +#define DRW_L5YADD_LYADD (0xFFFFFFFFu) +#define DRW_L5YADD_LYADD_SHIFT (0u) +#define DRW_L6YADD_LYADD (0xFFFFFFFFu) +#define DRW_L6YADD_LYADD_SHIFT (0u) +#define DRW_L1BAND_LBAND (0xFFFFFFFFu) +#define DRW_L1BAND_LBAND_SHIFT (0u) +#define DRW_L2BAND_LBAND (0xFFFFFFFFu) +#define DRW_L2BAND_LBAND_SHIFT (0u) +#define DRW_COLOR1_COLOR1B (0x000000FFu) +#define DRW_COLOR1_COLOR1B_SHIFT (0u) +#define DRW_COLOR1_COLOR1G (0x0000FF00u) +#define DRW_COLOR1_COLOR1G_SHIFT (8u) +#define DRW_COLOR1_COLOR1R (0x00FF0000u) +#define DRW_COLOR1_COLOR1R_SHIFT (16u) +#define DRW_COLOR1_COLOR1A (0xFF000000u) +#define DRW_COLOR1_COLOR1A_SHIFT (24u) +#define DRW_COLOR2_COLOR2B (0x000000FFu) +#define DRW_COLOR2_COLOR2B_SHIFT (0u) +#define DRW_COLOR2_COLOR2G (0x0000FF00u) +#define DRW_COLOR2_COLOR2G_SHIFT (8u) +#define DRW_COLOR2_COLOR2R (0x00FF0000u) +#define DRW_COLOR2_COLOR2R_SHIFT (16u) +#define DRW_COLOR2_COLOR2A (0xFF000000u) +#define DRW_COLOR2_COLOR2A_SHIFT (24u) +#define DRW_PATTERN_PATTERN (0x000000FFu) +#define DRW_PATTERN_PATTERN_SHIFT (0u) +#define DRW_SIZE_SIZEX (0x0000FFFFu) +#define DRW_SIZE_SIZEX_SHIFT (0u) +#define DRW_SIZE_SIZEY (0xFFFF0000u) +#define DRW_SIZE_SIZEY_SHIFT (16u) +#define DRW_PITCH_PITCH (0x0000FFFFu) +#define DRW_PITCH_PITCH_SHIFT (0u) +#define DRW_PITCH_SSD (0xFFFF0000u) +#define DRW_PITCH_SSD_SHIFT (16u) +#define DRW_ORIGIN_ORIGIN (0xFFFFFFFFu) +#define DRW_ORIGIN_ORIGIN_SHIFT (0u) +#define DRW_LUSTART_LUSTART (0xFFFFFFFFu) +#define DRW_LUSTART_LUSTART_SHIFT (0u) +#define DRW_LUXADD_LUXADD (0xFFFFFFFFu) +#define DRW_LUXADD_LUXADD_SHIFT (0u) +#define DRW_LUYADD_LUYADD (0xFFFFFFFFu) +#define DRW_LUYADD_LUYADD_SHIFT (0u) +#define DRW_LVSTARTI_LVSTARTI (0xFFFFFFFFu) +#define DRW_LVSTARTI_LVSTARTI_SHIFT (0u) +#define DRW_LVSTARTF_LVSTARTF (0x0000FFFFu) +#define DRW_LVSTARTF_LVSTARTF_SHIFT (0u) +#define DRW_LVXADDI_LVXADDI (0xFFFFFFFFu) +#define DRW_LVXADDI_LVXADDI_SHIFT (0u) +#define DRW_LVYADDI_LVYADDI (0xFFFFFFFFu) +#define DRW_LVYADDI_LVYADDI_SHIFT (0u) +#define DRW_LVYXADDF_LVXADDF (0x0000FFFFu) +#define DRW_LVYXADDF_LVXADDF_SHIFT (0u) +#define DRW_LVYXADDF_LVYADDF (0xFFFF0000u) +#define DRW_LVYXADDF_LVYADDF_SHIFT (16u) +#define DRW_TEXPITCH_TEXPITCH (0x000007FFu) +#define DRW_TEXPITCH_TEXPITCH_SHIFT (0u) +#define DRW_TEXMASK_TEXUMASK (0x000007FFu) +#define DRW_TEXMASK_TEXUMASK_SHIFT (0u) +#define DRW_TEXMASK_TEXVMASK (0xFFFFF800u) +#define DRW_TEXMASK_TEXVMASK_SHIFT (11u) +#define DRW_TEXORIGIN_TEXORIGIN (0xFFFFFFFFu) +#define DRW_TEXORIGIN_TEXORIGIN_SHIFT (0u) +#define DRW_IRQCTL_ENUMIRQEN (0x00000001u) +#define DRW_IRQCTL_ENUMIRQEN_SHIFT (0u) +#define DRW_IRQCTL_DLISTIRQEN (0x00000002u) +#define DRW_IRQCTL_DLISTIRQEN_SHIFT (1u) +#define DRW_IRQCTL_ENUMIRQCLR (0x00000004u) +#define DRW_IRQCTL_ENUMIRQCLR_SHIFT (2u) +#define DRW_IRQCTL_DLISTIRQCLR (0x00000008u) +#define DRW_IRQCTL_DLISTIRQCLR_SHIFT (3u) +#define DRW_IRQCTL_BUSIRQEN (0x00000010u) +#define DRW_IRQCTL_BUSIRQEN_SHIFT (4u) +#define DRW_IRQCTL_BUSIRQCLR (0x00000020u) +#define DRW_IRQCTL_BUSIRQCLR_SHIFT (5u) +#define DRW_CACHECTL_CENABLEFX (0x00000001u) +#define DRW_CACHECTL_CENABLEFX_SHIFT (0u) +#define DRW_CACHECTL_CFLUSHFX (0x00000002u) +#define DRW_CACHECTL_CFLUSHFX_SHIFT (1u) +#define DRW_CACHECTL_CENABLETX (0x00000004u) +#define DRW_CACHECTL_CENABLETX_SHIFT (2u) +#define DRW_CACHECTL_CFLUSHTX (0x00000008u) +#define DRW_CACHECTL_CFLUSHTX_SHIFT (3u) +#define DRW_DLISTSTART_DLISTSTART (0xFFFFFFFFu) +#define DRW_DLISTSTART_DLISTSTART_SHIFT (0u) +#define DRW_PERFCOUNT1_PERFCOUNT (0xFFFFFFFFu) +#define DRW_PERFCOUNT1_PERFCOUNT_SHIFT (0u) +#define DRW_PERFCOUNT2_PERFCOUNT (0xFFFFFFFFu) +#define DRW_PERFCOUNT2_PERFCOUNT_SHIFT (0u) +#define DRW_PERFTRIGGER_PERFTRIGGER1 (0x0000001Fu) +#define DRW_PERFTRIGGER_PERFTRIGGER1_SHIFT (0u) +#define DRW_PERFTRIGGER_PERFTRIGGER2 (0x001F0000u) +#define DRW_PERFTRIGGER_PERFTRIGGER2_SHIFT (16u) +#define DRW_TEXCLADDR_CLADDR (0x000000FFu) +#define DRW_TEXCLADDR_CLADDR_SHIFT (0u) +#define DRW_TEXCLDATA_CLDATA (0xFFFFFFFFu) +#define DRW_TEXCLDATA_CLDATA_SHIFT (0u) +#define DRW_TEXCLOFFSET_CLOFFSET (0x000000FFu) +#define DRW_TEXCLOFFSET_CLOFFSET_SHIFT (0u) +#define DRW_COLKEY_COLKEYB (0x000000FFu) +#define DRW_COLKEY_COLKEYB_SHIFT (0u) +#define DRW_COLKEY_COLKEYG (0x0000FF00u) +#define DRW_COLKEY_COLKEYG_SHIFT (8u) +#define DRW_COLKEY_COLKEYR (0x00FF0000u) +#define DRW_COLKEY_COLKEYR_SHIFT (16u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/edmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/edmac_iobitmask.h new file mode 100644 index 0000000..c234b54 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/edmac_iobitmask.h @@ -0,0 +1,188 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef EDMAC_IOBITMASK_H +#define EDMAC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define EDMAC_EDMR_SWR (0x00000001u) +#define EDMAC_EDMR_SWR_SHIFT (0u) +#define EDMAC_EDMR_DL (0x00000030u) +#define EDMAC_EDMR_DL_SHIFT (4u) +#define EDMAC_EDMR_DE (0x00000040u) +#define EDMAC_EDMR_DE_SHIFT (6u) +#define EDMAC_EDTRR_TR (0x00000001u) +#define EDMAC_EDTRR_TR_SHIFT (0u) +#define EDMAC_EDRRR_RR (0x00000001u) +#define EDMAC_EDRRR_RR_SHIFT (0u) +#define EDMAC_TDLAR_TDLAR (0xFFFFFFFFu) +#define EDMAC_TDLAR_TDLAR_SHIFT (0u) +#define EDMAC_RDLAR_RDLAR (0xFFFFFFFFu) +#define EDMAC_RDLAR_RDLAR_SHIFT (0u) +#define EDMAC_EESR_CERF (0x00000001u) +#define EDMAC_EESR_CERF_SHIFT (0u) +#define EDMAC_EESR_PRE (0x00000002u) +#define EDMAC_EESR_PRE_SHIFT (1u) +#define EDMAC_EESR_RTSF (0x00000004u) +#define EDMAC_EESR_RTSF_SHIFT (2u) +#define EDMAC_EESR_RTLF (0x00000008u) +#define EDMAC_EESR_RTLF_SHIFT (3u) +#define EDMAC_EESR_RRF (0x00000010u) +#define EDMAC_EESR_RRF_SHIFT (4u) +#define EDMAC_EESR_RMAF (0x00000080u) +#define EDMAC_EESR_RMAF_SHIFT (7u) +#define EDMAC_EESR_TRO (0x00000100u) +#define EDMAC_EESR_TRO_SHIFT (8u) +#define EDMAC_EESR_CD (0x00000200u) +#define EDMAC_EESR_CD_SHIFT (9u) +#define EDMAC_EESR_DLC (0x00000400u) +#define EDMAC_EESR_DLC_SHIFT (10u) +#define EDMAC_EESR_CND (0x00000800u) +#define EDMAC_EESR_CND_SHIFT (11u) +#define EDMAC_EESR_RFOF (0x00010000u) +#define EDMAC_EESR_RFOF_SHIFT (16u) +#define EDMAC_EESR_RDE (0x00020000u) +#define EDMAC_EESR_RDE_SHIFT (17u) +#define EDMAC_EESR_FR (0x00040000u) +#define EDMAC_EESR_FR_SHIFT (18u) +#define EDMAC_EESR_TFUF (0x00080000u) +#define EDMAC_EESR_TFUF_SHIFT (19u) +#define EDMAC_EESR_TDE (0x00100000u) +#define EDMAC_EESR_TDE_SHIFT (20u) +#define EDMAC_EESR_TC (0x00200000u) +#define EDMAC_EESR_TC_SHIFT (21u) +#define EDMAC_EESR_ECI (0x00400000u) +#define EDMAC_EESR_ECI_SHIFT (22u) +#define EDMAC_EESR_RFCOF (0x01000000u) +#define EDMAC_EESR_RFCOF_SHIFT (24u) +#define EDMAC_EESR_RABT (0x02000000u) +#define EDMAC_EESR_RABT_SHIFT (25u) +#define EDMAC_EESR_TABT (0x04000000u) +#define EDMAC_EESR_TABT_SHIFT (26u) +#define EDMAC_EESR_TWB (0x40000000u) +#define EDMAC_EESR_TWB_SHIFT (30u) +#define EDMAC_EESIPR_CERFIP (0x00000001u) +#define EDMAC_EESIPR_CERFIP_SHIFT (0u) +#define EDMAC_EESIPR_PREIP (0x00000002u) +#define EDMAC_EESIPR_PREIP_SHIFT (1u) +#define EDMAC_EESIPR_RTSFIP (0x00000004u) +#define EDMAC_EESIPR_RTSFIP_SHIFT (2u) +#define EDMAC_EESIPR_RTLFIP (0x00000008u) +#define EDMAC_EESIPR_RTLFIP_SHIFT (3u) +#define EDMAC_EESIPR_RRFIP (0x00000010u) +#define EDMAC_EESIPR_RRFIP_SHIFT (4u) +#define EDMAC_EESIPR_RMAFIP (0x00000080u) +#define EDMAC_EESIPR_RMAFIP_SHIFT (7u) +#define EDMAC_EESIPR_TROIP (0x00000100u) +#define EDMAC_EESIPR_TROIP_SHIFT (8u) +#define EDMAC_EESIPR_CDIP (0x00000200u) +#define EDMAC_EESIPR_CDIP_SHIFT (9u) +#define EDMAC_EESIPR_DLCIP (0x00000400u) +#define EDMAC_EESIPR_DLCIP_SHIFT (10u) +#define EDMAC_EESIPR_CNDIP (0x00000800u) +#define EDMAC_EESIPR_CNDIP_SHIFT (11u) +#define EDMAC_EESIPR_RFOFIP (0x00010000u) +#define EDMAC_EESIPR_RFOFIP_SHIFT (16u) +#define EDMAC_EESIPR_RDEIP (0x00020000u) +#define EDMAC_EESIPR_RDEIP_SHIFT (17u) +#define EDMAC_EESIPR_FRIP (0x00040000u) +#define EDMAC_EESIPR_FRIP_SHIFT (18u) +#define EDMAC_EESIPR_TFUFIP (0x00080000u) +#define EDMAC_EESIPR_TFUFIP_SHIFT (19u) +#define EDMAC_EESIPR_TDEIP (0x00100000u) +#define EDMAC_EESIPR_TDEIP_SHIFT (20u) +#define EDMAC_EESIPR_TCIP (0x00200000u) +#define EDMAC_EESIPR_TCIP_SHIFT (21u) +#define EDMAC_EESIPR_ECIIP (0x00400000u) +#define EDMAC_EESIPR_ECIIP_SHIFT (22u) +#define EDMAC_EESIPR_RFCOFIP (0x01000000u) +#define EDMAC_EESIPR_RFCOFIP_SHIFT (24u) +#define EDMAC_EESIPR_RABTIP (0x02000000u) +#define EDMAC_EESIPR_RABTIP_SHIFT (25u) +#define EDMAC_EESIPR_TABTIP (0x04000000u) +#define EDMAC_EESIPR_TABTIP_SHIFT (26u) +#define EDMAC_EESIPR_TWBIP (0x40000000u) +#define EDMAC_EESIPR_TWBIP_SHIFT (30u) +#define EDMAC_TRSCER_RRFCE (0x00000010u) +#define EDMAC_TRSCER_RRFCE_SHIFT (4u) +#define EDMAC_TRSCER_RMAFCE (0x00000080u) +#define EDMAC_TRSCER_RMAFCE_SHIFT (7u) +#define EDMAC_RMFCR_MFC (0x0000FFFFu) +#define EDMAC_RMFCR_MFC_SHIFT (0u) +#define EDMAC_TFTR_TFT (0x000007FFu) +#define EDMAC_TFTR_TFT_SHIFT (0u) +#define EDMAC_FDR_RFD (0x0000001Fu) +#define EDMAC_FDR_RFD_SHIFT (0u) +#define EDMAC_FDR_TFD (0x00001F00u) +#define EDMAC_FDR_TFD_SHIFT (8u) +#define EDMAC_RMCR_RNR (0x00000001u) +#define EDMAC_RMCR_RNR_SHIFT (0u) +#define EDMAC_TFUCR_UNDER (0x0000FFFFu) +#define EDMAC_TFUCR_UNDER_SHIFT (0u) +#define EDMAC_RFOCR_OVER (0x0000FFFFu) +#define EDMAC_RFOCR_OVER_SHIFT (0u) +#define EDMAC_IOSR_ELB (0x00000001u) +#define EDMAC_IOSR_ELB_SHIFT (0u) +#define EDMAC_FCFTR_RFDO (0x00000007u) +#define EDMAC_FCFTR_RFDO_SHIFT (0u) +#define EDMAC_FCFTR_RFFO (0x00070000u) +#define EDMAC_FCFTR_RFFO_SHIFT (16u) +#define EDMAC_RPADIR_PADR (0x0000003Fu) +#define EDMAC_RPADIR_PADR_SHIFT (0u) +#define EDMAC_RPADIR_PADS (0x00030000u) +#define EDMAC_RPADIR_PADS_SHIFT (16u) +#define EDMAC_TRIMD_TIS (0x00000001u) +#define EDMAC_TRIMD_TIS_SHIFT (0u) +#define EDMAC_TRIMD_TIM (0x00000010u) +#define EDMAC_TRIMD_TIM_SHIFT (4u) +#define EDMAC_RBWAR_RBWAR (0xFFFFFFFFu) +#define EDMAC_RBWAR_RBWAR_SHIFT (0u) +#define EDMAC_RDFAR_RDFAR (0xFFFFFFFFu) +#define EDMAC_RDFAR_RDFAR_SHIFT (0u) +#define EDMAC_TBRAR_TBRAR (0xFFFFFFFFu) +#define EDMAC_TBRAR_TBRAR_SHIFT (0u) +#define EDMAC_TDFAR_TDFAR (0xFFFFFFFFu) +#define EDMAC_TDFAR_TDFAR_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/eptpc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/eptpc_iobitmask.h new file mode 100644 index 0000000..d1cfeae --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/eptpc_iobitmask.h @@ -0,0 +1,568 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef EPTPC_IOBITMASK_H +#define EPTPC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define EPTPC_PTRSTR_RESET (0x00000001u) +#define EPTPC_PTRSTR_RESET_SHIFT (0u) +#define EPTPC_STCSELR_SCLKSEL (0x00000700u) +#define EPTPC_STCSELR_SCLKSEL_SHIFT (8u) +#define EPTPC_BYPASS_BYPASS0 (0x00000001u) +#define EPTPC_BYPASS_BYPASS0_SHIFT (0u) +#define EPTPC_BYPASS_BYPASS1 (0x00010000u) +#define EPTPC_BYPASS_BYPASS1_SHIFT (16u) +#define EPTPC_MIESR_ST (0x00000001u) +#define EPTPC_MIESR_ST_SHIFT (0u) +#define EPTPC_MIESR_SY0 (0x00000002u) +#define EPTPC_MIESR_SY0_SHIFT (1u) +#define EPTPC_MIESR_SY1 (0x00000004u) +#define EPTPC_MIESR_SY1_SHIFT (2u) +#define EPTPC_MIESR_PRC (0x00000008u) +#define EPTPC_MIESR_PRC_SHIFT (3u) +#define EPTPC_MIESR_CYC0 (0x00010000u) +#define EPTPC_MIESR_CYC0_SHIFT (16u) +#define EPTPC_MIESR_CYC1 (0x00020000u) +#define EPTPC_MIESR_CYC1_SHIFT (17u) +#define EPTPC_MIESR_CYC2 (0x00040000u) +#define EPTPC_MIESR_CYC2_SHIFT (18u) +#define EPTPC_MIESR_CYC3 (0x00080000u) +#define EPTPC_MIESR_CYC3_SHIFT (19u) +#define EPTPC_MIESR_CYC4 (0x00100000u) +#define EPTPC_MIESR_CYC4_SHIFT (20u) +#define EPTPC_MIESR_CYC5 (0x00200000u) +#define EPTPC_MIESR_CYC5_SHIFT (21u) +#define EPTPC_MIEIPR_ST (0x00000001u) +#define EPTPC_MIEIPR_ST_SHIFT (0u) +#define EPTPC_MIEIPR_SY0 (0x00000002u) +#define EPTPC_MIEIPR_SY0_SHIFT (1u) +#define EPTPC_MIEIPR_SY1 (0x00000004u) +#define EPTPC_MIEIPR_SY1_SHIFT (2u) +#define EPTPC_MIEIPR_PR (0x00000008u) +#define EPTPC_MIEIPR_PR_SHIFT (3u) +#define EPTPC_MIEIPR_CYC0 (0x00010000u) +#define EPTPC_MIEIPR_CYC0_SHIFT (16u) +#define EPTPC_MIEIPR_CYC1 (0x00020000u) +#define EPTPC_MIEIPR_CYC1_SHIFT (17u) +#define EPTPC_MIEIPR_CYC2 (0x00040000u) +#define EPTPC_MIEIPR_CYC2_SHIFT (18u) +#define EPTPC_MIEIPR_CYC3 (0x00080000u) +#define EPTPC_MIEIPR_CYC3_SHIFT (19u) +#define EPTPC_MIEIPR_CYC4 (0x00100000u) +#define EPTPC_MIEIPR_CYC4_SHIFT (20u) +#define EPTPC_MIEIPR_CYC5 (0x00200000u) +#define EPTPC_MIEIPR_CYC5_SHIFT (21u) +#define EPTPC_ELIPPR_PLSP (0x00010000u) +#define EPTPC_ELIPPR_PLSP_SHIFT (16u) +#define EPTPC_ELIPPR_PLSN (0x01000000u) +#define EPTPC_ELIPPR_PLSN_SHIFT (24u) +#define EPTPC_ELIPACR_PLSP (0x00010000u) +#define EPTPC_ELIPACR_PLSP_SHIFT (16u) +#define EPTPC_ELIPACR_PLSN (0x01000000u) +#define EPTPC_ELIPACR_PLSN_SHIFT (24u) +#define EPTPC_STSR_SYNC (0x00000001u) +#define EPTPC_STSR_SYNC_SHIFT (0u) +#define EPTPC_STSR_SYNCOUT (0x00000002u) +#define EPTPC_STSR_SYNCOUT_SHIFT (1u) +#define EPTPC_STSR_SYNTOUT (0x00000008u) +#define EPTPC_STSR_SYNTOUT_SHIFT (3u) +#define EPTPC_STSR_W10D (0x00000010u) +#define EPTPC_STSR_W10D_SHIFT (4u) +#define EPTPC_STIPR_SYNC (0x00000001u) +#define EPTPC_STIPR_SYNC_SHIFT (0u) +#define EPTPC_STIPR_SYNCOUT (0x00000002u) +#define EPTPC_STIPR_SYNCOUT_SHIFT (1u) +#define EPTPC_STIPR_SYNTOUT (0x00000008u) +#define EPTPC_STIPR_SYNTOUT_SHIFT (3u) +#define EPTPC_STIPR_W10D (0x00000010u) +#define EPTPC_STIPR_W10D_SHIFT (4u) +#define EPTPC_STCFR_STCF (0x00000003u) +#define EPTPC_STCFR_STCF_SHIFT (0u) +#define EPTPC_STMR_WINT (0x000000FFu) +#define EPTPC_STMR_WINT_SHIFT (0u) +#define EPTPC_STMR_CMOD (0x00002000u) +#define EPTPC_STMR_CMOD_SHIFT (13u) +#define EPTPC_STMR_W10S (0x00008000u) +#define EPTPC_STMR_W10S_SHIFT (15u) +#define EPTPC_STMR_SYTH (0x000F0000u) +#define EPTPC_STMR_SYTH_SHIFT (16u) +#define EPTPC_STMR_DVTH (0x00F00000u) +#define EPTPC_STMR_DVTH_SHIFT (20u) +#define EPTPC_STMR_ALEN0 (0x10000000u) +#define EPTPC_STMR_ALEN0_SHIFT (28u) +#define EPTPC_STMR_ALEN1 (0x20000000u) +#define EPTPC_STMR_ALEN1_SHIFT (29u) +#define EPTPC_SYNTOR_SYNTOR (0xFFFFFFFFu) +#define EPTPC_SYNTOR_SYNTOR_SHIFT (0u) +#define EPTPC_IPTSELR_IPTSEL0 (0x00000001u) +#define EPTPC_IPTSELR_IPTSEL0_SHIFT (0u) +#define EPTPC_IPTSELR_IPTSEL1 (0x00000002u) +#define EPTPC_IPTSELR_IPTSEL1_SHIFT (1u) +#define EPTPC_IPTSELR_IPTSEL2 (0x00000004u) +#define EPTPC_IPTSELR_IPTSEL2_SHIFT (2u) +#define EPTPC_IPTSELR_IPTSEL3 (0x00000008u) +#define EPTPC_IPTSELR_IPTSEL3_SHIFT (3u) +#define EPTPC_IPTSELR_IPTSEL4 (0x00000010u) +#define EPTPC_IPTSELR_IPTSEL4_SHIFT (4u) +#define EPTPC_IPTSELR_IPTSEL5 (0x00000020u) +#define EPTPC_IPTSELR_IPTSEL5_SHIFT (5u) +#define EPTPC_MITSELR_MINTEN0 (0x00000001u) +#define EPTPC_MITSELR_MINTEN0_SHIFT (0u) +#define EPTPC_MITSELR_MINTEN1 (0x00000002u) +#define EPTPC_MITSELR_MINTEN1_SHIFT (1u) +#define EPTPC_MITSELR_MINTEN2 (0x00000004u) +#define EPTPC_MITSELR_MINTEN2_SHIFT (2u) +#define EPTPC_MITSELR_MINTEN3 (0x00000008u) +#define EPTPC_MITSELR_MINTEN3_SHIFT (3u) +#define EPTPC_MITSELR_MINTEN4 (0x00000010u) +#define EPTPC_MITSELR_MINTEN4_SHIFT (4u) +#define EPTPC_MITSELR_MINTEN5 (0x00000020u) +#define EPTPC_MITSELR_MINTEN5_SHIFT (5u) +#define EPTPC_STCHSELR_SYSEL (0x00000001u) +#define EPTPC_STCHSELR_SYSEL_SHIFT (0u) +#define EPTPC_SYNSTARTR_STR (0x00000001u) +#define EPTPC_SYNSTARTR_STR_SHIFT (0u) +#define EPTPC_LCIVLDR_LOAD (0x00000001u) +#define EPTPC_LCIVLDR_LOAD_SHIFT (0u) +#define EPTPC_SYNTDARU_SYNTDARU (0xFFFFFFFFu) +#define EPTPC_SYNTDARU_SYNTDARU_SHIFT (0u) +#define EPTPC_SYNTDARL_SYNTDARL (0xFFFFFFFFu) +#define EPTPC_SYNTDARL_SYNTDARL_SHIFT (0u) +#define EPTPC_SYNTDBRU_SYNTDBRU (0xFFFFFFFFu) +#define EPTPC_SYNTDBRU_SYNTDBRU_SHIFT (0u) +#define EPTPC_SYNTDBRL_SYNTDBRL (0xFFFFFFFFu) +#define EPTPC_SYNTDBRL_SYNTDBRL_SHIFT (0u) +#define EPTPC_LCIVRU_LCIVRU (0x0000FFFFu) +#define EPTPC_LCIVRU_LCIVRU_SHIFT (0u) +#define EPTPC_LCIVRM_LCIVRM (0x0000FFFFu) +#define EPTPC_LCIVRM_LCIVRM_SHIFT (0u) +#define EPTPC_LCIVRL_LCIVRL (0x0000FFFFu) +#define EPTPC_LCIVRL_LCIVRL_SHIFT (0u) +#define EPTPC_GETW10R_GW10 (0x00000001u) +#define EPTPC_GETW10R_GW10_SHIFT (0u) +#define EPTPC_PLIMITRU_PLIMITRU (0x7FFFFFFFu) +#define EPTPC_PLIMITRU_PLIMITRU_SHIFT (0u) +#define EPTPC_PLIMITRM_PLIMITRM (0xFFFFFFFFu) +#define EPTPC_PLIMITRM_PLIMITRM_SHIFT (0u) +#define EPTPC_PLIMITRL_PLIMITRL (0xFFFFFFFFu) +#define EPTPC_PLIMITRL_PLIMITRL_SHIFT (0u) +#define EPTPC_MLIMITRU_MLIMITRU (0x7FFFFFFFu) +#define EPTPC_MLIMITRU_MLIMITRU_SHIFT (0u) +#define EPTPC_MLIMITRM_MLIMITRM (0xFFFFFFFFu) +#define EPTPC_MLIMITRM_MLIMITRM_SHIFT (0u) +#define EPTPC_MLIMITRL_MLIMITRL (0xFFFFFFFFu) +#define EPTPC_MLIMITRL_MLIMITRL_SHIFT (0u) +#define EPTPC_GETINFOR_INFO (0x00000001u) +#define EPTPC_GETINFOR_INFO_SHIFT (0u) +#define EPTPC_LCCVRU_LCCVRU (0x0000FFFFu) +#define EPTPC_LCCVRU_LCCVRU_SHIFT (0u) +#define EPTPC_LCCVRM_LCCVRM (0xFFFFFFFFu) +#define EPTPC_LCCVRM_LCCVRM_SHIFT (0u) +#define EPTPC_LCCVRL_LCCVRL (0xFFFFFFFFu) +#define EPTPC_LCCVRL_LCCVRL_SHIFT (0u) +#define EPTPC_PW10VRU_PW10VRU (0xFFFFFFFFu) +#define EPTPC_PW10VRU_PW10VRU_SHIFT (0u) +#define EPTPC_PW10VRM_PW10VRM (0xFFFFFFFFu) +#define EPTPC_PW10VRM_PW10VRM_SHIFT (0u) +#define EPTPC_PW10VRL_PW10VRL (0xFFFFFFFFu) +#define EPTPC_PW10VRL_PW10VRL_SHIFT (0u) +#define EPTPC_MW10RU_MW10RU (0xFFFFFFFFu) +#define EPTPC_MW10RU_MW10RU_SHIFT (0u) +#define EPTPC_MW10RM_MW10RM (0xFFFFFFFFu) +#define EPTPC_MW10RM_MW10RM_SHIFT (0u) +#define EPTPC_MW10RL_MW10RL (0xFFFFFFFFu) +#define EPTPC_MW10RL_MW10RL_SHIFT (0u) +#define EPTPC_TMSTTRU0_TMSTTRU0 (0xFFFFFFFFu) +#define EPTPC_TMSTTRU0_TMSTTRU0_SHIFT (0u) +#define EPTPC_TMSTTRL0_TMSTTRL0 (0xFFFFFFFFu) +#define EPTPC_TMSTTRL0_TMSTTRL0_SHIFT (0u) +#define EPTPC_TMCYCR0_TMCYCR0 (0xFFFFFFFFu) +#define EPTPC_TMCYCR0_TMCYCR0_SHIFT (0u) +#define EPTPC_TMPLSR0_TMPLSR0 (0x1FFFFFFFu) +#define EPTPC_TMPLSR0_TMPLSR0_SHIFT (0u) +#define EPTPC_TMSTTRU1_TMSTTRU1 (0xFFFFFFFFu) +#define EPTPC_TMSTTRU1_TMSTTRU1_SHIFT (0u) +#define EPTPC_TMSTTRL1_TMSTTRL1 (0xFFFFFFFFu) +#define EPTPC_TMSTTRL1_TMSTTRL1_SHIFT (0u) +#define EPTPC_TMCYCR1_TMCYCR1 (0xFFFFFFFFu) +#define EPTPC_TMCYCR1_TMCYCR1_SHIFT (0u) +#define EPTPC_TMPLSR1_TMPLSR1 (0x1FFFFFFFu) +#define EPTPC_TMPLSR1_TMPLSR1_SHIFT (0u) +#define EPTPC_TMSTTRU2_TMSTTRU2 (0xFFFFFFFFu) +#define EPTPC_TMSTTRU2_TMSTTRU2_SHIFT (0u) +#define EPTPC_TMSTTRL2_TMSTTRL2 (0xFFFFFFFFu) +#define EPTPC_TMSTTRL2_TMSTTRL2_SHIFT (0u) +#define EPTPC_TMCYCR2_TMCYCR2 (0xFFFFFFFFu) +#define EPTPC_TMCYCR2_TMCYCR2_SHIFT (0u) +#define EPTPC_TMPLSR2_TMPLSR2 (0x1FFFFFFFu) +#define EPTPC_TMPLSR2_TMPLSR2_SHIFT (0u) +#define EPTPC_TMSTTRU3_TMSTTRU3 (0xFFFFFFFFu) +#define EPTPC_TMSTTRU3_TMSTTRU3_SHIFT (0u) +#define EPTPC_TMSTTRL3_TMSTTRL3 (0xFFFFFFFFu) +#define EPTPC_TMSTTRL3_TMSTTRL3_SHIFT (0u) +#define EPTPC_TMCYCR3_TMCYCR3 (0xFFFFFFFFu) +#define EPTPC_TMCYCR3_TMCYCR3_SHIFT (0u) +#define EPTPC_TMPLSR3_TMPLSR3 (0x1FFFFFFFu) +#define EPTPC_TMPLSR3_TMPLSR3_SHIFT (0u) +#define EPTPC_TMSTTRU4_TMSTTRU4 (0xFFFFFFFFu) +#define EPTPC_TMSTTRU4_TMSTTRU4_SHIFT (0u) +#define EPTPC_TMSTTRL4_TMSTTRL4 (0xFFFFFFFFu) +#define EPTPC_TMSTTRL4_TMSTTRL4_SHIFT (0u) +#define EPTPC_TMCYCR4_TMCYCR4 (0xFFFFFFFFu) +#define EPTPC_TMCYCR4_TMCYCR4_SHIFT (0u) +#define EPTPC_TMPLSR4_TMPLSR4 (0x1FFFFFFFu) +#define EPTPC_TMPLSR4_TMPLSR4_SHIFT (0u) +#define EPTPC_TMSTTRU5_TMSTTRU5 (0xFFFFFFFFu) +#define EPTPC_TMSTTRU5_TMSTTRU5_SHIFT (0u) +#define EPTPC_TMSTTRL5_TMSTTRL5 (0xFFFFFFFFu) +#define EPTPC_TMSTTRL5_TMSTTRL5_SHIFT (0u) +#define EPTPC_TMCYCR5_TMCYCR5 (0xFFFFFFFFu) +#define EPTPC_TMCYCR5_TMCYCR5_SHIFT (0u) +#define EPTPC_TMPLSR5_TMPLSR5 (0x1FFFFFFFu) +#define EPTPC_TMPLSR5_TMPLSR5_SHIFT (0u) +#define EPTPC_TMSTARTR_EN0 (0x00000001u) +#define EPTPC_TMSTARTR_EN0_SHIFT (0u) +#define EPTPC_TMSTARTR_EN1 (0x00000002u) +#define EPTPC_TMSTARTR_EN1_SHIFT (1u) +#define EPTPC_TMSTARTR_EN2 (0x00000004u) +#define EPTPC_TMSTARTR_EN2_SHIFT (2u) +#define EPTPC_TMSTARTR_EN3 (0x00000008u) +#define EPTPC_TMSTARTR_EN3_SHIFT (3u) +#define EPTPC_TMSTARTR_EN4 (0x00000010u) +#define EPTPC_TMSTARTR_EN4_SHIFT (4u) +#define EPTPC_TMSTARTR_EN5 (0x00000020u) +#define EPTPC_TMSTARTR_EN5_SHIFT (5u) +#define EPTPC_PRSR_OVRE0 (0x00000001u) +#define EPTPC_PRSR_OVRE0_SHIFT (0u) +#define EPTPC_PRSR_OVRE1 (0x00000002u) +#define EPTPC_PRSR_OVRE1_SHIFT (1u) +#define EPTPC_PRSR_OVRE2 (0x00000004u) +#define EPTPC_PRSR_OVRE2_SHIFT (2u) +#define EPTPC_PRSR_OVRE3 (0x00000008u) +#define EPTPC_PRSR_OVRE3_SHIFT (3u) +#define EPTPC_PRSR_MACE (0x00000100u) +#define EPTPC_PRSR_MACE_SHIFT (8u) +#define EPTPC_PRSR_URE0 (0x10000000u) +#define EPTPC_PRSR_URE0_SHIFT (28u) +#define EPTPC_PRSR_URE1 (0x20000000u) +#define EPTPC_PRSR_URE1_SHIFT (29u) +#define EPTPC_PRIPR_OVRE0 (0x00000001u) +#define EPTPC_PRIPR_OVRE0_SHIFT (0u) +#define EPTPC_PRIPR_OVRE1 (0x00000002u) +#define EPTPC_PRIPR_OVRE1_SHIFT (1u) +#define EPTPC_PRIPR_OVRE2 (0x00000004u) +#define EPTPC_PRIPR_OVRE2_SHIFT (2u) +#define EPTPC_PRIPR_OVRE3 (0x00000008u) +#define EPTPC_PRIPR_OVRE3_SHIFT (3u) +#define EPTPC_PRIPR_MACE (0x00000100u) +#define EPTPC_PRIPR_MACE_SHIFT (8u) +#define EPTPC_PRIPR_URE0 (0x10000000u) +#define EPTPC_PRIPR_URE0_SHIFT (28u) +#define EPTPC_PRIPR_URE1 (0x20000000u) +#define EPTPC_PRIPR_URE1_SHIFT (29u) +#define EPTPC_PRMACRU0_PRMACRU0 (0x00FFFFFFu) +#define EPTPC_PRMACRU0_PRMACRU0_SHIFT (0u) +#define EPTPC_PRMACRL0_PRMACRL0 (0x00FFFFFFu) +#define EPTPC_PRMACRL0_PRMACRL0_SHIFT (0u) +#define EPTPC_PRMACRU1_PRMACRU1 (0x00FFFFFFu) +#define EPTPC_PRMACRU1_PRMACRU1_SHIFT (0u) +#define EPTPC_PRMACRL1_PRMACRL1 (0x00FFFFFFu) +#define EPTPC_PRMACRL1_PRMACRL1_SHIFT (0u) +#define EPTPC_TRNDISR_TDIS (0x00000003u) +#define EPTPC_TRNDISR_TDIS_SHIFT (0u) +#define EPTPC_TRNMR_MOD (0x00000001u) +#define EPTPC_TRNMR_MOD_SHIFT (0u) +#define EPTPC_TRNMR_FWD0 (0x00000100u) +#define EPTPC_TRNMR_FWD0_SHIFT (8u) +#define EPTPC_TRNMR_FWD1 (0x00000200u) +#define EPTPC_TRNMR_FWD1_SHIFT (9u) +#define EPTPC_TRNCTTDR_THVAL (0x000007FFu) +#define EPTPC_TRNCTTDR_THVAL_SHIFT (0u) +#define EPTPC_SYSR_OFMUD (0x00000001u) +#define EPTPC_SYSR_OFMUD_SHIFT (0u) +#define EPTPC_SYSR_INTCHG (0x00000002u) +#define EPTPC_SYSR_INTCHG_SHIFT (1u) +#define EPTPC_SYSR_MPDUD (0x00000004u) +#define EPTPC_SYSR_MPDUD_SHIFT (2u) +#define EPTPC_SYSR_DRPTO (0x00000010u) +#define EPTPC_SYSR_DRPTO_SHIFT (4u) +#define EPTPC_SYSR_INTDEV (0x00000020u) +#define EPTPC_SYSR_INTDEV_SHIFT (5u) +#define EPTPC_SYSR_DRQOVR (0x00000040u) +#define EPTPC_SYSR_DRQOVR_SHIFT (6u) +#define EPTPC_SYSR_RECLP (0x00001000u) +#define EPTPC_SYSR_RECLP_SHIFT (12u) +#define EPTPC_SYSR_INFABT (0x00004000u) +#define EPTPC_SYSR_INFABT_SHIFT (14u) +#define EPTPC_SYSR_RESDN (0x00010000u) +#define EPTPC_SYSR_RESDN_SHIFT (16u) +#define EPTPC_SYSR_GENDN (0x00020000u) +#define EPTPC_SYSR_GENDN_SHIFT (17u) +#define EPTPC_SYIPR_OFMUD (0x00000001u) +#define EPTPC_SYIPR_OFMUD_SHIFT (0u) +#define EPTPC_SYIPR_INTCHG (0x00000002u) +#define EPTPC_SYIPR_INTCHG_SHIFT (1u) +#define EPTPC_SYIPR_MPDUD (0x00000004u) +#define EPTPC_SYIPR_MPDUD_SHIFT (2u) +#define EPTPC_SYIPR_DRPTO (0x00000010u) +#define EPTPC_SYIPR_DRPTO_SHIFT (4u) +#define EPTPC_SYIPR_INTDEV (0x00000020u) +#define EPTPC_SYIPR_INTDEV_SHIFT (5u) +#define EPTPC_SYIPR_DRQOVR (0x00000040u) +#define EPTPC_SYIPR_DRQOVR_SHIFT (6u) +#define EPTPC_SYIPR_RECLP (0x00001000u) +#define EPTPC_SYIPR_RECLP_SHIFT (12u) +#define EPTPC_SYIPR_INFABT (0x00004000u) +#define EPTPC_SYIPR_INFABT_SHIFT (14u) +#define EPTPC_SYIPR_RESDN (0x00010000u) +#define EPTPC_SYIPR_RESDN_SHIFT (16u) +#define EPTPC_SYIPR_GENDN (0x00020000u) +#define EPTPC_SYIPR_GENDN_SHIFT (17u) +#define EPTPC_SYMACRU_SYMACRU (0x00FFFFFFu) +#define EPTPC_SYMACRU_SYMACRU_SHIFT (0u) +#define EPTPC_SYMACRL_SYMACRL (0x00FFFFFFu) +#define EPTPC_SYMACRL_SYMACRL_SHIFT (0u) +#define EPTPC_SYLLCCTLR_CTL (0x000000FFu) +#define EPTPC_SYLLCCTLR_CTL_SHIFT (0u) +#define EPTPC_SYIPADDRR_SYIPADDRR (0xFFFFFFFFu) +#define EPTPC_SYIPADDRR_SYIPADDRR_SHIFT (0u) +#define EPTPC_SYSPVRR_VER (0x0000000Fu) +#define EPTPC_SYSPVRR_VER_SHIFT (0u) +#define EPTPC_SYSPVRR_TRSP (0x000000F0u) +#define EPTPC_SYSPVRR_TRSP_SHIFT (4u) +#define EPTPC_SYDOMR_DNUM (0x000000FFu) +#define EPTPC_SYDOMR_DNUM_SHIFT (0u) +#define EPTPC_ANFR_FLAG0 (0x00000001u) +#define EPTPC_ANFR_FLAG0_SHIFT (0u) +#define EPTPC_ANFR_FLAG1 (0x00000002u) +#define EPTPC_ANFR_FLAG1_SHIFT (1u) +#define EPTPC_ANFR_FLAG2 (0x00000004u) +#define EPTPC_ANFR_FLAG2_SHIFT (2u) +#define EPTPC_ANFR_FLAG3 (0x00000008u) +#define EPTPC_ANFR_FLAG3_SHIFT (3u) +#define EPTPC_ANFR_FLAG4 (0x00000010u) +#define EPTPC_ANFR_FLAG4_SHIFT (4u) +#define EPTPC_ANFR_FLAG5 (0x00000020u) +#define EPTPC_ANFR_FLAG5_SHIFT (5u) +#define EPTPC_ANFR_FLAG8 (0x00000100u) +#define EPTPC_ANFR_FLAG8_SHIFT (8u) +#define EPTPC_ANFR_FLAG10 (0x00000400u) +#define EPTPC_ANFR_FLAG10_SHIFT (10u) +#define EPTPC_ANFR_FLAG13 (0x00002000u) +#define EPTPC_ANFR_FLAG13_SHIFT (13u) +#define EPTPC_ANFR_FLAG14 (0x00004000u) +#define EPTPC_ANFR_FLAG14_SHIFT (14u) +#define EPTPC_SYNFR_FLAG10 (0x00000400u) +#define EPTPC_SYNFR_FLAG10_SHIFT (10u) +#define EPTPC_SYNFR_FLAG13 (0x00002000u) +#define EPTPC_SYNFR_FLAG13_SHIFT (13u) +#define EPTPC_SYNFR_FLAG14 (0x00004000u) +#define EPTPC_SYNFR_FLAG14_SHIFT (14u) +#define EPTPC_DYRQFR_FLAG10 (0x00000400u) +#define EPTPC_DYRQFR_FLAG10_SHIFT (10u) +#define EPTPC_DYRQFR_FLAG13 (0x00002000u) +#define EPTPC_DYRQFR_FLAG13_SHIFT (13u) +#define EPTPC_DYRQFR_FLAG14 (0x00004000u) +#define EPTPC_DYRQFR_FLAG14_SHIFT (14u) +#define EPTPC_DYRPFR_FLAG8 (0x00000100u) +#define EPTPC_DYRPFR_FLAG8_SHIFT (8u) +#define EPTPC_DYRPFR_FLAG9 (0x00000200u) +#define EPTPC_DYRPFR_FLAG9_SHIFT (9u) +#define EPTPC_DYRPFR_FLAG10 (0x00000400u) +#define EPTPC_DYRPFR_FLAG10_SHIFT (10u) +#define EPTPC_DYRPFR_FLAG13 (0x00002000u) +#define EPTPC_DYRPFR_FLAG13_SHIFT (13u) +#define EPTPC_DYRPFR_FLAG14 (0x00004000u) +#define EPTPC_DYRPFR_FLAG14_SHIFT (14u) +#define EPTPC_SYCIDRL_SYCIDRL (0xFFFFFFFFu) +#define EPTPC_SYCIDRL_SYCIDRL_SHIFT (0u) +#define EPTPC_SYCIDRU_SYCIDRU (0xFFFFFFFFu) +#define EPTPC_SYCIDRU_SYCIDRU_SHIFT (0u) +#define EPTPC_SYPNUMR_PNUM (0x0000FFFFu) +#define EPTPC_SYPNUMR_PNUM_SHIFT (0u) +#define EPTPC_SYRVLDR_BMUP (0x00000001u) +#define EPTPC_SYRVLDR_BMUP_SHIFT (0u) +#define EPTPC_SYRVLDR_STUP (0x00000002u) +#define EPTPC_SYRVLDR_STUP_SHIFT (1u) +#define EPTPC_SYRVLDR_ANUP (0x00000004u) +#define EPTPC_SYRVLDR_ANUP_SHIFT (2u) +#define EPTPC_SYRFL1R_ANCE (0x00000003u) +#define EPTPC_SYRFL1R_ANCE_SHIFT (0u) +#define EPTPC_SYRFL1R_SYNC (0x00000070u) +#define EPTPC_SYRFL1R_SYNC_SHIFT (4u) +#define EPTPC_SYRFL1R_FUP (0x00000700u) +#define EPTPC_SYRFL1R_FUP_SHIFT (8u) +#define EPTPC_SYRFL1R_DRQ (0x00007000u) +#define EPTPC_SYRFL1R_DRQ_SHIFT (12u) +#define EPTPC_SYRFL1R_DRP (0x00070000u) +#define EPTPC_SYRFL1R_DRP_SHIFT (16u) +#define EPTPC_SYRFL1R_PDRQ (0x00700000u) +#define EPTPC_SYRFL1R_PDRQ_SHIFT (20u) +#define EPTPC_SYRFL1R_PDRP (0x07000000u) +#define EPTPC_SYRFL1R_PDRP_SHIFT (24u) +#define EPTPC_SYRFL1R_PDFUP (0x70000000u) +#define EPTPC_SYRFL1R_PDFUP_SHIFT (28u) +#define EPTPC_SYRFL2R_MAN (0x00000003u) +#define EPTPC_SYRFL2R_MAN_SHIFT (0u) +#define EPTPC_SYRFL2R_SIG (0x00000030u) +#define EPTPC_SYRFL2R_SIG_SHIFT (4u) +#define EPTPC_SYRFL2R_ILL (0x30000000u) +#define EPTPC_SYRFL2R_ILL_SHIFT (28u) +#define EPTPC_SYTRENR_ANCE (0x00000001u) +#define EPTPC_SYTRENR_ANCE_SHIFT (0u) +#define EPTPC_SYTRENR_SYNC (0x00000010u) +#define EPTPC_SYTRENR_SYNC_SHIFT (4u) +#define EPTPC_SYTRENR_DRQ (0x00000100u) +#define EPTPC_SYTRENR_DRQ_SHIFT (8u) +#define EPTPC_SYTRENR_PDRQ (0x00001000u) +#define EPTPC_SYTRENR_PDRQ_SHIFT (12u) +#define EPTPC_MTCIDL_MTCIDL (0xFFFFFFFFu) +#define EPTPC_MTCIDL_MTCIDL_SHIFT (0u) +#define EPTPC_MTCIDU_MTCIDU (0xFFFFFFFFu) +#define EPTPC_MTCIDU_MTCIDU_SHIFT (0u) +#define EPTPC_MTPID_PNUM (0x0000FFFFu) +#define EPTPC_MTPID_PNUM_SHIFT (0u) +#define EPTPC_SYTLIR_ANCE (0x000000FFu) +#define EPTPC_SYTLIR_ANCE_SHIFT (0u) +#define EPTPC_SYTLIR_SYNC (0x0000FF00u) +#define EPTPC_SYTLIR_SYNC_SHIFT (8u) +#define EPTPC_SYTLIR_DREQ (0x00FF0000u) +#define EPTPC_SYTLIR_DREQ_SHIFT (16u) +#define EPTPC_SYRLIR_ANCE (0x000000FFu) +#define EPTPC_SYRLIR_ANCE_SHIFT (0u) +#define EPTPC_SYRLIR_SYNC (0x0000FF00u) +#define EPTPC_SYRLIR_SYNC_SHIFT (8u) +#define EPTPC_SYRLIR_DRESP (0x00FF0000u) +#define EPTPC_SYRLIR_DRESP_SHIFT (16u) +#define EPTPC_OFMRL_OFMRL (0xFFFFFFFFu) +#define EPTPC_OFMRL_OFMRL_SHIFT (0u) +#define EPTPC_OFMRU_OFMRU (0xFFFFFFFFu) +#define EPTPC_OFMRU_OFMRU_SHIFT (0u) +#define EPTPC_MPDRU_MPDRU (0xFFFFFFFFu) +#define EPTPC_MPDRU_MPDRU_SHIFT (0u) +#define EPTPC_MPDRL_MPDRL (0xFFFFFFFFu) +#define EPTPC_MPDRL_MPDRL_SHIFT (0u) +#define EPTPC_GMPR_GMPR2 (0x000000FFu) +#define EPTPC_GMPR_GMPR2_SHIFT (0u) +#define EPTPC_GMPR_GMPR1 (0x00FF0000u) +#define EPTPC_GMPR_GMPR1_SHIFT (16u) +#define EPTPC_GMCQR_GMCQR (0xFFFFFFFFu) +#define EPTPC_GMCQR_GMCQR_SHIFT (0u) +#define EPTPC_GMIDRU_GMIDRU (0xFFFFFFFFu) +#define EPTPC_GMIDRU_GMIDRU_SHIFT (0u) +#define EPTPC_GMIDRL_GMIDRL (0xFFFFFFFFu) +#define EPTPC_GMIDRL_GMIDRL_SHIFT (0u) +#define EPTPC_CUOTSR_TSRC (0x000000FFu) +#define EPTPC_CUOTSR_TSRC_SHIFT (0u) +#define EPTPC_CUOTSR_CUTO (0xFFFF0000u) +#define EPTPC_CUOTSR_CUTO_SHIFT (16u) +#define EPTPC_SRR_SRMV (0x0000FFFFu) +#define EPTPC_SRR_SRMV_SHIFT (0u) +#define EPTPC_PPMACRU_PPMACRU (0x00FFFFFFu) +#define EPTPC_PPMACRU_PPMACRU_SHIFT (0u) +#define EPTPC_PPMACRL_PPMACRL (0x00FFFFFFu) +#define EPTPC_PPMACRL_PPMACRL_SHIFT (0u) +#define EPTPC_PDMACRU_PDMACRU (0x00FFFFFFu) +#define EPTPC_PDMACRU_PDMACRU_SHIFT (0u) +#define EPTPC_PDMACRL_PDMACRL (0x00FFFFFFu) +#define EPTPC_PDMACRL_PDMACRL_SHIFT (0u) +#define EPTPC_PETYPER_TYPE (0x0000FFFFu) +#define EPTPC_PETYPER_TYPE_SHIFT (0u) +#define EPTPC_PPIPR_PPIPR (0xFFFFFFFFu) +#define EPTPC_PPIPR_PPIPR_SHIFT (0u) +#define EPTPC_PDIPR_PDIPR (0xFFFFFFFFu) +#define EPTPC_PDIPR_PDIPR_SHIFT (0u) +#define EPTPC_PETOSR_EVTO (0x000000FFu) +#define EPTPC_PETOSR_EVTO_SHIFT (0u) +#define EPTPC_PGTOSR_GETO (0x000000FFu) +#define EPTPC_PGTOSR_GETO_SHIFT (0u) +#define EPTPC_PPTTLR_PRTL (0x000000FFu) +#define EPTPC_PPTTLR_PRTL_SHIFT (0u) +#define EPTPC_PDTTLR_PDTL (0x000000FFu) +#define EPTPC_PDTTLR_PDTL_SHIFT (0u) +#define EPTPC_PEUDPR_EVUPT (0x0000FFFFu) +#define EPTPC_PEUDPR_EVUPT_SHIFT (0u) +#define EPTPC_PGUDPR_GEUPT (0x0000FFFFu) +#define EPTPC_PGUDPR_GEUPT_SHIFT (0u) +#define EPTPC_FFLTR_SEL (0x00000001u) +#define EPTPC_FFLTR_SEL_SHIFT (0u) +#define EPTPC_FFLTR_PRT (0x00000002u) +#define EPTPC_FFLTR_PRT_SHIFT (1u) +#define EPTPC_FFLTR_ENB (0x00000004u) +#define EPTPC_FFLTR_ENB_SHIFT (2u) +#define EPTPC_FFLTR_EXTPRM (0x00010000u) +#define EPTPC_FFLTR_EXTPRM_SHIFT (16u) +#define EPTPC_FMAC0RU_FMAC0RU (0x00FFFFFFu) +#define EPTPC_FMAC0RU_FMAC0RU_SHIFT (0u) +#define EPTPC_FMAC0RL_FMAC0RL (0x00FFFFFFu) +#define EPTPC_FMAC0RL_FMAC0RL_SHIFT (0u) +#define EPTPC_FMAC1RU_FMAC1RU (0x00FFFFFFu) +#define EPTPC_FMAC1RU_FMAC1RU_SHIFT (0u) +#define EPTPC_FMAC1RL_FMAC1RL (0x00FFFFFFu) +#define EPTPC_FMAC1RL_FMAC1RL_SHIFT (0u) +#define EPTPC_DASYMRU_DASYMRU (0x0000FFFFu) +#define EPTPC_DASYMRU_DASYMRU_SHIFT (0u) +#define EPTPC_DASYMRL_DASYMRL (0xFFFFFFFFu) +#define EPTPC_DASYMRL_DASYMRL_SHIFT (0u) +#define EPTPC_TSLATR_EGP (0x0000FFFFu) +#define EPTPC_TSLATR_EGP_SHIFT (0u) +#define EPTPC_TSLATR_INGP (0xFFFF0000u) +#define EPTPC_TSLATR_INGP_SHIFT (16u) +#define EPTPC_SYCONFR_TCYC (0x000000FFu) +#define EPTPC_SYCONFR_TCYC_SHIFT (0u) +#define EPTPC_SYCONFR_SBDIS (0x00001000u) +#define EPTPC_SYCONFR_SBDIS_SHIFT (12u) +#define EPTPC_SYCONFR_FILDIS (0x00010000u) +#define EPTPC_SYCONFR_FILDIS_SHIFT (16u) +#define EPTPC_SYCONFR_TCMOD (0x00100000u) +#define EPTPC_SYCONFR_TCMOD_SHIFT (20u) +#define EPTPC_SYFORMR_FORM0 (0x00000001u) +#define EPTPC_SYFORMR_FORM0_SHIFT (0u) +#define EPTPC_SYFORMR_FORM1 (0x00000002u) +#define EPTPC_SYFORMR_FORM1_SHIFT (1u) +#define EPTPC_RSTOUTR_RSTOUTR (0xFFFFFFFFu) +#define EPTPC_RSTOUTR_RSTOUTR_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/etherc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/etherc_iobitmask.h new file mode 100644 index 0000000..9966b24 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/etherc_iobitmask.h @@ -0,0 +1,148 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef ETHERC_IOBITMASK_H +#define ETHERC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define ETHERC_ECMR_PRM (0x00000001u) +#define ETHERC_ECMR_PRM_SHIFT (0u) +#define ETHERC_ECMR_DM (0x00000002u) +#define ETHERC_ECMR_DM_SHIFT (1u) +#define ETHERC_ECMR_RTM (0x00000004u) +#define ETHERC_ECMR_RTM_SHIFT (2u) +#define ETHERC_ECMR_ILB (0x00000008u) +#define ETHERC_ECMR_ILB_SHIFT (3u) +#define ETHERC_ECMR_TE (0x00000020u) +#define ETHERC_ECMR_TE_SHIFT (5u) +#define ETHERC_ECMR_RE (0x00000040u) +#define ETHERC_ECMR_RE_SHIFT (6u) +#define ETHERC_ECMR_MPDE (0x00000200u) +#define ETHERC_ECMR_MPDE_SHIFT (9u) +#define ETHERC_ECMR_PRCEF (0x00001000u) +#define ETHERC_ECMR_PRCEF_SHIFT (12u) +#define ETHERC_ECMR_TXF (0x00010000u) +#define ETHERC_ECMR_TXF_SHIFT (16u) +#define ETHERC_ECMR_RXF (0x00020000u) +#define ETHERC_ECMR_RXF_SHIFT (17u) +#define ETHERC_ECMR_PFR (0x00040000u) +#define ETHERC_ECMR_PFR_SHIFT (18u) +#define ETHERC_ECMR_ZPF (0x00080000u) +#define ETHERC_ECMR_ZPF_SHIFT (19u) +#define ETHERC_ECMR_TPC (0x00100000u) +#define ETHERC_ECMR_TPC_SHIFT (20u) +#define ETHERC_RFLR_RFL (0x00000FFFu) +#define ETHERC_RFLR_RFL_SHIFT (0u) +#define ETHERC_ECSR_ICD (0x00000001u) +#define ETHERC_ECSR_ICD_SHIFT (0u) +#define ETHERC_ECSR_MPD (0x00000002u) +#define ETHERC_ECSR_MPD_SHIFT (1u) +#define ETHERC_ECSR_LCHNG (0x00000004u) +#define ETHERC_ECSR_LCHNG_SHIFT (2u) +#define ETHERC_ECSR_PSRTO (0x00000010u) +#define ETHERC_ECSR_PSRTO_SHIFT (4u) +#define ETHERC_ECSR_BFR (0x00000020u) +#define ETHERC_ECSR_BFR_SHIFT (5u) +#define ETHERC_ECSIPR_ICDIP (0x00000001u) +#define ETHERC_ECSIPR_ICDIP_SHIFT (0u) +#define ETHERC_ECSIPR_MPDIP (0x00000002u) +#define ETHERC_ECSIPR_MPDIP_SHIFT (1u) +#define ETHERC_ECSIPR_LCHNGIP (0x00000004u) +#define ETHERC_ECSIPR_LCHNGIP_SHIFT (2u) +#define ETHERC_ECSIPR_PSRTOIP (0x00000010u) +#define ETHERC_ECSIPR_PSRTOIP_SHIFT (4u) +#define ETHERC_ECSIPR_BFSIPR (0x00000020u) +#define ETHERC_ECSIPR_BFSIPR_SHIFT (5u) +#define ETHERC_PIR_MDC (0x00000001u) +#define ETHERC_PIR_MDC_SHIFT (0u) +#define ETHERC_PIR_MMD (0x00000002u) +#define ETHERC_PIR_MMD_SHIFT (1u) +#define ETHERC_PIR_MDO (0x00000004u) +#define ETHERC_PIR_MDO_SHIFT (2u) +#define ETHERC_PIR_MDI (0x00000008u) +#define ETHERC_PIR_MDI_SHIFT (3u) +#define ETHERC_PSR_LMON (0x00000001u) +#define ETHERC_PSR_LMON_SHIFT (0u) +#define ETHERC_RDMLR_RMD (0x000FFFFFu) +#define ETHERC_RDMLR_RMD_SHIFT (0u) +#define ETHERC_IPGR_IPG (0x0000001Fu) +#define ETHERC_IPGR_IPG_SHIFT (0u) +#define ETHERC_APR_AP (0x0000FFFFu) +#define ETHERC_APR_AP_SHIFT (0u) +#define ETHERC_MPR_MP (0x0000FFFFu) +#define ETHERC_MPR_MP_SHIFT (0u) +#define ETHERC_RFCF_RPAUSE (0x000000FFu) +#define ETHERC_RFCF_RPAUSE_SHIFT (0u) +#define ETHERC_TPAUSER_TPAUSE (0x0000FFFFu) +#define ETHERC_TPAUSER_TPAUSE_SHIFT (0u) +#define ETHERC_TPAUSECR_TXP (0x000000FFu) +#define ETHERC_TPAUSECR_TXP_SHIFT (0u) +#define ETHERC_BCFRR_BCF (0x0000FFFFu) +#define ETHERC_BCFRR_BCF_SHIFT (0u) +#define ETHERC_MAHR_MAHR (0xFFFFFFFFu) +#define ETHERC_MAHR_MAHR_SHIFT (0u) +#define ETHERC_MALR_MALR (0x0000FFFFu) +#define ETHERC_MALR_MALR_SHIFT (0u) +#define ETHERC_TROCR_TROCR (0xFFFFFFFFu) +#define ETHERC_TROCR_TROCR_SHIFT (0u) +#define ETHERC_CDCR_CDCR (0xFFFFFFFFu) +#define ETHERC_CDCR_CDCR_SHIFT (0u) +#define ETHERC_LCCR_LCCR (0xFFFFFFFFu) +#define ETHERC_LCCR_LCCR_SHIFT (0u) +#define ETHERC_CNDCR_CNDCR (0xFFFFFFFFu) +#define ETHERC_CNDCR_CNDCR_SHIFT (0u) +#define ETHERC_CEFCR_CEFCR (0xFFFFFFFFu) +#define ETHERC_CEFCR_CEFCR_SHIFT (0u) +#define ETHERC_FRECR_FRECR (0xFFFFFFFFu) +#define ETHERC_FRECR_FRECR_SHIFT (0u) +#define ETHERC_TSFRCR_TSFRCR (0xFFFFFFFFu) +#define ETHERC_TSFRCR_TSFRCR_SHIFT (0u) +#define ETHERC_TLFRCR_TLFRCR (0xFFFFFFFFu) +#define ETHERC_TLFRCR_TLFRCR_SHIFT (0u) +#define ETHERC_RFCR_RFCR (0xFFFFFFFFu) +#define ETHERC_RFCR_RFCR_SHIFT (0u) +#define ETHERC_MAFCR_MAFCR (0xFFFFFFFFu) +#define ETHERC_MAFCR_MAFCR_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpio_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpio_iobitmask.h new file mode 100644 index 0000000..4534ef2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpio_iobitmask.h @@ -0,0 +1,828 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef GPIO_IOBITMASK_H +#define GPIO_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define GPIO_P00PFS_PSEL (0x07u) +#define GPIO_P00PFS_PSEL_SHIFT (0u) +#define GPIO_P00PFS_ISEL (0x40u) +#define GPIO_P00PFS_ISEL_SHIFT (6u) +#define GPIO_P01PFS_PSEL (0x07u) +#define GPIO_P01PFS_PSEL_SHIFT (0u) +#define GPIO_P01PFS_ISEL (0x40u) +#define GPIO_P01PFS_ISEL_SHIFT (6u) +#define GPIO_P02PFS_PSEL (0x07u) +#define GPIO_P02PFS_PSEL_SHIFT (0u) +#define GPIO_P02PFS_ISEL (0x40u) +#define GPIO_P02PFS_ISEL_SHIFT (6u) +#define GPIO_P03PFS_PSEL (0x07u) +#define GPIO_P03PFS_PSEL_SHIFT (0u) +#define GPIO_P03PFS_ISEL (0x40u) +#define GPIO_P03PFS_ISEL_SHIFT (6u) +#define GPIO_P04PFS_PSEL (0x07u) +#define GPIO_P04PFS_PSEL_SHIFT (0u) +#define GPIO_P04PFS_ISEL (0x40u) +#define GPIO_P04PFS_ISEL_SHIFT (6u) +#define GPIO_P05PFS_PSEL (0x07u) +#define GPIO_P05PFS_PSEL_SHIFT (0u) +#define GPIO_P05PFS_ISEL (0x40u) +#define GPIO_P05PFS_ISEL_SHIFT (6u) +#define GPIO_P06PFS_PSEL (0x07u) +#define GPIO_P06PFS_PSEL_SHIFT (0u) +#define GPIO_P06PFS_ISEL (0x40u) +#define GPIO_P06PFS_ISEL_SHIFT (6u) +#define GPIO_P10PFS_PSEL (0x07u) +#define GPIO_P10PFS_PSEL_SHIFT (0u) +#define GPIO_P10PFS_ISEL (0x40u) +#define GPIO_P10PFS_ISEL_SHIFT (6u) +#define GPIO_P11PFS_PSEL (0x07u) +#define GPIO_P11PFS_PSEL_SHIFT (0u) +#define GPIO_P11PFS_ISEL (0x40u) +#define GPIO_P11PFS_ISEL_SHIFT (6u) +#define GPIO_P12PFS_PSEL (0x07u) +#define GPIO_P12PFS_PSEL_SHIFT (0u) +#define GPIO_P12PFS_ISEL (0x40u) +#define GPIO_P12PFS_ISEL_SHIFT (6u) +#define GPIO_P13PFS_PSEL (0x07u) +#define GPIO_P13PFS_PSEL_SHIFT (0u) +#define GPIO_P13PFS_ISEL (0x40u) +#define GPIO_P13PFS_ISEL_SHIFT (6u) +#define GPIO_P14PFS_PSEL (0x07u) +#define GPIO_P14PFS_PSEL_SHIFT (0u) +#define GPIO_P14PFS_ISEL (0x40u) +#define GPIO_P14PFS_ISEL_SHIFT (6u) +#define GPIO_P20PFS_PSEL (0x07u) +#define GPIO_P20PFS_PSEL_SHIFT (0u) +#define GPIO_P20PFS_ISEL (0x40u) +#define GPIO_P20PFS_ISEL_SHIFT (6u) +#define GPIO_P21PFS_PSEL (0x07u) +#define GPIO_P21PFS_PSEL_SHIFT (0u) +#define GPIO_P21PFS_ISEL (0x40u) +#define GPIO_P21PFS_ISEL_SHIFT (6u) +#define GPIO_P22PFS_PSEL (0x07u) +#define GPIO_P22PFS_PSEL_SHIFT (0u) +#define GPIO_P22PFS_ISEL (0x40u) +#define GPIO_P22PFS_ISEL_SHIFT (6u) +#define GPIO_P23PFS_PSEL (0x07u) +#define GPIO_P23PFS_PSEL_SHIFT (0u) +#define GPIO_P23PFS_ISEL (0x40u) +#define GPIO_P23PFS_ISEL_SHIFT (6u) +#define GPIO_P30PFS_PSEL (0x07u) +#define GPIO_P30PFS_PSEL_SHIFT (0u) +#define GPIO_P30PFS_ISEL (0x40u) +#define GPIO_P30PFS_ISEL_SHIFT (6u) +#define GPIO_P31PFS_PSEL (0x07u) +#define GPIO_P31PFS_PSEL_SHIFT (0u) +#define GPIO_P31PFS_ISEL (0x40u) +#define GPIO_P31PFS_ISEL_SHIFT (6u) +#define GPIO_P32PFS_PSEL (0x07u) +#define GPIO_P32PFS_PSEL_SHIFT (0u) +#define GPIO_P32PFS_ISEL (0x40u) +#define GPIO_P32PFS_ISEL_SHIFT (6u) +#define GPIO_P33PFS_PSEL (0x07u) +#define GPIO_P33PFS_PSEL_SHIFT (0u) +#define GPIO_P33PFS_ISEL (0x40u) +#define GPIO_P33PFS_ISEL_SHIFT (6u) +#define GPIO_P34PFS_PSEL (0x07u) +#define GPIO_P34PFS_PSEL_SHIFT (0u) +#define GPIO_P34PFS_ISEL (0x40u) +#define GPIO_P34PFS_ISEL_SHIFT (6u) +#define GPIO_P35PFS_PSEL (0x07u) +#define GPIO_P35PFS_PSEL_SHIFT (0u) +#define GPIO_P35PFS_ISEL (0x40u) +#define GPIO_P35PFS_ISEL_SHIFT (6u) +#define GPIO_P40PFS_PSEL (0x07u) +#define GPIO_P40PFS_PSEL_SHIFT (0u) +#define GPIO_P40PFS_ISEL (0x40u) +#define GPIO_P40PFS_ISEL_SHIFT (6u) +#define GPIO_P41PFS_PSEL (0x07u) +#define GPIO_P41PFS_PSEL_SHIFT (0u) +#define GPIO_P41PFS_ISEL (0x40u) +#define GPIO_P41PFS_ISEL_SHIFT (6u) +#define GPIO_P42PFS_PSEL (0x07u) +#define GPIO_P42PFS_PSEL_SHIFT (0u) +#define GPIO_P42PFS_ISEL (0x40u) +#define GPIO_P42PFS_ISEL_SHIFT (6u) +#define GPIO_P43PFS_PSEL (0x07u) +#define GPIO_P43PFS_PSEL_SHIFT (0u) +#define GPIO_P43PFS_ISEL (0x40u) +#define GPIO_P43PFS_ISEL_SHIFT (6u) +#define GPIO_P44PFS_PSEL (0x07u) +#define GPIO_P44PFS_PSEL_SHIFT (0u) +#define GPIO_P44PFS_ISEL (0x40u) +#define GPIO_P44PFS_ISEL_SHIFT (6u) +#define GPIO_P45PFS_PSEL (0x07u) +#define GPIO_P45PFS_PSEL_SHIFT (0u) +#define GPIO_P45PFS_ISEL (0x40u) +#define GPIO_P45PFS_ISEL_SHIFT (6u) +#define GPIO_P46PFS_PSEL (0x07u) +#define GPIO_P46PFS_PSEL_SHIFT (0u) +#define GPIO_P46PFS_ISEL (0x40u) +#define GPIO_P46PFS_ISEL_SHIFT (6u) +#define GPIO_P47PFS_PSEL (0x07u) +#define GPIO_P47PFS_PSEL_SHIFT (0u) +#define GPIO_P47PFS_ISEL (0x40u) +#define GPIO_P47PFS_ISEL_SHIFT (6u) +#define GPIO_P50PFS_PSEL (0x07u) +#define GPIO_P50PFS_PSEL_SHIFT (0u) +#define GPIO_P50PFS_ISEL (0x40u) +#define GPIO_P50PFS_ISEL_SHIFT (6u) +#define GPIO_P51PFS_PSEL (0x07u) +#define GPIO_P51PFS_PSEL_SHIFT (0u) +#define GPIO_P51PFS_ISEL (0x40u) +#define GPIO_P51PFS_ISEL_SHIFT (6u) +#define GPIO_P52PFS_PSEL (0x07u) +#define GPIO_P52PFS_PSEL_SHIFT (0u) +#define GPIO_P52PFS_ISEL (0x40u) +#define GPIO_P52PFS_ISEL_SHIFT (6u) +#define GPIO_P53PFS_PSEL (0x07u) +#define GPIO_P53PFS_PSEL_SHIFT (0u) +#define GPIO_P53PFS_ISEL (0x40u) +#define GPIO_P53PFS_ISEL_SHIFT (6u) +#define GPIO_P54PFS_PSEL (0x07u) +#define GPIO_P54PFS_PSEL_SHIFT (0u) +#define GPIO_P54PFS_ISEL (0x40u) +#define GPIO_P54PFS_ISEL_SHIFT (6u) +#define GPIO_P55PFS_PSEL (0x07u) +#define GPIO_P55PFS_PSEL_SHIFT (0u) +#define GPIO_P55PFS_ISEL (0x40u) +#define GPIO_P55PFS_ISEL_SHIFT (6u) +#define GPIO_P56PFS_PSEL (0x07u) +#define GPIO_P56PFS_PSEL_SHIFT (0u) +#define GPIO_P56PFS_ISEL (0x40u) +#define GPIO_P56PFS_ISEL_SHIFT (6u) +#define GPIO_P57PFS_PSEL (0x07u) +#define GPIO_P57PFS_PSEL_SHIFT (0u) +#define GPIO_P57PFS_ISEL (0x40u) +#define GPIO_P57PFS_ISEL_SHIFT (6u) +#define GPIO_P60PFS_PSEL (0x07u) +#define GPIO_P60PFS_PSEL_SHIFT (0u) +#define GPIO_P60PFS_ISEL (0x40u) +#define GPIO_P60PFS_ISEL_SHIFT (6u) +#define GPIO_P61PFS_PSEL (0x07u) +#define GPIO_P61PFS_PSEL_SHIFT (0u) +#define GPIO_P61PFS_ISEL (0x40u) +#define GPIO_P61PFS_ISEL_SHIFT (6u) +#define GPIO_P62PFS_PSEL (0x07u) +#define GPIO_P62PFS_PSEL_SHIFT (0u) +#define GPIO_P62PFS_ISEL (0x40u) +#define GPIO_P62PFS_ISEL_SHIFT (6u) +#define GPIO_P63PFS_PSEL (0x07u) +#define GPIO_P63PFS_PSEL_SHIFT (0u) +#define GPIO_P63PFS_ISEL (0x40u) +#define GPIO_P63PFS_ISEL_SHIFT (6u) +#define GPIO_P64PFS_PSEL (0x07u) +#define GPIO_P64PFS_PSEL_SHIFT (0u) +#define GPIO_P64PFS_ISEL (0x40u) +#define GPIO_P64PFS_ISEL_SHIFT (6u) +#define GPIO_P65PFS_PSEL (0x07u) +#define GPIO_P65PFS_PSEL_SHIFT (0u) +#define GPIO_P65PFS_ISEL (0x40u) +#define GPIO_P65PFS_ISEL_SHIFT (6u) +#define GPIO_P66PFS_PSEL (0x07u) +#define GPIO_P66PFS_PSEL_SHIFT (0u) +#define GPIO_P66PFS_ISEL (0x40u) +#define GPIO_P66PFS_ISEL_SHIFT (6u) +#define GPIO_P67PFS_PSEL (0x07u) +#define GPIO_P67PFS_PSEL_SHIFT (0u) +#define GPIO_P67PFS_ISEL (0x40u) +#define GPIO_P67PFS_ISEL_SHIFT (6u) +#define GPIO_P70PFS_PSEL (0x07u) +#define GPIO_P70PFS_PSEL_SHIFT (0u) +#define GPIO_P70PFS_ISEL (0x40u) +#define GPIO_P70PFS_ISEL_SHIFT (6u) +#define GPIO_P71PFS_PSEL (0x07u) +#define GPIO_P71PFS_PSEL_SHIFT (0u) +#define GPIO_P71PFS_ISEL (0x40u) +#define GPIO_P71PFS_ISEL_SHIFT (6u) +#define GPIO_P72PFS_PSEL (0x07u) +#define GPIO_P72PFS_PSEL_SHIFT (0u) +#define GPIO_P72PFS_ISEL (0x40u) +#define GPIO_P72PFS_ISEL_SHIFT (6u) +#define GPIO_P73PFS_PSEL (0x07u) +#define GPIO_P73PFS_PSEL_SHIFT (0u) +#define GPIO_P73PFS_ISEL (0x40u) +#define GPIO_P73PFS_ISEL_SHIFT (6u) +#define GPIO_P74PFS_PSEL (0x07u) +#define GPIO_P74PFS_PSEL_SHIFT (0u) +#define GPIO_P74PFS_ISEL (0x40u) +#define GPIO_P74PFS_ISEL_SHIFT (6u) +#define GPIO_P75PFS_PSEL (0x07u) +#define GPIO_P75PFS_PSEL_SHIFT (0u) +#define GPIO_P75PFS_ISEL (0x40u) +#define GPIO_P75PFS_ISEL_SHIFT (6u) +#define GPIO_P76PFS_PSEL (0x07u) +#define GPIO_P76PFS_PSEL_SHIFT (0u) +#define GPIO_P76PFS_ISEL (0x40u) +#define GPIO_P76PFS_ISEL_SHIFT (6u) +#define GPIO_P77PFS_PSEL (0x07u) +#define GPIO_P77PFS_PSEL_SHIFT (0u) +#define GPIO_P77PFS_ISEL (0x40u) +#define GPIO_P77PFS_ISEL_SHIFT (6u) +#define GPIO_P80PFS_PSEL (0x07u) +#define GPIO_P80PFS_PSEL_SHIFT (0u) +#define GPIO_P80PFS_ISEL (0x40u) +#define GPIO_P80PFS_ISEL_SHIFT (6u) +#define GPIO_P81PFS_PSEL (0x07u) +#define GPIO_P81PFS_PSEL_SHIFT (0u) +#define GPIO_P81PFS_ISEL (0x40u) +#define GPIO_P81PFS_ISEL_SHIFT (6u) +#define GPIO_P82PFS_PSEL (0x07u) +#define GPIO_P82PFS_PSEL_SHIFT (0u) +#define GPIO_P82PFS_ISEL (0x40u) +#define GPIO_P82PFS_ISEL_SHIFT (6u) +#define GPIO_P83PFS_PSEL (0x07u) +#define GPIO_P83PFS_PSEL_SHIFT (0u) +#define GPIO_P83PFS_ISEL (0x40u) +#define GPIO_P83PFS_ISEL_SHIFT (6u) +#define GPIO_P84PFS_PSEL (0x07u) +#define GPIO_P84PFS_PSEL_SHIFT (0u) +#define GPIO_P84PFS_ISEL (0x40u) +#define GPIO_P84PFS_ISEL_SHIFT (6u) +#define GPIO_P85PFS_PSEL (0x07u) +#define GPIO_P85PFS_PSEL_SHIFT (0u) +#define GPIO_P85PFS_ISEL (0x40u) +#define GPIO_P85PFS_ISEL_SHIFT (6u) +#define GPIO_P86PFS_PSEL (0x07u) +#define GPIO_P86PFS_PSEL_SHIFT (0u) +#define GPIO_P86PFS_ISEL (0x40u) +#define GPIO_P86PFS_ISEL_SHIFT (6u) +#define GPIO_P87PFS_PSEL (0x07u) +#define GPIO_P87PFS_PSEL_SHIFT (0u) +#define GPIO_P87PFS_ISEL (0x40u) +#define GPIO_P87PFS_ISEL_SHIFT (6u) +#define GPIO_P90PFS_PSEL (0x07u) +#define GPIO_P90PFS_PSEL_SHIFT (0u) +#define GPIO_P90PFS_ISEL (0x40u) +#define GPIO_P90PFS_ISEL_SHIFT (6u) +#define GPIO_P91PFS_PSEL (0x07u) +#define GPIO_P91PFS_PSEL_SHIFT (0u) +#define GPIO_P91PFS_ISEL (0x40u) +#define GPIO_P91PFS_ISEL_SHIFT (6u) +#define GPIO_P92PFS_PSEL (0x07u) +#define GPIO_P92PFS_PSEL_SHIFT (0u) +#define GPIO_P92PFS_ISEL (0x40u) +#define GPIO_P92PFS_ISEL_SHIFT (6u) +#define GPIO_P93PFS_PSEL (0x07u) +#define GPIO_P93PFS_PSEL_SHIFT (0u) +#define GPIO_P93PFS_ISEL (0x40u) +#define GPIO_P93PFS_ISEL_SHIFT (6u) +#define GPIO_P94PFS_PSEL (0x07u) +#define GPIO_P94PFS_PSEL_SHIFT (0u) +#define GPIO_P94PFS_ISEL (0x40u) +#define GPIO_P94PFS_ISEL_SHIFT (6u) +#define GPIO_P95PFS_PSEL (0x07u) +#define GPIO_P95PFS_PSEL_SHIFT (0u) +#define GPIO_P95PFS_ISEL (0x40u) +#define GPIO_P95PFS_ISEL_SHIFT (6u) +#define GPIO_P96PFS_PSEL (0x07u) +#define GPIO_P96PFS_PSEL_SHIFT (0u) +#define GPIO_P96PFS_ISEL (0x40u) +#define GPIO_P96PFS_ISEL_SHIFT (6u) +#define GPIO_P97PFS_PSEL (0x07u) +#define GPIO_P97PFS_PSEL_SHIFT (0u) +#define GPIO_P97PFS_ISEL (0x40u) +#define GPIO_P97PFS_ISEL_SHIFT (6u) +#define GPIO_PA0PFS_PSEL (0x07u) +#define GPIO_PA0PFS_PSEL_SHIFT (0u) +#define GPIO_PA0PFS_ISEL (0x40u) +#define GPIO_PA0PFS_ISEL_SHIFT (6u) +#define GPIO_PA1PFS_PSEL (0x07u) +#define GPIO_PA1PFS_PSEL_SHIFT (0u) +#define GPIO_PA1PFS_ISEL (0x40u) +#define GPIO_PA1PFS_ISEL_SHIFT (6u) +#define GPIO_PA2PFS_PSEL (0x07u) +#define GPIO_PA2PFS_PSEL_SHIFT (0u) +#define GPIO_PA2PFS_ISEL (0x40u) +#define GPIO_PA2PFS_ISEL_SHIFT (6u) +#define GPIO_PA3PFS_PSEL (0x07u) +#define GPIO_PA3PFS_PSEL_SHIFT (0u) +#define GPIO_PA3PFS_ISEL (0x40u) +#define GPIO_PA3PFS_ISEL_SHIFT (6u) +#define GPIO_PA4PFS_PSEL (0x07u) +#define GPIO_PA4PFS_PSEL_SHIFT (0u) +#define GPIO_PA4PFS_ISEL (0x40u) +#define GPIO_PA4PFS_ISEL_SHIFT (6u) +#define GPIO_PA5PFS_PSEL (0x07u) +#define GPIO_PA5PFS_PSEL_SHIFT (0u) +#define GPIO_PA5PFS_ISEL (0x40u) +#define GPIO_PA5PFS_ISEL_SHIFT (6u) +#define GPIO_PA6PFS_PSEL (0x07u) +#define GPIO_PA6PFS_PSEL_SHIFT (0u) +#define GPIO_PA6PFS_ISEL (0x40u) +#define GPIO_PA6PFS_ISEL_SHIFT (6u) +#define GPIO_PA7PFS_PSEL (0x07u) +#define GPIO_PA7PFS_PSEL_SHIFT (0u) +#define GPIO_PA7PFS_ISEL (0x40u) +#define GPIO_PA7PFS_ISEL_SHIFT (6u) +#define GPIO_PB0PFS_PSEL (0x07u) +#define GPIO_PB0PFS_PSEL_SHIFT (0u) +#define GPIO_PB0PFS_ISEL (0x40u) +#define GPIO_PB0PFS_ISEL_SHIFT (6u) +#define GPIO_PB1PFS_PSEL (0x07u) +#define GPIO_PB1PFS_PSEL_SHIFT (0u) +#define GPIO_PB1PFS_ISEL (0x40u) +#define GPIO_PB1PFS_ISEL_SHIFT (6u) +#define GPIO_PB2PFS_PSEL (0x07u) +#define GPIO_PB2PFS_PSEL_SHIFT (0u) +#define GPIO_PB2PFS_ISEL (0x40u) +#define GPIO_PB2PFS_ISEL_SHIFT (6u) +#define GPIO_PB3PFS_PSEL (0x07u) +#define GPIO_PB3PFS_PSEL_SHIFT (0u) +#define GPIO_PB3PFS_ISEL (0x40u) +#define GPIO_PB3PFS_ISEL_SHIFT (6u) +#define GPIO_PB4PFS_PSEL (0x07u) +#define GPIO_PB4PFS_PSEL_SHIFT (0u) +#define GPIO_PB4PFS_ISEL (0x40u) +#define GPIO_PB4PFS_ISEL_SHIFT (6u) +#define GPIO_PB5PFS_PSEL (0x07u) +#define GPIO_PB5PFS_PSEL_SHIFT (0u) +#define GPIO_PB5PFS_ISEL (0x40u) +#define GPIO_PB5PFS_ISEL_SHIFT (6u) +#define GPIO_PC0PFS_PSEL (0x07u) +#define GPIO_PC0PFS_PSEL_SHIFT (0u) +#define GPIO_PC0PFS_ISEL (0x40u) +#define GPIO_PC0PFS_ISEL_SHIFT (6u) +#define GPIO_PC1PFS_PSEL (0x07u) +#define GPIO_PC1PFS_PSEL_SHIFT (0u) +#define GPIO_PC1PFS_ISEL (0x40u) +#define GPIO_PC1PFS_ISEL_SHIFT (6u) +#define GPIO_PC2PFS_PSEL (0x07u) +#define GPIO_PC2PFS_PSEL_SHIFT (0u) +#define GPIO_PC2PFS_ISEL (0x40u) +#define GPIO_PC2PFS_ISEL_SHIFT (6u) +#define GPIO_PC3PFS_PSEL (0x07u) +#define GPIO_PC3PFS_PSEL_SHIFT (0u) +#define GPIO_PC3PFS_ISEL (0x40u) +#define GPIO_PC3PFS_ISEL_SHIFT (6u) +#define GPIO_PC4PFS_PSEL (0x07u) +#define GPIO_PC4PFS_PSEL_SHIFT (0u) +#define GPIO_PC4PFS_ISEL (0x40u) +#define GPIO_PC4PFS_ISEL_SHIFT (6u) +#define GPIO_PC5PFS_PSEL (0x07u) +#define GPIO_PC5PFS_PSEL_SHIFT (0u) +#define GPIO_PC5PFS_ISEL (0x40u) +#define GPIO_PC5PFS_ISEL_SHIFT (6u) +#define GPIO_PC6PFS_PSEL (0x07u) +#define GPIO_PC6PFS_PSEL_SHIFT (0u) +#define GPIO_PC6PFS_ISEL (0x40u) +#define GPIO_PC6PFS_ISEL_SHIFT (6u) +#define GPIO_PC7PFS_PSEL (0x07u) +#define GPIO_PC7PFS_PSEL_SHIFT (0u) +#define GPIO_PC7PFS_ISEL (0x40u) +#define GPIO_PC7PFS_ISEL_SHIFT (6u) +#define GPIO_PD0PFS_PSEL (0x07u) +#define GPIO_PD0PFS_PSEL_SHIFT (0u) +#define GPIO_PD0PFS_ISEL (0x40u) +#define GPIO_PD0PFS_ISEL_SHIFT (6u) +#define GPIO_PD1PFS_PSEL (0x07u) +#define GPIO_PD1PFS_PSEL_SHIFT (0u) +#define GPIO_PD1PFS_ISEL (0x40u) +#define GPIO_PD1PFS_ISEL_SHIFT (6u) +#define GPIO_PD2PFS_PSEL (0x07u) +#define GPIO_PD2PFS_PSEL_SHIFT (0u) +#define GPIO_PD2PFS_ISEL (0x40u) +#define GPIO_PD2PFS_ISEL_SHIFT (6u) +#define GPIO_PD3PFS_PSEL (0x07u) +#define GPIO_PD3PFS_PSEL_SHIFT (0u) +#define GPIO_PD3PFS_ISEL (0x40u) +#define GPIO_PD3PFS_ISEL_SHIFT (6u) +#define GPIO_PD4PFS_PSEL (0x07u) +#define GPIO_PD4PFS_PSEL_SHIFT (0u) +#define GPIO_PD4PFS_ISEL (0x40u) +#define GPIO_PD4PFS_ISEL_SHIFT (6u) +#define GPIO_PD5PFS_PSEL (0x07u) +#define GPIO_PD5PFS_PSEL_SHIFT (0u) +#define GPIO_PD5PFS_ISEL (0x40u) +#define GPIO_PD5PFS_ISEL_SHIFT (6u) +#define GPIO_PD6PFS_PSEL (0x07u) +#define GPIO_PD6PFS_PSEL_SHIFT (0u) +#define GPIO_PD6PFS_ISEL (0x40u) +#define GPIO_PD6PFS_ISEL_SHIFT (6u) +#define GPIO_PD7PFS_PSEL (0x07u) +#define GPIO_PD7PFS_PSEL_SHIFT (0u) +#define GPIO_PD7PFS_ISEL (0x40u) +#define GPIO_PD7PFS_ISEL_SHIFT (6u) +#define GPIO_PE0PFS_PSEL (0x07u) +#define GPIO_PE0PFS_PSEL_SHIFT (0u) +#define GPIO_PE0PFS_ISEL (0x40u) +#define GPIO_PE0PFS_ISEL_SHIFT (6u) +#define GPIO_PE1PFS_PSEL (0x07u) +#define GPIO_PE1PFS_PSEL_SHIFT (0u) +#define GPIO_PE1PFS_ISEL (0x40u) +#define GPIO_PE1PFS_ISEL_SHIFT (6u) +#define GPIO_PE2PFS_PSEL (0x07u) +#define GPIO_PE2PFS_PSEL_SHIFT (0u) +#define GPIO_PE2PFS_ISEL (0x40u) +#define GPIO_PE2PFS_ISEL_SHIFT (6u) +#define GPIO_PE3PFS_PSEL (0x07u) +#define GPIO_PE3PFS_PSEL_SHIFT (0u) +#define GPIO_PE3PFS_ISEL (0x40u) +#define GPIO_PE3PFS_ISEL_SHIFT (6u) +#define GPIO_PE4PFS_PSEL (0x07u) +#define GPIO_PE4PFS_PSEL_SHIFT (0u) +#define GPIO_PE4PFS_ISEL (0x40u) +#define GPIO_PE4PFS_ISEL_SHIFT (6u) +#define GPIO_PE5PFS_PSEL (0x07u) +#define GPIO_PE5PFS_PSEL_SHIFT (0u) +#define GPIO_PE5PFS_ISEL (0x40u) +#define GPIO_PE5PFS_ISEL_SHIFT (6u) +#define GPIO_PE6PFS_PSEL (0x07u) +#define GPIO_PE6PFS_PSEL_SHIFT (0u) +#define GPIO_PE6PFS_ISEL (0x40u) +#define GPIO_PE6PFS_ISEL_SHIFT (6u) +#define GPIO_PF0PFS_PSEL (0x07u) +#define GPIO_PF0PFS_PSEL_SHIFT (0u) +#define GPIO_PF0PFS_ISEL (0x40u) +#define GPIO_PF0PFS_ISEL_SHIFT (6u) +#define GPIO_PF1PFS_PSEL (0x07u) +#define GPIO_PF1PFS_PSEL_SHIFT (0u) +#define GPIO_PF1PFS_ISEL (0x40u) +#define GPIO_PF1PFS_ISEL_SHIFT (6u) +#define GPIO_PF2PFS_PSEL (0x07u) +#define GPIO_PF2PFS_PSEL_SHIFT (0u) +#define GPIO_PF2PFS_ISEL (0x40u) +#define GPIO_PF2PFS_ISEL_SHIFT (6u) +#define GPIO_PF3PFS_PSEL (0x07u) +#define GPIO_PF3PFS_PSEL_SHIFT (0u) +#define GPIO_PF3PFS_ISEL (0x40u) +#define GPIO_PF3PFS_ISEL_SHIFT (6u) +#define GPIO_PF4PFS_PSEL (0x07u) +#define GPIO_PF4PFS_PSEL_SHIFT (0u) +#define GPIO_PF4PFS_ISEL (0x40u) +#define GPIO_PF4PFS_ISEL_SHIFT (6u) +#define GPIO_PF5PFS_PSEL (0x07u) +#define GPIO_PF5PFS_PSEL_SHIFT (0u) +#define GPIO_PF5PFS_ISEL (0x40u) +#define GPIO_PF5PFS_ISEL_SHIFT (6u) +#define GPIO_PF6PFS_PSEL (0x07u) +#define GPIO_PF6PFS_PSEL_SHIFT (0u) +#define GPIO_PF6PFS_ISEL (0x40u) +#define GPIO_PF6PFS_ISEL_SHIFT (6u) +#define GPIO_PF7PFS_PSEL (0x07u) +#define GPIO_PF7PFS_PSEL_SHIFT (0u) +#define GPIO_PF7PFS_ISEL (0x40u) +#define GPIO_PF7PFS_ISEL_SHIFT (6u) +#define GPIO_PG0PFS_PSEL (0x07u) +#define GPIO_PG0PFS_PSEL_SHIFT (0u) +#define GPIO_PG0PFS_ISEL (0x40u) +#define GPIO_PG0PFS_ISEL_SHIFT (6u) +#define GPIO_PG1PFS_PSEL (0x07u) +#define GPIO_PG1PFS_PSEL_SHIFT (0u) +#define GPIO_PG1PFS_ISEL (0x40u) +#define GPIO_PG1PFS_ISEL_SHIFT (6u) +#define GPIO_PG2PFS_PSEL (0x07u) +#define GPIO_PG2PFS_PSEL_SHIFT (0u) +#define GPIO_PG2PFS_ISEL (0x40u) +#define GPIO_PG2PFS_ISEL_SHIFT (6u) +#define GPIO_PG3PFS_PSEL (0x07u) +#define GPIO_PG3PFS_PSEL_SHIFT (0u) +#define GPIO_PG3PFS_ISEL (0x40u) +#define GPIO_PG3PFS_ISEL_SHIFT (6u) +#define GPIO_PG4PFS_PSEL (0x07u) +#define GPIO_PG4PFS_PSEL_SHIFT (0u) +#define GPIO_PG4PFS_ISEL (0x40u) +#define GPIO_PG4PFS_ISEL_SHIFT (6u) +#define GPIO_PG5PFS_PSEL (0x07u) +#define GPIO_PG5PFS_PSEL_SHIFT (0u) +#define GPIO_PG5PFS_ISEL (0x40u) +#define GPIO_PG5PFS_ISEL_SHIFT (6u) +#define GPIO_PG6PFS_PSEL (0x07u) +#define GPIO_PG6PFS_PSEL_SHIFT (0u) +#define GPIO_PG6PFS_ISEL (0x40u) +#define GPIO_PG6PFS_ISEL_SHIFT (6u) +#define GPIO_PG7PFS_PSEL (0x07u) +#define GPIO_PG7PFS_PSEL_SHIFT (0u) +#define GPIO_PG7PFS_ISEL (0x40u) +#define GPIO_PG7PFS_ISEL_SHIFT (6u) +#define GPIO_PH0PFS_PSEL (0x07u) +#define GPIO_PH0PFS_PSEL_SHIFT (0u) +#define GPIO_PH0PFS_ISEL (0x40u) +#define GPIO_PH0PFS_ISEL_SHIFT (6u) +#define GPIO_PH1PFS_PSEL (0x07u) +#define GPIO_PH1PFS_PSEL_SHIFT (0u) +#define GPIO_PH1PFS_ISEL (0x40u) +#define GPIO_PH1PFS_ISEL_SHIFT (6u) +#define GPIO_PH2PFS_PSEL (0x07u) +#define GPIO_PH2PFS_PSEL_SHIFT (0u) +#define GPIO_PH2PFS_ISEL (0x40u) +#define GPIO_PH2PFS_ISEL_SHIFT (6u) +#define GPIO_PH3PFS_PSEL (0x07u) +#define GPIO_PH3PFS_PSEL_SHIFT (0u) +#define GPIO_PH3PFS_ISEL (0x40u) +#define GPIO_PH3PFS_ISEL_SHIFT (6u) +#define GPIO_PH4PFS_PSEL (0x07u) +#define GPIO_PH4PFS_PSEL_SHIFT (0u) +#define GPIO_PH4PFS_ISEL (0x40u) +#define GPIO_PH4PFS_ISEL_SHIFT (6u) +#define GPIO_PH5PFS_PSEL (0x07u) +#define GPIO_PH5PFS_PSEL_SHIFT (0u) +#define GPIO_PH5PFS_ISEL (0x40u) +#define GPIO_PH5PFS_ISEL_SHIFT (6u) +#define GPIO_PH6PFS_PSEL (0x07u) +#define GPIO_PH6PFS_PSEL_SHIFT (0u) +#define GPIO_PH6PFS_ISEL (0x40u) +#define GPIO_PH6PFS_ISEL_SHIFT (6u) +#define GPIO_PJ0PFS_PSEL (0x07u) +#define GPIO_PJ0PFS_PSEL_SHIFT (0u) +#define GPIO_PJ0PFS_ISEL (0x40u) +#define GPIO_PJ0PFS_ISEL_SHIFT (6u) +#define GPIO_PJ1PFS_PSEL (0x07u) +#define GPIO_PJ1PFS_PSEL_SHIFT (0u) +#define GPIO_PJ1PFS_ISEL (0x40u) +#define GPIO_PJ1PFS_ISEL_SHIFT (6u) +#define GPIO_PJ2PFS_PSEL (0x07u) +#define GPIO_PJ2PFS_PSEL_SHIFT (0u) +#define GPIO_PJ2PFS_ISEL (0x40u) +#define GPIO_PJ2PFS_ISEL_SHIFT (6u) +#define GPIO_PJ3PFS_PSEL (0x07u) +#define GPIO_PJ3PFS_PSEL_SHIFT (0u) +#define GPIO_PJ3PFS_ISEL (0x40u) +#define GPIO_PJ3PFS_ISEL_SHIFT (6u) +#define GPIO_PJ4PFS_PSEL (0x07u) +#define GPIO_PJ4PFS_PSEL_SHIFT (0u) +#define GPIO_PJ4PFS_ISEL (0x40u) +#define GPIO_PJ4PFS_ISEL_SHIFT (6u) +#define GPIO_PJ5PFS_PSEL (0x07u) +#define GPIO_PJ5PFS_PSEL_SHIFT (0u) +#define GPIO_PJ5PFS_ISEL (0x40u) +#define GPIO_PJ5PFS_ISEL_SHIFT (6u) +#define GPIO_PJ6PFS_PSEL (0x07u) +#define GPIO_PJ6PFS_PSEL_SHIFT (0u) +#define GPIO_PJ6PFS_ISEL (0x40u) +#define GPIO_PJ6PFS_ISEL_SHIFT (6u) +#define GPIO_PJ7PFS_PSEL (0x07u) +#define GPIO_PJ7PFS_PSEL_SHIFT (0u) +#define GPIO_PJ7PFS_ISEL (0x40u) +#define GPIO_PJ7PFS_ISEL_SHIFT (6u) +#define GPIO_PK0PFS_PSEL (0x07u) +#define GPIO_PK0PFS_PSEL_SHIFT (0u) +#define GPIO_PK0PFS_ISEL (0x40u) +#define GPIO_PK0PFS_ISEL_SHIFT (6u) +#define GPIO_PK1PFS_PSEL (0x07u) +#define GPIO_PK1PFS_PSEL_SHIFT (0u) +#define GPIO_PK1PFS_ISEL (0x40u) +#define GPIO_PK1PFS_ISEL_SHIFT (6u) +#define GPIO_PK2PFS_PSEL (0x07u) +#define GPIO_PK2PFS_PSEL_SHIFT (0u) +#define GPIO_PK2PFS_ISEL (0x40u) +#define GPIO_PK2PFS_ISEL_SHIFT (6u) +#define GPIO_PK3PFS_PSEL (0x07u) +#define GPIO_PK3PFS_PSEL_SHIFT (0u) +#define GPIO_PK3PFS_ISEL (0x40u) +#define GPIO_PK3PFS_ISEL_SHIFT (6u) +#define GPIO_PK4PFS_PSEL (0x07u) +#define GPIO_PK4PFS_PSEL_SHIFT (0u) +#define GPIO_PK4PFS_ISEL (0x40u) +#define GPIO_PK4PFS_ISEL_SHIFT (6u) +#define GPIO_PK5PFS_PSEL (0x07u) +#define GPIO_PK5PFS_PSEL_SHIFT (0u) +#define GPIO_PK5PFS_ISEL (0x40u) +#define GPIO_PK5PFS_ISEL_SHIFT (6u) +#define GPIO_PL0PFS_PSEL (0x07u) +#define GPIO_PL0PFS_PSEL_SHIFT (0u) +#define GPIO_PL0PFS_ISEL (0x40u) +#define GPIO_PL0PFS_ISEL_SHIFT (6u) +#define GPIO_PL1PFS_PSEL (0x07u) +#define GPIO_PL1PFS_PSEL_SHIFT (0u) +#define GPIO_PL1PFS_ISEL (0x40u) +#define GPIO_PL1PFS_ISEL_SHIFT (6u) +#define GPIO_PL2PFS_PSEL (0x07u) +#define GPIO_PL2PFS_PSEL_SHIFT (0u) +#define GPIO_PL2PFS_ISEL (0x40u) +#define GPIO_PL2PFS_ISEL_SHIFT (6u) +#define GPIO_PL3PFS_PSEL (0x07u) +#define GPIO_PL3PFS_PSEL_SHIFT (0u) +#define GPIO_PL3PFS_ISEL (0x40u) +#define GPIO_PL3PFS_ISEL_SHIFT (6u) +#define GPIO_PL4PFS_PSEL (0x07u) +#define GPIO_PL4PFS_PSEL_SHIFT (0u) +#define GPIO_PL4PFS_ISEL (0x40u) +#define GPIO_PL4PFS_ISEL_SHIFT (6u) +#define GPIO_PM0PFS_PSEL (0x07u) +#define GPIO_PM0PFS_PSEL_SHIFT (0u) +#define GPIO_PM0PFS_ISEL (0x40u) +#define GPIO_PM0PFS_ISEL_SHIFT (6u) +#define GPIO_PM1PFS_PSEL (0x07u) +#define GPIO_PM1PFS_PSEL_SHIFT (0u) +#define GPIO_PM1PFS_ISEL (0x40u) +#define GPIO_PM1PFS_ISEL_SHIFT (6u) +#define GPIO_PWPR_PFSWE (0x40u) +#define GPIO_PWPR_PFSWE_SHIFT (6u) +#define GPIO_PWPR_B0WI (0x80u) +#define GPIO_PWPR_B0WI_SHIFT (7u) +#define GPIO_PFENET_PHYMODE0 (0x01u) +#define GPIO_PFENET_PHYMODE0_SHIFT (0u) +#define GPIO_PFENET_PHYMODE1 (0x02u) +#define GPIO_PFENET_PHYMODE1_SHIFT (1u) +#define GPIO_PPOC_POC0 (0x00000001u) +#define GPIO_PPOC_POC0_SHIFT (0u) +#define GPIO_PPOC_POC2 (0x00000004u) +#define GPIO_PPOC_POC2_SHIFT (2u) +#define GPIO_PPOC_POC3 (0x00000008u) +#define GPIO_PPOC_POC3_SHIFT (3u) +#define GPIO_PPOC_POCSEL0 (0x00000100u) +#define GPIO_PPOC_POCSEL0_SHIFT (8u) +#define GPIO_PSDMMC0_SD0_CLK_DRV (0x00000003u) +#define GPIO_PSDMMC0_SD0_CLK_DRV_SHIFT (0u) +#define GPIO_PSDMMC0_SD0_CMD_DRV (0x0000000Cu) +#define GPIO_PSDMMC0_SD0_CMD_DRV_SHIFT (2u) +#define GPIO_PSDMMC0_SD0_DAT0_DRV (0x00000030u) +#define GPIO_PSDMMC0_SD0_DAT0_DRV_SHIFT (4u) +#define GPIO_PSDMMC0_SD0_DAT1_DRV (0x000000C0u) +#define GPIO_PSDMMC0_SD0_DAT1_DRV_SHIFT (6u) +#define GPIO_PSDMMC0_SD0_DAT2_DRV (0x00000300u) +#define GPIO_PSDMMC0_SD0_DAT2_DRV_SHIFT (8u) +#define GPIO_PSDMMC0_SD0_DAT3_DRV (0x00000C00u) +#define GPIO_PSDMMC0_SD0_DAT3_DRV_SHIFT (10u) +#define GPIO_PSDMMC0_SD0_CLK_TDSEL (0x00003000u) +#define GPIO_PSDMMC0_SD0_CLK_TDSEL_SHIFT (12u) +#define GPIO_PSDMMC1_SD0_DAT4_DRV (0x00000003u) +#define GPIO_PSDMMC1_SD0_DAT4_DRV_SHIFT (0u) +#define GPIO_PSDMMC1_SD0_DAT5_DRV (0x0000000Cu) +#define GPIO_PSDMMC1_SD0_DAT5_DRV_SHIFT (2u) +#define GPIO_PSDMMC1_SD0_DAT6_DRV (0x00000030u) +#define GPIO_PSDMMC1_SD0_DAT6_DRV_SHIFT (4u) +#define GPIO_PSDMMC1_SD0_DAT7_DRV (0x000000C0u) +#define GPIO_PSDMMC1_SD0_DAT7_DRV_SHIFT (6u) +#define GPIO_PSDMMC1_SD0_RSTN_DRV (0x00000300u) +#define GPIO_PSDMMC1_SD0_RSTN_DRV_SHIFT (8u) +#define GPIO_PSDMMC2_SD1_CLK_DRV (0x00000003u) +#define GPIO_PSDMMC2_SD1_CLK_DRV_SHIFT (0u) +#define GPIO_PSDMMC2_SD1_CMD_DRV (0x0000000Cu) +#define GPIO_PSDMMC2_SD1_CMD_DRV_SHIFT (2u) +#define GPIO_PSDMMC2_SD1_DAT0_DRV (0x00000030u) +#define GPIO_PSDMMC2_SD1_DAT0_DRV_SHIFT (4u) +#define GPIO_PSDMMC2_SD1_DAT1_DRV (0x000000C0u) +#define GPIO_PSDMMC2_SD1_DAT1_DRV_SHIFT (6u) +#define GPIO_PSDMMC2_SD1_DAT2_DRV (0x00000300u) +#define GPIO_PSDMMC2_SD1_DAT2_DRV_SHIFT (8u) +#define GPIO_PSDMMC2_SD1_DAT3_DRV (0x00000C00u) +#define GPIO_PSDMMC2_SD1_DAT3_DRV_SHIFT (10u) +#define GPIO_PSDMMC2_SD1_CLK_TDSEL (0x00003000u) +#define GPIO_PSDMMC2_SD1_CLK_TDSEL_SHIFT (12u) +#define GPIO_PSPIBSC_QSPI0_SPCLK_DRV (0x00000003u) +#define GPIO_PSPIBSC_QSPI0_SPCLK_DRV_SHIFT (0u) +#define GPIO_PSPIBSC_QSPI0_IO0_DRV (0x0000000Cu) +#define GPIO_PSPIBSC_QSPI0_IO0_DRV_SHIFT (2u) +#define GPIO_PSPIBSC_QSPI0_IO1_DRV (0x00000030u) +#define GPIO_PSPIBSC_QSPI0_IO1_DRV_SHIFT (4u) +#define GPIO_PSPIBSC_QSPI0_IO2_DRV (0x000000C0u) +#define GPIO_PSPIBSC_QSPI0_IO2_DRV_SHIFT (6u) +#define GPIO_PSPIBSC_QSPI0_IO3_DRV (0x00000300u) +#define GPIO_PSPIBSC_QSPI0_IO3_DRV_SHIFT (8u) +#define GPIO_PSPIBSC_QSPI0_SSL_DRV (0x00000C00u) +#define GPIO_PSPIBSC_QSPI0_SSL_DRV_SHIFT (10u) +#define GPIO_PSPIBSC_RPC_RESETN_DRV (0x00003000u) +#define GPIO_PSPIBSC_RPC_RESETN_DRV_SHIFT (12u) +#define GPIO_PSPIBSC_RPC_WPN_DRV (0x0000C000u) +#define GPIO_PSPIBSC_RPC_WPN_DRV_SHIFT (14u) +#define GPIO_PSPIBSC_QSPI1_SPCLK_DRV (0x00030000u) +#define GPIO_PSPIBSC_QSPI1_SPCLK_DRV_SHIFT (16u) +#define GPIO_PSPIBSC_QSPI1_IO0_DRV (0x000C0000u) +#define GPIO_PSPIBSC_QSPI1_IO0_DRV_SHIFT (18u) +#define GPIO_PSPIBSC_QSPI1_IO1_DRV (0x00300000u) +#define GPIO_PSPIBSC_QSPI1_IO1_DRV_SHIFT (20u) +#define GPIO_PSPIBSC_QSPI1_IO2_DRV (0x00C00000u) +#define GPIO_PSPIBSC_QSPI1_IO2_DRV_SHIFT (22u) +#define GPIO_PSPIBSC_QSPI1_IO3_DRV (0x03000000u) +#define GPIO_PSPIBSC_QSPI1_IO3_DRV_SHIFT (24u) +#define GPIO_PSPIBSC_QSPI1_SSL_DRV (0x0C000000u) +#define GPIO_PSPIBSC_QSPI1_SSL_DRV_SHIFT (26u) +#define GPIO_PHMOM0_HOSEL (0x00000001u) +#define GPIO_PHMOM0_HOSEL_SHIFT (0u) +#define GPIO_PMODEPFS_ET0_EXOUT_SEL (0x00000001u) +#define GPIO_PMODEPFS_ET0_EXOUT_SEL_SHIFT (0u) +#define GPIO_PMODEPFS_ET1_EXOUT_SEL (0x00000002u) +#define GPIO_PMODEPFS_ET1_EXOUT_SEL_SHIFT (1u) +#define GPIO_PMODEPFS_VBUS0_SEL (0x00000004u) +#define GPIO_PMODEPFS_VBUS0_SEL_SHIFT (2u) +#define GPIO_PMODEPFS_VBUS1_SEL (0x00000008u) +#define GPIO_PMODEPFS_VBUS1_SEL_SHIFT (3u) +#define GPIO_PCKIO_CKIO_DRV (0x03u) +#define GPIO_PCKIO_CKIO_DRV_SHIFT (0u) +#define GPIO_PDR_PDR0 (0x0003u) +#define GPIO_PDR_PDR0_SHIFT (0u) +#define GPIO_PDR_PDR1 (0x000Cu) +#define GPIO_PDR_PDR1_SHIFT (2u) +#define GPIO_PDR_PDR2 (0x0030u) +#define GPIO_PDR_PDR2_SHIFT (4u) +#define GPIO_PDR_PDR3 (0x00C0u) +#define GPIO_PDR_PDR3_SHIFT (6u) +#define GPIO_PDR_PDR4 (0x0300u) +#define GPIO_PDR_PDR4_SHIFT (8u) +#define GPIO_PDR_PDR5 (0x0C00u) +#define GPIO_PDR_PDR5_SHIFT (10u) +#define GPIO_PDR_PDR6 (0x3000u) +#define GPIO_PDR_PDR6_SHIFT (12u) +#define GPIO_PODR_PODR0 (0x01u) +#define GPIO_PODR_PODR0_SHIFT (0u) +#define GPIO_PODR_PODR1 (0x02u) +#define GPIO_PODR_PODR1_SHIFT (1u) +#define GPIO_PODR_PODR2 (0x04u) +#define GPIO_PODR_PODR2_SHIFT (2u) +#define GPIO_PODR_PODR3 (0x08u) +#define GPIO_PODR_PODR3_SHIFT (3u) +#define GPIO_PODR_PODR4 (0x10u) +#define GPIO_PODR_PODR4_SHIFT (4u) +#define GPIO_PODR_PODR5 (0x20u) +#define GPIO_PODR_PODR5_SHIFT (5u) +#define GPIO_PODR_PODR6 (0x40u) +#define GPIO_PODR_PODR6_SHIFT (6u) +#define GPIO_PIDR_PIDR0 (0x01u) +#define GPIO_PIDR_PIDR0_SHIFT (0u) +#define GPIO_PIDR_PIDR1 (0x02u) +#define GPIO_PIDR_PIDR1_SHIFT (1u) +#define GPIO_PIDR_PIDR2 (0x04u) +#define GPIO_PIDR_PIDR2_SHIFT (2u) +#define GPIO_PIDR_PIDR3 (0x08u) +#define GPIO_PIDR_PIDR3_SHIFT (3u) +#define GPIO_PIDR_PIDR4 (0x10u) +#define GPIO_PIDR_PIDR4_SHIFT (4u) +#define GPIO_PIDR_PIDR5 (0x20u) +#define GPIO_PIDR_PIDR5_SHIFT (5u) +#define GPIO_PIDR_PIDR6 (0x40u) +#define GPIO_PIDR_PIDR6_SHIFT (6u) +#define GPIO_PMR_PMR0 (0x01u) +#define GPIO_PMR_PMR0_SHIFT (0u) +#define GPIO_PMR_PMR1 (0x02u) +#define GPIO_PMR_PMR1_SHIFT (1u) +#define GPIO_PMR_PMR2 (0x04u) +#define GPIO_PMR_PMR2_SHIFT (2u) +#define GPIO_PMR_PMR3 (0x08u) +#define GPIO_PMR_PMR3_SHIFT (3u) +#define GPIO_PMR_PMR4 (0x10u) +#define GPIO_PMR_PMR4_SHIFT (4u) +#define GPIO_PMR_PMR5 (0x20u) +#define GPIO_PMR_PMR5_SHIFT (5u) +#define GPIO_PMR_PMR6 (0x40u) +#define GPIO_PMR_PMR6_SHIFT (6u) +#define GPIO_DSCR_DSCR0 (0x0003u) +#define GPIO_DSCR_DSCR0_SHIFT (0u) +#define GPIO_DSCR_DSCR1 (0x000Cu) +#define GPIO_DSCR_DSCR1_SHIFT (2u) +#define GPIO_DSCR_DSCR2 (0x0030u) +#define GPIO_DSCR_DSCR2_SHIFT (4u) +#define GPIO_DSCR_DSCR3 (0x00C0u) +#define GPIO_DSCR_DSCR3_SHIFT (6u) +#define GPIO_DSCR_DSCR4 (0x0300u) +#define GPIO_DSCR_DSCR4_SHIFT (8u) +#define GPIO_DSCR_DSCR5 (0x0C00u) +#define GPIO_DSCR_DSCR5_SHIFT (10u) +#define GPIO_DSCR_DSCR6 (0x3000u) +#define GPIO_DSCR_DSCR6_SHIFT (12u) +#define GPIO_PDR_PDR7 (0xC000u) +#define GPIO_PDR_PDR7_SHIFT (14u) +#define GPIO_PODR_PODR7 (0x80u) +#define GPIO_PODR_PODR7_SHIFT (7u) +#define GPIO_PIDR_PIDR7 (0x80u) +#define GPIO_PIDR_PIDR7_SHIFT (7u) +#define GPIO_PMR_PMR7 (0x80u) +#define GPIO_PMR_PMR7_SHIFT (7u) +#define GPIO_DSCR_DSCR7 (0xC000u) +#define GPIO_DSCR_DSCR7_SHIFT (14u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpt_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpt_iobitmask.h new file mode 100644 index 0000000..e2496d5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/gpt_iobitmask.h @@ -0,0 +1,668 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef GPT_IOBITMASK_H +#define GPT_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define GPT_GTECR_EVCON (0x80u) +#define GPT_GTECR_EVCON_SHIFT (7u) +#define GPT_GTESR0_EVS (0x007Fu) +#define GPT_GTESR0_EVS_SHIFT (0u) +#define GPT_GTESR1_EVS (0x007Fu) +#define GPT_GTESR1_EVS_SHIFT (0u) +#define GPT_GTESR2_EVS (0x007Fu) +#define GPT_GTESR2_EVS_SHIFT (0u) +#define GPT_GTESR3_EVS (0x007Fu) +#define GPT_GTESR3_EVS_SHIFT (0u) +#define GPT_GTESR4_EVS (0x007Fu) +#define GPT_GTESR4_EVS_SHIFT (0u) +#define GPT_GTESR5_EVS (0x007Fu) +#define GPT_GTESR5_EVS_SHIFT (0u) +#define GPT_GTESR6_EVS (0x007Fu) +#define GPT_GTESR6_EVS_SHIFT (0u) +#define GPT_GTESR7_EVS (0x007Fu) +#define GPT_GTESR7_EVS_SHIFT (0u) +#define GPT_GTWP_WP (0x00000001u) +#define GPT_GTWP_WP_SHIFT (0u) +#define GPT_GTWP_PRKEY (0x0000FF00u) +#define GPT_GTWP_PRKEY_SHIFT (8u) +#define GPT_GTSTR_CSTRT0 (0x00000001u) +#define GPT_GTSTR_CSTRT0_SHIFT (0u) +#define GPT_GTSTR_CSTRT1 (0x00000002u) +#define GPT_GTSTR_CSTRT1_SHIFT (1u) +#define GPT_GTSTR_CSTRT2 (0x00000004u) +#define GPT_GTSTR_CSTRT2_SHIFT (2u) +#define GPT_GTSTR_CSTRT3 (0x00000008u) +#define GPT_GTSTR_CSTRT3_SHIFT (3u) +#define GPT_GTSTR_CSTRT4 (0x00000010u) +#define GPT_GTSTR_CSTRT4_SHIFT (4u) +#define GPT_GTSTR_CSTRT5 (0x00000020u) +#define GPT_GTSTR_CSTRT5_SHIFT (5u) +#define GPT_GTSTR_CSTRT6 (0x00000040u) +#define GPT_GTSTR_CSTRT6_SHIFT (6u) +#define GPT_GTSTR_CSTRT7 (0x00000080u) +#define GPT_GTSTR_CSTRT7_SHIFT (7u) +#define GPT_GTSTP_CSTOP0 (0x00000001u) +#define GPT_GTSTP_CSTOP0_SHIFT (0u) +#define GPT_GTSTP_CSTOP1 (0x00000002u) +#define GPT_GTSTP_CSTOP1_SHIFT (1u) +#define GPT_GTSTP_CSTOP2 (0x00000004u) +#define GPT_GTSTP_CSTOP2_SHIFT (2u) +#define GPT_GTSTP_CSTOP3 (0x00000008u) +#define GPT_GTSTP_CSTOP3_SHIFT (3u) +#define GPT_GTSTP_CSTOP4 (0x00000010u) +#define GPT_GTSTP_CSTOP4_SHIFT (4u) +#define GPT_GTSTP_CSTOP5 (0x00000020u) +#define GPT_GTSTP_CSTOP5_SHIFT (5u) +#define GPT_GTSTP_CSTOP6 (0x00000040u) +#define GPT_GTSTP_CSTOP6_SHIFT (6u) +#define GPT_GTSTP_CSTOP7 (0x00000080u) +#define GPT_GTSTP_CSTOP7_SHIFT (7u) +#define GPT_GTCLR_CCLR0 (0x00000001u) +#define GPT_GTCLR_CCLR0_SHIFT (0u) +#define GPT_GTCLR_CCLR1 (0x00000002u) +#define GPT_GTCLR_CCLR1_SHIFT (1u) +#define GPT_GTCLR_CCLR2 (0x00000004u) +#define GPT_GTCLR_CCLR2_SHIFT (2u) +#define GPT_GTCLR_CCLR3 (0x00000008u) +#define GPT_GTCLR_CCLR3_SHIFT (3u) +#define GPT_GTCLR_CCLR4 (0x00000010u) +#define GPT_GTCLR_CCLR4_SHIFT (4u) +#define GPT_GTCLR_CCLR5 (0x00000020u) +#define GPT_GTCLR_CCLR5_SHIFT (5u) +#define GPT_GTCLR_CCLR6 (0x00000040u) +#define GPT_GTCLR_CCLR6_SHIFT (6u) +#define GPT_GTCLR_CCLR7 (0x00000080u) +#define GPT_GTCLR_CCLR7_SHIFT (7u) +#define GPT_GTSSR_SSGTRGAR (0x00000001u) +#define GPT_GTSSR_SSGTRGAR_SHIFT (0u) +#define GPT_GTSSR_SSGTRGAF (0x00000002u) +#define GPT_GTSSR_SSGTRGAF_SHIFT (1u) +#define GPT_GTSSR_SSGTRGBR (0x00000004u) +#define GPT_GTSSR_SSGTRGBR_SHIFT (2u) +#define GPT_GTSSR_SSGTRGBF (0x00000008u) +#define GPT_GTSSR_SSGTRGBF_SHIFT (3u) +#define GPT_GTSSR_SSGTRGCR (0x00000010u) +#define GPT_GTSSR_SSGTRGCR_SHIFT (4u) +#define GPT_GTSSR_SSGTRGCF (0x00000020u) +#define GPT_GTSSR_SSGTRGCF_SHIFT (5u) +#define GPT_GTSSR_SSGTRGDR (0x00000040u) +#define GPT_GTSSR_SSGTRGDR_SHIFT (6u) +#define GPT_GTSSR_SSGTRGDF (0x00000080u) +#define GPT_GTSSR_SSGTRGDF_SHIFT (7u) +#define GPT_GTSSR_SSCARBL (0x00000100u) +#define GPT_GTSSR_SSCARBL_SHIFT (8u) +#define GPT_GTSSR_SSCARBH (0x00000200u) +#define GPT_GTSSR_SSCARBH_SHIFT (9u) +#define GPT_GTSSR_SSCAFBL (0x00000400u) +#define GPT_GTSSR_SSCAFBL_SHIFT (10u) +#define GPT_GTSSR_SSCAFBH (0x00000800u) +#define GPT_GTSSR_SSCAFBH_SHIFT (11u) +#define GPT_GTSSR_SSCBRAL (0x00001000u) +#define GPT_GTSSR_SSCBRAL_SHIFT (12u) +#define GPT_GTSSR_SSCBRAH (0x00002000u) +#define GPT_GTSSR_SSCBRAH_SHIFT (13u) +#define GPT_GTSSR_SSCBFAL (0x00004000u) +#define GPT_GTSSR_SSCBFAL_SHIFT (14u) +#define GPT_GTSSR_SSCBFAH (0x00008000u) +#define GPT_GTSSR_SSCBFAH_SHIFT (15u) +#define GPT_GTSSR_SSEVTA (0x00010000u) +#define GPT_GTSSR_SSEVTA_SHIFT (16u) +#define GPT_GTSSR_SSEVTB (0x00020000u) +#define GPT_GTSSR_SSEVTB_SHIFT (17u) +#define GPT_GTSSR_SSEVTC (0x00040000u) +#define GPT_GTSSR_SSEVTC_SHIFT (18u) +#define GPT_GTSSR_SSEVTD (0x00080000u) +#define GPT_GTSSR_SSEVTD_SHIFT (19u) +#define GPT_GTSSR_SSEVTE (0x00100000u) +#define GPT_GTSSR_SSEVTE_SHIFT (20u) +#define GPT_GTSSR_SSEVTF (0x00200000u) +#define GPT_GTSSR_SSEVTF_SHIFT (21u) +#define GPT_GTSSR_SSEVTG (0x00400000u) +#define GPT_GTSSR_SSEVTG_SHIFT (22u) +#define GPT_GTSSR_SSEVTH (0x00800000u) +#define GPT_GTSSR_SSEVTH_SHIFT (23u) +#define GPT_GTSSR_CSTRT (0x80000000u) +#define GPT_GTSSR_CSTRT_SHIFT (31u) +#define GPT_GTPSR_PSGTRGAR (0x00000001u) +#define GPT_GTPSR_PSGTRGAR_SHIFT (0u) +#define GPT_GTPSR_PSGTRGAF (0x00000002u) +#define GPT_GTPSR_PSGTRGAF_SHIFT (1u) +#define GPT_GTPSR_PSGTRGBR (0x00000004u) +#define GPT_GTPSR_PSGTRGBR_SHIFT (2u) +#define GPT_GTPSR_PSGTRGBF (0x00000008u) +#define GPT_GTPSR_PSGTRGBF_SHIFT (3u) +#define GPT_GTPSR_PSGTRGCR (0x00000010u) +#define GPT_GTPSR_PSGTRGCR_SHIFT (4u) +#define GPT_GTPSR_PSGTRGCF (0x00000020u) +#define GPT_GTPSR_PSGTRGCF_SHIFT (5u) +#define GPT_GTPSR_PSGTRGDR (0x00000040u) +#define GPT_GTPSR_PSGTRGDR_SHIFT (6u) +#define GPT_GTPSR_PSGTRGDF (0x00000080u) +#define GPT_GTPSR_PSGTRGDF_SHIFT (7u) +#define GPT_GTPSR_PSCARBL (0x00000100u) +#define GPT_GTPSR_PSCARBL_SHIFT (8u) +#define GPT_GTPSR_PSCARBH (0x00000200u) +#define GPT_GTPSR_PSCARBH_SHIFT (9u) +#define GPT_GTPSR_PSCAFBL (0x00000400u) +#define GPT_GTPSR_PSCAFBL_SHIFT (10u) +#define GPT_GTPSR_PSCAFBH (0x00000800u) +#define GPT_GTPSR_PSCAFBH_SHIFT (11u) +#define GPT_GTPSR_PSCBRAL (0x00001000u) +#define GPT_GTPSR_PSCBRAL_SHIFT (12u) +#define GPT_GTPSR_PSCBRAH (0x00002000u) +#define GPT_GTPSR_PSCBRAH_SHIFT (13u) +#define GPT_GTPSR_PSCBFAL (0x00004000u) +#define GPT_GTPSR_PSCBFAL_SHIFT (14u) +#define GPT_GTPSR_PSCBFAH (0x00008000u) +#define GPT_GTPSR_PSCBFAH_SHIFT (15u) +#define GPT_GTPSR_PSEVTA (0x00010000u) +#define GPT_GTPSR_PSEVTA_SHIFT (16u) +#define GPT_GTPSR_PSEVTB (0x00020000u) +#define GPT_GTPSR_PSEVTB_SHIFT (17u) +#define GPT_GTPSR_PSEVTC (0x00040000u) +#define GPT_GTPSR_PSEVTC_SHIFT (18u) +#define GPT_GTPSR_PSEVTD (0x00080000u) +#define GPT_GTPSR_PSEVTD_SHIFT (19u) +#define GPT_GTPSR_PSEVTE (0x00100000u) +#define GPT_GTPSR_PSEVTE_SHIFT (20u) +#define GPT_GTPSR_PSEVTF (0x00200000u) +#define GPT_GTPSR_PSEVTF_SHIFT (21u) +#define GPT_GTPSR_PSEVTG (0x00400000u) +#define GPT_GTPSR_PSEVTG_SHIFT (22u) +#define GPT_GTPSR_PSEVTH (0x00800000u) +#define GPT_GTPSR_PSEVTH_SHIFT (23u) +#define GPT_GTPSR_CSTOP (0x80000000u) +#define GPT_GTPSR_CSTOP_SHIFT (31u) +#define GPT_GTCSR_CSGTRGAR (0x00000001u) +#define GPT_GTCSR_CSGTRGAR_SHIFT (0u) +#define GPT_GTCSR_CSGTRGAF (0x00000002u) +#define GPT_GTCSR_CSGTRGAF_SHIFT (1u) +#define GPT_GTCSR_CSGTRGBR (0x00000004u) +#define GPT_GTCSR_CSGTRGBR_SHIFT (2u) +#define GPT_GTCSR_CSGTRGBF (0x00000008u) +#define GPT_GTCSR_CSGTRGBF_SHIFT (3u) +#define GPT_GTCSR_CSGTRGCR (0x00000010u) +#define GPT_GTCSR_CSGTRGCR_SHIFT (4u) +#define GPT_GTCSR_CSGTRGCF (0x00000020u) +#define GPT_GTCSR_CSGTRGCF_SHIFT (5u) +#define GPT_GTCSR_CSGTRGDR (0x00000040u) +#define GPT_GTCSR_CSGTRGDR_SHIFT (6u) +#define GPT_GTCSR_CSGTRGDF (0x00000080u) +#define GPT_GTCSR_CSGTRGDF_SHIFT (7u) +#define GPT_GTCSR_CSCARBL (0x00000100u) +#define GPT_GTCSR_CSCARBL_SHIFT (8u) +#define GPT_GTCSR_CSCARBH (0x00000200u) +#define GPT_GTCSR_CSCARBH_SHIFT (9u) +#define GPT_GTCSR_CSCAFBL (0x00000400u) +#define GPT_GTCSR_CSCAFBL_SHIFT (10u) +#define GPT_GTCSR_CSCAFBH (0x00000800u) +#define GPT_GTCSR_CSCAFBH_SHIFT (11u) +#define GPT_GTCSR_CSCBRAL (0x00001000u) +#define GPT_GTCSR_CSCBRAL_SHIFT (12u) +#define GPT_GTCSR_CSCBRAH (0x00002000u) +#define GPT_GTCSR_CSCBRAH_SHIFT (13u) +#define GPT_GTCSR_CSCBFAL (0x00004000u) +#define GPT_GTCSR_CSCBFAL_SHIFT (14u) +#define GPT_GTCSR_CSCBFAH (0x00008000u) +#define GPT_GTCSR_CSCBFAH_SHIFT (15u) +#define GPT_GTCSR_CSEVTA (0x00010000u) +#define GPT_GTCSR_CSEVTA_SHIFT (16u) +#define GPT_GTCSR_CSEVTB (0x00020000u) +#define GPT_GTCSR_CSEVTB_SHIFT (17u) +#define GPT_GTCSR_CSEVTC (0x00040000u) +#define GPT_GTCSR_CSEVTC_SHIFT (18u) +#define GPT_GTCSR_CSEVTD (0x00080000u) +#define GPT_GTCSR_CSEVTD_SHIFT (19u) +#define GPT_GTCSR_CSEVTE (0x00100000u) +#define GPT_GTCSR_CSEVTE_SHIFT (20u) +#define GPT_GTCSR_CSEVTF (0x00200000u) +#define GPT_GTCSR_CSEVTF_SHIFT (21u) +#define GPT_GTCSR_CSEVTG (0x00400000u) +#define GPT_GTCSR_CSEVTG_SHIFT (22u) +#define GPT_GTCSR_CSEVTH (0x00800000u) +#define GPT_GTCSR_CSEVTH_SHIFT (23u) +#define GPT_GTCSR_CCLR (0x80000000u) +#define GPT_GTCSR_CCLR_SHIFT (31u) +#define GPT_GTUPSR_USGTRGAR (0x00000001u) +#define GPT_GTUPSR_USGTRGAR_SHIFT (0u) +#define GPT_GTUPSR_USGTRGAF (0x00000002u) +#define GPT_GTUPSR_USGTRGAF_SHIFT (1u) +#define GPT_GTUPSR_USGTRGBR (0x00000004u) +#define GPT_GTUPSR_USGTRGBR_SHIFT (2u) +#define GPT_GTUPSR_USGTRGBF (0x00000008u) +#define GPT_GTUPSR_USGTRGBF_SHIFT (3u) +#define GPT_GTUPSR_USGTRGCR (0x00000010u) +#define GPT_GTUPSR_USGTRGCR_SHIFT (4u) +#define GPT_GTUPSR_USGTRGCF (0x00000020u) +#define GPT_GTUPSR_USGTRGCF_SHIFT (5u) +#define GPT_GTUPSR_USGTRGDR (0x00000040u) +#define GPT_GTUPSR_USGTRGDR_SHIFT (6u) +#define GPT_GTUPSR_USGTRGDF (0x00000080u) +#define GPT_GTUPSR_USGTRGDF_SHIFT (7u) +#define GPT_GTUPSR_USCARBL (0x00000100u) +#define GPT_GTUPSR_USCARBL_SHIFT (8u) +#define GPT_GTUPSR_USCARBH (0x00000200u) +#define GPT_GTUPSR_USCARBH_SHIFT (9u) +#define GPT_GTUPSR_USCAFBL (0x00000400u) +#define GPT_GTUPSR_USCAFBL_SHIFT (10u) +#define GPT_GTUPSR_USCAFBH (0x00000800u) +#define GPT_GTUPSR_USCAFBH_SHIFT (11u) +#define GPT_GTUPSR_USCBRAL (0x00001000u) +#define GPT_GTUPSR_USCBRAL_SHIFT (12u) +#define GPT_GTUPSR_USCBRAH (0x00002000u) +#define GPT_GTUPSR_USCBRAH_SHIFT (13u) +#define GPT_GTUPSR_USCBFAL (0x00004000u) +#define GPT_GTUPSR_USCBFAL_SHIFT (14u) +#define GPT_GTUPSR_USCBFAH (0x00008000u) +#define GPT_GTUPSR_USCBFAH_SHIFT (15u) +#define GPT_GTUPSR_USEVTA (0x00010000u) +#define GPT_GTUPSR_USEVTA_SHIFT (16u) +#define GPT_GTUPSR_USEVTB (0x00020000u) +#define GPT_GTUPSR_USEVTB_SHIFT (17u) +#define GPT_GTUPSR_USEVTC (0x00040000u) +#define GPT_GTUPSR_USEVTC_SHIFT (18u) +#define GPT_GTUPSR_USEVTD (0x00080000u) +#define GPT_GTUPSR_USEVTD_SHIFT (19u) +#define GPT_GTUPSR_USEVTE (0x00100000u) +#define GPT_GTUPSR_USEVTE_SHIFT (20u) +#define GPT_GTUPSR_USEVTF (0x00200000u) +#define GPT_GTUPSR_USEVTF_SHIFT (21u) +#define GPT_GTUPSR_USEVTG (0x00400000u) +#define GPT_GTUPSR_USEVTG_SHIFT (22u) +#define GPT_GTUPSR_USEVTH (0x00800000u) +#define GPT_GTUPSR_USEVTH_SHIFT (23u) +#define GPT_GTDNSR_DSGTRGAR (0x00000001u) +#define GPT_GTDNSR_DSGTRGAR_SHIFT (0u) +#define GPT_GTDNSR_DSGTRGAF (0x00000002u) +#define GPT_GTDNSR_DSGTRGAF_SHIFT (1u) +#define GPT_GTDNSR_DSGTRGBR (0x00000004u) +#define GPT_GTDNSR_DSGTRGBR_SHIFT (2u) +#define GPT_GTDNSR_DSGTRGBF (0x00000008u) +#define GPT_GTDNSR_DSGTRGBF_SHIFT (3u) +#define GPT_GTDNSR_DSGTRGCR (0x00000010u) +#define GPT_GTDNSR_DSGTRGCR_SHIFT (4u) +#define GPT_GTDNSR_DSGTRGCF (0x00000020u) +#define GPT_GTDNSR_DSGTRGCF_SHIFT (5u) +#define GPT_GTDNSR_DSGTRGDR (0x00000040u) +#define GPT_GTDNSR_DSGTRGDR_SHIFT (6u) +#define GPT_GTDNSR_DSGTRGDF (0x00000080u) +#define GPT_GTDNSR_DSGTRGDF_SHIFT (7u) +#define GPT_GTDNSR_DSCARBL (0x00000100u) +#define GPT_GTDNSR_DSCARBL_SHIFT (8u) +#define GPT_GTDNSR_DSCARBH (0x00000200u) +#define GPT_GTDNSR_DSCARBH_SHIFT (9u) +#define GPT_GTDNSR_DSCAFBL (0x00000400u) +#define GPT_GTDNSR_DSCAFBL_SHIFT (10u) +#define GPT_GTDNSR_DSCAFBH (0x00000800u) +#define GPT_GTDNSR_DSCAFBH_SHIFT (11u) +#define GPT_GTDNSR_DSCBRAL (0x00001000u) +#define GPT_GTDNSR_DSCBRAL_SHIFT (12u) +#define GPT_GTDNSR_DSCBRAH (0x00002000u) +#define GPT_GTDNSR_DSCBRAH_SHIFT (13u) +#define GPT_GTDNSR_DSCBFAL (0x00004000u) +#define GPT_GTDNSR_DSCBFAL_SHIFT (14u) +#define GPT_GTDNSR_DSCBFAH (0x00008000u) +#define GPT_GTDNSR_DSCBFAH_SHIFT (15u) +#define GPT_GTDNSR_DSEVTA (0x00010000u) +#define GPT_GTDNSR_DSEVTA_SHIFT (16u) +#define GPT_GTDNSR_DSEVTB (0x00020000u) +#define GPT_GTDNSR_DSEVTB_SHIFT (17u) +#define GPT_GTDNSR_DSEVTC (0x00040000u) +#define GPT_GTDNSR_DSEVTC_SHIFT (18u) +#define GPT_GTDNSR_DSEVTD (0x00080000u) +#define GPT_GTDNSR_DSEVTD_SHIFT (19u) +#define GPT_GTDNSR_DSEVTE (0x00100000u) +#define GPT_GTDNSR_DSEVTE_SHIFT (20u) +#define GPT_GTDNSR_DSEVTF (0x00200000u) +#define GPT_GTDNSR_DSEVTF_SHIFT (21u) +#define GPT_GTDNSR_DSEVTG (0x00400000u) +#define GPT_GTDNSR_DSEVTG_SHIFT (22u) +#define GPT_GTDNSR_DSEVTH (0x00800000u) +#define GPT_GTDNSR_DSEVTH_SHIFT (23u) +#define GPT_GTICASR_ASGTRGAR (0x00000001u) +#define GPT_GTICASR_ASGTRGAR_SHIFT (0u) +#define GPT_GTICASR_ASGTRGAF (0x00000002u) +#define GPT_GTICASR_ASGTRGAF_SHIFT (1u) +#define GPT_GTICASR_ASGTRGBR (0x00000004u) +#define GPT_GTICASR_ASGTRGBR_SHIFT (2u) +#define GPT_GTICASR_ASGTRGBF (0x00000008u) +#define GPT_GTICASR_ASGTRGBF_SHIFT (3u) +#define GPT_GTICASR_ASGTRGCR (0x00000010u) +#define GPT_GTICASR_ASGTRGCR_SHIFT (4u) +#define GPT_GTICASR_ASGTRGCF (0x00000020u) +#define GPT_GTICASR_ASGTRGCF_SHIFT (5u) +#define GPT_GTICASR_ASGTRGDR (0x00000040u) +#define GPT_GTICASR_ASGTRGDR_SHIFT (6u) +#define GPT_GTICASR_ASGTRGDF (0x00000080u) +#define GPT_GTICASR_ASGTRGDF_SHIFT (7u) +#define GPT_GTICASR_ASCARBL (0x00000100u) +#define GPT_GTICASR_ASCARBL_SHIFT (8u) +#define GPT_GTICASR_ASCARBH (0x00000200u) +#define GPT_GTICASR_ASCARBH_SHIFT (9u) +#define GPT_GTICASR_ASCAFBL (0x00000400u) +#define GPT_GTICASR_ASCAFBL_SHIFT (10u) +#define GPT_GTICASR_ASCAFBH (0x00000800u) +#define GPT_GTICASR_ASCAFBH_SHIFT (11u) +#define GPT_GTICASR_ASCBRAL (0x00001000u) +#define GPT_GTICASR_ASCBRAL_SHIFT (12u) +#define GPT_GTICASR_ASCBRAH (0x00002000u) +#define GPT_GTICASR_ASCBRAH_SHIFT (13u) +#define GPT_GTICASR_ASCBFAL (0x00004000u) +#define GPT_GTICASR_ASCBFAL_SHIFT (14u) +#define GPT_GTICASR_ASCBFAH (0x00008000u) +#define GPT_GTICASR_ASCBFAH_SHIFT (15u) +#define GPT_GTICASR_ASEVTA (0x00010000u) +#define GPT_GTICASR_ASEVTA_SHIFT (16u) +#define GPT_GTICASR_ASEVTB (0x00020000u) +#define GPT_GTICASR_ASEVTB_SHIFT (17u) +#define GPT_GTICASR_ASEVTC (0x00040000u) +#define GPT_GTICASR_ASEVTC_SHIFT (18u) +#define GPT_GTICASR_ASEVTD (0x00080000u) +#define GPT_GTICASR_ASEVTD_SHIFT (19u) +#define GPT_GTICASR_ASEVTE (0x00100000u) +#define GPT_GTICASR_ASEVTE_SHIFT (20u) +#define GPT_GTICASR_ASEVTF (0x00200000u) +#define GPT_GTICASR_ASEVTF_SHIFT (21u) +#define GPT_GTICASR_ASEVTG (0x00400000u) +#define GPT_GTICASR_ASEVTG_SHIFT (22u) +#define GPT_GTICASR_ASEVTH (0x00800000u) +#define GPT_GTICASR_ASEVTH_SHIFT (23u) +#define GPT_GTICBSR_BSGTRGAR (0x00000001u) +#define GPT_GTICBSR_BSGTRGAR_SHIFT (0u) +#define GPT_GTICBSR_BSGTRGAF (0x00000002u) +#define GPT_GTICBSR_BSGTRGAF_SHIFT (1u) +#define GPT_GTICBSR_BSGTRGBR (0x00000004u) +#define GPT_GTICBSR_BSGTRGBR_SHIFT (2u) +#define GPT_GTICBSR_BSGTRGBF (0x00000008u) +#define GPT_GTICBSR_BSGTRGBF_SHIFT (3u) +#define GPT_GTICBSR_BSGTRGCR (0x00000010u) +#define GPT_GTICBSR_BSGTRGCR_SHIFT (4u) +#define GPT_GTICBSR_BSGTRGCF (0x00000020u) +#define GPT_GTICBSR_BSGTRGCF_SHIFT (5u) +#define GPT_GTICBSR_BSGTRGDR (0x00000040u) +#define GPT_GTICBSR_BSGTRGDR_SHIFT (6u) +#define GPT_GTICBSR_BSGTRGDF (0x00000080u) +#define GPT_GTICBSR_BSGTRGDF_SHIFT (7u) +#define GPT_GTICBSR_BSCARBL (0x00000100u) +#define GPT_GTICBSR_BSCARBL_SHIFT (8u) +#define GPT_GTICBSR_BSCARBH (0x00000200u) +#define GPT_GTICBSR_BSCARBH_SHIFT (9u) +#define GPT_GTICBSR_BSCAFBL (0x00000400u) +#define GPT_GTICBSR_BSCAFBL_SHIFT (10u) +#define GPT_GTICBSR_BSCAFBH (0x00000800u) +#define GPT_GTICBSR_BSCAFBH_SHIFT (11u) +#define GPT_GTICBSR_BSCBRAL (0x00001000u) +#define GPT_GTICBSR_BSCBRAL_SHIFT (12u) +#define GPT_GTICBSR_BSCBRAH (0x00002000u) +#define GPT_GTICBSR_BSCBRAH_SHIFT (13u) +#define GPT_GTICBSR_BSCBFAL (0x00004000u) +#define GPT_GTICBSR_BSCBFAL_SHIFT (14u) +#define GPT_GTICBSR_BSCBFAH (0x00008000u) +#define GPT_GTICBSR_BSCBFAH_SHIFT (15u) +#define GPT_GTICBSR_BSEVTA (0x00010000u) +#define GPT_GTICBSR_BSEVTA_SHIFT (16u) +#define GPT_GTICBSR_BSEVTB (0x00020000u) +#define GPT_GTICBSR_BSEVTB_SHIFT (17u) +#define GPT_GTICBSR_BSEVTC (0x00040000u) +#define GPT_GTICBSR_BSEVTC_SHIFT (18u) +#define GPT_GTICBSR_BSEVTD (0x00080000u) +#define GPT_GTICBSR_BSEVTD_SHIFT (19u) +#define GPT_GTICBSR_BSEVTE (0x00100000u) +#define GPT_GTICBSR_BSEVTE_SHIFT (20u) +#define GPT_GTICBSR_BSEVTF (0x00200000u) +#define GPT_GTICBSR_BSEVTF_SHIFT (21u) +#define GPT_GTICBSR_BSEVTG (0x00400000u) +#define GPT_GTICBSR_BSEVTG_SHIFT (22u) +#define GPT_GTICBSR_BSEVTH (0x00800000u) +#define GPT_GTICBSR_BSEVTH_SHIFT (23u) +#define GPT_GTCR_CST (0x00000001u) +#define GPT_GTCR_CST_SHIFT (0u) +#define GPT_GTCR_MD (0x00070000u) +#define GPT_GTCR_MD_SHIFT (16u) +#define GPT_GTCR_TPCS (0x07000000u) +#define GPT_GTCR_TPCS_SHIFT (24u) +#define GPT_GTUDDTYC_UD (0x00000001u) +#define GPT_GTUDDTYC_UD_SHIFT (0u) +#define GPT_GTUDDTYC_UDF (0x00000002u) +#define GPT_GTUDDTYC_UDF_SHIFT (1u) +#define GPT_GTUDDTYC_OADTY (0x00030000u) +#define GPT_GTUDDTYC_OADTY_SHIFT (16u) +#define GPT_GTUDDTYC_OADTYF (0x00040000u) +#define GPT_GTUDDTYC_OADTYF_SHIFT (18u) +#define GPT_GTUDDTYC_OADTYR (0x00080000u) +#define GPT_GTUDDTYC_OADTYR_SHIFT (19u) +#define GPT_GTUDDTYC_OBDTY (0x03000000u) +#define GPT_GTUDDTYC_OBDTY_SHIFT (24u) +#define GPT_GTUDDTYC_OBDTYF (0x04000000u) +#define GPT_GTUDDTYC_OBDTYF_SHIFT (26u) +#define GPT_GTUDDTYC_OBDTYR (0x08000000u) +#define GPT_GTUDDTYC_OBDTYR_SHIFT (27u) +#define GPT_GTIOR_GTIOA (0x0000001Fu) +#define GPT_GTIOR_GTIOA_SHIFT (0u) +#define GPT_GTIOR_OADFLT (0x00000040u) +#define GPT_GTIOR_OADFLT_SHIFT (6u) +#define GPT_GTIOR_OAHLD (0x00000080u) +#define GPT_GTIOR_OAHLD_SHIFT (7u) +#define GPT_GTIOR_OAE (0x00000100u) +#define GPT_GTIOR_OAE_SHIFT (8u) +#define GPT_GTIOR_OADF (0x00000600u) +#define GPT_GTIOR_OADF_SHIFT (9u) +#define GPT_GTIOR_NFAEN (0x00002000u) +#define GPT_GTIOR_NFAEN_SHIFT (13u) +#define GPT_GTIOR_NFCSA (0x0000C000u) +#define GPT_GTIOR_NFCSA_SHIFT (14u) +#define GPT_GTIOR_GTIOB (0x001F0000u) +#define GPT_GTIOR_GTIOB_SHIFT (16u) +#define GPT_GTIOR_OBDFLT (0x00400000u) +#define GPT_GTIOR_OBDFLT_SHIFT (22u) +#define GPT_GTIOR_OBHLD (0x00800000u) +#define GPT_GTIOR_OBHLD_SHIFT (23u) +#define GPT_GTIOR_OBE (0x01000000u) +#define GPT_GTIOR_OBE_SHIFT (24u) +#define GPT_GTIOR_OBDF (0x06000000u) +#define GPT_GTIOR_OBDF_SHIFT (25u) +#define GPT_GTIOR_NFBEN (0x20000000u) +#define GPT_GTIOR_NFBEN_SHIFT (29u) +#define GPT_GTIOR_NFCSB (0xC0000000u) +#define GPT_GTIOR_NFCSB_SHIFT (30u) +#define GPT_GTINTAD_GTINTA (0x00000001u) +#define GPT_GTINTAD_GTINTA_SHIFT (0u) +#define GPT_GTINTAD_GTINTB (0x00000002u) +#define GPT_GTINTAD_GTINTB_SHIFT (1u) +#define GPT_GTINTAD_GTINTC (0x00000004u) +#define GPT_GTINTAD_GTINTC_SHIFT (2u) +#define GPT_GTINTAD_GTINTD (0x00000008u) +#define GPT_GTINTAD_GTINTD_SHIFT (3u) +#define GPT_GTINTAD_GTINTE (0x00000010u) +#define GPT_GTINTAD_GTINTE_SHIFT (4u) +#define GPT_GTINTAD_GTINTF (0x00000020u) +#define GPT_GTINTAD_GTINTF_SHIFT (5u) +#define GPT_GTINTAD_GTINTPR (0x000000C0u) +#define GPT_GTINTAD_GTINTPR_SHIFT (6u) +#define GPT_GTINTAD_ADTRAUEN (0x00010000u) +#define GPT_GTINTAD_ADTRAUEN_SHIFT (16u) +#define GPT_GTINTAD_ADTRADEN (0x00020000u) +#define GPT_GTINTAD_ADTRADEN_SHIFT (17u) +#define GPT_GTINTAD_ADTRBUEN (0x00040000u) +#define GPT_GTINTAD_ADTRBUEN_SHIFT (18u) +#define GPT_GTINTAD_ADTRBDEN (0x00080000u) +#define GPT_GTINTAD_ADTRBDEN_SHIFT (19u) +#define GPT_GTINTAD_GRP (0x03000000u) +#define GPT_GTINTAD_GRP_SHIFT (24u) +#define GPT_GTINTAD_GRPDTE (0x10000000u) +#define GPT_GTINTAD_GRPDTE_SHIFT (28u) +#define GPT_GTINTAD_GRPABH (0x20000000u) +#define GPT_GTINTAD_GRPABH_SHIFT (29u) +#define GPT_GTINTAD_GRPABL (0x40000000u) +#define GPT_GTINTAD_GRPABL_SHIFT (30u) +#define GPT_GTST_TCFA (0x00000001u) +#define GPT_GTST_TCFA_SHIFT (0u) +#define GPT_GTST_TCFB (0x00000002u) +#define GPT_GTST_TCFB_SHIFT (1u) +#define GPT_GTST_TCFC (0x00000004u) +#define GPT_GTST_TCFC_SHIFT (2u) +#define GPT_GTST_TCFD (0x00000008u) +#define GPT_GTST_TCFD_SHIFT (3u) +#define GPT_GTST_TCFE (0x00000010u) +#define GPT_GTST_TCFE_SHIFT (4u) +#define GPT_GTST_TCFF (0x00000020u) +#define GPT_GTST_TCFF_SHIFT (5u) +#define GPT_GTST_TCFPO (0x00000040u) +#define GPT_GTST_TCFPO_SHIFT (6u) +#define GPT_GTST_TCFPU (0x00000080u) +#define GPT_GTST_TCFPU_SHIFT (7u) +#define GPT_GTST_ITCNT (0x00000700u) +#define GPT_GTST_ITCNT_SHIFT (8u) +#define GPT_GTST_TUCF (0x00008000u) +#define GPT_GTST_TUCF_SHIFT (15u) +#define GPT_GTST_ADTRAUF (0x00010000u) +#define GPT_GTST_ADTRAUF_SHIFT (16u) +#define GPT_GTST_ADTRADF (0x00020000u) +#define GPT_GTST_ADTRADF_SHIFT (17u) +#define GPT_GTST_ADTRBUF (0x00040000u) +#define GPT_GTST_ADTRBUF_SHIFT (18u) +#define GPT_GTST_ADTRBDF (0x00080000u) +#define GPT_GTST_ADTRBDF_SHIFT (19u) +#define GPT_GTST_ODF (0x01000000u) +#define GPT_GTST_ODF_SHIFT (24u) +#define GPT_GTST_DTEF (0x10000000u) +#define GPT_GTST_DTEF_SHIFT (28u) +#define GPT_GTST_OABHF (0x20000000u) +#define GPT_GTST_OABHF_SHIFT (29u) +#define GPT_GTST_OABLF (0x40000000u) +#define GPT_GTST_OABLF_SHIFT (30u) +#define GPT_GTBER_BD (0x0000000Fu) +#define GPT_GTBER_BD_SHIFT (0u) +#define GPT_GTBER_CCRA (0x00030000u) +#define GPT_GTBER_CCRA_SHIFT (16u) +#define GPT_GTBER_CCRB (0x000C0000u) +#define GPT_GTBER_CCRB_SHIFT (18u) +#define GPT_GTBER_PR (0x00300000u) +#define GPT_GTBER_PR_SHIFT (20u) +#define GPT_GTBER_CCRSWT (0x00400000u) +#define GPT_GTBER_CCRSWT_SHIFT (22u) +#define GPT_GTBER_ADTTA (0x03000000u) +#define GPT_GTBER_ADTTA_SHIFT (24u) +#define GPT_GTBER_ADTDA (0x04000000u) +#define GPT_GTBER_ADTDA_SHIFT (26u) +#define GPT_GTBER_ADTTB (0x30000000u) +#define GPT_GTBER_ADTTB_SHIFT (28u) +#define GPT_GTBER_ADTDB (0x40000000u) +#define GPT_GTBER_ADTDB_SHIFT (30u) +#define GPT_GTITC_ITLA (0x00000001u) +#define GPT_GTITC_ITLA_SHIFT (0u) +#define GPT_GTITC_ITLB (0x00000002u) +#define GPT_GTITC_ITLB_SHIFT (1u) +#define GPT_GTITC_ITLC (0x00000004u) +#define GPT_GTITC_ITLC_SHIFT (2u) +#define GPT_GTITC_ITLD (0x00000008u) +#define GPT_GTITC_ITLD_SHIFT (3u) +#define GPT_GTITC_ITLE (0x00000010u) +#define GPT_GTITC_ITLE_SHIFT (4u) +#define GPT_GTITC_ITLF (0x00000020u) +#define GPT_GTITC_ITLF_SHIFT (5u) +#define GPT_GTITC_IVTC (0x000000C0u) +#define GPT_GTITC_IVTC_SHIFT (6u) +#define GPT_GTITC_IVTT (0x00000700u) +#define GPT_GTITC_IVTT_SHIFT (8u) +#define GPT_GTITC_ADTAL (0x00001000u) +#define GPT_GTITC_ADTAL_SHIFT (12u) +#define GPT_GTITC_ADTBL (0x00004000u) +#define GPT_GTITC_ADTBL_SHIFT (14u) +#define GPT_GTCNT_GTCNT (0xFFFFFFFFu) +#define GPT_GTCNT_GTCNT_SHIFT (0u) +#define GPT_GTCCRA_GTCCRA (0xFFFFFFFFu) +#define GPT_GTCCRA_GTCCRA_SHIFT (0u) +#define GPT_GTCCRB_GTCCRB (0xFFFFFFFFu) +#define GPT_GTCCRB_GTCCRB_SHIFT (0u) +#define GPT_GTCCRC_GTCCRC (0xFFFFFFFFu) +#define GPT_GTCCRC_GTCCRC_SHIFT (0u) +#define GPT_GTCCRE_GTCCRE (0xFFFFFFFFu) +#define GPT_GTCCRE_GTCCRE_SHIFT (0u) +#define GPT_GTCCRD_GTCCRD (0xFFFFFFFFu) +#define GPT_GTCCRD_GTCCRD_SHIFT (0u) +#define GPT_GTCCRF_GTCCRF (0xFFFFFFFFu) +#define GPT_GTCCRF_GTCCRF_SHIFT (0u) +#define GPT_GTPR_GTPR (0xFFFFFFFFu) +#define GPT_GTPR_GTPR_SHIFT (0u) +#define GPT_GTPBR_GTPBR (0xFFFFFFFFu) +#define GPT_GTPBR_GTPBR_SHIFT (0u) +#define GPT_GTPDBR_GTPDBR (0xFFFFFFFFu) +#define GPT_GTPDBR_GTPDBR_SHIFT (0u) +#define GPT_GTADTRA_GTADTRA (0xFFFFFFFFu) +#define GPT_GTADTRA_GTADTRA_SHIFT (0u) +#define GPT_GTADTBRA_GTADTBRA (0xFFFFFFFFu) +#define GPT_GTADTBRA_GTADTBRA_SHIFT (0u) +#define GPT_GTADTDBRA_GTADTDBRA (0xFFFFFFFFu) +#define GPT_GTADTDBRA_GTADTDBRA_SHIFT (0u) +#define GPT_GTADTRB_GTADTRB (0xFFFFFFFFu) +#define GPT_GTADTRB_GTADTRB_SHIFT (0u) +#define GPT_GTADTBRB_GTADTBRB (0xFFFFFFFFu) +#define GPT_GTADTBRB_GTADTBRB_SHIFT (0u) +#define GPT_GTADTDBRB_GTADTDBRB (0xFFFFFFFFu) +#define GPT_GTADTDBRB_GTADTDBRB_SHIFT (0u) +#define GPT_GTDTCR_TDE (0x00000001u) +#define GPT_GTDTCR_TDE_SHIFT (0u) +#define GPT_GTDTCR_TDBUE (0x00000010u) +#define GPT_GTDTCR_TDBUE_SHIFT (4u) +#define GPT_GTDTCR_TDBDE (0x00000020u) +#define GPT_GTDTCR_TDBDE_SHIFT (5u) +#define GPT_GTDTCR_TDFER (0x00000100u) +#define GPT_GTDTCR_TDFER_SHIFT (8u) +#define GPT_GTDVU_GTDVU (0xFFFFFFFFu) +#define GPT_GTDVU_GTDVU_SHIFT (0u) +#define GPT_GTDVD_GTDVD (0xFFFFFFFFu) +#define GPT_GTDVD_GTDVD_SHIFT (0u) +#define GPT_GTDBU_GTDBU (0xFFFFFFFFu) +#define GPT_GTDBU_GTDBU_SHIFT (0u) +#define GPT_GTDBD_GTDBD (0xFFFFFFFFu) +#define GPT_GTDBD_GTDBD_SHIFT (0u) +#define GPT_GTSOS_SOS (0x00000003u) +#define GPT_GTSOS_SOS_SHIFT (0u) +#define GPT_GTSOTR_SOTR (0x00000001u) +#define GPT_GTSOTR_SOTR_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/hyper_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/hyper_iobitmask.h new file mode 100644 index 0000000..c7f3121 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/hyper_iobitmask.h @@ -0,0 +1,112 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef HYPER_IOBITMASK_H +#define HYPER_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define HYPER_CSR_RACT (0x00000001u) +#define HYPER_CSR_RACT_SHIFT (0u) +#define HYPER_CSR_RDECERR (0x00000100u) +#define HYPER_CSR_RDECERR_SHIFT (8u) +#define HYPER_CSR_RTRSERR (0x00000200u) +#define HYPER_CSR_RTRSERR_SHIFT (9u) +#define HYPER_CSR_RRSTOERR (0x00000400u) +#define HYPER_CSR_RRSTOERR_SHIFT (10u) +#define HYPER_CSR_RDSSTALL (0x00000800u) +#define HYPER_CSR_RDSSTALL_SHIFT (11u) +#define HYPER_CSR_WACT (0x00010000u) +#define HYPER_CSR_WACT_SHIFT (16u) +#define HYPER_CSR_WDECERR (0x01000000u) +#define HYPER_CSR_WDECERR_SHIFT (24u) +#define HYPER_CSR_WTRSERR (0x02000000u) +#define HYPER_CSR_WTRSERR_SHIFT (25u) +#define HYPER_CSR_WRSTOERR (0x04000000u) +#define HYPER_CSR_WRSTOERR_SHIFT (26u) +#define HYPER_IEN_RPCINTE (0x00000001u) +#define HYPER_IEN_RPCINTE_SHIFT (0u) +#define HYPER_IEN_INTP (0x80000000u) +#define HYPER_IEN_INTP_SHIFT (31u) +#define HYPER_ISR_RPCINTS (0x00000001u) +#define HYPER_ISR_RPCINTS_SHIFT (0u) +#define HYPER_MCR0_MAXLEN (0x07FC0000u) +#define HYPER_MCR0_MAXLEN_SHIFT (18u) +#define HYPER_MCR0_MAXEN (0x80000000u) +#define HYPER_MCR0_MAXEN_SHIFT (31u) +#define HYPER_MCR1_DEVTYPE (0x00000010u) +#define HYPER_MCR1_DEVTYPE_SHIFT (4u) +#define HYPER_MCR1_CRT (0x00000020u) +#define HYPER_MCR1_CRT_SHIFT (5u) +#define HYPER_MCR1_MAXLEN (0x07FC0000u) +#define HYPER_MCR1_MAXLEN_SHIFT (18u) +#define HYPER_MCR1_MAXEN (0x80000000u) +#define HYPER_MCR1_MAXEN_SHIFT (31u) +#define HYPER_MTR0_WCSH (0x00000F00u) +#define HYPER_MTR0_WCSH_SHIFT (8u) +#define HYPER_MTR0_RCSH (0x0000F000u) +#define HYPER_MTR0_RCSH_SHIFT (12u) +#define HYPER_MTR0_WCSS (0x000F0000u) +#define HYPER_MTR0_WCSS_SHIFT (16u) +#define HYPER_MTR0_RCSS (0x00F00000u) +#define HYPER_MTR0_RCSS_SHIFT (20u) +#define HYPER_MTR0_WCSHI (0x0F000000u) +#define HYPER_MTR0_WCSHI_SHIFT (24u) +#define HYPER_MTR0_RCSHI (0xF0000000u) +#define HYPER_MTR0_RCSHI_SHIFT (28u) +#define HYPER_MTR1_LTCY (0x0000000Fu) +#define HYPER_MTR1_LTCY_SHIFT (0u) +#define HYPER_MTR1_WCSH (0x00000F00u) +#define HYPER_MTR1_WCSH_SHIFT (8u) +#define HYPER_MTR1_RCSH (0x0000F000u) +#define HYPER_MTR1_RCSH_SHIFT (12u) +#define HYPER_MTR1_WCSS (0x000F0000u) +#define HYPER_MTR1_WCSS_SHIFT (16u) +#define HYPER_MTR1_RCSS (0x00F00000u) +#define HYPER_MTR1_RCSS_SHIFT (20u) +#define HYPER_MTR1_WCSHI (0x0F000000u) +#define HYPER_MTR1_WCSHI_SHIFT (24u) +#define HYPER_MTR1_RCSHI (0xF0000000u) +#define HYPER_MTR1_RCSHI_SHIFT (28u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/imr2_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/imr2_iobitmask.h new file mode 100644 index 0000000..176ffa4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/imr2_iobitmask.h @@ -0,0 +1,186 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef IMR2_IOBITMASK_H +#define IMR2_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define IMR2_CR_RS (0x00000001u) +#define IMR2_CR_RS_SHIFT (0u) +#define IMR2_CR_ARS (0x00000002u) +#define IMR2_CR_ARS_SHIFT (1u) +#define IMR2_CR_SFE (0x00000004u) +#define IMR2_CR_SFE_SHIFT (2u) +#define IMR2_CR_SWRST (0x00008000u) +#define IMR2_CR_SWRST_SHIFT (15u) +#define IMR2_SR_TRA (0x00000001u) +#define IMR2_SR_TRA_SHIFT (0u) +#define IMR2_SR_IER (0x00000002u) +#define IMR2_SR_IER_SHIFT (1u) +#define IMR2_SR_INT (0x00000004u) +#define IMR2_SR_INT_SHIFT (2u) +#define IMR2_SR_DSA (0x00000040u) +#define IMR2_SR_DSA_SHIFT (6u) +#define IMR2_SR_SFS (0x00000080u) +#define IMR2_SR_SFS_SHIFT (7u) +#define IMR2_SRCR_TRACLR (0x00000001u) +#define IMR2_SRCR_TRACLR_SHIFT (0u) +#define IMR2_SRCR_IERCLR (0x00000002u) +#define IMR2_SRCR_IERCLR_SHIFT (1u) +#define IMR2_SRCR_INTCLR (0x00000004u) +#define IMR2_SRCR_INTCLR_SHIFT (2u) +#define IMR2_ICR_TRAENB (0x00000001u) +#define IMR2_ICR_TRAENB_SHIFT (0u) +#define IMR2_ICR_IERENB (0x00000002u) +#define IMR2_ICR_IERENB_SHIFT (1u) +#define IMR2_ICR_INTENB (0x00000004u) +#define IMR2_ICR_INTENB_SHIFT (2u) +#define IMR2_IMR_TEAM (0x00000001u) +#define IMR2_IMR_TEAM_SHIFT (0u) +#define IMR2_IMR_IEM (0x00000002u) +#define IMR2_IMR_IEM_SHIFT (1u) +#define IMR2_IMR_INM (0x00000004u) +#define IMR2_IMR_INM_SHIFT (2u) +#define IMR2_DLPR_DLP (0xFFFFFFFFu) +#define IMR2_DLPR_DLP_SHIFT (0u) +#define IMR2_DLSAR_DLSA (0xFFFFFFC0u) +#define IMR2_DLSAR_DLSA_SHIFT (3u) +#define IMR2_DSAR_DSA (0xFFFFFC00u) +#define IMR2_DSAR_DSA_SHIFT (5u) +#define IMR2_DSTR_DST (0x00003FFFu) +#define IMR2_DSTR_DST_SHIFT (0u) +#define IMR2_DSAR2_DSA2 (0xFFFFFC00u) +#define IMR2_DSAR2_DSA2_SHIFT (5u) +#define IMR2_DLSAR2_DLSA2 (0xFFFFFFC0u) +#define IMR2_DLSAR2_DLSA2_SHIFT (3u) +#define IMR2_TRIMR_TME (0x00000001u) +#define IMR2_TRIMR_TME_SHIFT (0u) +#define IMR2_TRIMR_BFE (0x00000002u) +#define IMR2_TRIMR_BFE_SHIFT (1u) +#define IMR2_TRIMR_AUTODG (0x00000004u) +#define IMR2_TRIMR_AUTODG_SHIFT (2u) +#define IMR2_TRIMR_AUTOSG (0x00000008u) +#define IMR2_TRIMR_AUTOSG_SHIFT (3u) +#define IMR2_TRIMR_DXDYM (0x00000010u) +#define IMR2_TRIMR_DXDYM_SHIFT (4u) +#define IMR2_TRIMR_DUDVM (0x00000020u) +#define IMR2_TRIMR_DUDVM_SHIFT (5u) +#define IMR2_TRIMR_TCM (0x00000040u) +#define IMR2_TRIMR_TCM_SHIFT (6u) +#define IMR2_TRIMSR_TMES (0x00000001u) +#define IMR2_TRIMSR_TMES_SHIFT (0u) +#define IMR2_TRIMSR_BFES (0x00000002u) +#define IMR2_TRIMSR_BFES_SHIFT (1u) +#define IMR2_TRIMSR_AUTODGS (0x00000004u) +#define IMR2_TRIMSR_AUTODGS_SHIFT (2u) +#define IMR2_TRIMSR_AUTOSGS (0x00000008u) +#define IMR2_TRIMSR_AUTOSGS_SHIFT (3u) +#define IMR2_TRIMSR_DXDYMS (0x00000010u) +#define IMR2_TRIMSR_DXDYMS_SHIFT (4u) +#define IMR2_TRIMSR_DUDVMS (0x00000020u) +#define IMR2_TRIMSR_DUDVMS_SHIFT (5u) +#define IMR2_TRIMSR_TCMS (0x00000040u) +#define IMR2_TRIMSR_TCMS_SHIFT (6u) +#define IMR2_TRIMCR_TMEC (0x00000001u) +#define IMR2_TRIMCR_TMEC_SHIFT (0u) +#define IMR2_TRIMCR_BFEC (0x00000002u) +#define IMR2_TRIMCR_BFEC_SHIFT (1u) +#define IMR2_TRIMCR_AUTODGC (0x00000004u) +#define IMR2_TRIMCR_AUTODGC_SHIFT (2u) +#define IMR2_TRIMCR_AUTOSGC (0x00000008u) +#define IMR2_TRIMCR_AUTOSGC_SHIFT (3u) +#define IMR2_TRIMCR_DXDYMC (0x00000010u) +#define IMR2_TRIMCR_DXDYMC_SHIFT (4u) +#define IMR2_TRIMCR_DUDVMC (0x00000020u) +#define IMR2_TRIMCR_DUDVMC_SHIFT (5u) +#define IMR2_TRIMCR_TCMC (0x00000040u) +#define IMR2_TRIMCR_TCMC_SHIFT (6u) +#define IMR2_TRICR_TCY (0x000000FFu) +#define IMR2_TRICR_TCY_SHIFT (0u) +#define IMR2_TRICR_TCU (0x0000FF00u) +#define IMR2_TRICR_TCU_SHIFT (8u) +#define IMR2_TRICR_TCV (0x00FF0000u) +#define IMR2_TRICR_TCV_SHIFT (16u) +#define IMR2_TRICR_YCFORM (0x80000000u) +#define IMR2_TRICR_YCFORM_SHIFT (31u) +#define IMR2_UVDPOR_UVDPO (0x00000007u) +#define IMR2_UVDPOR_UVDPO_SHIFT (0u) +#define IMR2_UVDPOR_DDP (0x00000100u) +#define IMR2_UVDPOR_DDP_SHIFT (8u) +#define IMR2_SUSR_SVW (0x000007FFu) +#define IMR2_SUSR_SVW_SHIFT (0u) +#define IMR2_SUSR_SUW (0x07FF0000u) +#define IMR2_SUSR_SUW_SHIFT (16u) +#define IMR2_SVSR_SVS (0x000007FFu) +#define IMR2_SVSR_SVS_SHIFT (0u) +#define IMR2_XMINR_XMIN (0x00001FFFu) +#define IMR2_XMINR_XMIN_SHIFT (0u) +#define IMR2_YMINR_YMIN (0x00001FFFu) +#define IMR2_YMINR_YMIN_SHIFT (0u) +#define IMR2_XMAXR_XMAX (0x00001FFFu) +#define IMR2_XMAXR_XMAX_SHIFT (0u) +#define IMR2_YMAXR_YMAX (0x00001FFFu) +#define IMR2_YMAXR_YMAX_SHIFT (0u) +#define IMR2_AMXSR_AMXS (0x00001FFFu) +#define IMR2_AMXSR_AMXS_SHIFT (0u) +#define IMR2_AMYSR_AMYS (0x00001FFFu) +#define IMR2_AMYSR_AMYS_SHIFT (0u) +#define IMR2_AMXOR_AMXO (0x00001FFFu) +#define IMR2_AMXOR_AMXO_SHIFT (0u) +#define IMR2_AMYOR_AMYO (0x00001FFFu) +#define IMR2_AMYOR_AMYO_SHIFT (0u) +#define IMR2_MACR1_EMAM (0x00001000u) +#define IMR2_MACR1_EMAM_SHIFT (12u) +#define IMR2_LSPR_LSPR (0x000003FFu) +#define IMR2_LSPR_LSPR_SHIFT (0u) +#define IMR2_LEPR_LEPR (0x000003FFu) +#define IMR2_LEPR_LEPR_SHIFT (0u) +#define IMR2_LMSR_LMSR (0x00000007u) +#define IMR2_LMSR_LMSR_SHIFT (0u) +#define IMR2_LMSPPCR_SPPC (0x000007FFu) +#define IMR2_LMSPPCR_SPPC_SHIFT (0u) +#define IMR2_LMEPPCR_EPPC (0x000007FFu) +#define IMR2_LMEPPCR_EPPC_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/intc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/intc_iobitmask.h new file mode 100644 index 0000000..58ec6ad --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/intc_iobitmask.h @@ -0,0 +1,2720 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef INTC_IOBITMASK_H +#define INTC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define INTC_GICD_CTLR_EnableGrp0 (0x00000001u) +#define INTC_GICD_CTLR_EnableGrp0_SHIFT (0u) +#define INTC_GICD_CTLR_EnableGrp1 (0x00000002u) +#define INTC_GICD_CTLR_EnableGrp1_SHIFT (1u) +#define INTC_GICD_TYPER_ITLinesNumber (0x0000001Fu) +#define INTC_GICD_TYPER_ITLinesNumber_SHIFT (0u) +#define INTC_GICD_TYPER_CPUNumber (0x000000E0u) +#define INTC_GICD_TYPER_CPUNumber_SHIFT (5u) +#define INTC_GICD_TYPER_SecurityExtn (0x00000400u) +#define INTC_GICD_TYPER_SecurityExtn_SHIFT (10u) +#define INTC_GICD_TYPER_LSPI (0x0000F800u) +#define INTC_GICD_TYPER_LSPI_SHIFT (11u) +#define INTC_GICD_IIDR_Implementer (0x00000FFFu) +#define INTC_GICD_IIDR_Implementer_SHIFT (0u) +#define INTC_GICD_IIDR_Revision (0x0000F000u) +#define INTC_GICD_IIDR_Revision_SHIFT (12u) +#define INTC_GICD_IIDR_Variant (0x000F0000u) +#define INTC_GICD_IIDR_Variant_SHIFT (16u) +#define INTC_GICD_IIDR_ProductID (0xFF000000u) +#define INTC_GICD_IIDR_ProductID_SHIFT (24u) +#define INTC_GICD_IGROUPR0_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR0_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR1_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR1_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR2_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR2_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR3_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR3_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR4_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR4_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR5_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR5_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR6_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR6_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR7_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR7_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR8_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR8_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR9_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR9_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR10_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR10_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR11_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR11_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR12_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR12_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR13_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR13_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR14_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR14_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_IGROUPR15_Securitystatusbits (0xFFFFFFFFu) +#define INTC_GICD_IGROUPR15_Securitystatusbits_SHIFT (0u) +#define INTC_GICD_ISENABLER0_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER0_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER1_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER1_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER2_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER2_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER3_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER3_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER4_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER4_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER5_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER5_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER6_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER6_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER7_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER7_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER8_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER8_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER9_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER9_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER10_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER10_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER11_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER11_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER12_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER12_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER13_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER13_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER14_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER14_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ISENABLER15_Set_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ISENABLER15_Set_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER0_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER0_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER1_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER1_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER2_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER2_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER3_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER3_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER4_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER4_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER5_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER5_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER6_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER6_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER7_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER7_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER8_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER8_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER9_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER9_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER10_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER10_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER11_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER11_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER12_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER12_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER13_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER13_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER14_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER14_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ICENABLER15_Clear_enablebits (0xFFFFFFFFu) +#define INTC_GICD_ICENABLER15_Clear_enablebits_SHIFT (0u) +#define INTC_GICD_ISPENDR0_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR0_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR1_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR1_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR2_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR2_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR3_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR3_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR4_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR4_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR5_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR5_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR6_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR6_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR7_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR7_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR8_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR8_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR9_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR9_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR10_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR10_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR11_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR11_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR12_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR12_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR13_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR13_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR14_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR14_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ISPENDR15_Set_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ISPENDR15_Set_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR0_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR0_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR1_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR1_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR2_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR2_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR3_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR3_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR4_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR4_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR5_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR5_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR6_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR6_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR7_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR7_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR8_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR8_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR9_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR9_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR10_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR10_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR11_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR11_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR12_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR12_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR13_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR13_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR14_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR14_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ICPENDR15_Clear_pendingbits (0xFFFFFFFFu) +#define INTC_GICD_ICPENDR15_Clear_pendingbits_SHIFT (0u) +#define INTC_GICD_ISACTIVER0_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER0_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER1_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER1_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER2_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER2_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER3_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER3_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER4_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER4_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER5_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER5_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER6_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER6_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER7_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER7_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER8_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER8_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER9_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER9_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER10_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER10_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER11_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER11_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER12_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER12_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER13_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER13_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER14_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER14_Activebits_SHIFT (0u) +#define INTC_GICD_ISACTIVER15_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ISACTIVER15_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER0_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER0_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER1_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER1_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER2_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER2_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER3_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER3_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER4_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER4_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER5_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER5_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER6_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER6_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER7_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER7_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER8_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER8_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER9_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER9_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER10_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER10_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER11_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER11_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER12_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER12_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER13_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER13_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER14_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER14_Activebits_SHIFT (0u) +#define INTC_GICD_ICACTIVER15_Activebits (0xFFFFFFFFu) +#define INTC_GICD_ICACTIVER15_Activebits_SHIFT (0u) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR0_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR1_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR2_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR3_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR4_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR5_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR6_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR7_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR8_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR9_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR10_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR11_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR12_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR13_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR14_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR15_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR16_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR17_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR18_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR19_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR20_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR21_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR22_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR23_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR24_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR25_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR26_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR27_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR28_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR29_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR30_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR31_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR32_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR33_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR34_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR35_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR36_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR37_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR38_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR39_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR40_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR41_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR42_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR43_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR44_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR45_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR46_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR47_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR48_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR49_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR50_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR51_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR52_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR53_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR54_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR55_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR56_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR57_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR58_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR59_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR60_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR61_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR62_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR63_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR64_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR65_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR66_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR67_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR68_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR69_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR70_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR71_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR72_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR73_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR74_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR75_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR76_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR77_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR78_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR79_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR80_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR81_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR82_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR83_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR84_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR85_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR86_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR87_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR88_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR89_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR90_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR91_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR92_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR93_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR94_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR95_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR96_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR97_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR98_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR99_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR100_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR101_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR102_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR103_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR104_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR105_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR106_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR107_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR108_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR109_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR110_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR111_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR112_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR113_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR114_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR115_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR116_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR117_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR118_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR119_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR120_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR121_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR122_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR123_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR124_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR125_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR126_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset0 (0x000000FFu) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset0_SHIFT (0u) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset1 (0x0000FF00u) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset1_SHIFT (8u) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset2 (0x00FF0000u) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset2_SHIFT (16u) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset3 (0xFF000000u) +#define INTC_GICD_IPRIORITYR127_Prioritybyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR0_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR1_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR2_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR3_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR4_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR5_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR6_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR7_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR8_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR9_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR10_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR11_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR12_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR13_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR14_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR15_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR16_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR17_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR18_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR19_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR20_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR21_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR22_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR23_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR24_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR25_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR26_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR27_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR28_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR29_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR30_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR31_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR32_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR33_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR34_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR35_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR36_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR37_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR38_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR39_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR40_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR41_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR42_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR43_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR44_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR45_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR46_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR47_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR48_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR49_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR50_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR51_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR52_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR53_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR54_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR55_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR56_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR57_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR58_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR59_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR60_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR61_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR62_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR63_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR64_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR65_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR66_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR67_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR68_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR69_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR70_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR71_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR72_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR73_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR74_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR75_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR76_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR77_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR78_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR79_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR80_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR81_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR82_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR83_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR84_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR85_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR86_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR87_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR88_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR89_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR90_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR91_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR92_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR93_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR94_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR95_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR96_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR97_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR98_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR99_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR100_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR101_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR102_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR103_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR104_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR105_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR106_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR107_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR108_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR109_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR110_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR111_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR112_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR113_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR114_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR115_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR116_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR117_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR118_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR119_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR120_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR121_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR122_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR123_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR124_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR125_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR126_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset0 (0x000000FFu) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset0_SHIFT (0u) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset1 (0x0000FF00u) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset1_SHIFT (8u) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset2 (0x00FF0000u) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset2_SHIFT (16u) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset3 (0xFF000000u) +#define INTC_GICD_ITARGETR127_CPUtargetsbyteoffset3_SHIFT (24u) +#define INTC_GICD_ICFGR0_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR0_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR1_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR1_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR2_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR2_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR3_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR3_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR4_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR4_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR5_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR5_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR6_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR6_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR7_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR7_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR8_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR8_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR9_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR9_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR10_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR10_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR11_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR11_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR12_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR12_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR13_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR13_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR14_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR14_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR15_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR15_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR16_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR16_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR17_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR17_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR18_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR18_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR19_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR19_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR20_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR20_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR21_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR21_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR22_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR22_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR23_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR23_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR24_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR24_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR25_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR25_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR26_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR26_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR27_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR27_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR28_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR28_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR29_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR29_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR30_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR30_Int_config_SHIFT (0u) +#define INTC_GICD_ICFGR31_Int_config (0xFFFFFFFFu) +#define INTC_GICD_ICFGR31_Int_config_SHIFT (0u) +#define INTC_GICD_PPISR_ppi_status (0x0000FFFFu) +#define INTC_GICD_PPISR_ppi_status_SHIFT (0u) +#define INTC_GICD_SPISR0_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR0_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR1_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR1_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR2_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR2_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR3_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR3_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR4_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR4_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR5_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR5_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR6_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR6_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR7_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR7_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR8_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR8_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR9_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR9_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR10_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR10_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR11_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR11_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR12_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR12_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR13_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR13_spi_status_SHIFT (0u) +#define INTC_GICD_SPISR14_spi_status (0xFFFFFFFFu) +#define INTC_GICD_SPISR14_spi_status_SHIFT (0u) +#define INTC_GICD_SGIR_SGIINTID (0x0000000Fu) +#define INTC_GICD_SGIR_SGIINTID_SHIFT (0u) +#define INTC_GICD_SGIR_NSATT (0x00008000u) +#define INTC_GICD_SGIR_NSATT_SHIFT (15u) +#define INTC_GICD_SGIR_CPUTargetList (0x00FF0000u) +#define INTC_GICD_SGIR_CPUTargetList_SHIFT (16u) +#define INTC_GICD_SGIR_TargetListFilter (0x03000000u) +#define INTC_GICD_SGIR_TargetListFilter_SHIFT (24u) +#define INTC_GICD_CPENDSGIR0_SGI0_Clers_pending (0x000000FFu) +#define INTC_GICD_CPENDSGIR0_SGI0_Clers_pending_SHIFT (0u) +#define INTC_GICD_CPENDSGIR0_SGI1_Clers_pending (0x0000FF00u) +#define INTC_GICD_CPENDSGIR0_SGI1_Clers_pending_SHIFT (8u) +#define INTC_GICD_CPENDSGIR0_SGI2_Clers_pending (0x00FF0000u) +#define INTC_GICD_CPENDSGIR0_SGI2_Clers_pending_SHIFT (16u) +#define INTC_GICD_CPENDSGIR0_SGI3_Clers_pending (0xFF000000u) +#define INTC_GICD_CPENDSGIR0_SGI3_Clers_pending_SHIFT (24u) +#define INTC_GICD_CPENDSGIR1_SGI4_Clers_pending (0x000000FFu) +#define INTC_GICD_CPENDSGIR1_SGI4_Clers_pending_SHIFT (0u) +#define INTC_GICD_CPENDSGIR1_SGI5_Clers_pending (0x0000FF00u) +#define INTC_GICD_CPENDSGIR1_SGI5_Clers_pending_SHIFT (8u) +#define INTC_GICD_CPENDSGIR1_SGI6_Clers_pending (0x00FF0000u) +#define INTC_GICD_CPENDSGIR1_SGI6_Clers_pending_SHIFT (16u) +#define INTC_GICD_CPENDSGIR1_SGI7_Clers_pending (0xFF000000u) +#define INTC_GICD_CPENDSGIR1_SGI7_Clers_pending_SHIFT (24u) +#define INTC_GICD_CPENDSGIR2_SGI8_Clers_pending (0x000000FFu) +#define INTC_GICD_CPENDSGIR2_SGI8_Clers_pending_SHIFT (0u) +#define INTC_GICD_CPENDSGIR2_SGI9_Clers_pending (0x0000FF00u) +#define INTC_GICD_CPENDSGIR2_SGI9_Clers_pending_SHIFT (8u) +#define INTC_GICD_CPENDSGIR2_SGI10_Clers_pending (0x00FF0000u) +#define INTC_GICD_CPENDSGIR2_SGI10_Clers_pending_SHIFT (16u) +#define INTC_GICD_CPENDSGIR2_SGI11_Clers_pending (0xFF000000u) +#define INTC_GICD_CPENDSGIR2_SGI11_Clers_pending_SHIFT (24u) +#define INTC_GICD_CPENDSGIR3_SGI12_Clers_pending (0x000000FFu) +#define INTC_GICD_CPENDSGIR3_SGI12_Clers_pending_SHIFT (0u) +#define INTC_GICD_CPENDSGIR3_SGI13_Clers_pending (0x0000FF00u) +#define INTC_GICD_CPENDSGIR3_SGI13_Clers_pending_SHIFT (8u) +#define INTC_GICD_CPENDSGIR3_SGI14_Clers_pending (0x00FF0000u) +#define INTC_GICD_CPENDSGIR3_SGI14_Clers_pending_SHIFT (16u) +#define INTC_GICD_CPENDSGIR3_SGI15_Clers_pending (0xFF000000u) +#define INTC_GICD_CPENDSGIR3_SGI15_Clers_pending_SHIFT (24u) +#define INTC_GICD_SPENDSGIR0_SGI0_Set_pending (0x000000FFu) +#define INTC_GICD_SPENDSGIR0_SGI0_Set_pending_SHIFT (0u) +#define INTC_GICD_SPENDSGIR0_SGI1_Set_pending (0x0000FF00u) +#define INTC_GICD_SPENDSGIR0_SGI1_Set_pending_SHIFT (8u) +#define INTC_GICD_SPENDSGIR0_SGI2_Set_pending (0x00FF0000u) +#define INTC_GICD_SPENDSGIR0_SGI2_Set_pending_SHIFT (16u) +#define INTC_GICD_SPENDSGIR0_SGI3_Set_pending (0xFF000000u) +#define INTC_GICD_SPENDSGIR0_SGI3_Set_pending_SHIFT (24u) +#define INTC_GICD_SPENDSGIR1_SGI4_Set_pending (0x000000FFu) +#define INTC_GICD_SPENDSGIR1_SGI4_Set_pending_SHIFT (0u) +#define INTC_GICD_SPENDSGIR1_SGI5_Set_pending (0x0000FF00u) +#define INTC_GICD_SPENDSGIR1_SGI5_Set_pending_SHIFT (8u) +#define INTC_GICD_SPENDSGIR1_SGI6_Set_pending (0x00FF0000u) +#define INTC_GICD_SPENDSGIR1_SGI6_Set_pending_SHIFT (16u) +#define INTC_GICD_SPENDSGIR1_SGI7_Set_pending (0xFF000000u) +#define INTC_GICD_SPENDSGIR1_SGI7_Set_pending_SHIFT (24u) +#define INTC_GICD_SPENDSGIR2_SGI8_Set_pending (0x000000FFu) +#define INTC_GICD_SPENDSGIR2_SGI8_Set_pending_SHIFT (0u) +#define INTC_GICD_SPENDSGIR2_SGI9_Set_pending (0x0000FF00u) +#define INTC_GICD_SPENDSGIR2_SGI9_Set_pending_SHIFT (8u) +#define INTC_GICD_SPENDSGIR2_SGI10_Set_pending (0x00FF0000u) +#define INTC_GICD_SPENDSGIR2_SGI10_Set_pending_SHIFT (16u) +#define INTC_GICD_SPENDSGIR2_SGI11_Set_pending (0xFF000000u) +#define INTC_GICD_SPENDSGIR2_SGI11_Set_pending_SHIFT (24u) +#define INTC_GICD_SPENDSGIR3_SGI12_Set_pending (0x000000FFu) +#define INTC_GICD_SPENDSGIR3_SGI12_Set_pending_SHIFT (0u) +#define INTC_GICD_SPENDSGIR3_SGI13_Set_pending (0x0000FF00u) +#define INTC_GICD_SPENDSGIR3_SGI13_Set_pending_SHIFT (8u) +#define INTC_GICD_SPENDSGIR3_SGI14_Set_pending (0x00FF0000u) +#define INTC_GICD_SPENDSGIR3_SGI14_Set_pending_SHIFT (16u) +#define INTC_GICD_SPENDSGIR3_SGI15_Set_pending (0xFF000000u) +#define INTC_GICD_SPENDSGIR3_SGI15_Set_pending_SHIFT (24u) +#define INTC_GICD_PIDR4_ARM_CCfield (0x0000000Fu) +#define INTC_GICD_PIDR4_ARM_CCfield_SHIFT (0u) +#define INTC_GICD_PIDR4_ARM_Reserved (0x000000F0u) +#define INTC_GICD_PIDR4_ARM_Reserved_SHIFT (4u) +#define INTC_GICD_PIDR5_ARM_Reserved (0x000000FFu) +#define INTC_GICD_PIDR5_ARM_Reserved_SHIFT (0u) +#define INTC_GICD_PIDR6_ARM_Reserved (0x000000FFu) +#define INTC_GICD_PIDR6_ARM_Reserved_SHIFT (0u) +#define INTC_GICD_PIDR7_ARM_Reserved (0x000000FFu) +#define INTC_GICD_PIDR7_ARM_Reserved_SHIFT (0u) +#define INTC_GICD_PIDR0_ARM_DIDfield (0x000000FFu) +#define INTC_GICD_PIDR0_ARM_DIDfield_SHIFT (0u) +#define INTC_GICD_PIDR1_ARM_DIDfield (0x0000000Fu) +#define INTC_GICD_PIDR1_ARM_DIDfield_SHIFT (0u) +#define INTC_GICD_PIDR1_ARM_AIDfield (0x000000F0u) +#define INTC_GICD_PIDR1_ARM_AIDfield_SHIFT (4u) +#define INTC_GICD_PIDR2_ARM_AIDfield (0x00000007u) +#define INTC_GICD_PIDR2_ARM_AIDfield_SHIFT (0u) +#define INTC_GICD_PIDR2_ARM_UJEPfield (0x00000008u) +#define INTC_GICD_PIDR2_ARM_UJEPfield_SHIFT (3u) +#define INTC_GICD_PIDR2_Arfield (0x000000F0u) +#define INTC_GICD_PIDR2_Arfield_SHIFT (4u) +#define INTC_GICD_PIDR3_ARM_Reserved (0x0000000Fu) +#define INTC_GICD_PIDR3_ARM_Reserved_SHIFT (0u) +#define INTC_GICD_PIDR3_ARM_Rfield (0x000000F0u) +#define INTC_GICD_PIDR3_ARM_Rfield_SHIFT (4u) +#define INTC_GICD_CIDR0_ARM_FVPCD (0x000000FFu) +#define INTC_GICD_CIDR0_ARM_FVPCD_SHIFT (0u) +#define INTC_GICD_CIDR1_ARM_FVPCD (0x000000FFu) +#define INTC_GICD_CIDR1_ARM_FVPCD_SHIFT (0u) +#define INTC_GICD_CIDR2_ARM_FVPCD (0x000000FFu) +#define INTC_GICD_CIDR2_ARM_FVPCD_SHIFT (0u) +#define INTC_GICD_CIDR3_ARM_FVPCD (0x000000FFu) +#define INTC_GICD_CIDR3_ARM_FVPCD_SHIFT (0u) +#define INTC_GICC_CTLR_EnableGrp0 (0x00000001u) +#define INTC_GICC_CTLR_EnableGrp0_SHIFT (0u) +#define INTC_GICC_CTLR_EnableGrp1 (0x00000002u) +#define INTC_GICC_CTLR_EnableGrp1_SHIFT (1u) +#define INTC_GICC_CTLR_AckCtl (0x00000004u) +#define INTC_GICC_CTLR_AckCtl_SHIFT (2u) +#define INTC_GICC_CTLR_FIQEn (0x00000008u) +#define INTC_GICC_CTLR_FIQEn_SHIFT (3u) +#define INTC_GICC_CTLR_CBPR (0x00000010u) +#define INTC_GICC_CTLR_CBPR_SHIFT (4u) +#define INTC_GICC_CTLR_FIQBypDisGrp0 (0x00000020u) +#define INTC_GICC_CTLR_FIQBypDisGrp0_SHIFT (5u) +#define INTC_GICC_CTLR_IRQBypDisGrp0 (0x00000040u) +#define INTC_GICC_CTLR_IRQBypDisGrp0_SHIFT (6u) +#define INTC_GICC_CTLR_FIQBypDisGrp1 (0x00000080u) +#define INTC_GICC_CTLR_FIQBypDisGrp1_SHIFT (7u) +#define INTC_GICC_CTLR_IRQBypDisGrp1 (0x00000100u) +#define INTC_GICC_CTLR_IRQBypDisGrp1_SHIFT (8u) +#define INTC_GICC_CTLR_EOImodeS (0x00000200u) +#define INTC_GICC_CTLR_EOImodeS_SHIFT (9u) +#define INTC_GICC_CTLR_EOImodeNS (0x00000400u) +#define INTC_GICC_CTLR_EOImodeNS_SHIFT (10u) +#define INTC_GICC_PMR_Priority (0x000000FFu) +#define INTC_GICC_PMR_Priority_SHIFT (0u) +#define INTC_GICC_BPR_Binarypoint (0x00000007u) +#define INTC_GICC_BPR_Binarypoint_SHIFT (0u) +#define INTC_GICC_IAR_InterruptID (0x000003FFu) +#define INTC_GICC_IAR_InterruptID_SHIFT (0u) +#define INTC_GICC_IAR_CPUID (0x00001C00u) +#define INTC_GICC_IAR_CPUID_SHIFT (10u) +#define INTC_GICC_EOIR_EOIINTID (0x000003FFu) +#define INTC_GICC_EOIR_EOIINTID_SHIFT (0u) +#define INTC_GICC_EOIR_CPUID (0x00001C00u) +#define INTC_GICC_EOIR_CPUID_SHIFT (10u) +#define INTC_GICC_RPR_Priority (0x000000FFu) +#define INTC_GICC_RPR_Priority_SHIFT (0u) +#define INTC_GICC_HPPIR_PENDINTID (0x000003FFu) +#define INTC_GICC_HPPIR_PENDINTID_SHIFT (0u) +#define INTC_GICC_HPPIR_CPUID (0x00001C00u) +#define INTC_GICC_HPPIR_CPUID_SHIFT (10u) +#define INTC_GICC_ABPR_Binarypoint (0x00000007u) +#define INTC_GICC_ABPR_Binarypoint_SHIFT (0u) +#define INTC_GICC_AIAR_InterruptID (0x000003FFu) +#define INTC_GICC_AIAR_InterruptID_SHIFT (0u) +#define INTC_GICC_AIAR_CPUID (0x00001C00u) +#define INTC_GICC_AIAR_CPUID_SHIFT (10u) +#define INTC_GICC_AEOIR_InterruptID (0x000003FFu) +#define INTC_GICC_AEOIR_InterruptID_SHIFT (0u) +#define INTC_GICC_AEOIR_CPUID (0x00001C00u) +#define INTC_GICC_AEOIR_CPUID_SHIFT (10u) +#define INTC_GICC_AHPPIR_PENDINTID (0x000003FFu) +#define INTC_GICC_AHPPIR_PENDINTID_SHIFT (0u) +#define INTC_GICC_AHPPIR_CPUID (0x00001C00u) +#define INTC_GICC_AHPPIR_CPUID_SHIFT (10u) +#define INTC_GICC_APR0_AP_Group0 (0xFFFFFFFFu) +#define INTC_GICC_APR0_AP_Group0_SHIFT (0u) +#define INTC_GICC_NSAPR0_AP_Group1 (0x0000FFFFu) +#define INTC_GICC_NSAPR0_AP_Group1_SHIFT (0u) +#define INTC_GICC_NSAPR0_AP_Group0 (0xFFFF0000u) +#define INTC_GICC_NSAPR0_AP_Group0_SHIFT (16u) +#define INTC_GICC_IIDR_Implementer (0x00000FFFu) +#define INTC_GICC_IIDR_Implementer_SHIFT (0u) +#define INTC_GICC_IIDR_Revision (0x0000F000u) +#define INTC_GICC_IIDR_Revision_SHIFT (12u) +#define INTC_GICC_IIDR_Architectureversion (0x000F0000u) +#define INTC_GICC_IIDR_Architectureversion_SHIFT (16u) +#define INTC_GICC_IIDR_ProductID (0xFFF00000u) +#define INTC_GICC_IIDR_ProductID_SHIFT (20u) +#define INTC_GICC_DIR_InterruptID (0x000003FFu) +#define INTC_GICC_DIR_InterruptID_SHIFT (0u) +#define INTC_GICC_DIR_CPUID (0x00001C00u) +#define INTC_GICC_DIR_CPUID_SHIFT (10u) +#define INTC_ICR0_NMIF (0x0002u) +#define INTC_ICR0_NMIF_SHIFT (1u) +#define INTC_ICR0_NMIE (0x0100u) +#define INTC_ICR0_NMIE_SHIFT (8u) +#define INTC_ICR0_NMIL (0x8000u) +#define INTC_ICR0_NMIL_SHIFT (15u) +#define INTC_ICR1_IRQ00S (0x0001u) +#define INTC_ICR1_IRQ00S_SHIFT (0u) +#define INTC_ICR1_IRQ01S (0x0002u) +#define INTC_ICR1_IRQ01S_SHIFT (1u) +#define INTC_ICR1_IRQ10S (0x0004u) +#define INTC_ICR1_IRQ10S_SHIFT (2u) +#define INTC_ICR1_IRQ11S (0x0008u) +#define INTC_ICR1_IRQ11S_SHIFT (3u) +#define INTC_ICR1_IRQ20S (0x0010u) +#define INTC_ICR1_IRQ20S_SHIFT (4u) +#define INTC_ICR1_IRQ21S (0x0020u) +#define INTC_ICR1_IRQ21S_SHIFT (5u) +#define INTC_ICR1_IRQ30S (0x0040u) +#define INTC_ICR1_IRQ30S_SHIFT (6u) +#define INTC_ICR1_IRQ31S (0x0080u) +#define INTC_ICR1_IRQ31S_SHIFT (7u) +#define INTC_ICR1_IRQ40S (0x0100u) +#define INTC_ICR1_IRQ40S_SHIFT (8u) +#define INTC_ICR1_IRQ41S (0x0200u) +#define INTC_ICR1_IRQ41S_SHIFT (9u) +#define INTC_ICR1_IRQ50S (0x0400u) +#define INTC_ICR1_IRQ50S_SHIFT (10u) +#define INTC_ICR1_IRQ51S (0x0800u) +#define INTC_ICR1_IRQ51S_SHIFT (11u) +#define INTC_ICR1_IRQ60S (0x1000u) +#define INTC_ICR1_IRQ60S_SHIFT (12u) +#define INTC_ICR1_IRQ61S (0x2000u) +#define INTC_ICR1_IRQ61S_SHIFT (13u) +#define INTC_ICR1_IRQ70S (0x4000u) +#define INTC_ICR1_IRQ70S_SHIFT (14u) +#define INTC_ICR1_IRQ71S (0x8000u) +#define INTC_ICR1_IRQ71S_SHIFT (15u) +#define INTC_IRQRR_IRQ0F (0x0001u) +#define INTC_IRQRR_IRQ0F_SHIFT (0u) +#define INTC_IRQRR_IRQ1F (0x0002u) +#define INTC_IRQRR_IRQ1F_SHIFT (1u) +#define INTC_IRQRR_IRQ2F (0x0004u) +#define INTC_IRQRR_IRQ2F_SHIFT (2u) +#define INTC_IRQRR_IRQ3F (0x0008u) +#define INTC_IRQRR_IRQ3F_SHIFT (3u) +#define INTC_IRQRR_IRQ4F (0x0010u) +#define INTC_IRQRR_IRQ4F_SHIFT (4u) +#define INTC_IRQRR_IRQ5F (0x0020u) +#define INTC_IRQRR_IRQ5F_SHIFT (5u) +#define INTC_IRQRR_IRQ6F (0x0040u) +#define INTC_IRQRR_IRQ6F_SHIFT (6u) +#define INTC_IRQRR_IRQ7F (0x0080u) +#define INTC_IRQRR_IRQ7F_SHIFT (7u) +#define INTC_IRQRR_IRQMSK (0x8000u) +#define INTC_IRQRR_IRQMSK_SHIFT (15u) +#define INTC_SSTBCCR0_DP (0x0001u) +#define INTC_SSTBCCR0_DP_SHIFT (0u) +#define INTC_SSTBCCR0_DM (0x0002u) +#define INTC_SSTBCCR0_DM_SHIFT (1u) +#define INTC_SSTBCCR0_VBUSIN (0x0100u) +#define INTC_SSTBCCR0_VBUSIN_SHIFT (8u) +#define INTC_SSTBCCR0_OVRCLR (0x0200u) +#define INTC_SSTBCCR0_OVRCLR_SHIFT (9u) +#define INTC_SSTBCCR0_CC1_RD (0x0400u) +#define INTC_SSTBCCR0_CC1_RD_SHIFT (10u) +#define INTC_SSTBCCR0_CC2_RD (0x0800u) +#define INTC_SSTBCCR0_CC2_RD_SHIFT (11u) +#define INTC_SSTBCCR1_DP (0x0001u) +#define INTC_SSTBCCR1_DP_SHIFT (0u) +#define INTC_SSTBCCR1_DM (0x0002u) +#define INTC_SSTBCCR1_DM_SHIFT (1u) +#define INTC_SSTBCCR1_VBUSIN (0x0100u) +#define INTC_SSTBCCR1_VBUSIN_SHIFT (8u) +#define INTC_SSTBCCR1_OVRCLR (0x0200u) +#define INTC_SSTBCCR1_OVRCLR_SHIFT (9u) +#define INTC_SSTBCCR1_CC1_RD (0x0400u) +#define INTC_SSTBCCR1_CC1_RD_SHIFT (10u) +#define INTC_SSTBCCR1_CC2_RD (0x0800u) +#define INTC_SSTBCCR1_CC2_RD_SHIFT (11u) +#define INTC_SSTBCRR0_DP (0x0001u) +#define INTC_SSTBCRR0_DP_SHIFT (0u) +#define INTC_SSTBCRR0_DM (0x0002u) +#define INTC_SSTBCRR0_DM_SHIFT (1u) +#define INTC_SSTBCRR0_VBUSIN (0x0100u) +#define INTC_SSTBCRR0_VBUSIN_SHIFT (8u) +#define INTC_SSTBCRR0_OVRCLR (0x0200u) +#define INTC_SSTBCRR0_OVRCLR_SHIFT (9u) +#define INTC_SSTBCRR0_CC1_RD (0x0400u) +#define INTC_SSTBCRR0_CC1_RD_SHIFT (10u) +#define INTC_SSTBCRR0_CC2_RD (0x0800u) +#define INTC_SSTBCRR0_CC2_RD_SHIFT (11u) +#define INTC_SSTBCRR1_DP (0x0001u) +#define INTC_SSTBCRR1_DP_SHIFT (0u) +#define INTC_SSTBCRR1_DM (0x0002u) +#define INTC_SSTBCRR1_DM_SHIFT (1u) +#define INTC_SSTBCRR1_VBUSIN (0x0100u) +#define INTC_SSTBCRR1_VBUSIN_SHIFT (8u) +#define INTC_SSTBCRR1_OVRCLR (0x0200u) +#define INTC_SSTBCRR1_OVRCLR_SHIFT (9u) +#define INTC_SSTBCRR1_CC1_RD (0x0400u) +#define INTC_SSTBCRR1_CC1_RD_SHIFT (10u) +#define INTC_SSTBCRR1_CC2_RD (0x0800u) +#define INTC_SSTBCRR1_CC2_RD_SHIFT (11u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/irda_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/irda_iobitmask.h new file mode 100644 index 0000000..f431030 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/irda_iobitmask.h @@ -0,0 +1,58 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef IRDA_IOBITMASK_H +#define IRDA_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define IRDA_IRCR_IRRXINV (0x04u) +#define IRDA_IRCR_IRRXINV_SHIFT (2u) +#define IRDA_IRCR_IRTXINV (0x08u) +#define IRDA_IRCR_IRTXINV_SHIFT (3u) +#define IRDA_IRCR_IRCKS (0x70u) +#define IRDA_IRCR_IRCKS_SHIFT (4u) +#define IRDA_IRCR_IRE (0x80u) +#define IRDA_IRCR_IRE_SHIFT (7u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/jcu_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/jcu_iobitmask.h new file mode 100644 index 0000000..d3b4bc3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/jcu_iobitmask.h @@ -0,0 +1,204 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef JCU_IOBITMASK_H +#define JCU_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define JCU_JCMOD_REDU (0x07u) +#define JCU_JCMOD_REDU_SHIFT (0u) +#define JCU_JCMOD_DSP (0x08u) +#define JCU_JCMOD_DSP_SHIFT (3u) +#define JCU_JCCMD_JSRT (0x01u) +#define JCU_JCCMD_JSRT_SHIFT (0u) +#define JCU_JCCMD_JRST (0x02u) +#define JCU_JCCMD_JRST_SHIFT (1u) +#define JCU_JCCMD_JEND (0x04u) +#define JCU_JCCMD_JEND_SHIFT (2u) +#define JCU_JCCMD_BRST (0x80u) +#define JCU_JCCMD_BRST_SHIFT (7u) +#define JCU_JCQTN_QT1 (0x03u) +#define JCU_JCQTN_QT1_SHIFT (0u) +#define JCU_JCQTN_QT2 (0x0Cu) +#define JCU_JCQTN_QT2_SHIFT (2u) +#define JCU_JCQTN_QT3 (0x30u) +#define JCU_JCQTN_QT3_SHIFT (4u) +#define JCU_JCHTN_HTD1 (0x01u) +#define JCU_JCHTN_HTD1_SHIFT (0u) +#define JCU_JCHTN_HTA1 (0x02u) +#define JCU_JCHTN_HTA1_SHIFT (1u) +#define JCU_JCHTN_HTD2 (0x04u) +#define JCU_JCHTN_HTD2_SHIFT (2u) +#define JCU_JCHTN_HTA2 (0x08u) +#define JCU_JCHTN_HTA2_SHIFT (3u) +#define JCU_JCHTN_HTD3 (0x10u) +#define JCU_JCHTN_HTD3_SHIFT (4u) +#define JCU_JCHTN_HTA3 (0x20u) +#define JCU_JCHTN_HTA3_SHIFT (5u) +#define JCU_JCDRIU_DRIU (0xFFu) +#define JCU_JCDRIU_DRIU_SHIFT (0u) +#define JCU_JCDRID_DRID (0xFFu) +#define JCU_JCDRID_DRID_SHIFT (0u) +#define JCU_JCVSZU_VSZU (0xFFu) +#define JCU_JCVSZU_VSZU_SHIFT (0u) +#define JCU_JCVSZD_VSZD (0xFFu) +#define JCU_JCVSZD_VSZD_SHIFT (0u) +#define JCU_JCHSZU_HSZU (0xFFu) +#define JCU_JCHSZU_HSZU_SHIFT (0u) +#define JCU_JCHSZD_HSZD (0xFFu) +#define JCU_JCHSZD_HSZD_SHIFT (0u) +#define JCU_JCDTCU_DCU (0xFFu) +#define JCU_JCDTCU_DCU_SHIFT (0u) +#define JCU_JCDTCM_DCM (0xFFu) +#define JCU_JCDTCM_DCM_SHIFT (0u) +#define JCU_JCDTCD_DCD (0xFFu) +#define JCU_JCDTCD_DCD_SHIFT (0u) +#define JCU_JINTE0_INT3 (0x08u) +#define JCU_JINTE0_INT3_SHIFT (3u) +#define JCU_JINTE0_INT5 (0x20u) +#define JCU_JINTE0_INT5_SHIFT (5u) +#define JCU_JINTE0_INT6 (0x40u) +#define JCU_JINTE0_INT6_SHIFT (6u) +#define JCU_JINTE0_INT7 (0x80u) +#define JCU_JINTE0_INT7_SHIFT (7u) +#define JCU_JINTS0_INS3 (0x08u) +#define JCU_JINTS0_INS3_SHIFT (3u) +#define JCU_JINTS0_INS5 (0x20u) +#define JCU_JINTS0_INS5_SHIFT (5u) +#define JCU_JINTS0_INS6 (0x40u) +#define JCU_JINTS0_INS6_SHIFT (6u) +#define JCU_JCDERR_ERR (0x0Fu) +#define JCU_JCDERR_ERR_SHIFT (0u) +#define JCU_JCRST_RST (0x01u) +#define JCU_JCRST_RST_SHIFT (0u) +#define JCU_JIFECNT_DINSWAP (0x00000007u) +#define JCU_JIFECNT_DINSWAP_SHIFT (0u) +#define JCU_JIFECNT_DINLC (0x00000010u) +#define JCU_JIFECNT_DINLC_SHIFT (4u) +#define JCU_JIFECNT_DINRCMD (0x00000020u) +#define JCU_JIFECNT_DINRCMD_SHIFT (5u) +#define JCU_JIFECNT_DINRINI (0x00000040u) +#define JCU_JIFECNT_DINRINI_SHIFT (6u) +#define JCU_JIFECNT_JOUTSWAP (0x00000700u) +#define JCU_JIFECNT_JOUTSWAP_SHIFT (8u) +#define JCU_JIFECNT_JOUTC (0x00001000u) +#define JCU_JIFECNT_JOUTC_SHIFT (12u) +#define JCU_JIFECNT_JOUTRCMD (0x00002000u) +#define JCU_JIFECNT_JOUTRCMD_SHIFT (13u) +#define JCU_JIFECNT_JOUTRINI (0x00004000u) +#define JCU_JIFECNT_JOUTRINI_SHIFT (14u) +#define JCU_JIFESA_ESA (0xFFFFFFFFu) +#define JCU_JIFESA_ESA_SHIFT (0u) +#define JCU_JIFESOFST_ESMW (0x00007FFFu) +#define JCU_JIFESOFST_ESMW_SHIFT (0u) +#define JCU_JIFEDA_EDA (0xFFFFFFFFu) +#define JCU_JIFEDA_EDA_SHIFT (0u) +#define JCU_JIFESLC_LINES (0x0000FFFFu) +#define JCU_JIFESLC_LINES_SHIFT (0u) +#define JCU_JIFEDDC_JDATAS (0x0000FFFFu) +#define JCU_JIFEDDC_JDATAS_SHIFT (0u) +#define JCU_JIFDCNT_DOUTSWAP (0x00000007u) +#define JCU_JIFDCNT_DOUTSWAP_SHIFT (0u) +#define JCU_JIFDCNT_DOUTLC (0x00000010u) +#define JCU_JIFDCNT_DOUTLC_SHIFT (4u) +#define JCU_JIFDCNT_DOUTRCMD (0x00000020u) +#define JCU_JIFDCNT_DOUTRCMD_SHIFT (5u) +#define JCU_JIFDCNT_DOUTRINI (0x00000040u) +#define JCU_JIFDCNT_DOUTRINI_SHIFT (6u) +#define JCU_JIFDCNT_JINSWAP (0x00000700u) +#define JCU_JIFDCNT_JINSWAP_SHIFT (8u) +#define JCU_JIFDCNT_JINC (0x00001000u) +#define JCU_JIFDCNT_JINC_SHIFT (12u) +#define JCU_JIFDCNT_JINRCMD (0x00002000u) +#define JCU_JIFDCNT_JINRCMD_SHIFT (13u) +#define JCU_JIFDCNT_JINRINI (0x00004000u) +#define JCU_JIFDCNT_JINRINI_SHIFT (14u) +#define JCU_JIFDCNT_OPF (0x03000000u) +#define JCU_JIFDCNT_OPF_SHIFT (24u) +#define JCU_JIFDCNT_HINTER (0x0C000000u) +#define JCU_JIFDCNT_HINTER_SHIFT (26u) +#define JCU_JIFDCNT_VINTER (0x30000000u) +#define JCU_JIFDCNT_VINTER_SHIFT (28u) +#define JCU_JIFDSA_DSA (0xFFFFFFFFu) +#define JCU_JIFDSA_DSA_SHIFT (0u) +#define JCU_JIFDDOFST_DDMW (0x00007FFFu) +#define JCU_JIFDDOFST_DDMW_SHIFT (0u) +#define JCU_JIFDDA_DDA (0xFFFFFFFFu) +#define JCU_JIFDDA_DDA_SHIFT (0u) +#define JCU_JIFDSDC_JDATAS (0x0000FFFFu) +#define JCU_JIFDSDC_JDATAS_SHIFT (0u) +#define JCU_JIFDDLC_LINES (0x0000FFFFu) +#define JCU_JIFDDLC_LINES_SHIFT (0u) +#define JCU_JIFDADT_ALPHA (0x000000FFu) +#define JCU_JIFDADT_ALPHA_SHIFT (0u) +#define JCU_JINTE1_DOUTLEN (0x00000001u) +#define JCU_JINTE1_DOUTLEN_SHIFT (0u) +#define JCU_JINTE1_JINEN (0x00000002u) +#define JCU_JINTE1_JINEN_SHIFT (1u) +#define JCU_JINTE1_DBTEN (0x00000004u) +#define JCU_JINTE1_DBTEN_SHIFT (2u) +#define JCU_JINTE1_JOUTEN (0x00000010u) +#define JCU_JINTE1_JOUTEN_SHIFT (4u) +#define JCU_JINTE1_DINLEN (0x00000020u) +#define JCU_JINTE1_DINLEN_SHIFT (5u) +#define JCU_JINTE1_CBTEN (0x00000040u) +#define JCU_JINTE1_CBTEN_SHIFT (6u) +#define JCU_JINTS1_DOUTLF (0x00000001u) +#define JCU_JINTS1_DOUTLF_SHIFT (0u) +#define JCU_JINTS1_JINF (0x00000002u) +#define JCU_JINTS1_JINF_SHIFT (1u) +#define JCU_JINTS1_DBTF (0x00000004u) +#define JCU_JINTS1_DBTF_SHIFT (2u) +#define JCU_JINTS1_JOUTF (0x00000010u) +#define JCU_JINTS1_JOUTF_SHIFT (4u) +#define JCU_JINTS1_DINLF (0x00000020u) +#define JCU_JINTS1_DINLF_SHIFT (5u) +#define JCU_JINTS1_CBTF (0x00000040u) +#define JCU_JINTS1_CBTF_SHIFT (6u) +#define JCU_JIFESVSZ_DINYCHG (0x00008000u) +#define JCU_JIFESVSZ_DINYCHG_SHIFT (15u) +#define JCU_JIFESHSZ_DOUTYCHG (0x00008000u) +#define JCU_JIFESHSZ_DOUTYCHG_SHIFT (15u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/lvds_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/lvds_iobitmask.h new file mode 100644 index 0000000..d6467b8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/lvds_iobitmask.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef LVDS_IOBITMASK_H +#define LVDS_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define LVDS_LVDS_UPDATE_LVDS_UPDATE (0x00010000u) +#define LVDS_LVDS_UPDATE_LVDS_UPDATE_SHIFT (16u) +#define LVDS_LVDSFCL_LVDS_SEL0 (0x0000000Fu) +#define LVDS_LVDSFCL_LVDS_SEL0_SHIFT (0u) +#define LVDS_LVDSFCL_LVDS_SEL1 (0x000000F0u) +#define LVDS_LVDSFCL_LVDS_SEL1_SHIFT (4u) +#define LVDS_LVDSFCL_LVDS_SEL2 (0x00000F00u) +#define LVDS_LVDSFCL_LVDS_SEL2_SHIFT (8u) +#define LVDS_LVDSFCL_SYNC_POL (0x00C00000u) +#define LVDS_LVDSFCL_SYNC_POL_SHIFT (22u) +#define LVDS_LVDSFCL_SYNC_MODE (0x10000000u) +#define LVDS_LVDSFCL_SYNC_MODE_SHIFT (28u) +#define LVDS_LCLKSELR_LVDS_CLK_EN (0x00000010u) +#define LVDS_LCLKSELR_LVDS_CLK_EN_SHIFT (4u) +#define LVDS_LCLKSELR_LVDS_ODIV_SET (0x00000300u) +#define LVDS_LCLKSELR_LVDS_ODIV_SET_SHIFT (8u) +#define LVDS_LCLKSELR_LVDSPLL_TST (0x0000FC00u) +#define LVDS_LCLKSELR_LVDSPLL_TST_SHIFT (10u) +#define LVDS_LCLKSELR_LVDS_IN_CLK_SEL (0x03000000u) +#define LVDS_LCLKSELR_LVDS_IN_CLK_SEL_SHIFT (24u) +#define LVDS_LPLLSETR_LVDSPLL_PD (0x00000001u) +#define LVDS_LPLLSETR_LVDSPLL_PD_SHIFT (0u) +#define LVDS_LPLLSETR_LVDSPLL_OD (0x00000030u) +#define LVDS_LPLLSETR_LVDSPLL_OD_SHIFT (4u) +#define LVDS_LPLLSETR_LVDSPLL_RD (0x00000700u) +#define LVDS_LPLLSETR_LVDSPLL_RD_SHIFT (8u) +#define LVDS_LPLLSETR_LVDSPLL_FD (0x007F0000u) +#define LVDS_LPLLSETR_LVDSPLL_FD_SHIFT (16u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/mtu_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/mtu_iobitmask.h new file mode 100644 index 0000000..4511995 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/mtu_iobitmask.h @@ -0,0 +1,586 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef MTU_IOBITMASK_H +#define MTU_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define MTU_TOERA_OE3B (0x01u) +#define MTU_TOERA_OE3B_SHIFT (0u) +#define MTU_TOERA_OE4A (0x02u) +#define MTU_TOERA_OE4A_SHIFT (1u) +#define MTU_TOERA_OE4B (0x04u) +#define MTU_TOERA_OE4B_SHIFT (2u) +#define MTU_TOERA_OE3D (0x08u) +#define MTU_TOERA_OE3D_SHIFT (3u) +#define MTU_TOERA_OE4C (0x10u) +#define MTU_TOERA_OE4C_SHIFT (4u) +#define MTU_TOERA_OE4D (0x20u) +#define MTU_TOERA_OE4D_SHIFT (5u) +#define MTU_TGCRA_UF (0x01u) +#define MTU_TGCRA_UF_SHIFT (0u) +#define MTU_TGCRA_VF (0x02u) +#define MTU_TGCRA_VF_SHIFT (1u) +#define MTU_TGCRA_WF (0x04u) +#define MTU_TGCRA_WF_SHIFT (2u) +#define MTU_TGCRA_FB (0x08u) +#define MTU_TGCRA_FB_SHIFT (3u) +#define MTU_TGCRA_P (0x10u) +#define MTU_TGCRA_P_SHIFT (4u) +#define MTU_TGCRA_N (0x20u) +#define MTU_TGCRA_N_SHIFT (5u) +#define MTU_TGCRA_BDC (0x40u) +#define MTU_TGCRA_BDC_SHIFT (6u) +#define MTU_TOCR1A_OLSP (0x01u) +#define MTU_TOCR1A_OLSP_SHIFT (0u) +#define MTU_TOCR1A_OLSN (0x02u) +#define MTU_TOCR1A_OLSN_SHIFT (1u) +#define MTU_TOCR1A_TOCS (0x04u) +#define MTU_TOCR1A_TOCS_SHIFT (2u) +#define MTU_TOCR1A_TOCL (0x08u) +#define MTU_TOCR1A_TOCL_SHIFT (3u) +#define MTU_TOCR1A_PSYE (0x40u) +#define MTU_TOCR1A_PSYE_SHIFT (6u) +#define MTU_TOCR2A_OLS1P (0x01u) +#define MTU_TOCR2A_OLS1P_SHIFT (0u) +#define MTU_TOCR2A_OLS1N (0x02u) +#define MTU_TOCR2A_OLS1N_SHIFT (1u) +#define MTU_TOCR2A_OLS2P (0x04u) +#define MTU_TOCR2A_OLS2P_SHIFT (2u) +#define MTU_TOCR2A_OLS2N (0x08u) +#define MTU_TOCR2A_OLS2N_SHIFT (3u) +#define MTU_TOCR2A_OLS3P (0x10u) +#define MTU_TOCR2A_OLS3P_SHIFT (4u) +#define MTU_TOCR2A_OLS3N (0x20u) +#define MTU_TOCR2A_OLS3N_SHIFT (5u) +#define MTU_TOCR2A_BF (0xC0u) +#define MTU_TOCR2A_BF_SHIFT (6u) +#define MTU_TCDRA_TCDRA (0xFFFFu) +#define MTU_TCDRA_TCDRA_SHIFT (0u) +#define MTU_TDDRA_TDDRA (0xFFFFu) +#define MTU_TDDRA_TDDRA_SHIFT (0u) +#define MTU_TCNTSA_TCNTSA (0xFFFFu) +#define MTU_TCNTSA_TCNTSA_SHIFT (0u) +#define MTU_TCBRA_TCBRA (0xFFFFu) +#define MTU_TCBRA_TCBRA_SHIFT (0u) +#define MTU_TITCR1A_T4VCOR (0x07u) +#define MTU_TITCR1A_T4VCOR_SHIFT (0u) +#define MTU_TITCR1A_T4VEN (0x08u) +#define MTU_TITCR1A_T4VEN_SHIFT (3u) +#define MTU_TITCR1A_T3ACOR (0x70u) +#define MTU_TITCR1A_T3ACOR_SHIFT (4u) +#define MTU_TITCR1A_T3AEN (0x80u) +#define MTU_TITCR1A_T3AEN_SHIFT (7u) +#define MTU_TITCNT1A_T4VCNT (0x07u) +#define MTU_TITCNT1A_T4VCNT_SHIFT (0u) +#define MTU_TITCNT1A_T3ACNT (0x70u) +#define MTU_TITCNT1A_T3ACNT_SHIFT (4u) +#define MTU_TBTERA_BTE (0x03u) +#define MTU_TBTERA_BTE_SHIFT (0u) +#define MTU_TDERA_TDER (0x01u) +#define MTU_TDERA_TDER_SHIFT (0u) +#define MTU_TOLBRA_OLS1P (0x01u) +#define MTU_TOLBRA_OLS1P_SHIFT (0u) +#define MTU_TOLBRA_OLS1N (0x02u) +#define MTU_TOLBRA_OLS1N_SHIFT (1u) +#define MTU_TOLBRA_OLS2P (0x04u) +#define MTU_TOLBRA_OLS2P_SHIFT (2u) +#define MTU_TOLBRA_OLS2N (0x08u) +#define MTU_TOLBRA_OLS2N_SHIFT (3u) +#define MTU_TOLBRA_OLS3P (0x10u) +#define MTU_TOLBRA_OLS3P_SHIFT (4u) +#define MTU_TOLBRA_OLS3N (0x20u) +#define MTU_TOLBRA_OLS3N_SHIFT (5u) +#define MTU_TITMRA_TITM (0x01u) +#define MTU_TITMRA_TITM_SHIFT (0u) +#define MTU_TITCR2A_TRG4COR (0x07u) +#define MTU_TITCR2A_TRG4COR_SHIFT (0u) +#define MTU_TITCNT2A_TRG4CNT (0x07u) +#define MTU_TITCNT2A_TRG4CNT_SHIFT (0u) +#define MTU_TWCRA_WRE (0x01u) +#define MTU_TWCRA_WRE_SHIFT (0u) +#define MTU_TWCRA_SCC (0x02u) +#define MTU_TWCRA_SCC_SHIFT (1u) +#define MTU_TWCRA_CCE (0x80u) +#define MTU_TWCRA_CCE_SHIFT (7u) +#define MTU_TMDR2A_DRS (0x01u) +#define MTU_TMDR2A_DRS_SHIFT (0u) +#define MTU_TSTRA_CST0 (0x01u) +#define MTU_TSTRA_CST0_SHIFT (0u) +#define MTU_TSTRA_CST1 (0x02u) +#define MTU_TSTRA_CST1_SHIFT (1u) +#define MTU_TSTRA_CST2 (0x04u) +#define MTU_TSTRA_CST2_SHIFT (2u) +#define MTU_TSTRA_CST8 (0x08u) +#define MTU_TSTRA_CST8_SHIFT (3u) +#define MTU_TSTRA_CST3 (0x40u) +#define MTU_TSTRA_CST3_SHIFT (6u) +#define MTU_TSTRA_CST4 (0x80u) +#define MTU_TSTRA_CST4_SHIFT (7u) +#define MTU_TSYRA_SYNC0 (0x01u) +#define MTU_TSYRA_SYNC0_SHIFT (0u) +#define MTU_TSYRA_SYNC1 (0x02u) +#define MTU_TSYRA_SYNC1_SHIFT (1u) +#define MTU_TSYRA_SYNC2 (0x04u) +#define MTU_TSYRA_SYNC2_SHIFT (2u) +#define MTU_TSYRA_SYNC3 (0x40u) +#define MTU_TSYRA_SYNC3_SHIFT (6u) +#define MTU_TSYRA_SYNC4 (0x80u) +#define MTU_TSYRA_SYNC4_SHIFT (7u) +#define MTU_TCSYSTR_SCH7 (0x01u) +#define MTU_TCSYSTR_SCH7_SHIFT (0u) +#define MTU_TCSYSTR_SCH6 (0x02u) +#define MTU_TCSYSTR_SCH6_SHIFT (1u) +#define MTU_TCSYSTR_SCH4 (0x08u) +#define MTU_TCSYSTR_SCH4_SHIFT (3u) +#define MTU_TCSYSTR_SCH3 (0x10u) +#define MTU_TCSYSTR_SCH3_SHIFT (4u) +#define MTU_TCSYSTR_SCH2 (0x20u) +#define MTU_TCSYSTR_SCH2_SHIFT (5u) +#define MTU_TCSYSTR_SCH1 (0x40u) +#define MTU_TCSYSTR_SCH1_SHIFT (6u) +#define MTU_TCSYSTR_SCH0 (0x80u) +#define MTU_TCSYSTR_SCH0_SHIFT (7u) +#define MTU_TRWERA_RWE (0x01u) +#define MTU_TRWERA_RWE_SHIFT (0u) +#define MTU_TOERB_OE6B (0x01u) +#define MTU_TOERB_OE6B_SHIFT (0u) +#define MTU_TOERB_OE7A (0x02u) +#define MTU_TOERB_OE7A_SHIFT (1u) +#define MTU_TOERB_OE7B (0x04u) +#define MTU_TOERB_OE7B_SHIFT (2u) +#define MTU_TOERB_OE6D (0x08u) +#define MTU_TOERB_OE6D_SHIFT (3u) +#define MTU_TOERB_OE7C (0x10u) +#define MTU_TOERB_OE7C_SHIFT (4u) +#define MTU_TOERB_OE7D (0x20u) +#define MTU_TOERB_OE7D_SHIFT (5u) +#define MTU_TOCR1B_OLSP (0x01u) +#define MTU_TOCR1B_OLSP_SHIFT (0u) +#define MTU_TOCR1B_OLSN (0x02u) +#define MTU_TOCR1B_OLSN_SHIFT (1u) +#define MTU_TOCR1B_TOCS (0x04u) +#define MTU_TOCR1B_TOCS_SHIFT (2u) +#define MTU_TOCR1B_TOCL (0x08u) +#define MTU_TOCR1B_TOCL_SHIFT (3u) +#define MTU_TOCR1B_PSYE (0x40u) +#define MTU_TOCR1B_PSYE_SHIFT (6u) +#define MTU_TOCR2B_OLS1P (0x01u) +#define MTU_TOCR2B_OLS1P_SHIFT (0u) +#define MTU_TOCR2B_OLS1N (0x02u) +#define MTU_TOCR2B_OLS1N_SHIFT (1u) +#define MTU_TOCR2B_OLS2P (0x04u) +#define MTU_TOCR2B_OLS2P_SHIFT (2u) +#define MTU_TOCR2B_OLS2N (0x08u) +#define MTU_TOCR2B_OLS2N_SHIFT (3u) +#define MTU_TOCR2B_OLS3P (0x10u) +#define MTU_TOCR2B_OLS3P_SHIFT (4u) +#define MTU_TOCR2B_OLS3N (0x20u) +#define MTU_TOCR2B_OLS3N_SHIFT (5u) +#define MTU_TOCR2B_BF (0xC0u) +#define MTU_TOCR2B_BF_SHIFT (6u) +#define MTU_TCDRB_TCDRB (0xFFFFu) +#define MTU_TCDRB_TCDRB_SHIFT (0u) +#define MTU_TDDRB_TDDRB (0xFFFFu) +#define MTU_TDDRB_TDDRB_SHIFT (0u) +#define MTU_TCNTSB_TCNTSB (0xFFFFu) +#define MTU_TCNTSB_TCNTSB_SHIFT (0u) +#define MTU_TCBRB_TCBRB (0xFFFFu) +#define MTU_TCBRB_TCBRB_SHIFT (0u) +#define MTU_TITCR1B_T7VCOR (0x07u) +#define MTU_TITCR1B_T7VCOR_SHIFT (0u) +#define MTU_TITCR1B_T7VEN (0x08u) +#define MTU_TITCR1B_T7VEN_SHIFT (3u) +#define MTU_TITCR1B_T6ACOR (0x70u) +#define MTU_TITCR1B_T6ACOR_SHIFT (4u) +#define MTU_TITCR1B_T6AEN (0x80u) +#define MTU_TITCR1B_T6AEN_SHIFT (7u) +#define MTU_TITCNT1B_T7VCNT (0x07u) +#define MTU_TITCNT1B_T7VCNT_SHIFT (0u) +#define MTU_TITCNT1B_T6ACNT (0x70u) +#define MTU_TITCNT1B_T6ACNT_SHIFT (4u) +#define MTU_TBTERB_BTE (0x03u) +#define MTU_TBTERB_BTE_SHIFT (0u) +#define MTU_TDERB_TDER (0x01u) +#define MTU_TDERB_TDER_SHIFT (0u) +#define MTU_TOLBRB_OLS1P (0x01u) +#define MTU_TOLBRB_OLS1P_SHIFT (0u) +#define MTU_TOLBRB_OLS1N (0x02u) +#define MTU_TOLBRB_OLS1N_SHIFT (1u) +#define MTU_TOLBRB_OLS2P (0x04u) +#define MTU_TOLBRB_OLS2P_SHIFT (2u) +#define MTU_TOLBRB_OLS2N (0x08u) +#define MTU_TOLBRB_OLS2N_SHIFT (3u) +#define MTU_TOLBRB_OLS3P (0x10u) +#define MTU_TOLBRB_OLS3P_SHIFT (4u) +#define MTU_TOLBRB_OLS3N (0x20u) +#define MTU_TOLBRB_OLS3N_SHIFT (5u) +#define MTU_TITMRB_TITM (0x01u) +#define MTU_TITMRB_TITM_SHIFT (0u) +#define MTU_TITCR2B_TRG7COR (0x07u) +#define MTU_TITCR2B_TRG7COR_SHIFT (0u) +#define MTU_TITCNT2B_TRG7CNT (0x07u) +#define MTU_TITCNT2B_TRG7CNT_SHIFT (0u) +#define MTU_TWCRB_WRE (0x01u) +#define MTU_TWCRB_WRE_SHIFT (0u) +#define MTU_TWCRB_SCC (0x02u) +#define MTU_TWCRB_SCC_SHIFT (1u) +#define MTU_TWCRB_CCE (0x80u) +#define MTU_TWCRB_CCE_SHIFT (7u) +#define MTU_TMDR2B_DRS (0x01u) +#define MTU_TMDR2B_DRS_SHIFT (0u) +#define MTU_TSTRB_CST6 (0x40u) +#define MTU_TSTRB_CST6_SHIFT (6u) +#define MTU_TSTRB_CST7 (0x80u) +#define MTU_TSTRB_CST7_SHIFT (7u) +#define MTU_TSYRB_SYNC6 (0x40u) +#define MTU_TSYRB_SYNC6_SHIFT (6u) +#define MTU_TSYRB_SYNC7 (0x80u) +#define MTU_TSYRB_SYNC7_SHIFT (7u) +#define MTU_TRWERB_RWE (0x01u) +#define MTU_TRWERB_RWE_SHIFT (0u) +#define MTU_NFCR0_NFAEN (0x01u) +#define MTU_NFCR0_NFAEN_SHIFT (0u) +#define MTU_NFCR0_NFBEN (0x02u) +#define MTU_NFCR0_NFBEN_SHIFT (1u) +#define MTU_NFCR0_NFCEN (0x04u) +#define MTU_NFCR0_NFCEN_SHIFT (2u) +#define MTU_NFCR0_NFDEN (0x08u) +#define MTU_NFCR0_NFDEN_SHIFT (3u) +#define MTU_NFCR0_NFCS (0x30u) +#define MTU_NFCR0_NFCS_SHIFT (4u) +#define MTU_NFCRC_NFAEN (0x01u) +#define MTU_NFCRC_NFAEN_SHIFT (0u) +#define MTU_NFCRC_NFBEN (0x02u) +#define MTU_NFCRC_NFBEN_SHIFT (1u) +#define MTU_NFCRC_NFCEN (0x04u) +#define MTU_NFCRC_NFCEN_SHIFT (2u) +#define MTU_NFCRC_NFDEN (0x08u) +#define MTU_NFCRC_NFDEN_SHIFT (3u) +#define MTU_NFCRC_NFCSC (0x30u) +#define MTU_NFCRC_NFCSC_SHIFT (4u) +#define MTU_TCR_TPSC (0x07u) +#define MTU_TCR_TPSC_SHIFT (0u) +#define MTU_TCR_CKEG (0x18u) +#define MTU_TCR_CKEG_SHIFT (3u) +#define MTU_TCR_CCLR (0xE0u) +#define MTU_TCR_CCLR_SHIFT (5u) +#define MTU_TMDR1_MD (0x0Fu) +#define MTU_TMDR1_MD_SHIFT (0u) +#define MTU_TMDR1_BFA (0x10u) +#define MTU_TMDR1_BFA_SHIFT (4u) +#define MTU_TMDR1_BFB (0x20u) +#define MTU_TMDR1_BFB_SHIFT (5u) +#define MTU_TMDR1_BFE (0x40u) +#define MTU_TMDR1_BFE_SHIFT (6u) +#define MTU_TIORH_IOA (0x0Fu) +#define MTU_TIORH_IOA_SHIFT (0u) +#define MTU_TIORH_IOB (0xF0u) +#define MTU_TIORH_IOB_SHIFT (4u) +#define MTU_TIORL_IOC (0x0Fu) +#define MTU_TIORL_IOC_SHIFT (0u) +#define MTU_TIORL_IOD (0xF0u) +#define MTU_TIORL_IOD_SHIFT (4u) +#define MTU_TIER_TGIEA (0x01u) +#define MTU_TIER_TGIEA_SHIFT (0u) +#define MTU_TIER_TGIEB (0x02u) +#define MTU_TIER_TGIEB_SHIFT (1u) +#define MTU_TIER_TGIEC (0x04u) +#define MTU_TIER_TGIEC_SHIFT (2u) +#define MTU_TIER_TGIED (0x08u) +#define MTU_TIER_TGIED_SHIFT (3u) +#define MTU_TIER_TCIEV (0x10u) +#define MTU_TIER_TCIEV_SHIFT (4u) +#define MTU_TIER_TTGE (0x80u) +#define MTU_TIER_TTGE_SHIFT (7u) +#define MTU_TCNT_TCNT (0xFFFFu) +#define MTU_TCNT_TCNT_SHIFT (0u) +#define MTU_TGRA_TGRA (0xFFFFu) +#define MTU_TGRA_TGRA_SHIFT (0u) +#define MTU_TGRB_TGRB (0xFFFFu) +#define MTU_TGRB_TGRB_SHIFT (0u) +#define MTU_TGRC_TGRC (0xFFFFu) +#define MTU_TGRC_TGRC_SHIFT (0u) +#define MTU_TGRD_TGRD (0xFFFFu) +#define MTU_TGRD_TGRD_SHIFT (0u) +#define MTU_TGRE_TGRE (0xFFFFu) +#define MTU_TGRE_TGRE_SHIFT (0u) +#define MTU_TGRF_TGRF (0xFFFFu) +#define MTU_TGRF_TGRF_SHIFT (0u) +#define MTU_TIER2_TGIEE (0x01u) +#define MTU_TIER2_TGIEE_SHIFT (0u) +#define MTU_TIER2_TGIEF (0x02u) +#define MTU_TIER2_TGIEF_SHIFT (1u) +#define MTU_TIER2_TTGE2 (0x80u) +#define MTU_TIER2_TTGE2_SHIFT (7u) +#define MTU_TBTM_TTSA (0x01u) +#define MTU_TBTM_TTSA_SHIFT (0u) +#define MTU_TBTM_TTSB (0x02u) +#define MTU_TBTM_TTSB_SHIFT (1u) +#define MTU_TBTM_TTSE (0x04u) +#define MTU_TBTM_TTSE_SHIFT (2u) +#define MTU_TCR2_TPSC2 (0x07u) +#define MTU_TCR2_TPSC2_SHIFT (0u) +#define MTU_NFCR1_NFAEN (0x01u) +#define MTU_NFCR1_NFAEN_SHIFT (0u) +#define MTU_NFCR1_NFBEN (0x02u) +#define MTU_NFCR1_NFBEN_SHIFT (1u) +#define MTU_NFCR1_NFCEN (0x04u) +#define MTU_NFCR1_NFCEN_SHIFT (2u) +#define MTU_NFCR1_NFDEN (0x08u) +#define MTU_NFCR1_NFDEN_SHIFT (3u) +#define MTU_NFCR1_NFCS (0x30u) +#define MTU_NFCR1_NFCS_SHIFT (4u) +#define MTU_TIOR_IOA (0x0Fu) +#define MTU_TIOR_IOA_SHIFT (0u) +#define MTU_TIOR_IOB (0xF0u) +#define MTU_TIOR_IOB_SHIFT (4u) +#define MTU_TIER_TCIEU (0x20u) +#define MTU_TIER_TCIEU_SHIFT (5u) +#define MTU_TSR_TCFD (0x80u) +#define MTU_TSR_TCFD_SHIFT (7u) +#define MTU_TICCR_I1AE (0x01u) +#define MTU_TICCR_I1AE_SHIFT (0u) +#define MTU_TICCR_I1BE (0x02u) +#define MTU_TICCR_I1BE_SHIFT (1u) +#define MTU_TICCR_I2AE (0x04u) +#define MTU_TICCR_I2AE_SHIFT (2u) +#define MTU_TICCR_I2BE (0x08u) +#define MTU_TICCR_I2BE_SHIFT (3u) +#define MTU_TMDR3_LWA (0x01u) +#define MTU_TMDR3_LWA_SHIFT (0u) +#define MTU_TMDR3_PHCKSEL (0x02u) +#define MTU_TMDR3_PHCKSEL_SHIFT (1u) +#define MTU_TCR2_PCB (0x18u) +#define MTU_TCR2_PCB_SHIFT (3u) +#define MTU_TCNTLW_TCNTLW (0xFFFFFFFFu) +#define MTU_TCNTLW_TCNTLW_SHIFT (0u) +#define MTU_TGRALW_TGRALW (0xFFFFFFFFu) +#define MTU_TGRALW_TGRALW_SHIFT (0u) +#define MTU_TGRBLW_TGRBLW (0xFFFFFFFFu) +#define MTU_TGRBLW_TGRBLW_SHIFT (0u) +#define MTU_NFCR2_NFAEN (0x01u) +#define MTU_NFCR2_NFAEN_SHIFT (0u) +#define MTU_NFCR2_NFBEN (0x02u) +#define MTU_NFCR2_NFBEN_SHIFT (1u) +#define MTU_NFCR2_NFCEN (0x04u) +#define MTU_NFCR2_NFCEN_SHIFT (2u) +#define MTU_NFCR2_NFDEN (0x08u) +#define MTU_NFCR2_NFDEN_SHIFT (3u) +#define MTU_NFCR2_NFCS (0x30u) +#define MTU_NFCR2_NFCS_SHIFT (4u) +#define MTU_NFCR3_NFAEN (0x01u) +#define MTU_NFCR3_NFAEN_SHIFT (0u) +#define MTU_NFCR3_NFBEN (0x02u) +#define MTU_NFCR3_NFBEN_SHIFT (1u) +#define MTU_NFCR3_NFCEN (0x04u) +#define MTU_NFCR3_NFCEN_SHIFT (2u) +#define MTU_NFCR3_NFDEN (0x08u) +#define MTU_NFCR3_NFDEN_SHIFT (3u) +#define MTU_NFCR3_NFCS (0x30u) +#define MTU_NFCR3_NFCS_SHIFT (4u) +#define MTU_TIER_TTGE2 (0x40u) +#define MTU_TIER_TTGE2_SHIFT (6u) +#define MTU_TADCR_ITB4VE (0x0001u) +#define MTU_TADCR_ITB4VE_SHIFT (0u) +#define MTU_TADCR_ITB3AE (0x0002u) +#define MTU_TADCR_ITB3AE_SHIFT (1u) +#define MTU_TADCR_ITA4VE (0x0004u) +#define MTU_TADCR_ITA4VE_SHIFT (2u) +#define MTU_TADCR_ITA3AE (0x0008u) +#define MTU_TADCR_ITA3AE_SHIFT (3u) +#define MTU_TADCR_DT4BE (0x0010u) +#define MTU_TADCR_DT4BE_SHIFT (4u) +#define MTU_TADCR_UT4BE (0x0020u) +#define MTU_TADCR_UT4BE_SHIFT (5u) +#define MTU_TADCR_DT4AE (0x0040u) +#define MTU_TADCR_DT4AE_SHIFT (6u) +#define MTU_TADCR_UT4AE (0x0080u) +#define MTU_TADCR_UT4AE_SHIFT (7u) +#define MTU_TADCR_BF (0xC000u) +#define MTU_TADCR_BF_SHIFT (14u) +#define MTU_TADCORA_TADCORA (0xFFFFu) +#define MTU_TADCORA_TADCORA_SHIFT (0u) +#define MTU_TADCORB_TADCORB (0xFFFFu) +#define MTU_TADCORB_TADCORB_SHIFT (0u) +#define MTU_TADCOBRA_TADCOBRA (0xFFFFu) +#define MTU_TADCOBRA_TADCOBRA_SHIFT (0u) +#define MTU_TADCOBRB_TADCOBRB (0xFFFFu) +#define MTU_TADCOBRB_TADCOBRB_SHIFT (0u) +#define MTU_NFCR4_NFAEN (0x01u) +#define MTU_NFCR4_NFAEN_SHIFT (0u) +#define MTU_NFCR4_NFBEN (0x02u) +#define MTU_NFCR4_NFBEN_SHIFT (1u) +#define MTU_NFCR4_NFCEN (0x04u) +#define MTU_NFCR4_NFCEN_SHIFT (2u) +#define MTU_NFCR4_NFDEN (0x08u) +#define MTU_NFCR4_NFDEN_SHIFT (3u) +#define MTU_NFCR4_NFCS (0x30u) +#define MTU_NFCR4_NFCS_SHIFT (4u) +#define MTU_NFCR5_NFUEN (0x01u) +#define MTU_NFCR5_NFUEN_SHIFT (0u) +#define MTU_NFCR5_NFVEN (0x02u) +#define MTU_NFCR5_NFVEN_SHIFT (1u) +#define MTU_NFCR5_NFWEN (0x04u) +#define MTU_NFCR5_NFWEN_SHIFT (2u) +#define MTU_NFCR5_NFCS (0x30u) +#define MTU_NFCR5_NFCS_SHIFT (4u) +#define MTU_TCNTU_TCNTU (0xFFFFu) +#define MTU_TCNTU_TCNTU_SHIFT (0u) +#define MTU_TGRU_TGRU (0xFFFFu) +#define MTU_TGRU_TGRU_SHIFT (0u) +#define MTU_TCRU_TPSC (0x03u) +#define MTU_TCRU_TPSC_SHIFT (0u) +#define MTU_TCR2U_TPSC2 (0x07u) +#define MTU_TCR2U_TPSC2_SHIFT (0u) +#define MTU_TCR2U_CKEG (0x18u) +#define MTU_TCR2U_CKEG_SHIFT (3u) +#define MTU_TIORU_IOC (0x1Fu) +#define MTU_TIORU_IOC_SHIFT (0u) +#define MTU_TCNTV_TCNTV (0xFFFFu) +#define MTU_TCNTV_TCNTV_SHIFT (0u) +#define MTU_TGRV_TGRV (0xFFFFu) +#define MTU_TGRV_TGRV_SHIFT (0u) +#define MTU_TCRV_TPSC (0x03u) +#define MTU_TCRV_TPSC_SHIFT (0u) +#define MTU_TCR2V_TPSC2 (0x07u) +#define MTU_TCR2V_TPSC2_SHIFT (0u) +#define MTU_TCR2V_CKEG (0x18u) +#define MTU_TCR2V_CKEG_SHIFT (3u) +#define MTU_TIORV_IOC (0x1Fu) +#define MTU_TIORV_IOC_SHIFT (0u) +#define MTU_TCNTW_TCNTW (0xFFFFu) +#define MTU_TCNTW_TCNTW_SHIFT (0u) +#define MTU_TGRW_TGRW (0xFFFFu) +#define MTU_TGRW_TGRW_SHIFT (0u) +#define MTU_TCRW_TPSC (0x03u) +#define MTU_TCRW_TPSC_SHIFT (0u) +#define MTU_TCR2W_TPSC2 (0x07u) +#define MTU_TCR2W_TPSC2_SHIFT (0u) +#define MTU_TCR2W_CKEG (0x18u) +#define MTU_TCR2W_CKEG_SHIFT (3u) +#define MTU_TIORW_IOC (0x1Fu) +#define MTU_TIORW_IOC_SHIFT (0u) +#define MTU_TIER_TGIE5W (0x01u) +#define MTU_TIER_TGIE5W_SHIFT (0u) +#define MTU_TIER_TGIE5V (0x02u) +#define MTU_TIER_TGIE5V_SHIFT (1u) +#define MTU_TIER_TGIE5U (0x04u) +#define MTU_TIER_TGIE5U_SHIFT (2u) +#define MTU_TSTR_CSTW5 (0x01u) +#define MTU_TSTR_CSTW5_SHIFT (0u) +#define MTU_TSTR_CSTV5 (0x02u) +#define MTU_TSTR_CSTV5_SHIFT (1u) +#define MTU_TSTR_CSTU5 (0x04u) +#define MTU_TSTR_CSTU5_SHIFT (2u) +#define MTU_TCNTCMPCLR_CMPCLR5W (0x01u) +#define MTU_TCNTCMPCLR_CMPCLR5W_SHIFT (0u) +#define MTU_TCNTCMPCLR_CMPCLR5V (0x02u) +#define MTU_TCNTCMPCLR_CMPCLR5V_SHIFT (1u) +#define MTU_TCNTCMPCLR_CMPCLR5U (0x04u) +#define MTU_TCNTCMPCLR_CMPCLR5U_SHIFT (2u) +#define MTU_TSYCR_CE2B (0x01u) +#define MTU_TSYCR_CE2B_SHIFT (0u) +#define MTU_TSYCR_CE2A (0x02u) +#define MTU_TSYCR_CE2A_SHIFT (1u) +#define MTU_TSYCR_CE1B (0x04u) +#define MTU_TSYCR_CE1B_SHIFT (2u) +#define MTU_TSYCR_CE1A (0x08u) +#define MTU_TSYCR_CE1A_SHIFT (3u) +#define MTU_TSYCR_CE0D (0x10u) +#define MTU_TSYCR_CE0D_SHIFT (4u) +#define MTU_TSYCR_CE0C (0x20u) +#define MTU_TSYCR_CE0C_SHIFT (5u) +#define MTU_TSYCR_CE0B (0x40u) +#define MTU_TSYCR_CE0B_SHIFT (6u) +#define MTU_TSYCR_CE0A (0x80u) +#define MTU_TSYCR_CE0A_SHIFT (7u) +#define MTU_NFCR6_NFAEN (0x01u) +#define MTU_NFCR6_NFAEN_SHIFT (0u) +#define MTU_NFCR6_NFBEN (0x02u) +#define MTU_NFCR6_NFBEN_SHIFT (1u) +#define MTU_NFCR6_NFCEN (0x04u) +#define MTU_NFCR6_NFCEN_SHIFT (2u) +#define MTU_NFCR6_NFDEN (0x08u) +#define MTU_NFCR6_NFDEN_SHIFT (3u) +#define MTU_NFCR6_NFCS (0x30u) +#define MTU_NFCR6_NFCS_SHIFT (4u) +#define MTU_TADCR_ITB7VE (0x0001u) +#define MTU_TADCR_ITB7VE_SHIFT (0u) +#define MTU_TADCR_ITB6AE (0x0002u) +#define MTU_TADCR_ITB6AE_SHIFT (1u) +#define MTU_TADCR_ITA7VE (0x0004u) +#define MTU_TADCR_ITA7VE_SHIFT (2u) +#define MTU_TADCR_ITA6AE (0x0008u) +#define MTU_TADCR_ITA6AE_SHIFT (3u) +#define MTU_TADCR_DT7BE (0x0010u) +#define MTU_TADCR_DT7BE_SHIFT (4u) +#define MTU_TADCR_UT7BE (0x0020u) +#define MTU_TADCR_UT7BE_SHIFT (5u) +#define MTU_TADCR_DT7AE (0x0040u) +#define MTU_TADCR_DT7AE_SHIFT (6u) +#define MTU_TADCR_UT7AE (0x0080u) +#define MTU_TADCR_UT7AE_SHIFT (7u) +#define MTU_NFCR7_NFAEN (0x01u) +#define MTU_NFCR7_NFAEN_SHIFT (0u) +#define MTU_NFCR7_NFBEN (0x02u) +#define MTU_NFCR7_NFBEN_SHIFT (1u) +#define MTU_NFCR7_NFCEN (0x04u) +#define MTU_NFCR7_NFCEN_SHIFT (2u) +#define MTU_NFCR7_NFDEN (0x08u) +#define MTU_NFCR7_NFDEN_SHIFT (3u) +#define MTU_NFCR7_NFCS (0x30u) +#define MTU_NFCR7_NFCS_SHIFT (4u) +#define MTU_NFCR8_NFAEN (0x01u) +#define MTU_NFCR8_NFAEN_SHIFT (0u) +#define MTU_NFCR8_NFBEN (0x02u) +#define MTU_NFCR8_NFBEN_SHIFT (1u) +#define MTU_NFCR8_NFCEN (0x04u) +#define MTU_NFCR8_NFCEN_SHIFT (2u) +#define MTU_NFCR8_NFDEN (0x08u) +#define MTU_NFCR8_NFDEN_SHIFT (3u) +#define MTU_NFCR8_NFCS (0x30u) +#define MTU_NFCR8_NFCS_SHIFT (4u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/nandc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/nandc_iobitmask.h new file mode 100644 index 0000000..8245df6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/nandc_iobitmask.h @@ -0,0 +1,280 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef NANDC_IOBITMASK_H +#define NANDC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define NANDC_COMMAND_CMD_SEQ (0x0000003Fu) +#define NANDC_COMMAND_CMD_SEQ_SHIFT (0u) +#define NANDC_COMMAND_INPUT_SEL (0x00000040u) +#define NANDC_COMMAND_INPUT_SEL_SHIFT (6u) +#define NANDC_COMMAND_DATA_SEL (0x00000080u) +#define NANDC_COMMAND_DATA_SEL_SHIFT (7u) +#define NANDC_COMMAND_CMD_0 (0x0000FF00u) +#define NANDC_COMMAND_CMD_0_SHIFT (8u) +#define NANDC_COMMAND_CMD_1 (0x00FF0000u) +#define NANDC_COMMAND_CMD_1_SHIFT (16u) +#define NANDC_COMMAND_CMD_2 (0xFF000000u) +#define NANDC_COMMAND_CMD_2_SHIFT (24u) +#define NANDC_CONTROL_READ_STATUS_EN (0x00000001u) +#define NANDC_CONTROL_READ_STATUS_EN_SHIFT (0u) +#define NANDC_CONTROL_ECC_BLOCK_SIZE (0x00000006u) +#define NANDC_CONTROL_ECC_BLOCK_SIZE_SHIFT (1u) +#define NANDC_CONTROL_INT_EN (0x00000010u) +#define NANDC_CONTROL_INT_EN_SHIFT (4u) +#define NANDC_CONTROL_ECC_EN (0x00000020u) +#define NANDC_CONTROL_ECC_EN_SHIFT (5u) +#define NANDC_CONTROL_BLOCK_SIZE (0x000000C0u) +#define NANDC_CONTROL_BLOCK_SIZE_SHIFT (6u) +#define NANDC_CONTROL_BBM_EN (0x00002000u) +#define NANDC_CONTROL_BBM_EN_SHIFT (13u) +#define NANDC_CONTROL_PROT_EN (0x00004000u) +#define NANDC_CONTROL_PROT_EN_SHIFT (14u) +#define NANDC_CONTROL_ADDR0_AUTO_INCR (0x00010000u) +#define NANDC_CONTROL_ADDR0_AUTO_INCR_SHIFT (16u) +#define NANDC_CONTROL_ADDR1_AUTO_INCR (0x00020000u) +#define NANDC_CONTROL_ADDR1_AUTO_INCR_SHIFT (17u) +#define NANDC_CONTROL_SMALL_BLOCK_EN (0x00200000u) +#define NANDC_CONTROL_SMALL_BLOCK_EN_SHIFT (21u) +#define NANDC_CONTROL_MLUN_EN (0x00400000u) +#define NANDC_CONTROL_MLUN_EN_SHIFT (22u) +#define NANDC_CONTROL_AUTO_READ_STAT_EN (0x00800000u) +#define NANDC_CONTROL_AUTO_READ_STAT_EN_SHIFT (23u) +#define NANDC_STATUS_MEM0_ST (0x00000001u) +#define NANDC_STATUS_MEM0_ST_SHIFT (0u) +#define NANDC_STATUS_CTRL_STAT (0x00000100u) +#define NANDC_STATUS_CTRL_STAT_SHIFT (8u) +#define NANDC_STATUS_DATASIZE_ERROR_ST (0x00000200u) +#define NANDC_STATUS_DATASIZE_ERROR_ST_SHIFT (9u) +#define NANDC_STATUS_DATA_REG_ST (0x00000400u) +#define NANDC_STATUS_DATA_REG_ST_SHIFT (10u) +#define NANDC_STATUS_CMD_ID (0x00FF0000u) +#define NANDC_STATUS_CMD_ID_SHIFT (16u) +#define NANDC_STATUS_MASK_STATE_MASK (0x000000FFu) +#define NANDC_STATUS_MASK_STATE_MASK_SHIFT (0u) +#define NANDC_STATUS_MASK_ERROR_MASK (0x0000FF00u) +#define NANDC_STATUS_MASK_ERROR_MASK_SHIFT (8u) +#define NANDC_INT_MASK_PROT_INT_EN (0x00000001u) +#define NANDC_INT_MASK_PROT_INT_EN_SHIFT (0u) +#define NANDC_INT_MASK_CMD_END_INT_EN (0x00000002u) +#define NANDC_INT_MASK_CMD_END_INT_EN_SHIFT (1u) +#define NANDC_INT_MASK_DATA_REG_INT_EN (0x00000004u) +#define NANDC_INT_MASK_DATA_REG_INT_EN_SHIFT (2u) +#define NANDC_INT_MASK_DMA_INT_EN (0x00000008u) +#define NANDC_INT_MASK_DMA_INT_EN_SHIFT (3u) +#define NANDC_INT_MASK_TRANS_ERR_EN (0x00000010u) +#define NANDC_INT_MASK_TRANS_ERR_EN_SHIFT (4u) +#define NANDC_INT_MASK_PG_SZ_ERR_INT_EN (0x00000040u) +#define NANDC_INT_MASK_PG_SZ_ERR_INT_EN_SHIFT (6u) +#define NANDC_INT_MASK_MEM0_RDY_INT_EN (0x00000100u) +#define NANDC_INT_MASK_MEM0_RDY_INT_EN_SHIFT (8u) +#define NANDC_INT_MASK_STAT_ERR_INT0_EN (0x00010000u) +#define NANDC_INT_MASK_STAT_ERR_INT0_EN_SHIFT (16u) +#define NANDC_INT_MASK_ECC_INT0_EN (0x01000000u) +#define NANDC_INT_MASK_ECC_INT0_EN_SHIFT (24u) +#define NANDC_INT_STATUS_PROT_INT_FL (0x00000001u) +#define NANDC_INT_STATUS_PROT_INT_FL_SHIFT (0u) +#define NANDC_INT_STATUS_CMD_END_INT_FL (0x00000002u) +#define NANDC_INT_STATUS_CMD_END_INT_FL_SHIFT (1u) +#define NANDC_INT_STATUS_DATA_REG_INT_FL (0x00000004u) +#define NANDC_INT_STATUS_DATA_REG_INT_FL_SHIFT (2u) +#define NANDC_INT_STATUS_DMA_INT_FL (0x00000008u) +#define NANDC_INT_STATUS_DMA_INT_FL_SHIFT (3u) +#define NANDC_INT_STATUS_TRANS_ERR_FL (0x00000010u) +#define NANDC_INT_STATUS_TRANS_ERR_FL_SHIFT (4u) +#define NANDC_INT_STATUS_PG_SZ_ERR_INT_FL (0x00000040u) +#define NANDC_INT_STATUS_PG_SZ_ERR_INT_FL_SHIFT (6u) +#define NANDC_INT_STATUS_MEM0_RDY_INT_FL (0x00000100u) +#define NANDC_INT_STATUS_MEM0_RDY_INT_FL_SHIFT (8u) +#define NANDC_INT_STATUS_STAT_ERR_INT0_FL (0x00010000u) +#define NANDC_INT_STATUS_STAT_ERR_INT0_FL_SHIFT (16u) +#define NANDC_INT_STATUS_ECC_INT0_FL (0x01000000u) +#define NANDC_INT_STATUS_ECC_INT0_FL_SHIFT (24u) +#define NANDC_ECC_CTRL_ECC_CAP (0x00000007u) +#define NANDC_ECC_CTRL_ECC_CAP_SHIFT (0u) +#define NANDC_ECC_CTRL_ERR_THRESHOLD (0x00003F00u) +#define NANDC_ECC_CTRL_ERR_THRESHOLD_SHIFT (8u) +#define NANDC_ECC_CTRL_ECC_SEL (0x00030000u) +#define NANDC_ECC_CTRL_ECC_SEL_SHIFT (16u) +#define NANDC_ECC_OFFSET_ECC_OFFSET (0x0000FFFFu) +#define NANDC_ECC_OFFSET_ECC_OFFSET_SHIFT (0u) +#define NANDC_ECC_STAT_ECC_ERROR_0 (0x00000001u) +#define NANDC_ECC_STAT_ECC_ERROR_0_SHIFT (0u) +#define NANDC_ECC_STAT_ECC_UNC_0 (0x00000100u) +#define NANDC_ECC_STAT_ECC_UNC_0_SHIFT (8u) +#define NANDC_ECC_STAT_ECC_OVER_0 (0x00010000u) +#define NANDC_ECC_STAT_ECC_OVER_0_SHIFT (16u) +#define NANDC_ADDR0_COL_ADDR0_COL (0x0000FFFFu) +#define NANDC_ADDR0_COL_ADDR0_COL_SHIFT (0u) +#define NANDC_ADDR0_ROW_ADDR0_ROW (0x00FFFFFFu) +#define NANDC_ADDR0_ROW_ADDR0_ROW_SHIFT (0u) +#define NANDC_ADDR1_COL_ADDR1_COL (0x0000FFFFu) +#define NANDC_ADDR1_COL_ADDR1_COL_SHIFT (0u) +#define NANDC_ADDR1_ROW_ADDR1_ROW (0x00FFFFFFu) +#define NANDC_ADDR1_ROW_ADDR1_ROW_SHIFT (0u) +#define NANDC_FIFO_DATA_FIFO_DATA (0xFFFFFFFFu) +#define NANDC_FIFO_DATA_FIFO_DATA_SHIFT (0u) +#define NANDC_DATA_REG_DATA_REG (0xFFFFFFFFu) +#define NANDC_DATA_REG_DATA_REG_SHIFT (0u) +#define NANDC_DATA_REG_SIZE_DATA_REG_SIZE (0x00000003u) +#define NANDC_DATA_REG_SIZE_DATA_REG_SIZE_SHIFT (0u) +#define NANDC_DEV0_PTR_PTR_ADDR (0x00000FF0u) +#define NANDC_DEV0_PTR_PTR_ADDR_SHIFT (2u) +#define NANDC_DMA_ADDR_L_DMA_ADDR_L (0xFFFFFFFFu) +#define NANDC_DMA_ADDR_L_DMA_ADDR_L_SHIFT (0u) +#define NANDC_DMA_CNT_CNT_INIT (0xFFFFFFFFu) +#define NANDC_DMA_CNT_CNT_INIT_SHIFT (0u) +#define NANDC_DMA_CTRL_DMA_READY (0x00000001u) +#define NANDC_DMA_CTRL_DMA_READY_SHIFT (0u) +#define NANDC_DMA_CTRL_DMA_BURST (0x0000001Cu) +#define NANDC_DMA_CTRL_DMA_BURST_SHIFT (2u) +#define NANDC_DMA_CTRL_DMA_MODE (0x00000020u) +#define NANDC_DMA_CTRL_DMA_MODE_SHIFT (5u) +#define NANDC_DMA_CTRL_DMA_START (0x00000080u) +#define NANDC_DMA_CTRL_DMA_START_SHIFT (7u) +#define NANDC_BBM_CTRL_RMP_INIT (0x00000001u) +#define NANDC_BBM_CTRL_RMP_INIT_SHIFT (0u) +#define NANDC_DATA_SIZE_DATA_SIZE (0x00007FFFu) +#define NANDC_DATA_SIZE_DATA_SIZE_SHIFT (0u) +#define NANDC_TIMINGS_ASYN_TRWP (0x0000000Fu) +#define NANDC_TIMINGS_ASYN_TRWP_SHIFT (0u) +#define NANDC_TIMINGS_ASYN_TRWH (0x000000F0u) +#define NANDC_TIMINGS_ASYN_TRWH_SHIFT (4u) +#define NANDC_TIME_SEQ_0_TCCS (0x0000003Fu) +#define NANDC_TIME_SEQ_0_TCCS_SHIFT (0u) +#define NANDC_TIME_SEQ_0_TADL (0x00003F00u) +#define NANDC_TIME_SEQ_0_TADL_SHIFT (8u) +#define NANDC_TIME_SEQ_0_TRHW (0x003F0000u) +#define NANDC_TIME_SEQ_0_TRHW_SHIFT (16u) +#define NANDC_TIME_SEQ_0_TWHR (0x3F000000u) +#define NANDC_TIME_SEQ_0_TWHR_SHIFT (24u) +#define NANDC_TIME_SEQ_1_TWB (0x0000003Fu) +#define NANDC_TIME_SEQ_1_TWB_SHIFT (0u) +#define NANDC_TIME_SEQ_1_TRR (0x00003F00u) +#define NANDC_TIME_SEQ_1_TRR_SHIFT (8u) +#define NANDC_TIME_GEN_SEQ_0_t0_d0 (0x0000003Fu) +#define NANDC_TIME_GEN_SEQ_0_t0_d0_SHIFT (0u) +#define NANDC_TIME_GEN_SEQ_0_t0_d1 (0x00003F00u) +#define NANDC_TIME_GEN_SEQ_0_t0_d1_SHIFT (8u) +#define NANDC_TIME_GEN_SEQ_0_t0_d2 (0x003F0000u) +#define NANDC_TIME_GEN_SEQ_0_t0_d2_SHIFT (16u) +#define NANDC_TIME_GEN_SEQ_0_t0_d3 (0x3F000000u) +#define NANDC_TIME_GEN_SEQ_0_t0_d3_SHIFT (24u) +#define NANDC_TIME_GEN_SEQ_1_t0_d4 (0x0000003Fu) +#define NANDC_TIME_GEN_SEQ_1_t0_d4_SHIFT (0u) +#define NANDC_TIME_GEN_SEQ_1_t0_d5 (0x00003F00u) +#define NANDC_TIME_GEN_SEQ_1_t0_d5_SHIFT (8u) +#define NANDC_TIME_GEN_SEQ_1_t0_d6 (0x003F0000u) +#define NANDC_TIME_GEN_SEQ_1_t0_d6_SHIFT (16u) +#define NANDC_TIME_GEN_SEQ_1_t0_d7 (0x3F000000u) +#define NANDC_TIME_GEN_SEQ_1_t0_d7_SHIFT (24u) +#define NANDC_TIME_GEN_SEQ_2_t0_d8 (0x0000003Fu) +#define NANDC_TIME_GEN_SEQ_2_t0_d8_SHIFT (0u) +#define NANDC_TIME_GEN_SEQ_2_t0_d9 (0x00003F00u) +#define NANDC_TIME_GEN_SEQ_2_t0_d9_SHIFT (8u) +#define NANDC_TIME_GEN_SEQ_2_t0_d10 (0x003F0000u) +#define NANDC_TIME_GEN_SEQ_2_t0_d10_SHIFT (16u) +#define NANDC_TIME_GEN_SEQ_2_t0_d11 (0x3F000000u) +#define NANDC_TIME_GEN_SEQ_2_t0_d11_SHIFT (24u) +#define NANDC_FIFO_INIT_FIFO_INIT (0x00000001u) +#define NANDC_FIFO_INIT_FIFO_INIT_SHIFT (0u) +#define NANDC_FIFO_STATE_DF_R_EMPTY (0x00000001u) +#define NANDC_FIFO_STATE_DF_R_EMPTY_SHIFT (0u) +#define NANDC_FIFO_STATE_DF_W_FULL (0x00000002u) +#define NANDC_FIFO_STATE_DF_W_FULL_SHIFT (1u) +#define NANDC_FIFO_STATE_CF_EMPTY (0x00000004u) +#define NANDC_FIFO_STATE_CF_EMPTY_SHIFT (2u) +#define NANDC_FIFO_STATE_CF_FULL (0x00000008u) +#define NANDC_FIFO_STATE_CF_FULL_SHIFT (3u) +#define NANDC_FIFO_STATE_CF_ACCPT_R (0x00000010u) +#define NANDC_FIFO_STATE_CF_ACCPT_R_SHIFT (4u) +#define NANDC_FIFO_STATE_CF_ACCPT_W (0x00000020u) +#define NANDC_FIFO_STATE_CF_ACCPT_W_SHIFT (5u) +#define NANDC_FIFO_STATE_DF_R_FULL (0x00000040u) +#define NANDC_FIFO_STATE_DF_R_FULL_SHIFT (6u) +#define NANDC_FIFO_STATE_DF_W_EMPTY (0x00000080u) +#define NANDC_FIFO_STATE_DF_W_EMPTY_SHIFT (7u) +#define NANDC_GEN_SEQ_CTRL_CMD0_EN (0x00000001u) +#define NANDC_GEN_SEQ_CTRL_CMD0_EN_SHIFT (0u) +#define NANDC_GEN_SEQ_CTRL_CMD1_EN (0x00000002u) +#define NANDC_GEN_SEQ_CTRL_CMD1_EN_SHIFT (1u) +#define NANDC_GEN_SEQ_CTRL_CMD2_EN (0x00000004u) +#define NANDC_GEN_SEQ_CTRL_CMD2_EN_SHIFT (2u) +#define NANDC_GEN_SEQ_CTRL_CMD3_EN (0x00000008u) +#define NANDC_GEN_SEQ_CTRL_CMD3_EN_SHIFT (3u) +#define NANDC_GEN_SEQ_CTRL_COL_A0 (0x00000030u) +#define NANDC_GEN_SEQ_CTRL_COL_A0_SHIFT (4u) +#define NANDC_GEN_SEQ_CTRL_COL_A1 (0x000000C0u) +#define NANDC_GEN_SEQ_CTRL_COL_A1_SHIFT (6u) +#define NANDC_GEN_SEQ_CTRL_ROW_A0 (0x00000300u) +#define NANDC_GEN_SEQ_CTRL_ROW_A0_SHIFT (8u) +#define NANDC_GEN_SEQ_CTRL_ROW_A1 (0x00000C00u) +#define NANDC_GEN_SEQ_CTRL_ROW_A1_SHIFT (10u) +#define NANDC_GEN_SEQ_CTRL_DATA_EN (0x00001000u) +#define NANDC_GEN_SEQ_CTRL_DATA_EN_SHIFT (12u) +#define NANDC_GEN_SEQ_CTRL_DELAY_EN (0x00006000u) +#define NANDC_GEN_SEQ_CTRL_DELAY_EN_SHIFT (13u) +#define NANDC_GEN_SEQ_CTRL_IMD_SEQ (0x00008000u) +#define NANDC_GEN_SEQ_CTRL_IMD_SEQ_SHIFT (15u) +#define NANDC_GEN_SEQ_CTRL_CMD_3 (0x00FF0000u) +#define NANDC_GEN_SEQ_CTRL_CMD_3_SHIFT (16u) +#define NANDC_MLUN_MLUN_IDX (0x00000007u) +#define NANDC_MLUN_MLUN_IDX_SHIFT (0u) +#define NANDC_MLUN_LUN_SEL (0x00000300u) +#define NANDC_MLUN_LUN_SEL_SHIFT (8u) +#define NANDC_DEV0_SIZE_DEV_SIZE (0x00000FFFu) +#define NANDC_DEV0_SIZE_DEV_SIZE_SHIFT (0u) +#define NANDC_DMA_TRIG_TLVL_DMA_TRIG_TLVL (0x000000FFu) +#define NANDC_DMA_TRIG_TLVL_DMA_TRIG_TLVL_SHIFT (0u) +#define NANDC_CMD_MARK_CMD_ID (0x000000FFu) +#define NANDC_CMD_MARK_CMD_ID_SHIFT (0u) +#define NANDC_LUN_STATUS0_MEM0_LUN (0x000000FFu) +#define NANDC_LUN_STATUS0_MEM0_LUN_SHIFT (0u) +#define NANDC_TIME_GEN_SEQ_3_t0_d12 (0x0000003Fu) +#define NANDC_TIME_GEN_SEQ_3_t0_d12_SHIFT (0u) +#define NANDC_ECC_CNT_ERR_LVL (0x0000003Fu) +#define NANDC_ECC_CNT_ERR_LVL_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/octa_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/octa_iobitmask.h new file mode 100644 index 0000000..98df0cc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/octa_iobitmask.h @@ -0,0 +1,222 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef OCTA_IOBITMASK_H +#define OCTA_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define OCTA_DCR_DVCMD0 (0x000000FFu) +#define OCTA_DCR_DVCMD0_SHIFT (0u) +#define OCTA_DCR_DVCMD1 (0x0000FF00u) +#define OCTA_DCR_DVCMD1_SHIFT (8u) +#define OCTA_DAR_DVAD0 (0x000000FFu) +#define OCTA_DAR_DVAD0_SHIFT (0u) +#define OCTA_DAR_DVAD1 (0x0000FF00u) +#define OCTA_DAR_DVAD1_SHIFT (8u) +#define OCTA_DAR_DVAD2 (0x00FF0000u) +#define OCTA_DAR_DVAD2_SHIFT (16u) +#define OCTA_DAR_DVAD3 (0xFF000000u) +#define OCTA_DAR_DVAD3_SHIFT (24u) +#define OCTA_DCSR_DALEN (0x000000FFu) +#define OCTA_DCSR_DALEN_SHIFT (0u) +#define OCTA_DCSR_DMLEN (0x0000FF00u) +#define OCTA_DCSR_DMLEN_SHIFT (8u) +#define OCTA_DCSR_ACDV (0x00080000u) +#define OCTA_DCSR_ACDV_SHIFT (19u) +#define OCTA_DCSR_CMDLEN (0x00700000u) +#define OCTA_DCSR_CMDLEN_SHIFT (20u) +#define OCTA_DCSR_DAOR (0x00800000u) +#define OCTA_DCSR_DAOR_SHIFT (23u) +#define OCTA_DCSR_ADLEN (0x07000000u) +#define OCTA_DCSR_ADLEN_SHIFT (24u) +#define OCTA_DCSR_DOPI (0x08000000u) +#define OCTA_DCSR_DOPI_SHIFT (27u) +#define OCTA_DCSR_ACDA (0x10000000u) +#define OCTA_DCSR_ACDA_SHIFT (28u) +#define OCTA_DSR0_DV0SZ (0x3FFFFFFFu) +#define OCTA_DSR0_DV0SZ_SHIFT (0u) +#define OCTA_DSR0_DV0TYP (0xC0000000u) +#define OCTA_DSR0_DV0TYP_SHIFT (30u) +#define OCTA_DSR1_DV1SZ (0x3FFFFFFFu) +#define OCTA_DSR1_DV1SZ_SHIFT (0u) +#define OCTA_DSR1_DV1TYP (0xC0000000u) +#define OCTA_DSR1_DV1TYP_SHIFT (30u) +#define OCTA_MDTR_DV0DEL (0x000000FFu) +#define OCTA_MDTR_DV0DEL_SHIFT (0u) +#define OCTA_MDTR_DQSERAM (0x00000F00u) +#define OCTA_MDTR_DQSERAM_SHIFT (8u) +#define OCTA_MDTR_DQSESOPI (0x0000F000u) +#define OCTA_MDTR_DQSESOPI_SHIFT (12u) +#define OCTA_MDTR_DV1DEL (0x00FF0000u) +#define OCTA_MDTR_DV1DEL_SHIFT (16u) +#define OCTA_MDTR_DQSEDOPI (0x0F000000u) +#define OCTA_MDTR_DQSEDOPI_SHIFT (24u) +#define OCTA_ACTR_CTP (0xFFFFFFFFu) +#define OCTA_ACTR_CTP_SHIFT (0u) +#define OCTA_ACAR0_CAD0 (0xFFFFFFFFu) +#define OCTA_ACAR0_CAD0_SHIFT (0u) +#define OCTA_ACAR1_CAD1 (0xFFFFFFFFu) +#define OCTA_ACAR1_CAD1_SHIFT (0u) +#define OCTA_DRCSTR_CTRW0 (0x0000007Fu) +#define OCTA_DRCSTR_CTRW0_SHIFT (0u) +#define OCTA_DRCSTR_CTR0 (0x00000080u) +#define OCTA_DRCSTR_CTR0_SHIFT (7u) +#define OCTA_DRCSTR_DVRDCMD0 (0x00000700u) +#define OCTA_DRCSTR_DVRDCMD0_SHIFT (8u) +#define OCTA_DRCSTR_DVRDHI0 (0x00003800u) +#define OCTA_DRCSTR_DVRDHI0_SHIFT (11u) +#define OCTA_DRCSTR_DVRDLO0 (0x0000C000u) +#define OCTA_DRCSTR_DVRDLO0_SHIFT (14u) +#define OCTA_DRCSTR_CTRW1 (0x007F0000u) +#define OCTA_DRCSTR_CTRW1_SHIFT (16u) +#define OCTA_DRCSTR_CTR1 (0x00800000u) +#define OCTA_DRCSTR_CTR1_SHIFT (23u) +#define OCTA_DRCSTR_DVRDCMD1 (0x07000000u) +#define OCTA_DRCSTR_DVRDCMD1_SHIFT (24u) +#define OCTA_DRCSTR_DVRDHI1 (0x38000000u) +#define OCTA_DRCSTR_DVRDHI1_SHIFT (27u) +#define OCTA_DRCSTR_DVRDLO1 (0xC0000000u) +#define OCTA_DRCSTR_DVRDLO1_SHIFT (30u) +#define OCTA_DWCSTR_DVWCMD0 (0x00000700u) +#define OCTA_DWCSTR_DVWCMD0_SHIFT (8u) +#define OCTA_DWCSTR_DVWHI0 (0x00003800u) +#define OCTA_DWCSTR_DVWHI0_SHIFT (11u) +#define OCTA_DWCSTR_DVWLO0 (0x0000C000u) +#define OCTA_DWCSTR_DVWLO0_SHIFT (14u) +#define OCTA_DWCSTR_DVWCMD1 (0x07000000u) +#define OCTA_DWCSTR_DVWCMD1_SHIFT (24u) +#define OCTA_DWCSTR_DVWHI1 (0x38000000u) +#define OCTA_DWCSTR_DVWHI1_SHIFT (27u) +#define OCTA_DWCSTR_DVWLO1 (0xC0000000u) +#define OCTA_DWCSTR_DVWLO1_SHIFT (30u) +#define OCTA_DCSTR_DVSELCMD (0x00000700u) +#define OCTA_DCSTR_DVSELCMD_SHIFT (8u) +#define OCTA_DCSTR_DVSELHI (0x00003800u) +#define OCTA_DCSTR_DVSELHI_SHIFT (11u) +#define OCTA_DCSTR_DVSELLO (0x0000C000u) +#define OCTA_DCSTR_DVSELLO_SHIFT (14u) +#define OCTA_CDSR_DV0TTYP (0x00000003u) +#define OCTA_CDSR_DV0TTYP_SHIFT (0u) +#define OCTA_CDSR_DV1TTYP (0x0000000Cu) +#define OCTA_CDSR_DV1TTYP_SHIFT (2u) +#define OCTA_CDSR_DV0PC (0x00000010u) +#define OCTA_CDSR_DV0PC_SHIFT (4u) +#define OCTA_CDSR_DV1PC (0x00000020u) +#define OCTA_CDSR_DV1PC_SHIFT (5u) +#define OCTA_CDSR_ACMEME (0x00000C00u) +#define OCTA_CDSR_ACMEME_SHIFT (10u) +#define OCTA_CDSR_ACMODE (0x00003000u) +#define OCTA_CDSR_ACMODE_SHIFT (12u) +#define OCTA_CDSR_DLFT (0x80000000u) +#define OCTA_CDSR_DLFT_SHIFT (31u) +#define OCTA_MDLR_DV0RDL (0x000000FFu) +#define OCTA_MDLR_DV0RDL_SHIFT (0u) +#define OCTA_MDLR_DV0WDL (0x0000FF00u) +#define OCTA_MDLR_DV0WDL_SHIFT (8u) +#define OCTA_MDLR_DV1RDL (0x00FF0000u) +#define OCTA_MDLR_DV1RDL_SHIFT (16u) +#define OCTA_MDLR_DV1WDL (0xFF000000u) +#define OCTA_MDLR_DV1WDL_SHIFT (24u) +#define OCTA_MRWCR0_D0MRCMD0 (0x000000FFu) +#define OCTA_MRWCR0_D0MRCMD0_SHIFT (0u) +#define OCTA_MRWCR0_D0MRCMD1 (0x0000FF00u) +#define OCTA_MRWCR0_D0MRCMD1_SHIFT (8u) +#define OCTA_MRWCR0_D0MWCMD0 (0x00FF0000u) +#define OCTA_MRWCR0_D0MWCMD0_SHIFT (16u) +#define OCTA_MRWCR0_D0MWCMD1 (0xFF000000u) +#define OCTA_MRWCR0_D0MWCMD1_SHIFT (24u) +#define OCTA_MRWCR1_D1MRCMD0 (0x000000FFu) +#define OCTA_MRWCR1_D1MRCMD0_SHIFT (0u) +#define OCTA_MRWCR1_D1MRCMD1 (0x0000FF00u) +#define OCTA_MRWCR1_D1MRCMD1_SHIFT (8u) +#define OCTA_MRWCR1_D1MWCMD0 (0x00FF0000u) +#define OCTA_MRWCR1_D1MWCMD0_SHIFT (16u) +#define OCTA_MRWCR1_D1MWCMD1 (0xFF000000u) +#define OCTA_MRWCR1_D1MWCMD1_SHIFT (24u) +#define OCTA_MRWCSR_MRAL0 (0x00000007u) +#define OCTA_MRWCSR_MRAL0_SHIFT (0u) +#define OCTA_MRWCSR_MRCL0 (0x00000038u) +#define OCTA_MRWCSR_MRCL0_SHIFT (3u) +#define OCTA_MRWCSR_MRO0 (0x00000040u) +#define OCTA_MRWCSR_MRO0_SHIFT (6u) +#define OCTA_MRWCSR_MWAL0 (0x00000700u) +#define OCTA_MRWCSR_MWAL0_SHIFT (8u) +#define OCTA_MRWCSR_MWCL0 (0x00003800u) +#define OCTA_MRWCSR_MWCL0_SHIFT (11u) +#define OCTA_MRWCSR_MWO0 (0x00004000u) +#define OCTA_MRWCSR_MWO0_SHIFT (14u) +#define OCTA_MRWCSR_MRAL1 (0x00070000u) +#define OCTA_MRWCSR_MRAL1_SHIFT (16u) +#define OCTA_MRWCSR_MRCL1 (0x00380000u) +#define OCTA_MRWCSR_MRCL1_SHIFT (19u) +#define OCTA_MRWCSR_MRO1 (0x00400000u) +#define OCTA_MRWCSR_MRO1_SHIFT (22u) +#define OCTA_MRWCSR_MWAL1 (0x07000000u) +#define OCTA_MRWCSR_MWAL1_SHIFT (24u) +#define OCTA_MRWCSR_MWCL1 (0x38000000u) +#define OCTA_MRWCSR_MWCL1_SHIFT (27u) +#define OCTA_MRWCSR_MWO1 (0x40000000u) +#define OCTA_MRWCSR_MWO1_SHIFT (30u) +#define OCTA_ESR_MRESR (0x000000FFu) +#define OCTA_ESR_MRESR_SHIFT (0u) +#define OCTA_ESR_MWESR (0x0000FF00u) +#define OCTA_ESR_MWESR_SHIFT (8u) +#define OCTA_CWDR_WD0 (0x000000FFu) +#define OCTA_CWDR_WD0_SHIFT (0u) +#define OCTA_CWDR_WD1 (0x0000FF00u) +#define OCTA_CWDR_WD1_SHIFT (8u) +#define OCTA_CWDR_WD2 (0x00FF0000u) +#define OCTA_CWDR_WD2_SHIFT (16u) +#define OCTA_CWDR_WD3 (0xFF000000u) +#define OCTA_CWDR_WD3_SHIFT (24u) +#define OCTA_CRR_RD0 (0x000000FFu) +#define OCTA_CRR_RD0_SHIFT (0u) +#define OCTA_CRR_RD1 (0x0000FF00u) +#define OCTA_CRR_RD1_SHIFT (8u) +#define OCTA_CRR_RD2 (0x00FF0000u) +#define OCTA_CRR_RD2_SHIFT (16u) +#define OCTA_CRR_RD3 (0xFF000000u) +#define OCTA_CRR_RD3_SHIFT (24u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ostm_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ostm_iobitmask.h new file mode 100644 index 0000000..31191e7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ostm_iobitmask.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef OSTM_IOBITMASK_H +#define OSTM_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define OSTM_OSTMnCMP_OSTMnCMP (0xFFFFFFFFu) +#define OSTM_OSTMnCMP_OSTMnCMP_SHIFT (0u) +#define OSTM_OSTMnCNT_OSTMnCNT (0xFFFFFFFFu) +#define OSTM_OSTMnCNT_OSTMnCNT_SHIFT (0u) +#define OSTM_OSTMnTE_OSTMnTE (0x01u) +#define OSTM_OSTMnTE_OSTMnTE_SHIFT (0u) +#define OSTM_OSTMnTS_OSTMnTS (0x01u) +#define OSTM_OSTMnTS_OSTMnTS_SHIFT (0u) +#define OSTM_OSTMnTT_OSTMnTT (0x01u) +#define OSTM_OSTMnTT_OSTMnTT_SHIFT (0u) +#define OSTM_OSTMnCTL_OSTMnMD0 (0x01u) +#define OSTM_OSTMnCTL_OSTMnMD0_SHIFT (0u) +#define OSTM_OSTMnCTL_OSTMnMD1 (0x02u) +#define OSTM_OSTMnCTL_OSTMnMD1_SHIFT (1u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pl310_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pl310_iobitmask.h new file mode 100644 index 0000000..5e64eb1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pl310_iobitmask.h @@ -0,0 +1,318 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef PL310_IOBITMASK_H +#define PL310_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define PL310_REG0_CACHE_ID_RTLrelease (0x0000003Fu) +#define PL310_REG0_CACHE_ID_RTLrelease_SHIFT (0u) +#define PL310_REG0_CACHE_ID_Partnumber (0x000003C0u) +#define PL310_REG0_CACHE_ID_Partnumber_SHIFT (6u) +#define PL310_REG0_CACHE_ID_CACHEID (0x0000FC00u) +#define PL310_REG0_CACHE_ID_CACHEID_SHIFT (10u) +#define PL310_REG0_CACHE_ID_Implementer (0xFF000000u) +#define PL310_REG0_CACHE_ID_Implementer_SHIFT (24u) +#define PL310_REG0_CACHE_TYPE_L2cachelinelength1 (0x00000003u) +#define PL310_REG0_CACHE_TYPE_L2cachelinelength1_SHIFT (0u) +#define PL310_REG0_CACHE_TYPE_L2associativity1 (0x00000040u) +#define PL310_REG0_CACHE_TYPE_L2associativity1_SHIFT (6u) +#define PL310_REG0_CACHE_TYPE_Isize (0x00000F80u) +#define PL310_REG0_CACHE_TYPE_Isize_SHIFT (7u) +#define PL310_REG0_CACHE_TYPE_L2cachelinelength0 (0x00003000u) +#define PL310_REG0_CACHE_TYPE_L2cachelinelength0_SHIFT (12u) +#define PL310_REG0_CACHE_TYPE_L2associativity0 (0x00040000u) +#define PL310_REG0_CACHE_TYPE_L2associativity0_SHIFT (18u) +#define PL310_REG0_CACHE_TYPE_Dsize (0x00F80000u) +#define PL310_REG0_CACHE_TYPE_Dsize_SHIFT (19u) +#define PL310_REG0_CACHE_TYPE_H (0x01000000u) +#define PL310_REG0_CACHE_TYPE_H_SHIFT (24u) +#define PL310_REG0_CACHE_TYPE_ctype (0x1E000000u) +#define PL310_REG0_CACHE_TYPE_ctype_SHIFT (25u) +#define PL310_REG0_CACHE_TYPE_Databanking (0x80000000u) +#define PL310_REG0_CACHE_TYPE_Databanking_SHIFT (31u) +#define PL310_REG1_CONTROL_L2Cacheenable (0x00000001u) +#define PL310_REG1_CONTROL_L2Cacheenable_SHIFT (0u) +#define PL310_REG1_AUX_CONTROL_FullLineofZeroEnable (0x00000001u) +#define PL310_REG1_AUX_CONTROL_FullLineofZeroEnable_SHIFT (0u) +#define PL310_REG1_AUX_CONTROL_HighPriorityforSOandDevReadsEnable (0x00000400u) +#define PL310_REG1_AUX_CONTROL_HighPriorityforSOandDevReadsEnable_SHIFT (10u) +#define PL310_REG1_AUX_CONTROL_StorebufferdevicelimitationEnable (0x00000800u) +#define PL310_REG1_AUX_CONTROL_StorebufferdevicelimitationEnable_SHIFT (11u) +#define PL310_REG1_AUX_CONTROL_Exclusivecacheconfiguration (0x00001000u) +#define PL310_REG1_AUX_CONTROL_Exclusivecacheconfiguration_SHIFT (12u) +#define PL310_REG1_AUX_CONTROL_SharedAttributeInvalidateEnable (0x00002000u) +#define PL310_REG1_AUX_CONTROL_SharedAttributeInvalidateEnable_SHIFT (13u) +#define PL310_REG1_AUX_CONTROL_Associativity (0x00010000u) +#define PL310_REG1_AUX_CONTROL_Associativity_SHIFT (16u) +#define PL310_REG1_AUX_CONTROL_Waysize (0x000E0000u) +#define PL310_REG1_AUX_CONTROL_Waysize_SHIFT (17u) +#define PL310_REG1_AUX_CONTROL_Eventmonitorbusenable (0x00100000u) +#define PL310_REG1_AUX_CONTROL_Eventmonitorbusenable_SHIFT (20u) +#define PL310_REG1_AUX_CONTROL_Parityenable (0x00200000u) +#define PL310_REG1_AUX_CONTROL_Parityenable_SHIFT (21u) +#define PL310_REG1_AUX_CONTROL_Sharedattributeoverrideenable (0x00400000u) +#define PL310_REG1_AUX_CONTROL_Sharedattributeoverrideenable_SHIFT (22u) +#define PL310_REG1_AUX_CONTROL_Forcewriteallocate (0x01800000u) +#define PL310_REG1_AUX_CONTROL_Forcewriteallocate_SHIFT (23u) +#define PL310_REG1_AUX_CONTROL_Cachereplacementpolicy (0x02000000u) +#define PL310_REG1_AUX_CONTROL_Cachereplacementpolicy_SHIFT (25u) +#define PL310_REG1_AUX_CONTROL_Nonsecurelockdownenable (0x04000000u) +#define PL310_REG1_AUX_CONTROL_Nonsecurelockdownenable_SHIFT (26u) +#define PL310_REG1_AUX_CONTROL_Nonsecureinterruptaccesscontrol (0x08000000u) +#define PL310_REG1_AUX_CONTROL_Nonsecureinterruptaccesscontrol_SHIFT (27u) +#define PL310_REG1_AUX_CONTROL_Dataprefetchenable (0x10000000u) +#define PL310_REG1_AUX_CONTROL_Dataprefetchenable_SHIFT (28u) +#define PL310_REG1_AUX_CONTROL_Instructionprefetchenable (0x20000000u) +#define PL310_REG1_AUX_CONTROL_Instructionprefetchenable_SHIFT (29u) +#define PL310_REG1_AUX_CONTROL_EarlyBRESPenable (0x40000000u) +#define PL310_REG1_AUX_CONTROL_EarlyBRESPenable_SHIFT (30u) +#define PL310_REG1_TAG_RAM_CONTROL_RAMsetuplatency (0x00000007u) +#define PL310_REG1_TAG_RAM_CONTROL_RAMsetuplatency_SHIFT (0u) +#define PL310_REG1_TAG_RAM_CONTROL_RAMreadaccesslatency (0x00000070u) +#define PL310_REG1_TAG_RAM_CONTROL_RAMreadaccesslatency_SHIFT (4u) +#define PL310_REG1_TAG_RAM_CONTROL_RAMwriteaccesslatency (0x00000700u) +#define PL310_REG1_TAG_RAM_CONTROL_RAMwriteaccesslatency_SHIFT (8u) +#define PL310_REG1_DATA_RAM_CONTROL_RAMsetuplatency (0x00000007u) +#define PL310_REG1_DATA_RAM_CONTROL_RAMsetuplatency_SHIFT (0u) +#define PL310_REG1_DATA_RAM_CONTROL_RAMreadaccesslatency (0x00000070u) +#define PL310_REG1_DATA_RAM_CONTROL_RAMreadaccesslatency_SHIFT (4u) +#define PL310_REG1_DATA_RAM_CONTROL_RAMwriteaccesslatency (0x00000700u) +#define PL310_REG1_DATA_RAM_CONTROL_RAMwriteaccesslatency_SHIFT (8u) +#define PL310_REG2_EV_COUNTER_CTRL_Eventcounterenable (0x00000001u) +#define PL310_REG2_EV_COUNTER_CTRL_Eventcounterenable_SHIFT (0u) +#define PL310_REG2_EV_COUNTER_CTRL_Counterreset (0x00000006u) +#define PL310_REG2_EV_COUNTER_CTRL_Counterreset_SHIFT (1u) +#define PL310_REG2_EV_COUNTER1_CFG_Eventcounterinterruptgeneration (0x00000003u) +#define PL310_REG2_EV_COUNTER1_CFG_Eventcounterinterruptgeneration_SHIFT (0u) +#define PL310_REG2_EV_COUNTER1_CFG_Countereventsource (0x0000003Cu) +#define PL310_REG2_EV_COUNTER1_CFG_Countereventsource_SHIFT (2u) +#define PL310_REG2_EV_COUNTER0_CFG_Eventcounterinterruptgeneration (0x00000003u) +#define PL310_REG2_EV_COUNTER0_CFG_Eventcounterinterruptgeneration_SHIFT (0u) +#define PL310_REG2_EV_COUNTER0_CFG_Countereventsource (0x0000003Cu) +#define PL310_REG2_EV_COUNTER0_CFG_Countereventsource_SHIFT (2u) +#define PL310_REG2_EV_COUNTER1_Countervalue (0xFFFFFFFFu) +#define PL310_REG2_EV_COUNTER1_Countervalue_SHIFT (0u) +#define PL310_REG2_EV_COUNTER0_Countervalue (0xFFFFFFFFu) +#define PL310_REG2_EV_COUNTER0_Countervalue_SHIFT (0u) +#define PL310_REG2_INT_MASK_ECNTR (0x00000001u) +#define PL310_REG2_INT_MASK_ECNTR_SHIFT (0u) +#define PL310_REG2_INT_MASK_PARRT (0x00000002u) +#define PL310_REG2_INT_MASK_PARRT_SHIFT (1u) +#define PL310_REG2_INT_MASK_PARRD (0x00000004u) +#define PL310_REG2_INT_MASK_PARRD_SHIFT (2u) +#define PL310_REG2_INT_MASK_ERRWT (0x00000008u) +#define PL310_REG2_INT_MASK_ERRWT_SHIFT (3u) +#define PL310_REG2_INT_MASK_ERRWD (0x00000010u) +#define PL310_REG2_INT_MASK_ERRWD_SHIFT (4u) +#define PL310_REG2_INT_MASK_ERRRT (0x00000020u) +#define PL310_REG2_INT_MASK_ERRRT_SHIFT (5u) +#define PL310_REG2_INT_MASK_ERRRD (0x00000040u) +#define PL310_REG2_INT_MASK_ERRRD_SHIFT (6u) +#define PL310_REG2_INT_MASK_SLVERR (0x00000080u) +#define PL310_REG2_INT_MASK_SLVERR_SHIFT (7u) +#define PL310_REG2_INT_MASK_DECERR (0x00000100u) +#define PL310_REG2_INT_MASK_DECERR_SHIFT (8u) +#define PL310_REG2_INT_MASK_STATUS_ECNTR (0x00000001u) +#define PL310_REG2_INT_MASK_STATUS_ECNTR_SHIFT (0u) +#define PL310_REG2_INT_MASK_STATUS_PARRT (0x00000002u) +#define PL310_REG2_INT_MASK_STATUS_PARRT_SHIFT (1u) +#define PL310_REG2_INT_MASK_STATUS_PARRD (0x00000004u) +#define PL310_REG2_INT_MASK_STATUS_PARRD_SHIFT (2u) +#define PL310_REG2_INT_MASK_STATUS_ERRWT (0x00000008u) +#define PL310_REG2_INT_MASK_STATUS_ERRWT_SHIFT (3u) +#define PL310_REG2_INT_MASK_STATUS_ERRWD (0x00000010u) +#define PL310_REG2_INT_MASK_STATUS_ERRWD_SHIFT (4u) +#define PL310_REG2_INT_MASK_STATUS_ERRRT (0x00000020u) +#define PL310_REG2_INT_MASK_STATUS_ERRRT_SHIFT (5u) +#define PL310_REG2_INT_MASK_STATUS_ERRRD (0x00000040u) +#define PL310_REG2_INT_MASK_STATUS_ERRRD_SHIFT (6u) +#define PL310_REG2_INT_MASK_STATUS_SLVERR (0x00000080u) +#define PL310_REG2_INT_MASK_STATUS_SLVERR_SHIFT (7u) +#define PL310_REG2_INT_MASK_STATUS_DECERR (0x00000100u) +#define PL310_REG2_INT_MASK_STATUS_DECERR_SHIFT (8u) +#define PL310_REG2_INT_RAW_STATUS_ECNTR (0x00000001u) +#define PL310_REG2_INT_RAW_STATUS_ECNTR_SHIFT (0u) +#define PL310_REG2_INT_RAW_STATUS_PARRT (0x00000002u) +#define PL310_REG2_INT_RAW_STATUS_PARRT_SHIFT (1u) +#define PL310_REG2_INT_RAW_STATUS_PARRD (0x00000004u) +#define PL310_REG2_INT_RAW_STATUS_PARRD_SHIFT (2u) +#define PL310_REG2_INT_RAW_STATUS_ERRWT (0x00000008u) +#define PL310_REG2_INT_RAW_STATUS_ERRWT_SHIFT (3u) +#define PL310_REG2_INT_RAW_STATUS_ERRWD (0x00000010u) +#define PL310_REG2_INT_RAW_STATUS_ERRWD_SHIFT (4u) +#define PL310_REG2_INT_RAW_STATUS_ERRRT (0x00000020u) +#define PL310_REG2_INT_RAW_STATUS_ERRRT_SHIFT (5u) +#define PL310_REG2_INT_RAW_STATUS_ERRRD (0x00000040u) +#define PL310_REG2_INT_RAW_STATUS_ERRRD_SHIFT (6u) +#define PL310_REG2_INT_RAW_STATUS_SLVERR (0x00000080u) +#define PL310_REG2_INT_RAW_STATUS_SLVERR_SHIFT (7u) +#define PL310_REG2_INT_RAW_STATUS_DECERR (0x00000100u) +#define PL310_REG2_INT_RAW_STATUS_DECERR_SHIFT (8u) +#define PL310_REG2_INT_CLEAR_ECNTR (0x00000001u) +#define PL310_REG2_INT_CLEAR_ECNTR_SHIFT (0u) +#define PL310_REG2_INT_CLEAR_PARRT (0x00000002u) +#define PL310_REG2_INT_CLEAR_PARRT_SHIFT (1u) +#define PL310_REG2_INT_CLEAR_PARRD (0x00000004u) +#define PL310_REG2_INT_CLEAR_PARRD_SHIFT (2u) +#define PL310_REG2_INT_CLEAR_ERRWT (0x00000008u) +#define PL310_REG2_INT_CLEAR_ERRWT_SHIFT (3u) +#define PL310_REG2_INT_CLEAR_ERRWD (0x00000010u) +#define PL310_REG2_INT_CLEAR_ERRWD_SHIFT (4u) +#define PL310_REG2_INT_CLEAR_ERRRT (0x00000020u) +#define PL310_REG2_INT_CLEAR_ERRRT_SHIFT (5u) +#define PL310_REG2_INT_CLEAR_ERRRD (0x00000040u) +#define PL310_REG2_INT_CLEAR_ERRRD_SHIFT (6u) +#define PL310_REG2_INT_CLEAR_SLVERR (0x00000080u) +#define PL310_REG2_INT_CLEAR_SLVERR_SHIFT (7u) +#define PL310_REG2_INT_CLEAR_DECERR (0x00000100u) +#define PL310_REG2_INT_CLEAR_DECERR_SHIFT (8u) +#define PL310_REG7_CACHE_SYNC_C (0x00000001u) +#define PL310_REG7_CACHE_SYNC_C_SHIFT (0u) +#define PL310_REG7_INV_PA_C (0x00000001u) +#define PL310_REG7_INV_PA_C_SHIFT (0u) +#define PL310_REG7_INV_PA_INDEX (0x00003FE0u) +#define PL310_REG7_INV_PA_INDEX_SHIFT (5u) +#define PL310_REG7_INV_PA_TAG (0xFFFFC000u) +#define PL310_REG7_INV_PA_TAG_SHIFT (14u) +#define PL310_REG7_INV_WAY_Way_bits (0x000000FFu) +#define PL310_REG7_INV_WAY_Way_bits_SHIFT (0u) +#define PL310_REG7_CLEAN_PA_C (0x00000001u) +#define PL310_REG7_CLEAN_PA_C_SHIFT (0u) +#define PL310_REG7_CLEAN_PA_INDEX (0x00003FE0u) +#define PL310_REG7_CLEAN_PA_INDEX_SHIFT (5u) +#define PL310_REG7_CLEAN_PA_TAG (0xFFFFC000u) +#define PL310_REG7_CLEAN_PA_TAG_SHIFT (14u) +#define PL310_REG7_CLEAN_INDEX_C (0x00000001u) +#define PL310_REG7_CLEAN_INDEX_C_SHIFT (0u) +#define PL310_REG7_CLEAN_INDEX_INDEX (0x00003FE0u) +#define PL310_REG7_CLEAN_INDEX_INDEX_SHIFT (5u) +#define PL310_REG7_CLEAN_INDEX_Way (0x70000000u) +#define PL310_REG7_CLEAN_INDEX_Way_SHIFT (28u) +#define PL310_REG7_CLEAN_WAY_Way_bits (0x000000FFu) +#define PL310_REG7_CLEAN_WAY_Way_bits_SHIFT (0u) +#define PL310_REG7_CLEAN_INV_PA_C (0x00000001u) +#define PL310_REG7_CLEAN_INV_PA_C_SHIFT (0u) +#define PL310_REG7_CLEAN_INV_PA_INDEX (0x00003FE0u) +#define PL310_REG7_CLEAN_INV_PA_INDEX_SHIFT (5u) +#define PL310_REG7_CLEAN_INV_PA_TAG (0xFFFFC000u) +#define PL310_REG7_CLEAN_INV_PA_TAG_SHIFT (14u) +#define PL310_REG7_CLEAN_INV_INDEX_C (0x00000001u) +#define PL310_REG7_CLEAN_INV_INDEX_C_SHIFT (0u) +#define PL310_REG7_CLEAN_INV_INDEX_INDEX (0x00003FE0u) +#define PL310_REG7_CLEAN_INV_INDEX_INDEX_SHIFT (5u) +#define PL310_REG7_CLEAN_INV_INDEX_Way (0x70000000u) +#define PL310_REG7_CLEAN_INV_INDEX_Way_SHIFT (28u) +#define PL310_REG7_CLEAN_INV_WAY_Way_bits (0x000000FFu) +#define PL310_REG7_CLEAN_INV_WAY_Way_bits_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN0_DATALOCK000 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN0_DATALOCK000_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN0_INSTRLOCK000 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN0_INSTRLOCK000_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN1_DATALOCK001 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN1_DATALOCK001_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN1_INSTRLOCK001 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN1_INSTRLOCK001_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN2_DATALOCK002 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN2_DATALOCK002_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN2_INSTRLOCK002 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN2_INSTRLOCK002_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN3_DATALOCK003 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN3_DATALOCK003_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN3_INSTRLOCK003 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN3_INSTRLOCK003_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN4_DATALOCK004 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN4_DATALOCK004_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN4_INSTRLOCK004 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN4_INSTRLOCK004_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN5_DATALOCK005 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN5_DATALOCK005_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN5_INSTRLOCK005 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN5_INSTRLOCK005_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN6_DATALOCK006 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN6_DATALOCK006_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN6_INSTRLOCK006 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN6_INSTRLOCK006_SHIFT (0u) +#define PL310_REG9_D_LOCKDOWN7_DATALOCK007 (0x000000FFu) +#define PL310_REG9_D_LOCKDOWN7_DATALOCK007_SHIFT (0u) +#define PL310_REG9_I_LOCKDOWN7_INSTRLOCK007 (0x000000FFu) +#define PL310_REG9_I_LOCKDOWN7_INSTRLOCK007_SHIFT (0u) +#define PL310_REG9_LOCK_LINE_EN_lockdown_by_line_enable (0x00000001u) +#define PL310_REG9_LOCK_LINE_EN_lockdown_by_line_enable_SHIFT (0u) +#define PL310_REG9_UNLOCK_WAY_unlock_all_lines_by_way_operation (0x000000FFu) +#define PL310_REG9_UNLOCK_WAY_unlock_all_lines_by_way_operation_SHIFT (0u) +#define PL310_REG12_ADDR_FILTERING_START_address_filtering_enable (0x00000001u) +#define PL310_REG12_ADDR_FILTERING_START_address_filtering_enable_SHIFT (0u) +#define PL310_REG12_ADDR_FILTERING_START_address_filtering_start (0xFFF00000u) +#define PL310_REG12_ADDR_FILTERING_START_address_filtering_start_SHIFT (20u) +#define PL310_REG12_ADDR_FILTERING_END_address_filtering_end (0xFFF00000u) +#define PL310_REG12_ADDR_FILTERING_END_address_filtering_end_SHIFT (20u) +#define PL310_REG15_DEBUG_CTRL_DCL (0x00000001u) +#define PL310_REG15_DEBUG_CTRL_DCL_SHIFT (0u) +#define PL310_REG15_DEBUG_CTRL_DWB (0x00000002u) +#define PL310_REG15_DEBUG_CTRL_DWB_SHIFT (1u) +#define PL310_REG15_DEBUG_CTRL_SPNIDEN (0x00000004u) +#define PL310_REG15_DEBUG_CTRL_SPNIDEN_SHIFT (2u) +#define PL310_REG15_PREFETCH_CTRL_Prefetchoffset (0x0000001Fu) +#define PL310_REG15_PREFETCH_CTRL_Prefetchoffset_SHIFT (0u) +#define PL310_REG15_PREFETCH_CTRL_NotsameIDonexclusivesequenceenable (0x00200000u) +#define PL310_REG15_PREFETCH_CTRL_NotsameIDonexclusivesequenceenable_SHIFT (21u) +#define PL310_REG15_PREFETCH_CTRL_IncrdoubleLinefillenable (0x00800000u) +#define PL310_REG15_PREFETCH_CTRL_IncrdoubleLinefillenable_SHIFT (23u) +#define PL310_REG15_PREFETCH_CTRL_Prefetchdropenable (0x01000000u) +#define PL310_REG15_PREFETCH_CTRL_Prefetchdropenable_SHIFT (24u) +#define PL310_REG15_PREFETCH_CTRL_DoublelinefillonWRAPreaddisable (0x08000000u) +#define PL310_REG15_PREFETCH_CTRL_DoublelinefillonWRAPreaddisable_SHIFT (27u) +#define PL310_REG15_PREFETCH_CTRL_Dataprefetchenable (0x10000000u) +#define PL310_REG15_PREFETCH_CTRL_Dataprefetchenable_SHIFT (28u) +#define PL310_REG15_PREFETCH_CTRL_Instructionprefetchenable (0x20000000u) +#define PL310_REG15_PREFETCH_CTRL_Instructionprefetchenable_SHIFT (29u) +#define PL310_REG15_PREFETCH_CTRL_Doublelinefillenable (0x40000000u) +#define PL310_REG15_PREFETCH_CTRL_Doublelinefillenable_SHIFT (30u) +#define PL310_REG15_POWER_CTRL_standby_mode_en (0x00000001u) +#define PL310_REG15_POWER_CTRL_standby_mode_en_SHIFT (0u) +#define PL310_REG15_POWER_CTRL_dynamic_clk_gating_en (0x00000002u) +#define PL310_REG15_POWER_CTRL_dynamic_clk_gating_en_SHIFT (1u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pmg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pmg_iobitmask.h new file mode 100644 index 0000000..5c5c2fb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/pmg_iobitmask.h @@ -0,0 +1,174 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef PMG_IOBITMASK_H +#define PMG_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define PMG_RRAMKP_RRAMKP0 (0x01u) +#define PMG_RRAMKP_RRAMKP0_SHIFT (0u) +#define PMG_RRAMKP_RRAMKP1 (0x02u) +#define PMG_RRAMKP_RRAMKP1_SHIFT (1u) +#define PMG_RRAMKP_RRAMKP2 (0x04u) +#define PMG_RRAMKP_RRAMKP2_SHIFT (2u) +#define PMG_RRAMKP_RRAMKP3 (0x08u) +#define PMG_RRAMKP_RRAMKP3_SHIFT (3u) +#define PMG_DSCTR_RAMBOOT (0x40u) +#define PMG_DSCTR_RAMBOOT_SHIFT (6u) +#define PMG_DSCTR_EBUSKEEPE (0x80u) +#define PMG_DSCTR_EBUSKEEPE_SHIFT (7u) +#define PMG_DSSSR_P3_1 (0x0001u) +#define PMG_DSSSR_P3_1_SHIFT (0u) +#define PMG_DSSSR_P3_3 (0x0002u) +#define PMG_DSSSR_P3_3_SHIFT (1u) +#define PMG_DSSSR_P6_2 (0x0004u) +#define PMG_DSSSR_P6_2_SHIFT (2u) +#define PMG_DSSSR_PE_1 (0x0008u) +#define PMG_DSSSR_PE_1_SHIFT (3u) +#define PMG_DSSSR_PH_1 (0x0010u) +#define PMG_DSSSR_PH_1_SHIFT (4u) +#define PMG_DSSSR_PG_2 (0x0020u) +#define PMG_DSSSR_PG_2_SHIFT (5u) +#define PMG_DSSSR_RTCAR0 (0x0040u) +#define PMG_DSSSR_RTCAR0_SHIFT (6u) +#define PMG_DSSSR_RTCAR1 (0x0080u) +#define PMG_DSSSR_RTCAR1_SHIFT (7u) +#define PMG_DSSSR_NMI (0x0100u) +#define PMG_DSSSR_NMI_SHIFT (8u) +#define PMG_DSSSR_PG_6 (0x0200u) +#define PMG_DSSSR_PG_6_SHIFT (9u) +#define PMG_DSSSR_PH_0 (0x0400u) +#define PMG_DSSSR_PH_0_SHIFT (10u) +#define PMG_DSSSR_PJ_1 (0x0800u) +#define PMG_DSSSR_PJ_1_SHIFT (11u) +#define PMG_DSSSR_PJ_5 (0x1000u) +#define PMG_DSSSR_PJ_5_SHIFT (12u) +#define PMG_DSSSR_PK_2 (0x2000u) +#define PMG_DSSSR_PK_2_SHIFT (13u) +#define PMG_DSSSR_PK_4 (0x4000u) +#define PMG_DSSSR_PK_4_SHIFT (14u) +#define PMG_DSESR_P3_1E (0x0001u) +#define PMG_DSESR_P3_1E_SHIFT (0u) +#define PMG_DSESR_P3_3E (0x0002u) +#define PMG_DSESR_P3_3E_SHIFT (1u) +#define PMG_DSESR_P6_2E (0x0004u) +#define PMG_DSESR_P6_2E_SHIFT (2u) +#define PMG_DSESR_PE_1E (0x0008u) +#define PMG_DSESR_PE_1E_SHIFT (3u) +#define PMG_DSESR_PH_1E (0x0010u) +#define PMG_DSESR_PH_1E_SHIFT (4u) +#define PMG_DSESR_PG_2E (0x0020u) +#define PMG_DSESR_PG_2E_SHIFT (5u) +#define PMG_DSESR_NMIE (0x0100u) +#define PMG_DSESR_NMIE_SHIFT (8u) +#define PMG_DSESR_PG_6E (0x0200u) +#define PMG_DSESR_PG_6E_SHIFT (9u) +#define PMG_DSESR_PH_0E (0x0400u) +#define PMG_DSESR_PH_0E_SHIFT (10u) +#define PMG_DSESR_PJ_1E (0x0800u) +#define PMG_DSESR_PJ_1E_SHIFT (11u) +#define PMG_DSESR_PJ_5E (0x1000u) +#define PMG_DSESR_PJ_5E_SHIFT (12u) +#define PMG_DSESR_PK_2E (0x2000u) +#define PMG_DSESR_PK_2E_SHIFT (13u) +#define PMG_DSESR_PK_4E (0x4000u) +#define PMG_DSESR_PK_4E_SHIFT (14u) +#define PMG_DSFR_P3_1F (0x0001u) +#define PMG_DSFR_P3_1F_SHIFT (0u) +#define PMG_DSFR_P3_3F (0x0002u) +#define PMG_DSFR_P3_3F_SHIFT (1u) +#define PMG_DSFR_P6_2F (0x0004u) +#define PMG_DSFR_P6_2F_SHIFT (2u) +#define PMG_DSFR_PE_1F (0x0008u) +#define PMG_DSFR_PE_1F_SHIFT (3u) +#define PMG_DSFR_PH_1F (0x0010u) +#define PMG_DSFR_PH_1F_SHIFT (4u) +#define PMG_DSFR_PG_2F (0x0020u) +#define PMG_DSFR_PG_2F_SHIFT (5u) +#define PMG_DSFR_RTCARF0 (0x0040u) +#define PMG_DSFR_RTCARF0_SHIFT (6u) +#define PMG_DSFR_RTCARF1 (0x0080u) +#define PMG_DSFR_RTCARF1_SHIFT (7u) +#define PMG_DSFR_NMIF (0x0100u) +#define PMG_DSFR_NMIF_SHIFT (8u) +#define PMG_DSFR_PG_6F (0x0200u) +#define PMG_DSFR_PG_6F_SHIFT (9u) +#define PMG_DSFR_PH_0F (0x0400u) +#define PMG_DSFR_PH_0F_SHIFT (10u) +#define PMG_DSFR_PJ_1F (0x0800u) +#define PMG_DSFR_PJ_1F_SHIFT (11u) +#define PMG_DSFR_PJ_5F (0x1000u) +#define PMG_DSFR_PJ_5F_SHIFT (12u) +#define PMG_DSFR_PK_2F (0x2000u) +#define PMG_DSFR_PK_2F_SHIFT (13u) +#define PMG_DSFR_PK_4F (0x4000u) +#define PMG_DSFR_PK_4F_SHIFT (14u) +#define PMG_DSFR_IOKEEP (0x8000u) +#define PMG_DSFR_IOKEEP_SHIFT (15u) +#define PMG_DSCNT_CNTD (0x00FFu) +#define PMG_DSCNT_CNTD_SHIFT (0u) +#define PMG_XTALCTR_GAIN0 (0x01u) +#define PMG_XTALCTR_GAIN0_SHIFT (0u) +#define PMG_USBDSSSR_USBDSCE0 (0x01u) +#define PMG_USBDSSSR_USBDSCE0_SHIFT (0u) +#define PMG_USBDSSSR_USBDSCE1 (0x02u) +#define PMG_USBDSSSR_USBDSCE1_SHIFT (1u) +#define PMG_USBDSSSR_USBDSCE2 (0x04u) +#define PMG_USBDSSSR_USBDSCE2_SHIFT (2u) +#define PMG_USBDSSSR_USBDSCE3 (0x08u) +#define PMG_USBDSSSR_USBDSCE3_SHIFT (3u) +#define PMG_USBDSFR_USBDSF0 (0x01u) +#define PMG_USBDSFR_USBDSF0_SHIFT (0u) +#define PMG_USBDSFR_USBDSF1 (0x02u) +#define PMG_USBDSFR_USBDSF1_SHIFT (1u) +#define PMG_USBDSFR_USBDSF2 (0x04u) +#define PMG_USBDSFR_USBDSF2_SHIFT (2u) +#define PMG_USBDSFR_USBDSF3 (0x08u) +#define PMG_USBDSFR_USBDSF3_SHIFT (3u) +#define PMG_RTCXTALSEL_RTC0XT (0x0001u) +#define PMG_RTCXTALSEL_RTC0XT_SHIFT (0u) +#define PMG_RTCXTALSEL_RTC1XT (0x0002u) +#define PMG_RTCXTALSEL_RTC1XT_SHIFT (1u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poe3_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poe3_iobitmask.h new file mode 100644 index 0000000..79eb025 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poe3_iobitmask.h @@ -0,0 +1,142 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef POE3_IOBITMASK_H +#define POE3_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define POE3_ICSR1_POE0M (0x0003u) +#define POE3_ICSR1_POE0M_SHIFT (0u) +#define POE3_ICSR1_PIE1 (0x0100u) +#define POE3_ICSR1_PIE1_SHIFT (8u) +#define POE3_ICSR1_POE0F (0x1000u) +#define POE3_ICSR1_POE0F_SHIFT (12u) +#define POE3_OCSR1_OIE1 (0x0100u) +#define POE3_OCSR1_OIE1_SHIFT (8u) +#define POE3_OCSR1_OCE1 (0x0200u) +#define POE3_OCSR1_OCE1_SHIFT (9u) +#define POE3_OCSR1_OSF1 (0x8000u) +#define POE3_OCSR1_OSF1_SHIFT (15u) +#define POE3_ICSR2_POE4M (0x0003u) +#define POE3_ICSR2_POE4M_SHIFT (0u) +#define POE3_ICSR2_PIE2 (0x0100u) +#define POE3_ICSR2_PIE2_SHIFT (8u) +#define POE3_ICSR2_POE4F (0x1000u) +#define POE3_ICSR2_POE4F_SHIFT (12u) +#define POE3_OCSR2_OIE2 (0x0100u) +#define POE3_OCSR2_OIE2_SHIFT (8u) +#define POE3_OCSR2_OCE2 (0x0200u) +#define POE3_OCSR2_OCE2_SHIFT (9u) +#define POE3_OCSR2_OSF2 (0x8000u) +#define POE3_OCSR2_OSF2_SHIFT (15u) +#define POE3_ICSR3_POE8M (0x0003u) +#define POE3_ICSR3_POE8M_SHIFT (0u) +#define POE3_ICSR3_PIE3 (0x0100u) +#define POE3_ICSR3_PIE3_SHIFT (8u) +#define POE3_ICSR3_POE8E (0x0200u) +#define POE3_ICSR3_POE8E_SHIFT (9u) +#define POE3_ICSR3_POE8F (0x1000u) +#define POE3_ICSR3_POE8F_SHIFT (12u) +#define POE3_SPOER_MTUCH34HIZ (0x01u) +#define POE3_SPOER_MTUCH34HIZ_SHIFT (0u) +#define POE3_SPOER_MTUCH67HIZ (0x02u) +#define POE3_SPOER_MTUCH67HIZ_SHIFT (1u) +#define POE3_SPOER_MTUCH0HIZ (0x04u) +#define POE3_SPOER_MTUCH0HIZ_SHIFT (2u) +#define POE3_POECR1_MTU0AZE (0x01u) +#define POE3_POECR1_MTU0AZE_SHIFT (0u) +#define POE3_POECR1_MTU0BZE (0x02u) +#define POE3_POECR1_MTU0BZE_SHIFT (1u) +#define POE3_POECR1_MTU0CZE (0x04u) +#define POE3_POECR1_MTU0CZE_SHIFT (2u) +#define POE3_POECR1_MTU0DZE (0x08u) +#define POE3_POECR1_MTU0DZE_SHIFT (3u) +#define POE3_POECR2_MTU7BDZE (0x0001u) +#define POE3_POECR2_MTU7BDZE_SHIFT (0u) +#define POE3_POECR2_MTU7ACZE (0x0002u) +#define POE3_POECR2_MTU7ACZE_SHIFT (1u) +#define POE3_POECR2_MTU6BDZE (0x0004u) +#define POE3_POECR2_MTU6BDZE_SHIFT (2u) +#define POE3_POECR2_MTU4BDZE (0x0100u) +#define POE3_POECR2_MTU4BDZE_SHIFT (8u) +#define POE3_POECR2_MTU4ACZE (0x0200u) +#define POE3_POECR2_MTU4ACZE_SHIFT (9u) +#define POE3_POECR2_MTU3BDZE (0x0400u) +#define POE3_POECR2_MTU3BDZE_SHIFT (10u) +#define POE3_POECR4_IC2ADDMT34ZE (0x0004u) +#define POE3_POECR4_IC2ADDMT34ZE_SHIFT (2u) +#define POE3_POECR4_IC3ADDMT34ZE (0x0008u) +#define POE3_POECR4_IC3ADDMT34ZE_SHIFT (3u) +#define POE3_POECR4_IC4ADDMT34ZE (0x0010u) +#define POE3_POECR4_IC4ADDMT34ZE_SHIFT (4u) +#define POE3_POECR4_IC1ADDMT67ZE (0x0200u) +#define POE3_POECR4_IC1ADDMT67ZE_SHIFT (9u) +#define POE3_POECR4_IC3ADDMT67ZE (0x0800u) +#define POE3_POECR4_IC3ADDMT67ZE_SHIFT (11u) +#define POE3_POECR4_IC4ADDMT67ZE (0x1000u) +#define POE3_POECR4_IC4ADDMT67ZE_SHIFT (12u) +#define POE3_POECR5_IC1ADDMT0ZE (0x0002u) +#define POE3_POECR5_IC1ADDMT0ZE_SHIFT (1u) +#define POE3_POECR5_IC2ADDMT0ZE (0x0004u) +#define POE3_POECR5_IC2ADDMT0ZE_SHIFT (2u) +#define POE3_POECR5_IC4ADDMT0ZE (0x0010u) +#define POE3_POECR5_IC4ADDMT0ZE_SHIFT (4u) +#define POE3_ICSR4_POE10M (0x0003u) +#define POE3_ICSR4_POE10M_SHIFT (0u) +#define POE3_ICSR4_PIE4 (0x0100u) +#define POE3_ICSR4_PIE4_SHIFT (8u) +#define POE3_ICSR4_POE10E (0x0200u) +#define POE3_ICSR4_POE10E_SHIFT (9u) +#define POE3_ICSR4_POE10F (0x1000u) +#define POE3_ICSR4_POE10F_SHIFT (12u) +#define POE3_M0SELR1_M0ASEL (0x0Fu) +#define POE3_M0SELR1_M0ASEL_SHIFT (0u) +#define POE3_M0SELR1_M0BSEL (0xF0u) +#define POE3_M0SELR1_M0BSEL_SHIFT (4u) +#define POE3_M0SELR2_M0CSEL (0x0Fu) +#define POE3_M0SELR2_M0CSEL_SHIFT (0u) +#define POE3_M0SELR2_M0DSEL (0xF0u) +#define POE3_M0SELR2_M0DSEL_SHIFT (4u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poeg_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poeg_iobitmask.h new file mode 100644 index 0000000..f0bf63a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/poeg_iobitmask.h @@ -0,0 +1,122 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef POEG_IOBITMASK_H +#define POEG_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define POEG_POEGGA_PIDF (0x00000001u) +#define POEG_POEGGA_PIDF_SHIFT (0u) +#define POEG_POEGGA_IOCF (0x00000002u) +#define POEG_POEGGA_IOCF_SHIFT (1u) +#define POEG_POEGGA_SSF (0x00000008u) +#define POEG_POEGGA_SSF_SHIFT (3u) +#define POEG_POEGGA_PIDE (0x00000010u) +#define POEG_POEGGA_PIDE_SHIFT (4u) +#define POEG_POEGGA_IOCE (0x00000020u) +#define POEG_POEGGA_IOCE_SHIFT (5u) +#define POEG_POEGGA_ST (0x00010000u) +#define POEG_POEGGA_ST_SHIFT (16u) +#define POEG_POEGGA_INV (0x10000000u) +#define POEG_POEGGA_INV_SHIFT (28u) +#define POEG_POEGGA_NFEN (0x20000000u) +#define POEG_POEGGA_NFEN_SHIFT (29u) +#define POEG_POEGGA_NFCS (0xC0000000u) +#define POEG_POEGGA_NFCS_SHIFT (30u) +#define POEG_POEGGB_PIDF (0x00000001u) +#define POEG_POEGGB_PIDF_SHIFT (0u) +#define POEG_POEGGB_IOCF (0x00000002u) +#define POEG_POEGGB_IOCF_SHIFT (1u) +#define POEG_POEGGB_SSF (0x00000008u) +#define POEG_POEGGB_SSF_SHIFT (3u) +#define POEG_POEGGB_PIDE (0x00000010u) +#define POEG_POEGGB_PIDE_SHIFT (4u) +#define POEG_POEGGB_IOCE (0x00000020u) +#define POEG_POEGGB_IOCE_SHIFT (5u) +#define POEG_POEGGB_ST (0x00010000u) +#define POEG_POEGGB_ST_SHIFT (16u) +#define POEG_POEGGB_INV (0x10000000u) +#define POEG_POEGGB_INV_SHIFT (28u) +#define POEG_POEGGB_NFEN (0x20000000u) +#define POEG_POEGGB_NFEN_SHIFT (29u) +#define POEG_POEGGB_NFCS (0xC0000000u) +#define POEG_POEGGB_NFCS_SHIFT (30u) +#define POEG_POEGGC_PIDF (0x00000001u) +#define POEG_POEGGC_PIDF_SHIFT (0u) +#define POEG_POEGGC_IOCF (0x00000002u) +#define POEG_POEGGC_IOCF_SHIFT (1u) +#define POEG_POEGGC_SSF (0x00000008u) +#define POEG_POEGGC_SSF_SHIFT (3u) +#define POEG_POEGGC_PIDE (0x00000010u) +#define POEG_POEGGC_PIDE_SHIFT (4u) +#define POEG_POEGGC_IOCE (0x00000020u) +#define POEG_POEGGC_IOCE_SHIFT (5u) +#define POEG_POEGGC_ST (0x00010000u) +#define POEG_POEGGC_ST_SHIFT (16u) +#define POEG_POEGGC_INV (0x10000000u) +#define POEG_POEGGC_INV_SHIFT (28u) +#define POEG_POEGGC_NFEN (0x20000000u) +#define POEG_POEGGC_NFEN_SHIFT (29u) +#define POEG_POEGGC_NFCS (0xC0000000u) +#define POEG_POEGGC_NFCS_SHIFT (30u) +#define POEG_POEGGD_PIDF (0x00000001u) +#define POEG_POEGGD_PIDF_SHIFT (0u) +#define POEG_POEGGD_IOCF (0x00000002u) +#define POEG_POEGGD_IOCF_SHIFT (1u) +#define POEG_POEGGD_SSF (0x00000008u) +#define POEG_POEGGD_SSF_SHIFT (3u) +#define POEG_POEGGD_PIDE (0x00000010u) +#define POEG_POEGGD_PIDE_SHIFT (4u) +#define POEG_POEGGD_IOCE (0x00000020u) +#define POEG_POEGGD_IOCE_SHIFT (5u) +#define POEG_POEGGD_ST (0x00010000u) +#define POEG_POEGGD_ST_SHIFT (16u) +#define POEG_POEGGD_INV (0x10000000u) +#define POEG_POEGGD_INV_SHIFT (28u) +#define POEG_POEGGD_NFEN (0x20000000u) +#define POEG_POEGGD_NFEN_SHIFT (29u) +#define POEG_POEGGD_NFCS (0xC0000000u) +#define POEG_POEGGD_NFCS_SHIFT (30u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/prr_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/prr_iobitmask.h new file mode 100644 index 0000000..7b1225a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/prr_iobitmask.h @@ -0,0 +1,344 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef PRR_IOBITMASK_H +#define PRR_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define PRR_BSID_DID (0xFFFFFFFFu) +#define PRR_BSID_DID_SHIFT (0u) +#define PRR_AXIBUSCTL0_ETHAXCACHE (0x00000003u) +#define PRR_AXIBUSCTL0_ETHAXCACHE_SHIFT (0u) +#define PRR_AXIBUSCTL0_JCUAWCACHE (0x000F0000u) +#define PRR_AXIBUSCTL0_JCUAWCACHE_SHIFT (16u) +#define PRR_AXIBUSCTL0_JCUARCACHE (0x0F000000u) +#define PRR_AXIBUSCTL0_JCUARCACHE_SHIFT (24u) +#define PRR_AXIBUSCTL1_VINAWCACHE (0x0000000Fu) +#define PRR_AXIBUSCTL1_VINAWCACHE_SHIFT (0u) +#define PRR_AXIBUSCTL1_IMR20AWCACHE (0x000F0000u) +#define PRR_AXIBUSCTL1_IMR20AWCACHE_SHIFT (16u) +#define PRR_AXIBUSCTL1_IMR20ARCACHE (0x0F000000u) +#define PRR_AXIBUSCTL1_IMR20ARCACHE_SHIFT (24u) +#define PRR_AXIBUSCTL2_CEUAWCACHE (0x0000000Fu) +#define PRR_AXIBUSCTL2_CEUAWCACHE_SHIFT (0u) +#define PRR_AXIBUSCTL3_SDMMC1AWCACHE (0x0000000Fu) +#define PRR_AXIBUSCTL3_SDMMC1AWCACHE_SHIFT (0u) +#define PRR_AXIBUSCTL3_SDMMC1ARCACHE (0x00000F00u) +#define PRR_AXIBUSCTL3_SDMMC1ARCACHE_SHIFT (8u) +#define PRR_AXIBUSCTL3_SDMMC0AWCACHE (0x000F0000u) +#define PRR_AXIBUSCTL3_SDMMC0AWCACHE_SHIFT (16u) +#define PRR_AXIBUSCTL3_SDMMC0ARCACHE (0x0F000000u) +#define PRR_AXIBUSCTL3_SDMMC0ARCACHE_SHIFT (24u) +#define PRR_AXIBUSCTL4_DRPAWCACHE (0x0000000Fu) +#define PRR_AXIBUSCTL4_DRPAWCACHE_SHIFT (0u) +#define PRR_AXIBUSCTL4_DRPARCACHE (0x00000F00u) +#define PRR_AXIBUSCTL4_DRPARCACHE_SHIFT (8u) +#define PRR_AXIBUSCTL4_NANDAWCACHE (0x000F0000u) +#define PRR_AXIBUSCTL4_NANDAWCACHE_SHIFT (16u) +#define PRR_AXIBUSCTL4_NANDARCACHE (0x0F000000u) +#define PRR_AXIBUSCTL4_NANDARCACHE_SHIFT (24u) +#define PRR_AXIBUSCTL5_D2D1AXCACHE (0x00000003u) +#define PRR_AXIBUSCTL5_D2D1AXCACHE_SHIFT (0u) +#define PRR_AXIBUSCTL5_D2D0AXCACHE (0x00030000u) +#define PRR_AXIBUSCTL5_D2D0AXCACHE_SHIFT (16u) +#define PRR_AXIBUSCTL6_VDC602ARCACHE (0x00000F00u) +#define PRR_AXIBUSCTL6_VDC602ARCACHE_SHIFT (8u) +#define PRR_AXIBUSCTL6_VDC601AWCACHE (0x000F0000u) +#define PRR_AXIBUSCTL6_VDC601AWCACHE_SHIFT (16u) +#define PRR_AXIBUSCTL6_VDC601ARCACHE (0x0F000000u) +#define PRR_AXIBUSCTL6_VDC601ARCACHE_SHIFT (24u) +#define PRR_AXIBUSCTL7_VDC604ARCACHE (0x00000F00u) +#define PRR_AXIBUSCTL7_VDC604ARCACHE_SHIFT (8u) +#define PRR_AXIRERRCTL0_CEURERREN (0x00000100u) +#define PRR_AXIRERRCTL0_CEURERREN_SHIFT (8u) +#define PRR_AXIRERRCTL0_VINRERREN (0x00010000u) +#define PRR_AXIRERRCTL0_VINRERREN_SHIFT (16u) +#define PRR_AXIRERRCTL0_IMR20RERREN (0x00100000u) +#define PRR_AXIRERRCTL0_IMR20RERREN_SHIFT (20u) +#define PRR_AXIRERRCTL0_JCURERREN (0x10000000u) +#define PRR_AXIRERRCTL0_JCURERREN_SHIFT (28u) +#define PRR_AXIRERRCTL1_DRPRERREN (0x00010000u) +#define PRR_AXIRERRCTL1_DRPRERREN_SHIFT (16u) +#define PRR_AXIRERRCTL1_NANDRERREN (0x00100000u) +#define PRR_AXIRERRCTL1_NANDRERREN_SHIFT (20u) +#define PRR_AXIRERRCTL1_SDMMC1RERREN (0x01000000u) +#define PRR_AXIRERRCTL1_SDMMC1RERREN_SHIFT (24u) +#define PRR_AXIRERRCTL1_SDMMC0RERREN (0x10000000u) +#define PRR_AXIRERRCTL1_SDMMC0RERREN_SHIFT (28u) +#define PRR_AXIRERRCTL2_VDC604RERREN (0x00010000u) +#define PRR_AXIRERRCTL2_VDC604RERREN_SHIFT (16u) +#define PRR_AXIRERRCTL2_VDC602RERREN (0x01000000u) +#define PRR_AXIRERRCTL2_VDC602RERREN_SHIFT (24u) +#define PRR_AXIRERRCTL2_VDC601RERREN (0x10000000u) +#define PRR_AXIRERRCTL2_VDC601RERREN_SHIFT (28u) +#define PRR_AXIRERRST0_CEUBRESP (0x00000300u) +#define PRR_AXIRERRST0_CEUBRESP_SHIFT (8u) +#define PRR_AXIRERRST0_VINBRESP (0x00030000u) +#define PRR_AXIRERRST0_VINBRESP_SHIFT (16u) +#define PRR_AXIRERRST0_IMR20BRESP (0x00300000u) +#define PRR_AXIRERRST0_IMR20BRESP_SHIFT (20u) +#define PRR_AXIRERRST0_IMR20RRESP (0x00C00000u) +#define PRR_AXIRERRST0_IMR20RRESP_SHIFT (22u) +#define PRR_AXIRERRST0_JCUBRESP (0x30000000u) +#define PRR_AXIRERRST0_JCUBRESP_SHIFT (28u) +#define PRR_AXIRERRST0_JCURRESP (0xC0000000u) +#define PRR_AXIRERRST0_JCURRESP_SHIFT (30u) +#define PRR_AXIRERRST1_DRPBRESP (0x00030000u) +#define PRR_AXIRERRST1_DRPBRESP_SHIFT (16u) +#define PRR_AXIRERRST1_DRPRRESP (0x000C0000u) +#define PRR_AXIRERRST1_DRPRRESP_SHIFT (18u) +#define PRR_AXIRERRST1_NANDBRESP (0x00300000u) +#define PRR_AXIRERRST1_NANDBRESP_SHIFT (20u) +#define PRR_AXIRERRST1_NANDRRESP (0x00C00000u) +#define PRR_AXIRERRST1_NANDRRESP_SHIFT (22u) +#define PRR_AXIRERRST1_SDMMC1BRESP (0x03000000u) +#define PRR_AXIRERRST1_SDMMC1BRESP_SHIFT (24u) +#define PRR_AXIRERRST1_SDMMC1RRESP (0x0C000000u) +#define PRR_AXIRERRST1_SDMMC1RRESP_SHIFT (26u) +#define PRR_AXIRERRST1_SDMMC0BRESP (0x30000000u) +#define PRR_AXIRERRST1_SDMMC0BRESP_SHIFT (28u) +#define PRR_AXIRERRST1_SDMMC0RRESP (0xC0000000u) +#define PRR_AXIRERRST1_SDMMC0RRESP_SHIFT (30u) +#define PRR_AXIRERRST2_VDC604RRESP (0x000C0000u) +#define PRR_AXIRERRST2_VDC604RRESP_SHIFT (18u) +#define PRR_AXIRERRST2_VDC602RRESP (0x0C000000u) +#define PRR_AXIRERRST2_VDC602RRESP_SHIFT (26u) +#define PRR_AXIRERRST2_VDC601BRESP (0x30000000u) +#define PRR_AXIRERRST2_VDC601BRESP_SHIFT (28u) +#define PRR_AXIRERRST2_VDC601RRESP (0xC0000000u) +#define PRR_AXIRERRST2_VDC601RRESP_SHIFT (30u) +#define PRR_AXIRERRCLR0_CEUBRESPCLR (0x00000100u) +#define PRR_AXIRERRCLR0_CEUBRESPCLR_SHIFT (8u) +#define PRR_AXIRERRCLR0_SERBRESPCLR (0x00001000u) +#define PRR_AXIRERRCLR0_SERBRESPCLR_SHIFT (12u) +#define PRR_AXIRERRCLR0_SERRRESPCLR (0x00004000u) +#define PRR_AXIRERRCLR0_SERRRESPCLR_SHIFT (14u) +#define PRR_AXIRERRCLR0_VINBRESPCLR (0x00010000u) +#define PRR_AXIRERRCLR0_VINBRESPCLR_SHIFT (16u) +#define PRR_AXIRERRCLR0_IMR20BRESPCLR (0x00100000u) +#define PRR_AXIRERRCLR0_IMR20BRESPCLR_SHIFT (20u) +#define PRR_AXIRERRCLR0_IMR20RRESPCLR (0x00400000u) +#define PRR_AXIRERRCLR0_IMR20RRESPCLR_SHIFT (22u) +#define PRR_AXIRERRCLR0_JCUBRESPCLR (0x10000000u) +#define PRR_AXIRERRCLR0_JCUBRESPCLR_SHIFT (28u) +#define PRR_AXIRERRCLR0_JCURRESPCLR (0x40000000u) +#define PRR_AXIRERRCLR0_JCURRESPCLR_SHIFT (30u) +#define PRR_AXIRERRCLR1_DRPBRESPCLR (0x00010000u) +#define PRR_AXIRERRCLR1_DRPBRESPCLR_SHIFT (16u) +#define PRR_AXIRERRCLR1_DRPRRESPCLR (0x00040000u) +#define PRR_AXIRERRCLR1_DRPRRESPCLR_SHIFT (18u) +#define PRR_AXIRERRCLR1_NANDBRESPCLR (0x00100000u) +#define PRR_AXIRERRCLR1_NANDBRESPCLR_SHIFT (20u) +#define PRR_AXIRERRCLR1_NANDRRESPCLR (0x00400000u) +#define PRR_AXIRERRCLR1_NANDRRESPCLR_SHIFT (22u) +#define PRR_AXIRERRCLR1_SDMMC1BRESPCLR (0x01000000u) +#define PRR_AXIRERRCLR1_SDMMC1BRESPCLR_SHIFT (24u) +#define PRR_AXIRERRCLR1_SDMMC1RRESPCLR (0x04000000u) +#define PRR_AXIRERRCLR1_SDMMC1RRESPCLR_SHIFT (26u) +#define PRR_AXIRERRCLR1_SDMMC0BRESPCLR (0x10000000u) +#define PRR_AXIRERRCLR1_SDMMC0BRESPCLR_SHIFT (28u) +#define PRR_AXIRERRCLR1_SDMMC0RRESPCLR (0x40000000u) +#define PRR_AXIRERRCLR1_SDMMC0RRESPCLR_SHIFT (30u) +#define PRR_AXIRERRCLR2_VDC604RRESPCLR (0x00040000u) +#define PRR_AXIRERRCLR2_VDC604RRESPCLR_SHIFT (18u) +#define PRR_AXIRERRCLR2_VDC602RRESPCLR (0x04000000u) +#define PRR_AXIRERRCLR2_VDC602RRESPCLR_SHIFT (26u) +#define PRR_AXIRERRCLR2_VDC601BRESPCLR (0x10000000u) +#define PRR_AXIRERRCLR2_VDC601BRESPCLR_SHIFT (28u) +#define PRR_AXIRERRCLR2_VDC601RRESPCLR (0x40000000u) +#define PRR_AXIRERRCLR2_VDC601RRESPCLR_SHIFT (30u) +#define PRR_MSTACCCTL0_VINAWNS (0x00000002u) +#define PRR_MSTACCCTL0_VINAWNS_SHIFT (1u) +#define PRR_MSTACCCTL0_IMR20AWNS (0x00000200u) +#define PRR_MSTACCCTL0_IMR20AWNS_SHIFT (9u) +#define PRR_MSTACCCTL0_IMR20ARNS (0x00002000u) +#define PRR_MSTACCCTL0_IMR20ARNS_SHIFT (13u) +#define PRR_MSTACCCTL0_ETHAxNS (0x00020000u) +#define PRR_MSTACCCTL0_ETHAxNS_SHIFT (17u) +#define PRR_MSTACCCTL0_JCUAWNS (0x02000000u) +#define PRR_MSTACCCTL0_JCUAWNS_SHIFT (25u) +#define PRR_MSTACCCTL0_JCUARNS (0x20000000u) +#define PRR_MSTACCCTL0_JCUARNS_SHIFT (29u) +#define PRR_MSTACCCTL1_SDMMC1AWNS (0x00000002u) +#define PRR_MSTACCCTL1_SDMMC1AWNS_SHIFT (1u) +#define PRR_MSTACCCTL1_SDMMC1ARNS (0x00000020u) +#define PRR_MSTACCCTL1_SDMMC1ARNS_SHIFT (5u) +#define PRR_MSTACCCTL1_SDMMC0AWNS (0x00000200u) +#define PRR_MSTACCCTL1_SDMMC0AWNS_SHIFT (9u) +#define PRR_MSTACCCTL1_SDMMC0ARNS (0x00002000u) +#define PRR_MSTACCCTL1_SDMMC0ARNS_SHIFT (13u) +#define PRR_MSTACCCTL1_CEUAWNS (0x00020000u) +#define PRR_MSTACCCTL1_CEUAWNS_SHIFT (17u) +#define PRR_MSTACCCTL2_D2D1AxNS (0x00000002u) +#define PRR_MSTACCCTL2_D2D1AxNS_SHIFT (1u) +#define PRR_MSTACCCTL2_D2D0AxNS (0x00000200u) +#define PRR_MSTACCCTL2_D2D0AxNS_SHIFT (9u) +#define PRR_MSTACCCTL2_DRPAWNS (0x00020000u) +#define PRR_MSTACCCTL2_DRPAWNS_SHIFT (17u) +#define PRR_MSTACCCTL2_DRPARNS (0x00200000u) +#define PRR_MSTACCCTL2_DRPARNS_SHIFT (21u) +#define PRR_MSTACCCTL2_NANDAWNS (0x02000000u) +#define PRR_MSTACCCTL2_NANDAWNS_SHIFT (25u) +#define PRR_MSTACCCTL2_NANDARNS (0x20000000u) +#define PRR_MSTACCCTL2_NANDARNS_SHIFT (29u) +#define PRR_MSTACCCTL3_VDC604ARNS (0x00000020u) +#define PRR_MSTACCCTL3_VDC604ARNS_SHIFT (5u) +#define PRR_MSTACCCTL3_VDC602ARNS (0x00200000u) +#define PRR_MSTACCCTL3_VDC602ARNS_SHIFT (21u) +#define PRR_MSTACCCTL3_VDC601AWNS (0x02000000u) +#define PRR_MSTACCCTL3_VDC601AWNS_SHIFT (25u) +#define PRR_MSTACCCTL3_VDC601ARNS (0x20000000u) +#define PRR_MSTACCCTL3_VDC601ARNS_SHIFT (29u) +#define PRR_MSTACCCTL4_USB11AxNS (0x00000002u) +#define PRR_MSTACCCTL4_USB11AxNS_SHIFT (1u) +#define PRR_MSTACCCTL4_USB10AxNS (0x00000200u) +#define PRR_MSTACCCTL4_USB10AxNS_SHIFT (9u) +#define PRR_MSTACCCTL4_USB01AxNS (0x00020000u) +#define PRR_MSTACCCTL4_USB01AxNS_SHIFT (17u) +#define PRR_MSTACCCTL4_USB00AxNS (0x02000000u) +#define PRR_MSTACCCTL4_USB00AxNS_SHIFT (25u) +#define PRR_SLVACCCTL0_WDTNS (0x00000010u) +#define PRR_SLVACCCTL0_WDTNS_SHIFT (4u) +#define PRR_SLVACCCTL0_INTC2NS (0x00000040u) +#define PRR_SLVACCCTL0_INTC2NS_SHIFT (6u) +#define PRR_SLVACCCTL0_POEGNS (0x00004000u) +#define PRR_SLVACCCTL0_POEGNS_SHIFT (14u) +#define PRR_SLVACCCTL0_POE3NS (0x00010000u) +#define PRR_SLVACCCTL0_POE3NS_SHIFT (16u) +#define PRR_SLVACCCTL0_GPTNS (0x00040000u) +#define PRR_SLVACCCTL0_GPTNS_SHIFT (18u) +#define PRR_SLVACCCTL0_MTU3NS (0x00100000u) +#define PRR_SLVACCCTL0_MTU3NS_SHIFT (20u) +#define PRR_SLVACCCTL0_IMR20NS (0x00400000u) +#define PRR_SLVACCCTL0_IMR20NS_SHIFT (22u) +#define PRR_SLVACCCTL0_VDC60NS (0x01000000u) +#define PRR_SLVACCCTL0_VDC60NS_SHIFT (24u) +#define PRR_SLVACCCTL0_SYSNS (0x40000000u) +#define PRR_SLVACCCTL0_SYSNS_SHIFT (30u) +#define PRR_SLVACCCTL1_RSPINS (0x00000001u) +#define PRR_SLVACCCTL1_RSPINS_SHIFT (0u) +#define PRR_SLVACCCTL1_JCUNS (0x00000004u) +#define PRR_SLVACCCTL1_JCUNS_SHIFT (2u) +#define PRR_SLVACCCTL1_SCIFNS (0x00000010u) +#define PRR_SLVACCCTL1_SCIFNS_SHIFT (4u) +#define PRR_SLVACCCTL1_SCINS (0x00000040u) +#define PRR_SLVACCCTL1_SCINS_SHIFT (6u) +#define PRR_SLVACCCTL1_IRDANS (0x00000100u) +#define PRR_SLVACCCTL1_IRDANS_SHIFT (8u) +#define PRR_SLVACCCTL1_ADNS (0x00000400u) +#define PRR_SLVACCCTL1_ADNS_SHIFT (10u) +#define PRR_SLVACCCTL1_SENS (0x00004000u) +#define PRR_SLVACCCTL1_SENS_SHIFT (14u) +#define PRR_SLVACCCTL1_RCANNS (0x00010000u) +#define PRR_SLVACCCTL1_RCANNS_SHIFT (16u) +#define PRR_SLVACCCTL1_SPDIFNS (0x00040000u) +#define PRR_SLVACCCTL1_SPDIFNS_SHIFT (18u) +#define PRR_SLVACCCTL1_SSIFNS (0x00100000u) +#define PRR_SLVACCCTL1_SSIFNS_SHIFT (20u) +#define PRR_SLVACCCTL1_OSTM2NS (0x00400000u) +#define PRR_SLVACCCTL1_OSTM2NS_SHIFT (22u) +#define PRR_SLVACCCTL1_OSTM1NS (0x01000000u) +#define PRR_SLVACCCTL1_OSTM1NS_SHIFT (24u) +#define PRR_SLVACCCTL1_OSTM0NS (0x04000000u) +#define PRR_SLVACCCTL1_OSTM0NS_SHIFT (26u) +#define PRR_SLVACCCTL1_I2CNS (0x10000000u) +#define PRR_SLVACCCTL1_I2CNS_SHIFT (28u) +#define PRR_SLVACCCTL1_GPIONS (0x40000000u) +#define PRR_SLVACCCTL1_GPIONS_SHIFT (30u) +#define PRR_SLVACCCTL2_TSIPNS (0x00000004u) +#define PRR_SLVACCCTL2_TSIPNS_SHIFT (2u) +#define PRR_SLVACCCTL2_DRPNS (0x00000010u) +#define PRR_SLVACCCTL2_DRPNS_SHIFT (4u) +#define PRR_SLVACCCTL2_CEUNS (0x00000040u) +#define PRR_SLVACCCTL2_CEUNS_SHIFT (6u) +#define PRR_SLVACCCTL2_USB11NS (0x00000100u) +#define PRR_SLVACCCTL2_USB11NS_SHIFT (8u) +#define PRR_SLVACCCTL2_USB10NS (0x00000400u) +#define PRR_SLVACCCTL2_USB10NS_SHIFT (10u) +#define PRR_SLVACCCTL2_USB01NS (0x00001000u) +#define PRR_SLVACCCTL2_USB01NS_SHIFT (12u) +#define PRR_SLVACCCTL2_USB00NS (0x00004000u) +#define PRR_SLVACCCTL2_USB00NS_SHIFT (14u) +#define PRR_SLVACCCTL2_VINNS (0x00400000u) +#define PRR_SLVACCCTL2_VINNS_SHIFT (22u) +#define PRR_SLVACCCTL2_MIPINS (0x01000000u) +#define PRR_SLVACCCTL2_MIPINS_SHIFT (24u) +#define PRR_SLVACCCTL2_D2DNS (0x04000000u) +#define PRR_SLVACCCTL2_D2DNS_SHIFT (26u) +#define PRR_SLVACCCTL2_ETHNS (0x40000000u) +#define PRR_SLVACCCTL2_ETHNS_SHIFT (30u) +#define PRR_SLVACCCTL3_CSNS (0x00100000u) +#define PRR_SLVACCCTL3_CSNS_SHIFT (20u) +#define PRR_SLVACCCTL3_NANDNS (0x01000000u) +#define PRR_SLVACCCTL3_NANDNS_SHIFT (24u) +#define PRR_SLVACCCTL3_SDMMC1NS (0x04000000u) +#define PRR_SLVACCCTL3_SDMMC1NS_SHIFT (26u) +#define PRR_SLVACCCTL3_SDMMC0NS (0x10000000u) +#define PRR_SLVACCCTL3_SDMMC0NS_SHIFT (28u) +#define PRR_SLVACCCTL4_VRAM4NS (0x00000100u) +#define PRR_SLVACCCTL4_VRAM4NS_SHIFT (8u) +#define PRR_SLVACCCTL4_VRAM3NS (0x00000400u) +#define PRR_SLVACCCTL4_VRAM3NS_SHIFT (10u) +#define PRR_SLVACCCTL4_VRAM2NS (0x00001000u) +#define PRR_SLVACCCTL4_VRAM2NS_SHIFT (12u) +#define PRR_SLVACCCTL4_VRAM1NS (0x00004000u) +#define PRR_SLVACCCTL4_VRAM1NS_SHIFT (14u) +#define PRR_SLVACCCTL4_VRAM0NS (0x00010000u) +#define PRR_SLVACCCTL4_VRAM0NS_SHIFT (16u) +#define PRR_SLVACCCTL4_RRAMNS (0x00040000u) +#define PRR_SLVACCCTL4_RRAMNS_SHIFT (18u) +#define PRR_SLVACCCTL4_HYPRNS (0x00100000u) +#define PRR_SLVACCCTL4_HYPRNS_SHIFT (20u) +#define PRR_SLVACCCTL4_HYPNS (0x00400000u) +#define PRR_SLVACCCTL4_HYPNS_SHIFT (22u) +#define PRR_SLVACCCTL4_OCTARNS (0x01000000u) +#define PRR_SLVACCCTL4_OCTARNS_SHIFT (24u) +#define PRR_SLVACCCTL4_OCTANS (0x04000000u) +#define PRR_SLVACCCTL4_OCTANS_SHIFT (26u) +#define PRR_SLVACCCTL4_SPINS (0x10000000u) +#define PRR_SLVACCCTL4_SPINS_SHIFT (28u) +#define PRR_SLVACCCTL4_BSCNS (0x40000000u) +#define PRR_SLVACCCTL4_BSCNS_SHIFT (30u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ptpedmac_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ptpedmac_iobitmask.h new file mode 100644 index 0000000..91775a8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ptpedmac_iobitmask.h @@ -0,0 +1,148 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef PTPEDMAC_IOBITMASK_H +#define PTPEDMAC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define PTPEDMAC_EDMR_SWR (0x00000001u) +#define PTPEDMAC_EDMR_SWR_SHIFT (0u) +#define PTPEDMAC_EDMR_DL (0x00000030u) +#define PTPEDMAC_EDMR_DL_SHIFT (4u) +#define PTPEDMAC_EDMR_DE (0x00000040u) +#define PTPEDMAC_EDMR_DE_SHIFT (6u) +#define PTPEDMAC_EDTRR_TR (0x00000001u) +#define PTPEDMAC_EDTRR_TR_SHIFT (0u) +#define PTPEDMAC_EDRRR_RR (0x00000001u) +#define PTPEDMAC_EDRRR_RR_SHIFT (0u) +#define PTPEDMAC_TDLAR_TDLAR (0xFFFFFFFFu) +#define PTPEDMAC_TDLAR_TDLAR_SHIFT (0u) +#define PTPEDMAC_RDLAR_RDLAR (0xFFFFFFFFu) +#define PTPEDMAC_RDLAR_RDLAR_SHIFT (0u) +#define PTPEDMAC_EESR_TYPE (0x0000000Fu) +#define PTPEDMAC_EESR_TYPE_SHIFT (0u) +#define PTPEDMAC_EESR_PVER (0x00000010u) +#define PTPEDMAC_EESR_PVER_SHIFT (4u) +#define PTPEDMAC_EESR_RPORT (0x00000080u) +#define PTPEDMAC_EESR_RPORT_SHIFT (7u) +#define PTPEDMAC_EESR_MACE (0x00000100u) +#define PTPEDMAC_EESR_MACE_SHIFT (8u) +#define PTPEDMAC_EESR_RFOF (0x00010000u) +#define PTPEDMAC_EESR_RFOF_SHIFT (16u) +#define PTPEDMAC_EESR_RDE (0x00020000u) +#define PTPEDMAC_EESR_RDE_SHIFT (17u) +#define PTPEDMAC_EESR_FR (0x00040000u) +#define PTPEDMAC_EESR_FR_SHIFT (18u) +#define PTPEDMAC_EESR_TFUF (0x00080000u) +#define PTPEDMAC_EESR_TFUF_SHIFT (19u) +#define PTPEDMAC_EESR_TDE (0x00100000u) +#define PTPEDMAC_EESR_TDE_SHIFT (20u) +#define PTPEDMAC_EESR_TC (0x00200000u) +#define PTPEDMAC_EESR_TC_SHIFT (21u) +#define PTPEDMAC_EESR_RFCOF (0x01000000u) +#define PTPEDMAC_EESR_RFCOF_SHIFT (24u) +#define PTPEDMAC_EESR_TABT (0x04000000u) +#define PTPEDMAC_EESR_TABT_SHIFT (26u) +#define PTPEDMAC_EESR_TWB (0x40000000u) +#define PTPEDMAC_EESR_TWB_SHIFT (30u) +#define PTPEDMAC_EESIPR_PVERIP (0x00000010u) +#define PTPEDMAC_EESIPR_PVERIP_SHIFT (4u) +#define PTPEDMAC_EESIPR_RPORTIP (0x00000080u) +#define PTPEDMAC_EESIPR_RPORTIP_SHIFT (7u) +#define PTPEDMAC_EESIPR_MACEIP (0x00000100u) +#define PTPEDMAC_EESIPR_MACEIP_SHIFT (8u) +#define PTPEDMAC_EESIPR_RFOFIP (0x00010000u) +#define PTPEDMAC_EESIPR_RFOFIP_SHIFT (16u) +#define PTPEDMAC_EESIPR_RDEIP (0x00020000u) +#define PTPEDMAC_EESIPR_RDEIP_SHIFT (17u) +#define PTPEDMAC_EESIPR_FRIP (0x00040000u) +#define PTPEDMAC_EESIPR_FRIP_SHIFT (18u) +#define PTPEDMAC_EESIPR_TFUFIP (0x00080000u) +#define PTPEDMAC_EESIPR_TFUFIP_SHIFT (19u) +#define PTPEDMAC_EESIPR_TDEIP (0x00100000u) +#define PTPEDMAC_EESIPR_TDEIP_SHIFT (20u) +#define PTPEDMAC_EESIPR_TCIP (0x00200000u) +#define PTPEDMAC_EESIPR_TCIP_SHIFT (21u) +#define PTPEDMAC_EESIPR_RFCOFIP (0x01000000u) +#define PTPEDMAC_EESIPR_RFCOFIP_SHIFT (24u) +#define PTPEDMAC_EESIPR_TABTIP (0x04000000u) +#define PTPEDMAC_EESIPR_TABTIP_SHIFT (26u) +#define PTPEDMAC_EESIPR_TWBIP (0x40000000u) +#define PTPEDMAC_EESIPR_TWBIP_SHIFT (30u) +#define PTPEDMAC_RMFCR_MFC (0x0000FFFFu) +#define PTPEDMAC_RMFCR_MFC_SHIFT (0u) +#define PTPEDMAC_TFTR_TFT (0x000007FFu) +#define PTPEDMAC_TFTR_TFT_SHIFT (0u) +#define PTPEDMAC_FDR_RFD (0x0000001Fu) +#define PTPEDMAC_FDR_RFD_SHIFT (0u) +#define PTPEDMAC_FDR_TFD (0x00001F00u) +#define PTPEDMAC_FDR_TFD_SHIFT (8u) +#define PTPEDMAC_RMCR_RNR (0x00000001u) +#define PTPEDMAC_RMCR_RNR_SHIFT (0u) +#define PTPEDMAC_TFUCR_UNDER (0x0000FFFFu) +#define PTPEDMAC_TFUCR_UNDER_SHIFT (0u) +#define PTPEDMAC_RFOCR_OVER (0x0000FFFFu) +#define PTPEDMAC_RFOCR_OVER_SHIFT (0u) +#define PTPEDMAC_FCFTR_RFDO (0x00000007u) +#define PTPEDMAC_FCFTR_RFDO_SHIFT (0u) +#define PTPEDMAC_FCFTR_RFFO (0x00070000u) +#define PTPEDMAC_FCFTR_RFFO_SHIFT (16u) +#define PTPEDMAC_RPADIR_PADR (0x0000003Fu) +#define PTPEDMAC_RPADIR_PADR_SHIFT (0u) +#define PTPEDMAC_RPADIR_PADS (0x00030000u) +#define PTPEDMAC_RPADIR_PADS_SHIFT (16u) +#define PTPEDMAC_TRIMD_TIS (0x00000001u) +#define PTPEDMAC_TRIMD_TIS_SHIFT (0u) +#define PTPEDMAC_TRIMD_TIM (0x00000010u) +#define PTPEDMAC_TRIMD_TIM_SHIFT (4u) +#define PTPEDMAC_RBWAR_RBWAR (0xFFFFFFFFu) +#define PTPEDMAC_RBWAR_RBWAR_SHIFT (0u) +#define PTPEDMAC_RDFAR_RDFAR (0xFFFFFFFFu) +#define PTPEDMAC_RDFAR_RDFAR_SHIFT (0u) +#define PTPEDMAC_TBRAR_TBRAR (0xFFFFFFFFu) +#define PTPEDMAC_TBRAR_TBRAR_SHIFT (0u) +#define PTPEDMAC_TDFAR_TDFAR (0xFFFFFFFFu) +#define PTPEDMAC_TDFAR_TDFAR_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcan_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcan_iobitmask.h new file mode 100644 index 0000000..6fe73fe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcan_iobitmask.h @@ -0,0 +1,4476 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef RCAN_IOBITMASK_H +#define RCAN_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define RCAN_RSCAN0C0CFG_BRP (0x000003FFu) +#define RCAN_RSCAN0C0CFG_BRP_SHIFT (0u) +#define RCAN_RSCAN0C0CFG_TSEG1 (0x000F0000u) +#define RCAN_RSCAN0C0CFG_TSEG1_SHIFT (16u) +#define RCAN_RSCAN0C0CFG_TSEG2 (0x00700000u) +#define RCAN_RSCAN0C0CFG_TSEG2_SHIFT (20u) +#define RCAN_RSCAN0C0CFG_SJW (0x03000000u) +#define RCAN_RSCAN0C0CFG_SJW_SHIFT (24u) +#define RCAN_RSCAN0C0CTR_CHMDC (0x00000003u) +#define RCAN_RSCAN0C0CTR_CHMDC_SHIFT (0u) +#define RCAN_RSCAN0C0CTR_CSLPR (0x00000004u) +#define RCAN_RSCAN0C0CTR_CSLPR_SHIFT (2u) +#define RCAN_RSCAN0C0CTR_RTBO (0x00000008u) +#define RCAN_RSCAN0C0CTR_RTBO_SHIFT (3u) +#define RCAN_RSCAN0C0CTR_BEIE (0x00000100u) +#define RCAN_RSCAN0C0CTR_BEIE_SHIFT (8u) +#define RCAN_RSCAN0C0CTR_EWIE (0x00000200u) +#define RCAN_RSCAN0C0CTR_EWIE_SHIFT (9u) +#define RCAN_RSCAN0C0CTR_EPIE (0x00000400u) +#define RCAN_RSCAN0C0CTR_EPIE_SHIFT (10u) +#define RCAN_RSCAN0C0CTR_BOEIE (0x00000800u) +#define RCAN_RSCAN0C0CTR_BOEIE_SHIFT (11u) +#define RCAN_RSCAN0C0CTR_BORIE (0x00001000u) +#define RCAN_RSCAN0C0CTR_BORIE_SHIFT (12u) +#define RCAN_RSCAN0C0CTR_OLIE (0x00002000u) +#define RCAN_RSCAN0C0CTR_OLIE_SHIFT (13u) +#define RCAN_RSCAN0C0CTR_BLIE (0x00004000u) +#define RCAN_RSCAN0C0CTR_BLIE_SHIFT (14u) +#define RCAN_RSCAN0C0CTR_ALIE (0x00008000u) +#define RCAN_RSCAN0C0CTR_ALIE_SHIFT (15u) +#define RCAN_RSCAN0C0CTR_TAIE (0x00010000u) +#define RCAN_RSCAN0C0CTR_TAIE_SHIFT (16u) +#define RCAN_RSCAN0C0CTR_BOM (0x00600000u) +#define RCAN_RSCAN0C0CTR_BOM_SHIFT (21u) +#define RCAN_RSCAN0C0CTR_ERRD (0x00800000u) +#define RCAN_RSCAN0C0CTR_ERRD_SHIFT (23u) +#define RCAN_RSCAN0C0CTR_CTME (0x01000000u) +#define RCAN_RSCAN0C0CTR_CTME_SHIFT (24u) +#define RCAN_RSCAN0C0CTR_CTMS (0x06000000u) +#define RCAN_RSCAN0C0CTR_CTMS_SHIFT (25u) +#define RCAN_RSCAN0C0CTR_CRCT (0x40000000u) +#define RCAN_RSCAN0C0CTR_CRCT_SHIFT (30u) +#define RCAN_RSCAN0C0STS_CRSTSTS (0x00000001u) +#define RCAN_RSCAN0C0STS_CRSTSTS_SHIFT (0u) +#define RCAN_RSCAN0C0STS_CHLTSTS (0x00000002u) +#define RCAN_RSCAN0C0STS_CHLTSTS_SHIFT (1u) +#define RCAN_RSCAN0C0STS_CSLPSTS (0x00000004u) +#define RCAN_RSCAN0C0STS_CSLPSTS_SHIFT (2u) +#define RCAN_RSCAN0C0STS_EPSTS (0x00000008u) +#define RCAN_RSCAN0C0STS_EPSTS_SHIFT (3u) +#define RCAN_RSCAN0C0STS_BOSTS (0x00000010u) +#define RCAN_RSCAN0C0STS_BOSTS_SHIFT (4u) +#define RCAN_RSCAN0C0STS_TRMSTS (0x00000020u) +#define RCAN_RSCAN0C0STS_TRMSTS_SHIFT (5u) +#define RCAN_RSCAN0C0STS_RECSTS (0x00000040u) +#define RCAN_RSCAN0C0STS_RECSTS_SHIFT (6u) +#define RCAN_RSCAN0C0STS_COMSTS (0x00000080u) +#define RCAN_RSCAN0C0STS_COMSTS_SHIFT (7u) +#define RCAN_RSCAN0C0STS_REC (0x00FF0000u) +#define RCAN_RSCAN0C0STS_REC_SHIFT (16u) +#define RCAN_RSCAN0C0STS_TEC (0xFF000000u) +#define RCAN_RSCAN0C0STS_TEC_SHIFT (24u) +#define RCAN_RSCAN0C0ERFL_BEF (0x00000001u) +#define RCAN_RSCAN0C0ERFL_BEF_SHIFT (0u) +#define RCAN_RSCAN0C0ERFL_EWF (0x00000002u) +#define RCAN_RSCAN0C0ERFL_EWF_SHIFT (1u) +#define RCAN_RSCAN0C0ERFL_EPF (0x00000004u) +#define RCAN_RSCAN0C0ERFL_EPF_SHIFT (2u) +#define RCAN_RSCAN0C0ERFL_BOEF (0x00000008u) +#define RCAN_RSCAN0C0ERFL_BOEF_SHIFT (3u) +#define RCAN_RSCAN0C0ERFL_BORF (0x00000010u) +#define RCAN_RSCAN0C0ERFL_BORF_SHIFT (4u) +#define RCAN_RSCAN0C0ERFL_OVLF (0x00000020u) +#define RCAN_RSCAN0C0ERFL_OVLF_SHIFT (5u) +#define RCAN_RSCAN0C0ERFL_BLF (0x00000040u) +#define RCAN_RSCAN0C0ERFL_BLF_SHIFT (6u) +#define RCAN_RSCAN0C0ERFL_ALF (0x00000080u) +#define RCAN_RSCAN0C0ERFL_ALF_SHIFT (7u) +#define RCAN_RSCAN0C0ERFL_SERR (0x00000100u) +#define RCAN_RSCAN0C0ERFL_SERR_SHIFT (8u) +#define RCAN_RSCAN0C0ERFL_FERR (0x00000200u) +#define RCAN_RSCAN0C0ERFL_FERR_SHIFT (9u) +#define RCAN_RSCAN0C0ERFL_AERR (0x00000400u) +#define RCAN_RSCAN0C0ERFL_AERR_SHIFT (10u) +#define RCAN_RSCAN0C0ERFL_CERR (0x00000800u) +#define RCAN_RSCAN0C0ERFL_CERR_SHIFT (11u) +#define RCAN_RSCAN0C0ERFL_B1ERR (0x00001000u) +#define RCAN_RSCAN0C0ERFL_B1ERR_SHIFT (12u) +#define RCAN_RSCAN0C0ERFL_B0ERR (0x00002000u) +#define RCAN_RSCAN0C0ERFL_B0ERR_SHIFT (13u) +#define RCAN_RSCAN0C0ERFL_ADERR (0x00004000u) +#define RCAN_RSCAN0C0ERFL_ADERR_SHIFT (14u) +#define RCAN_RSCAN0C0ERFL_CRCREG (0x7FFF0000u) +#define RCAN_RSCAN0C0ERFL_CRCREG_SHIFT (16u) +#define RCAN_RSCAN0C1CFG_BRP (0x000003FFu) +#define RCAN_RSCAN0C1CFG_BRP_SHIFT (0u) +#define RCAN_RSCAN0C1CFG_TSEG1 (0x000F0000u) +#define RCAN_RSCAN0C1CFG_TSEG1_SHIFT (16u) +#define RCAN_RSCAN0C1CFG_TSEG2 (0x00700000u) +#define RCAN_RSCAN0C1CFG_TSEG2_SHIFT (20u) +#define RCAN_RSCAN0C1CFG_SJW (0x03000000u) +#define RCAN_RSCAN0C1CFG_SJW_SHIFT (24u) +#define RCAN_RSCAN0C1CTR_CHMDC (0x00000003u) +#define RCAN_RSCAN0C1CTR_CHMDC_SHIFT (0u) +#define RCAN_RSCAN0C1CTR_CSLPR (0x00000004u) +#define RCAN_RSCAN0C1CTR_CSLPR_SHIFT (2u) +#define RCAN_RSCAN0C1CTR_RTBO (0x00000008u) +#define RCAN_RSCAN0C1CTR_RTBO_SHIFT (3u) +#define RCAN_RSCAN0C1CTR_BEIE (0x00000100u) +#define RCAN_RSCAN0C1CTR_BEIE_SHIFT (8u) +#define RCAN_RSCAN0C1CTR_EWIE (0x00000200u) +#define RCAN_RSCAN0C1CTR_EWIE_SHIFT (9u) +#define RCAN_RSCAN0C1CTR_EPIE (0x00000400u) +#define RCAN_RSCAN0C1CTR_EPIE_SHIFT (10u) +#define RCAN_RSCAN0C1CTR_BOEIE (0x00000800u) +#define RCAN_RSCAN0C1CTR_BOEIE_SHIFT (11u) +#define RCAN_RSCAN0C1CTR_BORIE (0x00001000u) +#define RCAN_RSCAN0C1CTR_BORIE_SHIFT (12u) +#define RCAN_RSCAN0C1CTR_OLIE (0x00002000u) +#define RCAN_RSCAN0C1CTR_OLIE_SHIFT (13u) +#define RCAN_RSCAN0C1CTR_BLIE (0x00004000u) +#define RCAN_RSCAN0C1CTR_BLIE_SHIFT (14u) +#define RCAN_RSCAN0C1CTR_ALIE (0x00008000u) +#define RCAN_RSCAN0C1CTR_ALIE_SHIFT (15u) +#define RCAN_RSCAN0C1CTR_TAIE (0x00010000u) +#define RCAN_RSCAN0C1CTR_TAIE_SHIFT (16u) +#define RCAN_RSCAN0C1CTR_BOM (0x00600000u) +#define RCAN_RSCAN0C1CTR_BOM_SHIFT (21u) +#define RCAN_RSCAN0C1CTR_ERRD (0x00800000u) +#define RCAN_RSCAN0C1CTR_ERRD_SHIFT (23u) +#define RCAN_RSCAN0C1CTR_CTME (0x01000000u) +#define RCAN_RSCAN0C1CTR_CTME_SHIFT (24u) +#define RCAN_RSCAN0C1CTR_CTMS (0x06000000u) +#define RCAN_RSCAN0C1CTR_CTMS_SHIFT (25u) +#define RCAN_RSCAN0C1CTR_CRCT (0x40000000u) +#define RCAN_RSCAN0C1CTR_CRCT_SHIFT (30u) +#define RCAN_RSCAN0C1STS_CRSTSTS (0x00000001u) +#define RCAN_RSCAN0C1STS_CRSTSTS_SHIFT (0u) +#define RCAN_RSCAN0C1STS_CHLTSTS (0x00000002u) +#define RCAN_RSCAN0C1STS_CHLTSTS_SHIFT (1u) +#define RCAN_RSCAN0C1STS_CSLPSTS (0x00000004u) +#define RCAN_RSCAN0C1STS_CSLPSTS_SHIFT (2u) +#define RCAN_RSCAN0C1STS_EPSTS (0x00000008u) +#define RCAN_RSCAN0C1STS_EPSTS_SHIFT (3u) +#define RCAN_RSCAN0C1STS_BOSTS (0x00000010u) +#define RCAN_RSCAN0C1STS_BOSTS_SHIFT (4u) +#define RCAN_RSCAN0C1STS_TRMSTS (0x00000020u) +#define RCAN_RSCAN0C1STS_TRMSTS_SHIFT (5u) +#define RCAN_RSCAN0C1STS_RECSTS (0x00000040u) +#define RCAN_RSCAN0C1STS_RECSTS_SHIFT (6u) +#define RCAN_RSCAN0C1STS_COMSTS (0x00000080u) +#define RCAN_RSCAN0C1STS_COMSTS_SHIFT (7u) +#define RCAN_RSCAN0C1STS_REC (0x00FF0000u) +#define RCAN_RSCAN0C1STS_REC_SHIFT (16u) +#define RCAN_RSCAN0C1STS_TEC (0xFF000000u) +#define RCAN_RSCAN0C1STS_TEC_SHIFT (24u) +#define RCAN_RSCAN0C1ERFL_BEF (0x00000001u) +#define RCAN_RSCAN0C1ERFL_BEF_SHIFT (0u) +#define RCAN_RSCAN0C1ERFL_EWF (0x00000002u) +#define RCAN_RSCAN0C1ERFL_EWF_SHIFT (1u) +#define RCAN_RSCAN0C1ERFL_EPF (0x00000004u) +#define RCAN_RSCAN0C1ERFL_EPF_SHIFT (2u) +#define RCAN_RSCAN0C1ERFL_BOEF (0x00000008u) +#define RCAN_RSCAN0C1ERFL_BOEF_SHIFT (3u) +#define RCAN_RSCAN0C1ERFL_BORF (0x00000010u) +#define RCAN_RSCAN0C1ERFL_BORF_SHIFT (4u) +#define RCAN_RSCAN0C1ERFL_OVLF (0x00000020u) +#define RCAN_RSCAN0C1ERFL_OVLF_SHIFT (5u) +#define RCAN_RSCAN0C1ERFL_BLF (0x00000040u) +#define RCAN_RSCAN0C1ERFL_BLF_SHIFT (6u) +#define RCAN_RSCAN0C1ERFL_ALF (0x00000080u) +#define RCAN_RSCAN0C1ERFL_ALF_SHIFT (7u) +#define RCAN_RSCAN0C1ERFL_SERR (0x00000100u) +#define RCAN_RSCAN0C1ERFL_SERR_SHIFT (8u) +#define RCAN_RSCAN0C1ERFL_FERR (0x00000200u) +#define RCAN_RSCAN0C1ERFL_FERR_SHIFT (9u) +#define RCAN_RSCAN0C1ERFL_AERR (0x00000400u) +#define RCAN_RSCAN0C1ERFL_AERR_SHIFT (10u) +#define RCAN_RSCAN0C1ERFL_CERR (0x00000800u) +#define RCAN_RSCAN0C1ERFL_CERR_SHIFT (11u) +#define RCAN_RSCAN0C1ERFL_B1ERR (0x00001000u) +#define RCAN_RSCAN0C1ERFL_B1ERR_SHIFT (12u) +#define RCAN_RSCAN0C1ERFL_B0ERR (0x00002000u) +#define RCAN_RSCAN0C1ERFL_B0ERR_SHIFT (13u) +#define RCAN_RSCAN0C1ERFL_ADERR (0x00004000u) +#define RCAN_RSCAN0C1ERFL_ADERR_SHIFT (14u) +#define RCAN_RSCAN0C1ERFL_CRCREG (0x7FFF0000u) +#define RCAN_RSCAN0C1ERFL_CRCREG_SHIFT (16u) +#define RCAN_RSCAN0GCFG_TPRI (0x00000001u) +#define RCAN_RSCAN0GCFG_TPRI_SHIFT (0u) +#define RCAN_RSCAN0GCFG_DCE (0x00000002u) +#define RCAN_RSCAN0GCFG_DCE_SHIFT (1u) +#define RCAN_RSCAN0GCFG_DRE (0x00000004u) +#define RCAN_RSCAN0GCFG_DRE_SHIFT (2u) +#define RCAN_RSCAN0GCFG_MME (0x00000008u) +#define RCAN_RSCAN0GCFG_MME_SHIFT (3u) +#define RCAN_RSCAN0GCFG_DCS (0x00000010u) +#define RCAN_RSCAN0GCFG_DCS_SHIFT (4u) +#define RCAN_RSCAN0GCFG_TMTSCE (0x00000080u) +#define RCAN_RSCAN0GCFG_TMTSCE_SHIFT (7u) +#define RCAN_RSCAN0GCFG_TSP (0x00000F00u) +#define RCAN_RSCAN0GCFG_TSP_SHIFT (8u) +#define RCAN_RSCAN0GCFG_TSSS (0x00001000u) +#define RCAN_RSCAN0GCFG_TSSS_SHIFT (12u) +#define RCAN_RSCAN0GCFG_TSBTCS (0x0000E000u) +#define RCAN_RSCAN0GCFG_TSBTCS_SHIFT (13u) +#define RCAN_RSCAN0GCFG_ITRCP (0xFFFF0000u) +#define RCAN_RSCAN0GCFG_ITRCP_SHIFT (16u) +#define RCAN_RSCAN0GCTR_GMDC (0x00000003u) +#define RCAN_RSCAN0GCTR_GMDC_SHIFT (0u) +#define RCAN_RSCAN0GCTR_GSLPR (0x00000004u) +#define RCAN_RSCAN0GCTR_GSLPR_SHIFT (2u) +#define RCAN_RSCAN0GCTR_DEIE (0x00000100u) +#define RCAN_RSCAN0GCTR_DEIE_SHIFT (8u) +#define RCAN_RSCAN0GCTR_MEIE (0x00000200u) +#define RCAN_RSCAN0GCTR_MEIE_SHIFT (9u) +#define RCAN_RSCAN0GCTR_THLEIE (0x00000400u) +#define RCAN_RSCAN0GCTR_THLEIE_SHIFT (10u) +#define RCAN_RSCAN0GCTR_TSRST (0x00010000u) +#define RCAN_RSCAN0GCTR_TSRST_SHIFT (16u) +#define RCAN_RSCAN0GSTS_GRSTSTS (0x00000001u) +#define RCAN_RSCAN0GSTS_GRSTSTS_SHIFT (0u) +#define RCAN_RSCAN0GSTS_GHLTSTS (0x00000002u) +#define RCAN_RSCAN0GSTS_GHLTSTS_SHIFT (1u) +#define RCAN_RSCAN0GSTS_GSLPSTS (0x00000004u) +#define RCAN_RSCAN0GSTS_GSLPSTS_SHIFT (2u) +#define RCAN_RSCAN0GSTS_GRAMINIT (0x00000008u) +#define RCAN_RSCAN0GSTS_GRAMINIT_SHIFT (3u) +#define RCAN_RSCAN0GERFL_DEF (0x00000001u) +#define RCAN_RSCAN0GERFL_DEF_SHIFT (0u) +#define RCAN_RSCAN0GERFL_MES (0x00000002u) +#define RCAN_RSCAN0GERFL_MES_SHIFT (1u) +#define RCAN_RSCAN0GERFL_THLES (0x00000004u) +#define RCAN_RSCAN0GERFL_THLES_SHIFT (2u) +#define RCAN_RSCAN0GTSC_TS (0x0000FFFFu) +#define RCAN_RSCAN0GTSC_TS_SHIFT (0u) +#define RCAN_RSCAN0GAFLECTR_AFLPN (0x0000001Fu) +#define RCAN_RSCAN0GAFLECTR_AFLPN_SHIFT (0u) +#define RCAN_RSCAN0GAFLECTR_AFLDAE (0x00000100u) +#define RCAN_RSCAN0GAFLECTR_AFLDAE_SHIFT (8u) +#define RCAN_RSCAN0GAFLCFG0_RNC1 (0x00FF0000u) +#define RCAN_RSCAN0GAFLCFG0_RNC1_SHIFT (16u) +#define RCAN_RSCAN0GAFLCFG0_RNC0 (0xFF000000u) +#define RCAN_RSCAN0GAFLCFG0_RNC0_SHIFT (24u) +#define RCAN_RSCAN0RMNB_NRXMB (0x000000FFu) +#define RCAN_RSCAN0RMNB_NRXMB_SHIFT (0u) +#define RCAN_RSCAN0RMND0_RMNS0 (0x00000001u) +#define RCAN_RSCAN0RMND0_RMNS0_SHIFT (0u) +#define RCAN_RSCAN0RMND0_RMNS1 (0x00000002u) +#define RCAN_RSCAN0RMND0_RMNS1_SHIFT (1u) +#define RCAN_RSCAN0RMND0_RMNS2 (0x00000004u) +#define RCAN_RSCAN0RMND0_RMNS2_SHIFT (2u) +#define RCAN_RSCAN0RMND0_RMNS3 (0x00000008u) +#define RCAN_RSCAN0RMND0_RMNS3_SHIFT (3u) +#define RCAN_RSCAN0RMND0_RMNS4 (0x00000010u) +#define RCAN_RSCAN0RMND0_RMNS4_SHIFT (4u) +#define RCAN_RSCAN0RMND0_RMNS5 (0x00000020u) +#define RCAN_RSCAN0RMND0_RMNS5_SHIFT (5u) +#define RCAN_RSCAN0RMND0_RMNS6 (0x00000040u) +#define RCAN_RSCAN0RMND0_RMNS6_SHIFT (6u) +#define RCAN_RSCAN0RMND0_RMNS7 (0x00000080u) +#define RCAN_RSCAN0RMND0_RMNS7_SHIFT (7u) +#define RCAN_RSCAN0RMND0_RMNS8 (0x00000100u) +#define RCAN_RSCAN0RMND0_RMNS8_SHIFT (8u) +#define RCAN_RSCAN0RMND0_RMNS9 (0x00000200u) +#define RCAN_RSCAN0RMND0_RMNS9_SHIFT (9u) +#define RCAN_RSCAN0RMND0_RMNS10 (0x00000400u) +#define RCAN_RSCAN0RMND0_RMNS10_SHIFT (10u) +#define RCAN_RSCAN0RMND0_RMNS11 (0x00000800u) +#define RCAN_RSCAN0RMND0_RMNS11_SHIFT (11u) +#define RCAN_RSCAN0RMND0_RMNS12 (0x00001000u) +#define RCAN_RSCAN0RMND0_RMNS12_SHIFT (12u) +#define RCAN_RSCAN0RMND0_RMNS13 (0x00002000u) +#define RCAN_RSCAN0RMND0_RMNS13_SHIFT (13u) +#define RCAN_RSCAN0RMND0_RMNS14 (0x00004000u) +#define RCAN_RSCAN0RMND0_RMNS14_SHIFT (14u) +#define RCAN_RSCAN0RMND0_RMNS15 (0x00008000u) +#define RCAN_RSCAN0RMND0_RMNS15_SHIFT (15u) +#define RCAN_RSCAN0RMND0_RMNS16 (0x00010000u) +#define RCAN_RSCAN0RMND0_RMNS16_SHIFT (16u) +#define RCAN_RSCAN0RMND0_RMNS17 (0x00020000u) +#define RCAN_RSCAN0RMND0_RMNS17_SHIFT (17u) +#define RCAN_RSCAN0RMND0_RMNS18 (0x00040000u) +#define RCAN_RSCAN0RMND0_RMNS18_SHIFT (18u) +#define RCAN_RSCAN0RMND0_RMNS19 (0x00080000u) +#define RCAN_RSCAN0RMND0_RMNS19_SHIFT (19u) +#define RCAN_RSCAN0RMND0_RMNS20 (0x00100000u) +#define RCAN_RSCAN0RMND0_RMNS20_SHIFT (20u) +#define RCAN_RSCAN0RMND0_RMNS21 (0x00200000u) +#define RCAN_RSCAN0RMND0_RMNS21_SHIFT (21u) +#define RCAN_RSCAN0RMND0_RMNS22 (0x00400000u) +#define RCAN_RSCAN0RMND0_RMNS22_SHIFT (22u) +#define RCAN_RSCAN0RMND0_RMNS23 (0x00800000u) +#define RCAN_RSCAN0RMND0_RMNS23_SHIFT (23u) +#define RCAN_RSCAN0RMND0_RMNS24 (0x01000000u) +#define RCAN_RSCAN0RMND0_RMNS24_SHIFT (24u) +#define RCAN_RSCAN0RMND0_RMNS25 (0x02000000u) +#define RCAN_RSCAN0RMND0_RMNS25_SHIFT (25u) +#define RCAN_RSCAN0RMND0_RMNS26 (0x04000000u) +#define RCAN_RSCAN0RMND0_RMNS26_SHIFT (26u) +#define RCAN_RSCAN0RMND0_RMNS27 (0x08000000u) +#define RCAN_RSCAN0RMND0_RMNS27_SHIFT (27u) +#define RCAN_RSCAN0RMND0_RMNS28 (0x10000000u) +#define RCAN_RSCAN0RMND0_RMNS28_SHIFT (28u) +#define RCAN_RSCAN0RMND0_RMNS29 (0x20000000u) +#define RCAN_RSCAN0RMND0_RMNS29_SHIFT (29u) +#define RCAN_RSCAN0RMND0_RMNS30 (0x40000000u) +#define RCAN_RSCAN0RMND0_RMNS30_SHIFT (30u) +#define RCAN_RSCAN0RMND0_RMNS31 (0x80000000u) +#define RCAN_RSCAN0RMND0_RMNS31_SHIFT (31u) +#define RCAN_RSCAN0RFCC0_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC0_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC0_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC0_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC0_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC0_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC0_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC0_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC0_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC0_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFCC1_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC1_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC1_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC1_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC1_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC1_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC1_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC1_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC1_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC1_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFCC2_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC2_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC2_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC2_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC2_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC2_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC2_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC2_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC2_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC2_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFCC3_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC3_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC3_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC3_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC3_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC3_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC3_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC3_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC3_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC3_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFCC4_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC4_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC4_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC4_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC4_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC4_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC4_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC4_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC4_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC4_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFCC5_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC5_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC5_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC5_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC5_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC5_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC5_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC5_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC5_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC5_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFCC6_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC6_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC6_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC6_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC6_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC6_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC6_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC6_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC6_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC6_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFCC7_RFE (0x00000001u) +#define RCAN_RSCAN0RFCC7_RFE_SHIFT (0u) +#define RCAN_RSCAN0RFCC7_RFIE (0x00000002u) +#define RCAN_RSCAN0RFCC7_RFIE_SHIFT (1u) +#define RCAN_RSCAN0RFCC7_RFDC (0x00000700u) +#define RCAN_RSCAN0RFCC7_RFDC_SHIFT (8u) +#define RCAN_RSCAN0RFCC7_RFIM (0x00001000u) +#define RCAN_RSCAN0RFCC7_RFIM_SHIFT (12u) +#define RCAN_RSCAN0RFCC7_RFIGCV (0x0000E000u) +#define RCAN_RSCAN0RFCC7_RFIGCV_SHIFT (13u) +#define RCAN_RSCAN0RFSTS0_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS0_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS0_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS0_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS0_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS0_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS0_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS0_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS0_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS0_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFSTS1_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS1_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS1_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS1_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS1_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS1_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS1_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS1_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS1_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS1_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFSTS2_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS2_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS2_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS2_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS2_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS2_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS2_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS2_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS2_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS2_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFSTS3_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS3_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS3_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS3_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS3_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS3_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS3_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS3_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS3_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS3_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFSTS4_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS4_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS4_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS4_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS4_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS4_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS4_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS4_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS4_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS4_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFSTS5_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS5_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS5_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS5_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS5_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS5_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS5_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS5_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS5_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS5_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFSTS6_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS6_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS6_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS6_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS6_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS6_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS6_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS6_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS6_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS6_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFSTS7_RFEMP (0x00000001u) +#define RCAN_RSCAN0RFSTS7_RFEMP_SHIFT (0u) +#define RCAN_RSCAN0RFSTS7_RFFLL (0x00000002u) +#define RCAN_RSCAN0RFSTS7_RFFLL_SHIFT (1u) +#define RCAN_RSCAN0RFSTS7_RFMLT (0x00000004u) +#define RCAN_RSCAN0RFSTS7_RFMLT_SHIFT (2u) +#define RCAN_RSCAN0RFSTS7_RFIF (0x00000008u) +#define RCAN_RSCAN0RFSTS7_RFIF_SHIFT (3u) +#define RCAN_RSCAN0RFSTS7_RFMC (0x0000FF00u) +#define RCAN_RSCAN0RFSTS7_RFMC_SHIFT (8u) +#define RCAN_RSCAN0RFPCTR0_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR0_RFPC_SHIFT (0u) +#define RCAN_RSCAN0RFPCTR1_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR1_RFPC_SHIFT (0u) +#define RCAN_RSCAN0RFPCTR2_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR2_RFPC_SHIFT (0u) +#define RCAN_RSCAN0RFPCTR3_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR3_RFPC_SHIFT (0u) +#define RCAN_RSCAN0RFPCTR4_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR4_RFPC_SHIFT (0u) +#define RCAN_RSCAN0RFPCTR5_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR5_RFPC_SHIFT (0u) +#define RCAN_RSCAN0RFPCTR6_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR6_RFPC_SHIFT (0u) +#define RCAN_RSCAN0RFPCTR7_RFPC (0x000000FFu) +#define RCAN_RSCAN0RFPCTR7_RFPC_SHIFT (0u) +#define RCAN_RSCAN0CFCC0_CFE (0x00000001u) +#define RCAN_RSCAN0CFCC0_CFE_SHIFT (0u) +#define RCAN_RSCAN0CFCC0_CFRXIE (0x00000002u) +#define RCAN_RSCAN0CFCC0_CFRXIE_SHIFT (1u) +#define RCAN_RSCAN0CFCC0_CFTXIE (0x00000004u) +#define RCAN_RSCAN0CFCC0_CFTXIE_SHIFT (2u) +#define RCAN_RSCAN0CFCC0_CFDC (0x00000700u) +#define RCAN_RSCAN0CFCC0_CFDC_SHIFT (8u) +#define RCAN_RSCAN0CFCC0_CFIM (0x00001000u) +#define RCAN_RSCAN0CFCC0_CFIM_SHIFT (12u) +#define RCAN_RSCAN0CFCC0_CFIGCV (0x0000E000u) +#define RCAN_RSCAN0CFCC0_CFIGCV_SHIFT (13u) +#define RCAN_RSCAN0CFCC0_CFM (0x00030000u) +#define RCAN_RSCAN0CFCC0_CFM_SHIFT (16u) +#define RCAN_RSCAN0CFCC0_CFITSS (0x00040000u) +#define RCAN_RSCAN0CFCC0_CFITSS_SHIFT (18u) +#define RCAN_RSCAN0CFCC0_CFITR (0x00080000u) +#define RCAN_RSCAN0CFCC0_CFITR_SHIFT (19u) +#define RCAN_RSCAN0CFCC0_CFTML (0x00F00000u) +#define RCAN_RSCAN0CFCC0_CFTML_SHIFT (20u) +#define RCAN_RSCAN0CFCC0_CFITT (0xFF000000u) +#define RCAN_RSCAN0CFCC0_CFITT_SHIFT (24u) +#define RCAN_RSCAN0CFCC1_CFE (0x00000001u) +#define RCAN_RSCAN0CFCC1_CFE_SHIFT (0u) +#define RCAN_RSCAN0CFCC1_CFRXIE (0x00000002u) +#define RCAN_RSCAN0CFCC1_CFRXIE_SHIFT (1u) +#define RCAN_RSCAN0CFCC1_CFTXIE (0x00000004u) +#define RCAN_RSCAN0CFCC1_CFTXIE_SHIFT (2u) +#define RCAN_RSCAN0CFCC1_CFDC (0x00000700u) +#define RCAN_RSCAN0CFCC1_CFDC_SHIFT (8u) +#define RCAN_RSCAN0CFCC1_CFIM (0x00001000u) +#define RCAN_RSCAN0CFCC1_CFIM_SHIFT (12u) +#define RCAN_RSCAN0CFCC1_CFIGCV (0x0000E000u) +#define RCAN_RSCAN0CFCC1_CFIGCV_SHIFT (13u) +#define RCAN_RSCAN0CFCC1_CFM (0x00030000u) +#define RCAN_RSCAN0CFCC1_CFM_SHIFT (16u) +#define RCAN_RSCAN0CFCC1_CFITSS (0x00040000u) +#define RCAN_RSCAN0CFCC1_CFITSS_SHIFT (18u) +#define RCAN_RSCAN0CFCC1_CFITR (0x00080000u) +#define RCAN_RSCAN0CFCC1_CFITR_SHIFT (19u) +#define RCAN_RSCAN0CFCC1_CFTML (0x00F00000u) +#define RCAN_RSCAN0CFCC1_CFTML_SHIFT (20u) +#define RCAN_RSCAN0CFCC1_CFITT (0xFF000000u) +#define RCAN_RSCAN0CFCC1_CFITT_SHIFT (24u) +#define RCAN_RSCAN0CFCC2_CFE (0x00000001u) +#define RCAN_RSCAN0CFCC2_CFE_SHIFT (0u) +#define RCAN_RSCAN0CFCC2_CFRXIE (0x00000002u) +#define RCAN_RSCAN0CFCC2_CFRXIE_SHIFT (1u) +#define RCAN_RSCAN0CFCC2_CFTXIE (0x00000004u) +#define RCAN_RSCAN0CFCC2_CFTXIE_SHIFT (2u) +#define RCAN_RSCAN0CFCC2_CFDC (0x00000700u) +#define RCAN_RSCAN0CFCC2_CFDC_SHIFT (8u) +#define RCAN_RSCAN0CFCC2_CFIM (0x00001000u) +#define RCAN_RSCAN0CFCC2_CFIM_SHIFT (12u) +#define RCAN_RSCAN0CFCC2_CFIGCV (0x0000E000u) +#define RCAN_RSCAN0CFCC2_CFIGCV_SHIFT (13u) +#define RCAN_RSCAN0CFCC2_CFM (0x00030000u) +#define RCAN_RSCAN0CFCC2_CFM_SHIFT (16u) +#define RCAN_RSCAN0CFCC2_CFITSS (0x00040000u) +#define RCAN_RSCAN0CFCC2_CFITSS_SHIFT (18u) +#define RCAN_RSCAN0CFCC2_CFITR (0x00080000u) +#define RCAN_RSCAN0CFCC2_CFITR_SHIFT (19u) +#define RCAN_RSCAN0CFCC2_CFTML (0x00F00000u) +#define RCAN_RSCAN0CFCC2_CFTML_SHIFT (20u) +#define RCAN_RSCAN0CFCC2_CFITT (0xFF000000u) +#define RCAN_RSCAN0CFCC2_CFITT_SHIFT (24u) +#define RCAN_RSCAN0CFCC3_CFE (0x00000001u) +#define RCAN_RSCAN0CFCC3_CFE_SHIFT (0u) +#define RCAN_RSCAN0CFCC3_CFRXIE (0x00000002u) +#define RCAN_RSCAN0CFCC3_CFRXIE_SHIFT (1u) +#define RCAN_RSCAN0CFCC3_CFTXIE (0x00000004u) +#define RCAN_RSCAN0CFCC3_CFTXIE_SHIFT (2u) +#define RCAN_RSCAN0CFCC3_CFDC (0x00000700u) +#define RCAN_RSCAN0CFCC3_CFDC_SHIFT (8u) +#define RCAN_RSCAN0CFCC3_CFIM (0x00001000u) +#define RCAN_RSCAN0CFCC3_CFIM_SHIFT (12u) +#define RCAN_RSCAN0CFCC3_CFIGCV (0x0000E000u) +#define RCAN_RSCAN0CFCC3_CFIGCV_SHIFT (13u) +#define RCAN_RSCAN0CFCC3_CFM (0x00030000u) +#define RCAN_RSCAN0CFCC3_CFM_SHIFT (16u) +#define RCAN_RSCAN0CFCC3_CFITSS (0x00040000u) +#define RCAN_RSCAN0CFCC3_CFITSS_SHIFT (18u) +#define RCAN_RSCAN0CFCC3_CFITR (0x00080000u) +#define RCAN_RSCAN0CFCC3_CFITR_SHIFT (19u) +#define RCAN_RSCAN0CFCC3_CFTML (0x00F00000u) +#define RCAN_RSCAN0CFCC3_CFTML_SHIFT (20u) +#define RCAN_RSCAN0CFCC3_CFITT (0xFF000000u) +#define RCAN_RSCAN0CFCC3_CFITT_SHIFT (24u) +#define RCAN_RSCAN0CFCC4_CFE (0x00000001u) +#define RCAN_RSCAN0CFCC4_CFE_SHIFT (0u) +#define RCAN_RSCAN0CFCC4_CFRXIE (0x00000002u) +#define RCAN_RSCAN0CFCC4_CFRXIE_SHIFT (1u) +#define RCAN_RSCAN0CFCC4_CFTXIE (0x00000004u) +#define RCAN_RSCAN0CFCC4_CFTXIE_SHIFT (2u) +#define RCAN_RSCAN0CFCC4_CFDC (0x00000700u) +#define RCAN_RSCAN0CFCC4_CFDC_SHIFT (8u) +#define RCAN_RSCAN0CFCC4_CFIM (0x00001000u) +#define RCAN_RSCAN0CFCC4_CFIM_SHIFT (12u) +#define RCAN_RSCAN0CFCC4_CFIGCV (0x0000E000u) +#define RCAN_RSCAN0CFCC4_CFIGCV_SHIFT (13u) +#define RCAN_RSCAN0CFCC4_CFM (0x00030000u) +#define RCAN_RSCAN0CFCC4_CFM_SHIFT (16u) +#define RCAN_RSCAN0CFCC4_CFITSS (0x00040000u) +#define RCAN_RSCAN0CFCC4_CFITSS_SHIFT (18u) +#define RCAN_RSCAN0CFCC4_CFITR (0x00080000u) +#define RCAN_RSCAN0CFCC4_CFITR_SHIFT (19u) +#define RCAN_RSCAN0CFCC4_CFTML (0x00F00000u) +#define RCAN_RSCAN0CFCC4_CFTML_SHIFT (20u) +#define RCAN_RSCAN0CFCC4_CFITT (0xFF000000u) +#define RCAN_RSCAN0CFCC4_CFITT_SHIFT (24u) +#define RCAN_RSCAN0CFCC5_CFE (0x00000001u) +#define RCAN_RSCAN0CFCC5_CFE_SHIFT (0u) +#define RCAN_RSCAN0CFCC5_CFRXIE (0x00000002u) +#define RCAN_RSCAN0CFCC5_CFRXIE_SHIFT (1u) +#define RCAN_RSCAN0CFCC5_CFTXIE (0x00000004u) +#define RCAN_RSCAN0CFCC5_CFTXIE_SHIFT (2u) +#define RCAN_RSCAN0CFCC5_CFDC (0x00000700u) +#define RCAN_RSCAN0CFCC5_CFDC_SHIFT (8u) +#define RCAN_RSCAN0CFCC5_CFIM (0x00001000u) +#define RCAN_RSCAN0CFCC5_CFIM_SHIFT (12u) +#define RCAN_RSCAN0CFCC5_CFIGCV (0x0000E000u) +#define RCAN_RSCAN0CFCC5_CFIGCV_SHIFT (13u) +#define RCAN_RSCAN0CFCC5_CFM (0x00030000u) +#define RCAN_RSCAN0CFCC5_CFM_SHIFT (16u) +#define RCAN_RSCAN0CFCC5_CFITSS (0x00040000u) +#define RCAN_RSCAN0CFCC5_CFITSS_SHIFT (18u) +#define RCAN_RSCAN0CFCC5_CFITR (0x00080000u) +#define RCAN_RSCAN0CFCC5_CFITR_SHIFT (19u) +#define RCAN_RSCAN0CFCC5_CFTML (0x00F00000u) +#define RCAN_RSCAN0CFCC5_CFTML_SHIFT (20u) +#define RCAN_RSCAN0CFCC5_CFITT (0xFF000000u) +#define RCAN_RSCAN0CFCC5_CFITT_SHIFT (24u) +#define RCAN_RSCAN0CFSTS0_CFEMP (0x00000001u) +#define RCAN_RSCAN0CFSTS0_CFEMP_SHIFT (0u) +#define RCAN_RSCAN0CFSTS0_CFFLL (0x00000002u) +#define RCAN_RSCAN0CFSTS0_CFFLL_SHIFT (1u) +#define RCAN_RSCAN0CFSTS0_CFMLT (0x00000004u) +#define RCAN_RSCAN0CFSTS0_CFMLT_SHIFT (2u) +#define RCAN_RSCAN0CFSTS0_CFRXIF (0x00000008u) +#define RCAN_RSCAN0CFSTS0_CFRXIF_SHIFT (3u) +#define RCAN_RSCAN0CFSTS0_CFTXIF (0x00000010u) +#define RCAN_RSCAN0CFSTS0_CFTXIF_SHIFT (4u) +#define RCAN_RSCAN0CFSTS0_CFMC (0x0000FF00u) +#define RCAN_RSCAN0CFSTS0_CFMC_SHIFT (8u) +#define RCAN_RSCAN0CFSTS1_CFEMP (0x00000001u) +#define RCAN_RSCAN0CFSTS1_CFEMP_SHIFT (0u) +#define RCAN_RSCAN0CFSTS1_CFFLL (0x00000002u) +#define RCAN_RSCAN0CFSTS1_CFFLL_SHIFT (1u) +#define RCAN_RSCAN0CFSTS1_CFMLT (0x00000004u) +#define RCAN_RSCAN0CFSTS1_CFMLT_SHIFT (2u) +#define RCAN_RSCAN0CFSTS1_CFRXIF (0x00000008u) +#define RCAN_RSCAN0CFSTS1_CFRXIF_SHIFT (3u) +#define RCAN_RSCAN0CFSTS1_CFTXIF (0x00000010u) +#define RCAN_RSCAN0CFSTS1_CFTXIF_SHIFT (4u) +#define RCAN_RSCAN0CFSTS1_CFMC (0x0000FF00u) +#define RCAN_RSCAN0CFSTS1_CFMC_SHIFT (8u) +#define RCAN_RSCAN0CFSTS2_CFEMP (0x00000001u) +#define RCAN_RSCAN0CFSTS2_CFEMP_SHIFT (0u) +#define RCAN_RSCAN0CFSTS2_CFFLL (0x00000002u) +#define RCAN_RSCAN0CFSTS2_CFFLL_SHIFT (1u) +#define RCAN_RSCAN0CFSTS2_CFMLT (0x00000004u) +#define RCAN_RSCAN0CFSTS2_CFMLT_SHIFT (2u) +#define RCAN_RSCAN0CFSTS2_CFRXIF (0x00000008u) +#define RCAN_RSCAN0CFSTS2_CFRXIF_SHIFT (3u) +#define RCAN_RSCAN0CFSTS2_CFTXIF (0x00000010u) +#define RCAN_RSCAN0CFSTS2_CFTXIF_SHIFT (4u) +#define RCAN_RSCAN0CFSTS2_CFMC (0x0000FF00u) +#define RCAN_RSCAN0CFSTS2_CFMC_SHIFT (8u) +#define RCAN_RSCAN0CFSTS3_CFEMP (0x00000001u) +#define RCAN_RSCAN0CFSTS3_CFEMP_SHIFT (0u) +#define RCAN_RSCAN0CFSTS3_CFFLL (0x00000002u) +#define RCAN_RSCAN0CFSTS3_CFFLL_SHIFT (1u) +#define RCAN_RSCAN0CFSTS3_CFMLT (0x00000004u) +#define RCAN_RSCAN0CFSTS3_CFMLT_SHIFT (2u) +#define RCAN_RSCAN0CFSTS3_CFRXIF (0x00000008u) +#define RCAN_RSCAN0CFSTS3_CFRXIF_SHIFT (3u) +#define RCAN_RSCAN0CFSTS3_CFTXIF (0x00000010u) +#define RCAN_RSCAN0CFSTS3_CFTXIF_SHIFT (4u) +#define RCAN_RSCAN0CFSTS3_CFMC (0x0000FF00u) +#define RCAN_RSCAN0CFSTS3_CFMC_SHIFT (8u) +#define RCAN_RSCAN0CFSTS4_CFEMP (0x00000001u) +#define RCAN_RSCAN0CFSTS4_CFEMP_SHIFT (0u) +#define RCAN_RSCAN0CFSTS4_CFFLL (0x00000002u) +#define RCAN_RSCAN0CFSTS4_CFFLL_SHIFT (1u) +#define RCAN_RSCAN0CFSTS4_CFMLT (0x00000004u) +#define RCAN_RSCAN0CFSTS4_CFMLT_SHIFT (2u) +#define RCAN_RSCAN0CFSTS4_CFRXIF (0x00000008u) +#define RCAN_RSCAN0CFSTS4_CFRXIF_SHIFT (3u) +#define RCAN_RSCAN0CFSTS4_CFTXIF (0x00000010u) +#define RCAN_RSCAN0CFSTS4_CFTXIF_SHIFT (4u) +#define RCAN_RSCAN0CFSTS4_CFMC (0x0000FF00u) +#define RCAN_RSCAN0CFSTS4_CFMC_SHIFT (8u) +#define RCAN_RSCAN0CFSTS5_CFEMP (0x00000001u) +#define RCAN_RSCAN0CFSTS5_CFEMP_SHIFT (0u) +#define RCAN_RSCAN0CFSTS5_CFFLL (0x00000002u) +#define RCAN_RSCAN0CFSTS5_CFFLL_SHIFT (1u) +#define RCAN_RSCAN0CFSTS5_CFMLT (0x00000004u) +#define RCAN_RSCAN0CFSTS5_CFMLT_SHIFT (2u) +#define RCAN_RSCAN0CFSTS5_CFRXIF (0x00000008u) +#define RCAN_RSCAN0CFSTS5_CFRXIF_SHIFT (3u) +#define RCAN_RSCAN0CFSTS5_CFTXIF (0x00000010u) +#define RCAN_RSCAN0CFSTS5_CFTXIF_SHIFT (4u) +#define RCAN_RSCAN0CFSTS5_CFMC (0x0000FF00u) +#define RCAN_RSCAN0CFSTS5_CFMC_SHIFT (8u) +#define RCAN_RSCAN0CFPCTR0_CFPC (0x000000FFu) +#define RCAN_RSCAN0CFPCTR0_CFPC_SHIFT (0u) +#define RCAN_RSCAN0CFPCTR1_CFPC (0x000000FFu) +#define RCAN_RSCAN0CFPCTR1_CFPC_SHIFT (0u) +#define RCAN_RSCAN0CFPCTR2_CFPC (0x000000FFu) +#define RCAN_RSCAN0CFPCTR2_CFPC_SHIFT (0u) +#define RCAN_RSCAN0CFPCTR3_CFPC (0x000000FFu) +#define RCAN_RSCAN0CFPCTR3_CFPC_SHIFT (0u) +#define RCAN_RSCAN0CFPCTR4_CFPC (0x000000FFu) +#define RCAN_RSCAN0CFPCTR4_CFPC_SHIFT (0u) +#define RCAN_RSCAN0CFPCTR5_CFPC (0x000000FFu) +#define RCAN_RSCAN0CFPCTR5_CFPC_SHIFT (0u) +#define RCAN_RSCAN0FESTS_RF0EMP (0x00000001u) +#define RCAN_RSCAN0FESTS_RF0EMP_SHIFT (0u) +#define RCAN_RSCAN0FESTS_RF1EMP (0x00000002u) +#define RCAN_RSCAN0FESTS_RF1EMP_SHIFT (1u) +#define RCAN_RSCAN0FESTS_RF2EMP (0x00000004u) +#define RCAN_RSCAN0FESTS_RF2EMP_SHIFT (2u) +#define RCAN_RSCAN0FESTS_RF3EMP (0x00000008u) +#define RCAN_RSCAN0FESTS_RF3EMP_SHIFT (3u) +#define RCAN_RSCAN0FESTS_RF4EMP (0x00000010u) +#define RCAN_RSCAN0FESTS_RF4EMP_SHIFT (4u) +#define RCAN_RSCAN0FESTS_RF5EMP (0x00000020u) +#define RCAN_RSCAN0FESTS_RF5EMP_SHIFT (5u) +#define RCAN_RSCAN0FESTS_RF6EMP (0x00000040u) +#define RCAN_RSCAN0FESTS_RF6EMP_SHIFT (6u) +#define RCAN_RSCAN0FESTS_RF7EMP (0x00000080u) +#define RCAN_RSCAN0FESTS_RF7EMP_SHIFT (7u) +#define RCAN_RSCAN0FESTS_CF0EMP (0x00000100u) +#define RCAN_RSCAN0FESTS_CF0EMP_SHIFT (8u) +#define RCAN_RSCAN0FESTS_CF1EMP (0x00000200u) +#define RCAN_RSCAN0FESTS_CF1EMP_SHIFT (9u) +#define RCAN_RSCAN0FESTS_CF2EMP (0x00000400u) +#define RCAN_RSCAN0FESTS_CF2EMP_SHIFT (10u) +#define RCAN_RSCAN0FESTS_CF3EMP (0x00000800u) +#define RCAN_RSCAN0FESTS_CF3EMP_SHIFT (11u) +#define RCAN_RSCAN0FESTS_CF4EMP (0x00001000u) +#define RCAN_RSCAN0FESTS_CF4EMP_SHIFT (12u) +#define RCAN_RSCAN0FESTS_CF5EMP (0x00002000u) +#define RCAN_RSCAN0FESTS_CF5EMP_SHIFT (13u) +#define RCAN_RSCAN0FFSTS_RF0FLL (0x00000001u) +#define RCAN_RSCAN0FFSTS_RF0FLL_SHIFT (0u) +#define RCAN_RSCAN0FFSTS_RF1FLL (0x00000002u) +#define RCAN_RSCAN0FFSTS_RF1FLL_SHIFT (1u) +#define RCAN_RSCAN0FFSTS_RF2FLL (0x00000004u) +#define RCAN_RSCAN0FFSTS_RF2FLL_SHIFT (2u) +#define RCAN_RSCAN0FFSTS_RF3FLL (0x00000008u) +#define RCAN_RSCAN0FFSTS_RF3FLL_SHIFT (3u) +#define RCAN_RSCAN0FFSTS_RF4FLL (0x00000010u) +#define RCAN_RSCAN0FFSTS_RF4FLL_SHIFT (4u) +#define RCAN_RSCAN0FFSTS_RF5FLL (0x00000020u) +#define RCAN_RSCAN0FFSTS_RF5FLL_SHIFT (5u) +#define RCAN_RSCAN0FFSTS_RF6FLL (0x00000040u) +#define RCAN_RSCAN0FFSTS_RF6FLL_SHIFT (6u) +#define RCAN_RSCAN0FFSTS_RF7FLL (0x00000080u) +#define RCAN_RSCAN0FFSTS_RF7FLL_SHIFT (7u) +#define RCAN_RSCAN0FFSTS_CF0FLL (0x00000100u) +#define RCAN_RSCAN0FFSTS_CF0FLL_SHIFT (8u) +#define RCAN_RSCAN0FFSTS_CF1FLL (0x00000200u) +#define RCAN_RSCAN0FFSTS_CF1FLL_SHIFT (9u) +#define RCAN_RSCAN0FFSTS_CF2FLL (0x00000400u) +#define RCAN_RSCAN0FFSTS_CF2FLL_SHIFT (10u) +#define RCAN_RSCAN0FFSTS_CF3FLL (0x00000800u) +#define RCAN_RSCAN0FFSTS_CF3FLL_SHIFT (11u) +#define RCAN_RSCAN0FFSTS_CF4FLL (0x00001000u) +#define RCAN_RSCAN0FFSTS_CF4FLL_SHIFT (12u) +#define RCAN_RSCAN0FFSTS_CF5FLL (0x00002000u) +#define RCAN_RSCAN0FFSTS_CF5FLL_SHIFT (13u) +#define RCAN_RSCAN0FMSTS_RF0MLT (0x00000001u) +#define RCAN_RSCAN0FMSTS_RF0MLT_SHIFT (0u) +#define RCAN_RSCAN0FMSTS_RF1MLT (0x00000002u) +#define RCAN_RSCAN0FMSTS_RF1MLT_SHIFT (1u) +#define RCAN_RSCAN0FMSTS_RF2MLT (0x00000004u) +#define RCAN_RSCAN0FMSTS_RF2MLT_SHIFT (2u) +#define RCAN_RSCAN0FMSTS_RF3MLT (0x00000008u) +#define RCAN_RSCAN0FMSTS_RF3MLT_SHIFT (3u) +#define RCAN_RSCAN0FMSTS_RF4MLT (0x00000010u) +#define RCAN_RSCAN0FMSTS_RF4MLT_SHIFT (4u) +#define RCAN_RSCAN0FMSTS_RF5MLT (0x00000020u) +#define RCAN_RSCAN0FMSTS_RF5MLT_SHIFT (5u) +#define RCAN_RSCAN0FMSTS_RF6MLT (0x00000040u) +#define RCAN_RSCAN0FMSTS_RF6MLT_SHIFT (6u) +#define RCAN_RSCAN0FMSTS_RF7MLT (0x00000080u) +#define RCAN_RSCAN0FMSTS_RF7MLT_SHIFT (7u) +#define RCAN_RSCAN0FMSTS_CF0MLT (0x00000100u) +#define RCAN_RSCAN0FMSTS_CF0MLT_SHIFT (8u) +#define RCAN_RSCAN0FMSTS_CF1MLT (0x00000200u) +#define RCAN_RSCAN0FMSTS_CF1MLT_SHIFT (9u) +#define RCAN_RSCAN0FMSTS_CF2MLT (0x00000400u) +#define RCAN_RSCAN0FMSTS_CF2MLT_SHIFT (10u) +#define RCAN_RSCAN0FMSTS_CF3MLT (0x00000800u) +#define RCAN_RSCAN0FMSTS_CF3MLT_SHIFT (11u) +#define RCAN_RSCAN0FMSTS_CF4MLT (0x00001000u) +#define RCAN_RSCAN0FMSTS_CF4MLT_SHIFT (12u) +#define RCAN_RSCAN0FMSTS_CF5MLT (0x00002000u) +#define RCAN_RSCAN0FMSTS_CF5MLT_SHIFT (13u) +#define RCAN_RSCAN0RFISTS_RF0IF (0x00000001u) +#define RCAN_RSCAN0RFISTS_RF0IF_SHIFT (0u) +#define RCAN_RSCAN0RFISTS_RF1IF (0x00000002u) +#define RCAN_RSCAN0RFISTS_RF1IF_SHIFT (1u) +#define RCAN_RSCAN0RFISTS_RF2IF (0x00000004u) +#define RCAN_RSCAN0RFISTS_RF2IF_SHIFT (2u) +#define RCAN_RSCAN0RFISTS_RF3IF (0x00000008u) +#define RCAN_RSCAN0RFISTS_RF3IF_SHIFT (3u) +#define RCAN_RSCAN0RFISTS_RF4IF (0x00000010u) +#define RCAN_RSCAN0RFISTS_RF4IF_SHIFT (4u) +#define RCAN_RSCAN0RFISTS_RF5IF (0x00000020u) +#define RCAN_RSCAN0RFISTS_RF5IF_SHIFT (5u) +#define RCAN_RSCAN0RFISTS_RF6IF (0x00000040u) +#define RCAN_RSCAN0RFISTS_RF6IF_SHIFT (6u) +#define RCAN_RSCAN0RFISTS_RF7IF (0x00000080u) +#define RCAN_RSCAN0RFISTS_RF7IF_SHIFT (7u) +#define RCAN_RSCAN0CFRISTS_CF0RXIF (0x00000001u) +#define RCAN_RSCAN0CFRISTS_CF0RXIF_SHIFT (0u) +#define RCAN_RSCAN0CFRISTS_CF1RXIF (0x00000002u) +#define RCAN_RSCAN0CFRISTS_CF1RXIF_SHIFT (1u) +#define RCAN_RSCAN0CFRISTS_CF2RXIF (0x00000004u) +#define RCAN_RSCAN0CFRISTS_CF2RXIF_SHIFT (2u) +#define RCAN_RSCAN0CFRISTS_CF3RXIF (0x00000008u) +#define RCAN_RSCAN0CFRISTS_CF3RXIF_SHIFT (3u) +#define RCAN_RSCAN0CFRISTS_CF4RXIF (0x00000010u) +#define RCAN_RSCAN0CFRISTS_CF4RXIF_SHIFT (4u) +#define RCAN_RSCAN0CFRISTS_CF5RXIF (0x00000020u) +#define RCAN_RSCAN0CFRISTS_CF5RXIF_SHIFT (5u) +#define RCAN_RSCAN0CFTISTS_CF0TXIF (0x00000001u) +#define RCAN_RSCAN0CFTISTS_CF0TXIF_SHIFT (0u) +#define RCAN_RSCAN0CFTISTS_CF1TXIF (0x00000002u) +#define RCAN_RSCAN0CFTISTS_CF1TXIF_SHIFT (1u) +#define RCAN_RSCAN0CFTISTS_CF2TXIF (0x00000004u) +#define RCAN_RSCAN0CFTISTS_CF2TXIF_SHIFT (2u) +#define RCAN_RSCAN0CFTISTS_CF3TXIF (0x00000008u) +#define RCAN_RSCAN0CFTISTS_CF3TXIF_SHIFT (3u) +#define RCAN_RSCAN0CFTISTS_CF4TXIF (0x00000010u) +#define RCAN_RSCAN0CFTISTS_CF4TXIF_SHIFT (4u) +#define RCAN_RSCAN0CFTISTS_CF5TXIF (0x00000020u) +#define RCAN_RSCAN0CFTISTS_CF5TXIF_SHIFT (5u) +#define RCAN_RSCAN0TMC0_TMTR (0x01u) +#define RCAN_RSCAN0TMC0_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC0_TMTAR (0x02u) +#define RCAN_RSCAN0TMC0_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC0_TMOM (0x04u) +#define RCAN_RSCAN0TMC0_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC1_TMTR (0x01u) +#define RCAN_RSCAN0TMC1_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC1_TMTAR (0x02u) +#define RCAN_RSCAN0TMC1_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC1_TMOM (0x04u) +#define RCAN_RSCAN0TMC1_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC2_TMTR (0x01u) +#define RCAN_RSCAN0TMC2_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC2_TMTAR (0x02u) +#define RCAN_RSCAN0TMC2_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC2_TMOM (0x04u) +#define RCAN_RSCAN0TMC2_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC3_TMTR (0x01u) +#define RCAN_RSCAN0TMC3_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC3_TMTAR (0x02u) +#define RCAN_RSCAN0TMC3_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC3_TMOM (0x04u) +#define RCAN_RSCAN0TMC3_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC4_TMTR (0x01u) +#define RCAN_RSCAN0TMC4_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC4_TMTAR (0x02u) +#define RCAN_RSCAN0TMC4_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC4_TMOM (0x04u) +#define RCAN_RSCAN0TMC4_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC5_TMTR (0x01u) +#define RCAN_RSCAN0TMC5_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC5_TMTAR (0x02u) +#define RCAN_RSCAN0TMC5_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC5_TMOM (0x04u) +#define RCAN_RSCAN0TMC5_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC6_TMTR (0x01u) +#define RCAN_RSCAN0TMC6_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC6_TMTAR (0x02u) +#define RCAN_RSCAN0TMC6_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC6_TMOM (0x04u) +#define RCAN_RSCAN0TMC6_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC7_TMTR (0x01u) +#define RCAN_RSCAN0TMC7_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC7_TMTAR (0x02u) +#define RCAN_RSCAN0TMC7_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC7_TMOM (0x04u) +#define RCAN_RSCAN0TMC7_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC8_TMTR (0x01u) +#define RCAN_RSCAN0TMC8_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC8_TMTAR (0x02u) +#define RCAN_RSCAN0TMC8_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC8_TMOM (0x04u) +#define RCAN_RSCAN0TMC8_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC9_TMTR (0x01u) +#define RCAN_RSCAN0TMC9_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC9_TMTAR (0x02u) +#define RCAN_RSCAN0TMC9_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC9_TMOM (0x04u) +#define RCAN_RSCAN0TMC9_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC10_TMTR (0x01u) +#define RCAN_RSCAN0TMC10_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC10_TMTAR (0x02u) +#define RCAN_RSCAN0TMC10_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC10_TMOM (0x04u) +#define RCAN_RSCAN0TMC10_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC11_TMTR (0x01u) +#define RCAN_RSCAN0TMC11_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC11_TMTAR (0x02u) +#define RCAN_RSCAN0TMC11_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC11_TMOM (0x04u) +#define RCAN_RSCAN0TMC11_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC12_TMTR (0x01u) +#define RCAN_RSCAN0TMC12_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC12_TMTAR (0x02u) +#define RCAN_RSCAN0TMC12_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC12_TMOM (0x04u) +#define RCAN_RSCAN0TMC12_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC13_TMTR (0x01u) +#define RCAN_RSCAN0TMC13_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC13_TMTAR (0x02u) +#define RCAN_RSCAN0TMC13_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC13_TMOM (0x04u) +#define RCAN_RSCAN0TMC13_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC14_TMTR (0x01u) +#define RCAN_RSCAN0TMC14_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC14_TMTAR (0x02u) +#define RCAN_RSCAN0TMC14_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC14_TMOM (0x04u) +#define RCAN_RSCAN0TMC14_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC15_TMTR (0x01u) +#define RCAN_RSCAN0TMC15_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC15_TMTAR (0x02u) +#define RCAN_RSCAN0TMC15_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC15_TMOM (0x04u) +#define RCAN_RSCAN0TMC15_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC16_TMTR (0x01u) +#define RCAN_RSCAN0TMC16_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC16_TMTAR (0x02u) +#define RCAN_RSCAN0TMC16_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC16_TMOM (0x04u) +#define RCAN_RSCAN0TMC16_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC17_TMTR (0x01u) +#define RCAN_RSCAN0TMC17_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC17_TMTAR (0x02u) +#define RCAN_RSCAN0TMC17_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC17_TMOM (0x04u) +#define RCAN_RSCAN0TMC17_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC18_TMTR (0x01u) +#define RCAN_RSCAN0TMC18_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC18_TMTAR (0x02u) +#define RCAN_RSCAN0TMC18_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC18_TMOM (0x04u) +#define RCAN_RSCAN0TMC18_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC19_TMTR (0x01u) +#define RCAN_RSCAN0TMC19_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC19_TMTAR (0x02u) +#define RCAN_RSCAN0TMC19_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC19_TMOM (0x04u) +#define RCAN_RSCAN0TMC19_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC20_TMTR (0x01u) +#define RCAN_RSCAN0TMC20_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC20_TMTAR (0x02u) +#define RCAN_RSCAN0TMC20_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC20_TMOM (0x04u) +#define RCAN_RSCAN0TMC20_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC21_TMTR (0x01u) +#define RCAN_RSCAN0TMC21_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC21_TMTAR (0x02u) +#define RCAN_RSCAN0TMC21_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC21_TMOM (0x04u) +#define RCAN_RSCAN0TMC21_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC22_TMTR (0x01u) +#define RCAN_RSCAN0TMC22_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC22_TMTAR (0x02u) +#define RCAN_RSCAN0TMC22_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC22_TMOM (0x04u) +#define RCAN_RSCAN0TMC22_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC23_TMTR (0x01u) +#define RCAN_RSCAN0TMC23_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC23_TMTAR (0x02u) +#define RCAN_RSCAN0TMC23_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC23_TMOM (0x04u) +#define RCAN_RSCAN0TMC23_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC24_TMTR (0x01u) +#define RCAN_RSCAN0TMC24_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC24_TMTAR (0x02u) +#define RCAN_RSCAN0TMC24_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC24_TMOM (0x04u) +#define RCAN_RSCAN0TMC24_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC25_TMTR (0x01u) +#define RCAN_RSCAN0TMC25_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC25_TMTAR (0x02u) +#define RCAN_RSCAN0TMC25_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC25_TMOM (0x04u) +#define RCAN_RSCAN0TMC25_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC26_TMTR (0x01u) +#define RCAN_RSCAN0TMC26_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC26_TMTAR (0x02u) +#define RCAN_RSCAN0TMC26_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC26_TMOM (0x04u) +#define RCAN_RSCAN0TMC26_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC27_TMTR (0x01u) +#define RCAN_RSCAN0TMC27_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC27_TMTAR (0x02u) +#define RCAN_RSCAN0TMC27_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC27_TMOM (0x04u) +#define RCAN_RSCAN0TMC27_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC28_TMTR (0x01u) +#define RCAN_RSCAN0TMC28_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC28_TMTAR (0x02u) +#define RCAN_RSCAN0TMC28_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC28_TMOM (0x04u) +#define RCAN_RSCAN0TMC28_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC29_TMTR (0x01u) +#define RCAN_RSCAN0TMC29_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC29_TMTAR (0x02u) +#define RCAN_RSCAN0TMC29_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC29_TMOM (0x04u) +#define RCAN_RSCAN0TMC29_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC30_TMTR (0x01u) +#define RCAN_RSCAN0TMC30_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC30_TMTAR (0x02u) +#define RCAN_RSCAN0TMC30_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC30_TMOM (0x04u) +#define RCAN_RSCAN0TMC30_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMC31_TMTR (0x01u) +#define RCAN_RSCAN0TMC31_TMTR_SHIFT (0u) +#define RCAN_RSCAN0TMC31_TMTAR (0x02u) +#define RCAN_RSCAN0TMC31_TMTAR_SHIFT (1u) +#define RCAN_RSCAN0TMC31_TMOM (0x04u) +#define RCAN_RSCAN0TMC31_TMOM_SHIFT (2u) +#define RCAN_RSCAN0TMSTS0_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS0_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS0_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS0_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS0_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS0_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS0_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS0_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS1_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS1_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS1_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS1_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS1_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS1_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS1_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS1_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS2_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS2_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS2_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS2_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS2_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS2_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS2_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS2_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS3_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS3_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS3_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS3_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS3_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS3_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS3_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS3_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS4_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS4_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS4_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS4_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS4_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS4_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS4_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS4_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS5_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS5_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS5_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS5_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS5_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS5_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS5_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS5_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS6_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS6_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS6_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS6_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS6_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS6_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS6_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS6_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS7_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS7_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS7_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS7_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS7_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS7_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS7_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS7_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS8_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS8_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS8_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS8_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS8_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS8_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS8_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS8_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS9_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS9_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS9_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS9_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS9_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS9_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS9_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS9_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS10_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS10_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS10_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS10_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS10_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS10_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS10_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS10_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS11_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS11_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS11_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS11_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS11_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS11_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS11_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS11_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS12_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS12_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS12_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS12_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS12_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS12_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS12_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS12_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS13_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS13_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS13_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS13_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS13_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS13_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS13_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS13_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS14_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS14_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS14_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS14_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS14_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS14_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS14_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS14_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS15_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS15_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS15_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS15_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS15_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS15_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS15_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS15_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS16_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS16_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS16_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS16_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS16_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS16_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS16_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS16_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS17_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS17_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS17_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS17_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS17_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS17_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS17_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS17_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS18_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS18_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS18_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS18_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS18_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS18_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS18_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS18_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS19_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS19_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS19_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS19_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS19_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS19_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS19_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS19_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS20_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS20_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS20_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS20_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS20_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS20_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS20_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS20_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS21_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS21_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS21_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS21_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS21_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS21_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS21_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS21_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS22_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS22_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS22_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS22_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS22_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS22_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS22_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS22_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS23_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS23_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS23_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS23_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS23_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS23_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS23_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS23_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS24_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS24_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS24_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS24_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS24_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS24_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS24_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS24_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS25_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS25_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS25_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS25_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS25_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS25_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS25_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS25_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS26_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS26_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS26_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS26_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS26_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS26_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS26_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS26_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS27_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS27_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS27_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS27_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS27_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS27_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS27_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS27_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS28_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS28_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS28_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS28_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS28_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS28_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS28_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS28_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS29_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS29_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS29_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS29_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS29_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS29_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS29_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS29_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS30_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS30_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS30_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS30_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS30_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS30_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS30_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS30_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMSTS31_TMTSTS (0x01u) +#define RCAN_RSCAN0TMSTS31_TMTSTS_SHIFT (0u) +#define RCAN_RSCAN0TMSTS31_TMTRF (0x06u) +#define RCAN_RSCAN0TMSTS31_TMTRF_SHIFT (1u) +#define RCAN_RSCAN0TMSTS31_TMTRM (0x08u) +#define RCAN_RSCAN0TMSTS31_TMTRM_SHIFT (3u) +#define RCAN_RSCAN0TMSTS31_TMTARM (0x10u) +#define RCAN_RSCAN0TMSTS31_TMTARM_SHIFT (4u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS0 (0x00000001u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS0_SHIFT (0u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS1 (0x00000002u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS1_SHIFT (1u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS2 (0x00000004u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS2_SHIFT (2u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS3 (0x00000008u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS3_SHIFT (3u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS4 (0x00000010u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS4_SHIFT (4u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS5 (0x00000020u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS5_SHIFT (5u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS6 (0x00000040u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS6_SHIFT (6u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS7 (0x00000080u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS7_SHIFT (7u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS8 (0x00000100u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS8_SHIFT (8u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS9 (0x00000200u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS9_SHIFT (9u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS10 (0x00000400u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS10_SHIFT (10u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS11 (0x00000800u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS11_SHIFT (11u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS12 (0x00001000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS12_SHIFT (12u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS13 (0x00002000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS13_SHIFT (13u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS14 (0x00004000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS14_SHIFT (14u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS15 (0x00008000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS15_SHIFT (15u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS16 (0x00010000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS16_SHIFT (16u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS17 (0x00020000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS17_SHIFT (17u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS18 (0x00040000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS18_SHIFT (18u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS19 (0x00080000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS19_SHIFT (19u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS20 (0x00100000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS20_SHIFT (20u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS21 (0x00200000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS21_SHIFT (21u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS22 (0x00400000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS22_SHIFT (22u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS23 (0x00800000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS23_SHIFT (23u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS24 (0x01000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS24_SHIFT (24u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS25 (0x02000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS25_SHIFT (25u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS26 (0x04000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS26_SHIFT (26u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS27 (0x08000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS27_SHIFT (27u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS28 (0x10000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS28_SHIFT (28u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS29 (0x20000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS29_SHIFT (29u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS30 (0x40000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS30_SHIFT (30u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS31 (0x80000000u) +#define RCAN_RSCAN0TMTRSTS0_TMTRSTS31_SHIFT (31u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS0 (0x00000001u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS0_SHIFT (0u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS1 (0x00000002u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS1_SHIFT (1u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS2 (0x00000004u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS2_SHIFT (2u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS3 (0x00000008u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS3_SHIFT (3u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS4 (0x00000010u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS4_SHIFT (4u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS5 (0x00000020u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS5_SHIFT (5u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS6 (0x00000040u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS6_SHIFT (6u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS7 (0x00000080u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS7_SHIFT (7u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS8 (0x00000100u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS8_SHIFT (8u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS9 (0x00000200u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS9_SHIFT (9u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS10 (0x00000400u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS10_SHIFT (10u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS11 (0x00000800u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS11_SHIFT (11u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS12 (0x00001000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS12_SHIFT (12u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS13 (0x00002000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS13_SHIFT (13u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS14 (0x00004000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS14_SHIFT (14u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS15 (0x00008000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS15_SHIFT (15u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS16 (0x00010000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS16_SHIFT (16u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS17 (0x00020000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS17_SHIFT (17u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS18 (0x00040000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS18_SHIFT (18u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS19 (0x00080000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS19_SHIFT (19u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS20 (0x00100000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS20_SHIFT (20u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS21 (0x00200000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS21_SHIFT (21u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS22 (0x00400000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS22_SHIFT (22u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS23 (0x00800000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS23_SHIFT (23u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS24 (0x01000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS24_SHIFT (24u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS25 (0x02000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS25_SHIFT (25u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS26 (0x04000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS26_SHIFT (26u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS27 (0x08000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS27_SHIFT (27u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS28 (0x10000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS28_SHIFT (28u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS29 (0x20000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS29_SHIFT (29u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS30 (0x40000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS30_SHIFT (30u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS31 (0x80000000u) +#define RCAN_RSCAN0TMTARSTS0_TMTARSTS31_SHIFT (31u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS0 (0x00000001u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS0_SHIFT (0u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS1 (0x00000002u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS1_SHIFT (1u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS2 (0x00000004u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS2_SHIFT (2u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS3 (0x00000008u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS3_SHIFT (3u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS4 (0x00000010u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS4_SHIFT (4u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS5 (0x00000020u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS5_SHIFT (5u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS6 (0x00000040u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS6_SHIFT (6u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS7 (0x00000080u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS7_SHIFT (7u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS8 (0x00000100u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS8_SHIFT (8u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS9 (0x00000200u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS9_SHIFT (9u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS10 (0x00000400u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS10_SHIFT (10u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS11 (0x00000800u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS11_SHIFT (11u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS12 (0x00001000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS12_SHIFT (12u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS13 (0x00002000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS13_SHIFT (13u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS14 (0x00004000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS14_SHIFT (14u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS15 (0x00008000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS15_SHIFT (15u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS16 (0x00010000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS16_SHIFT (16u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS17 (0x00020000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS17_SHIFT (17u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS18 (0x00040000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS18_SHIFT (18u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS19 (0x00080000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS19_SHIFT (19u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS20 (0x00100000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS20_SHIFT (20u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS21 (0x00200000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS21_SHIFT (21u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS22 (0x00400000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS22_SHIFT (22u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS23 (0x00800000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS23_SHIFT (23u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS24 (0x01000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS24_SHIFT (24u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS25 (0x02000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS25_SHIFT (25u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS26 (0x04000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS26_SHIFT (26u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS27 (0x08000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS27_SHIFT (27u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS28 (0x10000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS28_SHIFT (28u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS29 (0x20000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS29_SHIFT (29u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS30 (0x40000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS30_SHIFT (30u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS31 (0x80000000u) +#define RCAN_RSCAN0TMTCSTS0_TMTCSTS31_SHIFT (31u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS0 (0x00000001u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS0_SHIFT (0u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS1 (0x00000002u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS1_SHIFT (1u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS2 (0x00000004u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS2_SHIFT (2u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS3 (0x00000008u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS3_SHIFT (3u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS4 (0x00000010u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS4_SHIFT (4u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS5 (0x00000020u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS5_SHIFT (5u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS6 (0x00000040u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS6_SHIFT (6u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS7 (0x00000080u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS7_SHIFT (7u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS8 (0x00000100u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS8_SHIFT (8u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS9 (0x00000200u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS9_SHIFT (9u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS10 (0x00000400u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS10_SHIFT (10u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS11 (0x00000800u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS11_SHIFT (11u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS12 (0x00001000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS12_SHIFT (12u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS13 (0x00002000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS13_SHIFT (13u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS14 (0x00004000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS14_SHIFT (14u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS15 (0x00008000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS15_SHIFT (15u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS16 (0x00010000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS16_SHIFT (16u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS17 (0x00020000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS17_SHIFT (17u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS18 (0x00040000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS18_SHIFT (18u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS19 (0x00080000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS19_SHIFT (19u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS20 (0x00100000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS20_SHIFT (20u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS21 (0x00200000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS21_SHIFT (21u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS22 (0x00400000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS22_SHIFT (22u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS23 (0x00800000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS23_SHIFT (23u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS24 (0x01000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS24_SHIFT (24u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS25 (0x02000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS25_SHIFT (25u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS26 (0x04000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS26_SHIFT (26u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS27 (0x08000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS27_SHIFT (27u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS28 (0x10000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS28_SHIFT (28u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS29 (0x20000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS29_SHIFT (29u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS30 (0x40000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS30_SHIFT (30u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS31 (0x80000000u) +#define RCAN_RSCAN0TMTASTS0_TMTASTS31_SHIFT (31u) +#define RCAN_RSCAN0TMIEC0_TMIE0 (0x00000001u) +#define RCAN_RSCAN0TMIEC0_TMIE0_SHIFT (0u) +#define RCAN_RSCAN0TMIEC0_TMIE1 (0x00000002u) +#define RCAN_RSCAN0TMIEC0_TMIE1_SHIFT (1u) +#define RCAN_RSCAN0TMIEC0_TMIE2 (0x00000004u) +#define RCAN_RSCAN0TMIEC0_TMIE2_SHIFT (2u) +#define RCAN_RSCAN0TMIEC0_TMIE3 (0x00000008u) +#define RCAN_RSCAN0TMIEC0_TMIE3_SHIFT (3u) +#define RCAN_RSCAN0TMIEC0_TMIE4 (0x00000010u) +#define RCAN_RSCAN0TMIEC0_TMIE4_SHIFT (4u) +#define RCAN_RSCAN0TMIEC0_TMIE5 (0x00000020u) +#define RCAN_RSCAN0TMIEC0_TMIE5_SHIFT (5u) +#define RCAN_RSCAN0TMIEC0_TMIE6 (0x00000040u) +#define RCAN_RSCAN0TMIEC0_TMIE6_SHIFT (6u) +#define RCAN_RSCAN0TMIEC0_TMIE7 (0x00000080u) +#define RCAN_RSCAN0TMIEC0_TMIE7_SHIFT (7u) +#define RCAN_RSCAN0TMIEC0_TMIE8 (0x00000100u) +#define RCAN_RSCAN0TMIEC0_TMIE8_SHIFT (8u) +#define RCAN_RSCAN0TMIEC0_TMIE9 (0x00000200u) +#define RCAN_RSCAN0TMIEC0_TMIE9_SHIFT (9u) +#define RCAN_RSCAN0TMIEC0_TMIE10 (0x00000400u) +#define RCAN_RSCAN0TMIEC0_TMIE10_SHIFT (10u) +#define RCAN_RSCAN0TMIEC0_TMIE11 (0x00000800u) +#define RCAN_RSCAN0TMIEC0_TMIE11_SHIFT (11u) +#define RCAN_RSCAN0TMIEC0_TMIE12 (0x00001000u) +#define RCAN_RSCAN0TMIEC0_TMIE12_SHIFT (12u) +#define RCAN_RSCAN0TMIEC0_TMIE13 (0x00002000u) +#define RCAN_RSCAN0TMIEC0_TMIE13_SHIFT (13u) +#define RCAN_RSCAN0TMIEC0_TMIE14 (0x00004000u) +#define RCAN_RSCAN0TMIEC0_TMIE14_SHIFT (14u) +#define RCAN_RSCAN0TMIEC0_TMIE15 (0x00008000u) +#define RCAN_RSCAN0TMIEC0_TMIE15_SHIFT (15u) +#define RCAN_RSCAN0TMIEC0_TMIE16 (0x00010000u) +#define RCAN_RSCAN0TMIEC0_TMIE16_SHIFT (16u) +#define RCAN_RSCAN0TMIEC0_TMIE17 (0x00020000u) +#define RCAN_RSCAN0TMIEC0_TMIE17_SHIFT (17u) +#define RCAN_RSCAN0TMIEC0_TMIE18 (0x00040000u) +#define RCAN_RSCAN0TMIEC0_TMIE18_SHIFT (18u) +#define RCAN_RSCAN0TMIEC0_TMIE19 (0x00080000u) +#define RCAN_RSCAN0TMIEC0_TMIE19_SHIFT (19u) +#define RCAN_RSCAN0TMIEC0_TMIE20 (0x00100000u) +#define RCAN_RSCAN0TMIEC0_TMIE20_SHIFT (20u) +#define RCAN_RSCAN0TMIEC0_TMIE21 (0x00200000u) +#define RCAN_RSCAN0TMIEC0_TMIE21_SHIFT (21u) +#define RCAN_RSCAN0TMIEC0_TMIE22 (0x00400000u) +#define RCAN_RSCAN0TMIEC0_TMIE22_SHIFT (22u) +#define RCAN_RSCAN0TMIEC0_TMIE23 (0x00800000u) +#define RCAN_RSCAN0TMIEC0_TMIE23_SHIFT (23u) +#define RCAN_RSCAN0TMIEC0_TMIE24 (0x01000000u) +#define RCAN_RSCAN0TMIEC0_TMIE24_SHIFT (24u) +#define RCAN_RSCAN0TMIEC0_TMIE25 (0x02000000u) +#define RCAN_RSCAN0TMIEC0_TMIE25_SHIFT (25u) +#define RCAN_RSCAN0TMIEC0_TMIE26 (0x04000000u) +#define RCAN_RSCAN0TMIEC0_TMIE26_SHIFT (26u) +#define RCAN_RSCAN0TMIEC0_TMIE27 (0x08000000u) +#define RCAN_RSCAN0TMIEC0_TMIE27_SHIFT (27u) +#define RCAN_RSCAN0TMIEC0_TMIE28 (0x10000000u) +#define RCAN_RSCAN0TMIEC0_TMIE28_SHIFT (28u) +#define RCAN_RSCAN0TMIEC0_TMIE29 (0x20000000u) +#define RCAN_RSCAN0TMIEC0_TMIE29_SHIFT (29u) +#define RCAN_RSCAN0TMIEC0_TMIE30 (0x40000000u) +#define RCAN_RSCAN0TMIEC0_TMIE30_SHIFT (30u) +#define RCAN_RSCAN0TMIEC0_TMIE31 (0x80000000u) +#define RCAN_RSCAN0TMIEC0_TMIE31_SHIFT (31u) +#define RCAN_RSCAN0TXQCC0_TXQE (0x00000001u) +#define RCAN_RSCAN0TXQCC0_TXQE_SHIFT (0u) +#define RCAN_RSCAN0TXQCC0_TXQDC (0x00000F00u) +#define RCAN_RSCAN0TXQCC0_TXQDC_SHIFT (8u) +#define RCAN_RSCAN0TXQCC0_TXQIE (0x00001000u) +#define RCAN_RSCAN0TXQCC0_TXQIE_SHIFT (12u) +#define RCAN_RSCAN0TXQCC0_TXQIM (0x00002000u) +#define RCAN_RSCAN0TXQCC0_TXQIM_SHIFT (13u) +#define RCAN_RSCAN0TXQCC1_TXQE (0x00000001u) +#define RCAN_RSCAN0TXQCC1_TXQE_SHIFT (0u) +#define RCAN_RSCAN0TXQCC1_TXQDC (0x00000F00u) +#define RCAN_RSCAN0TXQCC1_TXQDC_SHIFT (8u) +#define RCAN_RSCAN0TXQCC1_TXQIE (0x00001000u) +#define RCAN_RSCAN0TXQCC1_TXQIE_SHIFT (12u) +#define RCAN_RSCAN0TXQCC1_TXQIM (0x00002000u) +#define RCAN_RSCAN0TXQCC1_TXQIM_SHIFT (13u) +#define RCAN_RSCAN0TXQSTS0_TXQEMP (0x00000001u) +#define RCAN_RSCAN0TXQSTS0_TXQEMP_SHIFT (0u) +#define RCAN_RSCAN0TXQSTS0_TXQFLL (0x00000002u) +#define RCAN_RSCAN0TXQSTS0_TXQFLL_SHIFT (1u) +#define RCAN_RSCAN0TXQSTS0_TXQIF (0x00000004u) +#define RCAN_RSCAN0TXQSTS0_TXQIF_SHIFT (2u) +#define RCAN_RSCAN0TXQSTS1_TXQEMP (0x00000001u) +#define RCAN_RSCAN0TXQSTS1_TXQEMP_SHIFT (0u) +#define RCAN_RSCAN0TXQSTS1_TXQFLL (0x00000002u) +#define RCAN_RSCAN0TXQSTS1_TXQFLL_SHIFT (1u) +#define RCAN_RSCAN0TXQSTS1_TXQIF (0x00000004u) +#define RCAN_RSCAN0TXQSTS1_TXQIF_SHIFT (2u) +#define RCAN_RSCAN0TXQPCTR0_TXQPC (0x000000FFu) +#define RCAN_RSCAN0TXQPCTR0_TXQPC_SHIFT (0u) +#define RCAN_RSCAN0TXQPCTR1_TXQPC (0x000000FFu) +#define RCAN_RSCAN0TXQPCTR1_TXQPC_SHIFT (0u) +#define RCAN_RSCAN0THLCC0_THLE (0x00000001u) +#define RCAN_RSCAN0THLCC0_THLE_SHIFT (0u) +#define RCAN_RSCAN0THLCC0_THLIE (0x00000100u) +#define RCAN_RSCAN0THLCC0_THLIE_SHIFT (8u) +#define RCAN_RSCAN0THLCC0_THLIM (0x00000200u) +#define RCAN_RSCAN0THLCC0_THLIM_SHIFT (9u) +#define RCAN_RSCAN0THLCC0_THLDTE (0x00000400u) +#define RCAN_RSCAN0THLCC0_THLDTE_SHIFT (10u) +#define RCAN_RSCAN0THLCC1_THLE (0x00000001u) +#define RCAN_RSCAN0THLCC1_THLE_SHIFT (0u) +#define RCAN_RSCAN0THLCC1_THLIE (0x00000100u) +#define RCAN_RSCAN0THLCC1_THLIE_SHIFT (8u) +#define RCAN_RSCAN0THLCC1_THLIM (0x00000200u) +#define RCAN_RSCAN0THLCC1_THLIM_SHIFT (9u) +#define RCAN_RSCAN0THLCC1_THLDTE (0x00000400u) +#define RCAN_RSCAN0THLCC1_THLDTE_SHIFT (10u) +#define RCAN_RSCAN0THLSTS0_THLEMP (0x00000001u) +#define RCAN_RSCAN0THLSTS0_THLEMP_SHIFT (0u) +#define RCAN_RSCAN0THLSTS0_THLFLL (0x00000002u) +#define RCAN_RSCAN0THLSTS0_THLFLL_SHIFT (1u) +#define RCAN_RSCAN0THLSTS0_THLELT (0x00000004u) +#define RCAN_RSCAN0THLSTS0_THLELT_SHIFT (2u) +#define RCAN_RSCAN0THLSTS0_THLIF (0x00000008u) +#define RCAN_RSCAN0THLSTS0_THLIF_SHIFT (3u) +#define RCAN_RSCAN0THLSTS0_THLMC (0x00001F00u) +#define RCAN_RSCAN0THLSTS0_THLMC_SHIFT (8u) +#define RCAN_RSCAN0THLSTS1_THLEMP (0x00000001u) +#define RCAN_RSCAN0THLSTS1_THLEMP_SHIFT (0u) +#define RCAN_RSCAN0THLSTS1_THLFLL (0x00000002u) +#define RCAN_RSCAN0THLSTS1_THLFLL_SHIFT (1u) +#define RCAN_RSCAN0THLSTS1_THLELT (0x00000004u) +#define RCAN_RSCAN0THLSTS1_THLELT_SHIFT (2u) +#define RCAN_RSCAN0THLSTS1_THLIF (0x00000008u) +#define RCAN_RSCAN0THLSTS1_THLIF_SHIFT (3u) +#define RCAN_RSCAN0THLSTS1_THLMC (0x00001F00u) +#define RCAN_RSCAN0THLSTS1_THLMC_SHIFT (8u) +#define RCAN_RSCAN0THLPCTR0_THLPC (0x000000FFu) +#define RCAN_RSCAN0THLPCTR0_THLPC_SHIFT (0u) +#define RCAN_RSCAN0THLPCTR1_THLPC (0x000000FFu) +#define RCAN_RSCAN0THLPCTR1_THLPC_SHIFT (0u) +#define RCAN_RSCAN0GTINTSTS0_TSIF0 (0x00000001u) +#define RCAN_RSCAN0GTINTSTS0_TSIF0_SHIFT (0u) +#define RCAN_RSCAN0GTINTSTS0_TAIF0 (0x00000002u) +#define RCAN_RSCAN0GTINTSTS0_TAIF0_SHIFT (1u) +#define RCAN_RSCAN0GTINTSTS0_TQIF0 (0x00000004u) +#define RCAN_RSCAN0GTINTSTS0_TQIF0_SHIFT (2u) +#define RCAN_RSCAN0GTINTSTS0_CFTIF0 (0x00000008u) +#define RCAN_RSCAN0GTINTSTS0_CFTIF0_SHIFT (3u) +#define RCAN_RSCAN0GTINTSTS0_THIF0 (0x00000010u) +#define RCAN_RSCAN0GTINTSTS0_THIF0_SHIFT (4u) +#define RCAN_RSCAN0GTINTSTS0_TSIF1 (0x00000100u) +#define RCAN_RSCAN0GTINTSTS0_TSIF1_SHIFT (8u) +#define RCAN_RSCAN0GTINTSTS0_TAIF1 (0x00000200u) +#define RCAN_RSCAN0GTINTSTS0_TAIF1_SHIFT (9u) +#define RCAN_RSCAN0GTINTSTS0_TQIF1 (0x00000400u) +#define RCAN_RSCAN0GTINTSTS0_TQIF1_SHIFT (10u) +#define RCAN_RSCAN0GTINTSTS0_CFTIF1 (0x00000800u) +#define RCAN_RSCAN0GTINTSTS0_CFTIF1_SHIFT (11u) +#define RCAN_RSCAN0GTINTSTS0_THIF1 (0x00001000u) +#define RCAN_RSCAN0GTINTSTS0_THIF1_SHIFT (12u) +#define RCAN_RSCAN0GTSTCFG_C0ICBCE (0x00000001u) +#define RCAN_RSCAN0GTSTCFG_C0ICBCE_SHIFT (0u) +#define RCAN_RSCAN0GTSTCFG_C1ICBCE (0x00000002u) +#define RCAN_RSCAN0GTSTCFG_C1ICBCE_SHIFT (1u) +#define RCAN_RSCAN0GTSTCFG_RTMPS (0x007F0000u) +#define RCAN_RSCAN0GTSTCFG_RTMPS_SHIFT (16u) +#define RCAN_RSCAN0GTSTCTR_ICBCTME (0x00000001u) +#define RCAN_RSCAN0GTSTCTR_ICBCTME_SHIFT (0u) +#define RCAN_RSCAN0GTSTCTR_RTME (0x00000004u) +#define RCAN_RSCAN0GTSTCTR_RTME_SHIFT (2u) +#define RCAN_RSCAN0GFDCFG_TSCCFG (0x00000300u) +#define RCAN_RSCAN0GFDCFG_TSCCFG_SHIFT (8u) +#define RCAN_RSCAN0GLOCKK_LOCK (0x0000FFFFu) +#define RCAN_RSCAN0GLOCKK_LOCK_SHIFT (0u) +#define RCAN_RSCAN0GRMCFG_RCMC (0x00000001u) +#define RCAN_RSCAN0GRMCFG_RCMC_SHIFT (0u) +#define RCAN_RSCAN0GAFLID0_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID0_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID0_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID0_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID0_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID0_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID0_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID0_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM0_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM0_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM0_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM0_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM0_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM0_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_0_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_0_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_0_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_0_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_0_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_0_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_0_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_0_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_0_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_0_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID1_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID1_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID1_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID1_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID1_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID1_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID1_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID1_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM1_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM1_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM1_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM1_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM1_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM1_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_1_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_1_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_1_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_1_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_1_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_1_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_1_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_1_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_1_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_1_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID2_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID2_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID2_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID2_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID2_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID2_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID2_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID2_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM2_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM2_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM2_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM2_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM2_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM2_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_2_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_2_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_2_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_2_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_2_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_2_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_2_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_2_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_2_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_2_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID3_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID3_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID3_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID3_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID3_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID3_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID3_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID3_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM3_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM3_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM3_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM3_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM3_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM3_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_3_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_3_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_3_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_3_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_3_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_3_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_3_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_3_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_3_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_3_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID4_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID4_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID4_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID4_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID4_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID4_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID4_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID4_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM4_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM4_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM4_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM4_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM4_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM4_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_4_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_4_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_4_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_4_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_4_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_4_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_4_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_4_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_4_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_4_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID5_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID5_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID5_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID5_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID5_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID5_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID5_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID5_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM5_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM5_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM5_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM5_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM5_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM5_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_5_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_5_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_5_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_5_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_5_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_5_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_5_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_5_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_5_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_5_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID6_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID6_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID6_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID6_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID6_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID6_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID6_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID6_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM6_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM6_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM6_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM6_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM6_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM6_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_6_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_6_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_6_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_6_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_6_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_6_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_6_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_6_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_6_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_6_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID7_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID7_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID7_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID7_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID7_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID7_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID7_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID7_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM7_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM7_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM7_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM7_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM7_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM7_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_7_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_7_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_7_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_7_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_7_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_7_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_7_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_7_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_7_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_7_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID8_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID8_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID8_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID8_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID8_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID8_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID8_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID8_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM8_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM8_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM8_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM8_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM8_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM8_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_8_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_8_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_8_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_8_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_8_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_8_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_8_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_8_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_8_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_8_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID9_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID9_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID9_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID9_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID9_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID9_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID9_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID9_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM9_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM9_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM9_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM9_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM9_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM9_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_9_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_9_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_9_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_9_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_9_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_9_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_9_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_9_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_9_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_9_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID10_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID10_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID10_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID10_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID10_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID10_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID10_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID10_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM10_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM10_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM10_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM10_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM10_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM10_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_10_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_10_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_10_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_10_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_10_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_10_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_10_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_10_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_10_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_10_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID11_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID11_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID11_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID11_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID11_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID11_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID11_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID11_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM11_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM11_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM11_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM11_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM11_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM11_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_11_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_11_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_11_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_11_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_11_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_11_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_11_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_11_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_11_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_11_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID12_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID12_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID12_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID12_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID12_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID12_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID12_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID12_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM12_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM12_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM12_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM12_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM12_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM12_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_12_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_12_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_12_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_12_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_12_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_12_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_12_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_12_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_12_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_12_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID13_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID13_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID13_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID13_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID13_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID13_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID13_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID13_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM13_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM13_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM13_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM13_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM13_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM13_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_13_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_13_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_13_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_13_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_13_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_13_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_13_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_13_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_13_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_13_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID14_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID14_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID14_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID14_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID14_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID14_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID14_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID14_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM14_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM14_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM14_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM14_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM14_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM14_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_14_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_14_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_14_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_14_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_14_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_14_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_14_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_14_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_14_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_14_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0GAFLID15_GAFLID (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLID15_GAFLID_SHIFT (0u) +#define RCAN_RSCAN0GAFLID15_GAFLLB (0x20000000u) +#define RCAN_RSCAN0GAFLID15_GAFLLB_SHIFT (29u) +#define RCAN_RSCAN0GAFLID15_GAFLRTR (0x40000000u) +#define RCAN_RSCAN0GAFLID15_GAFLRTR_SHIFT (30u) +#define RCAN_RSCAN0GAFLID15_GAFLIDE (0x80000000u) +#define RCAN_RSCAN0GAFLID15_GAFLIDE_SHIFT (31u) +#define RCAN_RSCAN0GAFLM15_GAFLIDM (0x1FFFFFFFu) +#define RCAN_RSCAN0GAFLM15_GAFLIDM_SHIFT (0u) +#define RCAN_RSCAN0GAFLM15_GAFLRTRM (0x40000000u) +#define RCAN_RSCAN0GAFLM15_GAFLRTRM_SHIFT (30u) +#define RCAN_RSCAN0GAFLM15_GAFLIDEM (0x80000000u) +#define RCAN_RSCAN0GAFLM15_GAFLIDEM_SHIFT (31u) +#define RCAN_RSCAN0GAFLP0_15_GAFLRMDP (0x00007F00u) +#define RCAN_RSCAN0GAFLP0_15_GAFLRMDP_SHIFT (8u) +#define RCAN_RSCAN0GAFLP0_15_GAFLRMV (0x00008000u) +#define RCAN_RSCAN0GAFLP0_15_GAFLRMV_SHIFT (15u) +#define RCAN_RSCAN0GAFLP0_15_GAFLPTR (0x0FFF0000u) +#define RCAN_RSCAN0GAFLP0_15_GAFLPTR_SHIFT (16u) +#define RCAN_RSCAN0GAFLP0_15_GAFLDLC (0xF0000000u) +#define RCAN_RSCAN0GAFLP0_15_GAFLDLC_SHIFT (28u) +#define RCAN_RSCAN0GAFLP1_15_GAFLFDP (0x00003FFFu) +#define RCAN_RSCAN0GAFLP1_15_GAFLFDP_SHIFT (0u) +#define RCAN_RSCAN0RMID0_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID0_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID0_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID0_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID0_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID0_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR0_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR0_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR0_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR0_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR0_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR0_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_0_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_0_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_0_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_0_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_0_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_0_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_0_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_0_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_0_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_0_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_0_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_0_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_0_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_0_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_0_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_0_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID1_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID1_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID1_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID1_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID1_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID1_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR1_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR1_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR1_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR1_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR1_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR1_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_1_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_1_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_1_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_1_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_1_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_1_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_1_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_1_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_1_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_1_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_1_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_1_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_1_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_1_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_1_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_1_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID2_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID2_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID2_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID2_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID2_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID2_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR2_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR2_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR2_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR2_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR2_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR2_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_2_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_2_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_2_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_2_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_2_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_2_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_2_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_2_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_2_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_2_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_2_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_2_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_2_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_2_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_2_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_2_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID3_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID3_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID3_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID3_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID3_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID3_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR3_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR3_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR3_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR3_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR3_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR3_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_3_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_3_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_3_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_3_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_3_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_3_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_3_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_3_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_3_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_3_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_3_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_3_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_3_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_3_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_3_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_3_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID4_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID4_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID4_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID4_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID4_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID4_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR4_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR4_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR4_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR4_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR4_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR4_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_4_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_4_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_4_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_4_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_4_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_4_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_4_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_4_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_4_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_4_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_4_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_4_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_4_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_4_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_4_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_4_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID5_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID5_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID5_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID5_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID5_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID5_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR5_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR5_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR5_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR5_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR5_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR5_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_5_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_5_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_5_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_5_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_5_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_5_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_5_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_5_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_5_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_5_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_5_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_5_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_5_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_5_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_5_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_5_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID6_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID6_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID6_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID6_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID6_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID6_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR6_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR6_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR6_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR6_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR6_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR6_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_6_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_6_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_6_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_6_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_6_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_6_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_6_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_6_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_6_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_6_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_6_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_6_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_6_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_6_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_6_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_6_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID7_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID7_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID7_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID7_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID7_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID7_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR7_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR7_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR7_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR7_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR7_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR7_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_7_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_7_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_7_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_7_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_7_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_7_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_7_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_7_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_7_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_7_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_7_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_7_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_7_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_7_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_7_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_7_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID8_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID8_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID8_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID8_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID8_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID8_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR8_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR8_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR8_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR8_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR8_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR8_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_8_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_8_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_8_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_8_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_8_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_8_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_8_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_8_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_8_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_8_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_8_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_8_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_8_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_8_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_8_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_8_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID9_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID9_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID9_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID9_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID9_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID9_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR9_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR9_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR9_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR9_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR9_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR9_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_9_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_9_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_9_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_9_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_9_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_9_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_9_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_9_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_9_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_9_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_9_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_9_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_9_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_9_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_9_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_9_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID10_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID10_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID10_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID10_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID10_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID10_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR10_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR10_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR10_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR10_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR10_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR10_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_10_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_10_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_10_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_10_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_10_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_10_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_10_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_10_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_10_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_10_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_10_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_10_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_10_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_10_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_10_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_10_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID11_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID11_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID11_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID11_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID11_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID11_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR11_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR11_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR11_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR11_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR11_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR11_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_11_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_11_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_11_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_11_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_11_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_11_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_11_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_11_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_11_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_11_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_11_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_11_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_11_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_11_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_11_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_11_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID12_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID12_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID12_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID12_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID12_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID12_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR12_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR12_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR12_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR12_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR12_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR12_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_12_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_12_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_12_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_12_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_12_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_12_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_12_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_12_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_12_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_12_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_12_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_12_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_12_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_12_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_12_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_12_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID13_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID13_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID13_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID13_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID13_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID13_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR13_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR13_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR13_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR13_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR13_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR13_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_13_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_13_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_13_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_13_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_13_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_13_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_13_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_13_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_13_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_13_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_13_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_13_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_13_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_13_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_13_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_13_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID14_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID14_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID14_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID14_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID14_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID14_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR14_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR14_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR14_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR14_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR14_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR14_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_14_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_14_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_14_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_14_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_14_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_14_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_14_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_14_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_14_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_14_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_14_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_14_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_14_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_14_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_14_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_14_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID15_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID15_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID15_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID15_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID15_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID15_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR15_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR15_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR15_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR15_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR15_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR15_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_15_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_15_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_15_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_15_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_15_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_15_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_15_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_15_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_15_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_15_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_15_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_15_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_15_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_15_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_15_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_15_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID16_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID16_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID16_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID16_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID16_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID16_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR16_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR16_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR16_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR16_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR16_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR16_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_16_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_16_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_16_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_16_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_16_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_16_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_16_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_16_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_16_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_16_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_16_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_16_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_16_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_16_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_16_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_16_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID17_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID17_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID17_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID17_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID17_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID17_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR17_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR17_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR17_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR17_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR17_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR17_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_17_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_17_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_17_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_17_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_17_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_17_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_17_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_17_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_17_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_17_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_17_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_17_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_17_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_17_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_17_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_17_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID18_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID18_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID18_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID18_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID18_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID18_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR18_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR18_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR18_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR18_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR18_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR18_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_18_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_18_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_18_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_18_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_18_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_18_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_18_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_18_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_18_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_18_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_18_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_18_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_18_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_18_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_18_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_18_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID19_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID19_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID19_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID19_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID19_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID19_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR19_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR19_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR19_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR19_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR19_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR19_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_19_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_19_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_19_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_19_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_19_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_19_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_19_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_19_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_19_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_19_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_19_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_19_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_19_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_19_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_19_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_19_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID20_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID20_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID20_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID20_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID20_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID20_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR20_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR20_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR20_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR20_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR20_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR20_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_20_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_20_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_20_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_20_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_20_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_20_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_20_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_20_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_20_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_20_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_20_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_20_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_20_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_20_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_20_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_20_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID21_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID21_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID21_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID21_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID21_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID21_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR21_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR21_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR21_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR21_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR21_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR21_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_21_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_21_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_21_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_21_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_21_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_21_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_21_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_21_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_21_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_21_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_21_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_21_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_21_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_21_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_21_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_21_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID22_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID22_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID22_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID22_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID22_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID22_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR22_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR22_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR22_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR22_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR22_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR22_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_22_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_22_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_22_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_22_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_22_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_22_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_22_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_22_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_22_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_22_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_22_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_22_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_22_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_22_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_22_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_22_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID23_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID23_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID23_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID23_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID23_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID23_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR23_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR23_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR23_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR23_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR23_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR23_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_23_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_23_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_23_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_23_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_23_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_23_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_23_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_23_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_23_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_23_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_23_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_23_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_23_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_23_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_23_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_23_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID24_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID24_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID24_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID24_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID24_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID24_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR24_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR24_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR24_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR24_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR24_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR24_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_24_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_24_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_24_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_24_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_24_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_24_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_24_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_24_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_24_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_24_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_24_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_24_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_24_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_24_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_24_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_24_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID25_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID25_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID25_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID25_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID25_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID25_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR25_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR25_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR25_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR25_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR25_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR25_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_25_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_25_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_25_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_25_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_25_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_25_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_25_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_25_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_25_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_25_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_25_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_25_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_25_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_25_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_25_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_25_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID26_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID26_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID26_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID26_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID26_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID26_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR26_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR26_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR26_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR26_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR26_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR26_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_26_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_26_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_26_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_26_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_26_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_26_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_26_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_26_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_26_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_26_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_26_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_26_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_26_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_26_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_26_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_26_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID27_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID27_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID27_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID27_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID27_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID27_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR27_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR27_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR27_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR27_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR27_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR27_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_27_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_27_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_27_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_27_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_27_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_27_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_27_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_27_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_27_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_27_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_27_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_27_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_27_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_27_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_27_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_27_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID28_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID28_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID28_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID28_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID28_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID28_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR28_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR28_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR28_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR28_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR28_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR28_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_28_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_28_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_28_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_28_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_28_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_28_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_28_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_28_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_28_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_28_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_28_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_28_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_28_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_28_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_28_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_28_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID29_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID29_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID29_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID29_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID29_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID29_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR29_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR29_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR29_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR29_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR29_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR29_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_29_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_29_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_29_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_29_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_29_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_29_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_29_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_29_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_29_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_29_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_29_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_29_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_29_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_29_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_29_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_29_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID30_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID30_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID30_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID30_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID30_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID30_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR30_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR30_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR30_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR30_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR30_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR30_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_30_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_30_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_30_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_30_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_30_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_30_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_30_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_30_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_30_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_30_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_30_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_30_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_30_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_30_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_30_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_30_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RMID31_RMID (0x1FFFFFFFu) +#define RCAN_RSCAN0RMID31_RMID_SHIFT (0u) +#define RCAN_RSCAN0RMID31_RMRTR (0x40000000u) +#define RCAN_RSCAN0RMID31_RMRTR_SHIFT (30u) +#define RCAN_RSCAN0RMID31_RMIDE (0x80000000u) +#define RCAN_RSCAN0RMID31_RMIDE_SHIFT (31u) +#define RCAN_RSCAN0RMPTR31_RMTS (0x0000FFFFu) +#define RCAN_RSCAN0RMPTR31_RMTS_SHIFT (0u) +#define RCAN_RSCAN0RMPTR31_RMPTR (0x0FFF0000u) +#define RCAN_RSCAN0RMPTR31_RMPTR_SHIFT (16u) +#define RCAN_RSCAN0RMPTR31_RMDLC (0xF0000000u) +#define RCAN_RSCAN0RMPTR31_RMDLC_SHIFT (28u) +#define RCAN_RSCAN0RMDF0_31_RMDB0 (0x000000FFu) +#define RCAN_RSCAN0RMDF0_31_RMDB0_SHIFT (0u) +#define RCAN_RSCAN0RMDF0_31_RMDB1 (0x0000FF00u) +#define RCAN_RSCAN0RMDF0_31_RMDB1_SHIFT (8u) +#define RCAN_RSCAN0RMDF0_31_RMDB2 (0x00FF0000u) +#define RCAN_RSCAN0RMDF0_31_RMDB2_SHIFT (16u) +#define RCAN_RSCAN0RMDF0_31_RMDB3 (0xFF000000u) +#define RCAN_RSCAN0RMDF0_31_RMDB3_SHIFT (24u) +#define RCAN_RSCAN0RMDF1_31_RMDB4 (0x000000FFu) +#define RCAN_RSCAN0RMDF1_31_RMDB4_SHIFT (0u) +#define RCAN_RSCAN0RMDF1_31_RMDB5 (0x0000FF00u) +#define RCAN_RSCAN0RMDF1_31_RMDB5_SHIFT (8u) +#define RCAN_RSCAN0RMDF1_31_RMDB6 (0x00FF0000u) +#define RCAN_RSCAN0RMDF1_31_RMDB6_SHIFT (16u) +#define RCAN_RSCAN0RMDF1_31_RMDB7 (0xFF000000u) +#define RCAN_RSCAN0RMDF1_31_RMDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID0_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID0_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID0_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID0_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID0_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID0_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR0_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR0_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR0_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR0_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR0_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR0_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_0_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_0_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_0_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_0_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_0_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_0_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_0_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_0_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_0_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_0_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_0_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_0_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_0_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_0_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_0_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_0_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID1_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID1_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID1_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID1_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID1_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID1_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR1_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR1_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR1_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR1_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR1_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR1_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_1_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_1_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_1_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_1_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_1_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_1_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_1_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_1_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_1_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_1_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_1_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_1_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_1_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_1_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_1_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_1_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID2_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID2_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID2_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID2_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID2_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID2_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR2_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR2_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR2_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR2_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR2_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR2_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_2_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_2_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_2_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_2_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_2_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_2_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_2_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_2_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_2_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_2_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_2_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_2_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_2_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_2_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_2_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_2_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID3_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID3_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID3_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID3_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID3_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID3_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR3_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR3_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR3_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR3_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR3_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR3_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_3_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_3_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_3_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_3_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_3_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_3_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_3_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_3_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_3_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_3_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_3_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_3_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_3_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_3_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_3_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_3_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID4_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID4_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID4_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID4_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID4_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID4_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR4_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR4_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR4_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR4_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR4_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR4_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_4_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_4_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_4_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_4_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_4_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_4_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_4_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_4_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_4_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_4_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_4_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_4_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_4_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_4_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_4_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_4_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID5_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID5_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID5_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID5_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID5_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID5_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR5_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR5_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR5_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR5_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR5_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR5_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_5_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_5_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_5_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_5_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_5_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_5_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_5_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_5_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_5_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_5_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_5_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_5_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_5_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_5_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_5_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_5_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID6_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID6_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID6_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID6_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID6_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID6_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR6_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR6_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR6_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR6_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR6_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR6_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_6_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_6_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_6_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_6_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_6_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_6_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_6_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_6_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_6_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_6_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_6_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_6_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_6_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_6_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_6_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_6_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0RFID7_RFID (0x1FFFFFFFu) +#define RCAN_RSCAN0RFID7_RFID_SHIFT (0u) +#define RCAN_RSCAN0RFID7_RFRTR (0x40000000u) +#define RCAN_RSCAN0RFID7_RFRTR_SHIFT (30u) +#define RCAN_RSCAN0RFID7_RFIDE (0x80000000u) +#define RCAN_RSCAN0RFID7_RFIDE_SHIFT (31u) +#define RCAN_RSCAN0RFPTR7_RFTS (0x0000FFFFu) +#define RCAN_RSCAN0RFPTR7_RFTS_SHIFT (0u) +#define RCAN_RSCAN0RFPTR7_RFPTR (0x0FFF0000u) +#define RCAN_RSCAN0RFPTR7_RFPTR_SHIFT (16u) +#define RCAN_RSCAN0RFPTR7_RFDLC (0xF0000000u) +#define RCAN_RSCAN0RFPTR7_RFDLC_SHIFT (28u) +#define RCAN_RSCAN0RFDF0_7_RFDB0 (0x000000FFu) +#define RCAN_RSCAN0RFDF0_7_RFDB0_SHIFT (0u) +#define RCAN_RSCAN0RFDF0_7_RFDB1 (0x0000FF00u) +#define RCAN_RSCAN0RFDF0_7_RFDB1_SHIFT (8u) +#define RCAN_RSCAN0RFDF0_7_RFDB2 (0x00FF0000u) +#define RCAN_RSCAN0RFDF0_7_RFDB2_SHIFT (16u) +#define RCAN_RSCAN0RFDF0_7_RFDB3 (0xFF000000u) +#define RCAN_RSCAN0RFDF0_7_RFDB3_SHIFT (24u) +#define RCAN_RSCAN0RFDF1_7_RFDB4 (0x000000FFu) +#define RCAN_RSCAN0RFDF1_7_RFDB4_SHIFT (0u) +#define RCAN_RSCAN0RFDF1_7_RFDB5 (0x0000FF00u) +#define RCAN_RSCAN0RFDF1_7_RFDB5_SHIFT (8u) +#define RCAN_RSCAN0RFDF1_7_RFDB6 (0x00FF0000u) +#define RCAN_RSCAN0RFDF1_7_RFDB6_SHIFT (16u) +#define RCAN_RSCAN0RFDF1_7_RFDB7 (0xFF000000u) +#define RCAN_RSCAN0RFDF1_7_RFDB7_SHIFT (24u) +#define RCAN_RSCAN0CFID0_CFID (0x1FFFFFFFu) +#define RCAN_RSCAN0CFID0_CFID_SHIFT (0u) +#define RCAN_RSCAN0CFID0_THLEN (0x20000000u) +#define RCAN_RSCAN0CFID0_THLEN_SHIFT (29u) +#define RCAN_RSCAN0CFID0_CFRTR (0x40000000u) +#define RCAN_RSCAN0CFID0_CFRTR_SHIFT (30u) +#define RCAN_RSCAN0CFID0_CFIDE (0x80000000u) +#define RCAN_RSCAN0CFID0_CFIDE_SHIFT (31u) +#define RCAN_RSCAN0CFPTR0_CFTS (0x0000FFFFu) +#define RCAN_RSCAN0CFPTR0_CFTS_SHIFT (0u) +#define RCAN_RSCAN0CFPTR0_CFPTR (0x0FFF0000u) +#define RCAN_RSCAN0CFPTR0_CFPTR_SHIFT (16u) +#define RCAN_RSCAN0CFPTR0_CFDLC (0xF0000000u) +#define RCAN_RSCAN0CFPTR0_CFDLC_SHIFT (28u) +#define RCAN_RSCAN0CFDF0_0_CFDB0 (0x000000FFu) +#define RCAN_RSCAN0CFDF0_0_CFDB0_SHIFT (0u) +#define RCAN_RSCAN0CFDF0_0_CFDB1 (0x0000FF00u) +#define RCAN_RSCAN0CFDF0_0_CFDB1_SHIFT (8u) +#define RCAN_RSCAN0CFDF0_0_CFDB2 (0x00FF0000u) +#define RCAN_RSCAN0CFDF0_0_CFDB2_SHIFT (16u) +#define RCAN_RSCAN0CFDF0_0_CFDB3 (0xFF000000u) +#define RCAN_RSCAN0CFDF0_0_CFDB3_SHIFT (24u) +#define RCAN_RSCAN0CFDF1_0_CFDB4 (0x000000FFu) +#define RCAN_RSCAN0CFDF1_0_CFDB4_SHIFT (0u) +#define RCAN_RSCAN0CFDF1_0_CFDB5 (0x0000FF00u) +#define RCAN_RSCAN0CFDF1_0_CFDB5_SHIFT (8u) +#define RCAN_RSCAN0CFDF1_0_CFDB6 (0x00FF0000u) +#define RCAN_RSCAN0CFDF1_0_CFDB6_SHIFT (16u) +#define RCAN_RSCAN0CFDF1_0_CFDB7 (0xFF000000u) +#define RCAN_RSCAN0CFDF1_0_CFDB7_SHIFT (24u) +#define RCAN_RSCAN0CFID1_CFID (0x1FFFFFFFu) +#define RCAN_RSCAN0CFID1_CFID_SHIFT (0u) +#define RCAN_RSCAN0CFID1_THLEN (0x20000000u) +#define RCAN_RSCAN0CFID1_THLEN_SHIFT (29u) +#define RCAN_RSCAN0CFID1_CFRTR (0x40000000u) +#define RCAN_RSCAN0CFID1_CFRTR_SHIFT (30u) +#define RCAN_RSCAN0CFID1_CFIDE (0x80000000u) +#define RCAN_RSCAN0CFID1_CFIDE_SHIFT (31u) +#define RCAN_RSCAN0CFPTR1_CFTS (0x0000FFFFu) +#define RCAN_RSCAN0CFPTR1_CFTS_SHIFT (0u) +#define RCAN_RSCAN0CFPTR1_CFPTR (0x0FFF0000u) +#define RCAN_RSCAN0CFPTR1_CFPTR_SHIFT (16u) +#define RCAN_RSCAN0CFPTR1_CFDLC (0xF0000000u) +#define RCAN_RSCAN0CFPTR1_CFDLC_SHIFT (28u) +#define RCAN_RSCAN0CFDF0_1_CFDB0 (0x000000FFu) +#define RCAN_RSCAN0CFDF0_1_CFDB0_SHIFT (0u) +#define RCAN_RSCAN0CFDF0_1_CFDB1 (0x0000FF00u) +#define RCAN_RSCAN0CFDF0_1_CFDB1_SHIFT (8u) +#define RCAN_RSCAN0CFDF0_1_CFDB2 (0x00FF0000u) +#define RCAN_RSCAN0CFDF0_1_CFDB2_SHIFT (16u) +#define RCAN_RSCAN0CFDF0_1_CFDB3 (0xFF000000u) +#define RCAN_RSCAN0CFDF0_1_CFDB3_SHIFT (24u) +#define RCAN_RSCAN0CFDF1_1_CFDB4 (0x000000FFu) +#define RCAN_RSCAN0CFDF1_1_CFDB4_SHIFT (0u) +#define RCAN_RSCAN0CFDF1_1_CFDB5 (0x0000FF00u) +#define RCAN_RSCAN0CFDF1_1_CFDB5_SHIFT (8u) +#define RCAN_RSCAN0CFDF1_1_CFDB6 (0x00FF0000u) +#define RCAN_RSCAN0CFDF1_1_CFDB6_SHIFT (16u) +#define RCAN_RSCAN0CFDF1_1_CFDB7 (0xFF000000u) +#define RCAN_RSCAN0CFDF1_1_CFDB7_SHIFT (24u) +#define RCAN_RSCAN0CFID2_CFID (0x1FFFFFFFu) +#define RCAN_RSCAN0CFID2_CFID_SHIFT (0u) +#define RCAN_RSCAN0CFID2_THLEN (0x20000000u) +#define RCAN_RSCAN0CFID2_THLEN_SHIFT (29u) +#define RCAN_RSCAN0CFID2_CFRTR (0x40000000u) +#define RCAN_RSCAN0CFID2_CFRTR_SHIFT (30u) +#define RCAN_RSCAN0CFID2_CFIDE (0x80000000u) +#define RCAN_RSCAN0CFID2_CFIDE_SHIFT (31u) +#define RCAN_RSCAN0CFPTR2_CFTS (0x0000FFFFu) +#define RCAN_RSCAN0CFPTR2_CFTS_SHIFT (0u) +#define RCAN_RSCAN0CFPTR2_CFPTR (0x0FFF0000u) +#define RCAN_RSCAN0CFPTR2_CFPTR_SHIFT (16u) +#define RCAN_RSCAN0CFPTR2_CFDLC (0xF0000000u) +#define RCAN_RSCAN0CFPTR2_CFDLC_SHIFT (28u) +#define RCAN_RSCAN0CFDF0_2_CFDB0 (0x000000FFu) +#define RCAN_RSCAN0CFDF0_2_CFDB0_SHIFT (0u) +#define RCAN_RSCAN0CFDF0_2_CFDB1 (0x0000FF00u) +#define RCAN_RSCAN0CFDF0_2_CFDB1_SHIFT (8u) +#define RCAN_RSCAN0CFDF0_2_CFDB2 (0x00FF0000u) +#define RCAN_RSCAN0CFDF0_2_CFDB2_SHIFT (16u) +#define RCAN_RSCAN0CFDF0_2_CFDB3 (0xFF000000u) +#define RCAN_RSCAN0CFDF0_2_CFDB3_SHIFT (24u) +#define RCAN_RSCAN0CFDF1_2_CFDB4 (0x000000FFu) +#define RCAN_RSCAN0CFDF1_2_CFDB4_SHIFT (0u) +#define RCAN_RSCAN0CFDF1_2_CFDB5 (0x0000FF00u) +#define RCAN_RSCAN0CFDF1_2_CFDB5_SHIFT (8u) +#define RCAN_RSCAN0CFDF1_2_CFDB6 (0x00FF0000u) +#define RCAN_RSCAN0CFDF1_2_CFDB6_SHIFT (16u) +#define RCAN_RSCAN0CFDF1_2_CFDB7 (0xFF000000u) +#define RCAN_RSCAN0CFDF1_2_CFDB7_SHIFT (24u) +#define RCAN_RSCAN0CFID3_CFID (0x1FFFFFFFu) +#define RCAN_RSCAN0CFID3_CFID_SHIFT (0u) +#define RCAN_RSCAN0CFID3_THLEN (0x20000000u) +#define RCAN_RSCAN0CFID3_THLEN_SHIFT (29u) +#define RCAN_RSCAN0CFID3_CFRTR (0x40000000u) +#define RCAN_RSCAN0CFID3_CFRTR_SHIFT (30u) +#define RCAN_RSCAN0CFID3_CFIDE (0x80000000u) +#define RCAN_RSCAN0CFID3_CFIDE_SHIFT (31u) +#define RCAN_RSCAN0CFPTR3_CFTS (0x0000FFFFu) +#define RCAN_RSCAN0CFPTR3_CFTS_SHIFT (0u) +#define RCAN_RSCAN0CFPTR3_CFPTR (0x0FFF0000u) +#define RCAN_RSCAN0CFPTR3_CFPTR_SHIFT (16u) +#define RCAN_RSCAN0CFPTR3_CFDLC (0xF0000000u) +#define RCAN_RSCAN0CFPTR3_CFDLC_SHIFT (28u) +#define RCAN_RSCAN0CFDF0_3_CFDB0 (0x000000FFu) +#define RCAN_RSCAN0CFDF0_3_CFDB0_SHIFT (0u) +#define RCAN_RSCAN0CFDF0_3_CFDB1 (0x0000FF00u) +#define RCAN_RSCAN0CFDF0_3_CFDB1_SHIFT (8u) +#define RCAN_RSCAN0CFDF0_3_CFDB2 (0x00FF0000u) +#define RCAN_RSCAN0CFDF0_3_CFDB2_SHIFT (16u) +#define RCAN_RSCAN0CFDF0_3_CFDB3 (0xFF000000u) +#define RCAN_RSCAN0CFDF0_3_CFDB3_SHIFT (24u) +#define RCAN_RSCAN0CFDF1_3_CFDB4 (0x000000FFu) +#define RCAN_RSCAN0CFDF1_3_CFDB4_SHIFT (0u) +#define RCAN_RSCAN0CFDF1_3_CFDB5 (0x0000FF00u) +#define RCAN_RSCAN0CFDF1_3_CFDB5_SHIFT (8u) +#define RCAN_RSCAN0CFDF1_3_CFDB6 (0x00FF0000u) +#define RCAN_RSCAN0CFDF1_3_CFDB6_SHIFT (16u) +#define RCAN_RSCAN0CFDF1_3_CFDB7 (0xFF000000u) +#define RCAN_RSCAN0CFDF1_3_CFDB7_SHIFT (24u) +#define RCAN_RSCAN0CFID4_CFID (0x1FFFFFFFu) +#define RCAN_RSCAN0CFID4_CFID_SHIFT (0u) +#define RCAN_RSCAN0CFID4_THLEN (0x20000000u) +#define RCAN_RSCAN0CFID4_THLEN_SHIFT (29u) +#define RCAN_RSCAN0CFID4_CFRTR (0x40000000u) +#define RCAN_RSCAN0CFID4_CFRTR_SHIFT (30u) +#define RCAN_RSCAN0CFID4_CFIDE (0x80000000u) +#define RCAN_RSCAN0CFID4_CFIDE_SHIFT (31u) +#define RCAN_RSCAN0CFPTR4_CFTS (0x0000FFFFu) +#define RCAN_RSCAN0CFPTR4_CFTS_SHIFT (0u) +#define RCAN_RSCAN0CFPTR4_CFPTR (0x0FFF0000u) +#define RCAN_RSCAN0CFPTR4_CFPTR_SHIFT (16u) +#define RCAN_RSCAN0CFPTR4_CFDLC (0xF0000000u) +#define RCAN_RSCAN0CFPTR4_CFDLC_SHIFT (28u) +#define RCAN_RSCAN0CFDF0_4_CFDB0 (0x000000FFu) +#define RCAN_RSCAN0CFDF0_4_CFDB0_SHIFT (0u) +#define RCAN_RSCAN0CFDF0_4_CFDB1 (0x0000FF00u) +#define RCAN_RSCAN0CFDF0_4_CFDB1_SHIFT (8u) +#define RCAN_RSCAN0CFDF0_4_CFDB2 (0x00FF0000u) +#define RCAN_RSCAN0CFDF0_4_CFDB2_SHIFT (16u) +#define RCAN_RSCAN0CFDF0_4_CFDB3 (0xFF000000u) +#define RCAN_RSCAN0CFDF0_4_CFDB3_SHIFT (24u) +#define RCAN_RSCAN0CFDF1_4_CFDB4 (0x000000FFu) +#define RCAN_RSCAN0CFDF1_4_CFDB4_SHIFT (0u) +#define RCAN_RSCAN0CFDF1_4_CFDB5 (0x0000FF00u) +#define RCAN_RSCAN0CFDF1_4_CFDB5_SHIFT (8u) +#define RCAN_RSCAN0CFDF1_4_CFDB6 (0x00FF0000u) +#define RCAN_RSCAN0CFDF1_4_CFDB6_SHIFT (16u) +#define RCAN_RSCAN0CFDF1_4_CFDB7 (0xFF000000u) +#define RCAN_RSCAN0CFDF1_4_CFDB7_SHIFT (24u) +#define RCAN_RSCAN0CFID5_CFID (0x1FFFFFFFu) +#define RCAN_RSCAN0CFID5_CFID_SHIFT (0u) +#define RCAN_RSCAN0CFID5_THLEN (0x20000000u) +#define RCAN_RSCAN0CFID5_THLEN_SHIFT (29u) +#define RCAN_RSCAN0CFID5_CFRTR (0x40000000u) +#define RCAN_RSCAN0CFID5_CFRTR_SHIFT (30u) +#define RCAN_RSCAN0CFID5_CFIDE (0x80000000u) +#define RCAN_RSCAN0CFID5_CFIDE_SHIFT (31u) +#define RCAN_RSCAN0CFPTR5_CFTS (0x0000FFFFu) +#define RCAN_RSCAN0CFPTR5_CFTS_SHIFT (0u) +#define RCAN_RSCAN0CFPTR5_CFPTR (0x0FFF0000u) +#define RCAN_RSCAN0CFPTR5_CFPTR_SHIFT (16u) +#define RCAN_RSCAN0CFPTR5_CFDLC (0xF0000000u) +#define RCAN_RSCAN0CFPTR5_CFDLC_SHIFT (28u) +#define RCAN_RSCAN0CFDF0_5_CFDB0 (0x000000FFu) +#define RCAN_RSCAN0CFDF0_5_CFDB0_SHIFT (0u) +#define RCAN_RSCAN0CFDF0_5_CFDB1 (0x0000FF00u) +#define RCAN_RSCAN0CFDF0_5_CFDB1_SHIFT (8u) +#define RCAN_RSCAN0CFDF0_5_CFDB2 (0x00FF0000u) +#define RCAN_RSCAN0CFDF0_5_CFDB2_SHIFT (16u) +#define RCAN_RSCAN0CFDF0_5_CFDB3 (0xFF000000u) +#define RCAN_RSCAN0CFDF0_5_CFDB3_SHIFT (24u) +#define RCAN_RSCAN0CFDF1_5_CFDB4 (0x000000FFu) +#define RCAN_RSCAN0CFDF1_5_CFDB4_SHIFT (0u) +#define RCAN_RSCAN0CFDF1_5_CFDB5 (0x0000FF00u) +#define RCAN_RSCAN0CFDF1_5_CFDB5_SHIFT (8u) +#define RCAN_RSCAN0CFDF1_5_CFDB6 (0x00FF0000u) +#define RCAN_RSCAN0CFDF1_5_CFDB6_SHIFT (16u) +#define RCAN_RSCAN0CFDF1_5_CFDB7 (0xFF000000u) +#define RCAN_RSCAN0CFDF1_5_CFDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID0_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID0_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID0_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID0_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID0_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID0_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID0_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID0_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR0_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR0_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR0_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR0_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_0_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_0_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_0_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_0_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_0_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_0_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_0_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_0_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_0_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_0_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_0_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_0_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_0_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_0_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_0_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_0_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID1_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID1_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID1_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID1_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID1_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID1_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID1_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID1_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR1_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR1_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR1_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR1_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_1_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_1_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_1_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_1_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_1_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_1_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_1_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_1_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_1_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_1_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_1_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_1_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_1_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_1_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_1_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_1_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID2_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID2_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID2_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID2_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID2_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID2_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID2_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID2_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR2_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR2_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR2_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR2_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_2_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_2_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_2_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_2_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_2_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_2_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_2_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_2_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_2_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_2_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_2_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_2_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_2_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_2_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_2_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_2_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID3_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID3_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID3_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID3_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID3_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID3_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID3_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID3_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR3_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR3_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR3_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR3_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_3_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_3_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_3_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_3_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_3_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_3_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_3_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_3_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_3_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_3_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_3_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_3_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_3_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_3_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_3_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_3_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID4_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID4_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID4_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID4_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID4_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID4_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID4_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID4_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR4_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR4_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR4_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR4_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_4_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_4_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_4_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_4_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_4_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_4_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_4_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_4_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_4_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_4_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_4_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_4_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_4_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_4_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_4_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_4_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID5_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID5_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID5_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID5_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID5_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID5_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID5_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID5_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR5_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR5_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR5_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR5_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_5_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_5_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_5_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_5_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_5_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_5_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_5_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_5_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_5_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_5_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_5_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_5_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_5_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_5_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_5_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_5_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID6_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID6_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID6_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID6_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID6_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID6_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID6_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID6_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR6_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR6_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR6_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR6_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_6_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_6_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_6_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_6_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_6_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_6_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_6_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_6_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_6_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_6_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_6_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_6_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_6_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_6_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_6_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_6_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID7_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID7_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID7_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID7_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID7_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID7_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID7_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID7_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR7_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR7_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR7_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR7_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_7_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_7_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_7_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_7_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_7_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_7_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_7_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_7_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_7_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_7_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_7_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_7_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_7_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_7_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_7_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_7_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID8_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID8_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID8_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID8_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID8_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID8_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID8_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID8_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR8_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR8_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR8_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR8_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_8_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_8_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_8_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_8_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_8_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_8_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_8_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_8_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_8_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_8_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_8_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_8_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_8_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_8_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_8_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_8_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID9_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID9_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID9_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID9_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID9_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID9_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID9_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID9_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR9_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR9_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR9_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR9_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_9_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_9_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_9_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_9_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_9_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_9_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_9_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_9_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_9_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_9_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_9_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_9_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_9_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_9_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_9_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_9_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID10_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID10_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID10_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID10_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID10_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID10_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID10_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID10_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR10_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR10_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR10_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR10_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_10_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_10_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_10_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_10_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_10_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_10_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_10_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_10_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_10_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_10_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_10_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_10_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_10_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_10_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_10_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_10_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID11_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID11_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID11_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID11_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID11_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID11_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID11_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID11_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR11_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR11_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR11_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR11_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_11_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_11_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_11_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_11_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_11_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_11_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_11_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_11_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_11_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_11_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_11_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_11_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_11_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_11_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_11_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_11_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID12_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID12_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID12_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID12_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID12_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID12_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID12_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID12_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR12_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR12_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR12_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR12_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_12_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_12_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_12_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_12_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_12_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_12_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_12_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_12_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_12_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_12_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_12_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_12_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_12_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_12_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_12_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_12_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID13_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID13_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID13_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID13_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID13_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID13_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID13_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID13_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR13_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR13_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR13_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR13_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_13_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_13_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_13_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_13_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_13_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_13_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_13_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_13_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_13_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_13_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_13_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_13_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_13_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_13_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_13_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_13_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID14_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID14_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID14_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID14_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID14_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID14_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID14_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID14_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR14_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR14_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR14_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR14_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_14_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_14_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_14_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_14_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_14_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_14_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_14_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_14_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_14_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_14_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_14_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_14_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_14_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_14_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_14_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_14_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID15_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID15_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID15_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID15_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID15_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID15_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID15_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID15_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR15_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR15_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR15_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR15_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_15_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_15_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_15_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_15_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_15_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_15_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_15_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_15_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_15_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_15_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_15_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_15_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_15_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_15_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_15_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_15_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID16_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID16_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID16_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID16_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID16_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID16_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID16_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID16_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR16_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR16_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR16_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR16_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_16_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_16_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_16_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_16_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_16_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_16_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_16_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_16_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_16_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_16_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_16_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_16_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_16_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_16_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_16_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_16_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID17_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID17_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID17_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID17_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID17_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID17_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID17_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID17_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR17_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR17_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR17_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR17_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_17_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_17_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_17_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_17_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_17_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_17_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_17_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_17_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_17_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_17_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_17_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_17_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_17_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_17_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_17_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_17_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID18_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID18_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID18_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID18_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID18_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID18_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID18_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID18_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR18_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR18_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR18_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR18_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_18_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_18_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_18_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_18_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_18_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_18_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_18_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_18_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_18_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_18_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_18_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_18_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_18_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_18_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_18_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_18_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID19_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID19_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID19_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID19_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID19_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID19_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID19_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID19_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR19_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR19_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR19_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR19_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_19_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_19_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_19_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_19_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_19_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_19_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_19_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_19_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_19_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_19_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_19_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_19_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_19_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_19_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_19_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_19_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID20_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID20_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID20_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID20_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID20_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID20_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID20_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID20_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR20_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR20_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR20_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR20_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_20_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_20_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_20_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_20_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_20_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_20_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_20_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_20_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_20_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_20_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_20_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_20_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_20_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_20_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_20_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_20_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID21_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID21_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID21_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID21_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID21_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID21_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID21_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID21_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR21_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR21_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR21_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR21_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_21_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_21_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_21_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_21_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_21_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_21_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_21_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_21_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_21_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_21_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_21_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_21_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_21_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_21_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_21_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_21_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID22_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID22_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID22_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID22_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID22_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID22_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID22_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID22_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR22_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR22_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR22_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR22_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_22_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_22_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_22_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_22_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_22_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_22_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_22_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_22_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_22_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_22_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_22_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_22_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_22_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_22_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_22_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_22_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID23_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID23_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID23_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID23_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID23_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID23_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID23_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID23_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR23_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR23_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR23_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR23_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_23_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_23_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_23_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_23_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_23_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_23_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_23_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_23_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_23_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_23_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_23_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_23_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_23_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_23_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_23_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_23_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID24_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID24_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID24_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID24_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID24_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID24_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID24_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID24_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR24_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR24_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR24_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR24_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_24_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_24_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_24_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_24_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_24_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_24_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_24_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_24_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_24_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_24_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_24_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_24_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_24_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_24_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_24_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_24_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID25_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID25_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID25_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID25_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID25_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID25_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID25_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID25_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR25_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR25_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR25_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR25_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_25_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_25_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_25_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_25_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_25_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_25_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_25_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_25_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_25_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_25_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_25_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_25_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_25_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_25_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_25_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_25_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID26_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID26_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID26_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID26_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID26_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID26_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID26_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID26_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR26_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR26_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR26_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR26_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_26_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_26_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_26_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_26_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_26_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_26_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_26_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_26_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_26_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_26_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_26_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_26_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_26_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_26_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_26_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_26_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID27_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID27_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID27_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID27_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID27_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID27_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID27_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID27_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR27_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR27_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR27_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR27_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_27_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_27_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_27_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_27_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_27_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_27_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_27_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_27_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_27_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_27_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_27_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_27_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_27_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_27_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_27_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_27_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID28_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID28_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID28_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID28_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID28_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID28_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID28_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID28_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR28_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR28_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR28_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR28_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_28_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_28_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_28_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_28_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_28_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_28_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_28_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_28_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_28_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_28_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_28_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_28_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_28_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_28_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_28_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_28_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID29_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID29_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID29_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID29_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID29_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID29_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID29_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID29_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR29_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR29_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR29_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR29_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_29_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_29_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_29_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_29_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_29_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_29_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_29_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_29_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_29_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_29_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_29_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_29_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_29_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_29_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_29_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_29_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID30_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID30_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID30_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID30_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID30_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID30_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID30_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID30_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR30_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR30_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR30_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR30_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_30_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_30_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_30_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_30_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_30_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_30_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_30_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_30_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_30_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_30_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_30_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_30_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_30_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_30_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_30_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_30_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0TMID31_TMID (0x1FFFFFFFu) +#define RCAN_RSCAN0TMID31_TMID_SHIFT (0u) +#define RCAN_RSCAN0TMID31_THLEN (0x20000000u) +#define RCAN_RSCAN0TMID31_THLEN_SHIFT (29u) +#define RCAN_RSCAN0TMID31_TMRTR (0x40000000u) +#define RCAN_RSCAN0TMID31_TMRTR_SHIFT (30u) +#define RCAN_RSCAN0TMID31_TMIDE (0x80000000u) +#define RCAN_RSCAN0TMID31_TMIDE_SHIFT (31u) +#define RCAN_RSCAN0TMPTR31_TMPTR (0x00FF0000u) +#define RCAN_RSCAN0TMPTR31_TMPTR_SHIFT (16u) +#define RCAN_RSCAN0TMPTR31_TMDLC (0xF0000000u) +#define RCAN_RSCAN0TMPTR31_TMDLC_SHIFT (28u) +#define RCAN_RSCAN0TMDF0_31_TMDB0 (0x000000FFu) +#define RCAN_RSCAN0TMDF0_31_TMDB0_SHIFT (0u) +#define RCAN_RSCAN0TMDF0_31_TMDB1 (0x0000FF00u) +#define RCAN_RSCAN0TMDF0_31_TMDB1_SHIFT (8u) +#define RCAN_RSCAN0TMDF0_31_TMDB2 (0x00FF0000u) +#define RCAN_RSCAN0TMDF0_31_TMDB2_SHIFT (16u) +#define RCAN_RSCAN0TMDF0_31_TMDB3 (0xFF000000u) +#define RCAN_RSCAN0TMDF0_31_TMDB3_SHIFT (24u) +#define RCAN_RSCAN0TMDF1_31_TMDB4 (0x000000FFu) +#define RCAN_RSCAN0TMDF1_31_TMDB4_SHIFT (0u) +#define RCAN_RSCAN0TMDF1_31_TMDB5 (0x0000FF00u) +#define RCAN_RSCAN0TMDF1_31_TMDB5_SHIFT (8u) +#define RCAN_RSCAN0TMDF1_31_TMDB6 (0x00FF0000u) +#define RCAN_RSCAN0TMDF1_31_TMDB6_SHIFT (16u) +#define RCAN_RSCAN0TMDF1_31_TMDB7 (0xFF000000u) +#define RCAN_RSCAN0TMDF1_31_TMDB7_SHIFT (24u) +#define RCAN_RSCAN0THLACC0_BT (0x00000007u) +#define RCAN_RSCAN0THLACC0_BT_SHIFT (0u) +#define RCAN_RSCAN0THLACC0_BN (0x00000078u) +#define RCAN_RSCAN0THLACC0_BN_SHIFT (3u) +#define RCAN_RSCAN0THLACC0_TID (0x0000FF00u) +#define RCAN_RSCAN0THLACC0_TID_SHIFT (8u) +#define RCAN_RSCAN0THLACC0_TMTS (0xFFFF0000u) +#define RCAN_RSCAN0THLACC0_TMTS_SHIFT (16u) +#define RCAN_RSCAN0THLACC1_BT (0x00000007u) +#define RCAN_RSCAN0THLACC1_BT_SHIFT (0u) +#define RCAN_RSCAN0THLACC1_BN (0x00000078u) +#define RCAN_RSCAN0THLACC1_BN_SHIFT (3u) +#define RCAN_RSCAN0THLACC1_TID (0x0000FF00u) +#define RCAN_RSCAN0THLACC1_TID_SHIFT (8u) +#define RCAN_RSCAN0THLACC1_TMTS (0xFFFF0000u) +#define RCAN_RSCAN0THLACC1_TMTS_SHIFT (16u) +#define RCAN_RSCAN0RPGACC0_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC0_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC1_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC1_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC2_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC2_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC3_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC3_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC4_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC4_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC5_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC5_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC6_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC6_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC7_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC7_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC8_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC8_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC9_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC9_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC10_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC10_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC11_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC11_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC12_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC12_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC13_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC13_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC14_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC14_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC15_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC15_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC16_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC16_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC17_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC17_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC18_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC18_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC19_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC19_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC20_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC20_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC21_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC21_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC22_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC22_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC23_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC23_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC24_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC24_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC25_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC25_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC26_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC26_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC27_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC27_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC28_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC28_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC29_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC29_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC30_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC30_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC31_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC31_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC32_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC32_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC33_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC33_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC34_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC34_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC35_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC35_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC36_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC36_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC37_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC37_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC38_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC38_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC39_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC39_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC40_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC40_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC41_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC41_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC42_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC42_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC43_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC43_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC44_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC44_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC45_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC45_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC46_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC46_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC47_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC47_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC48_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC48_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC49_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC49_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC50_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC50_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC51_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC51_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC52_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC52_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC53_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC53_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC54_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC54_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC55_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC55_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC56_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC56_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC57_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC57_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC58_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC58_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC59_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC59_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC60_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC60_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC61_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC61_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC62_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC62_RDTA_SHIFT (0u) +#define RCAN_RSCAN0RPGACC63_RDTA (0xFFFFFFFFu) +#define RCAN_RSCAN0RPGACC63_RDTA_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcanfd_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcanfd_iobitmask.h new file mode 100644 index 0000000..e6930d2 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rcanfd_iobitmask.h @@ -0,0 +1,8260 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef RCANFD_IOBITMASK_H +#define RCANFD_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define RCANFD_RSCFD0CFDC0NCFG_NBRP (0x000003FFu) +#define RCANFD_RSCFD0CFDC0NCFG_NBRP_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0NCFG_NSJW (0x0000F800u) +#define RCANFD_RSCFD0CFDC0NCFG_NSJW_SHIFT (11u) +#define RCANFD_RSCFD0CFDC0NCFG_NTSEG1 (0x007F0000u) +#define RCANFD_RSCFD0CFDC0NCFG_NTSEG1_SHIFT (16u) +#define RCANFD_RSCFD0CFDC0NCFG_NTSEG2 (0x1F000000u) +#define RCANFD_RSCFD0CFDC0NCFG_NTSEG2_SHIFT (24u) +#define RCANFD_RSCFD0CFDC0CTR_CHMDC (0x00000003u) +#define RCANFD_RSCFD0CFDC0CTR_CHMDC_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0CTR_CSLPR (0x00000004u) +#define RCANFD_RSCFD0CFDC0CTR_CSLPR_SHIFT (2u) +#define RCANFD_RSCFD0CFDC0CTR_RTBO (0x00000008u) +#define RCANFD_RSCFD0CFDC0CTR_RTBO_SHIFT (3u) +#define RCANFD_RSCFD0CFDC0CTR_BEIE (0x00000100u) +#define RCANFD_RSCFD0CFDC0CTR_BEIE_SHIFT (8u) +#define RCANFD_RSCFD0CFDC0CTR_EWIE (0x00000200u) +#define RCANFD_RSCFD0CFDC0CTR_EWIE_SHIFT (9u) +#define RCANFD_RSCFD0CFDC0CTR_EPIE (0x00000400u) +#define RCANFD_RSCFD0CFDC0CTR_EPIE_SHIFT (10u) +#define RCANFD_RSCFD0CFDC0CTR_BOEIE (0x00000800u) +#define RCANFD_RSCFD0CFDC0CTR_BOEIE_SHIFT (11u) +#define RCANFD_RSCFD0CFDC0CTR_BORIE (0x00001000u) +#define RCANFD_RSCFD0CFDC0CTR_BORIE_SHIFT (12u) +#define RCANFD_RSCFD0CFDC0CTR_OLIE (0x00002000u) +#define RCANFD_RSCFD0CFDC0CTR_OLIE_SHIFT (13u) +#define RCANFD_RSCFD0CFDC0CTR_BLIE (0x00004000u) +#define RCANFD_RSCFD0CFDC0CTR_BLIE_SHIFT (14u) +#define RCANFD_RSCFD0CFDC0CTR_ALIE (0x00008000u) +#define RCANFD_RSCFD0CFDC0CTR_ALIE_SHIFT (15u) +#define RCANFD_RSCFD0CFDC0CTR_TAIE (0x00010000u) +#define RCANFD_RSCFD0CFDC0CTR_TAIE_SHIFT (16u) +#define RCANFD_RSCFD0CFDC0CTR_EOCOIE (0x00020000u) +#define RCANFD_RSCFD0CFDC0CTR_EOCOIE_SHIFT (17u) +#define RCANFD_RSCFD0CFDC0CTR_SOCOIE (0x00040000u) +#define RCANFD_RSCFD0CFDC0CTR_SOCOIE_SHIFT (18u) +#define RCANFD_RSCFD0CFDC0CTR_TDCVFIE (0x00080000u) +#define RCANFD_RSCFD0CFDC0CTR_TDCVFIE_SHIFT (19u) +#define RCANFD_RSCFD0CFDC0CTR_BOM (0x00600000u) +#define RCANFD_RSCFD0CFDC0CTR_BOM_SHIFT (21u) +#define RCANFD_RSCFD0CFDC0CTR_ERRD (0x00800000u) +#define RCANFD_RSCFD0CFDC0CTR_ERRD_SHIFT (23u) +#define RCANFD_RSCFD0CFDC0CTR_CTME (0x01000000u) +#define RCANFD_RSCFD0CFDC0CTR_CTME_SHIFT (24u) +#define RCANFD_RSCFD0CFDC0CTR_CTMS (0x06000000u) +#define RCANFD_RSCFD0CFDC0CTR_CTMS_SHIFT (25u) +#define RCANFD_RSCFD0CFDC0CTR_CRCT (0x40000000u) +#define RCANFD_RSCFD0CFDC0CTR_CRCT_SHIFT (30u) +#define RCANFD_RSCFD0CFDC0CTR_ROM (0x80000000u) +#define RCANFD_RSCFD0CFDC0CTR_ROM_SHIFT (31u) +#define RCANFD_RSCFD0CFDC0STS_CRSTSTS (0x00000001u) +#define RCANFD_RSCFD0CFDC0STS_CRSTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0STS_CHLTSTS (0x00000002u) +#define RCANFD_RSCFD0CFDC0STS_CHLTSTS_SHIFT (1u) +#define RCANFD_RSCFD0CFDC0STS_CSLPSTS (0x00000004u) +#define RCANFD_RSCFD0CFDC0STS_CSLPSTS_SHIFT (2u) +#define RCANFD_RSCFD0CFDC0STS_EPSTS (0x00000008u) +#define RCANFD_RSCFD0CFDC0STS_EPSTS_SHIFT (3u) +#define RCANFD_RSCFD0CFDC0STS_BOSTS (0x00000010u) +#define RCANFD_RSCFD0CFDC0STS_BOSTS_SHIFT (4u) +#define RCANFD_RSCFD0CFDC0STS_TRMSTS (0x00000020u) +#define RCANFD_RSCFD0CFDC0STS_TRMSTS_SHIFT (5u) +#define RCANFD_RSCFD0CFDC0STS_RECSTS (0x00000040u) +#define RCANFD_RSCFD0CFDC0STS_RECSTS_SHIFT (6u) +#define RCANFD_RSCFD0CFDC0STS_COMSTS (0x00000080u) +#define RCANFD_RSCFD0CFDC0STS_COMSTS_SHIFT (7u) +#define RCANFD_RSCFD0CFDC0STS_ESIF (0x00000100u) +#define RCANFD_RSCFD0CFDC0STS_ESIF_SHIFT (8u) +#define RCANFD_RSCFD0CFDC0STS_REC (0x00FF0000u) +#define RCANFD_RSCFD0CFDC0STS_REC_SHIFT (16u) +#define RCANFD_RSCFD0CFDC0STS_TEC (0xFF000000u) +#define RCANFD_RSCFD0CFDC0STS_TEC_SHIFT (24u) +#define RCANFD_RSCFD0CFDC0ERFL_BEF (0x00000001u) +#define RCANFD_RSCFD0CFDC0ERFL_BEF_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0ERFL_EWF (0x00000002u) +#define RCANFD_RSCFD0CFDC0ERFL_EWF_SHIFT (1u) +#define RCANFD_RSCFD0CFDC0ERFL_EPF (0x00000004u) +#define RCANFD_RSCFD0CFDC0ERFL_EPF_SHIFT (2u) +#define RCANFD_RSCFD0CFDC0ERFL_BOEF (0x00000008u) +#define RCANFD_RSCFD0CFDC0ERFL_BOEF_SHIFT (3u) +#define RCANFD_RSCFD0CFDC0ERFL_BORF (0x00000010u) +#define RCANFD_RSCFD0CFDC0ERFL_BORF_SHIFT (4u) +#define RCANFD_RSCFD0CFDC0ERFL_OVLF (0x00000020u) +#define RCANFD_RSCFD0CFDC0ERFL_OVLF_SHIFT (5u) +#define RCANFD_RSCFD0CFDC0ERFL_BLF (0x00000040u) +#define RCANFD_RSCFD0CFDC0ERFL_BLF_SHIFT (6u) +#define RCANFD_RSCFD0CFDC0ERFL_ALF (0x00000080u) +#define RCANFD_RSCFD0CFDC0ERFL_ALF_SHIFT (7u) +#define RCANFD_RSCFD0CFDC0ERFL_SERR (0x00000100u) +#define RCANFD_RSCFD0CFDC0ERFL_SERR_SHIFT (8u) +#define RCANFD_RSCFD0CFDC0ERFL_FERR (0x00000200u) +#define RCANFD_RSCFD0CFDC0ERFL_FERR_SHIFT (9u) +#define RCANFD_RSCFD0CFDC0ERFL_AERR (0x00000400u) +#define RCANFD_RSCFD0CFDC0ERFL_AERR_SHIFT (10u) +#define RCANFD_RSCFD0CFDC0ERFL_CERR (0x00000800u) +#define RCANFD_RSCFD0CFDC0ERFL_CERR_SHIFT (11u) +#define RCANFD_RSCFD0CFDC0ERFL_B1ERR (0x00001000u) +#define RCANFD_RSCFD0CFDC0ERFL_B1ERR_SHIFT (12u) +#define RCANFD_RSCFD0CFDC0ERFL_B0ERR (0x00002000u) +#define RCANFD_RSCFD0CFDC0ERFL_B0ERR_SHIFT (13u) +#define RCANFD_RSCFD0CFDC0ERFL_ADERR (0x00004000u) +#define RCANFD_RSCFD0CFDC0ERFL_ADERR_SHIFT (14u) +#define RCANFD_RSCFD0CFDC0ERFL_CRCREG (0x7FFF0000u) +#define RCANFD_RSCFD0CFDC0ERFL_CRCREG_SHIFT (16u) +#define RCANFD_RSCFD0CFDC1NCFG_NBRP (0x000003FFu) +#define RCANFD_RSCFD0CFDC1NCFG_NBRP_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1NCFG_NSJW (0x0000F800u) +#define RCANFD_RSCFD0CFDC1NCFG_NSJW_SHIFT (11u) +#define RCANFD_RSCFD0CFDC1NCFG_NTSEG1 (0x007F0000u) +#define RCANFD_RSCFD0CFDC1NCFG_NTSEG1_SHIFT (16u) +#define RCANFD_RSCFD0CFDC1NCFG_NTSEG2 (0x1F000000u) +#define RCANFD_RSCFD0CFDC1NCFG_NTSEG2_SHIFT (24u) +#define RCANFD_RSCFD0CFDC1CTR_CHMDC (0x00000003u) +#define RCANFD_RSCFD0CFDC1CTR_CHMDC_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1CTR_CSLPR (0x00000004u) +#define RCANFD_RSCFD0CFDC1CTR_CSLPR_SHIFT (2u) +#define RCANFD_RSCFD0CFDC1CTR_RTBO (0x00000008u) +#define RCANFD_RSCFD0CFDC1CTR_RTBO_SHIFT (3u) +#define RCANFD_RSCFD0CFDC1CTR_BEIE (0x00000100u) +#define RCANFD_RSCFD0CFDC1CTR_BEIE_SHIFT (8u) +#define RCANFD_RSCFD0CFDC1CTR_EWIE (0x00000200u) +#define RCANFD_RSCFD0CFDC1CTR_EWIE_SHIFT (9u) +#define RCANFD_RSCFD0CFDC1CTR_EPIE (0x00000400u) +#define RCANFD_RSCFD0CFDC1CTR_EPIE_SHIFT (10u) +#define RCANFD_RSCFD0CFDC1CTR_BOEIE (0x00000800u) +#define RCANFD_RSCFD0CFDC1CTR_BOEIE_SHIFT (11u) +#define RCANFD_RSCFD0CFDC1CTR_BORIE (0x00001000u) +#define RCANFD_RSCFD0CFDC1CTR_BORIE_SHIFT (12u) +#define RCANFD_RSCFD0CFDC1CTR_OLIE (0x00002000u) +#define RCANFD_RSCFD0CFDC1CTR_OLIE_SHIFT (13u) +#define RCANFD_RSCFD0CFDC1CTR_BLIE (0x00004000u) +#define RCANFD_RSCFD0CFDC1CTR_BLIE_SHIFT (14u) +#define RCANFD_RSCFD0CFDC1CTR_ALIE (0x00008000u) +#define RCANFD_RSCFD0CFDC1CTR_ALIE_SHIFT (15u) +#define RCANFD_RSCFD0CFDC1CTR_TAIE (0x00010000u) +#define RCANFD_RSCFD0CFDC1CTR_TAIE_SHIFT (16u) +#define RCANFD_RSCFD0CFDC1CTR_EOCOIE (0x00020000u) +#define RCANFD_RSCFD0CFDC1CTR_EOCOIE_SHIFT (17u) +#define RCANFD_RSCFD0CFDC1CTR_SOCOIE (0x00040000u) +#define RCANFD_RSCFD0CFDC1CTR_SOCOIE_SHIFT (18u) +#define RCANFD_RSCFD0CFDC1CTR_TDCVFIE (0x00080000u) +#define RCANFD_RSCFD0CFDC1CTR_TDCVFIE_SHIFT (19u) +#define RCANFD_RSCFD0CFDC1CTR_BOM (0x00600000u) +#define RCANFD_RSCFD0CFDC1CTR_BOM_SHIFT (21u) +#define RCANFD_RSCFD0CFDC1CTR_ERRD (0x00800000u) +#define RCANFD_RSCFD0CFDC1CTR_ERRD_SHIFT (23u) +#define RCANFD_RSCFD0CFDC1CTR_CTME (0x01000000u) +#define RCANFD_RSCFD0CFDC1CTR_CTME_SHIFT (24u) +#define RCANFD_RSCFD0CFDC1CTR_CTMS (0x06000000u) +#define RCANFD_RSCFD0CFDC1CTR_CTMS_SHIFT (25u) +#define RCANFD_RSCFD0CFDC1CTR_CRCT (0x40000000u) +#define RCANFD_RSCFD0CFDC1CTR_CRCT_SHIFT (30u) +#define RCANFD_RSCFD0CFDC1CTR_ROM (0x80000000u) +#define RCANFD_RSCFD0CFDC1CTR_ROM_SHIFT (31u) +#define RCANFD_RSCFD0CFDC1STS_CRSTSTS (0x00000001u) +#define RCANFD_RSCFD0CFDC1STS_CRSTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1STS_CHLTSTS (0x00000002u) +#define RCANFD_RSCFD0CFDC1STS_CHLTSTS_SHIFT (1u) +#define RCANFD_RSCFD0CFDC1STS_CSLPSTS (0x00000004u) +#define RCANFD_RSCFD0CFDC1STS_CSLPSTS_SHIFT (2u) +#define RCANFD_RSCFD0CFDC1STS_EPSTS (0x00000008u) +#define RCANFD_RSCFD0CFDC1STS_EPSTS_SHIFT (3u) +#define RCANFD_RSCFD0CFDC1STS_BOSTS (0x00000010u) +#define RCANFD_RSCFD0CFDC1STS_BOSTS_SHIFT (4u) +#define RCANFD_RSCFD0CFDC1STS_TRMSTS (0x00000020u) +#define RCANFD_RSCFD0CFDC1STS_TRMSTS_SHIFT (5u) +#define RCANFD_RSCFD0CFDC1STS_RECSTS (0x00000040u) +#define RCANFD_RSCFD0CFDC1STS_RECSTS_SHIFT (6u) +#define RCANFD_RSCFD0CFDC1STS_COMSTS (0x00000080u) +#define RCANFD_RSCFD0CFDC1STS_COMSTS_SHIFT (7u) +#define RCANFD_RSCFD0CFDC1STS_ESIF (0x00000100u) +#define RCANFD_RSCFD0CFDC1STS_ESIF_SHIFT (8u) +#define RCANFD_RSCFD0CFDC1STS_REC (0x00FF0000u) +#define RCANFD_RSCFD0CFDC1STS_REC_SHIFT (16u) +#define RCANFD_RSCFD0CFDC1STS_TEC (0xFF000000u) +#define RCANFD_RSCFD0CFDC1STS_TEC_SHIFT (24u) +#define RCANFD_RSCFD0CFDC1ERFL_BEF (0x00000001u) +#define RCANFD_RSCFD0CFDC1ERFL_BEF_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1ERFL_EWF (0x00000002u) +#define RCANFD_RSCFD0CFDC1ERFL_EWF_SHIFT (1u) +#define RCANFD_RSCFD0CFDC1ERFL_EPF (0x00000004u) +#define RCANFD_RSCFD0CFDC1ERFL_EPF_SHIFT (2u) +#define RCANFD_RSCFD0CFDC1ERFL_BOEF (0x00000008u) +#define RCANFD_RSCFD0CFDC1ERFL_BOEF_SHIFT (3u) +#define RCANFD_RSCFD0CFDC1ERFL_BORF (0x00000010u) +#define RCANFD_RSCFD0CFDC1ERFL_BORF_SHIFT (4u) +#define RCANFD_RSCFD0CFDC1ERFL_OVLF (0x00000020u) +#define RCANFD_RSCFD0CFDC1ERFL_OVLF_SHIFT (5u) +#define RCANFD_RSCFD0CFDC1ERFL_BLF (0x00000040u) +#define RCANFD_RSCFD0CFDC1ERFL_BLF_SHIFT (6u) +#define RCANFD_RSCFD0CFDC1ERFL_ALF (0x00000080u) +#define RCANFD_RSCFD0CFDC1ERFL_ALF_SHIFT (7u) +#define RCANFD_RSCFD0CFDC1ERFL_SERR (0x00000100u) +#define RCANFD_RSCFD0CFDC1ERFL_SERR_SHIFT (8u) +#define RCANFD_RSCFD0CFDC1ERFL_FERR (0x00000200u) +#define RCANFD_RSCFD0CFDC1ERFL_FERR_SHIFT (9u) +#define RCANFD_RSCFD0CFDC1ERFL_AERR (0x00000400u) +#define RCANFD_RSCFD0CFDC1ERFL_AERR_SHIFT (10u) +#define RCANFD_RSCFD0CFDC1ERFL_CERR (0x00000800u) +#define RCANFD_RSCFD0CFDC1ERFL_CERR_SHIFT (11u) +#define RCANFD_RSCFD0CFDC1ERFL_B1ERR (0x00001000u) +#define RCANFD_RSCFD0CFDC1ERFL_B1ERR_SHIFT (12u) +#define RCANFD_RSCFD0CFDC1ERFL_B0ERR (0x00002000u) +#define RCANFD_RSCFD0CFDC1ERFL_B0ERR_SHIFT (13u) +#define RCANFD_RSCFD0CFDC1ERFL_ADERR (0x00004000u) +#define RCANFD_RSCFD0CFDC1ERFL_ADERR_SHIFT (14u) +#define RCANFD_RSCFD0CFDC1ERFL_CRCREG (0x7FFF0000u) +#define RCANFD_RSCFD0CFDC1ERFL_CRCREG_SHIFT (16u) +#define RCANFD_RSCFD0CFDGCFG_TPRI (0x00000001u) +#define RCANFD_RSCFD0CFDGCFG_TPRI_SHIFT (0u) +#define RCANFD_RSCFD0CFDGCFG_DCE (0x00000002u) +#define RCANFD_RSCFD0CFDGCFG_DCE_SHIFT (1u) +#define RCANFD_RSCFD0CFDGCFG_DRE (0x00000004u) +#define RCANFD_RSCFD0CFDGCFG_DRE_SHIFT (2u) +#define RCANFD_RSCFD0CFDGCFG_MME (0x00000008u) +#define RCANFD_RSCFD0CFDGCFG_MME_SHIFT (3u) +#define RCANFD_RSCFD0CFDGCFG_DCS (0x00000010u) +#define RCANFD_RSCFD0CFDGCFG_DCS_SHIFT (4u) +#define RCANFD_RSCFD0CFDGCFG_CMPOC (0x00000020u) +#define RCANFD_RSCFD0CFDGCFG_CMPOC_SHIFT (5u) +#define RCANFD_RSCFD0CFDGCFG_TSP (0x00000F00u) +#define RCANFD_RSCFD0CFDGCFG_TSP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGCFG_TSSS (0x00001000u) +#define RCANFD_RSCFD0CFDGCFG_TSSS_SHIFT (12u) +#define RCANFD_RSCFD0CFDGCFG_TSBTCS (0x0000E000u) +#define RCANFD_RSCFD0CFDGCFG_TSBTCS_SHIFT (13u) +#define RCANFD_RSCFD0CFDGCFG_ITRCP (0xFFFF0000u) +#define RCANFD_RSCFD0CFDGCFG_ITRCP_SHIFT (16u) +#define RCANFD_RSCFD0CFDGCTR_GMDC (0x00000003u) +#define RCANFD_RSCFD0CFDGCTR_GMDC_SHIFT (0u) +#define RCANFD_RSCFD0CFDGCTR_GSLPR (0x00000004u) +#define RCANFD_RSCFD0CFDGCTR_GSLPR_SHIFT (2u) +#define RCANFD_RSCFD0CFDGCTR_DEIE (0x00000100u) +#define RCANFD_RSCFD0CFDGCTR_DEIE_SHIFT (8u) +#define RCANFD_RSCFD0CFDGCTR_MEIE (0x00000200u) +#define RCANFD_RSCFD0CFDGCTR_MEIE_SHIFT (9u) +#define RCANFD_RSCFD0CFDGCTR_THLEIE (0x00000400u) +#define RCANFD_RSCFD0CFDGCTR_THLEIE_SHIFT (10u) +#define RCANFD_RSCFD0CFDGCTR_CMPOFIE (0x00000800u) +#define RCANFD_RSCFD0CFDGCTR_CMPOFIE_SHIFT (11u) +#define RCANFD_RSCFD0CFDGCTR_TSRST (0x00010000u) +#define RCANFD_RSCFD0CFDGCTR_TSRST_SHIFT (16u) +#define RCANFD_RSCFD0CFDGSTS_GRSTSTS (0x00000001u) +#define RCANFD_RSCFD0CFDGSTS_GRSTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDGSTS_GHLTSTS (0x00000002u) +#define RCANFD_RSCFD0CFDGSTS_GHLTSTS_SHIFT (1u) +#define RCANFD_RSCFD0CFDGSTS_GSLPSTS (0x00000004u) +#define RCANFD_RSCFD0CFDGSTS_GSLPSTS_SHIFT (2u) +#define RCANFD_RSCFD0CFDGSTS_GRAMINIT (0x00000008u) +#define RCANFD_RSCFD0CFDGSTS_GRAMINIT_SHIFT (3u) +#define RCANFD_RSCFD0CFDGERFL_DEF (0x00000001u) +#define RCANFD_RSCFD0CFDGERFL_DEF_SHIFT (0u) +#define RCANFD_RSCFD0CFDGERFL_MES (0x00000002u) +#define RCANFD_RSCFD0CFDGERFL_MES_SHIFT (1u) +#define RCANFD_RSCFD0CFDGERFL_THLES (0x00000004u) +#define RCANFD_RSCFD0CFDGERFL_THLES_SHIFT (2u) +#define RCANFD_RSCFD0CFDGERFL_CMPOF (0x00000008u) +#define RCANFD_RSCFD0CFDGERFL_CMPOF_SHIFT (3u) +#define RCANFD_RSCFD0CFDGTSC_TS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDGTSC_TS_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLECTR_AFLPN (0x0000001Fu) +#define RCANFD_RSCFD0CFDGAFLECTR_AFLPN_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLECTR_AFLDAE (0x00000100u) +#define RCANFD_RSCFD0CFDGAFLECTR_AFLDAE_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLCFG0_RNC1 (0x00FF0000u) +#define RCANFD_RSCFD0CFDGAFLCFG0_RNC1_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLCFG0_RNC0 (0xFF000000u) +#define RCANFD_RSCFD0CFDGAFLCFG0_RNC0_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMNB_NRXMB (0x000000FFu) +#define RCANFD_RSCFD0CFDRMNB_NRXMB_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMNB_RMPLS (0x00000300u) +#define RCANFD_RSCFD0CFDRMNB_RMPLS_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMND0_RMNS0 (0x00000001u) +#define RCANFD_RSCFD0CFDRMND0_RMNS0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMND0_RMNS1 (0x00000002u) +#define RCANFD_RSCFD0CFDRMND0_RMNS1_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMND0_RMNS2 (0x00000004u) +#define RCANFD_RSCFD0CFDRMND0_RMNS2_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMND0_RMNS3 (0x00000008u) +#define RCANFD_RSCFD0CFDRMND0_RMNS3_SHIFT (3u) +#define RCANFD_RSCFD0CFDRMND0_RMNS4 (0x00000010u) +#define RCANFD_RSCFD0CFDRMND0_RMNS4_SHIFT (4u) +#define RCANFD_RSCFD0CFDRMND0_RMNS5 (0x00000020u) +#define RCANFD_RSCFD0CFDRMND0_RMNS5_SHIFT (5u) +#define RCANFD_RSCFD0CFDRMND0_RMNS6 (0x00000040u) +#define RCANFD_RSCFD0CFDRMND0_RMNS6_SHIFT (6u) +#define RCANFD_RSCFD0CFDRMND0_RMNS7 (0x00000080u) +#define RCANFD_RSCFD0CFDRMND0_RMNS7_SHIFT (7u) +#define RCANFD_RSCFD0CFDRMND0_RMNS8 (0x00000100u) +#define RCANFD_RSCFD0CFDRMND0_RMNS8_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMND0_RMNS9 (0x00000200u) +#define RCANFD_RSCFD0CFDRMND0_RMNS9_SHIFT (9u) +#define RCANFD_RSCFD0CFDRMND0_RMNS10 (0x00000400u) +#define RCANFD_RSCFD0CFDRMND0_RMNS10_SHIFT (10u) +#define RCANFD_RSCFD0CFDRMND0_RMNS11 (0x00000800u) +#define RCANFD_RSCFD0CFDRMND0_RMNS11_SHIFT (11u) +#define RCANFD_RSCFD0CFDRMND0_RMNS12 (0x00001000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS12_SHIFT (12u) +#define RCANFD_RSCFD0CFDRMND0_RMNS13 (0x00002000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS13_SHIFT (13u) +#define RCANFD_RSCFD0CFDRMND0_RMNS14 (0x00004000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS14_SHIFT (14u) +#define RCANFD_RSCFD0CFDRMND0_RMNS15 (0x00008000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS15_SHIFT (15u) +#define RCANFD_RSCFD0CFDRMND0_RMNS16 (0x00010000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS16_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMND0_RMNS17 (0x00020000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS17_SHIFT (17u) +#define RCANFD_RSCFD0CFDRMND0_RMNS18 (0x00040000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS18_SHIFT (18u) +#define RCANFD_RSCFD0CFDRMND0_RMNS19 (0x00080000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS19_SHIFT (19u) +#define RCANFD_RSCFD0CFDRMND0_RMNS20 (0x00100000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS20_SHIFT (20u) +#define RCANFD_RSCFD0CFDRMND0_RMNS21 (0x00200000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS21_SHIFT (21u) +#define RCANFD_RSCFD0CFDRMND0_RMNS22 (0x00400000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS22_SHIFT (22u) +#define RCANFD_RSCFD0CFDRMND0_RMNS23 (0x00800000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS23_SHIFT (23u) +#define RCANFD_RSCFD0CFDRMND0_RMNS24 (0x01000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS24_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMND0_RMNS25 (0x02000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS25_SHIFT (25u) +#define RCANFD_RSCFD0CFDRMND0_RMNS26 (0x04000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS26_SHIFT (26u) +#define RCANFD_RSCFD0CFDRMND0_RMNS27 (0x08000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS27_SHIFT (27u) +#define RCANFD_RSCFD0CFDRMND0_RMNS28 (0x10000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS28_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMND0_RMNS29 (0x20000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS29_SHIFT (29u) +#define RCANFD_RSCFD0CFDRMND0_RMNS30 (0x40000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS30_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMND0_RMNS31 (0x80000000u) +#define RCANFD_RSCFD0CFDRMND0_RMNS31_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFCC0_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC0_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC0_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC0_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC0_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC0_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC0_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC0_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC0_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC0_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC0_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC0_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFCC1_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC1_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC1_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC1_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC1_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC1_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC1_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC1_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC1_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC1_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC1_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC1_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFCC2_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC2_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC2_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC2_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC2_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC2_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC2_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC2_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC2_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC2_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC2_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC2_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFCC3_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC3_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC3_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC3_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC3_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC3_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC3_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC3_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC3_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC3_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC3_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC3_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFCC4_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC4_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC4_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC4_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC4_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC4_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC4_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC4_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC4_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC4_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC4_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC4_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFCC5_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC5_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC5_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC5_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC5_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC5_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC5_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC5_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC5_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC5_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC5_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC5_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFCC6_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC6_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC6_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC6_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC6_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC6_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC6_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC6_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC6_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC6_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC6_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC6_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFCC7_RFE (0x00000001u) +#define RCANFD_RSCFD0CFDRFCC7_RFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFCC7_RFIE (0x00000002u) +#define RCANFD_RSCFD0CFDRFCC7_RFIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFCC7_RFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDRFCC7_RFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFCC7_RFDC (0x00000700u) +#define RCANFD_RSCFD0CFDRFCC7_RFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFCC7_RFIM (0x00001000u) +#define RCANFD_RSCFD0CFDRFCC7_RFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDRFCC7_RFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDRFCC7_RFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFSTS0_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS0_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS0_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS0_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS0_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS0_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS0_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS0_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS0_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS0_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFSTS1_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS1_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS1_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS1_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS1_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS1_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS1_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS1_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS1_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS1_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFSTS2_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS2_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS2_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS2_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS2_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS2_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS2_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS2_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS2_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS2_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFSTS3_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS3_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS3_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS3_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS3_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS3_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS3_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS3_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS3_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS3_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFSTS4_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS4_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS4_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS4_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS4_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS4_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS4_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS4_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS4_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS4_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFSTS5_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS5_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS5_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS5_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS5_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS5_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS5_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS5_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS5_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS5_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFSTS6_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS6_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS6_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS6_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS6_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS6_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS6_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS6_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS6_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS6_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFSTS7_RFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDRFSTS7_RFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFSTS7_RFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDRFSTS7_RFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFSTS7_RFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDRFSTS7_RFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFSTS7_RFIF (0x00000008u) +#define RCANFD_RSCFD0CFDRFSTS7_RFIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFSTS7_RFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFSTS7_RFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFPCTR0_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR0_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPCTR1_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR1_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPCTR2_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR2_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPCTR3_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR3_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPCTR4_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR4_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPCTR5_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR5_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPCTR6_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR6_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPCTR7_RFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDRFPCTR7_RFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFCC0_CFE (0x00000001u) +#define RCANFD_RSCFD0CFDCFCC0_CFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFCC0_CFRXIE (0x00000002u) +#define RCANFD_RSCFD0CFDCFCC0_CFRXIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFCC0_CFTXIE (0x00000004u) +#define RCANFD_RSCFD0CFDCFCC0_CFTXIE_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFCC0_CFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDCFCC0_CFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFCC0_CFDC (0x00000700u) +#define RCANFD_RSCFD0CFDCFCC0_CFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFCC0_CFIM (0x00001000u) +#define RCANFD_RSCFD0CFDCFCC0_CFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDCFCC0_CFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDCFCC0_CFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDCFCC0_CFM (0x00030000u) +#define RCANFD_RSCFD0CFDCFCC0_CFM_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFCC0_CFITSS (0x00040000u) +#define RCANFD_RSCFD0CFDCFCC0_CFITSS_SHIFT (18u) +#define RCANFD_RSCFD0CFDCFCC0_CFITR (0x00080000u) +#define RCANFD_RSCFD0CFDCFCC0_CFITR_SHIFT (19u) +#define RCANFD_RSCFD0CFDCFCC0_CFTML (0x00F00000u) +#define RCANFD_RSCFD0CFDCFCC0_CFTML_SHIFT (20u) +#define RCANFD_RSCFD0CFDCFCC0_CFITT (0xFF000000u) +#define RCANFD_RSCFD0CFDCFCC0_CFITT_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFCC1_CFE (0x00000001u) +#define RCANFD_RSCFD0CFDCFCC1_CFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFCC1_CFRXIE (0x00000002u) +#define RCANFD_RSCFD0CFDCFCC1_CFRXIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFCC1_CFTXIE (0x00000004u) +#define RCANFD_RSCFD0CFDCFCC1_CFTXIE_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFCC1_CFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDCFCC1_CFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFCC1_CFDC (0x00000700u) +#define RCANFD_RSCFD0CFDCFCC1_CFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFCC1_CFIM (0x00001000u) +#define RCANFD_RSCFD0CFDCFCC1_CFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDCFCC1_CFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDCFCC1_CFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDCFCC1_CFM (0x00030000u) +#define RCANFD_RSCFD0CFDCFCC1_CFM_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFCC1_CFITSS (0x00040000u) +#define RCANFD_RSCFD0CFDCFCC1_CFITSS_SHIFT (18u) +#define RCANFD_RSCFD0CFDCFCC1_CFITR (0x00080000u) +#define RCANFD_RSCFD0CFDCFCC1_CFITR_SHIFT (19u) +#define RCANFD_RSCFD0CFDCFCC1_CFTML (0x00F00000u) +#define RCANFD_RSCFD0CFDCFCC1_CFTML_SHIFT (20u) +#define RCANFD_RSCFD0CFDCFCC1_CFITT (0xFF000000u) +#define RCANFD_RSCFD0CFDCFCC1_CFITT_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFCC2_CFE (0x00000001u) +#define RCANFD_RSCFD0CFDCFCC2_CFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFCC2_CFRXIE (0x00000002u) +#define RCANFD_RSCFD0CFDCFCC2_CFRXIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFCC2_CFTXIE (0x00000004u) +#define RCANFD_RSCFD0CFDCFCC2_CFTXIE_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFCC2_CFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDCFCC2_CFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFCC2_CFDC (0x00000700u) +#define RCANFD_RSCFD0CFDCFCC2_CFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFCC2_CFIM (0x00001000u) +#define RCANFD_RSCFD0CFDCFCC2_CFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDCFCC2_CFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDCFCC2_CFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDCFCC2_CFM (0x00030000u) +#define RCANFD_RSCFD0CFDCFCC2_CFM_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFCC2_CFITSS (0x00040000u) +#define RCANFD_RSCFD0CFDCFCC2_CFITSS_SHIFT (18u) +#define RCANFD_RSCFD0CFDCFCC2_CFITR (0x00080000u) +#define RCANFD_RSCFD0CFDCFCC2_CFITR_SHIFT (19u) +#define RCANFD_RSCFD0CFDCFCC2_CFTML (0x00F00000u) +#define RCANFD_RSCFD0CFDCFCC2_CFTML_SHIFT (20u) +#define RCANFD_RSCFD0CFDCFCC2_CFITT (0xFF000000u) +#define RCANFD_RSCFD0CFDCFCC2_CFITT_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFCC3_CFE (0x00000001u) +#define RCANFD_RSCFD0CFDCFCC3_CFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFCC3_CFRXIE (0x00000002u) +#define RCANFD_RSCFD0CFDCFCC3_CFRXIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFCC3_CFTXIE (0x00000004u) +#define RCANFD_RSCFD0CFDCFCC3_CFTXIE_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFCC3_CFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDCFCC3_CFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFCC3_CFDC (0x00000700u) +#define RCANFD_RSCFD0CFDCFCC3_CFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFCC3_CFIM (0x00001000u) +#define RCANFD_RSCFD0CFDCFCC3_CFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDCFCC3_CFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDCFCC3_CFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDCFCC3_CFM (0x00030000u) +#define RCANFD_RSCFD0CFDCFCC3_CFM_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFCC3_CFITSS (0x00040000u) +#define RCANFD_RSCFD0CFDCFCC3_CFITSS_SHIFT (18u) +#define RCANFD_RSCFD0CFDCFCC3_CFITR (0x00080000u) +#define RCANFD_RSCFD0CFDCFCC3_CFITR_SHIFT (19u) +#define RCANFD_RSCFD0CFDCFCC3_CFTML (0x00F00000u) +#define RCANFD_RSCFD0CFDCFCC3_CFTML_SHIFT (20u) +#define RCANFD_RSCFD0CFDCFCC3_CFITT (0xFF000000u) +#define RCANFD_RSCFD0CFDCFCC3_CFITT_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFCC4_CFE (0x00000001u) +#define RCANFD_RSCFD0CFDCFCC4_CFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFCC4_CFRXIE (0x00000002u) +#define RCANFD_RSCFD0CFDCFCC4_CFRXIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFCC4_CFTXIE (0x00000004u) +#define RCANFD_RSCFD0CFDCFCC4_CFTXIE_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFCC4_CFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDCFCC4_CFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFCC4_CFDC (0x00000700u) +#define RCANFD_RSCFD0CFDCFCC4_CFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFCC4_CFIM (0x00001000u) +#define RCANFD_RSCFD0CFDCFCC4_CFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDCFCC4_CFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDCFCC4_CFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDCFCC4_CFM (0x00030000u) +#define RCANFD_RSCFD0CFDCFCC4_CFM_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFCC4_CFITSS (0x00040000u) +#define RCANFD_RSCFD0CFDCFCC4_CFITSS_SHIFT (18u) +#define RCANFD_RSCFD0CFDCFCC4_CFITR (0x00080000u) +#define RCANFD_RSCFD0CFDCFCC4_CFITR_SHIFT (19u) +#define RCANFD_RSCFD0CFDCFCC4_CFTML (0x00F00000u) +#define RCANFD_RSCFD0CFDCFCC4_CFTML_SHIFT (20u) +#define RCANFD_RSCFD0CFDCFCC4_CFITT (0xFF000000u) +#define RCANFD_RSCFD0CFDCFCC4_CFITT_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFCC5_CFE (0x00000001u) +#define RCANFD_RSCFD0CFDCFCC5_CFE_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFCC5_CFRXIE (0x00000002u) +#define RCANFD_RSCFD0CFDCFCC5_CFRXIE_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFCC5_CFTXIE (0x00000004u) +#define RCANFD_RSCFD0CFDCFCC5_CFTXIE_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFCC5_CFPLS (0x00000070u) +#define RCANFD_RSCFD0CFDCFCC5_CFPLS_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFCC5_CFDC (0x00000700u) +#define RCANFD_RSCFD0CFDCFCC5_CFDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFCC5_CFIM (0x00001000u) +#define RCANFD_RSCFD0CFDCFCC5_CFIM_SHIFT (12u) +#define RCANFD_RSCFD0CFDCFCC5_CFIGCV (0x0000E000u) +#define RCANFD_RSCFD0CFDCFCC5_CFIGCV_SHIFT (13u) +#define RCANFD_RSCFD0CFDCFCC5_CFM (0x00030000u) +#define RCANFD_RSCFD0CFDCFCC5_CFM_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFCC5_CFITSS (0x00040000u) +#define RCANFD_RSCFD0CFDCFCC5_CFITSS_SHIFT (18u) +#define RCANFD_RSCFD0CFDCFCC5_CFITR (0x00080000u) +#define RCANFD_RSCFD0CFDCFCC5_CFITR_SHIFT (19u) +#define RCANFD_RSCFD0CFDCFCC5_CFTML (0x00F00000u) +#define RCANFD_RSCFD0CFDCFCC5_CFTML_SHIFT (20u) +#define RCANFD_RSCFD0CFDCFCC5_CFITT (0xFF000000u) +#define RCANFD_RSCFD0CFDCFCC5_CFITT_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFSTS0_CFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDCFSTS0_CFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFSTS0_CFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDCFSTS0_CFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFSTS0_CFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDCFSTS0_CFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFSTS0_CFRXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFSTS0_CFRXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFSTS0_CFTXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFSTS0_CFTXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFSTS0_CFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFSTS0_CFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFSTS1_CFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDCFSTS1_CFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFSTS1_CFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDCFSTS1_CFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFSTS1_CFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDCFSTS1_CFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFSTS1_CFRXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFSTS1_CFRXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFSTS1_CFTXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFSTS1_CFTXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFSTS1_CFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFSTS1_CFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFSTS2_CFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDCFSTS2_CFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFSTS2_CFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDCFSTS2_CFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFSTS2_CFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDCFSTS2_CFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFSTS2_CFRXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFSTS2_CFRXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFSTS2_CFTXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFSTS2_CFTXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFSTS2_CFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFSTS2_CFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFSTS3_CFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDCFSTS3_CFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFSTS3_CFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDCFSTS3_CFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFSTS3_CFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDCFSTS3_CFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFSTS3_CFRXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFSTS3_CFRXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFSTS3_CFTXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFSTS3_CFTXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFSTS3_CFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFSTS3_CFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFSTS4_CFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDCFSTS4_CFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFSTS4_CFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDCFSTS4_CFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFSTS4_CFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDCFSTS4_CFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFSTS4_CFRXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFSTS4_CFRXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFSTS4_CFTXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFSTS4_CFTXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFSTS4_CFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFSTS4_CFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFSTS5_CFEMP (0x00000001u) +#define RCANFD_RSCFD0CFDCFSTS5_CFEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFSTS5_CFFLL (0x00000002u) +#define RCANFD_RSCFD0CFDCFSTS5_CFFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFSTS5_CFMLT (0x00000004u) +#define RCANFD_RSCFD0CFDCFSTS5_CFMLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFSTS5_CFRXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFSTS5_CFRXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFSTS5_CFTXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFSTS5_CFTXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFSTS5_CFMC (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFSTS5_CFMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFPCTR0_CFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDCFPCTR0_CFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPCTR1_CFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDCFPCTR1_CFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPCTR2_CFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDCFPCTR2_CFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPCTR3_CFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDCFPCTR3_CFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPCTR4_CFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDCFPCTR4_CFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPCTR5_CFPC (0x000000FFu) +#define RCANFD_RSCFD0CFDCFPCTR5_CFPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDFESTS_RF0EMP (0x00000001u) +#define RCANFD_RSCFD0CFDFESTS_RF0EMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDFESTS_RF1EMP (0x00000002u) +#define RCANFD_RSCFD0CFDFESTS_RF1EMP_SHIFT (1u) +#define RCANFD_RSCFD0CFDFESTS_RF2EMP (0x00000004u) +#define RCANFD_RSCFD0CFDFESTS_RF2EMP_SHIFT (2u) +#define RCANFD_RSCFD0CFDFESTS_RF3EMP (0x00000008u) +#define RCANFD_RSCFD0CFDFESTS_RF3EMP_SHIFT (3u) +#define RCANFD_RSCFD0CFDFESTS_RF4EMP (0x00000010u) +#define RCANFD_RSCFD0CFDFESTS_RF4EMP_SHIFT (4u) +#define RCANFD_RSCFD0CFDFESTS_RF5EMP (0x00000020u) +#define RCANFD_RSCFD0CFDFESTS_RF5EMP_SHIFT (5u) +#define RCANFD_RSCFD0CFDFESTS_RF6EMP (0x00000040u) +#define RCANFD_RSCFD0CFDFESTS_RF6EMP_SHIFT (6u) +#define RCANFD_RSCFD0CFDFESTS_RF7EMP (0x00000080u) +#define RCANFD_RSCFD0CFDFESTS_RF7EMP_SHIFT (7u) +#define RCANFD_RSCFD0CFDFESTS_CF0EMP (0x00000100u) +#define RCANFD_RSCFD0CFDFESTS_CF0EMP_SHIFT (8u) +#define RCANFD_RSCFD0CFDFESTS_CF1EMP (0x00000200u) +#define RCANFD_RSCFD0CFDFESTS_CF1EMP_SHIFT (9u) +#define RCANFD_RSCFD0CFDFESTS_CF2EMP (0x00000400u) +#define RCANFD_RSCFD0CFDFESTS_CF2EMP_SHIFT (10u) +#define RCANFD_RSCFD0CFDFESTS_CF3EMP (0x00000800u) +#define RCANFD_RSCFD0CFDFESTS_CF3EMP_SHIFT (11u) +#define RCANFD_RSCFD0CFDFESTS_CF4EMP (0x00001000u) +#define RCANFD_RSCFD0CFDFESTS_CF4EMP_SHIFT (12u) +#define RCANFD_RSCFD0CFDFESTS_CF5EMP (0x00002000u) +#define RCANFD_RSCFD0CFDFESTS_CF5EMP_SHIFT (13u) +#define RCANFD_RSCFD0CFDFFSTS_RF0FLL (0x00000001u) +#define RCANFD_RSCFD0CFDFFSTS_RF0FLL_SHIFT (0u) +#define RCANFD_RSCFD0CFDFFSTS_RF1FLL (0x00000002u) +#define RCANFD_RSCFD0CFDFFSTS_RF1FLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDFFSTS_RF2FLL (0x00000004u) +#define RCANFD_RSCFD0CFDFFSTS_RF2FLL_SHIFT (2u) +#define RCANFD_RSCFD0CFDFFSTS_RF3FLL (0x00000008u) +#define RCANFD_RSCFD0CFDFFSTS_RF3FLL_SHIFT (3u) +#define RCANFD_RSCFD0CFDFFSTS_RF4FLL (0x00000010u) +#define RCANFD_RSCFD0CFDFFSTS_RF4FLL_SHIFT (4u) +#define RCANFD_RSCFD0CFDFFSTS_RF5FLL (0x00000020u) +#define RCANFD_RSCFD0CFDFFSTS_RF5FLL_SHIFT (5u) +#define RCANFD_RSCFD0CFDFFSTS_RF6FLL (0x00000040u) +#define RCANFD_RSCFD0CFDFFSTS_RF6FLL_SHIFT (6u) +#define RCANFD_RSCFD0CFDFFSTS_RF7FLL (0x00000080u) +#define RCANFD_RSCFD0CFDFFSTS_RF7FLL_SHIFT (7u) +#define RCANFD_RSCFD0CFDFFSTS_CF0FLL (0x00000100u) +#define RCANFD_RSCFD0CFDFFSTS_CF0FLL_SHIFT (8u) +#define RCANFD_RSCFD0CFDFFSTS_CF1FLL (0x00000200u) +#define RCANFD_RSCFD0CFDFFSTS_CF1FLL_SHIFT (9u) +#define RCANFD_RSCFD0CFDFFSTS_CF2FLL (0x00000400u) +#define RCANFD_RSCFD0CFDFFSTS_CF2FLL_SHIFT (10u) +#define RCANFD_RSCFD0CFDFFSTS_CF3FLL (0x00000800u) +#define RCANFD_RSCFD0CFDFFSTS_CF3FLL_SHIFT (11u) +#define RCANFD_RSCFD0CFDFFSTS_CF4FLL (0x00001000u) +#define RCANFD_RSCFD0CFDFFSTS_CF4FLL_SHIFT (12u) +#define RCANFD_RSCFD0CFDFFSTS_CF5FLL (0x00002000u) +#define RCANFD_RSCFD0CFDFFSTS_CF5FLL_SHIFT (13u) +#define RCANFD_RSCFD0CFDFMSTS_RF0MLT (0x00000001u) +#define RCANFD_RSCFD0CFDFMSTS_RF0MLT_SHIFT (0u) +#define RCANFD_RSCFD0CFDFMSTS_RF1MLT (0x00000002u) +#define RCANFD_RSCFD0CFDFMSTS_RF1MLT_SHIFT (1u) +#define RCANFD_RSCFD0CFDFMSTS_RF2MLT (0x00000004u) +#define RCANFD_RSCFD0CFDFMSTS_RF2MLT_SHIFT (2u) +#define RCANFD_RSCFD0CFDFMSTS_RF3MLT (0x00000008u) +#define RCANFD_RSCFD0CFDFMSTS_RF3MLT_SHIFT (3u) +#define RCANFD_RSCFD0CFDFMSTS_RF4MLT (0x00000010u) +#define RCANFD_RSCFD0CFDFMSTS_RF4MLT_SHIFT (4u) +#define RCANFD_RSCFD0CFDFMSTS_RF5MLT (0x00000020u) +#define RCANFD_RSCFD0CFDFMSTS_RF5MLT_SHIFT (5u) +#define RCANFD_RSCFD0CFDFMSTS_RF6MLT (0x00000040u) +#define RCANFD_RSCFD0CFDFMSTS_RF6MLT_SHIFT (6u) +#define RCANFD_RSCFD0CFDFMSTS_RF7MLT (0x00000080u) +#define RCANFD_RSCFD0CFDFMSTS_RF7MLT_SHIFT (7u) +#define RCANFD_RSCFD0CFDFMSTS_CF0MLT (0x00000100u) +#define RCANFD_RSCFD0CFDFMSTS_CF0MLT_SHIFT (8u) +#define RCANFD_RSCFD0CFDFMSTS_CF1MLT (0x00000200u) +#define RCANFD_RSCFD0CFDFMSTS_CF1MLT_SHIFT (9u) +#define RCANFD_RSCFD0CFDFMSTS_CF2MLT (0x00000400u) +#define RCANFD_RSCFD0CFDFMSTS_CF2MLT_SHIFT (10u) +#define RCANFD_RSCFD0CFDFMSTS_CF3MLT (0x00000800u) +#define RCANFD_RSCFD0CFDFMSTS_CF3MLT_SHIFT (11u) +#define RCANFD_RSCFD0CFDFMSTS_CF4MLT (0x00001000u) +#define RCANFD_RSCFD0CFDFMSTS_CF4MLT_SHIFT (12u) +#define RCANFD_RSCFD0CFDFMSTS_CF5MLT (0x00002000u) +#define RCANFD_RSCFD0CFDFMSTS_CF5MLT_SHIFT (13u) +#define RCANFD_RSCFD0CFDRFISTS_RF0IF (0x00000001u) +#define RCANFD_RSCFD0CFDRFISTS_RF0IF_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFISTS_RF1IF (0x00000002u) +#define RCANFD_RSCFD0CFDRFISTS_RF1IF_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFISTS_RF2IF (0x00000004u) +#define RCANFD_RSCFD0CFDRFISTS_RF2IF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFISTS_RF3IF (0x00000008u) +#define RCANFD_RSCFD0CFDRFISTS_RF3IF_SHIFT (3u) +#define RCANFD_RSCFD0CFDRFISTS_RF4IF (0x00000010u) +#define RCANFD_RSCFD0CFDRFISTS_RF4IF_SHIFT (4u) +#define RCANFD_RSCFD0CFDRFISTS_RF5IF (0x00000020u) +#define RCANFD_RSCFD0CFDRFISTS_RF5IF_SHIFT (5u) +#define RCANFD_RSCFD0CFDRFISTS_RF6IF (0x00000040u) +#define RCANFD_RSCFD0CFDRFISTS_RF6IF_SHIFT (6u) +#define RCANFD_RSCFD0CFDRFISTS_RF7IF (0x00000080u) +#define RCANFD_RSCFD0CFDRFISTS_RF7IF_SHIFT (7u) +#define RCANFD_RSCFD0CFDCFRISTS_CF0RXIF (0x00000001u) +#define RCANFD_RSCFD0CFDCFRISTS_CF0RXIF_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFRISTS_CF1RXIF (0x00000002u) +#define RCANFD_RSCFD0CFDCFRISTS_CF1RXIF_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFRISTS_CF2RXIF (0x00000004u) +#define RCANFD_RSCFD0CFDCFRISTS_CF2RXIF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFRISTS_CF3RXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFRISTS_CF3RXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFRISTS_CF4RXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFRISTS_CF4RXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFRISTS_CF5RXIF (0x00000020u) +#define RCANFD_RSCFD0CFDCFRISTS_CF5RXIF_SHIFT (5u) +#define RCANFD_RSCFD0CFDCFTISTS_CF0TXIF (0x00000001u) +#define RCANFD_RSCFD0CFDCFTISTS_CF0TXIF_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFTISTS_CF1TXIF (0x00000002u) +#define RCANFD_RSCFD0CFDCFTISTS_CF1TXIF_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFTISTS_CF2TXIF (0x00000004u) +#define RCANFD_RSCFD0CFDCFTISTS_CF2TXIF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFTISTS_CF3TXIF (0x00000008u) +#define RCANFD_RSCFD0CFDCFTISTS_CF3TXIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDCFTISTS_CF4TXIF (0x00000010u) +#define RCANFD_RSCFD0CFDCFTISTS_CF4TXIF_SHIFT (4u) +#define RCANFD_RSCFD0CFDCFTISTS_CF5TXIF (0x00000020u) +#define RCANFD_RSCFD0CFDCFTISTS_CF5TXIF_SHIFT (5u) +#define RCANFD_RSCFD0CFDTMC0_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC0_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC0_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC0_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC0_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC0_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC1_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC1_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC1_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC1_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC1_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC1_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC2_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC2_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC2_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC2_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC2_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC2_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC3_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC3_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC3_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC3_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC3_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC3_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC4_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC4_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC4_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC4_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC4_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC4_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC5_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC5_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC5_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC5_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC5_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC5_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC6_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC6_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC6_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC6_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC6_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC6_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC7_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC7_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC7_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC7_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC7_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC7_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC8_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC8_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC8_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC8_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC8_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC8_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC9_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC9_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC9_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC9_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC9_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC9_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC10_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC10_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC10_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC10_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC10_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC10_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC11_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC11_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC11_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC11_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC11_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC11_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC12_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC12_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC12_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC12_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC12_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC12_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC13_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC13_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC13_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC13_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC13_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC13_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC14_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC14_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC14_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC14_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC14_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC14_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC15_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC15_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC15_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC15_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC15_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC15_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC16_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC16_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC16_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC16_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC16_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC16_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC17_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC17_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC17_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC17_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC17_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC17_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC18_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC18_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC18_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC18_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC18_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC18_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC19_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC19_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC19_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC19_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC19_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC19_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC20_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC20_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC20_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC20_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC20_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC20_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC21_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC21_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC21_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC21_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC21_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC21_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC22_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC22_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC22_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC22_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC22_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC22_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC23_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC23_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC23_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC23_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC23_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC23_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC24_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC24_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC24_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC24_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC24_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC24_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC25_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC25_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC25_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC25_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC25_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC25_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC26_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC26_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC26_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC26_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC26_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC26_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC27_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC27_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC27_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC27_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC27_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC27_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC28_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC28_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC28_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC28_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC28_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC28_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC29_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC29_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC29_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC29_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC29_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC29_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC30_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC30_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC30_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC30_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC30_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC30_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMC31_TMTR (0x01u) +#define RCANFD_RSCFD0CFDTMC31_TMTR_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMC31_TMTAR (0x02u) +#define RCANFD_RSCFD0CFDTMC31_TMTAR_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMC31_TMOM (0x04u) +#define RCANFD_RSCFD0CFDTMC31_TMOM_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS0_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS1_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS2_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS3_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS4_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS5_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS6_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS7_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS8_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS9_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS10_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS11_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS12_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS13_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS14_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS15_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS16_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS17_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS18_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS19_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS20_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS21_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS22_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS23_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS24_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS25_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS26_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS27_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS28_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS29_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS30_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTSTS (0x01u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTSTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTRF (0x06u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTRF_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTRM (0x08u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTRM_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTARM (0x10u) +#define RCANFD_RSCFD0CFDTMSTS31_TMTARM_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS0 (0x00000001u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS1 (0x00000002u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS1_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS2 (0x00000004u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS2_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS3 (0x00000008u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS3_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS4 (0x00000010u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS4_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS5 (0x00000020u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS5_SHIFT (5u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS6 (0x00000040u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS6_SHIFT (6u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS7 (0x00000080u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS7_SHIFT (7u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS8 (0x00000100u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS8_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS9 (0x00000200u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS9_SHIFT (9u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS10 (0x00000400u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS10_SHIFT (10u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS11 (0x00000800u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS11_SHIFT (11u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS12 (0x00001000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS12_SHIFT (12u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS13 (0x00002000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS13_SHIFT (13u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS14 (0x00004000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS14_SHIFT (14u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS15 (0x00008000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS15_SHIFT (15u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS16 (0x00010000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS16_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS17 (0x00020000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS17_SHIFT (17u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS18 (0x00040000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS18_SHIFT (18u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS19 (0x00080000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS19_SHIFT (19u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS20 (0x00100000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS20_SHIFT (20u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS21 (0x00200000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS21_SHIFT (21u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS22 (0x00400000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS22_SHIFT (22u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS23 (0x00800000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS23_SHIFT (23u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS24 (0x01000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS24_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS25 (0x02000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS25_SHIFT (25u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS26 (0x04000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS26_SHIFT (26u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS27 (0x08000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS27_SHIFT (27u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS28 (0x10000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS28_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS29 (0x20000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS29_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS30 (0x40000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS30_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS31 (0x80000000u) +#define RCANFD_RSCFD0CFDTMTRSTS0_TMTRSTS31_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS0 (0x00000001u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS1 (0x00000002u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS1_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS2 (0x00000004u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS2_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS3 (0x00000008u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS3_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS4 (0x00000010u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS4_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS5 (0x00000020u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS5_SHIFT (5u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS6 (0x00000040u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS6_SHIFT (6u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS7 (0x00000080u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS7_SHIFT (7u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS8 (0x00000100u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS8_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS9 (0x00000200u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS9_SHIFT (9u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS10 (0x00000400u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS10_SHIFT (10u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS11 (0x00000800u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS11_SHIFT (11u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS12 (0x00001000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS12_SHIFT (12u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS13 (0x00002000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS13_SHIFT (13u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS14 (0x00004000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS14_SHIFT (14u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS15 (0x00008000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS15_SHIFT (15u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS16 (0x00010000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS16_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS17 (0x00020000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS17_SHIFT (17u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS18 (0x00040000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS18_SHIFT (18u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS19 (0x00080000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS19_SHIFT (19u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS20 (0x00100000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS20_SHIFT (20u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS21 (0x00200000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS21_SHIFT (21u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS22 (0x00400000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS22_SHIFT (22u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS23 (0x00800000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS23_SHIFT (23u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS24 (0x01000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS24_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS25 (0x02000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS25_SHIFT (25u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS26 (0x04000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS26_SHIFT (26u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS27 (0x08000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS27_SHIFT (27u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS28 (0x10000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS28_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS29 (0x20000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS29_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS30 (0x40000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS30_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS31 (0x80000000u) +#define RCANFD_RSCFD0CFDTMTARSTS0_TMTARSTS31_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS0 (0x00000001u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS1 (0x00000002u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS1_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS2 (0x00000004u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS2_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS3 (0x00000008u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS3_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS4 (0x00000010u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS4_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS5 (0x00000020u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS5_SHIFT (5u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS6 (0x00000040u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS6_SHIFT (6u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS7 (0x00000080u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS7_SHIFT (7u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS8 (0x00000100u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS8_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS9 (0x00000200u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS9_SHIFT (9u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS10 (0x00000400u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS10_SHIFT (10u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS11 (0x00000800u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS11_SHIFT (11u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS12 (0x00001000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS12_SHIFT (12u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS13 (0x00002000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS13_SHIFT (13u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS14 (0x00004000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS14_SHIFT (14u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS15 (0x00008000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS15_SHIFT (15u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS16 (0x00010000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS16_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS17 (0x00020000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS17_SHIFT (17u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS18 (0x00040000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS18_SHIFT (18u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS19 (0x00080000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS19_SHIFT (19u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS20 (0x00100000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS20_SHIFT (20u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS21 (0x00200000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS21_SHIFT (21u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS22 (0x00400000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS22_SHIFT (22u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS23 (0x00800000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS23_SHIFT (23u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS24 (0x01000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS24_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS25 (0x02000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS25_SHIFT (25u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS26 (0x04000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS26_SHIFT (26u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS27 (0x08000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS27_SHIFT (27u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS28 (0x10000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS28_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS29 (0x20000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS29_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS30 (0x40000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS30_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS31 (0x80000000u) +#define RCANFD_RSCFD0CFDTMTCSTS0_TMTCSTS31_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS0 (0x00000001u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS1 (0x00000002u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS1_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS2 (0x00000004u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS2_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS3 (0x00000008u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS3_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS4 (0x00000010u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS4_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS5 (0x00000020u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS5_SHIFT (5u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS6 (0x00000040u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS6_SHIFT (6u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS7 (0x00000080u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS7_SHIFT (7u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS8 (0x00000100u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS8_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS9 (0x00000200u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS9_SHIFT (9u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS10 (0x00000400u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS10_SHIFT (10u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS11 (0x00000800u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS11_SHIFT (11u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS12 (0x00001000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS12_SHIFT (12u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS13 (0x00002000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS13_SHIFT (13u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS14 (0x00004000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS14_SHIFT (14u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS15 (0x00008000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS15_SHIFT (15u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS16 (0x00010000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS16_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS17 (0x00020000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS17_SHIFT (17u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS18 (0x00040000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS18_SHIFT (18u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS19 (0x00080000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS19_SHIFT (19u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS20 (0x00100000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS20_SHIFT (20u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS21 (0x00200000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS21_SHIFT (21u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS22 (0x00400000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS22_SHIFT (22u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS23 (0x00800000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS23_SHIFT (23u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS24 (0x01000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS24_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS25 (0x02000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS25_SHIFT (25u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS26 (0x04000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS26_SHIFT (26u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS27 (0x08000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS27_SHIFT (27u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS28 (0x10000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS28_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS29 (0x20000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS29_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS30 (0x40000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS30_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS31 (0x80000000u) +#define RCANFD_RSCFD0CFDTMTASTS0_TMTASTS31_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE0 (0x00000001u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE1 (0x00000002u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE1_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE2 (0x00000004u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE2_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE3 (0x00000008u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE3_SHIFT (3u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE4 (0x00000010u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE4_SHIFT (4u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE5 (0x00000020u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE5_SHIFT (5u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE6 (0x00000040u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE6_SHIFT (6u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE7 (0x00000080u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE7_SHIFT (7u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE8 (0x00000100u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE8_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE9 (0x00000200u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE9_SHIFT (9u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE10 (0x00000400u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE10_SHIFT (10u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE11 (0x00000800u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE11_SHIFT (11u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE12 (0x00001000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE12_SHIFT (12u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE13 (0x00002000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE13_SHIFT (13u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE14 (0x00004000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE14_SHIFT (14u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE15 (0x00008000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE15_SHIFT (15u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE16 (0x00010000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE16_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE17 (0x00020000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE17_SHIFT (17u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE18 (0x00040000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE18_SHIFT (18u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE19 (0x00080000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE19_SHIFT (19u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE20 (0x00100000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE20_SHIFT (20u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE21 (0x00200000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE21_SHIFT (21u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE22 (0x00400000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE22_SHIFT (22u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE23 (0x00800000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE23_SHIFT (23u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE24 (0x01000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE24_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE25 (0x02000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE25_SHIFT (25u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE26 (0x04000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE26_SHIFT (26u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE27 (0x08000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE27_SHIFT (27u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE28 (0x10000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE28_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE29 (0x20000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE29_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE30 (0x40000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE30_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE31 (0x80000000u) +#define RCANFD_RSCFD0CFDTMIEC0_TMIE31_SHIFT (31u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQE (0x00000001u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQE_SHIFT (0u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQDC (0x00000F00u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQIE (0x00001000u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQIE_SHIFT (12u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQIM (0x00002000u) +#define RCANFD_RSCFD0CFDTXQCC0_TXQIM_SHIFT (13u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQE (0x00000001u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQE_SHIFT (0u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQDC (0x00000F00u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQDC_SHIFT (8u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQIE (0x00001000u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQIE_SHIFT (12u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQIM (0x00002000u) +#define RCANFD_RSCFD0CFDTXQCC1_TXQIM_SHIFT (13u) +#define RCANFD_RSCFD0CFDTXQSTS0_TXQEMP (0x00000001u) +#define RCANFD_RSCFD0CFDTXQSTS0_TXQEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDTXQSTS0_TXQFLL (0x00000002u) +#define RCANFD_RSCFD0CFDTXQSTS0_TXQFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDTXQSTS0_TXQIF (0x00000004u) +#define RCANFD_RSCFD0CFDTXQSTS0_TXQIF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTXQSTS1_TXQEMP (0x00000001u) +#define RCANFD_RSCFD0CFDTXQSTS1_TXQEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDTXQSTS1_TXQFLL (0x00000002u) +#define RCANFD_RSCFD0CFDTXQSTS1_TXQFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDTXQSTS1_TXQIF (0x00000004u) +#define RCANFD_RSCFD0CFDTXQSTS1_TXQIF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTXQPCTR0_TXQPC (0x000000FFu) +#define RCANFD_RSCFD0CFDTXQPCTR0_TXQPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDTXQPCTR1_TXQPC (0x000000FFu) +#define RCANFD_RSCFD0CFDTXQPCTR1_TXQPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLCC0_THLE (0x00000001u) +#define RCANFD_RSCFD0CFDTHLCC0_THLE_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLCC0_THLIE (0x00000100u) +#define RCANFD_RSCFD0CFDTHLCC0_THLIE_SHIFT (8u) +#define RCANFD_RSCFD0CFDTHLCC0_THLIM (0x00000200u) +#define RCANFD_RSCFD0CFDTHLCC0_THLIM_SHIFT (9u) +#define RCANFD_RSCFD0CFDTHLCC0_THLDTE (0x00000400u) +#define RCANFD_RSCFD0CFDTHLCC0_THLDTE_SHIFT (10u) +#define RCANFD_RSCFD0CFDTHLCC1_THLE (0x00000001u) +#define RCANFD_RSCFD0CFDTHLCC1_THLE_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLCC1_THLIE (0x00000100u) +#define RCANFD_RSCFD0CFDTHLCC1_THLIE_SHIFT (8u) +#define RCANFD_RSCFD0CFDTHLCC1_THLIM (0x00000200u) +#define RCANFD_RSCFD0CFDTHLCC1_THLIM_SHIFT (9u) +#define RCANFD_RSCFD0CFDTHLCC1_THLDTE (0x00000400u) +#define RCANFD_RSCFD0CFDTHLCC1_THLDTE_SHIFT (10u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLEMP (0x00000001u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLFLL (0x00000002u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLELT (0x00000004u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLELT_SHIFT (2u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLIF (0x00000008u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLMC (0x00001F00u) +#define RCANFD_RSCFD0CFDTHLSTS0_THLMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLEMP (0x00000001u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLEMP_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLFLL (0x00000002u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLFLL_SHIFT (1u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLELT (0x00000004u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLELT_SHIFT (2u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLIF (0x00000008u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLIF_SHIFT (3u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLMC (0x00001F00u) +#define RCANFD_RSCFD0CFDTHLSTS1_THLMC_SHIFT (8u) +#define RCANFD_RSCFD0CFDTHLPCTR0_THLPC (0x000000FFu) +#define RCANFD_RSCFD0CFDTHLPCTR0_THLPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLPCTR1_THLPC (0x000000FFu) +#define RCANFD_RSCFD0CFDTHLPCTR1_THLPC_SHIFT (0u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TSIF0 (0x00000001u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TSIF0_SHIFT (0u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TAIF0 (0x00000002u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TAIF0_SHIFT (1u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TQIF0 (0x00000004u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TQIF0_SHIFT (2u) +#define RCANFD_RSCFD0CFDGTINTSTS0_CFTIF0 (0x00000008u) +#define RCANFD_RSCFD0CFDGTINTSTS0_CFTIF0_SHIFT (3u) +#define RCANFD_RSCFD0CFDGTINTSTS0_THIF0 (0x00000010u) +#define RCANFD_RSCFD0CFDGTINTSTS0_THIF0_SHIFT (4u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TSIF1 (0x00000100u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TSIF1_SHIFT (8u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TAIF1 (0x00000200u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TAIF1_SHIFT (9u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TQIF1 (0x00000400u) +#define RCANFD_RSCFD0CFDGTINTSTS0_TQIF1_SHIFT (10u) +#define RCANFD_RSCFD0CFDGTINTSTS0_CFTIF1 (0x00000800u) +#define RCANFD_RSCFD0CFDGTINTSTS0_CFTIF1_SHIFT (11u) +#define RCANFD_RSCFD0CFDGTINTSTS0_THIF1 (0x00001000u) +#define RCANFD_RSCFD0CFDGTINTSTS0_THIF1_SHIFT (12u) +#define RCANFD_RSCFD0CFDGTSTCFG_C0ICBCE (0x00000001u) +#define RCANFD_RSCFD0CFDGTSTCFG_C0ICBCE_SHIFT (0u) +#define RCANFD_RSCFD0CFDGTSTCFG_C1ICBCE (0x00000002u) +#define RCANFD_RSCFD0CFDGTSTCFG_C1ICBCE_SHIFT (1u) +#define RCANFD_RSCFD0CFDGTSTCFG_RTMPS (0x007F0000u) +#define RCANFD_RSCFD0CFDGTSTCFG_RTMPS_SHIFT (16u) +#define RCANFD_RSCFD0CFDGTSTCTR_ICBCTME (0x00000001u) +#define RCANFD_RSCFD0CFDGTSTCTR_ICBCTME_SHIFT (0u) +#define RCANFD_RSCFD0CFDGTSTCTR_RTME (0x00000004u) +#define RCANFD_RSCFD0CFDGTSTCTR_RTME_SHIFT (2u) +#define RCANFD_RSCFD0CFDGFDCFG_RPED (0x00000001u) +#define RCANFD_RSCFD0CFDGFDCFG_RPED_SHIFT (0u) +#define RCANFD_RSCFD0CFDGFDCFG_TSCCFG (0x00000300u) +#define RCANFD_RSCFD0CFDGFDCFG_TSCCFG_SHIFT (8u) +#define RCANFD_RSCFD0CFDGLOCKK_LOCK (0x0000FFFFu) +#define RCANFD_RSCFD0CFDGLOCKK_LOCK_SHIFT (0u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE0 (0x00000001u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE1 (0x00000002u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE1_SHIFT (1u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE2 (0x00000004u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE2_SHIFT (2u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE3 (0x00000008u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE3_SHIFT (3u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE4 (0x00000010u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE4_SHIFT (4u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE5 (0x00000020u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE5_SHIFT (5u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE6 (0x00000040u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE6_SHIFT (6u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE7 (0x00000080u) +#define RCANFD_RSCFD0CFDCDTCT_RFDMAE7_SHIFT (7u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE0 (0x00000100u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE0_SHIFT (8u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE1 (0x00000200u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE1_SHIFT (9u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE2 (0x00000400u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE2_SHIFT (10u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE3 (0x00000800u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE3_SHIFT (11u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE4 (0x00001000u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE4_SHIFT (12u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE5 (0x00002000u) +#define RCANFD_RSCFD0CFDCDTCT_CFDMAE5_SHIFT (13u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS0 (0x00000001u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS1 (0x00000002u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS1_SHIFT (1u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS2 (0x00000004u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS2_SHIFT (2u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS3 (0x00000008u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS3_SHIFT (3u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS4 (0x00000010u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS4_SHIFT (4u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS5 (0x00000020u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS5_SHIFT (5u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS6 (0x00000040u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS6_SHIFT (6u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS7 (0x00000080u) +#define RCANFD_RSCFD0CFDCDTSTS_RFDMASTS7_SHIFT (7u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS0 (0x00000100u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS0_SHIFT (8u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS1 (0x00000200u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS1_SHIFT (9u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS2 (0x00000400u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS2_SHIFT (10u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS3 (0x00000800u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS3_SHIFT (11u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS4 (0x00001000u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS4_SHIFT (12u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS5 (0x00002000u) +#define RCANFD_RSCFD0CFDCDTSTS_CFDMASTS5_SHIFT (13u) +#define RCANFD_RSCFD0CFDGRMCFG_RCMC (0x00000001u) +#define RCANFD_RSCFD0CFDGRMCFG_RCMC_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0DCFG_DBRP (0x000000FFu) +#define RCANFD_RSCFD0CFDC0DCFG_DBRP_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0DCFG_DTSEG1 (0x000F0000u) +#define RCANFD_RSCFD0CFDC0DCFG_DTSEG1_SHIFT (16u) +#define RCANFD_RSCFD0CFDC0DCFG_DTSEG2 (0x00700000u) +#define RCANFD_RSCFD0CFDC0DCFG_DTSEG2_SHIFT (20u) +#define RCANFD_RSCFD0CFDC0DCFG_DSJW (0x07000000u) +#define RCANFD_RSCFD0CFDC0DCFG_DSJW_SHIFT (24u) +#define RCANFD_RSCFD0CFDC0FDCFG_EOCCFG (0x00000007u) +#define RCANFD_RSCFD0CFDC0FDCFG_EOCCFG_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0FDCFG_TDCOC (0x00000100u) +#define RCANFD_RSCFD0CFDC0FDCFG_TDCOC_SHIFT (8u) +#define RCANFD_RSCFD0CFDC0FDCFG_TDCE (0x00000200u) +#define RCANFD_RSCFD0CFDC0FDCFG_TDCE_SHIFT (9u) +#define RCANFD_RSCFD0CFDC0FDCFG_ESIC (0x00000400u) +#define RCANFD_RSCFD0CFDC0FDCFG_ESIC_SHIFT (10u) +#define RCANFD_RSCFD0CFDC0FDCFG_TDCO (0x007F0000u) +#define RCANFD_RSCFD0CFDC0FDCFG_TDCO_SHIFT (16u) +#define RCANFD_RSCFD0CFDC0FDCFG_GWEN (0x01000000u) +#define RCANFD_RSCFD0CFDC0FDCFG_GWEN_SHIFT (24u) +#define RCANFD_RSCFD0CFDC0FDCFG_GWFDF (0x02000000u) +#define RCANFD_RSCFD0CFDC0FDCFG_GWFDF_SHIFT (25u) +#define RCANFD_RSCFD0CFDC0FDCFG_GWBRS (0x04000000u) +#define RCANFD_RSCFD0CFDC0FDCFG_GWBRS_SHIFT (26u) +#define RCANFD_RSCFD0CFDC0FDCFG_TMME (0x08000000u) +#define RCANFD_RSCFD0CFDC0FDCFG_TMME_SHIFT (27u) +#define RCANFD_RSCFD0CFDC0FDCFG_FDOE (0x10000000u) +#define RCANFD_RSCFD0CFDC0FDCFG_FDOE_SHIFT (28u) +#define RCANFD_RSCFD0CFDC0FDCFG_REFE (0x20000000u) +#define RCANFD_RSCFD0CFDC0FDCFG_REFE_SHIFT (29u) +#define RCANFD_RSCFD0CFDC0FDCTR_EOCCLR (0x00000001u) +#define RCANFD_RSCFD0CFDC0FDCTR_EOCCLR_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0FDCTR_SOCCLR (0x00000002u) +#define RCANFD_RSCFD0CFDC0FDCTR_SOCCLR_SHIFT (1u) +#define RCANFD_RSCFD0CFDC0FDSTS_TDCR (0x0000007Fu) +#define RCANFD_RSCFD0CFDC0FDSTS_TDCR_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0FDSTS_TDCVF (0x00000080u) +#define RCANFD_RSCFD0CFDC0FDSTS_TDCVF_SHIFT (7u) +#define RCANFD_RSCFD0CFDC0FDSTS_EOCO (0x00000100u) +#define RCANFD_RSCFD0CFDC0FDSTS_EOCO_SHIFT (8u) +#define RCANFD_RSCFD0CFDC0FDSTS_SOCO (0x00000200u) +#define RCANFD_RSCFD0CFDC0FDSTS_SOCO_SHIFT (9u) +#define RCANFD_RSCFD0CFDC0FDSTS_EOC (0x00FF0000u) +#define RCANFD_RSCFD0CFDC0FDSTS_EOC_SHIFT (16u) +#define RCANFD_RSCFD0CFDC0FDSTS_SOC (0xFF000000u) +#define RCANFD_RSCFD0CFDC0FDSTS_SOC_SHIFT (24u) +#define RCANFD_RSCFD0CFDC0FDCRC_CRCREG (0x001FFFFFu) +#define RCANFD_RSCFD0CFDC0FDCRC_CRCREG_SHIFT (0u) +#define RCANFD_RSCFD0CFDC0FDCRC_SCNT (0x0F000000u) +#define RCANFD_RSCFD0CFDC0FDCRC_SCNT_SHIFT (24u) +#define RCANFD_RSCFD0CFDC1DCFG_DBRP (0x000000FFu) +#define RCANFD_RSCFD0CFDC1DCFG_DBRP_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1DCFG_DTSEG1 (0x000F0000u) +#define RCANFD_RSCFD0CFDC1DCFG_DTSEG1_SHIFT (16u) +#define RCANFD_RSCFD0CFDC1DCFG_DTSEG2 (0x00700000u) +#define RCANFD_RSCFD0CFDC1DCFG_DTSEG2_SHIFT (20u) +#define RCANFD_RSCFD0CFDC1DCFG_DSJW (0x07000000u) +#define RCANFD_RSCFD0CFDC1DCFG_DSJW_SHIFT (24u) +#define RCANFD_RSCFD0CFDC1FDCFG_EOCCFG (0x00000007u) +#define RCANFD_RSCFD0CFDC1FDCFG_EOCCFG_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1FDCFG_TDCOC (0x00000100u) +#define RCANFD_RSCFD0CFDC1FDCFG_TDCOC_SHIFT (8u) +#define RCANFD_RSCFD0CFDC1FDCFG_TDCE (0x00000200u) +#define RCANFD_RSCFD0CFDC1FDCFG_TDCE_SHIFT (9u) +#define RCANFD_RSCFD0CFDC1FDCFG_ESIC (0x00000400u) +#define RCANFD_RSCFD0CFDC1FDCFG_ESIC_SHIFT (10u) +#define RCANFD_RSCFD0CFDC1FDCFG_TDCO (0x007F0000u) +#define RCANFD_RSCFD0CFDC1FDCFG_TDCO_SHIFT (16u) +#define RCANFD_RSCFD0CFDC1FDCFG_GWEN (0x01000000u) +#define RCANFD_RSCFD0CFDC1FDCFG_GWEN_SHIFT (24u) +#define RCANFD_RSCFD0CFDC1FDCFG_GWFDF (0x02000000u) +#define RCANFD_RSCFD0CFDC1FDCFG_GWFDF_SHIFT (25u) +#define RCANFD_RSCFD0CFDC1FDCFG_GWBRS (0x04000000u) +#define RCANFD_RSCFD0CFDC1FDCFG_GWBRS_SHIFT (26u) +#define RCANFD_RSCFD0CFDC1FDCFG_TMME (0x08000000u) +#define RCANFD_RSCFD0CFDC1FDCFG_TMME_SHIFT (27u) +#define RCANFD_RSCFD0CFDC1FDCFG_FDOE (0x10000000u) +#define RCANFD_RSCFD0CFDC1FDCFG_FDOE_SHIFT (28u) +#define RCANFD_RSCFD0CFDC1FDCFG_REFE (0x20000000u) +#define RCANFD_RSCFD0CFDC1FDCFG_REFE_SHIFT (29u) +#define RCANFD_RSCFD0CFDC1FDCTR_EOCCLR (0x00000001u) +#define RCANFD_RSCFD0CFDC1FDCTR_EOCCLR_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1FDCTR_SOCCLR (0x00000002u) +#define RCANFD_RSCFD0CFDC1FDCTR_SOCCLR_SHIFT (1u) +#define RCANFD_RSCFD0CFDC1FDSTS_TDCR (0x0000007Fu) +#define RCANFD_RSCFD0CFDC1FDSTS_TDCR_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1FDSTS_TDCVF (0x00000080u) +#define RCANFD_RSCFD0CFDC1FDSTS_TDCVF_SHIFT (7u) +#define RCANFD_RSCFD0CFDC1FDSTS_EOCO (0x00000100u) +#define RCANFD_RSCFD0CFDC1FDSTS_EOCO_SHIFT (8u) +#define RCANFD_RSCFD0CFDC1FDSTS_SOCO (0x00000200u) +#define RCANFD_RSCFD0CFDC1FDSTS_SOCO_SHIFT (9u) +#define RCANFD_RSCFD0CFDC1FDSTS_EOC (0x00FF0000u) +#define RCANFD_RSCFD0CFDC1FDSTS_EOC_SHIFT (16u) +#define RCANFD_RSCFD0CFDC1FDSTS_SOC (0xFF000000u) +#define RCANFD_RSCFD0CFDC1FDSTS_SOC_SHIFT (24u) +#define RCANFD_RSCFD0CFDC1FDCRC_CRCREG (0x001FFFFFu) +#define RCANFD_RSCFD0CFDC1FDCRC_CRCREG_SHIFT (0u) +#define RCANFD_RSCFD0CFDC1FDCRC_SCNT (0x0F000000u) +#define RCANFD_RSCFD0CFDC1FDCRC_SCNT_SHIFT (24u) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID0_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM0_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM0_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM0_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM0_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM0_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM0_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_0_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_0_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_0_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID1_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM1_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM1_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM1_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM1_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM1_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM1_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_1_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_1_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_1_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID2_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM2_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM2_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM2_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM2_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM2_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM2_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_2_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_2_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_2_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID3_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM3_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM3_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM3_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM3_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM3_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM3_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_3_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_3_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_3_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID4_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM4_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM4_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM4_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM4_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM4_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM4_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_4_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_4_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_4_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID5_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM5_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM5_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM5_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM5_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM5_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM5_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_5_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_5_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_5_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID6_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM6_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM6_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM6_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM6_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM6_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM6_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_6_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_6_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_6_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID7_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM7_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM7_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM7_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM7_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM7_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM7_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_7_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_7_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_7_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID8_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM8_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM8_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM8_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM8_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM8_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM8_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_8_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_8_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_8_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID9_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM9_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM9_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM9_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM9_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM9_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM9_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_9_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_9_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_9_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID10_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM10_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM10_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM10_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM10_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM10_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM10_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_10_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_10_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_10_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID11_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM11_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM11_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM11_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM11_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM11_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM11_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_11_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_11_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_11_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID12_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM12_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM12_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM12_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM12_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM12_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM12_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_12_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_12_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_12_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID13_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM13_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM13_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM13_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM13_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM13_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM13_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_13_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_13_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_13_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID14_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM14_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM14_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM14_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM14_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM14_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM14_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_14_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_14_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_14_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLID_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLLB (0x20000000u) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLLB_SHIFT (29u) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLRTR (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLIDE (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLID15_GAFLIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLM15_GAFLIDM (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDGAFLM15_GAFLIDM_SHIFT (0u) +#define RCANFD_RSCFD0CFDGAFLM15_GAFLRTRM (0x40000000u) +#define RCANFD_RSCFD0CFDGAFLM15_GAFLRTRM_SHIFT (30u) +#define RCANFD_RSCFD0CFDGAFLM15_GAFLIDEM (0x80000000u) +#define RCANFD_RSCFD0CFDGAFLM15_GAFLIDEM_SHIFT (31u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLRMDP (0x00007F00u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLRMDP_SHIFT (8u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLRMV (0x00008000u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLRMV_SHIFT (15u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDGAFLP0_15_GAFLDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDGAFLP1_15_GAFLFDP (0x00003FFFu) +#define RCANFD_RSCFD0CFDGAFLP1_15_GAFLFDP_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID0_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID0_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID0_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID0_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID0_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID0_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR0_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR0_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR0_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR0_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR0_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR0_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS0_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS0_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS0_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS0_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS0_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS0_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_0_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_0_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_0_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_0_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_0_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID1_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID1_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID1_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID1_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID1_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID1_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR1_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR1_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR1_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR1_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR1_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR1_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS1_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS1_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS1_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS1_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS1_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS1_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_1_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_1_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_1_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_1_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_1_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID2_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID2_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID2_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID2_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID2_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID2_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR2_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR2_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR2_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR2_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR2_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR2_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS2_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS2_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS2_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS2_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS2_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS2_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_2_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_2_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_2_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_2_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_2_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID3_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID3_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID3_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID3_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID3_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID3_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR3_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR3_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR3_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR3_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR3_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR3_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS3_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS3_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS3_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS3_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS3_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS3_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_3_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_3_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_3_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_3_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_3_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID4_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID4_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID4_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID4_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID4_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID4_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR4_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR4_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR4_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR4_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR4_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR4_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS4_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS4_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS4_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS4_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS4_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS4_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_4_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_4_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_4_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_4_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_4_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID5_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID5_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID5_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID5_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID5_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID5_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR5_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR5_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR5_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR5_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR5_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR5_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS5_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS5_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS5_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS5_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS5_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS5_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_5_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_5_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_5_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_5_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_5_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID6_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID6_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID6_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID6_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID6_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID6_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR6_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR6_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR6_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR6_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR6_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR6_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS6_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS6_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS6_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS6_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS6_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS6_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_6_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_6_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_6_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_6_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_6_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID7_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID7_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID7_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID7_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID7_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID7_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR7_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR7_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR7_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR7_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR7_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR7_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS7_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS7_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS7_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS7_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS7_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS7_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_7_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_7_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_7_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_7_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_7_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID8_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID8_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID8_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID8_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID8_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID8_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR8_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR8_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR8_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR8_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR8_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR8_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS8_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS8_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS8_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS8_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS8_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS8_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_8_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_8_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_8_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_8_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_8_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID9_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID9_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID9_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID9_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID9_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID9_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR9_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR9_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR9_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR9_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR9_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR9_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS9_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS9_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS9_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS9_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS9_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS9_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_9_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_9_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_9_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_9_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_9_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID10_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID10_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID10_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID10_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID10_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID10_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR10_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR10_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR10_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR10_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR10_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR10_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS10_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS10_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS10_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS10_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS10_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS10_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_10_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_10_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_10_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_10_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_10_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID11_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID11_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID11_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID11_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID11_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID11_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR11_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR11_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR11_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR11_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR11_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR11_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS11_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS11_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS11_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS11_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS11_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS11_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_11_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_11_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_11_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_11_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_11_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID12_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID12_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID12_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID12_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID12_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID12_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR12_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR12_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR12_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR12_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR12_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR12_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS12_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS12_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS12_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS12_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS12_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS12_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_12_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_12_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_12_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_12_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_12_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID13_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID13_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID13_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID13_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID13_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID13_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR13_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR13_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR13_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR13_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR13_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR13_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS13_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS13_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS13_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS13_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS13_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS13_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_13_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_13_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_13_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_13_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_13_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID14_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID14_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID14_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID14_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID14_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID14_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR14_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR14_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR14_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR14_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR14_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR14_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS14_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS14_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS14_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS14_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS14_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS14_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_14_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_14_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_14_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_14_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_14_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID15_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID15_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID15_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID15_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID15_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID15_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR15_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR15_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR15_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR15_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR15_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR15_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS15_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS15_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS15_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS15_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS15_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS15_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_15_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_15_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_15_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_15_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_15_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID16_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID16_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID16_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID16_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID16_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID16_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR16_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR16_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR16_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR16_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR16_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR16_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS16_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS16_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS16_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS16_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS16_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS16_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_16_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_16_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_16_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_16_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_16_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID17_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID17_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID17_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID17_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID17_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID17_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR17_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR17_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR17_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR17_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR17_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR17_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS17_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS17_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS17_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS17_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS17_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS17_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_17_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_17_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_17_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_17_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_17_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID18_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID18_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID18_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID18_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID18_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID18_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR18_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR18_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR18_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR18_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR18_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR18_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS18_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS18_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS18_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS18_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS18_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS18_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_18_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_18_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_18_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_18_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_18_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID19_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID19_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID19_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID19_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID19_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID19_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR19_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR19_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR19_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR19_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR19_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR19_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS19_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS19_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS19_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS19_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS19_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS19_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_19_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_19_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_19_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_19_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_19_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID20_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID20_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID20_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID20_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID20_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID20_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR20_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR20_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR20_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR20_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR20_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR20_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS20_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS20_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS20_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS20_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS20_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS20_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_20_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_20_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_20_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_20_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_20_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID21_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID21_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID21_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID21_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID21_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID21_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR21_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR21_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR21_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR21_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR21_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR21_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS21_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS21_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS21_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS21_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS21_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS21_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_21_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_21_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_21_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_21_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_21_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID22_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID22_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID22_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID22_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID22_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID22_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR22_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR22_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR22_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR22_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR22_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR22_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS22_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS22_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS22_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS22_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS22_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS22_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_22_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_22_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_22_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_22_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_22_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID23_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID23_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID23_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID23_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID23_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID23_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR23_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR23_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR23_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR23_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR23_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR23_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS23_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS23_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS23_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS23_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS23_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS23_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_23_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_23_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_23_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_23_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_23_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID24_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID24_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID24_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID24_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID24_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID24_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR24_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR24_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR24_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR24_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR24_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR24_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS24_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS24_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS24_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS24_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS24_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS24_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_24_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_24_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_24_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_24_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_24_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID25_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID25_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID25_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID25_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID25_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID25_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR25_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR25_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR25_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR25_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR25_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR25_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS25_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS25_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS25_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS25_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS25_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS25_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_25_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_25_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_25_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_25_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_25_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID26_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID26_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID26_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID26_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID26_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID26_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR26_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR26_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR26_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR26_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR26_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR26_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS26_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS26_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS26_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS26_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS26_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS26_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_26_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_26_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_26_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_26_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_26_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID27_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID27_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID27_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID27_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID27_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID27_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR27_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR27_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR27_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR27_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR27_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR27_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS27_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS27_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS27_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS27_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS27_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS27_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_27_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_27_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_27_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_27_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_27_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID28_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID28_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID28_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID28_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID28_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID28_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR28_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR28_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR28_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR28_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR28_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR28_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS28_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS28_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS28_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS28_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS28_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS28_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_28_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_28_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_28_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_28_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_28_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID29_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID29_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID29_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID29_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID29_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID29_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR29_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR29_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR29_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR29_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR29_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR29_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS29_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS29_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS29_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS29_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS29_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS29_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_29_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_29_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_29_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_29_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_29_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID30_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID30_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID30_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID30_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID30_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID30_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR30_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR30_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR30_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR30_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR30_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR30_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS30_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS30_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS30_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS30_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS30_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS30_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_30_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_30_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_30_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_30_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_30_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMID31_RMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRMID31_RMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMID31_RMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRMID31_RMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRMID31_RMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRMID31_RMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRMPTR31_RMTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRMPTR31_RMTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMPTR31_RMPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRMPTR31_RMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMPTR31_RMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRMPTR31_RMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRMFDSTS31_RMESI (0x00000001u) +#define RCANFD_RSCFD0CFDRMFDSTS31_RMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMFDSTS31_RMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRMFDSTS31_RMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRMFDSTS31_RMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRMFDSTS31_RMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF0_31_RMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF1_31_RMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF2_31_RMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF3_31_RMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRMDF4_31_RMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID0_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID0_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID0_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID0_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID0_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID0_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR0_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR0_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR0_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR0_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR0_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR0_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS0_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS0_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS0_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS0_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS0_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS0_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_0_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_0_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_0_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_0_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_0_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_0_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_0_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_0_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_0_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_0_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_0_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_0_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_0_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_0_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_0_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_0_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID1_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID1_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID1_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID1_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID1_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID1_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR1_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR1_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR1_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR1_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR1_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR1_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS1_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS1_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS1_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS1_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS1_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS1_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_1_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_1_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_1_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_1_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_1_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_1_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_1_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_1_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_1_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_1_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_1_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_1_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_1_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_1_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_1_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_1_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID2_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID2_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID2_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID2_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID2_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID2_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR2_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR2_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR2_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR2_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR2_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR2_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS2_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS2_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS2_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS2_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS2_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS2_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_2_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_2_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_2_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_2_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_2_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_2_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_2_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_2_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_2_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_2_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_2_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_2_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_2_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_2_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_2_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_2_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID3_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID3_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID3_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID3_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID3_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID3_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR3_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR3_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR3_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR3_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR3_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR3_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS3_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS3_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS3_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS3_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS3_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS3_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_3_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_3_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_3_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_3_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_3_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_3_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_3_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_3_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_3_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_3_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_3_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_3_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_3_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_3_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_3_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_3_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID4_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID4_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID4_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID4_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID4_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID4_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR4_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR4_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR4_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR4_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR4_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR4_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS4_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS4_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS4_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS4_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS4_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS4_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_4_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_4_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_4_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_4_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_4_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_4_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_4_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_4_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_4_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_4_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_4_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_4_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_4_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_4_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_4_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_4_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID5_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID5_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID5_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID5_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID5_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID5_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR5_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR5_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR5_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR5_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR5_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR5_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS5_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS5_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS5_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS5_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS5_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS5_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_5_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_5_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_5_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_5_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_5_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_5_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_5_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_5_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_5_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_5_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_5_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_5_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_5_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_5_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_5_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_5_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID6_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID6_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID6_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID6_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID6_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID6_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR6_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR6_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR6_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR6_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR6_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR6_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS6_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS6_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS6_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS6_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS6_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS6_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_6_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_6_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_6_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_6_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_6_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_6_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_6_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_6_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_6_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_6_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_6_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_6_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_6_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_6_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_6_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_6_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFID7_RFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDRFID7_RFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFID7_RFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDRFID7_RFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDRFID7_RFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDRFID7_RFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDRFPTR7_RFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDRFPTR7_RFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFPTR7_RFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDRFPTR7_RFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFPTR7_RFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDRFPTR7_RFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDRFFDSTS7_RFESI (0x00000001u) +#define RCANFD_RSCFD0CFDRFFDSTS7_RFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFFDSTS7_RFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDRFFDSTS7_RFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDRFFDSTS7_RFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDRFFDSTS7_RFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF0_7_RFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF1_7_RFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF2_7_RFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF3_7_RFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF4_7_RFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF5_7_RFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF6_7_RFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF7_7_RFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF8_7_RFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF9_7_RFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF10_7_RFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF11_7_RFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF12_7_RFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF13_7_RFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF14_7_RFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDRFDF15_7_RFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFID0_CFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDCFID0_CFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFID0_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDCFID0_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDCFID0_CFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDCFID0_CFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDCFID0_CFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDCFID0_CFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDCFPTR0_CFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDCFPTR0_CFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPTR0_CFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDCFPTR0_CFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFPTR0_CFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDCFPTR0_CFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDCFFDCSTS0_CFESI (0x00000001u) +#define RCANFD_RSCFD0CFDCFFDCSTS0_CFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFFDCSTS0_CFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDCFFDCSTS0_CFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFFDCSTS0_CFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDCFFDCSTS0_CFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF0_0_CFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF1_0_CFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF2_0_CFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF3_0_CFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF4_0_CFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF5_0_CFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF6_0_CFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF7_0_CFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF8_0_CFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF9_0_CFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF10_0_CFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF11_0_CFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF12_0_CFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF13_0_CFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF14_0_CFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF15_0_CFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFID1_CFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDCFID1_CFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFID1_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDCFID1_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDCFID1_CFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDCFID1_CFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDCFID1_CFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDCFID1_CFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDCFPTR1_CFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDCFPTR1_CFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPTR1_CFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDCFPTR1_CFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFPTR1_CFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDCFPTR1_CFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDCFFDCSTS1_CFESI (0x00000001u) +#define RCANFD_RSCFD0CFDCFFDCSTS1_CFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFFDCSTS1_CFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDCFFDCSTS1_CFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFFDCSTS1_CFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDCFFDCSTS1_CFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF0_1_CFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF1_1_CFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF2_1_CFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF3_1_CFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF4_1_CFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF5_1_CFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF6_1_CFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF7_1_CFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF8_1_CFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF9_1_CFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF10_1_CFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF11_1_CFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF12_1_CFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF13_1_CFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF14_1_CFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF15_1_CFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFID2_CFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDCFID2_CFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFID2_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDCFID2_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDCFID2_CFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDCFID2_CFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDCFID2_CFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDCFID2_CFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDCFPTR2_CFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDCFPTR2_CFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPTR2_CFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDCFPTR2_CFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFPTR2_CFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDCFPTR2_CFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDCFFDCSTS2_CFESI (0x00000001u) +#define RCANFD_RSCFD0CFDCFFDCSTS2_CFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFFDCSTS2_CFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDCFFDCSTS2_CFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFFDCSTS2_CFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDCFFDCSTS2_CFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF0_2_CFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF1_2_CFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF2_2_CFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF3_2_CFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF4_2_CFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF5_2_CFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF6_2_CFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF7_2_CFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF8_2_CFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF9_2_CFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF10_2_CFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF11_2_CFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF12_2_CFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF13_2_CFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF14_2_CFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF15_2_CFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFID3_CFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDCFID3_CFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFID3_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDCFID3_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDCFID3_CFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDCFID3_CFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDCFID3_CFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDCFID3_CFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDCFPTR3_CFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDCFPTR3_CFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPTR3_CFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDCFPTR3_CFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFPTR3_CFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDCFPTR3_CFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDCFFDCSTS3_CFESI (0x00000001u) +#define RCANFD_RSCFD0CFDCFFDCSTS3_CFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFFDCSTS3_CFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDCFFDCSTS3_CFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFFDCSTS3_CFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDCFFDCSTS3_CFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF0_3_CFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF1_3_CFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF2_3_CFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF3_3_CFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF4_3_CFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF5_3_CFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF6_3_CFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF7_3_CFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF8_3_CFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF9_3_CFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF10_3_CFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF11_3_CFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF12_3_CFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF13_3_CFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF14_3_CFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF15_3_CFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFID4_CFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDCFID4_CFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFID4_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDCFID4_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDCFID4_CFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDCFID4_CFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDCFID4_CFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDCFID4_CFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDCFPTR4_CFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDCFPTR4_CFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPTR4_CFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDCFPTR4_CFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFPTR4_CFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDCFPTR4_CFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDCFFDCSTS4_CFESI (0x00000001u) +#define RCANFD_RSCFD0CFDCFFDCSTS4_CFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFFDCSTS4_CFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDCFFDCSTS4_CFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFFDCSTS4_CFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDCFFDCSTS4_CFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF0_4_CFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF1_4_CFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF2_4_CFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF3_4_CFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF4_4_CFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF5_4_CFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF6_4_CFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF7_4_CFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF8_4_CFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF9_4_CFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF10_4_CFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF11_4_CFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF12_4_CFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF13_4_CFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF14_4_CFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF15_4_CFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFID5_CFID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDCFID5_CFID_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFID5_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDCFID5_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDCFID5_CFRTR (0x40000000u) +#define RCANFD_RSCFD0CFDCFID5_CFRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDCFID5_CFIDE (0x80000000u) +#define RCANFD_RSCFD0CFDCFID5_CFIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDCFPTR5_CFTS (0x0000FFFFu) +#define RCANFD_RSCFD0CFDCFPTR5_CFTS_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFPTR5_CFPTR (0x0FFF0000u) +#define RCANFD_RSCFD0CFDCFPTR5_CFPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFPTR5_CFDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDCFPTR5_CFDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDCFFDCSTS5_CFESI (0x00000001u) +#define RCANFD_RSCFD0CFDCFFDCSTS5_CFESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFFDCSTS5_CFBRS (0x00000002u) +#define RCANFD_RSCFD0CFDCFFDCSTS5_CFBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDCFFDCSTS5_CFFDF (0x00000004u) +#define RCANFD_RSCFD0CFDCFFDCSTS5_CFFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF0_5_CFDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF1_5_CFDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF2_5_CFDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF3_5_CFDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF4_5_CFDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB20 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB20_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB21 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB21_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB22 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB22_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB23 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF5_5_CFDB23_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB24 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB24_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB25 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB25_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB26 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB26_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB27 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF6_5_CFDB27_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB28 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB28_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB29 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB29_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB30 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB30_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB31 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF7_5_CFDB31_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB32 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB32_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB33 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB33_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB34 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB34_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB35 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF8_5_CFDB35_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB36 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB36_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB37 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB37_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB38 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB38_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB39 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF9_5_CFDB39_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB40 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB40_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB41 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB41_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB42 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB42_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB43 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF10_5_CFDB43_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB44 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB44_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB45 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB45_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB46 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB46_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB47 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF11_5_CFDB47_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB48 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB48_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB49 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB49_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB50 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB50_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB51 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF12_5_CFDB51_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB52 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB52_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB53 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB53_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB54 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB54_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB55 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF13_5_CFDB55_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB56 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB56_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB57 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB57_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB58 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB58_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB59 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF14_5_CFDB59_SHIFT (24u) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB60 (0x000000FFu) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB60_SHIFT (0u) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB61 (0x0000FF00u) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB61_SHIFT (8u) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB62 (0x00FF0000u) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB62_SHIFT (16u) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB63 (0xFF000000u) +#define RCANFD_RSCFD0CFDCFDF15_5_CFDB63_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID0_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID0_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID0_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID0_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID0_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID0_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID0_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID0_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR0_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR0_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR0_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR0_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR0_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR0_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR0_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR0_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR0_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR0_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_0_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_0_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_0_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_0_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_0_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID1_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID1_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID1_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID1_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID1_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID1_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID1_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID1_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR1_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR1_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR1_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR1_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR1_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR1_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR1_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR1_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR1_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR1_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_1_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_1_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_1_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_1_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_1_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID2_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID2_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID2_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID2_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID2_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID2_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID2_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID2_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR2_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR2_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR2_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR2_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR2_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR2_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR2_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR2_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR2_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR2_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_2_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_2_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_2_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_2_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_2_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID3_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID3_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID3_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID3_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID3_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID3_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID3_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID3_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR3_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR3_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR3_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR3_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR3_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR3_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR3_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR3_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR3_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR3_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_3_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_3_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_3_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_3_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_3_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID4_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID4_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID4_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID4_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID4_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID4_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID4_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID4_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR4_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR4_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR4_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR4_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR4_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR4_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR4_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR4_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR4_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR4_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_4_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_4_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_4_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_4_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_4_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID5_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID5_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID5_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID5_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID5_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID5_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID5_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID5_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR5_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR5_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR5_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR5_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR5_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR5_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR5_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR5_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR5_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR5_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_5_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_5_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_5_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_5_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_5_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID6_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID6_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID6_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID6_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID6_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID6_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID6_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID6_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR6_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR6_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR6_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR6_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR6_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR6_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR6_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR6_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR6_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR6_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_6_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_6_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_6_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_6_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_6_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID7_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID7_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID7_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID7_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID7_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID7_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID7_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID7_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR7_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR7_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR7_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR7_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR7_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR7_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR7_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR7_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR7_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR7_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_7_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_7_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_7_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_7_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_7_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID8_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID8_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID8_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID8_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID8_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID8_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID8_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID8_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR8_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR8_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR8_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR8_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR8_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR8_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR8_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR8_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR8_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR8_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_8_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_8_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_8_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_8_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_8_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID9_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID9_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID9_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID9_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID9_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID9_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID9_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID9_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR9_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR9_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR9_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR9_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR9_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR9_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR9_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR9_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR9_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR9_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_9_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_9_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_9_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_9_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_9_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID10_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID10_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID10_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID10_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID10_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID10_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID10_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID10_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR10_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR10_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR10_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR10_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR10_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR10_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR10_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR10_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR10_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR10_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_10_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_10_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_10_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_10_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_10_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID11_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID11_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID11_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID11_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID11_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID11_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID11_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID11_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR11_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR11_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR11_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR11_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR11_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR11_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR11_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR11_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR11_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR11_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_11_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_11_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_11_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_11_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_11_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID12_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID12_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID12_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID12_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID12_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID12_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID12_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID12_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR12_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR12_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR12_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR12_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR12_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR12_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR12_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR12_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR12_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR12_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_12_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_12_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_12_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_12_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_12_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID13_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID13_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID13_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID13_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID13_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID13_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID13_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID13_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR13_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR13_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR13_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR13_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR13_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR13_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR13_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR13_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR13_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR13_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_13_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_13_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_13_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_13_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_13_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID14_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID14_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID14_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID14_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID14_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID14_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID14_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID14_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR14_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR14_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR14_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR14_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR14_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR14_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR14_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR14_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR14_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR14_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_14_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_14_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_14_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_14_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_14_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID15_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID15_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID15_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID15_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID15_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID15_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID15_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID15_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR15_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR15_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR15_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR15_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR15_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR15_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR15_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR15_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR15_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR15_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_15_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_15_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_15_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_15_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_15_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID16_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID16_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID16_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID16_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID16_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID16_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID16_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID16_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR16_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR16_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR16_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR16_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR16_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR16_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR16_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR16_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR16_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR16_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_16_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_16_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_16_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_16_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_16_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID17_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID17_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID17_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID17_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID17_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID17_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID17_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID17_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR17_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR17_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR17_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR17_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR17_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR17_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR17_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR17_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR17_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR17_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_17_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_17_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_17_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_17_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_17_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID18_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID18_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID18_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID18_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID18_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID18_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID18_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID18_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR18_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR18_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR18_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR18_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR18_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR18_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR18_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR18_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR18_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR18_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_18_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_18_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_18_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_18_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_18_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID19_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID19_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID19_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID19_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID19_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID19_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID19_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID19_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR19_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR19_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR19_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR19_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR19_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR19_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR19_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR19_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR19_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR19_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_19_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_19_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_19_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_19_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_19_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID20_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID20_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID20_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID20_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID20_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID20_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID20_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID20_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR20_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR20_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR20_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR20_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR20_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR20_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR20_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR20_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR20_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR20_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_20_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_20_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_20_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_20_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_20_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID21_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID21_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID21_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID21_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID21_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID21_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID21_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID21_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR21_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR21_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR21_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR21_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR21_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR21_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR21_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR21_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR21_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR21_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_21_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_21_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_21_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_21_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_21_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID22_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID22_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID22_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID22_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID22_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID22_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID22_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID22_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR22_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR22_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR22_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR22_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR22_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR22_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR22_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR22_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR22_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR22_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_22_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_22_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_22_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_22_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_22_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID23_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID23_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID23_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID23_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID23_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID23_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID23_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID23_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR23_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR23_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR23_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR23_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR23_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR23_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR23_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR23_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR23_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR23_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_23_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_23_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_23_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_23_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_23_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID24_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID24_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID24_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID24_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID24_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID24_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID24_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID24_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR24_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR24_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR24_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR24_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR24_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR24_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR24_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR24_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR24_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR24_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_24_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_24_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_24_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_24_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_24_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID25_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID25_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID25_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID25_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID25_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID25_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID25_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID25_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR25_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR25_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR25_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR25_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR25_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR25_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR25_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR25_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR25_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR25_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_25_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_25_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_25_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_25_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_25_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID26_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID26_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID26_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID26_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID26_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID26_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID26_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID26_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR26_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR26_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR26_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR26_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR26_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR26_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR26_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR26_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR26_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR26_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_26_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_26_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_26_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_26_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_26_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID27_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID27_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID27_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID27_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID27_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID27_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID27_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID27_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR27_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR27_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR27_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR27_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR27_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR27_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR27_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR27_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR27_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR27_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_27_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_27_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_27_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_27_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_27_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID28_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID28_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID28_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID28_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID28_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID28_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID28_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID28_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR28_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR28_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR28_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR28_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR28_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR28_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR28_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR28_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR28_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR28_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_28_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_28_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_28_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_28_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_28_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID29_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID29_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID29_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID29_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID29_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID29_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID29_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID29_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR29_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR29_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR29_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR29_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR29_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR29_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR29_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR29_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR29_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR29_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_29_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_29_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_29_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_29_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_29_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID30_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID30_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID30_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID30_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID30_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID30_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID30_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID30_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR30_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR30_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR30_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR30_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR30_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR30_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR30_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR30_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR30_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR30_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_30_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_30_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_30_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_30_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_30_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMID31_TMID (0x1FFFFFFFu) +#define RCANFD_RSCFD0CFDTMID31_TMID_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMID31_THLEN (0x20000000u) +#define RCANFD_RSCFD0CFDTMID31_THLEN_SHIFT (29u) +#define RCANFD_RSCFD0CFDTMID31_TMRTR (0x40000000u) +#define RCANFD_RSCFD0CFDTMID31_TMRTR_SHIFT (30u) +#define RCANFD_RSCFD0CFDTMID31_TMIDE (0x80000000u) +#define RCANFD_RSCFD0CFDTMID31_TMIDE_SHIFT (31u) +#define RCANFD_RSCFD0CFDTMPTR31_TMPTR (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMPTR31_TMPTR_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMPTR31_TMDLC (0xF0000000u) +#define RCANFD_RSCFD0CFDTMPTR31_TMDLC_SHIFT (28u) +#define RCANFD_RSCFD0CFDTMFDCTR31_TMESI (0x00000001u) +#define RCANFD_RSCFD0CFDTMFDCTR31_TMESI_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMFDCTR31_TMBRS (0x00000002u) +#define RCANFD_RSCFD0CFDTMFDCTR31_TMBRS_SHIFT (1u) +#define RCANFD_RSCFD0CFDTMFDCTR31_TMFDF (0x00000004u) +#define RCANFD_RSCFD0CFDTMFDCTR31_TMFDF_SHIFT (2u) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB0 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB0_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB1 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB1_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB2 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB2_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB3 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF0_31_TMDB3_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB4 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB4_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB5 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB5_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB6 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB6_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB7 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF1_31_TMDB7_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB8 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB8_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB9 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB9_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB10 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB10_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB11 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF2_31_TMDB11_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB12 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB12_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB13 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB13_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB14 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB14_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB15 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF3_31_TMDB15_SHIFT (24u) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB16 (0x000000FFu) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB16_SHIFT (0u) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB17 (0x0000FF00u) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB17_SHIFT (8u) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB18 (0x00FF0000u) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB18_SHIFT (16u) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB19 (0xFF000000u) +#define RCANFD_RSCFD0CFDTMDF4_31_TMDB19_SHIFT (24u) +#define RCANFD_RSCFD0CFDTHLACC0_BT (0x00000007u) +#define RCANFD_RSCFD0CFDTHLACC0_BT_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLACC0_BN (0x00000078u) +#define RCANFD_RSCFD0CFDTHLACC0_BN_SHIFT (3u) +#define RCANFD_RSCFD0CFDTHLACC0_TID (0x0000FF00u) +#define RCANFD_RSCFD0CFDTHLACC0_TID_SHIFT (8u) +#define RCANFD_RSCFD0CFDTHLACC0_TMTS (0xFFFF0000u) +#define RCANFD_RSCFD0CFDTHLACC0_TMTS_SHIFT (16u) +#define RCANFD_RSCFD0CFDTHLACC1_BT (0x00000007u) +#define RCANFD_RSCFD0CFDTHLACC1_BT_SHIFT (0u) +#define RCANFD_RSCFD0CFDTHLACC1_BN (0x00000078u) +#define RCANFD_RSCFD0CFDTHLACC1_BN_SHIFT (3u) +#define RCANFD_RSCFD0CFDTHLACC1_TID (0x0000FF00u) +#define RCANFD_RSCFD0CFDTHLACC1_TID_SHIFT (8u) +#define RCANFD_RSCFD0CFDTHLACC1_TMTS (0xFFFF0000u) +#define RCANFD_RSCFD0CFDTHLACC1_TMTS_SHIFT (16u) +#define RCANFD_RSCFD0CFDRPGACC0_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC0_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC1_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC1_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC2_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC2_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC3_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC3_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC4_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC4_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC5_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC5_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC6_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC6_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC7_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC7_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC8_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC8_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC9_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC9_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC10_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC10_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC11_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC11_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC12_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC12_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC13_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC13_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC14_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC14_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC15_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC15_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC16_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC16_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC17_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC17_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC18_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC18_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC19_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC19_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC20_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC20_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC21_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC21_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC22_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC22_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC23_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC23_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC24_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC24_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC25_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC25_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC26_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC26_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC27_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC27_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC28_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC28_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC29_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC29_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC30_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC30_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC31_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC31_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC32_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC32_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC33_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC33_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC34_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC34_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC35_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC35_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC36_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC36_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC37_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC37_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC38_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC38_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC39_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC39_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC40_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC40_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC41_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC41_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC42_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC42_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC43_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC43_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC44_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC44_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC45_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC45_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC46_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC46_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC47_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC47_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC48_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC48_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC49_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC49_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC50_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC50_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC51_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC51_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC52_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC52_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC53_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC53_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC54_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC54_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC55_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC55_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC56_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC56_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC57_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC57_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC58_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC58_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC59_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC59_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC60_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC60_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC61_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC61_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC62_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC62_RDTA_SHIFT (0u) +#define RCANFD_RSCFD0CFDRPGACC63_RDTA (0xFFFFFFFFu) +#define RCANFD_RSCFD0CFDRPGACC63_RDTA_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/riic_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/riic_iobitmask.h new file mode 100644 index 0000000..a2632cc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/riic_iobitmask.h @@ -0,0 +1,206 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef RIIC_IOBITMASK_H +#define RIIC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define RIIC_ICCR1_SDAI (0x00000001u) +#define RIIC_ICCR1_SDAI_SHIFT (0u) +#define RIIC_ICCR1_SCLI (0x00000002u) +#define RIIC_ICCR1_SCLI_SHIFT (1u) +#define RIIC_ICCR1_SDAO (0x00000004u) +#define RIIC_ICCR1_SDAO_SHIFT (2u) +#define RIIC_ICCR1_SCLO (0x00000008u) +#define RIIC_ICCR1_SCLO_SHIFT (3u) +#define RIIC_ICCR1_SOWP (0x00000010u) +#define RIIC_ICCR1_SOWP_SHIFT (4u) +#define RIIC_ICCR1_CLO (0x00000020u) +#define RIIC_ICCR1_CLO_SHIFT (5u) +#define RIIC_ICCR1_IICRST (0x00000040u) +#define RIIC_ICCR1_IICRST_SHIFT (6u) +#define RIIC_ICCR1_ICE (0x00000080u) +#define RIIC_ICCR1_ICE_SHIFT (7u) +#define RIIC_ICCR2_ST (0x00000002u) +#define RIIC_ICCR2_ST_SHIFT (1u) +#define RIIC_ICCR2_RS (0x00000004u) +#define RIIC_ICCR2_RS_SHIFT (2u) +#define RIIC_ICCR2_SP (0x00000008u) +#define RIIC_ICCR2_SP_SHIFT (3u) +#define RIIC_ICCR2_TRS (0x00000020u) +#define RIIC_ICCR2_TRS_SHIFT (5u) +#define RIIC_ICCR2_MST (0x00000040u) +#define RIIC_ICCR2_MST_SHIFT (6u) +#define RIIC_ICCR2_BBSY (0x00000080u) +#define RIIC_ICCR2_BBSY_SHIFT (7u) +#define RIIC_ICMR1_BC (0x00000007u) +#define RIIC_ICMR1_BC_SHIFT (0u) +#define RIIC_ICMR1_BCWP (0x00000008u) +#define RIIC_ICMR1_BCWP_SHIFT (3u) +#define RIIC_ICMR1_CKS (0x00000070u) +#define RIIC_ICMR1_CKS_SHIFT (4u) +#define RIIC_ICMR2_TMOS (0x00000001u) +#define RIIC_ICMR2_TMOS_SHIFT (0u) +#define RIIC_ICMR2_TMOL (0x00000002u) +#define RIIC_ICMR2_TMOL_SHIFT (1u) +#define RIIC_ICMR2_TMOH (0x00000004u) +#define RIIC_ICMR2_TMOH_SHIFT (2u) +#define RIIC_ICMR2_SDDL (0x00000070u) +#define RIIC_ICMR2_SDDL_SHIFT (4u) +#define RIIC_ICMR2_DLCS (0x00000080u) +#define RIIC_ICMR2_DLCS_SHIFT (7u) +#define RIIC_ICMR3_NF (0x00000003u) +#define RIIC_ICMR3_NF_SHIFT (0u) +#define RIIC_ICMR3_ACKBR (0x00000004u) +#define RIIC_ICMR3_ACKBR_SHIFT (2u) +#define RIIC_ICMR3_ACKBT (0x00000008u) +#define RIIC_ICMR3_ACKBT_SHIFT (3u) +#define RIIC_ICMR3_ACKWP (0x00000010u) +#define RIIC_ICMR3_ACKWP_SHIFT (4u) +#define RIIC_ICMR3_RDRFS (0x00000020u) +#define RIIC_ICMR3_RDRFS_SHIFT (5u) +#define RIIC_ICMR3_WAIT (0x00000040u) +#define RIIC_ICMR3_WAIT_SHIFT (6u) +#define RIIC_ICMR3_SMBE (0x00000080u) +#define RIIC_ICMR3_SMBE_SHIFT (7u) +#define RIIC_ICFER_TMOE (0x00000001u) +#define RIIC_ICFER_TMOE_SHIFT (0u) +#define RIIC_ICFER_MALE (0x00000002u) +#define RIIC_ICFER_MALE_SHIFT (1u) +#define RIIC_ICFER_NALE (0x00000004u) +#define RIIC_ICFER_NALE_SHIFT (2u) +#define RIIC_ICFER_SALE (0x00000008u) +#define RIIC_ICFER_SALE_SHIFT (3u) +#define RIIC_ICFER_NACKE (0x00000010u) +#define RIIC_ICFER_NACKE_SHIFT (4u) +#define RIIC_ICFER_NFE (0x00000020u) +#define RIIC_ICFER_NFE_SHIFT (5u) +#define RIIC_ICFER_SCLE (0x00000040u) +#define RIIC_ICFER_SCLE_SHIFT (6u) +#define RIIC_ICFER_FMPE (0x00000080u) +#define RIIC_ICFER_FMPE_SHIFT (7u) +#define RIIC_ICSER_SAR0 (0x00000001u) +#define RIIC_ICSER_SAR0_SHIFT (0u) +#define RIIC_ICSER_SAR1 (0x00000002u) +#define RIIC_ICSER_SAR1_SHIFT (1u) +#define RIIC_ICSER_SAR2 (0x00000004u) +#define RIIC_ICSER_SAR2_SHIFT (2u) +#define RIIC_ICSER_GCE (0x00000008u) +#define RIIC_ICSER_GCE_SHIFT (3u) +#define RIIC_ICSER_DIDE (0x00000020u) +#define RIIC_ICSER_DIDE_SHIFT (5u) +#define RIIC_ICSER_HOAE (0x00000080u) +#define RIIC_ICSER_HOAE_SHIFT (7u) +#define RIIC_ICIER_TMOIE (0x00000001u) +#define RIIC_ICIER_TMOIE_SHIFT (0u) +#define RIIC_ICIER_ALIE (0x00000002u) +#define RIIC_ICIER_ALIE_SHIFT (1u) +#define RIIC_ICIER_STIE (0x00000004u) +#define RIIC_ICIER_STIE_SHIFT (2u) +#define RIIC_ICIER_SPIE (0x00000008u) +#define RIIC_ICIER_SPIE_SHIFT (3u) +#define RIIC_ICIER_NAKIE (0x00000010u) +#define RIIC_ICIER_NAKIE_SHIFT (4u) +#define RIIC_ICIER_RIE (0x00000020u) +#define RIIC_ICIER_RIE_SHIFT (5u) +#define RIIC_ICIER_TEIE (0x00000040u) +#define RIIC_ICIER_TEIE_SHIFT (6u) +#define RIIC_ICIER_TIE (0x00000080u) +#define RIIC_ICIER_TIE_SHIFT (7u) +#define RIIC_ICSR1_AAS0 (0x00000001u) +#define RIIC_ICSR1_AAS0_SHIFT (0u) +#define RIIC_ICSR1_AAS1 (0x00000002u) +#define RIIC_ICSR1_AAS1_SHIFT (1u) +#define RIIC_ICSR1_AAS2 (0x00000004u) +#define RIIC_ICSR1_AAS2_SHIFT (2u) +#define RIIC_ICSR1_GCA (0x00000008u) +#define RIIC_ICSR1_GCA_SHIFT (3u) +#define RIIC_ICSR1_DID (0x00000020u) +#define RIIC_ICSR1_DID_SHIFT (5u) +#define RIIC_ICSR1_HOA (0x00000080u) +#define RIIC_ICSR1_HOA_SHIFT (7u) +#define RIIC_ICSR2_TMOF (0x00000001u) +#define RIIC_ICSR2_TMOF_SHIFT (0u) +#define RIIC_ICSR2_AL (0x00000002u) +#define RIIC_ICSR2_AL_SHIFT (1u) +#define RIIC_ICSR2_START (0x00000004u) +#define RIIC_ICSR2_START_SHIFT (2u) +#define RIIC_ICSR2_STOP (0x00000008u) +#define RIIC_ICSR2_STOP_SHIFT (3u) +#define RIIC_ICSR2_NACKF (0x00000010u) +#define RIIC_ICSR2_NACKF_SHIFT (4u) +#define RIIC_ICSR2_RDRF (0x00000020u) +#define RIIC_ICSR2_RDRF_SHIFT (5u) +#define RIIC_ICSR2_TEND (0x00000040u) +#define RIIC_ICSR2_TEND_SHIFT (6u) +#define RIIC_ICSR2_TDRE (0x00000080u) +#define RIIC_ICSR2_TDRE_SHIFT (7u) +#define RIIC_ICSAR0_SVA0 (0x00000001u) +#define RIIC_ICSAR0_SVA0_SHIFT (0u) +#define RIIC_ICSAR0_SVA (0x000003FCu) +#define RIIC_ICSAR0_SVA_SHIFT (1u) +#define RIIC_ICSAR0_FS0 (0x00008000u) +#define RIIC_ICSAR0_FS0_SHIFT (15u) +#define RIIC_ICSAR1_SVA0 (0x00000001u) +#define RIIC_ICSAR1_SVA0_SHIFT (0u) +#define RIIC_ICSAR1_SVA (0x000003FCu) +#define RIIC_ICSAR1_SVA_SHIFT (1u) +#define RIIC_ICSAR1_FS1 (0x00008000u) +#define RIIC_ICSAR1_FS1_SHIFT (15u) +#define RIIC_ICSAR2_SVA0 (0x00000001u) +#define RIIC_ICSAR2_SVA0_SHIFT (0u) +#define RIIC_ICSAR2_SVA (0x000003FCu) +#define RIIC_ICSAR2_SVA_SHIFT (1u) +#define RIIC_ICSAR2_FS2 (0x00008000u) +#define RIIC_ICSAR2_FS2_SHIFT (15u) +#define RIIC_ICBRL_BRL (0x0000001Fu) +#define RIIC_ICBRL_BRL_SHIFT (0u) +#define RIIC_ICBRH_BRH (0x0000001Fu) +#define RIIC_ICBRH_BRH_SHIFT (0u) +#define RIIC_ICDRT_DRT (0x000000FFu) +#define RIIC_ICDRT_DRT_SHIFT (0u) +#define RIIC_ICDRR_DRR (0x000000FFu) +#define RIIC_ICDRR_DRR_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rspi_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rspi_iobitmask.h new file mode 100644 index 0000000..468963e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rspi_iobitmask.h @@ -0,0 +1,308 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef RSPI_IOBITMASK_H +#define RSPI_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define RSPI_SPCR_MODFEN (0x04u) +#define RSPI_SPCR_MODFEN_SHIFT (2u) +#define RSPI_SPCR_MSTR (0x08u) +#define RSPI_SPCR_MSTR_SHIFT (3u) +#define RSPI_SPCR_SPEIE (0x10u) +#define RSPI_SPCR_SPEIE_SHIFT (4u) +#define RSPI_SPCR_SPTIE (0x20u) +#define RSPI_SPCR_SPTIE_SHIFT (5u) +#define RSPI_SPCR_SPE (0x40u) +#define RSPI_SPCR_SPE_SHIFT (6u) +#define RSPI_SPCR_SPRIE (0x80u) +#define RSPI_SPCR_SPRIE_SHIFT (7u) +#define RSPI_SSLP_SSL0P (0x01u) +#define RSPI_SSLP_SSL0P_SHIFT (0u) +#define RSPI_SPPCR_SPLP (0x01u) +#define RSPI_SPPCR_SPLP_SHIFT (0u) +#define RSPI_SPPCR_MOIFV (0x10u) +#define RSPI_SPPCR_MOIFV_SHIFT (4u) +#define RSPI_SPPCR_MOIFE (0x20u) +#define RSPI_SPPCR_MOIFE_SHIFT (5u) +#define RSPI_SPSR_OVRF (0x01u) +#define RSPI_SPSR_OVRF_SHIFT (0u) +#define RSPI_SPSR_MODF (0x04u) +#define RSPI_SPSR_MODF_SHIFT (2u) +#define RSPI_SPSR_SPTEF (0x20u) +#define RSPI_SPSR_SPTEF_SHIFT (5u) +#define RSPI_SPSR_TEND (0x40u) +#define RSPI_SPSR_TEND_SHIFT (6u) +#define RSPI_SPSR_SPRF (0x80u) +#define RSPI_SPSR_SPRF_SHIFT (7u) +#define RSPI_SPDR_SPD0 (0x00000001u) +#define RSPI_SPDR_SPD0_SHIFT (0u) +#define RSPI_SPDR_SPD1 (0x00000002u) +#define RSPI_SPDR_SPD1_SHIFT (1u) +#define RSPI_SPDR_SPD2 (0x00000004u) +#define RSPI_SPDR_SPD2_SHIFT (2u) +#define RSPI_SPDR_SPD3 (0x00000008u) +#define RSPI_SPDR_SPD3_SHIFT (3u) +#define RSPI_SPDR_SPD4 (0x00000010u) +#define RSPI_SPDR_SPD4_SHIFT (4u) +#define RSPI_SPDR_SPD5 (0x00000020u) +#define RSPI_SPDR_SPD5_SHIFT (5u) +#define RSPI_SPDR_SPD6 (0x00000040u) +#define RSPI_SPDR_SPD6_SHIFT (6u) +#define RSPI_SPDR_SPD7 (0x00000080u) +#define RSPI_SPDR_SPD7_SHIFT (7u) +#define RSPI_SPDR_SPD8 (0x00000100u) +#define RSPI_SPDR_SPD8_SHIFT (8u) +#define RSPI_SPDR_SPD9 (0x00000200u) +#define RSPI_SPDR_SPD9_SHIFT (9u) +#define RSPI_SPDR_SPD10 (0x00000400u) +#define RSPI_SPDR_SPD10_SHIFT (10u) +#define RSPI_SPDR_SPD11 (0x00000800u) +#define RSPI_SPDR_SPD11_SHIFT (11u) +#define RSPI_SPDR_SPD12 (0x00001000u) +#define RSPI_SPDR_SPD12_SHIFT (12u) +#define RSPI_SPDR_SPD13 (0x00002000u) +#define RSPI_SPDR_SPD13_SHIFT (13u) +#define RSPI_SPDR_SPD14 (0x00004000u) +#define RSPI_SPDR_SPD14_SHIFT (14u) +#define RSPI_SPDR_SPD15 (0x00008000u) +#define RSPI_SPDR_SPD15_SHIFT (15u) +#define RSPI_SPDR_SPD16 (0x00010000u) +#define RSPI_SPDR_SPD16_SHIFT (16u) +#define RSPI_SPDR_SPD17 (0x00020000u) +#define RSPI_SPDR_SPD17_SHIFT (17u) +#define RSPI_SPDR_SPD18 (0x00040000u) +#define RSPI_SPDR_SPD18_SHIFT (18u) +#define RSPI_SPDR_SPD19 (0x00080000u) +#define RSPI_SPDR_SPD19_SHIFT (19u) +#define RSPI_SPDR_SPD20 (0x00100000u) +#define RSPI_SPDR_SPD20_SHIFT (20u) +#define RSPI_SPDR_SPD21 (0x00200000u) +#define RSPI_SPDR_SPD21_SHIFT (21u) +#define RSPI_SPDR_SPD22 (0x00400000u) +#define RSPI_SPDR_SPD22_SHIFT (22u) +#define RSPI_SPDR_SPD23 (0x00800000u) +#define RSPI_SPDR_SPD23_SHIFT (23u) +#define RSPI_SPDR_SPD24 (0x01000000u) +#define RSPI_SPDR_SPD24_SHIFT (24u) +#define RSPI_SPDR_SPD25 (0x02000000u) +#define RSPI_SPDR_SPD25_SHIFT (25u) +#define RSPI_SPDR_SPD26 (0x04000000u) +#define RSPI_SPDR_SPD26_SHIFT (26u) +#define RSPI_SPDR_SPD27 (0x08000000u) +#define RSPI_SPDR_SPD27_SHIFT (27u) +#define RSPI_SPDR_SPD28 (0x10000000u) +#define RSPI_SPDR_SPD28_SHIFT (28u) +#define RSPI_SPDR_SPD29 (0x20000000u) +#define RSPI_SPDR_SPD29_SHIFT (29u) +#define RSPI_SPDR_SPD30 (0x40000000u) +#define RSPI_SPDR_SPD30_SHIFT (30u) +#define RSPI_SPDR_SPD31 (0x80000000u) +#define RSPI_SPDR_SPD31_SHIFT (31u) +#define RSPI_SPSCR_SPSLN0 (0x01u) +#define RSPI_SPSCR_SPSLN0_SHIFT (0u) +#define RSPI_SPSCR_SPSLN1 (0x02u) +#define RSPI_SPSCR_SPSLN1_SHIFT (1u) +#define RSPI_SPSSR_SPCP0 (0x01u) +#define RSPI_SPSSR_SPCP0_SHIFT (0u) +#define RSPI_SPSSR_SPCP1 (0x02u) +#define RSPI_SPSSR_SPCP1_SHIFT (1u) +#define RSPI_SPBR_SPR0 (0x01u) +#define RSPI_SPBR_SPR0_SHIFT (0u) +#define RSPI_SPBR_SPR1 (0x02u) +#define RSPI_SPBR_SPR1_SHIFT (1u) +#define RSPI_SPBR_SPR2 (0x04u) +#define RSPI_SPBR_SPR2_SHIFT (2u) +#define RSPI_SPBR_SPR3 (0x08u) +#define RSPI_SPBR_SPR3_SHIFT (3u) +#define RSPI_SPBR_SPR4 (0x10u) +#define RSPI_SPBR_SPR4_SHIFT (4u) +#define RSPI_SPBR_SPR5 (0x20u) +#define RSPI_SPBR_SPR5_SHIFT (5u) +#define RSPI_SPBR_SPR6 (0x40u) +#define RSPI_SPBR_SPR6_SHIFT (6u) +#define RSPI_SPBR_SPR7 (0x80u) +#define RSPI_SPBR_SPR7_SHIFT (7u) +#define RSPI_SPDCR_SPLW0 (0x20u) +#define RSPI_SPDCR_SPLW0_SHIFT (5u) +#define RSPI_SPDCR_SPLW1 (0x40u) +#define RSPI_SPDCR_SPLW1_SHIFT (6u) +#define RSPI_SPDCR_TXDMY (0x80u) +#define RSPI_SPDCR_TXDMY_SHIFT (7u) +#define RSPI_SPCKD_SCKDL0 (0x01u) +#define RSPI_SPCKD_SCKDL0_SHIFT (0u) +#define RSPI_SPCKD_SCKDL1 (0x02u) +#define RSPI_SPCKD_SCKDL1_SHIFT (1u) +#define RSPI_SPCKD_SCKDL2 (0x04u) +#define RSPI_SPCKD_SCKDL2_SHIFT (2u) +#define RSPI_SSLND_SLNDL0 (0x01u) +#define RSPI_SSLND_SLNDL0_SHIFT (0u) +#define RSPI_SSLND_SLNDL1 (0x02u) +#define RSPI_SSLND_SLNDL1_SHIFT (1u) +#define RSPI_SSLND_SLNDL2 (0x04u) +#define RSPI_SSLND_SLNDL2_SHIFT (2u) +#define RSPI_SPND_SPNDL0 (0x01u) +#define RSPI_SPND_SPNDL0_SHIFT (0u) +#define RSPI_SPND_SPNDL1 (0x02u) +#define RSPI_SPND_SPNDL1_SHIFT (1u) +#define RSPI_SPND_SPNDL2 (0x04u) +#define RSPI_SPND_SPNDL2_SHIFT (2u) +#define RSPI_SPCMD0_CPHA (0x0001u) +#define RSPI_SPCMD0_CPHA_SHIFT (0u) +#define RSPI_SPCMD0_CPOL (0x0002u) +#define RSPI_SPCMD0_CPOL_SHIFT (1u) +#define RSPI_SPCMD0_BRDV0 (0x0004u) +#define RSPI_SPCMD0_BRDV0_SHIFT (2u) +#define RSPI_SPCMD0_BRDV1 (0x0008u) +#define RSPI_SPCMD0_BRDV1_SHIFT (3u) +#define RSPI_SPCMD0_SSLKP (0x0080u) +#define RSPI_SPCMD0_SSLKP_SHIFT (7u) +#define RSPI_SPCMD0_SPB0 (0x0100u) +#define RSPI_SPCMD0_SPB0_SHIFT (8u) +#define RSPI_SPCMD0_SPB1 (0x0200u) +#define RSPI_SPCMD0_SPB1_SHIFT (9u) +#define RSPI_SPCMD0_SPB2 (0x0400u) +#define RSPI_SPCMD0_SPB2_SHIFT (10u) +#define RSPI_SPCMD0_SPB3 (0x0800u) +#define RSPI_SPCMD0_SPB3_SHIFT (11u) +#define RSPI_SPCMD0_LSBF (0x1000u) +#define RSPI_SPCMD0_LSBF_SHIFT (12u) +#define RSPI_SPCMD0_SPNDEN (0x2000u) +#define RSPI_SPCMD0_SPNDEN_SHIFT (13u) +#define RSPI_SPCMD0_SLNDEN (0x4000u) +#define RSPI_SPCMD0_SLNDEN_SHIFT (14u) +#define RSPI_SPCMD0_SCKDEN (0x8000u) +#define RSPI_SPCMD0_SCKDEN_SHIFT (15u) +#define RSPI_SPCMD1_CPHA (0x0001u) +#define RSPI_SPCMD1_CPHA_SHIFT (0u) +#define RSPI_SPCMD1_CPOL (0x0002u) +#define RSPI_SPCMD1_CPOL_SHIFT (1u) +#define RSPI_SPCMD1_BRDV0 (0x0004u) +#define RSPI_SPCMD1_BRDV0_SHIFT (2u) +#define RSPI_SPCMD1_BRDV1 (0x0008u) +#define RSPI_SPCMD1_BRDV1_SHIFT (3u) +#define RSPI_SPCMD1_SSLKP (0x0080u) +#define RSPI_SPCMD1_SSLKP_SHIFT (7u) +#define RSPI_SPCMD1_SPB0 (0x0100u) +#define RSPI_SPCMD1_SPB0_SHIFT (8u) +#define RSPI_SPCMD1_SPB1 (0x0200u) +#define RSPI_SPCMD1_SPB1_SHIFT (9u) +#define RSPI_SPCMD1_SPB2 (0x0400u) +#define RSPI_SPCMD1_SPB2_SHIFT (10u) +#define RSPI_SPCMD1_SPB3 (0x0800u) +#define RSPI_SPCMD1_SPB3_SHIFT (11u) +#define RSPI_SPCMD1_LSBF (0x1000u) +#define RSPI_SPCMD1_LSBF_SHIFT (12u) +#define RSPI_SPCMD1_SPNDEN (0x2000u) +#define RSPI_SPCMD1_SPNDEN_SHIFT (13u) +#define RSPI_SPCMD1_SLNDEN (0x4000u) +#define RSPI_SPCMD1_SLNDEN_SHIFT (14u) +#define RSPI_SPCMD1_SCKDEN (0x8000u) +#define RSPI_SPCMD1_SCKDEN_SHIFT (15u) +#define RSPI_SPCMD2_CPHA (0x0001u) +#define RSPI_SPCMD2_CPHA_SHIFT (0u) +#define RSPI_SPCMD2_CPOL (0x0002u) +#define RSPI_SPCMD2_CPOL_SHIFT (1u) +#define RSPI_SPCMD2_BRDV0 (0x0004u) +#define RSPI_SPCMD2_BRDV0_SHIFT (2u) +#define RSPI_SPCMD2_BRDV1 (0x0008u) +#define RSPI_SPCMD2_BRDV1_SHIFT (3u) +#define RSPI_SPCMD2_SSLKP (0x0080u) +#define RSPI_SPCMD2_SSLKP_SHIFT (7u) +#define RSPI_SPCMD2_SPB0 (0x0100u) +#define RSPI_SPCMD2_SPB0_SHIFT (8u) +#define RSPI_SPCMD2_SPB1 (0x0200u) +#define RSPI_SPCMD2_SPB1_SHIFT (9u) +#define RSPI_SPCMD2_SPB2 (0x0400u) +#define RSPI_SPCMD2_SPB2_SHIFT (10u) +#define RSPI_SPCMD2_SPB3 (0x0800u) +#define RSPI_SPCMD2_SPB3_SHIFT (11u) +#define RSPI_SPCMD2_LSBF (0x1000u) +#define RSPI_SPCMD2_LSBF_SHIFT (12u) +#define RSPI_SPCMD2_SPNDEN (0x2000u) +#define RSPI_SPCMD2_SPNDEN_SHIFT (13u) +#define RSPI_SPCMD2_SLNDEN (0x4000u) +#define RSPI_SPCMD2_SLNDEN_SHIFT (14u) +#define RSPI_SPCMD2_SCKDEN (0x8000u) +#define RSPI_SPCMD2_SCKDEN_SHIFT (15u) +#define RSPI_SPCMD3_CPHA (0x0001u) +#define RSPI_SPCMD3_CPHA_SHIFT (0u) +#define RSPI_SPCMD3_CPOL (0x0002u) +#define RSPI_SPCMD3_CPOL_SHIFT (1u) +#define RSPI_SPCMD3_BRDV0 (0x0004u) +#define RSPI_SPCMD3_BRDV0_SHIFT (2u) +#define RSPI_SPCMD3_BRDV1 (0x0008u) +#define RSPI_SPCMD3_BRDV1_SHIFT (3u) +#define RSPI_SPCMD3_SSLKP (0x0080u) +#define RSPI_SPCMD3_SSLKP_SHIFT (7u) +#define RSPI_SPCMD3_SPB0 (0x0100u) +#define RSPI_SPCMD3_SPB0_SHIFT (8u) +#define RSPI_SPCMD3_SPB1 (0x0200u) +#define RSPI_SPCMD3_SPB1_SHIFT (9u) +#define RSPI_SPCMD3_SPB2 (0x0400u) +#define RSPI_SPCMD3_SPB2_SHIFT (10u) +#define RSPI_SPCMD3_SPB3 (0x0800u) +#define RSPI_SPCMD3_SPB3_SHIFT (11u) +#define RSPI_SPCMD3_LSBF (0x1000u) +#define RSPI_SPCMD3_LSBF_SHIFT (12u) +#define RSPI_SPCMD3_SPNDEN (0x2000u) +#define RSPI_SPCMD3_SPNDEN_SHIFT (13u) +#define RSPI_SPCMD3_SLNDEN (0x4000u) +#define RSPI_SPCMD3_SLNDEN_SHIFT (14u) +#define RSPI_SPCMD3_SCKDEN (0x8000u) +#define RSPI_SPCMD3_SCKDEN_SHIFT (15u) +#define RSPI_SPBFCR_RXTRG (0x07u) +#define RSPI_SPBFCR_RXTRG_SHIFT (0u) +#define RSPI_SPBFCR_TXTRG (0x30u) +#define RSPI_SPBFCR_TXTRG_SHIFT (4u) +#define RSPI_SPBFCR_RXRST (0x40u) +#define RSPI_SPBFCR_RXRST_SHIFT (6u) +#define RSPI_SPBFCR_TXRST (0x80u) +#define RSPI_SPBFCR_TXRST_SHIFT (7u) +#define RSPI_SPBFDR_R (0x003Fu) +#define RSPI_SPBFDR_R_SHIFT (0u) +#define RSPI_SPBFDR_T (0x0F00u) +#define RSPI_SPBFDR_T_SHIFT (8u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rtc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rtc_iobitmask.h new file mode 100644 index 0000000..90dc889 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/rtc_iobitmask.h @@ -0,0 +1,198 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef RTC_IOBITMASK_H +#define RTC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define RTC_R64CNT_F64HZ (0x01u) +#define RTC_R64CNT_F64HZ_SHIFT (0u) +#define RTC_R64CNT_F32HZ (0x02u) +#define RTC_R64CNT_F32HZ_SHIFT (1u) +#define RTC_R64CNT_F16HZ (0x04u) +#define RTC_R64CNT_F16HZ_SHIFT (2u) +#define RTC_R64CNT_F8HZ (0x08u) +#define RTC_R64CNT_F8HZ_SHIFT (3u) +#define RTC_R64CNT_F4HZ (0x10u) +#define RTC_R64CNT_F4HZ_SHIFT (4u) +#define RTC_R64CNT_F2HZ (0x20u) +#define RTC_R64CNT_F2HZ_SHIFT (5u) +#define RTC_R64CNT_F1HZ (0x40u) +#define RTC_R64CNT_F1HZ_SHIFT (6u) +#define RTC_RSECCNT_SEC1 (0x0Fu) +#define RTC_RSECCNT_SEC1_SHIFT (0u) +#define RTC_RSECCNT_SEC10 (0x70u) +#define RTC_RSECCNT_SEC10_SHIFT (4u) +#define RTC_RMINCNT_MIN1 (0x0Fu) +#define RTC_RMINCNT_MIN1_SHIFT (0u) +#define RTC_RMINCNT_MIN10 (0x70u) +#define RTC_RMINCNT_MIN10_SHIFT (4u) +#define RTC_RHRCNT_HR1 (0x0Fu) +#define RTC_RHRCNT_HR1_SHIFT (0u) +#define RTC_RHRCNT_HR10 (0x30u) +#define RTC_RHRCNT_HR10_SHIFT (4u) +#define RTC_RHRCNT_PM (0x40u) +#define RTC_RHRCNT_PM_SHIFT (6u) +#define RTC_RWKCNT_DAYW (0x07u) +#define RTC_RWKCNT_DAYW_SHIFT (0u) +#define RTC_RDAYCNT_DATE1 (0x0Fu) +#define RTC_RDAYCNT_DATE1_SHIFT (0u) +#define RTC_RDAYCNT_DATE10 (0x30u) +#define RTC_RDAYCNT_DATE10_SHIFT (4u) +#define RTC_RMONCNT_MON1 (0x0Fu) +#define RTC_RMONCNT_MON1_SHIFT (0u) +#define RTC_RMONCNT_MON10 (0x10u) +#define RTC_RMONCNT_MON10_SHIFT (4u) +#define RTC_RYRCNT_YR1 (0x000Fu) +#define RTC_RYRCNT_YR1_SHIFT (0u) +#define RTC_RYRCNT_YR10 (0x00F0u) +#define RTC_RYRCNT_YR10_SHIFT (4u) +#define RTC_RSECAR_SEC1 (0x0Fu) +#define RTC_RSECAR_SEC1_SHIFT (0u) +#define RTC_RSECAR_SEC10 (0x70u) +#define RTC_RSECAR_SEC10_SHIFT (4u) +#define RTC_RSECAR_ENB (0x80u) +#define RTC_RSECAR_ENB_SHIFT (7u) +#define RTC_RMINAR_MIN1 (0x0Fu) +#define RTC_RMINAR_MIN1_SHIFT (0u) +#define RTC_RMINAR_MIN10 (0x70u) +#define RTC_RMINAR_MIN10_SHIFT (4u) +#define RTC_RMINAR_ENB (0x80u) +#define RTC_RMINAR_ENB_SHIFT (7u) +#define RTC_RHRAR_HR1 (0x0Fu) +#define RTC_RHRAR_HR1_SHIFT (0u) +#define RTC_RHRAR_HR10 (0x30u) +#define RTC_RHRAR_HR10_SHIFT (4u) +#define RTC_RHRAR_PM (0x40u) +#define RTC_RHRAR_PM_SHIFT (6u) +#define RTC_RHRAR_ENB (0x80u) +#define RTC_RHRAR_ENB_SHIFT (7u) +#define RTC_RWKAR_DAYW (0x07u) +#define RTC_RWKAR_DAYW_SHIFT (0u) +#define RTC_RWKAR_ENB (0x80u) +#define RTC_RWKAR_ENB_SHIFT (7u) +#define RTC_RDAYAR_DATE1 (0x0Fu) +#define RTC_RDAYAR_DATE1_SHIFT (0u) +#define RTC_RDAYAR_DATE10 (0x30u) +#define RTC_RDAYAR_DATE10_SHIFT (4u) +#define RTC_RDAYAR_ENB (0x80u) +#define RTC_RDAYAR_ENB_SHIFT (7u) +#define RTC_RMONAR_MON1 (0x0Fu) +#define RTC_RMONAR_MON1_SHIFT (0u) +#define RTC_RMONAR_MON10 (0x10u) +#define RTC_RMONAR_MON10_SHIFT (4u) +#define RTC_RMONAR_ENB (0x80u) +#define RTC_RMONAR_ENB_SHIFT (7u) +#define RTC_RYRAR_YR1 (0x000Fu) +#define RTC_RYRAR_YR1_SHIFT (0u) +#define RTC_RYRAR_YR10 (0x00F0u) +#define RTC_RYRAR_YR10_SHIFT (4u) +#define RTC_RYRAREN_ENB (0x80u) +#define RTC_RYRAREN_ENB_SHIFT (7u) +#define RTC_RSR_AF (0x01u) +#define RTC_RSR_AF_SHIFT (0u) +#define RTC_RSR_CF (0x02u) +#define RTC_RSR_CF_SHIFT (1u) +#define RTC_RSR_PF (0x04u) +#define RTC_RSR_PF_SHIFT (2u) +#define RTC_RCR1_AIE (0x01u) +#define RTC_RCR1_AIE_SHIFT (0u) +#define RTC_RCR1_CIE (0x02u) +#define RTC_RCR1_CIE_SHIFT (1u) +#define RTC_RCR1_PIE (0x04u) +#define RTC_RCR1_PIE_SHIFT (2u) +#define RTC_RCR1_PES (0xF0u) +#define RTC_RCR1_PES_SHIFT (4u) +#define RTC_RCR2_START (0x01u) +#define RTC_RCR2_START_SHIFT (0u) +#define RTC_RCR2_RESET (0x02u) +#define RTC_RCR2_RESET_SHIFT (1u) +#define RTC_RCR2_ADJ30 (0x04u) +#define RTC_RCR2_ADJ30_SHIFT (2u) +#define RTC_RCR2_AADJE (0x10u) +#define RTC_RCR2_AADJE_SHIFT (4u) +#define RTC_RCR2_AADJP (0x20u) +#define RTC_RCR2_AADJP_SHIFT (5u) +#define RTC_RCR2_HR24 (0x40u) +#define RTC_RCR2_HR24_SHIFT (6u) +#define RTC_RCR2_CNTMD (0x80u) +#define RTC_RCR2_CNTMD_SHIFT (7u) +#define RTC_RCR3_RTCEN (0x01u) +#define RTC_RCR3_RTCEN_SHIFT (0u) +#define RTC_RCR4_RCKSEL (0x01u) +#define RTC_RCR4_RCKSEL_SHIFT (0u) +#define RTC_RFRH_RFC (0x0001u) +#define RTC_RFRH_RFC_SHIFT (0u) +#define RTC_RFRL_RFC (0xFFFFu) +#define RTC_RFRL_RFC_SHIFT (0u) +#define RTC_RADJ_ADJ (0x3Fu) +#define RTC_RADJ_ADJ_SHIFT (0u) +#define RTC_RADJ_PMADJ (0xC0u) +#define RTC_RADJ_PMADJ_SHIFT (6u) +#define RTC_BCNT0_BCNT (0xFFu) +#define RTC_BCNT0_BCNT_SHIFT (0u) +#define RTC_BCNT1_BCNT (0x00u) +#define RTC_BCNT1_BCNT_SHIFT (0u) +#define RTC_BCNT2_BCNT (0x00u) +#define RTC_BCNT2_BCNT_SHIFT (0u) +#define RTC_BCNT3_BCNT (0x00u) +#define RTC_BCNT3_BCNT_SHIFT (0u) +#define RTC_BCNT0AR_BCNTAR (0xFFu) +#define RTC_BCNT0AR_BCNTAR_SHIFT (0u) +#define RTC_BCNT1AR_BCNTAR (0x00u) +#define RTC_BCNT1AR_BCNTAR_SHIFT (0u) +#define RTC_BCNT2AR_BCNTAR (0x00u) +#define RTC_BCNT2AR_BCNTAR_SHIFT (0u) +#define RTC_BCNT3AR_BCNTAR (0x00u) +#define RTC_BCNT3AR_BCNTAR_SHIFT (0u) +#define RTC_BCNT0AER_ENB (0xFFu) +#define RTC_BCNT0AER_ENB_SHIFT (0u) +#define RTC_BCNT1AER_ENB (0x00u) +#define RTC_BCNT1AER_ENB_SHIFT (0u) +#define RTC_BCNT2AER_ENB (0x0000u) +#define RTC_BCNT2AER_ENB_SHIFT (0u) +#define RTC_BCNT3AER_ENB (0x00u) +#define RTC_BCNT3AER_ENB_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scifa_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scifa_iobitmask.h new file mode 100644 index 0000000..ba1f7b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scifa_iobitmask.h @@ -0,0 +1,160 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef SCIFA_IOBITMASK_H +#define SCIFA_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define SCIFA_SMR_CKS (0x0003u) +#define SCIFA_SMR_CKS_SHIFT (0u) +#define SCIFA_SMR_STOP (0x0008u) +#define SCIFA_SMR_STOP_SHIFT (3u) +#define SCIFA_SMR_PM (0x0010u) +#define SCIFA_SMR_PM_SHIFT (4u) +#define SCIFA_SMR_PE (0x0020u) +#define SCIFA_SMR_PE_SHIFT (5u) +#define SCIFA_SMR_CHR (0x0040u) +#define SCIFA_SMR_CHR_SHIFT (6u) +#define SCIFA_SMR_CM (0x0080u) +#define SCIFA_SMR_CM_SHIFT (7u) +#define SCIFA_MDDR_MDDR (0xFFu) +#define SCIFA_MDDR_MDDR_SHIFT (0u) +#define SCIFA_BRR_BRR (0xFFu) +#define SCIFA_BRR_BRR_SHIFT (0u) +#define SCIFA_SCR_CKE (0x0003u) +#define SCIFA_SCR_CKE_SHIFT (0u) +#define SCIFA_SCR_TEIE (0x0004u) +#define SCIFA_SCR_TEIE_SHIFT (2u) +#define SCIFA_SCR_REIE (0x0008u) +#define SCIFA_SCR_REIE_SHIFT (3u) +#define SCIFA_SCR_RE (0x0010u) +#define SCIFA_SCR_RE_SHIFT (4u) +#define SCIFA_SCR_TE (0x0020u) +#define SCIFA_SCR_TE_SHIFT (5u) +#define SCIFA_SCR_RIE (0x0040u) +#define SCIFA_SCR_RIE_SHIFT (6u) +#define SCIFA_SCR_TIE (0x0080u) +#define SCIFA_SCR_TIE_SHIFT (7u) +#define SCIFA_FTDR_FTDR (0xFFu) +#define SCIFA_FTDR_FTDR_SHIFT (0u) +#define SCIFA_FSR_DR (0x0001u) +#define SCIFA_FSR_DR_SHIFT (0u) +#define SCIFA_FSR_RDF (0x0002u) +#define SCIFA_FSR_RDF_SHIFT (1u) +#define SCIFA_FSR_PER (0x0004u) +#define SCIFA_FSR_PER_SHIFT (2u) +#define SCIFA_FSR_FER (0x0008u) +#define SCIFA_FSR_FER_SHIFT (3u) +#define SCIFA_FSR_BRK (0x0010u) +#define SCIFA_FSR_BRK_SHIFT (4u) +#define SCIFA_FSR_TDFE (0x0020u) +#define SCIFA_FSR_TDFE_SHIFT (5u) +#define SCIFA_FSR_TEND (0x0040u) +#define SCIFA_FSR_TEND_SHIFT (6u) +#define SCIFA_FSR_ER (0x0080u) +#define SCIFA_FSR_ER_SHIFT (7u) +#define SCIFA_FRDR_FRDR (0xFFu) +#define SCIFA_FRDR_FRDR_SHIFT (0u) +#define SCIFA_FCR_LOOP (0x0001u) +#define SCIFA_FCR_LOOP_SHIFT (0u) +#define SCIFA_FCR_RFRST (0x0002u) +#define SCIFA_FCR_RFRST_SHIFT (1u) +#define SCIFA_FCR_TFRST (0x0004u) +#define SCIFA_FCR_TFRST_SHIFT (2u) +#define SCIFA_FCR_MCE (0x0008u) +#define SCIFA_FCR_MCE_SHIFT (3u) +#define SCIFA_FCR_TTRG (0x0030u) +#define SCIFA_FCR_TTRG_SHIFT (4u) +#define SCIFA_FCR_RTRG (0x00C0u) +#define SCIFA_FCR_RTRG_SHIFT (6u) +#define SCIFA_FCR_RSTRG (0x0700u) +#define SCIFA_FCR_RSTRG_SHIFT (8u) +#define SCIFA_FDR_R (0x001Fu) +#define SCIFA_FDR_R_SHIFT (0u) +#define SCIFA_FDR_T (0x1F00u) +#define SCIFA_FDR_T_SHIFT (8u) +#define SCIFA_SPTR_SPB2DT (0x0001u) +#define SCIFA_SPTR_SPB2DT_SHIFT (0u) +#define SCIFA_SPTR_SPB2IO (0x0002u) +#define SCIFA_SPTR_SPB2IO_SHIFT (1u) +#define SCIFA_SPTR_SCKDT (0x0004u) +#define SCIFA_SPTR_SCKDT_SHIFT (2u) +#define SCIFA_SPTR_SCKIO (0x0008u) +#define SCIFA_SPTR_SCKIO_SHIFT (3u) +#define SCIFA_SPTR_CTS2DT (0x0010u) +#define SCIFA_SPTR_CTS2DT_SHIFT (4u) +#define SCIFA_SPTR_CTS2IO (0x0020u) +#define SCIFA_SPTR_CTS2IO_SHIFT (5u) +#define SCIFA_SPTR_RTS2DT (0x0040u) +#define SCIFA_SPTR_RTS2DT_SHIFT (6u) +#define SCIFA_SPTR_RTS2IO (0x0080u) +#define SCIFA_SPTR_RTS2IO_SHIFT (7u) +#define SCIFA_LSR_ORER (0x0001u) +#define SCIFA_LSR_ORER_SHIFT (0u) +#define SCIFA_LSR_FER (0x003Cu) +#define SCIFA_LSR_FER_SHIFT (2u) +#define SCIFA_LSR_PER (0x0F00u) +#define SCIFA_LSR_PER_SHIFT (8u) +#define SCIFA_SEMR_ABCS0 (0x01u) +#define SCIFA_SEMR_ABCS0_SHIFT (0u) +#define SCIFA_SEMR_NFEN (0x04u) +#define SCIFA_SEMR_NFEN_SHIFT (2u) +#define SCIFA_SEMR_DIR (0x08u) +#define SCIFA_SEMR_DIR_SHIFT (3u) +#define SCIFA_SEMR_MDDRS (0x10u) +#define SCIFA_SEMR_MDDRS_SHIFT (4u) +#define SCIFA_SEMR_BRME (0x20u) +#define SCIFA_SEMR_BRME_SHIFT (5u) +#define SCIFA_SEMR_BGDM (0x80u) +#define SCIFA_SEMR_BGDM_SHIFT (7u) +#define SCIFA_FTCR_TFTC (0x001Fu) +#define SCIFA_FTCR_TFTC_SHIFT (0u) +#define SCIFA_FTCR_TTRGS (0x0080u) +#define SCIFA_FTCR_TTRGS_SHIFT (7u) +#define SCIFA_FTCR_RFTC (0x1F00u) +#define SCIFA_FTCR_RFTC_SHIFT (8u) +#define SCIFA_FTCR_RTRGS (0x8000u) +#define SCIFA_FTCR_RTRGS_SHIFT (15u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scim_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scim_iobitmask.h new file mode 100644 index 0000000..4189914 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/scim_iobitmask.h @@ -0,0 +1,140 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef SCIM_IOBITMASK_H +#define SCIM_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define SCIM_SMR_CKS (0x03u) +#define SCIM_SMR_CKS_SHIFT (0u) +#define SCIM_SMR_MP (0x04u) +#define SCIM_SMR_MP_SHIFT (2u) +#define SCIM_SMR_STOP (0x08u) +#define SCIM_SMR_STOP_SHIFT (3u) +#define SCIM_SMR_PM (0x10u) +#define SCIM_SMR_PM_SHIFT (4u) +#define SCIM_SMR_PE (0x20u) +#define SCIM_SMR_PE_SHIFT (5u) +#define SCIM_SMR_CHR (0x40u) +#define SCIM_SMR_CHR_SHIFT (6u) +#define SCIM_SMR_CM (0x80u) +#define SCIM_SMR_CM_SHIFT (7u) +#define SCIM_BRR_BRR (0xFFu) +#define SCIM_BRR_BRR_SHIFT (0u) +#define SCIM_SCR_CKE (0x03u) +#define SCIM_SCR_CKE_SHIFT (0u) +#define SCIM_SCR_TEIE (0x04u) +#define SCIM_SCR_TEIE_SHIFT (2u) +#define SCIM_SCR_MPIE (0x08u) +#define SCIM_SCR_MPIE_SHIFT (3u) +#define SCIM_SCR_RE (0x10u) +#define SCIM_SCR_RE_SHIFT (4u) +#define SCIM_SCR_TE (0x20u) +#define SCIM_SCR_TE_SHIFT (5u) +#define SCIM_SCR_RIE (0x40u) +#define SCIM_SCR_RIE_SHIFT (6u) +#define SCIM_SCR_TIE (0x80u) +#define SCIM_SCR_TIE_SHIFT (7u) +#define SCIM_TDR_TDR (0xFFu) +#define SCIM_TDR_TDR_SHIFT (0u) +#define SCIM_SSR_MPBT (0x01u) +#define SCIM_SSR_MPBT_SHIFT (0u) +#define SCIM_SSR_MPB (0x02u) +#define SCIM_SSR_MPB_SHIFT (1u) +#define SCIM_SSR_TEND (0x04u) +#define SCIM_SSR_TEND_SHIFT (2u) +#define SCIM_SSR_PER (0x08u) +#define SCIM_SSR_PER_SHIFT (3u) +#define SCIM_SSR_FER (0x10u) +#define SCIM_SSR_FER_SHIFT (4u) +#define SCIM_SSR_ORER (0x20u) +#define SCIM_SSR_ORER_SHIFT (5u) +#define SCIM_SSR_RDRF (0x40u) +#define SCIM_SSR_RDRF_SHIFT (6u) +#define SCIM_SSR_TDRE (0x80u) +#define SCIM_SSR_TDRE_SHIFT (7u) +#define SCIM_RDR_RDR (0xFFu) +#define SCIM_RDR_RDR_SHIFT (0u) +#define SCIM_SCMR_SMIF (0x01u) +#define SCIM_SCMR_SMIF_SHIFT (0u) +#define SCIM_SCMR_SINV (0x04u) +#define SCIM_SCMR_SINV_SHIFT (2u) +#define SCIM_SCMR_SDIR (0x08u) +#define SCIM_SCMR_SDIR_SHIFT (3u) +#define SCIM_SCMR_CHR1 (0x10u) +#define SCIM_SCMR_CHR1_SHIFT (4u) +#define SCIM_SCMR_BCP2 (0x80u) +#define SCIM_SCMR_BCP2_SHIFT (7u) +#define SCIM_SEMR_ACS0 (0x01u) +#define SCIM_SEMR_ACS0_SHIFT (0u) +#define SCIM_SEMR_BRME (0x04u) +#define SCIM_SEMR_BRME_SHIFT (2u) +#define SCIM_SEMR_ABCS (0x10u) +#define SCIM_SEMR_ABCS_SHIFT (4u) +#define SCIM_SEMR_NFEN (0x20u) +#define SCIM_SEMR_NFEN_SHIFT (5u) +#define SCIM_SEMR_BGDM (0x40u) +#define SCIM_SEMR_BGDM_SHIFT (6u) +#define SCIM_SEMR_RXDESEL (0x80u) +#define SCIM_SEMR_RXDESEL_SHIFT (7u) +#define SCIM_SNFR_NFCS (0x07u) +#define SCIM_SNFR_NFCS_SHIFT (0u) +#define SCIM_SECR_CTSE (0x02u) +#define SCIM_SECR_CTSE_SHIFT (1u) +#define SCIM_TDRHL_TDRHL (0xFFFFu) +#define SCIM_TDRHL_TDRHL_SHIFT (0u) +#define SCIM_TDRH_TDRH (0xFFu) +#define SCIM_TDRH_TDRH_SHIFT (0u) +#define SCIM_TDRL_TDRL (0xFFu) +#define SCIM_TDRL_TDRL_SHIFT (0u) +#define SCIM_RDRHL_RDRHL (0xFFFFu) +#define SCIM_RDRHL_RDRHL_SHIFT (0u) +#define SCIM_RDRH_RDRH (0xFFu) +#define SCIM_RDRH_RDRH_SHIFT (0u) +#define SCIM_RDRL_RDRL (0xFFu) +#define SCIM_RDRL_RDRL_SHIFT (0u) +#define SCIM_MDDR_MDDR (0xFFu) +#define SCIM_MDDR_MDDR_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sdmmc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sdmmc_iobitmask.h new file mode 100644 index 0000000..70cf4c0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sdmmc_iobitmask.h @@ -0,0 +1,362 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef SDMMC_IOBITMASK_H +#define SDMMC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define SDMMC_SCC_DTCNTL_TAPEN (0x00000001u) +#define SDMMC_SCC_DTCNTL_TAPEN_SHIFT (0u) +#define SDMMC_SCC_DTCNTL_TAPNUM (0x00000000u) +#define SDMMC_SCC_DTCNTL_TAPNUM_SHIFT (16u) +#define SDMMC_SCC_TAPSET_TAPSET (0x000000FFu) +#define SDMMC_SCC_TAPSET_TAPSET_SHIFT (0u) +#define SDMMC_SCC_DT2FF_DT2NSSET (0x000000FFu) +#define SDMMC_SCC_DT2FF_DT2NSSET_SHIFT (0u) +#define SDMMC_SCC_DT2FF_DT2NESET (0x0000FF00u) +#define SDMMC_SCC_DT2FF_DT2NESET_SHIFT (8u) +#define SDMMC_SCC_CKSEL_DTSEL (0x00000001u) +#define SDMMC_SCC_CKSEL_DTSEL_SHIFT (0u) +#define SDMMC_SCC_RVSCNTL_RVSEN (0x00000001u) +#define SDMMC_SCC_RVSCNTL_RVSEN_SHIFT (0u) +#define SDMMC_SCC_RVSCNTL_RVSW (0x00000002u) +#define SDMMC_SCC_RVSCNTL_RVSW_SHIFT (1u) +#define SDMMC_SCC_RVSCNTL_TAPSEL (0x0000FF00u) +#define SDMMC_SCC_RVSCNTL_TAPSEL_SHIFT (8u) +#define SDMMC_SCC_RVSREQ_REQTAPDWN (0x00000001u) +#define SDMMC_SCC_RVSREQ_REQTAPDWN_SHIFT (0u) +#define SDMMC_SCC_RVSREQ_REQTAPUP (0x00000002u) +#define SDMMC_SCC_RVSREQ_REQTAPUP_SHIFT (1u) +#define SDMMC_SCC_RVSREQ_RVSERR (0x00000004u) +#define SDMMC_SCC_RVSREQ_RVSERR_SHIFT (2u) +#define SDMMC_SCC_SMPCMP_CMPNGD (0x000001FFu) +#define SDMMC_SCC_SMPCMP_CMPNGD_SHIFT (0u) +#define SDMMC_SCC_SMPCMP_CMPNGU (0x01FF0000u) +#define SDMMC_SCC_SMPCMP_CMPNGU_SHIFT (16u) +#define SDMMC_SD_CMD_CF (0x0000000000000000u) +#define SDMMC_SD_CMD_CF_SHIFT (0u) +#define SDMMC_SD_CMD_C0 (0x0000000000000040u) +#define SDMMC_SD_CMD_C0_SHIFT (6u) +#define SDMMC_SD_CMD_C1 (0x0000000000000080u) +#define SDMMC_SD_CMD_C1_SHIFT (7u) +#define SDMMC_SD_CMD_MD0 (0x0000000000000100u) +#define SDMMC_SD_CMD_MD0_SHIFT (8u) +#define SDMMC_SD_CMD_MD1 (0x0000000000000200u) +#define SDMMC_SD_CMD_MD1_SHIFT (9u) +#define SDMMC_SD_CMD_MD2 (0x0000000000000400u) +#define SDMMC_SD_CMD_MD2_SHIFT (10u) +#define SDMMC_SD_CMD_MD3 (0x0000000000000800u) +#define SDMMC_SD_CMD_MD3_SHIFT (11u) +#define SDMMC_SD_CMD_MD4 (0x0000000000001000u) +#define SDMMC_SD_CMD_MD4_SHIFT (12u) +#define SDMMC_SD_CMD_MD5 (0x0000000000002000u) +#define SDMMC_SD_CMD_MD5_SHIFT (13u) +#define SDMMC_SD_CMD_MD6 (0x0000000000004000u) +#define SDMMC_SD_CMD_MD6_SHIFT (14u) +#define SDMMC_SD_CMD_MD7 (0x0000000000008000u) +#define SDMMC_SD_CMD_MD7_SHIFT (15u) +#define SDMMC_SD_ARG_CF (0x00000000FFFFFF00u) +#define SDMMC_SD_ARG_CF_SHIFT (0u) +#define SDMMC_SD_ARG1_CF (0x0000000000000000u) +#define SDMMC_SD_ARG1_CF_SHIFT (0u) +#define SDMMC_SD_STOP_STP (0x0000000000000001u) +#define SDMMC_SD_STOP_STP_SHIFT (0u) +#define SDMMC_SD_STOP_SEC (0x0000000000000100u) +#define SDMMC_SD_STOP_SEC_SHIFT (8u) +#define SDMMC_SD_STOP_HPICMD (0x0000000000010000u) +#define SDMMC_SD_STOP_HPICMD_SHIFT (16u) +#define SDMMC_SD_STOP_HPIMODE (0x0000000000020000u) +#define SDMMC_SD_STOP_HPIMODE_SHIFT (17u) +#define SDMMC_SD_SECCNT_CNT (0x00000000FFFFFFFFu) +#define SDMMC_SD_SECCNT_CNT_SHIFT (0u) +#define SDMMC_SD_RSP10_R (0xFFFFFFFFFFFFFF00u) +#define SDMMC_SD_RSP10_R_SHIFT (0u) +#define SDMMC_SD_RSP1_R (0x0000000000000000u) +#define SDMMC_SD_RSP1_R_SHIFT (0u) +#define SDMMC_SD_RSP32_R (0x0000000000000000u) +#define SDMMC_SD_RSP32_R_SHIFT (0u) +#define SDMMC_SD_RSP3_R (0x0000000000000000u) +#define SDMMC_SD_RSP3_R_SHIFT (0u) +#define SDMMC_SD_RSP54_R (0x0000000000000000u) +#define SDMMC_SD_RSP54_R_SHIFT (0u) +#define SDMMC_SD_RSP5_R (0x0000000000000000u) +#define SDMMC_SD_RSP5_R_SHIFT (0u) +#define SDMMC_SD_RSP76_R (0x0000000000000000u) +#define SDMMC_SD_RSP76_R_SHIFT (0u) +#define SDMMC_SD_RSP7_R (0x0000000000000000u) +#define SDMMC_SD_RSP7_R_SHIFT (0u) +#define SDMMC_SD_INFO1_INFO0 (0x0000000000000001u) +#define SDMMC_SD_INFO1_INFO0_SHIFT (0u) +#define SDMMC_SD_INFO1_INFO2 (0x0000000000000004u) +#define SDMMC_SD_INFO1_INFO2_SHIFT (2u) +#define SDMMC_SD_INFO1_INFO3 (0x0000000000000008u) +#define SDMMC_SD_INFO1_INFO3_SHIFT (3u) +#define SDMMC_SD_INFO1_INFO4 (0x0000000000000010u) +#define SDMMC_SD_INFO1_INFO4_SHIFT (4u) +#define SDMMC_SD_INFO1_INFO5 (0x0000000000000020u) +#define SDMMC_SD_INFO1_INFO5_SHIFT (5u) +#define SDMMC_SD_INFO1_INFO7 (0x0000000000000080u) +#define SDMMC_SD_INFO1_INFO7_SHIFT (7u) +#define SDMMC_SD_INFO1_INFO8 (0x0000000000000100u) +#define SDMMC_SD_INFO1_INFO8_SHIFT (8u) +#define SDMMC_SD_INFO1_INFO9 (0x0000000000000200u) +#define SDMMC_SD_INFO1_INFO9_SHIFT (9u) +#define SDMMC_SD_INFO1_INFO10 (0x0000000000000400u) +#define SDMMC_SD_INFO1_INFO10_SHIFT (10u) +#define SDMMC_SD_INFO1_HPIRES (0x0000000000010000u) +#define SDMMC_SD_INFO1_HPIRES_SHIFT (16u) +#define SDMMC_SD_INFO2_ERR0 (0x0000000000000001u) +#define SDMMC_SD_INFO2_ERR0_SHIFT (0u) +#define SDMMC_SD_INFO2_ERR1 (0x0000000000000002u) +#define SDMMC_SD_INFO2_ERR1_SHIFT (1u) +#define SDMMC_SD_INFO2_ERR2 (0x0000000000000004u) +#define SDMMC_SD_INFO2_ERR2_SHIFT (2u) +#define SDMMC_SD_INFO2_ERR3 (0x0000000000000008u) +#define SDMMC_SD_INFO2_ERR3_SHIFT (3u) +#define SDMMC_SD_INFO2_ERR4 (0x0000000000000010u) +#define SDMMC_SD_INFO2_ERR4_SHIFT (4u) +#define SDMMC_SD_INFO2_ERR5 (0x0000000000000020u) +#define SDMMC_SD_INFO2_ERR5_SHIFT (5u) +#define SDMMC_SD_INFO2_ERR6 (0x0000000000000040u) +#define SDMMC_SD_INFO2_ERR6_SHIFT (6u) +#define SDMMC_SD_INFO2_DAT0 (0x0000000000000080u) +#define SDMMC_SD_INFO2_DAT0_SHIFT (7u) +#define SDMMC_SD_INFO2_BRE (0x0000000000000100u) +#define SDMMC_SD_INFO2_BRE_SHIFT (8u) +#define SDMMC_SD_INFO2_BWE (0x0000000000000200u) +#define SDMMC_SD_INFO2_BWE_SHIFT (9u) +#define SDMMC_SD_INFO2_SCLKDIVEN (0x0000000000002000u) +#define SDMMC_SD_INFO2_SCLKDIVEN_SHIFT (13u) +#define SDMMC_SD_INFO2_CBSY (0x0000000000004000u) +#define SDMMC_SD_INFO2_CBSY_SHIFT (14u) +#define SDMMC_SD_INFO2_ILA (0x0000000000008000u) +#define SDMMC_SD_INFO2_ILA_SHIFT (15u) +#define SDMMC_SD_INFO1_MASK_IMASK0 (0x0000000000000001u) +#define SDMMC_SD_INFO1_MASK_IMASK0_SHIFT (0u) +#define SDMMC_SD_INFO1_MASK_IMASK2 (0x0000000000000004u) +#define SDMMC_SD_INFO1_MASK_IMASK2_SHIFT (2u) +#define SDMMC_SD_INFO1_MASK_IMASK3 (0x0000000000000008u) +#define SDMMC_SD_INFO1_MASK_IMASK3_SHIFT (3u) +#define SDMMC_SD_INFO1_MASK_IMASK4 (0x0000000000000010u) +#define SDMMC_SD_INFO1_MASK_IMASK4_SHIFT (4u) +#define SDMMC_SD_INFO1_MASK_IMASK8 (0x0000000000000100u) +#define SDMMC_SD_INFO1_MASK_IMASK8_SHIFT (8u) +#define SDMMC_SD_INFO1_MASK_IMASK9 (0x0000000000000200u) +#define SDMMC_SD_INFO1_MASK_IMASK9_SHIFT (9u) +#define SDMMC_SD_INFO1_MASK_IMASK16 (0x0000000000010000u) +#define SDMMC_SD_INFO1_MASK_IMASK16_SHIFT (16u) +#define SDMMC_SD_INFO2_MASK_EMASK0 (0x0000000000000001u) +#define SDMMC_SD_INFO2_MASK_EMASK0_SHIFT (0u) +#define SDMMC_SD_INFO2_MASK_EMASK1 (0x0000000000000002u) +#define SDMMC_SD_INFO2_MASK_EMASK1_SHIFT (1u) +#define SDMMC_SD_INFO2_MASK_EMASK2 (0x0000000000000004u) +#define SDMMC_SD_INFO2_MASK_EMASK2_SHIFT (2u) +#define SDMMC_SD_INFO2_MASK_EMASK3 (0x0000000000000008u) +#define SDMMC_SD_INFO2_MASK_EMASK3_SHIFT (3u) +#define SDMMC_SD_INFO2_MASK_EMASK4 (0x0000000000000010u) +#define SDMMC_SD_INFO2_MASK_EMASK4_SHIFT (4u) +#define SDMMC_SD_INFO2_MASK_EMASK5 (0x0000000000000020u) +#define SDMMC_SD_INFO2_MASK_EMASK5_SHIFT (5u) +#define SDMMC_SD_INFO2_MASK_EMASK6 (0x0000000000000040u) +#define SDMMC_SD_INFO2_MASK_EMASK6_SHIFT (6u) +#define SDMMC_SD_INFO2_MASK_BMASK0 (0x0000000000000100u) +#define SDMMC_SD_INFO2_MASK_BMASK0_SHIFT (8u) +#define SDMMC_SD_INFO2_MASK_BMASK1 (0x0000000000000200u) +#define SDMMC_SD_INFO2_MASK_BMASK1_SHIFT (9u) +#define SDMMC_SD_INFO2_MASK_IMASK (0x0000000000008000u) +#define SDMMC_SD_INFO2_MASK_IMASK_SHIFT (15u) +#define SDMMC_SD_CLK_CTRL_DIV (0x00000000000000FFu) +#define SDMMC_SD_CLK_CTRL_DIV_SHIFT (0u) +#define SDMMC_SD_CLK_CTRL_SCLKEN (0x0000000000000100u) +#define SDMMC_SD_CLK_CTRL_SCLKEN_SHIFT (8u) +#define SDMMC_SD_CLK_CTRL_SDCLKOFFEN (0x0000000000000200u) +#define SDMMC_SD_CLK_CTRL_SDCLKOFFEN_SHIFT (9u) +#define SDMMC_SD_SIZE_LEN (0x00000000000003FFu) +#define SDMMC_SD_SIZE_LEN_SHIFT (0u) +#define SDMMC_SD_OPTION_CTOP21 (0x0000000000000001u) +#define SDMMC_SD_OPTION_CTOP21_SHIFT (0u) +#define SDMMC_SD_OPTION_CTOP22 (0x0000000000000002u) +#define SDMMC_SD_OPTION_CTOP22_SHIFT (1u) +#define SDMMC_SD_OPTION_CTOP23 (0x0000000000000004u) +#define SDMMC_SD_OPTION_CTOP23_SHIFT (2u) +#define SDMMC_SD_OPTION_CTOP24 (0x0000000000000008u) +#define SDMMC_SD_OPTION_CTOP24_SHIFT (3u) +#define SDMMC_SD_OPTION_TOP24 (0x0000000000000010u) +#define SDMMC_SD_OPTION_TOP24_SHIFT (4u) +#define SDMMC_SD_OPTION_TOP25 (0x0000000000000020u) +#define SDMMC_SD_OPTION_TOP25_SHIFT (5u) +#define SDMMC_SD_OPTION_TOP26 (0x0000000000000040u) +#define SDMMC_SD_OPTION_TOP26_SHIFT (6u) +#define SDMMC_SD_OPTION_TOP27 (0x0000000000000080u) +#define SDMMC_SD_OPTION_TOP27_SHIFT (7u) +#define SDMMC_SD_OPTION_TOUTMASK (0x0000000000000100u) +#define SDMMC_SD_OPTION_TOUTMASK_SHIFT (8u) +#define SDMMC_SD_OPTION_EXTOP (0x0000000000000200u) +#define SDMMC_SD_OPTION_EXTOP_SHIFT (9u) +#define SDMMC_SD_OPTION_WIDTH8 (0x0000000000002000u) +#define SDMMC_SD_OPTION_WIDTH8_SHIFT (13u) +#define SDMMC_SD_OPTION_WIDTH (0x0000000000008000u) +#define SDMMC_SD_OPTION_WIDTH_SHIFT (15u) +#define SDMMC_SD_ERR_STS1_E0 (0x0000000000000001u) +#define SDMMC_SD_ERR_STS1_E0_SHIFT (0u) +#define SDMMC_SD_ERR_STS1_E1 (0x0000000000000002u) +#define SDMMC_SD_ERR_STS1_E1_SHIFT (1u) +#define SDMMC_SD_ERR_STS1_E2 (0x0000000000000004u) +#define SDMMC_SD_ERR_STS1_E2_SHIFT (2u) +#define SDMMC_SD_ERR_STS1_E3 (0x0000000000000008u) +#define SDMMC_SD_ERR_STS1_E3_SHIFT (3u) +#define SDMMC_SD_ERR_STS1_E4 (0x0000000000000010u) +#define SDMMC_SD_ERR_STS1_E4_SHIFT (4u) +#define SDMMC_SD_ERR_STS1_E5 (0x0000000000000020u) +#define SDMMC_SD_ERR_STS1_E5_SHIFT (5u) +#define SDMMC_SD_ERR_STS1_E8 (0x0000000000000100u) +#define SDMMC_SD_ERR_STS1_E8_SHIFT (8u) +#define SDMMC_SD_ERR_STS1_E9 (0x0000000000000200u) +#define SDMMC_SD_ERR_STS1_E9_SHIFT (9u) +#define SDMMC_SD_ERR_STS1_E10 (0x0000000000000400u) +#define SDMMC_SD_ERR_STS1_E10_SHIFT (10u) +#define SDMMC_SD_ERR_STS1_E11 (0x0000000000000800u) +#define SDMMC_SD_ERR_STS1_E11_SHIFT (11u) +#define SDMMC_SD_ERR_STS1_E12 (0x0000000000001000u) +#define SDMMC_SD_ERR_STS1_E12_SHIFT (12u) +#define SDMMC_SD_ERR_STS1_E13 (0x0000000000002000u) +#define SDMMC_SD_ERR_STS1_E13_SHIFT (13u) +#define SDMMC_SD_ERR_STS1_E14 (0x0000000000004000u) +#define SDMMC_SD_ERR_STS1_E14_SHIFT (14u) +#define SDMMC_SD_ERR_STS2_E0 (0x0000000000000001u) +#define SDMMC_SD_ERR_STS2_E0_SHIFT (0u) +#define SDMMC_SD_ERR_STS2_E1 (0x0000000000000002u) +#define SDMMC_SD_ERR_STS2_E1_SHIFT (1u) +#define SDMMC_SD_ERR_STS2_E2 (0x0000000000000004u) +#define SDMMC_SD_ERR_STS2_E2_SHIFT (2u) +#define SDMMC_SD_ERR_STS2_E3 (0x0000000000000008u) +#define SDMMC_SD_ERR_STS2_E3_SHIFT (3u) +#define SDMMC_SD_ERR_STS2_E4 (0x0000000000000010u) +#define SDMMC_SD_ERR_STS2_E4_SHIFT (4u) +#define SDMMC_SD_ERR_STS2_E5 (0x0000000000000020u) +#define SDMMC_SD_ERR_STS2_E5_SHIFT (5u) +#define SDMMC_SD_ERR_STS2_E6 (0x0000000000000040u) +#define SDMMC_SD_ERR_STS2_E6_SHIFT (6u) +#define SDMMC_SD_BUF0_BUF (0xFFFFFFFFFFFFFFFFu) +#define SDMMC_SD_BUF0_BUF_SHIFT (0u) +#define SDMMC_SDIO_MODE_IOMOD (0x0000000000000001u) +#define SDMMC_SDIO_MODE_IOMOD_SHIFT (0u) +#define SDMMC_SDIO_MODE_RWREQ (0x0000000000000004u) +#define SDMMC_SDIO_MODE_RWREQ_SHIFT (2u) +#define SDMMC_SDIO_MODE_IOABT (0x0000000000000100u) +#define SDMMC_SDIO_MODE_IOABT_SHIFT (8u) +#define SDMMC_SDIO_MODE_C52PUB (0x0000000000000200u) +#define SDMMC_SDIO_MODE_C52PUB_SHIFT (9u) +#define SDMMC_SDIO_INFO1_IOIRQ (0x0000000000000001u) +#define SDMMC_SDIO_INFO1_IOIRQ_SHIFT (0u) +#define SDMMC_SDIO_INFO1_EXPUB52 (0x0000000000004000u) +#define SDMMC_SDIO_INFO1_EXPUB52_SHIFT (14u) +#define SDMMC_SDIO_INFO1_EXWT (0x0000000000008000u) +#define SDMMC_SDIO_INFO1_EXWT_SHIFT (15u) +#define SDMMC_SDIO_INFO1_MASK_IOMSK (0x0000000000000001u) +#define SDMMC_SDIO_INFO1_MASK_IOMSK_SHIFT (0u) +#define SDMMC_SDIO_INFO1_MASK_MEXPUB52 (0x0000000000004000u) +#define SDMMC_SDIO_INFO1_MASK_MEXPUB52_SHIFT (14u) +#define SDMMC_SDIO_INFO1_MASK_MEXWT (0x0000000000008000u) +#define SDMMC_SDIO_INFO1_MASK_MEXWT_SHIFT (15u) +#define SDMMC_CC_EXT_MODE_DMASDRW (0x0000000000000002u) +#define SDMMC_CC_EXT_MODE_DMASDRW_SHIFT (1u) +#define SDMMC_SOFT_RST_SDRST (0x0000000000000001u) +#define SDMMC_SOFT_RST_SDRST_SHIFT (0u) +#define SDMMC_VERSION_IP (0x00000000000000FFu) +#define SDMMC_VERSION_IP_SHIFT (0u) +#define SDMMC_VERSION_UR (0x000000000000FF00u) +#define SDMMC_VERSION_UR_SHIFT (8u) +#define SDMMC_HOST_MODE_WMODE (0x0000000000000001u) +#define SDMMC_HOST_MODE_WMODE_SHIFT (0u) +#define SDMMC_HOST_MODE_ENDIAN (0x0000000000000002u) +#define SDMMC_HOST_MODE_ENDIAN_SHIFT (1u) +#define SDMMC_HOST_MODE_BUSWIDTH (0x0000000000000100u) +#define SDMMC_HOST_MODE_BUSWIDTH_SHIFT (8u) +#define SDMMC_SDIF_MODE_DDR (0x0000000000000001u) +#define SDMMC_SDIF_MODE_DDR_SHIFT (0u) +#define SDMMC_SDIF_MODE_NOCHKCR (0x0000000000000100u) +#define SDMMC_SDIF_MODE_NOCHKCR_SHIFT (8u) +#define SDMMC_SD_STATUS_SD_RST (0x0000000000000002u) +#define SDMMC_SD_STATUS_SD_RST_SHIFT (1u) +#define SDMMC_DM_CM_DTRAN_MODE_BUS_WIDTH (0x0000000000000030u) +#define SDMMC_DM_CM_DTRAN_MODE_BUS_WIDTH_SHIFT (4u) +#define SDMMC_DM_CM_DTRAN_MODE_CH_NUM (0x0000000000030000u) +#define SDMMC_DM_CM_DTRAN_MODE_CH_NUM_SHIFT (16u) +#define SDMMC_DM_CM_DTRAN_CTRL_DM_START (0x0000000000000001u) +#define SDMMC_DM_CM_DTRAN_CTRL_DM_START_SHIFT (0u) +#define SDMMC_DM_CM_RST_SEQRST (0x0000000000000001u) +#define SDMMC_DM_CM_RST_SEQRST_SHIFT (0u) +#define SDMMC_DM_CM_RST_DTRANRST0 (0x0000000000000100u) +#define SDMMC_DM_CM_RST_DTRANRST0_SHIFT (8u) +#define SDMMC_DM_CM_RST_DTRANRST1 (0x0000000000000200u) +#define SDMMC_DM_CM_RST_DTRANRST1_SHIFT (9u) +#define SDMMC_DM_CM_INFO1_SEQEND (0x0000000000000001u) +#define SDMMC_DM_CM_INFO1_SEQEND_SHIFT (0u) +#define SDMMC_DM_CM_INFO1_DTRANEND0 (0x0000000000010000u) +#define SDMMC_DM_CM_INFO1_DTRANEND0_SHIFT (16u) +#define SDMMC_DM_CM_INFO1_DTRANEND1 (0x0000000000100000u) +#define SDMMC_DM_CM_INFO1_DTRANEND1_SHIFT (20u) +#define SDMMC_DM_CM_INFO1_MASK_SEQEND_MASK (0x0000000000000001u) +#define SDMMC_DM_CM_INFO1_MASK_SEQEND_MASK_SHIFT (0u) +#define SDMMC_DM_CM_INFO1_MASK_DTRANEND0_MASK (0x0000000000010000u) +#define SDMMC_DM_CM_INFO1_MASK_DTRANEND0_MASK_SHIFT (16u) +#define SDMMC_DM_CM_INFO1_MASK_DTRANEND1_MASK (0x0000000000100000u) +#define SDMMC_DM_CM_INFO1_MASK_DTRANEND1_MASK_SHIFT (20u) +#define SDMMC_DM_CM_INFO2_SEQERR (0x0000000000000001u) +#define SDMMC_DM_CM_INFO2_SEQERR_SHIFT (0u) +#define SDMMC_DM_CM_INFO2_DTRANERR0 (0x0000000000010000u) +#define SDMMC_DM_CM_INFO2_DTRANERR0_SHIFT (16u) +#define SDMMC_DM_CM_INFO2_DTRANERR1 (0x0000000000020000u) +#define SDMMC_DM_CM_INFO2_DTRANERR1_SHIFT (17u) +#define SDMMC_DM_CM_INFO2_MASK_SEQERR_MASK (0x0000000000000001u) +#define SDMMC_DM_CM_INFO2_MASK_SEQERR_MASK_SHIFT (0u) +#define SDMMC_DM_CM_INFO2_MASK_DTRANERR0_MASK (0x0000000000010000u) +#define SDMMC_DM_CM_INFO2_MASK_DTRANERR0_MASK_SHIFT (16u) +#define SDMMC_DM_CM_INFO2_MASK_DTRANERR1_MASK (0x0000000000020000u) +#define SDMMC_DM_CM_INFO2_MASK_DTRANERR1_MASK_SHIFT (17u) +#define SDMMC_DM_DTRAN_ADDR_DADDR (0x00000000FFFFFFC0u) +#define SDMMC_DM_DTRAN_ADDR_DADDR_SHIFT (3u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spdif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spdif_iobitmask.h new file mode 100644 index 0000000..099b4d6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spdif_iobitmask.h @@ -0,0 +1,200 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef SPDIF_IOBITMASK_H +#define SPDIF_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define SPDIF_TLCA_TLCA (0x00FFFFFFu) +#define SPDIF_TLCA_TLCA_SHIFT (0u) +#define SPDIF_TRCA_TRCA (0x00FFFFFFu) +#define SPDIF_TRCA_TRCA_SHIFT (0u) +#define SPDIF_TLCS_CTL (0x0000003Eu) +#define SPDIF_TLCS_CTL_SHIFT (1u) +#define SPDIF_TLCS_CATCD (0x0000FF00u) +#define SPDIF_TLCS_CATCD_SHIFT (8u) +#define SPDIF_TLCS_SRCNO (0x000F0000u) +#define SPDIF_TLCS_SRCNO_SHIFT (16u) +#define SPDIF_TLCS_CHNO (0x00F00000u) +#define SPDIF_TLCS_CHNO_SHIFT (20u) +#define SPDIF_TLCS_FS (0x0F000000u) +#define SPDIF_TLCS_FS_SHIFT (24u) +#define SPDIF_TLCS_CLAC (0x30000000u) +#define SPDIF_TLCS_CLAC_SHIFT (28u) +#define SPDIF_TRCS_CTL (0x0000003Eu) +#define SPDIF_TRCS_CTL_SHIFT (1u) +#define SPDIF_TRCS_CATCD (0x0000FF00u) +#define SPDIF_TRCS_CATCD_SHIFT (8u) +#define SPDIF_TRCS_SRCNO (0x000F0000u) +#define SPDIF_TRCS_SRCNO_SHIFT (16u) +#define SPDIF_TRCS_CHNO (0x00F00000u) +#define SPDIF_TRCS_CHNO_SHIFT (20u) +#define SPDIF_TRCS_FS (0x0F000000u) +#define SPDIF_TRCS_FS_SHIFT (24u) +#define SPDIF_TRCS_CLAC (0x30000000u) +#define SPDIF_TRCS_CLAC_SHIFT (28u) +#define SPDIF_TUI_TUI (0xFFFFFFFFu) +#define SPDIF_TUI_TUI_SHIFT (0u) +#define SPDIF_RLCA_RLCA (0x00FFFFFFu) +#define SPDIF_RLCA_RLCA_SHIFT (0u) +#define SPDIF_RRCA_RRCA (0x00FFFFFFu) +#define SPDIF_RRCA_RRCA_SHIFT (0u) +#define SPDIF_RLCS_CTL (0x0000003Eu) +#define SPDIF_RLCS_CTL_SHIFT (1u) +#define SPDIF_RLCS_CATCD (0x0000FF00u) +#define SPDIF_RLCS_CATCD_SHIFT (8u) +#define SPDIF_RLCS_SRCNO (0x000F0000u) +#define SPDIF_RLCS_SRCNO_SHIFT (16u) +#define SPDIF_RLCS_CHNO (0x00F00000u) +#define SPDIF_RLCS_CHNO_SHIFT (20u) +#define SPDIF_RLCS_FS (0x0F000000u) +#define SPDIF_RLCS_FS_SHIFT (24u) +#define SPDIF_RLCS_CLAC (0x30000000u) +#define SPDIF_RLCS_CLAC_SHIFT (28u) +#define SPDIF_RRCS_CTL (0x0000003Eu) +#define SPDIF_RRCS_CTL_SHIFT (1u) +#define SPDIF_RRCS_CATCD (0x0000FF00u) +#define SPDIF_RRCS_CATCD_SHIFT (8u) +#define SPDIF_RRCS_SRCNO (0x000F0000u) +#define SPDIF_RRCS_SRCNO_SHIFT (16u) +#define SPDIF_RRCS_CHNO (0x00F00000u) +#define SPDIF_RRCS_CHNO_SHIFT (20u) +#define SPDIF_RRCS_FS (0x0F000000u) +#define SPDIF_RRCS_FS_SHIFT (24u) +#define SPDIF_RRCS_CLAC (0x30000000u) +#define SPDIF_RRCS_CLAC_SHIFT (28u) +#define SPDIF_RUI_RUI (0xFFFFFFFFu) +#define SPDIF_RUI_RUI_SHIFT (0u) +#define SPDIF_CTRL_TCBI (0x00000001u) +#define SPDIF_CTRL_TCBI_SHIFT (0u) +#define SPDIF_CTRL_TCSI (0x00000002u) +#define SPDIF_CTRL_TCSI_SHIFT (1u) +#define SPDIF_CTRL_RCBI (0x00000004u) +#define SPDIF_CTRL_RCBI_SHIFT (2u) +#define SPDIF_CTRL_RCSI (0x00000008u) +#define SPDIF_CTRL_RCSI_SHIFT (3u) +#define SPDIF_CTRL_TUII (0x00000010u) +#define SPDIF_CTRL_TUII_SHIFT (4u) +#define SPDIF_CTRL_RUII (0x00000020u) +#define SPDIF_CTRL_RUII_SHIFT (5u) +#define SPDIF_CTRL_ABUI (0x00000040u) +#define SPDIF_CTRL_ABUI_SHIFT (6u) +#define SPDIF_CTRL_ABOI (0x00000080u) +#define SPDIF_CTRL_ABOI_SHIFT (7u) +#define SPDIF_CTRL_CSEI (0x00000100u) +#define SPDIF_CTRL_CSEI_SHIFT (8u) +#define SPDIF_CTRL_PREI (0x00000200u) +#define SPDIF_CTRL_PREI_SHIFT (9u) +#define SPDIF_CTRL_PAEI (0x00000400u) +#define SPDIF_CTRL_PAEI_SHIFT (10u) +#define SPDIF_CTRL_CREI (0x00000800u) +#define SPDIF_CTRL_CREI_SHIFT (11u) +#define SPDIF_CTRL_UBUI (0x00001000u) +#define SPDIF_CTRL_UBUI_SHIFT (12u) +#define SPDIF_CTRL_UBOI (0x00002000u) +#define SPDIF_CTRL_UBOI_SHIFT (13u) +#define SPDIF_CTRL_TEIE (0x00004000u) +#define SPDIF_CTRL_TEIE_SHIFT (14u) +#define SPDIF_CTRL_REIE (0x00008000u) +#define SPDIF_CTRL_REIE_SHIFT (15u) +#define SPDIF_CTRL_TME (0x00010000u) +#define SPDIF_CTRL_TME_SHIFT (16u) +#define SPDIF_CTRL_RME (0x00020000u) +#define SPDIF_CTRL_RME_SHIFT (17u) +#define SPDIF_CTRL_AOS (0x00040000u) +#define SPDIF_CTRL_AOS_SHIFT (18u) +#define SPDIF_CTRL_NCSI (0x00080000u) +#define SPDIF_CTRL_NCSI_SHIFT (19u) +#define SPDIF_CTRL_TDE (0x00100000u) +#define SPDIF_CTRL_TDE_SHIFT (20u) +#define SPDIF_CTRL_RDE (0x00200000u) +#define SPDIF_CTRL_RDE_SHIFT (21u) +#define SPDIF_CTRL_TASS (0x00C00000u) +#define SPDIF_CTRL_TASS_SHIFT (22u) +#define SPDIF_CTRL_RASS (0x03000000u) +#define SPDIF_CTRL_RASS_SHIFT (24u) +#define SPDIF_CTRL_PB (0x04000000u) +#define SPDIF_CTRL_PB_SHIFT (26u) +#define SPDIF_CTRL_CKS (0x10000000u) +#define SPDIF_CTRL_CKS_SHIFT (28u) +#define SPDIF_STAT_CBTX (0x00000001u) +#define SPDIF_STAT_CBTX_SHIFT (0u) +#define SPDIF_STAT_CSTX (0x00000002u) +#define SPDIF_STAT_CSTX_SHIFT (1u) +#define SPDIF_STAT_CBRX (0x00000004u) +#define SPDIF_STAT_CBRX_SHIFT (2u) +#define SPDIF_STAT_CSRX (0x00000008u) +#define SPDIF_STAT_CSRX_SHIFT (3u) +#define SPDIF_STAT_TUIR (0x00000010u) +#define SPDIF_STAT_TUIR_SHIFT (4u) +#define SPDIF_STAT_RUIR (0x00000020u) +#define SPDIF_STAT_RUIR_SHIFT (5u) +#define SPDIF_STAT_ABU (0x00000040u) +#define SPDIF_STAT_ABU_SHIFT (6u) +#define SPDIF_STAT_ABO (0x00000080u) +#define SPDIF_STAT_ABO_SHIFT (7u) +#define SPDIF_STAT_CSE (0x00000100u) +#define SPDIF_STAT_CSE_SHIFT (8u) +#define SPDIF_STAT_PREE (0x00000200u) +#define SPDIF_STAT_PREE_SHIFT (9u) +#define SPDIF_STAT_PARE (0x00000400u) +#define SPDIF_STAT_PARE_SHIFT (10u) +#define SPDIF_STAT_CE (0x00000800u) +#define SPDIF_STAT_CE_SHIFT (11u) +#define SPDIF_STAT_UBU (0x00001000u) +#define SPDIF_STAT_UBU_SHIFT (12u) +#define SPDIF_STAT_UBO (0x00002000u) +#define SPDIF_STAT_UBO_SHIFT (13u) +#define SPDIF_STAT_TIS (0x00004000u) +#define SPDIF_STAT_TIS_SHIFT (14u) +#define SPDIF_STAT_RIS (0x00008000u) +#define SPDIF_STAT_RIS_SHIFT (15u) +#define SPDIF_STAT_CMD (0x00010000u) +#define SPDIF_STAT_CMD_SHIFT (16u) +#define SPDIF_TDAD_TDAD (0x00FFFFFFu) +#define SPDIF_TDAD_TDAD_SHIFT (0u) +#define SPDIF_RDAD_RDAD (0x00FFFFFFu) +#define SPDIF_RDAD_RDAD_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spibsc_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spibsc_iobitmask.h new file mode 100644 index 0000000..54b91c8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/spibsc_iobitmask.h @@ -0,0 +1,236 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef SPIBSC_IOBITMASK_H +#define SPIBSC_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define SPIBSC_CMNCR_BSZ (0x00000003u) +#define SPIBSC_CMNCR_BSZ_SHIFT (0u) +#define SPIBSC_CMNCR_IO0FV (0x00000300u) +#define SPIBSC_CMNCR_IO0FV_SHIFT (8u) +#define SPIBSC_CMNCR_IO2FV (0x00003000u) +#define SPIBSC_CMNCR_IO2FV_SHIFT (12u) +#define SPIBSC_CMNCR_IO3FV (0x0000C000u) +#define SPIBSC_CMNCR_IO3FV_SHIFT (14u) +#define SPIBSC_CMNCR_MOIIO0 (0x00030000u) +#define SPIBSC_CMNCR_MOIIO0_SHIFT (16u) +#define SPIBSC_CMNCR_MOIIO1 (0x000C0000u) +#define SPIBSC_CMNCR_MOIIO1_SHIFT (18u) +#define SPIBSC_CMNCR_MOIIO2 (0x00300000u) +#define SPIBSC_CMNCR_MOIIO2_SHIFT (20u) +#define SPIBSC_CMNCR_MOIIO3 (0x00C00000u) +#define SPIBSC_CMNCR_MOIIO3_SHIFT (22u) +#define SPIBSC_CMNCR_MD (0x80000000u) +#define SPIBSC_CMNCR_MD_SHIFT (31u) +#define SPIBSC_SSLDR_SCKDL (0x00000007u) +#define SPIBSC_SSLDR_SCKDL_SHIFT (0u) +#define SPIBSC_SSLDR_SLNDL (0x00000700u) +#define SPIBSC_SSLDR_SLNDL_SHIFT (8u) +#define SPIBSC_SSLDR_SPNDL (0x00070000u) +#define SPIBSC_SSLDR_SPNDL_SHIFT (16u) +#define SPIBSC_DRCR_SSLE (0x00000001u) +#define SPIBSC_DRCR_SSLE_SHIFT (0u) +#define SPIBSC_DRCR_RBE (0x00000100u) +#define SPIBSC_DRCR_RBE_SHIFT (8u) +#define SPIBSC_DRCR_RCF (0x00000200u) +#define SPIBSC_DRCR_RCF_SHIFT (9u) +#define SPIBSC_DRCR_RBURST (0x001F0000u) +#define SPIBSC_DRCR_RBURST_SHIFT (16u) +#define SPIBSC_DRCR_SSLN (0x01000000u) +#define SPIBSC_DRCR_SSLN_SHIFT (24u) +#define SPIBSC_DRCMR_OCMD (0x000000FFu) +#define SPIBSC_DRCMR_OCMD_SHIFT (0u) +#define SPIBSC_DRCMR_CMD (0x00FF0000u) +#define SPIBSC_DRCMR_CMD_SHIFT (16u) +#define SPIBSC_DREAR_EAC (0x00000007u) +#define SPIBSC_DREAR_EAC_SHIFT (0u) +#define SPIBSC_DREAR_EAV (0x00FF0000u) +#define SPIBSC_DREAR_EAV_SHIFT (16u) +#define SPIBSC_DROPR_OPD0 (0x000000FFu) +#define SPIBSC_DROPR_OPD0_SHIFT (0u) +#define SPIBSC_DROPR_OPD1 (0x0000FF00u) +#define SPIBSC_DROPR_OPD1_SHIFT (8u) +#define SPIBSC_DROPR_OPD2 (0x00FF0000u) +#define SPIBSC_DROPR_OPD2_SHIFT (16u) +#define SPIBSC_DROPR_OPD3 (0xFF000000u) +#define SPIBSC_DROPR_OPD3_SHIFT (24u) +#define SPIBSC_DRENR_OPDE (0x000000F0u) +#define SPIBSC_DRENR_OPDE_SHIFT (4u) +#define SPIBSC_DRENR_ADE (0x00000F00u) +#define SPIBSC_DRENR_ADE_SHIFT (8u) +#define SPIBSC_DRENR_OCDE (0x00001000u) +#define SPIBSC_DRENR_OCDE_SHIFT (12u) +#define SPIBSC_DRENR_CDE (0x00004000u) +#define SPIBSC_DRENR_CDE_SHIFT (14u) +#define SPIBSC_DRENR_DME (0x00008000u) +#define SPIBSC_DRENR_DME_SHIFT (15u) +#define SPIBSC_DRENR_DRDB (0x00030000u) +#define SPIBSC_DRENR_DRDB_SHIFT (16u) +#define SPIBSC_DRENR_OPDB (0x00300000u) +#define SPIBSC_DRENR_OPDB_SHIFT (20u) +#define SPIBSC_DRENR_ADB (0x03000000u) +#define SPIBSC_DRENR_ADB_SHIFT (24u) +#define SPIBSC_DRENR_OCDB (0x30000000u) +#define SPIBSC_DRENR_OCDB_SHIFT (28u) +#define SPIBSC_DRENR_CDB (0xC0000000u) +#define SPIBSC_DRENR_CDB_SHIFT (30u) +#define SPIBSC_SMCR_SPIE (0x00000001u) +#define SPIBSC_SMCR_SPIE_SHIFT (0u) +#define SPIBSC_SMCR_SPIWE (0x00000002u) +#define SPIBSC_SMCR_SPIWE_SHIFT (1u) +#define SPIBSC_SMCR_SPIRE (0x00000004u) +#define SPIBSC_SMCR_SPIRE_SHIFT (2u) +#define SPIBSC_SMCR_SSLKP (0x00000100u) +#define SPIBSC_SMCR_SSLKP_SHIFT (8u) +#define SPIBSC_SMCMR_OCMD (0x000000FFu) +#define SPIBSC_SMCMR_OCMD_SHIFT (0u) +#define SPIBSC_SMCMR_CMD (0x00FF0000u) +#define SPIBSC_SMCMR_CMD_SHIFT (16u) +#define SPIBSC_SMADR_ADR (0xFFFFFFFFu) +#define SPIBSC_SMADR_ADR_SHIFT (0u) +#define SPIBSC_SMOPR_OPD0 (0x000000FFu) +#define SPIBSC_SMOPR_OPD0_SHIFT (0u) +#define SPIBSC_SMOPR_OPD1 (0x0000FF00u) +#define SPIBSC_SMOPR_OPD1_SHIFT (8u) +#define SPIBSC_SMOPR_OPD2 (0x00FF0000u) +#define SPIBSC_SMOPR_OPD2_SHIFT (16u) +#define SPIBSC_SMOPR_OPD3 (0xFF000000u) +#define SPIBSC_SMOPR_OPD3_SHIFT (24u) +#define SPIBSC_SMENR_SPIDE (0x0000000Fu) +#define SPIBSC_SMENR_SPIDE_SHIFT (0u) +#define SPIBSC_SMENR_OPDE (0x000000F0u) +#define SPIBSC_SMENR_OPDE_SHIFT (4u) +#define SPIBSC_SMENR_ADE (0x00000F00u) +#define SPIBSC_SMENR_ADE_SHIFT (8u) +#define SPIBSC_SMENR_OCDE (0x00001000u) +#define SPIBSC_SMENR_OCDE_SHIFT (12u) +#define SPIBSC_SMENR_CDE (0x00004000u) +#define SPIBSC_SMENR_CDE_SHIFT (14u) +#define SPIBSC_SMENR_DME (0x00008000u) +#define SPIBSC_SMENR_DME_SHIFT (15u) +#define SPIBSC_SMENR_SPIDB (0x00030000u) +#define SPIBSC_SMENR_SPIDB_SHIFT (16u) +#define SPIBSC_SMENR_OPDB (0x00300000u) +#define SPIBSC_SMENR_OPDB_SHIFT (20u) +#define SPIBSC_SMENR_ADB (0x03000000u) +#define SPIBSC_SMENR_ADB_SHIFT (24u) +#define SPIBSC_SMENR_OCDB (0x30000000u) +#define SPIBSC_SMENR_OCDB_SHIFT (28u) +#define SPIBSC_SMENR_CDB (0xC0000000u) +#define SPIBSC_SMENR_CDB_SHIFT (30u) +#define SPIBSC_SMRDR0_RDATA0 (0xFFFFFFFFu) +#define SPIBSC_SMRDR0_RDATA0_SHIFT (0u) +#define SPIBSC_SMRDR1_RDATA1 (0xFFFFFFFFu) +#define SPIBSC_SMRDR1_RDATA1_SHIFT (0u) +#define SPIBSC_SMWDR0_WDATA0 (0xFFFFFFFFu) +#define SPIBSC_SMWDR0_WDATA0_SHIFT (0u) +#define SPIBSC_SMWDR1_WDATA1 (0xFFFFFFFFu) +#define SPIBSC_SMWDR1_WDATA1_SHIFT (0u) +#define SPIBSC_CMNSR_TEND (0x00000001u) +#define SPIBSC_CMNSR_TEND_SHIFT (0u) +#define SPIBSC_CMNSR_SSLF (0x00000002u) +#define SPIBSC_CMNSR_SSLF_SHIFT (1u) +#define SPIBSC_DRDMCR_DMCYC (0x0000001Fu) +#define SPIBSC_DRDMCR_DMCYC_SHIFT (0u) +#define SPIBSC_DRDRENR_DRDRE (0x00000001u) +#define SPIBSC_DRDRENR_DRDRE_SHIFT (0u) +#define SPIBSC_DRDRENR_OPDRE (0x00000010u) +#define SPIBSC_DRDRENR_OPDRE_SHIFT (4u) +#define SPIBSC_DRDRENR_ADDRE (0x00000100u) +#define SPIBSC_DRDRENR_ADDRE_SHIFT (8u) +#define SPIBSC_DRDRENR_HYPE (0x00007000u) +#define SPIBSC_DRDRENR_HYPE_SHIFT (12u) +#define SPIBSC_SMDMCR_DMCYC (0x0000001Fu) +#define SPIBSC_SMDMCR_DMCYC_SHIFT (0u) +#define SPIBSC_SMDRENR_SPIDRE (0x00000001u) +#define SPIBSC_SMDRENR_SPIDRE_SHIFT (0u) +#define SPIBSC_SMDRENR_OPDRE (0x00000010u) +#define SPIBSC_SMDRENR_OPDRE_SHIFT (4u) +#define SPIBSC_SMDRENR_ADDRE (0x00000100u) +#define SPIBSC_SMDRENR_ADDRE_SHIFT (8u) +#define SPIBSC_SMDRENR_HYPE (0x00007000u) +#define SPIBSC_SMDRENR_HYPE_SHIFT (12u) +#define SPIBSC_PHYADJ1_ADJ1 (0xFFFFFFFFu) +#define SPIBSC_PHYADJ1_ADJ1_SHIFT (0u) +#define SPIBSC_PHYADJ2_ADJ2 (0xFFFFFFFFu) +#define SPIBSC_PHYADJ2_ADJ2_SHIFT (0u) +#define SPIBSC_PHYCNT_PHYMEM (0x00000003u) +#define SPIBSC_PHYCNT_PHYMEM_SHIFT (0u) +#define SPIBSC_PHYCNT_WBUF (0x00000004u) +#define SPIBSC_PHYCNT_WBUF_SHIFT (2u) +#define SPIBSC_PHYCNT_WBUF2 (0x00000010u) +#define SPIBSC_PHYCNT_WBUF2_SHIFT (4u) +#define SPIBSC_PHYCNT_CKSEL (0x00030000u) +#define SPIBSC_PHYCNT_CKSEL_SHIFT (16u) +#define SPIBSC_PHYCNT_HS (0x00040000u) +#define SPIBSC_PHYCNT_HS_SHIFT (18u) +#define SPIBSC_PHYCNT_OCT (0x00100000u) +#define SPIBSC_PHYCNT_OCT_SHIFT (20u) +#define SPIBSC_PHYCNT_EXDS (0x00200000u) +#define SPIBSC_PHYCNT_EXDS_SHIFT (21u) +#define SPIBSC_PHYCNT_OCTA_1_0 (0x00C00000u) +#define SPIBSC_PHYCNT_OCTA_1_0_SHIFT (22u) +#define SPIBSC_PHYCNT_ALT_ALIGN (0x40000000u) +#define SPIBSC_PHYCNT_ALT_ALIGN_SHIFT (30u) +#define SPIBSC_PHYCNT_CAL (0x80000000u) +#define SPIBSC_PHYCNT_CAL_SHIFT (31u) +#define SPIBSC_PHYOFFSET1_DDRTMG (0x30000000u) +#define SPIBSC_PHYOFFSET1_DDRTMG_SHIFT (28u) +#define SPIBSC_PHYOFFSET2_OCTTMG (0x00000700u) +#define SPIBSC_PHYOFFSET2_OCTTMG_SHIFT (8u) +#define SPIBSC_PHYINT_INT (0x00000001u) +#define SPIBSC_PHYINT_INT_SHIFT (0u) +#define SPIBSC_PHYINT_WPVAL (0x00000002u) +#define SPIBSC_PHYINT_WPVAL_SHIFT (1u) +#define SPIBSC_PHYINT_RSTVAL (0x00000004u) +#define SPIBSC_PHYINT_RSTVAL_SHIFT (2u) +#define SPIBSC_PHYINT_INTEN (0x01000000u) +#define SPIBSC_PHYINT_INTEN_SHIFT (24u) +#define SPIBSC_PHYINT_WPEN (0x02000000u) +#define SPIBSC_PHYINT_WPEN_SHIFT (25u) +#define SPIBSC_PHYINT_RSTEN (0x04000000u) +#define SPIBSC_PHYINT_RSTEN_SHIFT (26u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sprite_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sprite_iobitmask.h new file mode 100644 index 0000000..56885f0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/sprite_iobitmask.h @@ -0,0 +1,516 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef SPRITE_IOBITMASK_H +#define SPRITE_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define SPRITE_SPEA0RLSL_SPEA0RBUSSEL (0x00000001u) +#define SPRITE_SPEA0RLSL_SPEA0RBUSSEL_SHIFT (0u) +#define SPRITE_SPEA0STA0_SPEA0RSTA0 (0xFFFFFFFFu) +#define SPRITE_SPEA0STA0_SPEA0RSTA0_SHIFT (0u) +#define SPRITE_SPEA0PHA0_SPEA0RPHA0 (0xFFFFFFFFu) +#define SPRITE_SPEA0PHA0_SPEA0RPHA0_SHIFT (0u) +#define SPRITE_SPEA0RCM0_SPEA0RCM0 (0x00000003u) +#define SPRITE_SPEA0RCM0_SPEA0RCM0_SHIFT (0u) +#define SPRITE_SPEA0RUP_SPEA0RUP0 (0x00000001u) +#define SPRITE_SPEA0RUP_SPEA0RUP0_SHIFT (0u) +#define SPRITE_SPEA0RCFG_SPEA0RDTH (0x00000007u) +#define SPRITE_SPEA0RCFG_SPEA0RDTH_SHIFT (0u) +#define SPRITE_SPEA0RCFG_SPEA0RLEN (0x00000070u) +#define SPRITE_SPEA0RCFG_SPEA0RLEN_SHIFT (4u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN0 (0x00000001u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN0_SHIFT (0u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN1 (0x00000002u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN1_SHIFT (1u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN2 (0x00000004u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN2_SHIFT (2u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN3 (0x00000008u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN3_SHIFT (3u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN4 (0x00000010u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN4_SHIFT (4u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN5 (0x00000020u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN5_SHIFT (5u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN6 (0x00000040u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN6_SHIFT (6u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN7 (0x00000080u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN7_SHIFT (7u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN8 (0x00000100u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN8_SHIFT (8u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN9 (0x00000200u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN9_SHIFT (9u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN10 (0x00000400u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN10_SHIFT (10u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN11 (0x00000800u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN11_SHIFT (11u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN12 (0x00001000u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN12_SHIFT (12u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN13 (0x00002000u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN13_SHIFT (13u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN14 (0x00004000u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN14_SHIFT (14u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN15 (0x00008000u) +#define SPRITE_SPEA0S0EN_SPEA0S0EN15_SHIFT (15u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS0 (0x00000001u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS0_SHIFT (0u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS1 (0x00000002u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS1_SHIFT (1u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS2 (0x00000004u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS2_SHIFT (2u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS3 (0x00000008u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS3_SHIFT (3u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS4 (0x00000010u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS4_SHIFT (4u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS5 (0x00000020u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS5_SHIFT (5u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS6 (0x00000040u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS6_SHIFT (6u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS7 (0x00000080u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS7_SHIFT (7u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS8 (0x00000100u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS8_SHIFT (8u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS9 (0x00000200u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS9_SHIFT (9u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS10 (0x00000400u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS10_SHIFT (10u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS11 (0x00000800u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS11_SHIFT (11u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS12 (0x00001000u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS12_SHIFT (12u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS13 (0x00002000u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS13_SHIFT (13u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS14 (0x00004000u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS14_SHIFT (14u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS15 (0x00008000u) +#define SPRITE_SPEA0S0DS_SPEA0S0DS15_SHIFT (15u) +#define SPRITE_SPEA0S0UP_SPEA0S0UP0 (0x00000001u) +#define SPRITE_SPEA0S0UP_SPEA0S0UP0_SHIFT (0u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN0 (0x00000001u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN0_SHIFT (0u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN1 (0x00000002u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN1_SHIFT (1u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN2 (0x00000004u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN2_SHIFT (2u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN3 (0x00000008u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN3_SHIFT (3u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN4 (0x00000010u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN4_SHIFT (4u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN5 (0x00000020u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN5_SHIFT (5u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN6 (0x00000040u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN6_SHIFT (6u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN7 (0x00000080u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN7_SHIFT (7u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN8 (0x00000100u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN8_SHIFT (8u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN9 (0x00000200u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN9_SHIFT (9u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN10 (0x00000400u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN10_SHIFT (10u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN11 (0x00000800u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN11_SHIFT (11u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN12 (0x00001000u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN12_SHIFT (12u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN13 (0x00002000u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN13_SHIFT (13u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN14 (0x00004000u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN14_SHIFT (14u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN15 (0x00008000u) +#define SPRITE_SPEA0S1EN_SPEA0S1EN15_SHIFT (15u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS0 (0x00000001u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS0_SHIFT (0u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS1 (0x00000002u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS1_SHIFT (1u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS2 (0x00000004u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS2_SHIFT (2u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS3 (0x00000008u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS3_SHIFT (3u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS4 (0x00000010u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS4_SHIFT (4u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS5 (0x00000020u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS5_SHIFT (5u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS6 (0x00000040u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS6_SHIFT (6u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS7 (0x00000080u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS7_SHIFT (7u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS8 (0x00000100u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS8_SHIFT (8u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS9 (0x00000200u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS9_SHIFT (9u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS10 (0x00000400u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS10_SHIFT (10u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS11 (0x00000800u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS11_SHIFT (11u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS12 (0x00001000u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS12_SHIFT (12u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS13 (0x00002000u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS13_SHIFT (13u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS14 (0x00004000u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS14_SHIFT (14u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS15 (0x00008000u) +#define SPRITE_SPEA0S1DS_SPEA0S1DS15_SHIFT (15u) +#define SPRITE_SPEA0S1UP_SPEA0S1UP0 (0x00000001u) +#define SPRITE_SPEA0S1UP_SPEA0S1UP0_SHIFT (0u) +#define SPRITE_SPEA0S0DA0_SPEA0S0DA0 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA0_SPEA0S0DA0_SHIFT (0u) +#define SPRITE_SPEA0S0LY0_SPEA0S0LYH0 (0x000007FFu) +#define SPRITE_SPEA0S0LY0_SPEA0S0LYH0_SHIFT (0u) +#define SPRITE_SPEA0S0LY0_SPEA0S0LYW0 (0x07FE0000u) +#define SPRITE_SPEA0S0LY0_SPEA0S0LYW0_SHIFT (17u) +#define SPRITE_SPEA0S0PS0_SPEA0S0PSY0 (0x00001FFFu) +#define SPRITE_SPEA0S0PS0_SPEA0S0PSY0_SHIFT (0u) +#define SPRITE_SPEA0S0PS0_SPEA0S0PSX0 (0x07FE0000u) +#define SPRITE_SPEA0S0PS0_SPEA0S0PSX0_SHIFT (17u) +#define SPRITE_SPEA0S0DA1_SPEA0S0DA1 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA1_SPEA0S0DA1_SHIFT (0u) +#define SPRITE_SPEA0S0LY1_SPEA0S0LYH1 (0x000007FFu) +#define SPRITE_SPEA0S0LY1_SPEA0S0LYH1_SHIFT (0u) +#define SPRITE_SPEA0S0LY1_SPEA0S0LYW1 (0x07FE0000u) +#define SPRITE_SPEA0S0LY1_SPEA0S0LYW1_SHIFT (17u) +#define SPRITE_SPEA0S0PS1_SPEA0S0PSY1 (0x00001FFFu) +#define SPRITE_SPEA0S0PS1_SPEA0S0PSY1_SHIFT (0u) +#define SPRITE_SPEA0S0PS1_SPEA0S0PSX1 (0x07FE0000u) +#define SPRITE_SPEA0S0PS1_SPEA0S0PSX1_SHIFT (17u) +#define SPRITE_SPEA0S0DA2_SPEA0S0DA2 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA2_SPEA0S0DA2_SHIFT (0u) +#define SPRITE_SPEA0S0LY2_SPEA0S0LYH2 (0x000007FFu) +#define SPRITE_SPEA0S0LY2_SPEA0S0LYH2_SHIFT (0u) +#define SPRITE_SPEA0S0LY2_SPEA0S0LYW2 (0x07FE0000u) +#define SPRITE_SPEA0S0LY2_SPEA0S0LYW2_SHIFT (17u) +#define SPRITE_SPEA0S0PS2_SPEA0S0PSY2 (0x00001FFFu) +#define SPRITE_SPEA0S0PS2_SPEA0S0PSY2_SHIFT (0u) +#define SPRITE_SPEA0S0PS2_SPEA0S0PSX2 (0x07FE0000u) +#define SPRITE_SPEA0S0PS2_SPEA0S0PSX2_SHIFT (17u) +#define SPRITE_SPEA0S0DA3_SPEA0S0DA3 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA3_SPEA0S0DA3_SHIFT (0u) +#define SPRITE_SPEA0S0LY3_SPEA0S0LYH3 (0x000007FFu) +#define SPRITE_SPEA0S0LY3_SPEA0S0LYH3_SHIFT (0u) +#define SPRITE_SPEA0S0LY3_SPEA0S0LYW3 (0x07FE0000u) +#define SPRITE_SPEA0S0LY3_SPEA0S0LYW3_SHIFT (17u) +#define SPRITE_SPEA0S0PS3_SPEA0S0PSY3 (0x00001FFFu) +#define SPRITE_SPEA0S0PS3_SPEA0S0PSY3_SHIFT (0u) +#define SPRITE_SPEA0S0PS3_SPEA0S0PSX3 (0x07FE0000u) +#define SPRITE_SPEA0S0PS3_SPEA0S0PSX3_SHIFT (17u) +#define SPRITE_SPEA0S0DA4_SPEA0S0DA4 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA4_SPEA0S0DA4_SHIFT (0u) +#define SPRITE_SPEA0S0LY4_SPEA0S0LYH4 (0x000007FFu) +#define SPRITE_SPEA0S0LY4_SPEA0S0LYH4_SHIFT (0u) +#define SPRITE_SPEA0S0LY4_SPEA0S0LYW4 (0x07FE0000u) +#define SPRITE_SPEA0S0LY4_SPEA0S0LYW4_SHIFT (17u) +#define SPRITE_SPEA0S0PS4_SPEA0S0PSY4 (0x00001FFFu) +#define SPRITE_SPEA0S0PS4_SPEA0S0PSY4_SHIFT (0u) +#define SPRITE_SPEA0S0PS4_SPEA0S0PSX4 (0x07FE0000u) +#define SPRITE_SPEA0S0PS4_SPEA0S0PSX4_SHIFT (17u) +#define SPRITE_SPEA0S0DA5_SPEA0S0DA5 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA5_SPEA0S0DA5_SHIFT (0u) +#define SPRITE_SPEA0S0LY5_SPEA0S0LYH5 (0x000007FFu) +#define SPRITE_SPEA0S0LY5_SPEA0S0LYH5_SHIFT (0u) +#define SPRITE_SPEA0S0LY5_SPEA0S0LYW5 (0x07FE0000u) +#define SPRITE_SPEA0S0LY5_SPEA0S0LYW5_SHIFT (17u) +#define SPRITE_SPEA0S0PS5_SPEA0S0PSY5 (0x00001FFFu) +#define SPRITE_SPEA0S0PS5_SPEA0S0PSY5_SHIFT (0u) +#define SPRITE_SPEA0S0PS5_SPEA0S0PSX5 (0x07FE0000u) +#define SPRITE_SPEA0S0PS5_SPEA0S0PSX5_SHIFT (17u) +#define SPRITE_SPEA0S0DA6_SPEA0S0DA6 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA6_SPEA0S0DA6_SHIFT (0u) +#define SPRITE_SPEA0S0LY6_SPEA0S0LYH6 (0x000007FFu) +#define SPRITE_SPEA0S0LY6_SPEA0S0LYH6_SHIFT (0u) +#define SPRITE_SPEA0S0LY6_SPEA0S0LYW6 (0x07FE0000u) +#define SPRITE_SPEA0S0LY6_SPEA0S0LYW6_SHIFT (17u) +#define SPRITE_SPEA0S0PS6_SPEA0S0PSY6 (0x00001FFFu) +#define SPRITE_SPEA0S0PS6_SPEA0S0PSY6_SHIFT (0u) +#define SPRITE_SPEA0S0PS6_SPEA0S0PSX6 (0x07FE0000u) +#define SPRITE_SPEA0S0PS6_SPEA0S0PSX6_SHIFT (17u) +#define SPRITE_SPEA0S0DA7_SPEA0S0DA7 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA7_SPEA0S0DA7_SHIFT (0u) +#define SPRITE_SPEA0S0LY7_SPEA0S0LYH7 (0x000007FFu) +#define SPRITE_SPEA0S0LY7_SPEA0S0LYH7_SHIFT (0u) +#define SPRITE_SPEA0S0LY7_SPEA0S0LYW7 (0x07FE0000u) +#define SPRITE_SPEA0S0LY7_SPEA0S0LYW7_SHIFT (17u) +#define SPRITE_SPEA0S0PS7_SPEA0S0PSY7 (0x00001FFFu) +#define SPRITE_SPEA0S0PS7_SPEA0S0PSY7_SHIFT (0u) +#define SPRITE_SPEA0S0PS7_SPEA0S0PSX7 (0x07FE0000u) +#define SPRITE_SPEA0S0PS7_SPEA0S0PSX7_SHIFT (17u) +#define SPRITE_SPEA0S0DA8_SPEA0S0DA8 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA8_SPEA0S0DA8_SHIFT (0u) +#define SPRITE_SPEA0S0LY8_SPEA0S0LYH8 (0x000007FFu) +#define SPRITE_SPEA0S0LY8_SPEA0S0LYH8_SHIFT (0u) +#define SPRITE_SPEA0S0LY8_SPEA0S0LYW8 (0x07FE0000u) +#define SPRITE_SPEA0S0LY8_SPEA0S0LYW8_SHIFT (17u) +#define SPRITE_SPEA0S0PS8_SPEA0S0PSY8 (0x00001FFFu) +#define SPRITE_SPEA0S0PS8_SPEA0S0PSY8_SHIFT (0u) +#define SPRITE_SPEA0S0PS8_SPEA0S0PSX8 (0x07FE0000u) +#define SPRITE_SPEA0S0PS8_SPEA0S0PSX8_SHIFT (17u) +#define SPRITE_SPEA0S0DA9_SPEA0S0DA9 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA9_SPEA0S0DA9_SHIFT (0u) +#define SPRITE_SPEA0S0LY9_SPEA0S0LYH9 (0x000007FFu) +#define SPRITE_SPEA0S0LY9_SPEA0S0LYH9_SHIFT (0u) +#define SPRITE_SPEA0S0LY9_SPEA0S0LYW9 (0x07FE0000u) +#define SPRITE_SPEA0S0LY9_SPEA0S0LYW9_SHIFT (17u) +#define SPRITE_SPEA0S0PS9_SPEA0S0PSY9 (0x00001FFFu) +#define SPRITE_SPEA0S0PS9_SPEA0S0PSY9_SHIFT (0u) +#define SPRITE_SPEA0S0PS9_SPEA0S0PSX9 (0x07FE0000u) +#define SPRITE_SPEA0S0PS9_SPEA0S0PSX9_SHIFT (17u) +#define SPRITE_SPEA0S0DA10_SPEA0S0DA10 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA10_SPEA0S0DA10_SHIFT (0u) +#define SPRITE_SPEA0S0LY10_SPEA0S0LYH10 (0x000007FFu) +#define SPRITE_SPEA0S0LY10_SPEA0S0LYH10_SHIFT (0u) +#define SPRITE_SPEA0S0LY10_SPEA0S0LYW10 (0x07FE0000u) +#define SPRITE_SPEA0S0LY10_SPEA0S0LYW10_SHIFT (17u) +#define SPRITE_SPEA0S0PS10_SPEA0S0PSY10 (0x00001FFFu) +#define SPRITE_SPEA0S0PS10_SPEA0S0PSY10_SHIFT (0u) +#define SPRITE_SPEA0S0PS10_SPEA0S0PSX10 (0x07FE0000u) +#define SPRITE_SPEA0S0PS10_SPEA0S0PSX10_SHIFT (17u) +#define SPRITE_SPEA0S0DA11_SPEA0S0DA11 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA11_SPEA0S0DA11_SHIFT (0u) +#define SPRITE_SPEA0S0LY11_SPEA0S0LYH11 (0x000007FFu) +#define SPRITE_SPEA0S0LY11_SPEA0S0LYH11_SHIFT (0u) +#define SPRITE_SPEA0S0LY11_SPEA0S0LYW11 (0x07FE0000u) +#define SPRITE_SPEA0S0LY11_SPEA0S0LYW11_SHIFT (17u) +#define SPRITE_SPEA0S0PS11_SPEA0S0PSY11 (0x00001FFFu) +#define SPRITE_SPEA0S0PS11_SPEA0S0PSY11_SHIFT (0u) +#define SPRITE_SPEA0S0PS11_SPEA0S0PSX11 (0x07FE0000u) +#define SPRITE_SPEA0S0PS11_SPEA0S0PSX11_SHIFT (17u) +#define SPRITE_SPEA0S0DA12_SPEA0S0DA12 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA12_SPEA0S0DA12_SHIFT (0u) +#define SPRITE_SPEA0S0LY12_SPEA0S0LYH12 (0x000007FFu) +#define SPRITE_SPEA0S0LY12_SPEA0S0LYH12_SHIFT (0u) +#define SPRITE_SPEA0S0LY12_SPEA0S0LYW12 (0x07FE0000u) +#define SPRITE_SPEA0S0LY12_SPEA0S0LYW12_SHIFT (17u) +#define SPRITE_SPEA0S0PS12_SPEA0S0PSY12 (0x00001FFFu) +#define SPRITE_SPEA0S0PS12_SPEA0S0PSY12_SHIFT (0u) +#define SPRITE_SPEA0S0PS12_SPEA0S0PSX12 (0x07FE0000u) +#define SPRITE_SPEA0S0PS12_SPEA0S0PSX12_SHIFT (17u) +#define SPRITE_SPEA0S0DA13_SPEA0S0DA13 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA13_SPEA0S0DA13_SHIFT (0u) +#define SPRITE_SPEA0S0LY13_SPEA0S0LYH13 (0x000007FFu) +#define SPRITE_SPEA0S0LY13_SPEA0S0LYH13_SHIFT (0u) +#define SPRITE_SPEA0S0LY13_SPEA0S0LYW13 (0x07FE0000u) +#define SPRITE_SPEA0S0LY13_SPEA0S0LYW13_SHIFT (17u) +#define SPRITE_SPEA0S0PS13_SPEA0S0PSY13 (0x00001FFFu) +#define SPRITE_SPEA0S0PS13_SPEA0S0PSY13_SHIFT (0u) +#define SPRITE_SPEA0S0PS13_SPEA0S0PSX13 (0x07FE0000u) +#define SPRITE_SPEA0S0PS13_SPEA0S0PSX13_SHIFT (17u) +#define SPRITE_SPEA0S0DA14_SPEA0S0DA14 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA14_SPEA0S0DA14_SHIFT (0u) +#define SPRITE_SPEA0S0LY14_SPEA0S0LYH14 (0x000007FFu) +#define SPRITE_SPEA0S0LY14_SPEA0S0LYH14_SHIFT (0u) +#define SPRITE_SPEA0S0LY14_SPEA0S0LYW14 (0x07FE0000u) +#define SPRITE_SPEA0S0LY14_SPEA0S0LYW14_SHIFT (17u) +#define SPRITE_SPEA0S0PS14_SPEA0S0PSY14 (0x00001FFFu) +#define SPRITE_SPEA0S0PS14_SPEA0S0PSY14_SHIFT (0u) +#define SPRITE_SPEA0S0PS14_SPEA0S0PSX14 (0x07FE0000u) +#define SPRITE_SPEA0S0PS14_SPEA0S0PSX14_SHIFT (17u) +#define SPRITE_SPEA0S0DA15_SPEA0S0DA15 (0xFFFFFFFFu) +#define SPRITE_SPEA0S0DA15_SPEA0S0DA15_SHIFT (0u) +#define SPRITE_SPEA0S0LY15_SPEA0S0LYH15 (0x000007FFu) +#define SPRITE_SPEA0S0LY15_SPEA0S0LYH15_SHIFT (0u) +#define SPRITE_SPEA0S0LY15_SPEA0S0LYW15 (0x07FE0000u) +#define SPRITE_SPEA0S0LY15_SPEA0S0LYW15_SHIFT (17u) +#define SPRITE_SPEA0S0PS15_SPEA0S0PSY15 (0x00001FFFu) +#define SPRITE_SPEA0S0PS15_SPEA0S0PSY15_SHIFT (0u) +#define SPRITE_SPEA0S0PS15_SPEA0S0PSX15 (0x07FE0000u) +#define SPRITE_SPEA0S0PS15_SPEA0S0PSX15_SHIFT (17u) +#define SPRITE_SPEA0S1DA0_SPEA0S1DA0 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA0_SPEA0S1DA0_SHIFT (0u) +#define SPRITE_SPEA0S1LY0_SPEA0S1LYH0 (0x000007FFu) +#define SPRITE_SPEA0S1LY0_SPEA0S1LYH0_SHIFT (0u) +#define SPRITE_SPEA0S1LY0_SPEA0S1LYW0 (0x07FE0000u) +#define SPRITE_SPEA0S1LY0_SPEA0S1LYW0_SHIFT (17u) +#define SPRITE_SPEA0S1PS0_SPEA0S1PSY0 (0x00001FFFu) +#define SPRITE_SPEA0S1PS0_SPEA0S1PSY0_SHIFT (0u) +#define SPRITE_SPEA0S1PS0_SPEA0S1PSX0 (0x07FE0000u) +#define SPRITE_SPEA0S1PS0_SPEA0S1PSX0_SHIFT (17u) +#define SPRITE_SPEA0S1DA1_SPEA0S1DA1 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA1_SPEA0S1DA1_SHIFT (0u) +#define SPRITE_SPEA0S1LY1_SPEA0S1LYH1 (0x000007FFu) +#define SPRITE_SPEA0S1LY1_SPEA0S1LYH1_SHIFT (0u) +#define SPRITE_SPEA0S1LY1_SPEA0S1LYW1 (0x07FE0000u) +#define SPRITE_SPEA0S1LY1_SPEA0S1LYW1_SHIFT (17u) +#define SPRITE_SPEA0S1PS1_SPEA0S1PSY1 (0x00001FFFu) +#define SPRITE_SPEA0S1PS1_SPEA0S1PSY1_SHIFT (0u) +#define SPRITE_SPEA0S1PS1_SPEA0S1PSX1 (0x07FE0000u) +#define SPRITE_SPEA0S1PS1_SPEA0S1PSX1_SHIFT (17u) +#define SPRITE_SPEA0S1DA2_SPEA0S1DA2 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA2_SPEA0S1DA2_SHIFT (0u) +#define SPRITE_SPEA0S1LY2_SPEA0S1LYH2 (0x000007FFu) +#define SPRITE_SPEA0S1LY2_SPEA0S1LYH2_SHIFT (0u) +#define SPRITE_SPEA0S1LY2_SPEA0S1LYW2 (0x07FE0000u) +#define SPRITE_SPEA0S1LY2_SPEA0S1LYW2_SHIFT (17u) +#define SPRITE_SPEA0S1PS2_SPEA0S1PSY2 (0x00001FFFu) +#define SPRITE_SPEA0S1PS2_SPEA0S1PSY2_SHIFT (0u) +#define SPRITE_SPEA0S1PS2_SPEA0S1PSX2 (0x07FE0000u) +#define SPRITE_SPEA0S1PS2_SPEA0S1PSX2_SHIFT (17u) +#define SPRITE_SPEA0S1DA3_SPEA0S1DA3 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA3_SPEA0S1DA3_SHIFT (0u) +#define SPRITE_SPEA0S1LY3_SPEA0S1LYH3 (0x000007FFu) +#define SPRITE_SPEA0S1LY3_SPEA0S1LYH3_SHIFT (0u) +#define SPRITE_SPEA0S1LY3_SPEA0S1LYW3 (0x07FE0000u) +#define SPRITE_SPEA0S1LY3_SPEA0S1LYW3_SHIFT (17u) +#define SPRITE_SPEA0S1PS3_SPEA0S1PSY3 (0x00001FFFu) +#define SPRITE_SPEA0S1PS3_SPEA0S1PSY3_SHIFT (0u) +#define SPRITE_SPEA0S1PS3_SPEA0S1PSX3 (0x07FE0000u) +#define SPRITE_SPEA0S1PS3_SPEA0S1PSX3_SHIFT (17u) +#define SPRITE_SPEA0S1DA4_SPEA0S1DA4 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA4_SPEA0S1DA4_SHIFT (0u) +#define SPRITE_SPEA0S1LY4_SPEA0S1LYH4 (0x000007FFu) +#define SPRITE_SPEA0S1LY4_SPEA0S1LYH4_SHIFT (0u) +#define SPRITE_SPEA0S1LY4_SPEA0S1LYW4 (0x07FE0000u) +#define SPRITE_SPEA0S1LY4_SPEA0S1LYW4_SHIFT (17u) +#define SPRITE_SPEA0S1PS4_SPEA0S1PSY4 (0x00001FFFu) +#define SPRITE_SPEA0S1PS4_SPEA0S1PSY4_SHIFT (0u) +#define SPRITE_SPEA0S1PS4_SPEA0S1PSX4 (0x07FE0000u) +#define SPRITE_SPEA0S1PS4_SPEA0S1PSX4_SHIFT (17u) +#define SPRITE_SPEA0S1DA5_SPEA0S1DA5 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA5_SPEA0S1DA5_SHIFT (0u) +#define SPRITE_SPEA0S1LY5_SPEA0S1LYH5 (0x000007FFu) +#define SPRITE_SPEA0S1LY5_SPEA0S1LYH5_SHIFT (0u) +#define SPRITE_SPEA0S1LY5_SPEA0S1LYW5 (0x07FE0000u) +#define SPRITE_SPEA0S1LY5_SPEA0S1LYW5_SHIFT (17u) +#define SPRITE_SPEA0S1PS5_SPEA0S1PSY5 (0x00001FFFu) +#define SPRITE_SPEA0S1PS5_SPEA0S1PSY5_SHIFT (0u) +#define SPRITE_SPEA0S1PS5_SPEA0S1PSX5 (0x07FE0000u) +#define SPRITE_SPEA0S1PS5_SPEA0S1PSX5_SHIFT (17u) +#define SPRITE_SPEA0S1DA6_SPEA0S1DA6 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA6_SPEA0S1DA6_SHIFT (0u) +#define SPRITE_SPEA0S1LY6_SPEA0S1LYH6 (0x000007FFu) +#define SPRITE_SPEA0S1LY6_SPEA0S1LYH6_SHIFT (0u) +#define SPRITE_SPEA0S1LY6_SPEA0S1LYW6 (0x07FE0000u) +#define SPRITE_SPEA0S1LY6_SPEA0S1LYW6_SHIFT (17u) +#define SPRITE_SPEA0S1PS6_SPEA0S1PSY6 (0x00001FFFu) +#define SPRITE_SPEA0S1PS6_SPEA0S1PSY6_SHIFT (0u) +#define SPRITE_SPEA0S1PS6_SPEA0S1PSX6 (0x07FE0000u) +#define SPRITE_SPEA0S1PS6_SPEA0S1PSX6_SHIFT (17u) +#define SPRITE_SPEA0S1DA7_SPEA0S1DA7 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA7_SPEA0S1DA7_SHIFT (0u) +#define SPRITE_SPEA0S1LY7_SPEA0S1LYH7 (0x000007FFu) +#define SPRITE_SPEA0S1LY7_SPEA0S1LYH7_SHIFT (0u) +#define SPRITE_SPEA0S1LY7_SPEA0S1LYW7 (0x07FE0000u) +#define SPRITE_SPEA0S1LY7_SPEA0S1LYW7_SHIFT (17u) +#define SPRITE_SPEA0S1PS7_SPEA0S1PSY7 (0x00001FFFu) +#define SPRITE_SPEA0S1PS7_SPEA0S1PSY7_SHIFT (0u) +#define SPRITE_SPEA0S1PS7_SPEA0S1PSX7 (0x07FE0000u) +#define SPRITE_SPEA0S1PS7_SPEA0S1PSX7_SHIFT (17u) +#define SPRITE_SPEA0S1DA8_SPEA0S1DA8 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA8_SPEA0S1DA8_SHIFT (0u) +#define SPRITE_SPEA0S1LY8_SPEA0S1LYH8 (0x000007FFu) +#define SPRITE_SPEA0S1LY8_SPEA0S1LYH8_SHIFT (0u) +#define SPRITE_SPEA0S1LY8_SPEA0S1LYW8 (0x07FE0000u) +#define SPRITE_SPEA0S1LY8_SPEA0S1LYW8_SHIFT (17u) +#define SPRITE_SPEA0S1PS8_SPEA0S1PSY8 (0x00001FFFu) +#define SPRITE_SPEA0S1PS8_SPEA0S1PSY8_SHIFT (0u) +#define SPRITE_SPEA0S1PS8_SPEA0S1PSX8 (0x07FE0000u) +#define SPRITE_SPEA0S1PS8_SPEA0S1PSX8_SHIFT (17u) +#define SPRITE_SPEA0S1DA9_SPEA0S1DA9 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA9_SPEA0S1DA9_SHIFT (0u) +#define SPRITE_SPEA0S1LY9_SPEA0S1LYH9 (0x000007FFu) +#define SPRITE_SPEA0S1LY9_SPEA0S1LYH9_SHIFT (0u) +#define SPRITE_SPEA0S1LY9_SPEA0S1LYW9 (0x07FE0000u) +#define SPRITE_SPEA0S1LY9_SPEA0S1LYW9_SHIFT (17u) +#define SPRITE_SPEA0S1PS9_SPEA0S1PSY9 (0x00001FFFu) +#define SPRITE_SPEA0S1PS9_SPEA0S1PSY9_SHIFT (0u) +#define SPRITE_SPEA0S1PS9_SPEA0S1PSX9 (0x07FE0000u) +#define SPRITE_SPEA0S1PS9_SPEA0S1PSX9_SHIFT (17u) +#define SPRITE_SPEA0S1DA10_SPEA0S1DA10 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA10_SPEA0S1DA10_SHIFT (0u) +#define SPRITE_SPEA0S1LY10_SPEA0S1LYH10 (0x000007FFu) +#define SPRITE_SPEA0S1LY10_SPEA0S1LYH10_SHIFT (0u) +#define SPRITE_SPEA0S1LY10_SPEA0S1LYW10 (0x07FE0000u) +#define SPRITE_SPEA0S1LY10_SPEA0S1LYW10_SHIFT (17u) +#define SPRITE_SPEA0S1PS10_SPEA0S1PSY10 (0x00001FFFu) +#define SPRITE_SPEA0S1PS10_SPEA0S1PSY10_SHIFT (0u) +#define SPRITE_SPEA0S1PS10_SPEA0S1PSX10 (0x07FE0000u) +#define SPRITE_SPEA0S1PS10_SPEA0S1PSX10_SHIFT (17u) +#define SPRITE_SPEA0S1DA11_SPEA0S1DA11 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA11_SPEA0S1DA11_SHIFT (0u) +#define SPRITE_SPEA0S1LY11_SPEA0S1LYH11 (0x000007FFu) +#define SPRITE_SPEA0S1LY11_SPEA0S1LYH11_SHIFT (0u) +#define SPRITE_SPEA0S1LY11_SPEA0S1LYW11 (0x07FE0000u) +#define SPRITE_SPEA0S1LY11_SPEA0S1LYW11_SHIFT (17u) +#define SPRITE_SPEA0S1PS11_SPEA0S1PSY11 (0x00001FFFu) +#define SPRITE_SPEA0S1PS11_SPEA0S1PSY11_SHIFT (0u) +#define SPRITE_SPEA0S1PS11_SPEA0S1PSX11 (0x07FE0000u) +#define SPRITE_SPEA0S1PS11_SPEA0S1PSX11_SHIFT (17u) +#define SPRITE_SPEA0S1DA12_SPEA0S1DA12 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA12_SPEA0S1DA12_SHIFT (0u) +#define SPRITE_SPEA0S1LY12_SPEA0S1LYH12 (0x000007FFu) +#define SPRITE_SPEA0S1LY12_SPEA0S1LYH12_SHIFT (0u) +#define SPRITE_SPEA0S1LY12_SPEA0S1LYW12 (0x07FE0000u) +#define SPRITE_SPEA0S1LY12_SPEA0S1LYW12_SHIFT (17u) +#define SPRITE_SPEA0S1PS12_SPEA0S1PSY12 (0x00001FFFu) +#define SPRITE_SPEA0S1PS12_SPEA0S1PSY12_SHIFT (0u) +#define SPRITE_SPEA0S1PS12_SPEA0S1PSX12 (0x07FE0000u) +#define SPRITE_SPEA0S1PS12_SPEA0S1PSX12_SHIFT (17u) +#define SPRITE_SPEA0S1DA13_SPEA0S1DA13 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA13_SPEA0S1DA13_SHIFT (0u) +#define SPRITE_SPEA0S1LY13_SPEA0S1LYH13 (0x000007FFu) +#define SPRITE_SPEA0S1LY13_SPEA0S1LYH13_SHIFT (0u) +#define SPRITE_SPEA0S1LY13_SPEA0S1LYW13 (0x07FE0000u) +#define SPRITE_SPEA0S1LY13_SPEA0S1LYW13_SHIFT (17u) +#define SPRITE_SPEA0S1PS13_SPEA0S1PSY13 (0x00001FFFu) +#define SPRITE_SPEA0S1PS13_SPEA0S1PSY13_SHIFT (0u) +#define SPRITE_SPEA0S1PS13_SPEA0S1PSX13 (0x07FE0000u) +#define SPRITE_SPEA0S1PS13_SPEA0S1PSX13_SHIFT (17u) +#define SPRITE_SPEA0S1DA14_SPEA0S1DA14 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA14_SPEA0S1DA14_SHIFT (0u) +#define SPRITE_SPEA0S1LY14_SPEA0S1LYH14 (0x000007FFu) +#define SPRITE_SPEA0S1LY14_SPEA0S1LYH14_SHIFT (0u) +#define SPRITE_SPEA0S1LY14_SPEA0S1LYW14 (0x07FE0000u) +#define SPRITE_SPEA0S1LY14_SPEA0S1LYW14_SHIFT (17u) +#define SPRITE_SPEA0S1PS14_SPEA0S1PSY14 (0x00001FFFu) +#define SPRITE_SPEA0S1PS14_SPEA0S1PSY14_SHIFT (0u) +#define SPRITE_SPEA0S1PS14_SPEA0S1PSX14 (0x07FE0000u) +#define SPRITE_SPEA0S1PS14_SPEA0S1PSX14_SHIFT (17u) +#define SPRITE_SPEA0S1DA15_SPEA0S1DA15 (0xFFFFFFFFu) +#define SPRITE_SPEA0S1DA15_SPEA0S1DA15_SHIFT (0u) +#define SPRITE_SPEA0S1LY15_SPEA0S1LYH15 (0x000007FFu) +#define SPRITE_SPEA0S1LY15_SPEA0S1LYH15_SHIFT (0u) +#define SPRITE_SPEA0S1LY15_SPEA0S1LYW15 (0x07FE0000u) +#define SPRITE_SPEA0S1LY15_SPEA0S1LYW15_SHIFT (17u) +#define SPRITE_SPEA0S1PS15_SPEA0S1PSY15 (0x00001FFFu) +#define SPRITE_SPEA0S1PS15_SPEA0S1PSY15_SHIFT (0u) +#define SPRITE_SPEA0S1PS15_SPEA0S1PSX15 (0x07FE0000u) +#define SPRITE_SPEA0S1PS15_SPEA0S1PSX15_SHIFT (17u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ssif_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ssif_iobitmask.h new file mode 100644 index 0000000..04b0c13 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/ssif_iobitmask.h @@ -0,0 +1,142 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef SSIF_IOBITMASK_H +#define SSIF_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define SSIF_SSICR_REN (0x00000001u) +#define SSIF_SSICR_REN_SHIFT (0u) +#define SSIF_SSICR_TEN (0x00000002u) +#define SSIF_SSICR_TEN_SHIFT (1u) +#define SSIF_SSICR_MUEN (0x00000008u) +#define SSIF_SSICR_MUEN_SHIFT (3u) +#define SSIF_SSICR_CKDV (0x000000F0u) +#define SSIF_SSICR_CKDV_SHIFT (4u) +#define SSIF_SSICR_DEL (0x00000100u) +#define SSIF_SSICR_DEL_SHIFT (8u) +#define SSIF_SSICR_PDTA (0x00000200u) +#define SSIF_SSICR_PDTA_SHIFT (9u) +#define SSIF_SSICR_SDTA (0x00000400u) +#define SSIF_SSICR_SDTA_SHIFT (10u) +#define SSIF_SSICR_SPDP (0x00000800u) +#define SSIF_SSICR_SPDP_SHIFT (11u) +#define SSIF_SSICR_LRCKP (0x00001000u) +#define SSIF_SSICR_LRCKP_SHIFT (12u) +#define SSIF_SSICR_BCKP (0x00002000u) +#define SSIF_SSICR_BCKP_SHIFT (13u) +#define SSIF_SSICR_MST (0x00004000u) +#define SSIF_SSICR_MST_SHIFT (14u) +#define SSIF_SSICR_SWL (0x00070000u) +#define SSIF_SSICR_SWL_SHIFT (16u) +#define SSIF_SSICR_DWL (0x00380000u) +#define SSIF_SSICR_DWL_SHIFT (19u) +#define SSIF_SSICR_FRM (0x00C00000u) +#define SSIF_SSICR_FRM_SHIFT (22u) +#define SSIF_SSICR_IIEN (0x02000000u) +#define SSIF_SSICR_IIEN_SHIFT (25u) +#define SSIF_SSICR_ROIEN (0x04000000u) +#define SSIF_SSICR_ROIEN_SHIFT (26u) +#define SSIF_SSICR_RUIEN (0x08000000u) +#define SSIF_SSICR_RUIEN_SHIFT (27u) +#define SSIF_SSICR_TOIEN (0x10000000u) +#define SSIF_SSICR_TOIEN_SHIFT (28u) +#define SSIF_SSICR_TUIEN (0x20000000u) +#define SSIF_SSICR_TUIEN_SHIFT (29u) +#define SSIF_SSICR_CKS (0x40000000u) +#define SSIF_SSICR_CKS_SHIFT (30u) +#define SSIF_SSISR_IIRQ (0x02000000u) +#define SSIF_SSISR_IIRQ_SHIFT (25u) +#define SSIF_SSISR_ROIRQ (0x04000000u) +#define SSIF_SSISR_ROIRQ_SHIFT (26u) +#define SSIF_SSISR_RUIRQ (0x08000000u) +#define SSIF_SSISR_RUIRQ_SHIFT (27u) +#define SSIF_SSISR_TOIRQ (0x10000000u) +#define SSIF_SSISR_TOIRQ_SHIFT (28u) +#define SSIF_SSISR_TUIRQ (0x20000000u) +#define SSIF_SSISR_TUIRQ_SHIFT (29u) +#define SSIF_SSIFCR_RFRST (0x00000001u) +#define SSIF_SSIFCR_RFRST_SHIFT (0u) +#define SSIF_SSIFCR_TFRST (0x00000002u) +#define SSIF_SSIFCR_TFRST_SHIFT (1u) +#define SSIF_SSIFCR_RIE (0x00000004u) +#define SSIF_SSIFCR_RIE_SHIFT (2u) +#define SSIF_SSIFCR_TIE (0x00000008u) +#define SSIF_SSIFCR_TIE_SHIFT (3u) +#define SSIF_SSIFCR_RXDNCE (0x00000100u) +#define SSIF_SSIFCR_RXDNCE_SHIFT (8u) +#define SSIF_SSIFCR_LRCKNCE (0x00000200u) +#define SSIF_SSIFCR_LRCKNCE_SHIFT (9u) +#define SSIF_SSIFCR_BCKNCE (0x00000400u) +#define SSIF_SSIFCR_BCKNCE_SHIFT (10u) +#define SSIF_SSIFCR_BSW (0x00000800u) +#define SSIF_SSIFCR_BSW_SHIFT (11u) +#define SSIF_SSIFCR_SSIRST (0x00010000u) +#define SSIF_SSIFCR_SSIRST_SHIFT (16u) +#define SSIF_SSIFCR_AUCKE (0x80000000u) +#define SSIF_SSIFCR_AUCKE_SHIFT (31u) +#define SSIF_SSIFSR_RDF (0x00000001u) +#define SSIF_SSIFSR_RDF_SHIFT (0u) +#define SSIF_SSIFSR_RDC (0x00003F00u) +#define SSIF_SSIFSR_RDC_SHIFT (8u) +#define SSIF_SSIFSR_TDE (0x00010000u) +#define SSIF_SSIFSR_TDE_SHIFT (16u) +#define SSIF_SSIFSR_TDC (0x3F000000u) +#define SSIF_SSIFSR_TDC_SHIFT (24u) +#define SSIF_SSIFTDR_SSIFTDR (0xFFFFFFFFu) +#define SSIF_SSIFTDR_SSIFTDR_SHIFT (0u) +#define SSIF_SSIFRDR_SSIFRDR (0xFFFFFFFFu) +#define SSIF_SSIFRDR_SSIFRDR_SHIFT (0u) +#define SSIF_SSIOFR_OMOD (0x00000003u) +#define SSIF_SSIOFR_OMOD_SHIFT (0u) +#define SSIF_SSIOFR_LRCONT (0x00000100u) +#define SSIF_SSIOFR_LRCONT_SHIFT (8u) +#define SSIF_SSIOFR_BCKASTP (0x00000200u) +#define SSIF_SSIOFR_BCKASTP_SHIFT (9u) +#define SSIF_SSISCR_RDFS (0x0000001Fu) +#define SSIF_SSISCR_RDFS_SHIFT (0u) +#define SSIF_SSISCR_TDES (0x00001F00u) +#define SSIF_SSISCR_TDES_SHIFT (8u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/usb_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/usb_iobitmask.h new file mode 100644 index 0000000..3495c4e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/usb_iobitmask.h @@ -0,0 +1,1388 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef USB_IOBITMASK_H +#define USB_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define USB_HCCONTROL_CBSR (0x00000003u) +#define USB_HCCONTROL_CBSR_SHIFT (0u) +#define USB_HCCONTROL_PLE (0x00000004u) +#define USB_HCCONTROL_PLE_SHIFT (2u) +#define USB_HCCONTROL_IE (0x00000008u) +#define USB_HCCONTROL_IE_SHIFT (3u) +#define USB_HCCONTROL_CLE (0x00000010u) +#define USB_HCCONTROL_CLE_SHIFT (4u) +#define USB_HCCONTROL_BLE (0x00000020u) +#define USB_HCCONTROL_BLE_SHIFT (5u) +#define USB_HCCONTROL_HCFS (0x000000C0u) +#define USB_HCCONTROL_HCFS_SHIFT (6u) +#define USB_HCCONTROL_RWC (0x00000200u) +#define USB_HCCONTROL_RWC_SHIFT (9u) +#define USB_HCCOMMANDSTATUS_HCR (0x00000001u) +#define USB_HCCOMMANDSTATUS_HCR_SHIFT (0u) +#define USB_HCCOMMANDSTATUS_CLF (0x00000002u) +#define USB_HCCOMMANDSTATUS_CLF_SHIFT (1u) +#define USB_HCCOMMANDSTATUS_BLF (0x00000004u) +#define USB_HCCOMMANDSTATUS_BLF_SHIFT (2u) +#define USB_HCCOMMANDSTATUS_SOC (0x00030000u) +#define USB_HCCOMMANDSTATUS_SOC_SHIFT (16u) +#define USB_HCINTERRUPTSTATUS_SO (0x00000001u) +#define USB_HCINTERRUPTSTATUS_SO_SHIFT (0u) +#define USB_HCINTERRUPTSTATUS_WDH (0x00000002u) +#define USB_HCINTERRUPTSTATUS_WDH_SHIFT (1u) +#define USB_HCINTERRUPTSTATUS_SF (0x00000004u) +#define USB_HCINTERRUPTSTATUS_SF_SHIFT (2u) +#define USB_HCINTERRUPTSTATUS_RD (0x00000008u) +#define USB_HCINTERRUPTSTATUS_RD_SHIFT (3u) +#define USB_HCINTERRUPTSTATUS_UE (0x00000010u) +#define USB_HCINTERRUPTSTATUS_UE_SHIFT (4u) +#define USB_HCINTERRUPTSTATUS_FNO (0x00000020u) +#define USB_HCINTERRUPTSTATUS_FNO_SHIFT (5u) +#define USB_HCINTERRUPTSTATUS_RHSC (0x00000040u) +#define USB_HCINTERRUPTSTATUS_RHSC_SHIFT (6u) +#define USB_HCINTERRUPTENABLE_SOE (0x00000001u) +#define USB_HCINTERRUPTENABLE_SOE_SHIFT (0u) +#define USB_HCINTERRUPTENABLE_WDHE (0x00000002u) +#define USB_HCINTERRUPTENABLE_WDHE_SHIFT (1u) +#define USB_HCINTERRUPTENABLE_SFE (0x00000004u) +#define USB_HCINTERRUPTENABLE_SFE_SHIFT (2u) +#define USB_HCINTERRUPTENABLE_RDE (0x00000008u) +#define USB_HCINTERRUPTENABLE_RDE_SHIFT (3u) +#define USB_HCINTERRUPTENABLE_UEE (0x00000010u) +#define USB_HCINTERRUPTENABLE_UEE_SHIFT (4u) +#define USB_HCINTERRUPTENABLE_FNOE (0x00000020u) +#define USB_HCINTERRUPTENABLE_FNOE_SHIFT (5u) +#define USB_HCINTERRUPTENABLE_RHSCE (0x00000040u) +#define USB_HCINTERRUPTENABLE_RHSCE_SHIFT (6u) +#define USB_HCINTERRUPTENABLE_OCE (0x40000000u) +#define USB_HCINTERRUPTENABLE_OCE_SHIFT (30u) +#define USB_HCINTERRUPTENABLE_MIE (0x80000000u) +#define USB_HCINTERRUPTENABLE_MIE_SHIFT (31u) +#define USB_HCINTERRUPTDISABLE_SOD (0x00000001u) +#define USB_HCINTERRUPTDISABLE_SOD_SHIFT (0u) +#define USB_HCINTERRUPTDISABLE_WDHD (0x00000002u) +#define USB_HCINTERRUPTDISABLE_WDHD_SHIFT (1u) +#define USB_HCINTERRUPTDISABLE_SFD (0x00000004u) +#define USB_HCINTERRUPTDISABLE_SFD_SHIFT (2u) +#define USB_HCINTERRUPTDISABLE_RDD (0x00000008u) +#define USB_HCINTERRUPTDISABLE_RDD_SHIFT (3u) +#define USB_HCINTERRUPTDISABLE_UED (0x00000010u) +#define USB_HCINTERRUPTDISABLE_UED_SHIFT (4u) +#define USB_HCINTERRUPTDISABLE_FNOD (0x00000020u) +#define USB_HCINTERRUPTDISABLE_FNOD_SHIFT (5u) +#define USB_HCINTERRUPTDISABLE_RHSCD (0x00000040u) +#define USB_HCINTERRUPTDISABLE_RHSCD_SHIFT (6u) +#define USB_HCINTERRUPTDISABLE_OCD (0x40000000u) +#define USB_HCINTERRUPTDISABLE_OCD_SHIFT (30u) +#define USB_HCINTERRUPTDISABLE_MID (0x80000000u) +#define USB_HCINTERRUPTDISABLE_MID_SHIFT (31u) +#define USB_HCHCCA_HcHCCA (0xFFFFFF00u) +#define USB_HCHCCA_HcHCCA_SHIFT (8u) +#define USB_HCPERIODCURRENTED_PECD (0xFFFFFFF0u) +#define USB_HCPERIODCURRENTED_PECD_SHIFT (4u) +#define USB_HCCONTROLHEADED_CHED (0xFFFFFFF0u) +#define USB_HCCONTROLHEADED_CHED_SHIFT (4u) +#define USB_HCCONTROLCURRENTED_CCED (0xFFFFFFF0u) +#define USB_HCCONTROLCURRENTED_CCED_SHIFT (4u) +#define USB_HCBULKHEADED_BHED (0xFFFFFFF0u) +#define USB_HCBULKHEADED_BHED_SHIFT (4u) +#define USB_HCBULKCURRENTED_BCED (0xFFFFFFF0u) +#define USB_HCBULKCURRENTED_BCED_SHIFT (4u) +#define USB_HCDONEHEAD_DH (0xFFFFFFF0u) +#define USB_HCDONEHEAD_DH_SHIFT (4u) +#define USB_HCFMINTERVAL_FI (0x00003FFFu) +#define USB_HCFMINTERVAL_FI_SHIFT (0u) +#define USB_HCFMINTERVAL_FSMPS (0x7FFF0000u) +#define USB_HCFMINTERVAL_FSMPS_SHIFT (16u) +#define USB_HCFMINTERVAL_FIT (0x80000000u) +#define USB_HCFMINTERVAL_FIT_SHIFT (31u) +#define USB_HCFMREMAINING_FR (0x00003FFFu) +#define USB_HCFMREMAINING_FR_SHIFT (0u) +#define USB_HCFMREMAINING_FRT (0x80000000u) +#define USB_HCFMREMAINING_FRT_SHIFT (31u) +#define USB_HCFMNUMBER_FN (0x0000FFFFu) +#define USB_HCFMNUMBER_FN_SHIFT (0u) +#define USB_HCPERIODICSTART_PS (0x00003FFFu) +#define USB_HCPERIODICSTART_PS_SHIFT (0u) +#define USB_HCLSTHRESHOLD_LST (0x00000FFFu) +#define USB_HCLSTHRESHOLD_LST_SHIFT (0u) +#define USB_HCRHDESCRIPTORA_NDP (0x000000FFu) +#define USB_HCRHDESCRIPTORA_NDP_SHIFT (0u) +#define USB_HCRHDESCRIPTORA_PSM (0x00000100u) +#define USB_HCRHDESCRIPTORA_PSM_SHIFT (8u) +#define USB_HCRHDESCRIPTORA_NPS (0x00000200u) +#define USB_HCRHDESCRIPTORA_NPS_SHIFT (9u) +#define USB_HCRHDESCRIPTORA_DT (0x00000400u) +#define USB_HCRHDESCRIPTORA_DT_SHIFT (10u) +#define USB_HCRHDESCRIPTORA_OCPM (0x00000800u) +#define USB_HCRHDESCRIPTORA_OCPM_SHIFT (11u) +#define USB_HCRHDESCRIPTORA_NOCP (0x00001000u) +#define USB_HCRHDESCRIPTORA_NOCP_SHIFT (12u) +#define USB_HCRHDESCRIPTORA_POTPGT (0xFF000000u) +#define USB_HCRHDESCRIPTORA_POTPGT_SHIFT (24u) +#define USB_HCRHDESCRIPTORB_DR (0x00000002u) +#define USB_HCRHDESCRIPTORB_DR_SHIFT (1u) +#define USB_HCRHDESCRIPTORB_PPCM (0x00020000u) +#define USB_HCRHDESCRIPTORB_PPCM_SHIFT (17u) +#define USB_HCRHSTATUS_LPS (0x00000001u) +#define USB_HCRHSTATUS_LPS_SHIFT (0u) +#define USB_HCRHSTATUS_OCI (0x00000002u) +#define USB_HCRHSTATUS_OCI_SHIFT (1u) +#define USB_HCRHSTATUS_DRWE (0x00008000u) +#define USB_HCRHSTATUS_DRWE_SHIFT (15u) +#define USB_HCRHSTATUS_LPSC (0x00010000u) +#define USB_HCRHSTATUS_LPSC_SHIFT (16u) +#define USB_HCRHSTATUS_OCIC (0x00020000u) +#define USB_HCRHSTATUS_OCIC_SHIFT (17u) +#define USB_HCRHSTATUS_CRWE (0x80000000u) +#define USB_HCRHSTATUS_CRWE_SHIFT (31u) +#define USB_HCRHPORTSTATUS1_CCS (0x00000001u) +#define USB_HCRHPORTSTATUS1_CCS_SHIFT (0u) +#define USB_HCRHPORTSTATUS1_PES (0x00000002u) +#define USB_HCRHPORTSTATUS1_PES_SHIFT (1u) +#define USB_HCRHPORTSTATUS1_PSS (0x00000004u) +#define USB_HCRHPORTSTATUS1_PSS_SHIFT (2u) +#define USB_HCRHPORTSTATUS1_POCI (0x00000008u) +#define USB_HCRHPORTSTATUS1_POCI_SHIFT (3u) +#define USB_HCRHPORTSTATUS1_PRS (0x00000010u) +#define USB_HCRHPORTSTATUS1_PRS_SHIFT (4u) +#define USB_HCRHPORTSTATUS1_PPS (0x00000100u) +#define USB_HCRHPORTSTATUS1_PPS_SHIFT (8u) +#define USB_HCRHPORTSTATUS1_LSDA (0x00000200u) +#define USB_HCRHPORTSTATUS1_LSDA_SHIFT (9u) +#define USB_HCRHPORTSTATUS1_CSC (0x00010000u) +#define USB_HCRHPORTSTATUS1_CSC_SHIFT (16u) +#define USB_HCRHPORTSTATUS1_PESC (0x00020000u) +#define USB_HCRHPORTSTATUS1_PESC_SHIFT (17u) +#define USB_HCRHPORTSTATUS1_PSSC (0x00040000u) +#define USB_HCRHPORTSTATUS1_PSSC_SHIFT (18u) +#define USB_HCRHPORTSTATUS1_OCIC (0x00080000u) +#define USB_HCRHPORTSTATUS1_OCIC_SHIFT (19u) +#define USB_HCRHPORTSTATUS1_PRSC (0x00100000u) +#define USB_HCRHPORTSTATUS1_PRSC_SHIFT (20u) +#define USB_CAPL_VERSION_CapabilityRegistersLength (0x000000FFu) +#define USB_CAPL_VERSION_CapabilityRegistersLength_SHIFT (0u) +#define USB_CAPL_VERSION_InterfaceVersionNumber (0xFFFF0000u) +#define USB_CAPL_VERSION_InterfaceVersionNumber_SHIFT (16u) +#define USB_HCSPARAMS_N_PORTS (0x0000000Fu) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0u) +#define USB_HCSPARAMS_PPC (0x00000010u) +#define USB_HCSPARAMS_PPC_SHIFT (4u) +#define USB_HCSPARAMS_PortRoutingRules (0x00000080u) +#define USB_HCSPARAMS_PortRoutingRules_SHIFT (7u) +#define USB_HCSPARAMS_N_PCC (0x00000F00u) +#define USB_HCSPARAMS_N_PCC_SHIFT (8u) +#define USB_HCSPARAMS_N_CC (0x0000F000u) +#define USB_HCSPARAMS_N_CC_SHIFT (12u) +#define USB_HCSPARAMS_P_INDICATOR (0x00010000u) +#define USB_HCSPARAMS_P_INDICATOR_SHIFT (16u) +#define USB_HCSPARAMS_DebugPortNumber (0x00F00000u) +#define USB_HCSPARAMS_DebugPortNumber_SHIFT (20u) +#define USB_HCCPARAMS_AddressingCapability (0x00000001u) +#define USB_HCCPARAMS_AddressingCapability_SHIFT (0u) +#define USB_HCCPARAMS_ProgramableFrameListFlag (0x00000002u) +#define USB_HCCPARAMS_ProgramableFrameListFlag_SHIFT (1u) +#define USB_HCCPARAMS_AsynchronousScheduleParkCapability (0x00000004u) +#define USB_HCCPARAMS_AsynchronousScheduleParkCapability_SHIFT (2u) +#define USB_HCCPARAMS_IsochronousSchedulingThreshold (0x000000F0u) +#define USB_HCCPARAMS_IsochronousSchedulingThreshold_SHIFT (4u) +#define USB_HCCPARAMS_EECP (0x0000FF00u) +#define USB_HCCPARAMS_EECP_SHIFT (8u) +#define USB_HCCPARAMS_HardwarePrefetch (0x00010000u) +#define USB_HCCPARAMS_HardwarePrefetch_SHIFT (16u) +#define USB_HCCPARAMS_LinkPowerManagementCapability (0x00020000u) +#define USB_HCCPARAMS_LinkPowerManagementCapability_SHIFT (17u) +#define USB_HCCPARAMS_PerPortChangeEventCapability (0x00040000u) +#define USB_HCCPARAMS_PerPortChangeEventCapability_SHIFT (18u) +#define USB_HCCPARAMS_FramePeriodicListCapability (0x00080000u) +#define USB_HCCPARAMS_FramePeriodicListCapability_SHIFT (19u) +#define USB_HCSP_PORTROUTE_CompanionPortRoute (0xFFFFFFFFu) +#define USB_HCSP_PORTROUTE_CompanionPortRoute_SHIFT (0u) +#define USB_USBCMD_RS (0x00000001u) +#define USB_USBCMD_RS_SHIFT (0u) +#define USB_USBCMD_HCRESET (0x00000002u) +#define USB_USBCMD_HCRESET_SHIFT (1u) +#define USB_USBCMD_FrameListSize (0x0000000Cu) +#define USB_USBCMD_FrameListSize_SHIFT (2u) +#define USB_USBCMD_PeriodicScheduleEnable (0x00000010u) +#define USB_USBCMD_PeriodicScheduleEnable_SHIFT (4u) +#define USB_USBCMD_AsynchronousScheduleEnable (0x00000020u) +#define USB_USBCMD_AsynchronousScheduleEnable_SHIFT (5u) +#define USB_USBCMD_InterruptonAsyncAdvanceDoorbell (0x00000040u) +#define USB_USBCMD_InterruptonAsyncAdvanceDoorbell_SHIFT (6u) +#define USB_USBCMD_AsynchronousScheduleParkModeCount (0x00000300u) +#define USB_USBCMD_AsynchronousScheduleParkModeCount_SHIFT (8u) +#define USB_USBCMD_AsynchronousScheduleParkModeEnable (0x00000800u) +#define USB_USBCMD_AsynchronousScheduleParkModeEnable_SHIFT (11u) +#define USB_USBCMD_PerPortChangeEventsEnable (0x00008000u) +#define USB_USBCMD_PerPortChangeEventsEnable_SHIFT (15u) +#define USB_USBCMD_InterruptThresholdControl (0x00FF0000u) +#define USB_USBCMD_InterruptThresholdControl_SHIFT (16u) +#define USB_USBCMD_HostInitiatedResumeDuration (0x0F000000u) +#define USB_USBCMD_HostInitiatedResumeDuration_SHIFT (24u) +#define USB_USBSTS_USBINT (0x00000001u) +#define USB_USBSTS_USBINT_SHIFT (0u) +#define USB_USBSTS_USBERRINT (0x00000002u) +#define USB_USBSTS_USBERRINT_SHIFT (1u) +#define USB_USBSTS_PortChangeDetect (0x00000004u) +#define USB_USBSTS_PortChangeDetect_SHIFT (2u) +#define USB_USBSTS_FrameListRollover (0x00000008u) +#define USB_USBSTS_FrameListRollover_SHIFT (3u) +#define USB_USBSTS_HostSystemError (0x00000010u) +#define USB_USBSTS_HostSystemError_SHIFT (4u) +#define USB_USBSTS_InterruptonAsyncAdvance (0x00000020u) +#define USB_USBSTS_InterruptonAsyncAdvance_SHIFT (5u) +#define USB_USBSTS_HCHalted (0x00001000u) +#define USB_USBSTS_HCHalted_SHIFT (12u) +#define USB_USBSTS_Reclamation (0x00002000u) +#define USB_USBSTS_Reclamation_SHIFT (13u) +#define USB_USBSTS_PeriodicScheduleStatus (0x00004000u) +#define USB_USBSTS_PeriodicScheduleStatus_SHIFT (14u) +#define USB_USBSTS_AsynchronousScheduleStatus (0x00008000u) +#define USB_USBSTS_AsynchronousScheduleStatus_SHIFT (15u) +#define USB_USBSTS_Port1ChangeDetect (0x00010000u) +#define USB_USBSTS_Port1ChangeDetect_SHIFT (16u) +#define USB_USBINTR_USBInterruptEnable (0x00000001u) +#define USB_USBINTR_USBInterruptEnable_SHIFT (0u) +#define USB_USBINTR_USBErrorInterruptEnable (0x00000002u) +#define USB_USBINTR_USBErrorInterruptEnable_SHIFT (1u) +#define USB_USBINTR_PortChangeDetectEnable (0x00000004u) +#define USB_USBINTR_PortChangeDetectEnable_SHIFT (2u) +#define USB_USBINTR_FrameListRolloverEnable (0x00000008u) +#define USB_USBINTR_FrameListRolloverEnable_SHIFT (3u) +#define USB_USBINTR_HostSystemErrorEnable (0x00000010u) +#define USB_USBINTR_HostSystemErrorEnable_SHIFT (4u) +#define USB_USBINTR_InterruptonAsyncAdvanceEnable (0x00000020u) +#define USB_USBINTR_InterruptonAsyncAdvanceEnable_SHIFT (5u) +#define USB_USBINTR_Port1ChangeEventEnable (0x00010000u) +#define USB_USBINTR_Port1ChangeEventEnable_SHIFT (16u) +#define USB_FRINDEX_FrameIndex (0x00003FFFu) +#define USB_FRINDEX_FrameIndex_SHIFT (0u) +#define USB_CTRLDSSEGMENT_CTRLDSSEGMENT (0xFFFFFFFFu) +#define USB_CTRLDSSEGMENT_CTRLDSSEGMENT_SHIFT (0u) +#define USB_PERIODICLISTBASE_BaseAddress (0xFFFFF000u) +#define USB_PERIODICLISTBASE_BaseAddress_SHIFT (12u) +#define USB_ASYNCLISTADDR_LPL (0xFFFFFFE0u) +#define USB_ASYNCLISTADDR_LPL_SHIFT (5u) +#define USB_CONFIGFLAG_CF (0x00000001u) +#define USB_CONFIGFLAG_CF_SHIFT (0u) +#define USB_PORTSC1_CurrentConnectStatus (0x00000001u) +#define USB_PORTSC1_CurrentConnectStatus_SHIFT (0u) +#define USB_PORTSC1_ConnectStatusChange (0x00000002u) +#define USB_PORTSC1_ConnectStatusChange_SHIFT (1u) +#define USB_PORTSC1_PortEnabled_Disabled (0x00000004u) +#define USB_PORTSC1_PortEnabled_Disabled_SHIFT (2u) +#define USB_PORTSC1_PortEnable_DisableChange (0x00000008u) +#define USB_PORTSC1_PortEnable_DisableChange_SHIFT (3u) +#define USB_PORTSC1_OvercurrentActive (0x00000010u) +#define USB_PORTSC1_OvercurrentActive_SHIFT (4u) +#define USB_PORTSC1_OvercurrentChange (0x00000020u) +#define USB_PORTSC1_OvercurrentChange_SHIFT (5u) +#define USB_PORTSC1_ForcePortResume (0x00000040u) +#define USB_PORTSC1_ForcePortResume_SHIFT (6u) +#define USB_PORTSC1_Suspend (0x00000080u) +#define USB_PORTSC1_Suspend_SHIFT (7u) +#define USB_PORTSC1_PortReset (0x00000100u) +#define USB_PORTSC1_PortReset_SHIFT (8u) +#define USB_PORTSC1_SuspendusingL1 (0x00000200u) +#define USB_PORTSC1_SuspendusingL1_SHIFT (9u) +#define USB_PORTSC1_LineStatus (0x00000C00u) +#define USB_PORTSC1_LineStatus_SHIFT (10u) +#define USB_PORTSC1_PP (0x00001000u) +#define USB_PORTSC1_PP_SHIFT (12u) +#define USB_PORTSC1_PortOwner (0x00002000u) +#define USB_PORTSC1_PortOwner_SHIFT (13u) +#define USB_PORTSC1_PortTestControl (0x000F0000u) +#define USB_PORTSC1_PortTestControl_SHIFT (16u) +#define USB_PORTSC1_WKCNNT_E (0x00100000u) +#define USB_PORTSC1_WKCNNT_E_SHIFT (20u) +#define USB_PORTSC1_WKDSCNNT_E (0x00200000u) +#define USB_PORTSC1_WKDSCNNT_E_SHIFT (21u) +#define USB_PORTSC1_WKOC_E (0x00400000u) +#define USB_PORTSC1_WKOC_E_SHIFT (22u) +#define USB_PORTSC1_SuspendStatus (0x01800000u) +#define USB_PORTSC1_SuspendStatus_SHIFT (23u) +#define USB_PORTSC1_DeviceAddress (0xFE000000u) +#define USB_PORTSC1_DeviceAddress_SHIFT (25u) +#define USB_INT_ENABLE_AHB_INTEN (0x00000001u) +#define USB_INT_ENABLE_AHB_INTEN_SHIFT (0u) +#define USB_INT_ENABLE_USBH_INTAEN (0x00000002u) +#define USB_INT_ENABLE_USBH_INTAEN_SHIFT (1u) +#define USB_INT_ENABLE_USBH_INTBEN (0x00000004u) +#define USB_INT_ENABLE_USBH_INTBEN_SHIFT (2u) +#define USB_INT_ENABLE_UCOM_INTEN (0x00000008u) +#define USB_INT_ENABLE_UCOM_INTEN_SHIFT (3u) +#define USB_INT_ENABLE_WAKEON_INTEN (0x00000010u) +#define USB_INT_ENABLE_WAKEON_INTEN_SHIFT (4u) +#define USB_INT_STATUS_AHB_INT (0x00000001u) +#define USB_INT_STATUS_AHB_INT_SHIFT (0u) +#define USB_INT_STATUS_USBH_INTA (0x00000002u) +#define USB_INT_STATUS_USBH_INTA_SHIFT (1u) +#define USB_INT_STATUS_USBH_INTB (0x00000004u) +#define USB_INT_STATUS_USBH_INTB_SHIFT (2u) +#define USB_INT_STATUS_UCOM_INT (0x00000008u) +#define USB_INT_STATUS_UCOM_INT_SHIFT (3u) +#define USB_INT_STATUS_WAKEON_INT (0x00000010u) +#define USB_INT_STATUS_WAKEON_INT_SHIFT (4u) +#define USB_AHB_BUS_CTR_MAX_BURST_LEN (0x00000003u) +#define USB_AHB_BUS_CTR_MAX_BURST_LEN_SHIFT (0u) +#define USB_AHB_BUS_CTR_ALIGN_ADDRESS (0x00000030u) +#define USB_AHB_BUS_CTR_ALIGN_ADDRESS_SHIFT (4u) +#define USB_AHB_BUS_CTR_PROT_MODE (0x00000100u) +#define USB_AHB_BUS_CTR_PROT_MODE_SHIFT (8u) +#define USB_AHB_BUS_CTR_PROT_TYPE (0x0000F000u) +#define USB_AHB_BUS_CTR_PROT_TYPE_SHIFT (12u) +#define USB_USBCTR_USBH_RST (0x00000001u) +#define USB_USBCTR_USBH_RST_SHIFT (0u) +#define USB_USBCTR_PLL_RST (0x00000002u) +#define USB_USBCTR_PLL_RST_SHIFT (1u) +#define USB_USBCTR_DIRPD (0x00000004u) +#define USB_USBCTR_DIRPD_SHIFT (2u) +#define USB_REGEN_CG_CTRL_RPB_WEN (0x01000000u) +#define USB_REGEN_CG_CTRL_RPB_WEN_SHIFT (24u) +#define USB_REGEN_CG_CTRL_PERI_CLK_MSK (0x10000000u) +#define USB_REGEN_CG_CTRL_PERI_CLK_MSK_SHIFT (28u) +#define USB_REGEN_CG_CTRL_HOST_CLK_MSK (0x20000000u) +#define USB_REGEN_CG_CTRL_HOST_CLK_MSK_SHIFT (29u) +#define USB_REGEN_CG_CTRL_NONUSE_CLK_MSK (0x80000000u) +#define USB_REGEN_CG_CTRL_NONUSE_CLK_MSK_SHIFT (31u) +#define USB_SPD_CTRL_GLOBAL_SUSPENDM_P1 (0x00000001u) +#define USB_SPD_CTRL_GLOBAL_SUSPENDM_P1_SHIFT (0u) +#define USB_SPD_CTRL_WKCNNT_ENABLE (0x00800000u) +#define USB_SPD_CTRL_WKCNNT_ENABLE_SHIFT (23u) +#define USB_SPD_CTRL_SLEEPM_ENABLE (0x40000000u) +#define USB_SPD_CTRL_SLEEPM_ENABLE_SHIFT (30u) +#define USB_SPD_CTRL_SUSPENDM_ENABLE (0x80000000u) +#define USB_SPD_CTRL_SUSPENDM_ENABLE_SHIFT (31u) +#define USB_SPD_RSM_TIMSET_TIMER_RESUME (0x0000FFFFu) +#define USB_SPD_RSM_TIMSET_TIMER_RESUME_SHIFT (0u) +#define USB_SPD_RSM_TIMSET_TIMER_CONNECT (0xFFFF0000u) +#define USB_SPD_RSM_TIMSET_TIMER_CONNECT_SHIFT (16u) +#define USB_OC_SLP_TIMSET_TIMER_OC (0x000FFFFFu) +#define USB_OC_SLP_TIMSET_TIMER_OC_SHIFT (0u) +#define USB_OC_SLP_TIMSET_TIMER_SLEEP (0x1FF00000u) +#define USB_OC_SLP_TIMSET_TIMER_SLEEP_SHIFT (20u) +#define USB_SBRN_FLADJ_PW_SBRN (0x000000FFu) +#define USB_SBRN_FLADJ_PW_SBRN_SHIFT (0u) +#define USB_SBRN_FLADJ_PW_FLADJ (0x0000FF00u) +#define USB_SBRN_FLADJ_PW_FLADJ_SHIFT (8u) +#define USB_SBRN_FLADJ_PW_PORTWAKECAP (0xFFFF0000u) +#define USB_SBRN_FLADJ_PW_PORTWAKECAP_SHIFT (16u) +#define USB_PORT_LPM_CTRL1_HIRD_SEL_P1 (0x00000001u) +#define USB_PORT_LPM_CTRL1_HIRD_SEL_P1_SHIFT (0u) +#define USB_PORT_LPM_CTRL1_RETRY_ENABLE_NYET_P1 (0x00000002u) +#define USB_PORT_LPM_CTRL1_RETRY_ENABLE_NYET_P1_SHIFT (1u) +#define USB_PORT_LPM_CTRL1_SLEEP_INT_EN_P1 (0x00000004u) +#define USB_PORT_LPM_CTRL1_SLEEP_INT_EN_P1_SHIFT (2u) +#define USB_PORT_LPM_CTRL1_REMOTEWAKE_EN_P1 (0x00000008u) +#define USB_PORT_LPM_CTRL1_REMOTEWAKE_EN_P1_SHIFT (3u) +#define USB_PORT_LPM_CTRL1_NYET_RETRY_CNT_P1 (0x000000F0u) +#define USB_PORT_LPM_CTRL1_NYET_RETRY_CNT_P1_SHIFT (4u) +#define USB_U2HC_EXT2_DUR_CTRL (0x00000200u) +#define USB_U2HC_EXT2_DUR_CTRL_SHIFT (9u) +#define USB_COMMCTRL_OTG_PERI (0x80000000u) +#define USB_COMMCTRL_OTG_PERI_SHIFT (31u) +#define USB_OBINTSTA_IDCHG_STA (0x00000001u) +#define USB_OBINTSTA_IDCHG_STA_SHIFT (0u) +#define USB_OBINTSTA_OCINT_STA (0x00000002u) +#define USB_OBINTSTA_OCINT_STA_SHIFT (1u) +#define USB_OBINTSTA_VBSTACHG_STA (0x00000004u) +#define USB_OBINTSTA_VBSTACHG_STA_SHIFT (2u) +#define USB_OBINTSTA_VBSTAINT_STA (0x00000008u) +#define USB_OBINTSTA_VBSTAINT_STA_SHIFT (3u) +#define USB_OBINTSTA_PDDETCHG1_STA (0x00000010u) +#define USB_OBINTSTA_PDDETCHG1_STA_SHIFT (4u) +#define USB_OBINTSTA_CHGDETCHG1_STA (0x00000040u) +#define USB_OBINTSTA_CHGDETCHG1_STA_SHIFT (6u) +#define USB_OBINTSTA_DMMONCHG_STA (0x00010000u) +#define USB_OBINTSTA_DMMONCHG_STA_SHIFT (16u) +#define USB_OBINTSTA_DPMONCHG_STA (0x00020000u) +#define USB_OBINTSTA_DPMONCHG_STA_SHIFT (17u) +#define USB_OBINTEN_IDCHG_EN (0x00000001u) +#define USB_OBINTEN_IDCHG_EN_SHIFT (0u) +#define USB_OBINTEN_OCINT_EN (0x00000002u) +#define USB_OBINTEN_OCINT_EN_SHIFT (1u) +#define USB_OBINTEN_VBSTACHG_EN (0x00000004u) +#define USB_OBINTEN_VBSTACHG_EN_SHIFT (2u) +#define USB_OBINTEN_VBSTAINT_EN (0x00000008u) +#define USB_OBINTEN_VBSTAINT_EN_SHIFT (3u) +#define USB_OBINTEN_PDDETCHG1_EN (0x00000010u) +#define USB_OBINTEN_PDDETCHG1_EN_SHIFT (4u) +#define USB_OBINTEN_CHGDETCHG1_EN (0x00000040u) +#define USB_OBINTEN_CHGDETCHG1_EN_SHIFT (6u) +#define USB_OBINTEN_DMMONCHG_EN (0x00010000u) +#define USB_OBINTEN_DMMONCHG_EN_SHIFT (16u) +#define USB_OBINTEN_DPMONCHG_EN (0x00020000u) +#define USB_OBINTEN_DPMONCHG_EN_SHIFT (17u) +#define USB_VBCTRL_VBOUT (0x00000001u) +#define USB_VBCTRL_VBOUT_SHIFT (0u) +#define USB_VBCTRL_VGPUO (0x00000010u) +#define USB_VBCTRL_VGPUO_SHIFT (4u) +#define USB_VBCTRL_VBLVL (0x00200000u) +#define USB_VBCTRL_VBLVL_SHIFT (21u) +#define USB_VBCTRL_VBSTA (0x20000000u) +#define USB_VBCTRL_VBSTA_SHIFT (29u) +#define USB_LINECTRL1_IDMON (0x00000001u) +#define USB_LINECTRL1_IDMON_SHIFT (0u) +#define USB_LINECTRL1_DMMON (0x00000004u) +#define USB_LINECTRL1_DMMON_SHIFT (2u) +#define USB_LINECTRL1_DPMON (0x00000008u) +#define USB_LINECTRL1_DPMON_SHIFT (3u) +#define USB_LINECTRL1_DM_RPD (0x00010000u) +#define USB_LINECTRL1_DM_RPD_SHIFT (16u) +#define USB_LINECTRL1_DMRPD_EN (0x00020000u) +#define USB_LINECTRL1_DMRPD_EN_SHIFT (17u) +#define USB_LINECTRL1_DP_RPD (0x00040000u) +#define USB_LINECTRL1_DP_RPD_SHIFT (18u) +#define USB_LINECTRL1_DPRPD_EN (0x00080000u) +#define USB_LINECTRL1_DPRPD_EN_SHIFT (19u) +#define USB_LINECTRL1_DSDP (0x00300000u) +#define USB_LINECTRL1_DSDP_SHIFT (20u) +#define USB_BCCTRL1_IDPSRCE (0x00000001u) +#define USB_BCCTRL1_IDPSRCE_SHIFT (0u) +#define USB_BCCTRL1_IDMSINKE (0x00000002u) +#define USB_BCCTRL1_IDMSINKE_SHIFT (1u) +#define USB_BCCTRL1_VDPSRCE (0x00000004u) +#define USB_BCCTRL1_VDPSRCE_SHIFT (2u) +#define USB_BCCTRL1_IDPSINKE (0x00000008u) +#define USB_BCCTRL1_IDPSINKE_SHIFT (3u) +#define USB_BCCTRL1_VDMSRCE (0x00000010u) +#define USB_BCCTRL1_VDMSRCE_SHIFT (4u) +#define USB_BCCTRL1_DCPMODE (0x00000020u) +#define USB_BCCTRL1_DCPMODE_SHIFT (5u) +#define USB_BCCTRL1_CHGDETSTS (0x00000100u) +#define USB_BCCTRL1_CHGDETSTS_SHIFT (8u) +#define USB_BCCTRL1_PDDETSTS (0x00000200u) +#define USB_BCCTRL1_PDDETSTS_SHIFT (9u) +#define USB_CC_STATUS_CC2_RA (0x00000001u) +#define USB_CC_STATUS_CC2_RA_SHIFT (0u) +#define USB_CC_STATUS_CC2_RD (0x00000002u) +#define USB_CC_STATUS_CC2_RD_SHIFT (1u) +#define USB_CC_STATUS_CC1_RA (0x00000004u) +#define USB_CC_STATUS_CC1_RA_SHIFT (2u) +#define USB_CC_STATUS_CC1_RD (0x00000008u) +#define USB_CC_STATUS_CC1_RD_SHIFT (3u) +#define USB_CC_STATUS_CC_LVL_STA (0x00000010u) +#define USB_CC_STATUS_CC_LVL_STA_SHIFT (4u) +#define USB_CC_STATUS_CC_PERI_STA (0x00000020u) +#define USB_CC_STATUS_CC_PERI_STA_SHIFT (5u) +#define USB_CC_STATUS_CC_LVL_EN (0x01000000u) +#define USB_CC_STATUS_CC_LVL_EN_SHIFT (24u) +#define USB_CC_STATUS_CC_LVL (0x1E000000u) +#define USB_CC_STATUS_CC_LVL_SHIFT (25u) +#define USB_CC_STATUS_CC_LVL_CLR (0x20000000u) +#define USB_CC_STATUS_CC_LVL_CLR_SHIFT (29u) +#define USB_CC_STATUS_CC_INT_SEL (0x80000000u) +#define USB_CC_STATUS_CC_INT_SEL_SHIFT (31u) +#define USB_PHYCLK_CTRL_UCLKSEL (0x00000001u) +#define USB_PHYCLK_CTRL_UCLKSEL_SHIFT (0u) +#define USB_PHYIF_CTRL_FIXPHY (0x00000001u) +#define USB_PHYIF_CTRL_FIXPHY_SHIFT (0u) +#define USB_SYSCFG0_USBE (0x0001u) +#define USB_SYSCFG0_USBE_SHIFT (0u) +#define USB_SYSCFG0_DPRPU (0x0010u) +#define USB_SYSCFG0_DPRPU_SHIFT (4u) +#define USB_SYSCFG0_DRPD (0x0020u) +#define USB_SYSCFG0_DRPD_SHIFT (5u) +#define USB_SYSCFG0_HSE (0x0080u) +#define USB_SYSCFG0_HSE_SHIFT (7u) +#define USB_SYSCFG0_CNEN (0x0100u) +#define USB_SYSCFG0_CNEN_SHIFT (8u) +#define USB_SYSCFG1_BWAIT (0x003Fu) +#define USB_SYSCFG1_BWAIT_SHIFT (0u) +#define USB_SYSSTS0_LNST (0x0003u) +#define USB_SYSSTS0_LNST_SHIFT (0u) +#define USB_DVSTCTR0_RHST (0x0007u) +#define USB_DVSTCTR0_RHST_SHIFT (0u) +#define USB_DVSTCTR0_WKUP (0x0100u) +#define USB_DVSTCTR0_WKUP_SHIFT (8u) +#define USB_DVSTCTR0_BRST1 (0x8000u) +#define USB_DVSTCTR0_BRST1_SHIFT (15u) +#define USB_TESTMODE_UTST (0x000Fu) +#define USB_TESTMODE_UTST_SHIFT (0u) +#define USB_TESTMODE_BRST3 (0x0800u) +#define USB_TESTMODE_BRST3_SHIFT (11u) +#define USB_TESTMODE_BRST2 (0x4000u) +#define USB_TESTMODE_BRST2_SHIFT (14u) +#define USB_CFIFO_FIFOPORT (0xFFFFFFFFu) +#define USB_CFIFO_FIFOPORT_SHIFT (0u) +#define USB_CFIFOSEL_CURPIPE (0x000Fu) +#define USB_CFIFOSEL_CURPIPE_SHIFT (0u) +#define USB_CFIFOSEL_ISEL (0x0020u) +#define USB_CFIFOSEL_ISEL_SHIFT (5u) +#define USB_CFIFOSEL_BIGEND (0x0100u) +#define USB_CFIFOSEL_BIGEND_SHIFT (8u) +#define USB_CFIFOSEL_MBW (0x0C00u) +#define USB_CFIFOSEL_MBW_SHIFT (10u) +#define USB_CFIFOSEL_REW (0x4000u) +#define USB_CFIFOSEL_REW_SHIFT (14u) +#define USB_CFIFOSEL_RCNT (0x8000u) +#define USB_CFIFOSEL_RCNT_SHIFT (15u) +#define USB_CFIFOCTR_DTLN (0x0FFFu) +#define USB_CFIFOCTR_DTLN_SHIFT (0u) +#define USB_CFIFOCTR_FRDY (0x2000u) +#define USB_CFIFOCTR_FRDY_SHIFT (13u) +#define USB_CFIFOCTR_BCLR (0x4000u) +#define USB_CFIFOCTR_BCLR_SHIFT (14u) +#define USB_CFIFOCTR_BVAL (0x8000u) +#define USB_CFIFOCTR_BVAL_SHIFT (15u) +#define USB_D0FIFOSEL_CURPIPE (0x000Fu) +#define USB_D0FIFOSEL_CURPIPE_SHIFT (0u) +#define USB_D0FIFOSEL_MBW (0x0C00u) +#define USB_D0FIFOSEL_MBW_SHIFT (10u) +#define USB_D0FIFOSEL_DREQE (0x1000u) +#define USB_D0FIFOSEL_DREQE_SHIFT (12u) +#define USB_D0FIFOSEL_DCLRM (0x2000u) +#define USB_D0FIFOSEL_DCLRM_SHIFT (13u) +#define USB_D0FIFOSEL_REW (0x4000u) +#define USB_D0FIFOSEL_REW_SHIFT (14u) +#define USB_D0FIFOSEL_RCNT (0x8000u) +#define USB_D0FIFOSEL_RCNT_SHIFT (15u) +#define USB_D0FIFOCTR_DTLN (0x0FFFu) +#define USB_D0FIFOCTR_DTLN_SHIFT (0u) +#define USB_D0FIFOCTR_FRDY (0x2000u) +#define USB_D0FIFOCTR_FRDY_SHIFT (13u) +#define USB_D0FIFOCTR_BCLR (0x4000u) +#define USB_D0FIFOCTR_BCLR_SHIFT (14u) +#define USB_D0FIFOCTR_BVAL (0x8000u) +#define USB_D0FIFOCTR_BVAL_SHIFT (15u) +#define USB_D1FIFOSEL_CURPIPE (0x000Fu) +#define USB_D1FIFOSEL_CURPIPE_SHIFT (0u) +#define USB_D1FIFOSEL_MBW (0x0C00u) +#define USB_D1FIFOSEL_MBW_SHIFT (10u) +#define USB_D1FIFOSEL_DREQE (0x1000u) +#define USB_D1FIFOSEL_DREQE_SHIFT (12u) +#define USB_D1FIFOSEL_DCLRM (0x2000u) +#define USB_D1FIFOSEL_DCLRM_SHIFT (13u) +#define USB_D1FIFOSEL_REW (0x4000u) +#define USB_D1FIFOSEL_REW_SHIFT (14u) +#define USB_D1FIFOSEL_RCNT (0x8000u) +#define USB_D1FIFOSEL_RCNT_SHIFT (15u) +#define USB_D1FIFOCTR_DTLN (0x0FFFu) +#define USB_D1FIFOCTR_DTLN_SHIFT (0u) +#define USB_D1FIFOCTR_FRDY (0x2000u) +#define USB_D1FIFOCTR_FRDY_SHIFT (13u) +#define USB_D1FIFOCTR_BCLR (0x4000u) +#define USB_D1FIFOCTR_BCLR_SHIFT (14u) +#define USB_D1FIFOCTR_BVAL (0x8000u) +#define USB_D1FIFOCTR_BVAL_SHIFT (15u) +#define USB_INTENB0_BRDYE (0x0100u) +#define USB_INTENB0_BRDYE_SHIFT (8u) +#define USB_INTENB0_NRDYE (0x0200u) +#define USB_INTENB0_NRDYE_SHIFT (9u) +#define USB_INTENB0_BEMPE (0x0400u) +#define USB_INTENB0_BEMPE_SHIFT (10u) +#define USB_INTENB0_CTRE (0x0800u) +#define USB_INTENB0_CTRE_SHIFT (11u) +#define USB_INTENB0_DVSE (0x1000u) +#define USB_INTENB0_DVSE_SHIFT (12u) +#define USB_INTENB0_SOFE (0x2000u) +#define USB_INTENB0_SOFE_SHIFT (13u) +#define USB_INTENB0_RSME (0x4000u) +#define USB_INTENB0_RSME_SHIFT (14u) +#define USB_INTENB0_VBSE (0x8000u) +#define USB_INTENB0_VBSE_SHIFT (15u) +#define USB_BRDYENB_PIPEBRDYE (0xFFFFu) +#define USB_BRDYENB_PIPEBRDYE_SHIFT (0u) +#define USB_NRDYENB_PIPENRDYE (0xFFFFu) +#define USB_NRDYENB_PIPENRDYE_SHIFT (0u) +#define USB_BEMPENB_PIPEBEMPE (0xFFFFu) +#define USB_BEMPENB_PIPEBEMPE_SHIFT (0u) +#define USB_SOFCFG_SOFM (0x000Cu) +#define USB_SOFCFG_SOFM_SHIFT (2u) +#define USB_SOFCFG_BRDYM (0x0040u) +#define USB_SOFCFG_BRDYM_SHIFT (6u) +#define USB_INTSTS0_CTSQ (0x0007u) +#define USB_INTSTS0_CTSQ_SHIFT (0u) +#define USB_INTSTS0_VALID (0x0008u) +#define USB_INTSTS0_VALID_SHIFT (3u) +#define USB_INTSTS0_DVSQ (0x0070u) +#define USB_INTSTS0_DVSQ_SHIFT (4u) +#define USB_INTSTS0_VBSTS (0x0080u) +#define USB_INTSTS0_VBSTS_SHIFT (7u) +#define USB_INTSTS0_BRDY (0x0100u) +#define USB_INTSTS0_BRDY_SHIFT (8u) +#define USB_INTSTS0_NRDY (0x0200u) +#define USB_INTSTS0_NRDY_SHIFT (9u) +#define USB_INTSTS0_BEMP (0x0400u) +#define USB_INTSTS0_BEMP_SHIFT (10u) +#define USB_INTSTS0_CTRT (0x0800u) +#define USB_INTSTS0_CTRT_SHIFT (11u) +#define USB_INTSTS0_DVST (0x1000u) +#define USB_INTSTS0_DVST_SHIFT (12u) +#define USB_INTSTS0_SOFR (0x2000u) +#define USB_INTSTS0_SOFR_SHIFT (13u) +#define USB_INTSTS0_RESM (0x4000u) +#define USB_INTSTS0_RESM_SHIFT (14u) +#define USB_INTSTS0_VBINT (0x8000u) +#define USB_INTSTS0_VBINT_SHIFT (15u) +#define USB_BRDYSTS_PIPEBRDY (0xFFFFu) +#define USB_BRDYSTS_PIPEBRDY_SHIFT (0u) +#define USB_NRDYSTS_PIPENRDY (0xFFFFu) +#define USB_NRDYSTS_PIPENRDY_SHIFT (0u) +#define USB_BEMPSTS_PIPEBEMP (0xFFFFu) +#define USB_BEMPSTS_PIPEBEMP_SHIFT (0u) +#define USB_FRMNUM_FRNM (0x07FFu) +#define USB_FRMNUM_FRNM_SHIFT (0u) +#define USB_FRMNUM_CRCE (0x4000u) +#define USB_FRMNUM_CRCE_SHIFT (14u) +#define USB_FRMNUM_OVRN (0x8000u) +#define USB_FRMNUM_OVRN_SHIFT (15u) +#define USB_UFRMNUM_UFRNM (0x0007u) +#define USB_UFRMNUM_UFRNM_SHIFT (0u) +#define USB_UFRMNUM_DVCHG (0x8000u) +#define USB_UFRMNUM_DVCHG_SHIFT (15u) +#define USB_USBADDR_USBADDR (0x007Fu) +#define USB_USBADDR_USBADDR_SHIFT (0u) +#define USB_USBADDR_STSRECOV0 (0x0700u) +#define USB_USBADDR_STSRECOV0_SHIFT (8u) +#define USB_USBREQ_bmRequestType (0x00FFu) +#define USB_USBREQ_bmRequestType_SHIFT (0u) +#define USB_USBREQ_bRequest (0xFF00u) +#define USB_USBREQ_bRequest_SHIFT (8u) +#define USB_USBVAL_wValue (0xFFFFu) +#define USB_USBVAL_wValue_SHIFT (0u) +#define USB_USBINDX_wIndex (0xFFFFu) +#define USB_USBINDX_wIndex_SHIFT (0u) +#define USB_USBLENG_wLength (0xFFFFu) +#define USB_USBLENG_wLength_SHIFT (0u) +#define USB_DCPCFG_SHTNAK (0x0080u) +#define USB_DCPCFG_SHTNAK_SHIFT (7u) +#define USB_DCPCFG_CNTMD (0x0100u) +#define USB_DCPCFG_CNTMD_SHIFT (8u) +#define USB_DCPMAXP_MXPS (0x007Fu) +#define USB_DCPMAXP_MXPS_SHIFT (0u) +#define USB_DCPCTR_PID (0x0003u) +#define USB_DCPCTR_PID_SHIFT (0u) +#define USB_DCPCTR_CCPL (0x0004u) +#define USB_DCPCTR_CCPL_SHIFT (2u) +#define USB_DCPCTR_PBUSY (0x0020u) +#define USB_DCPCTR_PBUSY_SHIFT (5u) +#define USB_DCPCTR_SQMON (0x0040u) +#define USB_DCPCTR_SQMON_SHIFT (6u) +#define USB_DCPCTR_SQSET (0x0080u) +#define USB_DCPCTR_SQSET_SHIFT (7u) +#define USB_DCPCTR_SQCLR (0x0100u) +#define USB_DCPCTR_SQCLR_SHIFT (8u) +#define USB_DCPCTR_BSTS (0x8000u) +#define USB_DCPCTR_BSTS_SHIFT (15u) +#define USB_PIPESEL_PIPESEL (0x000Fu) +#define USB_PIPESEL_PIPESEL_SHIFT (0u) +#define USB_PIPECFG_EPNUM (0x000Fu) +#define USB_PIPECFG_EPNUM_SHIFT (0u) +#define USB_PIPECFG_DIR (0x0010u) +#define USB_PIPECFG_DIR_SHIFT (4u) +#define USB_PIPECFG_SHTNAK (0x0080u) +#define USB_PIPECFG_SHTNAK_SHIFT (7u) +#define USB_PIPECFG_CNTMD (0x0100u) +#define USB_PIPECFG_CNTMD_SHIFT (8u) +#define USB_PIPECFG_DBLB (0x0200u) +#define USB_PIPECFG_DBLB_SHIFT (9u) +#define USB_PIPECFG_BFRE (0x0400u) +#define USB_PIPECFG_BFRE_SHIFT (10u) +#define USB_PIPECFG_TYPE (0xC000u) +#define USB_PIPECFG_TYPE_SHIFT (14u) +#define USB_PIPEBUF_BUFNMB (0x00FFu) +#define USB_PIPEBUF_BUFNMB_SHIFT (0u) +#define USB_PIPEBUF_BUFSIZE (0x7C00u) +#define USB_PIPEBUF_BUFSIZE_SHIFT (10u) +#define USB_PIPEMAXP_MXPS (0x07FFu) +#define USB_PIPEMAXP_MXPS_SHIFT (0u) +#define USB_PIPEPERI_IITV (0x0007u) +#define USB_PIPEPERI_IITV_SHIFT (0u) +#define USB_PIPEPERI_IFIS (0x1000u) +#define USB_PIPEPERI_IFIS_SHIFT (12u) +#define USB_PIPE1CTR_PID (0x0003u) +#define USB_PIPE1CTR_PID_SHIFT (0u) +#define USB_PIPE1CTR_PBUSY (0x0020u) +#define USB_PIPE1CTR_PBUSY_SHIFT (5u) +#define USB_PIPE1CTR_SQMON (0x0040u) +#define USB_PIPE1CTR_SQMON_SHIFT (6u) +#define USB_PIPE1CTR_SQSET (0x0080u) +#define USB_PIPE1CTR_SQSET_SHIFT (7u) +#define USB_PIPE1CTR_SQCLR (0x0100u) +#define USB_PIPE1CTR_SQCLR_SHIFT (8u) +#define USB_PIPE1CTR_ACLRM (0x0200u) +#define USB_PIPE1CTR_ACLRM_SHIFT (9u) +#define USB_PIPE1CTR_ATREPM (0x0400u) +#define USB_PIPE1CTR_ATREPM_SHIFT (10u) +#define USB_PIPE1CTR_INBUFM (0x4000u) +#define USB_PIPE1CTR_INBUFM_SHIFT (14u) +#define USB_PIPE1CTR_BSTS (0x8000u) +#define USB_PIPE1CTR_BSTS_SHIFT (15u) +#define USB_PIPE2CTR_PID (0x0003u) +#define USB_PIPE2CTR_PID_SHIFT (0u) +#define USB_PIPE2CTR_PBUSY (0x0020u) +#define USB_PIPE2CTR_PBUSY_SHIFT (5u) +#define USB_PIPE2CTR_SQMON (0x0040u) +#define USB_PIPE2CTR_SQMON_SHIFT (6u) +#define USB_PIPE2CTR_SQSET (0x0080u) +#define USB_PIPE2CTR_SQSET_SHIFT (7u) +#define USB_PIPE2CTR_SQCLR (0x0100u) +#define USB_PIPE2CTR_SQCLR_SHIFT (8u) +#define USB_PIPE2CTR_ACLRM (0x0200u) +#define USB_PIPE2CTR_ACLRM_SHIFT (9u) +#define USB_PIPE2CTR_ATREPM (0x0400u) +#define USB_PIPE2CTR_ATREPM_SHIFT (10u) +#define USB_PIPE2CTR_INBUFM (0x4000u) +#define USB_PIPE2CTR_INBUFM_SHIFT (14u) +#define USB_PIPE2CTR_BSTS (0x8000u) +#define USB_PIPE2CTR_BSTS_SHIFT (15u) +#define USB_PIPE3CTR_PID (0x0003u) +#define USB_PIPE3CTR_PID_SHIFT (0u) +#define USB_PIPE3CTR_PBUSY (0x0020u) +#define USB_PIPE3CTR_PBUSY_SHIFT (5u) +#define USB_PIPE3CTR_SQMON (0x0040u) +#define USB_PIPE3CTR_SQMON_SHIFT (6u) +#define USB_PIPE3CTR_SQSET (0x0080u) +#define USB_PIPE3CTR_SQSET_SHIFT (7u) +#define USB_PIPE3CTR_SQCLR (0x0100u) +#define USB_PIPE3CTR_SQCLR_SHIFT (8u) +#define USB_PIPE3CTR_ACLRM (0x0200u) +#define USB_PIPE3CTR_ACLRM_SHIFT (9u) +#define USB_PIPE3CTR_ATREPM (0x0400u) +#define USB_PIPE3CTR_ATREPM_SHIFT (10u) +#define USB_PIPE3CTR_INBUFM (0x4000u) +#define USB_PIPE3CTR_INBUFM_SHIFT (14u) +#define USB_PIPE3CTR_BSTS (0x8000u) +#define USB_PIPE3CTR_BSTS_SHIFT (15u) +#define USB_PIPE4CTR_PID (0x0003u) +#define USB_PIPE4CTR_PID_SHIFT (0u) +#define USB_PIPE4CTR_PBUSY (0x0020u) +#define USB_PIPE4CTR_PBUSY_SHIFT (5u) +#define USB_PIPE4CTR_SQMON (0x0040u) +#define USB_PIPE4CTR_SQMON_SHIFT (6u) +#define USB_PIPE4CTR_SQSET (0x0080u) +#define USB_PIPE4CTR_SQSET_SHIFT (7u) +#define USB_PIPE4CTR_SQCLR (0x0100u) +#define USB_PIPE4CTR_SQCLR_SHIFT (8u) +#define USB_PIPE4CTR_ACLRM (0x0200u) +#define USB_PIPE4CTR_ACLRM_SHIFT (9u) +#define USB_PIPE4CTR_ATREPM (0x0400u) +#define USB_PIPE4CTR_ATREPM_SHIFT (10u) +#define USB_PIPE4CTR_INBUFM (0x4000u) +#define USB_PIPE4CTR_INBUFM_SHIFT (14u) +#define USB_PIPE4CTR_BSTS (0x8000u) +#define USB_PIPE4CTR_BSTS_SHIFT (15u) +#define USB_PIPE5CTR_PID (0x0003u) +#define USB_PIPE5CTR_PID_SHIFT (0u) +#define USB_PIPE5CTR_PBUSY (0x0020u) +#define USB_PIPE5CTR_PBUSY_SHIFT (5u) +#define USB_PIPE5CTR_SQMON (0x0040u) +#define USB_PIPE5CTR_SQMON_SHIFT (6u) +#define USB_PIPE5CTR_SQSET (0x0080u) +#define USB_PIPE5CTR_SQSET_SHIFT (7u) +#define USB_PIPE5CTR_SQCLR (0x0100u) +#define USB_PIPE5CTR_SQCLR_SHIFT (8u) +#define USB_PIPE5CTR_ACLRM (0x0200u) +#define USB_PIPE5CTR_ACLRM_SHIFT (9u) +#define USB_PIPE5CTR_ATREPM (0x0400u) +#define USB_PIPE5CTR_ATREPM_SHIFT (10u) +#define USB_PIPE5CTR_INBUFM (0x4000u) +#define USB_PIPE5CTR_INBUFM_SHIFT (14u) +#define USB_PIPE5CTR_BSTS (0x8000u) +#define USB_PIPE5CTR_BSTS_SHIFT (15u) +#define USB_PIPE6CTR_PID (0x0003u) +#define USB_PIPE6CTR_PID_SHIFT (0u) +#define USB_PIPE6CTR_PBUSY (0x0020u) +#define USB_PIPE6CTR_PBUSY_SHIFT (5u) +#define USB_PIPE6CTR_SQMON (0x0040u) +#define USB_PIPE6CTR_SQMON_SHIFT (6u) +#define USB_PIPE6CTR_SQSET (0x0080u) +#define USB_PIPE6CTR_SQSET_SHIFT (7u) +#define USB_PIPE6CTR_SQCLR (0x0100u) +#define USB_PIPE6CTR_SQCLR_SHIFT (8u) +#define USB_PIPE6CTR_ACLRM (0x0200u) +#define USB_PIPE6CTR_ACLRM_SHIFT (9u) +#define USB_PIPE6CTR_BSTS (0x8000u) +#define USB_PIPE6CTR_BSTS_SHIFT (15u) +#define USB_PIPE7CTR_PID (0x0003u) +#define USB_PIPE7CTR_PID_SHIFT (0u) +#define USB_PIPE7CTR_PBUSY (0x0020u) +#define USB_PIPE7CTR_PBUSY_SHIFT (5u) +#define USB_PIPE7CTR_SQMON (0x0040u) +#define USB_PIPE7CTR_SQMON_SHIFT (6u) +#define USB_PIPE7CTR_SQSET (0x0080u) +#define USB_PIPE7CTR_SQSET_SHIFT (7u) +#define USB_PIPE7CTR_SQCLR (0x0100u) +#define USB_PIPE7CTR_SQCLR_SHIFT (8u) +#define USB_PIPE7CTR_ACLRM (0x0200u) +#define USB_PIPE7CTR_ACLRM_SHIFT (9u) +#define USB_PIPE7CTR_BSTS (0x8000u) +#define USB_PIPE7CTR_BSTS_SHIFT (15u) +#define USB_PIPE8CTR_PID (0x0003u) +#define USB_PIPE8CTR_PID_SHIFT (0u) +#define USB_PIPE8CTR_PBUSY (0x0020u) +#define USB_PIPE8CTR_PBUSY_SHIFT (5u) +#define USB_PIPE8CTR_SQMON (0x0040u) +#define USB_PIPE8CTR_SQMON_SHIFT (6u) +#define USB_PIPE8CTR_SQSET (0x0080u) +#define USB_PIPE8CTR_SQSET_SHIFT (7u) +#define USB_PIPE8CTR_SQCLR (0x0100u) +#define USB_PIPE8CTR_SQCLR_SHIFT (8u) +#define USB_PIPE8CTR_ACLRM (0x0200u) +#define USB_PIPE8CTR_ACLRM_SHIFT (9u) +#define USB_PIPE8CTR_BSTS (0x8000u) +#define USB_PIPE8CTR_BSTS_SHIFT (15u) +#define USB_PIPE9CTR_PID (0x0003u) +#define USB_PIPE9CTR_PID_SHIFT (0u) +#define USB_PIPE9CTR_PBUSY (0x0020u) +#define USB_PIPE9CTR_PBUSY_SHIFT (5u) +#define USB_PIPE9CTR_SQMON (0x0040u) +#define USB_PIPE9CTR_SQMON_SHIFT (6u) +#define USB_PIPE9CTR_SQSET (0x0080u) +#define USB_PIPE9CTR_SQSET_SHIFT (7u) +#define USB_PIPE9CTR_SQCLR (0x0100u) +#define USB_PIPE9CTR_SQCLR_SHIFT (8u) +#define USB_PIPE9CTR_ACLRM (0x0200u) +#define USB_PIPE9CTR_ACLRM_SHIFT (9u) +#define USB_PIPE9CTR_ATREPM (0x0400u) +#define USB_PIPE9CTR_ATREPM_SHIFT (10u) +#define USB_PIPE9CTR_INBUFM (0x4000u) +#define USB_PIPE9CTR_INBUFM_SHIFT (14u) +#define USB_PIPE9CTR_BSTS (0x8000u) +#define USB_PIPE9CTR_BSTS_SHIFT (15u) +#define USB_PIPEACTR_PID (0x0003u) +#define USB_PIPEACTR_PID_SHIFT (0u) +#define USB_PIPEACTR_PBUSY (0x0020u) +#define USB_PIPEACTR_PBUSY_SHIFT (5u) +#define USB_PIPEACTR_SQMON (0x0040u) +#define USB_PIPEACTR_SQMON_SHIFT (6u) +#define USB_PIPEACTR_SQSET (0x0080u) +#define USB_PIPEACTR_SQSET_SHIFT (7u) +#define USB_PIPEACTR_SQCLR (0x0100u) +#define USB_PIPEACTR_SQCLR_SHIFT (8u) +#define USB_PIPEACTR_ACLRM (0x0200u) +#define USB_PIPEACTR_ACLRM_SHIFT (9u) +#define USB_PIPEACTR_ATREPM (0x0400u) +#define USB_PIPEACTR_ATREPM_SHIFT (10u) +#define USB_PIPEACTR_INBUFM (0x4000u) +#define USB_PIPEACTR_INBUFM_SHIFT (14u) +#define USB_PIPEACTR_BSTS (0x8000u) +#define USB_PIPEACTR_BSTS_SHIFT (15u) +#define USB_PIPEBCTR_PID (0x0003u) +#define USB_PIPEBCTR_PID_SHIFT (0u) +#define USB_PIPEBCTR_PBUSY (0x0020u) +#define USB_PIPEBCTR_PBUSY_SHIFT (5u) +#define USB_PIPEBCTR_SQMON (0x0040u) +#define USB_PIPEBCTR_SQMON_SHIFT (6u) +#define USB_PIPEBCTR_SQSET (0x0080u) +#define USB_PIPEBCTR_SQSET_SHIFT (7u) +#define USB_PIPEBCTR_SQCLR (0x0100u) +#define USB_PIPEBCTR_SQCLR_SHIFT (8u) +#define USB_PIPEBCTR_ACLRM (0x0200u) +#define USB_PIPEBCTR_ACLRM_SHIFT (9u) +#define USB_PIPEBCTR_ATREPM (0x0400u) +#define USB_PIPEBCTR_ATREPM_SHIFT (10u) +#define USB_PIPEBCTR_INBUFM (0x4000u) +#define USB_PIPEBCTR_INBUFM_SHIFT (14u) +#define USB_PIPEBCTR_BSTS (0x8000u) +#define USB_PIPEBCTR_BSTS_SHIFT (15u) +#define USB_PIPECCTR_PID (0x0003u) +#define USB_PIPECCTR_PID_SHIFT (0u) +#define USB_PIPECCTR_PBUSY (0x0020u) +#define USB_PIPECCTR_PBUSY_SHIFT (5u) +#define USB_PIPECCTR_SQMON (0x0040u) +#define USB_PIPECCTR_SQMON_SHIFT (6u) +#define USB_PIPECCTR_SQSET (0x0080u) +#define USB_PIPECCTR_SQSET_SHIFT (7u) +#define USB_PIPECCTR_SQCLR (0x0100u) +#define USB_PIPECCTR_SQCLR_SHIFT (8u) +#define USB_PIPECCTR_ACLRM (0x0200u) +#define USB_PIPECCTR_ACLRM_SHIFT (9u) +#define USB_PIPECCTR_ATREPM (0x0400u) +#define USB_PIPECCTR_ATREPM_SHIFT (10u) +#define USB_PIPECCTR_INBUFM (0x4000u) +#define USB_PIPECCTR_INBUFM_SHIFT (14u) +#define USB_PIPECCTR_BSTS (0x8000u) +#define USB_PIPECCTR_BSTS_SHIFT (15u) +#define USB_PIPEDCTR_PID (0x0003u) +#define USB_PIPEDCTR_PID_SHIFT (0u) +#define USB_PIPEDCTR_PBUSY (0x0020u) +#define USB_PIPEDCTR_PBUSY_SHIFT (5u) +#define USB_PIPEDCTR_SQMON (0x0040u) +#define USB_PIPEDCTR_SQMON_SHIFT (6u) +#define USB_PIPEDCTR_SQSET (0x0080u) +#define USB_PIPEDCTR_SQSET_SHIFT (7u) +#define USB_PIPEDCTR_SQCLR (0x0100u) +#define USB_PIPEDCTR_SQCLR_SHIFT (8u) +#define USB_PIPEDCTR_ACLRM (0x0200u) +#define USB_PIPEDCTR_ACLRM_SHIFT (9u) +#define USB_PIPEDCTR_ATREPM (0x0400u) +#define USB_PIPEDCTR_ATREPM_SHIFT (10u) +#define USB_PIPEDCTR_INBUFM (0x4000u) +#define USB_PIPEDCTR_INBUFM_SHIFT (14u) +#define USB_PIPEDCTR_BSTS (0x8000u) +#define USB_PIPEDCTR_BSTS_SHIFT (15u) +#define USB_PIPEECTR_PID (0x0003u) +#define USB_PIPEECTR_PID_SHIFT (0u) +#define USB_PIPEECTR_PBUSY (0x0020u) +#define USB_PIPEECTR_PBUSY_SHIFT (5u) +#define USB_PIPEECTR_SQMON (0x0040u) +#define USB_PIPEECTR_SQMON_SHIFT (6u) +#define USB_PIPEECTR_SQSET (0x0080u) +#define USB_PIPEECTR_SQSET_SHIFT (7u) +#define USB_PIPEECTR_SQCLR (0x0100u) +#define USB_PIPEECTR_SQCLR_SHIFT (8u) +#define USB_PIPEECTR_ACLRM (0x0200u) +#define USB_PIPEECTR_ACLRM_SHIFT (9u) +#define USB_PIPEECTR_ATREPM (0x0400u) +#define USB_PIPEECTR_ATREPM_SHIFT (10u) +#define USB_PIPEECTR_INBUFM (0x4000u) +#define USB_PIPEECTR_INBUFM_SHIFT (14u) +#define USB_PIPEECTR_BSTS (0x8000u) +#define USB_PIPEECTR_BSTS_SHIFT (15u) +#define USB_PIPEFCTR_PID (0x0003u) +#define USB_PIPEFCTR_PID_SHIFT (0u) +#define USB_PIPEFCTR_PBUSY (0x0020u) +#define USB_PIPEFCTR_PBUSY_SHIFT (5u) +#define USB_PIPEFCTR_SQMON (0x0040u) +#define USB_PIPEFCTR_SQMON_SHIFT (6u) +#define USB_PIPEFCTR_SQSET (0x0080u) +#define USB_PIPEFCTR_SQSET_SHIFT (7u) +#define USB_PIPEFCTR_SQCLR (0x0100u) +#define USB_PIPEFCTR_SQCLR_SHIFT (8u) +#define USB_PIPEFCTR_ACLRM (0x0200u) +#define USB_PIPEFCTR_ACLRM_SHIFT (9u) +#define USB_PIPEFCTR_ATREPM (0x0400u) +#define USB_PIPEFCTR_ATREPM_SHIFT (10u) +#define USB_PIPEFCTR_INBUFM (0x4000u) +#define USB_PIPEFCTR_INBUFM_SHIFT (14u) +#define USB_PIPEFCTR_BSTS (0x8000u) +#define USB_PIPEFCTR_BSTS_SHIFT (15u) +#define USB_PIPE1TRE_TRCLR (0x0100u) +#define USB_PIPE1TRE_TRCLR_SHIFT (8u) +#define USB_PIPE1TRE_TRENB (0x0200u) +#define USB_PIPE1TRE_TRENB_SHIFT (9u) +#define USB_PIPE1TRN_TRNCNT (0xFFFFu) +#define USB_PIPE1TRN_TRNCNT_SHIFT (0u) +#define USB_PIPE2TRE_TRCLR (0x0100u) +#define USB_PIPE2TRE_TRCLR_SHIFT (8u) +#define USB_PIPE2TRE_TRENB (0x0200u) +#define USB_PIPE2TRE_TRENB_SHIFT (9u) +#define USB_PIPE2TRN_TRNCNT (0xFFFFu) +#define USB_PIPE2TRN_TRNCNT_SHIFT (0u) +#define USB_PIPE3TRE_TRCLR (0x0100u) +#define USB_PIPE3TRE_TRCLR_SHIFT (8u) +#define USB_PIPE3TRE_TRENB (0x0200u) +#define USB_PIPE3TRE_TRENB_SHIFT (9u) +#define USB_PIPE3TRN_TRNCNT (0xFFFFu) +#define USB_PIPE3TRN_TRNCNT_SHIFT (0u) +#define USB_PIPE4TRE_TRCLR (0x0100u) +#define USB_PIPE4TRE_TRCLR_SHIFT (8u) +#define USB_PIPE4TRE_TRENB (0x0200u) +#define USB_PIPE4TRE_TRENB_SHIFT (9u) +#define USB_PIPE4TRN_TRNCNT (0xFFFFu) +#define USB_PIPE4TRN_TRNCNT_SHIFT (0u) +#define USB_PIPE5TRE_TRCLR (0x0100u) +#define USB_PIPE5TRE_TRCLR_SHIFT (8u) +#define USB_PIPE5TRE_TRENB (0x0200u) +#define USB_PIPE5TRE_TRENB_SHIFT (9u) +#define USB_PIPE5TRN_TRNCNT (0xFFFFu) +#define USB_PIPE5TRN_TRNCNT_SHIFT (0u) +#define USB_PIPEBTRE_TRCLR (0x0100u) +#define USB_PIPEBTRE_TRCLR_SHIFT (8u) +#define USB_PIPEBTRE_TRENB (0x0200u) +#define USB_PIPEBTRE_TRENB_SHIFT (9u) +#define USB_PIPEBTRN_TRNCNT (0xFFFFu) +#define USB_PIPEBTRN_TRNCNT_SHIFT (0u) +#define USB_PIPECTRE_TRCLR (0x0100u) +#define USB_PIPECTRE_TRCLR_SHIFT (8u) +#define USB_PIPECTRE_TRENB (0x0200u) +#define USB_PIPECTRE_TRENB_SHIFT (9u) +#define USB_PIPECTRN_TRNCNT (0xFFFFu) +#define USB_PIPECTRN_TRNCNT_SHIFT (0u) +#define USB_PIPEDTRE_TRCLR (0x0100u) +#define USB_PIPEDTRE_TRCLR_SHIFT (8u) +#define USB_PIPEDTRE_TRENB (0x0200u) +#define USB_PIPEDTRE_TRENB_SHIFT (9u) +#define USB_PIPEDTRN_TRNCNT (0xFFFFu) +#define USB_PIPEDTRN_TRNCNT_SHIFT (0u) +#define USB_PIPEETRE_TRCLR (0x0100u) +#define USB_PIPEETRE_TRCLR_SHIFT (8u) +#define USB_PIPEETRE_TRENB (0x0200u) +#define USB_PIPEETRE_TRENB_SHIFT (9u) +#define USB_PIPEETRN_TRNCNT (0xFFFFu) +#define USB_PIPEETRN_TRNCNT_SHIFT (0u) +#define USB_PIPEFTRE_TRCLR (0x0100u) +#define USB_PIPEFTRE_TRCLR_SHIFT (8u) +#define USB_PIPEFTRE_TRENB (0x0200u) +#define USB_PIPEFTRE_TRENB_SHIFT (9u) +#define USB_PIPEFTRN_TRNCNT (0xFFFFu) +#define USB_PIPEFTRN_TRNCNT_SHIFT (0u) +#define USB_PIPE9TRE_TRCLR (0x0100u) +#define USB_PIPE9TRE_TRCLR_SHIFT (8u) +#define USB_PIPE9TRE_TRENB (0x0200u) +#define USB_PIPE9TRE_TRENB_SHIFT (9u) +#define USB_PIPE9TRN_TRNCNT (0xFFFFu) +#define USB_PIPE9TRN_TRNCNT_SHIFT (0u) +#define USB_PIPEATRE_TRCLR (0x0100u) +#define USB_PIPEATRE_TRCLR_SHIFT (8u) +#define USB_PIPEATRE_TRENB (0x0200u) +#define USB_PIPEATRE_TRENB_SHIFT (9u) +#define USB_PIPEATRN_TRNCNT (0xFFFFu) +#define USB_PIPEATRN_TRNCNT_SHIFT (0u) +#define USB_LPCTRL_HWUPM (0x0080u) +#define USB_LPCTRL_HWUPM_SHIFT (7u) +#define USB_LPSTS_SUSPM (0x4000u) +#define USB_LPSTS_SUSPM_SHIFT (14u) +#define USB_PHYFUNCTR_SusMon (0x4000u) +#define USB_PHYFUNCTR_SusMon_SHIFT (14u) +#define USB_PHYOTGCTR_DpPuDwn (0x0200u) +#define USB_PHYOTGCTR_DpPuDwn_SHIFT (9u) +#define USB_PHYOTGCTR_DmPuDwn (0x0400u) +#define USB_PHYOTGCTR_DmPuDwn_SHIFT (10u) +#define USB_PL1CTRL1_L1RESPEN (0x0001u) +#define USB_PL1CTRL1_L1RESPEN_SHIFT (0u) +#define USB_PL1CTRL1_L1RESPMD (0x0006u) +#define USB_PL1CTRL1_L1RESPMD_SHIFT (1u) +#define USB_PL1CTRL1_L1NEGOMD (0x0008u) +#define USB_PL1CTRL1_L1NEGOMD_SHIFT (3u) +#define USB_PL1CTRL1_DVSQ (0x00F0u) +#define USB_PL1CTRL1_DVSQ_SHIFT (4u) +#define USB_PL1CTRL1_HIRDTHR (0x0F00u) +#define USB_PL1CTRL1_HIRDTHR_SHIFT (8u) +#define USB_PL1CTRL1_L1EXTMD (0x4000u) +#define USB_PL1CTRL1_L1EXTMD_SHIFT (14u) +#define USB_PL1CTRL2_HIRDMON (0x0F00u) +#define USB_PL1CTRL2_HIRDMON_SHIFT (8u) +#define USB_PL1CTRL2_RWEMON (0x1000u) +#define USB_PL1CTRL2_RWEMON_SHIFT (12u) +#define USB_N0SA_0_SA_WD (0xFFFFFFFFu) +#define USB_N0SA_0_SA_WD_SHIFT (0u) +#define USB_N0DA_0_DA (0xFFFFFFFFu) +#define USB_N0DA_0_DA_SHIFT (0u) +#define USB_N0TB_0_TB (0xFFFFFFFFu) +#define USB_N0TB_0_TB_SHIFT (0u) +#define USB_N1SA_0_SA_WD (0xFFFFFFFFu) +#define USB_N1SA_0_SA_WD_SHIFT (0u) +#define USB_N1DA_0_DA (0xFFFFFFFFu) +#define USB_N1DA_0_DA_SHIFT (0u) +#define USB_N1TB_0_TB (0xFFFFFFFFu) +#define USB_N1TB_0_TB_SHIFT (0u) +#define USB_CRSA_0_CRSA (0xFFFFFFFFu) +#define USB_CRSA_0_CRSA_SHIFT (0u) +#define USB_CRDA_0_CRDA (0xFFFFFFFFu) +#define USB_CRDA_0_CRDA_SHIFT (0u) +#define USB_CRTB_0_CRTB (0xFFFFFFFFu) +#define USB_CRTB_0_CRTB_SHIFT (0u) +#define USB_CHSTAT_0_EN (0x00000001u) +#define USB_CHSTAT_0_EN_SHIFT (0u) +#define USB_CHSTAT_0_RQST (0x00000002u) +#define USB_CHSTAT_0_RQST_SHIFT (1u) +#define USB_CHSTAT_0_TACT (0x00000004u) +#define USB_CHSTAT_0_TACT_SHIFT (2u) +#define USB_CHSTAT_0_SUS (0x00000008u) +#define USB_CHSTAT_0_SUS_SHIFT (3u) +#define USB_CHSTAT_0_ER (0x00000010u) +#define USB_CHSTAT_0_ER_SHIFT (4u) +#define USB_CHSTAT_0_END (0x00000020u) +#define USB_CHSTAT_0_END_SHIFT (5u) +#define USB_CHSTAT_0_TC (0x00000040u) +#define USB_CHSTAT_0_TC_SHIFT (6u) +#define USB_CHSTAT_0_SR (0x00000080u) +#define USB_CHSTAT_0_SR_SHIFT (7u) +#define USB_CHSTAT_0_DL (0x00000100u) +#define USB_CHSTAT_0_DL_SHIFT (8u) +#define USB_CHSTAT_0_DW (0x00000200u) +#define USB_CHSTAT_0_DW_SHIFT (9u) +#define USB_CHSTAT_0_DER (0x00000400u) +#define USB_CHSTAT_0_DER_SHIFT (10u) +#define USB_CHSTAT_0_MODE (0x00000800u) +#define USB_CHSTAT_0_MODE_SHIFT (11u) +#define USB_CHSTAT_0_INTM (0x00010000u) +#define USB_CHSTAT_0_INTM_SHIFT (16u) +#define USB_CHSTAT_0_DMARQM (0x00020000u) +#define USB_CHSTAT_0_DMARQM_SHIFT (17u) +#define USB_CHSTAT_0_SWPRQ (0x00040000u) +#define USB_CHSTAT_0_SWPRQ_SHIFT (18u) +#define USB_CHSTAT_0_DNUM (0xFF000000u) +#define USB_CHSTAT_0_DNUM_SHIFT (24u) +#define USB_CHCTRL_0_SETEN (0x00000001u) +#define USB_CHCTRL_0_SETEN_SHIFT (0u) +#define USB_CHCTRL_0_CLREN (0x00000002u) +#define USB_CHCTRL_0_CLREN_SHIFT (1u) +#define USB_CHCTRL_0_STG (0x00000004u) +#define USB_CHCTRL_0_STG_SHIFT (2u) +#define USB_CHCTRL_0_SWRST (0x00000008u) +#define USB_CHCTRL_0_SWRST_SHIFT (3u) +#define USB_CHCTRL_0_CLRRQ (0x00000010u) +#define USB_CHCTRL_0_CLRRQ_SHIFT (4u) +#define USB_CHCTRL_0_CLREND (0x00000020u) +#define USB_CHCTRL_0_CLREND_SHIFT (5u) +#define USB_CHCTRL_0_CLRTC (0x00000040u) +#define USB_CHCTRL_0_CLRTC_SHIFT (6u) +#define USB_CHCTRL_0_CLRDER (0x00000080u) +#define USB_CHCTRL_0_CLRDER_SHIFT (7u) +#define USB_CHCTRL_0_SETSUS (0x00000100u) +#define USB_CHCTRL_0_SETSUS_SHIFT (8u) +#define USB_CHCTRL_0_CLRSUS (0x00000200u) +#define USB_CHCTRL_0_CLRSUS_SHIFT (9u) +#define USB_CHCTRL_0_SETREN (0x00001000u) +#define USB_CHCTRL_0_SETREN_SHIFT (12u) +#define USB_CHCTRL_0_SETSSWPRQ (0x00004000u) +#define USB_CHCTRL_0_SETSSWPRQ_SHIFT (14u) +#define USB_CHCTRL_0_SETINTM (0x00010000u) +#define USB_CHCTRL_0_SETINTM_SHIFT (16u) +#define USB_CHCTRL_0_CLRINTM (0x00020000u) +#define USB_CHCTRL_0_CLRINTM_SHIFT (17u) +#define USB_CHCTRL_0_SETDMARQM (0x00040000u) +#define USB_CHCTRL_0_SETDMARQM_SHIFT (18u) +#define USB_CHCTRL_0_CLRDMARQM (0x00080000u) +#define USB_CHCTRL_0_CLRDMARQM_SHIFT (19u) +#define USB_CHCFG_0_SEL (0x00000001u) +#define USB_CHCFG_0_SEL_SHIFT (0u) +#define USB_CHCFG_0_REQD (0x00000008u) +#define USB_CHCFG_0_REQD_SHIFT (3u) +#define USB_CHCFG_0_DRRP (0x00000800u) +#define USB_CHCFG_0_DRRP_SHIFT (11u) +#define USB_CHCFG_0_SDS (0x0000F000u) +#define USB_CHCFG_0_SDS_SHIFT (12u) +#define USB_CHCFG_0_DDS (0x000F0000u) +#define USB_CHCFG_0_DDS_SHIFT (16u) +#define USB_CHCFG_0_SAD (0x00100000u) +#define USB_CHCFG_0_SAD_SHIFT (20u) +#define USB_CHCFG_0_DAD (0x00200000u) +#define USB_CHCFG_0_DAD_SHIFT (21u) +#define USB_CHCFG_0_WONLY (0x00800000u) +#define USB_CHCFG_0_WONLY_SHIFT (23u) +#define USB_CHCFG_0_DEM (0x01000000u) +#define USB_CHCFG_0_DEM_SHIFT (24u) +#define USB_CHCFG_0_TCM (0x02000000u) +#define USB_CHCFG_0_TCM_SHIFT (25u) +#define USB_CHCFG_0_DIM (0x04000000u) +#define USB_CHCFG_0_DIM_SHIFT (26u) +#define USB_CHCFG_0_SBE (0x08000000u) +#define USB_CHCFG_0_SBE_SHIFT (27u) +#define USB_CHCFG_0_RSEL (0x10000000u) +#define USB_CHCFG_0_RSEL_SHIFT (28u) +#define USB_CHCFG_0_RSW (0x20000000u) +#define USB_CHCFG_0_RSW_SHIFT (29u) +#define USB_CHCFG_0_REN (0x40000000u) +#define USB_CHCFG_0_REN_SHIFT (30u) +#define USB_CHCFG_0_DMS (0x80000000u) +#define USB_CHCFG_0_DMS_SHIFT (31u) +#define USB_CHITVL_0_ITVL (0x0000FFFFu) +#define USB_CHITVL_0_ITVL_SHIFT (0u) +#define USB_CHEXT_0_SPR (0x0000000Fu) +#define USB_CHEXT_0_SPR_SHIFT (0u) +#define USB_CHEXT_0_DPR (0x00000F00u) +#define USB_CHEXT_0_DPR_SHIFT (8u) +#define USB_NXLA_0_NXLA (0xFFFFFFFFu) +#define USB_NXLA_0_NXLA_SHIFT (0u) +#define USB_CRLA_0_CRLA (0xFFFFFFFFu) +#define USB_CRLA_0_CRLA_SHIFT (0u) +#define USB_N0SA_1_SA_WD (0xFFFFFFFFu) +#define USB_N0SA_1_SA_WD_SHIFT (0u) +#define USB_N0DA_1_DA (0xFFFFFFFFu) +#define USB_N0DA_1_DA_SHIFT (0u) +#define USB_N0TB_1_TB (0xFFFFFFFFu) +#define USB_N0TB_1_TB_SHIFT (0u) +#define USB_N1SA_1_SA_WD (0xFFFFFFFFu) +#define USB_N1SA_1_SA_WD_SHIFT (0u) +#define USB_N1DA_1_DA (0xFFFFFFFFu) +#define USB_N1DA_1_DA_SHIFT (0u) +#define USB_N1TB_1_TB (0xFFFFFFFFu) +#define USB_N1TB_1_TB_SHIFT (0u) +#define USB_CRSA_1_CRSA (0xFFFFFFFFu) +#define USB_CRSA_1_CRSA_SHIFT (0u) +#define USB_CRDA_1_CRDA (0xFFFFFFFFu) +#define USB_CRDA_1_CRDA_SHIFT (0u) +#define USB_CRTB_1_CRTB (0xFFFFFFFFu) +#define USB_CRTB_1_CRTB_SHIFT (0u) +#define USB_CHSTAT_1_EN (0x00000001u) +#define USB_CHSTAT_1_EN_SHIFT (0u) +#define USB_CHSTAT_1_RQST (0x00000002u) +#define USB_CHSTAT_1_RQST_SHIFT (1u) +#define USB_CHSTAT_1_TACT (0x00000004u) +#define USB_CHSTAT_1_TACT_SHIFT (2u) +#define USB_CHSTAT_1_SUS (0x00000008u) +#define USB_CHSTAT_1_SUS_SHIFT (3u) +#define USB_CHSTAT_1_ER (0x00000010u) +#define USB_CHSTAT_1_ER_SHIFT (4u) +#define USB_CHSTAT_1_END (0x00000020u) +#define USB_CHSTAT_1_END_SHIFT (5u) +#define USB_CHSTAT_1_TC (0x00000040u) +#define USB_CHSTAT_1_TC_SHIFT (6u) +#define USB_CHSTAT_1_SR (0x00000080u) +#define USB_CHSTAT_1_SR_SHIFT (7u) +#define USB_CHSTAT_1_DL (0x00000100u) +#define USB_CHSTAT_1_DL_SHIFT (8u) +#define USB_CHSTAT_1_DW (0x00000200u) +#define USB_CHSTAT_1_DW_SHIFT (9u) +#define USB_CHSTAT_1_DER (0x00000400u) +#define USB_CHSTAT_1_DER_SHIFT (10u) +#define USB_CHSTAT_1_MODE (0x00000800u) +#define USB_CHSTAT_1_MODE_SHIFT (11u) +#define USB_CHSTAT_1_INTM (0x00010000u) +#define USB_CHSTAT_1_INTM_SHIFT (16u) +#define USB_CHSTAT_1_DMARQM (0x00020000u) +#define USB_CHSTAT_1_DMARQM_SHIFT (17u) +#define USB_CHSTAT_1_SWPRQ (0x00040000u) +#define USB_CHSTAT_1_SWPRQ_SHIFT (18u) +#define USB_CHSTAT_1_DNUM (0xFF000000u) +#define USB_CHSTAT_1_DNUM_SHIFT (24u) +#define USB_CHCTRL_1_SETEN (0x00000001u) +#define USB_CHCTRL_1_SETEN_SHIFT (0u) +#define USB_CHCTRL_1_CLREN (0x00000002u) +#define USB_CHCTRL_1_CLREN_SHIFT (1u) +#define USB_CHCTRL_1_STG (0x00000004u) +#define USB_CHCTRL_1_STG_SHIFT (2u) +#define USB_CHCTRL_1_SWRST (0x00000008u) +#define USB_CHCTRL_1_SWRST_SHIFT (3u) +#define USB_CHCTRL_1_CLRRQ (0x00000010u) +#define USB_CHCTRL_1_CLRRQ_SHIFT (4u) +#define USB_CHCTRL_1_CLREND (0x00000020u) +#define USB_CHCTRL_1_CLREND_SHIFT (5u) +#define USB_CHCTRL_1_CLRTC (0x00000040u) +#define USB_CHCTRL_1_CLRTC_SHIFT (6u) +#define USB_CHCTRL_1_CLRDER (0x00000080u) +#define USB_CHCTRL_1_CLRDER_SHIFT (7u) +#define USB_CHCTRL_1_SETSUS (0x00000100u) +#define USB_CHCTRL_1_SETSUS_SHIFT (8u) +#define USB_CHCTRL_1_CLRSUS (0x00000200u) +#define USB_CHCTRL_1_CLRSUS_SHIFT (9u) +#define USB_CHCTRL_1_SETREN (0x00001000u) +#define USB_CHCTRL_1_SETREN_SHIFT (12u) +#define USB_CHCTRL_1_SETSSWPRQ (0x00004000u) +#define USB_CHCTRL_1_SETSSWPRQ_SHIFT (14u) +#define USB_CHCTRL_1_SETINTM (0x00010000u) +#define USB_CHCTRL_1_SETINTM_SHIFT (16u) +#define USB_CHCTRL_1_CLRINTM (0x00020000u) +#define USB_CHCTRL_1_CLRINTM_SHIFT (17u) +#define USB_CHCTRL_1_SETDMARQM (0x00040000u) +#define USB_CHCTRL_1_SETDMARQM_SHIFT (18u) +#define USB_CHCTRL_1_CLRDMARQM (0x00080000u) +#define USB_CHCTRL_1_CLRDMARQM_SHIFT (19u) +#define USB_CHCFG_1_SEL (0x00000001u) +#define USB_CHCFG_1_SEL_SHIFT (0u) +#define USB_CHCFG_1_REQD (0x00000008u) +#define USB_CHCFG_1_REQD_SHIFT (3u) +#define USB_CHCFG_1_DRRP (0x00000800u) +#define USB_CHCFG_1_DRRP_SHIFT (11u) +#define USB_CHCFG_1_SDS (0x0000F000u) +#define USB_CHCFG_1_SDS_SHIFT (12u) +#define USB_CHCFG_1_DDS (0x000F0000u) +#define USB_CHCFG_1_DDS_SHIFT (16u) +#define USB_CHCFG_1_SAD (0x00100000u) +#define USB_CHCFG_1_SAD_SHIFT (20u) +#define USB_CHCFG_1_DAD (0x00200000u) +#define USB_CHCFG_1_DAD_SHIFT (21u) +#define USB_CHCFG_1_WONLY (0x00800000u) +#define USB_CHCFG_1_WONLY_SHIFT (23u) +#define USB_CHCFG_1_DEM (0x01000000u) +#define USB_CHCFG_1_DEM_SHIFT (24u) +#define USB_CHCFG_1_TCM (0x02000000u) +#define USB_CHCFG_1_TCM_SHIFT (25u) +#define USB_CHCFG_1_DIM (0x04000000u) +#define USB_CHCFG_1_DIM_SHIFT (26u) +#define USB_CHCFG_1_SBE (0x08000000u) +#define USB_CHCFG_1_SBE_SHIFT (27u) +#define USB_CHCFG_1_RSEL (0x10000000u) +#define USB_CHCFG_1_RSEL_SHIFT (28u) +#define USB_CHCFG_1_RSW (0x20000000u) +#define USB_CHCFG_1_RSW_SHIFT (29u) +#define USB_CHCFG_1_REN (0x40000000u) +#define USB_CHCFG_1_REN_SHIFT (30u) +#define USB_CHCFG_1_DMS (0x80000000u) +#define USB_CHCFG_1_DMS_SHIFT (31u) +#define USB_CHITVL_1_ITVL (0x0000FFFFu) +#define USB_CHITVL_1_ITVL_SHIFT (0u) +#define USB_CHEXT_1_SPR (0x0000000Fu) +#define USB_CHEXT_1_SPR_SHIFT (0u) +#define USB_CHEXT_1_DPR (0x00000F00u) +#define USB_CHEXT_1_DPR_SHIFT (8u) +#define USB_NXLA_1_NXLA (0xFFFFFFFFu) +#define USB_NXLA_1_NXLA_SHIFT (0u) +#define USB_CRLA_1_CRLA (0xFFFFFFFFu) +#define USB_CRLA_1_CRLA_SHIFT (0u) +#define USB_SCNT_0_SCNT (0xFFFFFFFFu) +#define USB_SCNT_0_SCNT_SHIFT (0u) +#define USB_SSKP_0_SSKP (0xFFFFFFFFu) +#define USB_SSKP_0_SSKP_SHIFT (0u) +#define USB_DCNT_0_DCNT (0xFFFFFFFFu) +#define USB_DCNT_0_DCNT_SHIFT (0u) +#define USB_DSKP_0_DSKP (0xFFFFFFFFu) +#define USB_DSKP_0_DSKP_SHIFT (0u) +#define USB_SCNT_1_SCNT (0xFFFFFFFFu) +#define USB_SCNT_1_SCNT_SHIFT (0u) +#define USB_SSKP_1_SSKP (0xFFFFFFFFu) +#define USB_SSKP_1_SSKP_SHIFT (0u) +#define USB_DCNT_1_DCNT (0xFFFFFFFFu) +#define USB_DCNT_1_DCNT_SHIFT (0u) +#define USB_DSKP_1_DSKP (0xFFFFFFFFu) +#define USB_DSKP_1_DSKP_SHIFT (0u) +#define USB_DCTRL_PR (0x00000001u) +#define USB_DCTRL_PR_SHIFT (0u) +#define USB_DCTRL_LVINT (0x00000002u) +#define USB_DCTRL_LVINT_SHIFT (1u) +#define USB_DCTRL_LDPR (0x000F0000u) +#define USB_DCTRL_LDPR_SHIFT (16u) +#define USB_DCTRL_LWPR (0x0F000000u) +#define USB_DCTRL_LWPR_SHIFT (24u) +#define USB_DSCITVL_DITVL (0x0000FF00u) +#define USB_DSCITVL_DITVL_SHIFT (8u) +#define USB_DST_EN_EN0 (0x00000001u) +#define USB_DST_EN_EN0_SHIFT (0u) +#define USB_DST_EN_EN1 (0x00000002u) +#define USB_DST_EN_EN1_SHIFT (1u) +#define USB_DST_ER_ER0 (0x00000001u) +#define USB_DST_ER_ER0_SHIFT (0u) +#define USB_DST_ER_ER1 (0x00000002u) +#define USB_DST_ER_ER1_SHIFT (1u) +#define USB_DST_END_END0 (0x00000001u) +#define USB_DST_END_END0_SHIFT (0u) +#define USB_DST_END_END1 (0x00000002u) +#define USB_DST_END_END1_SHIFT (1u) +#define USB_DST_TC_TC0 (0x00000001u) +#define USB_DST_TC_TC0_SHIFT (0u) +#define USB_DST_TC_TC1 (0x00000002u) +#define USB_DST_TC_TC1_SHIFT (1u) +#define USB_DST_SUS_SUS0 (0x00000001u) +#define USB_DST_SUS_SUS0_SHIFT (0u) +#define USB_DST_SUS_SUS1 (0x00000002u) +#define USB_DST_SUS_SUS1_SHIFT (1u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vdc6_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vdc6_iobitmask.h new file mode 100644 index 0000000..2d066ab --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vdc6_iobitmask.h @@ -0,0 +1,1340 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef VDC6_IOBITMASK_H +#define VDC6_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define VDC6_INP_UPDATE_INP_IMG_UPDATE (0x00000001u) +#define VDC6_INP_UPDATE_INP_IMG_UPDATE_SHIFT (0u) +#define VDC6_INP_UPDATE_INP_EXT_UPDATE (0x00000010u) +#define VDC6_INP_UPDATE_INP_EXT_UPDATE_SHIFT (4u) +#define VDC6_INP_SEL_CNT_INP_HS_EDGE (0x00000001u) +#define VDC6_INP_SEL_CNT_INP_HS_EDGE_SHIFT (0u) +#define VDC6_INP_SEL_CNT_INP_VS_EDGE (0x00000010u) +#define VDC6_INP_SEL_CNT_INP_VS_EDGE_SHIFT (4u) +#define VDC6_INP_SEL_CNT_INP_PXD_EDGE (0x00000100u) +#define VDC6_INP_SEL_CNT_INP_PXD_EDGE_SHIFT (8u) +#define VDC6_INP_SEL_CNT_INP_FORMAT (0x00007000u) +#define VDC6_INP_SEL_CNT_INP_FORMAT_SHIFT (12u) +#define VDC6_INP_SEL_CNT_INP_SEL (0x00100000u) +#define VDC6_INP_SEL_CNT_INP_SEL_SHIFT (20u) +#define VDC6_INP_EXT_SYNC_CNT_INP_H_POS (0x00000003u) +#define VDC6_INP_EXT_SYNC_CNT_INP_H_POS_SHIFT (0u) +#define VDC6_INP_EXT_SYNC_CNT_INP_F525_625 (0x00000010u) +#define VDC6_INP_EXT_SYNC_CNT_INP_F525_625_SHIFT (4u) +#define VDC6_INP_EXT_SYNC_CNT_INP_H_EDGE_SEL (0x00000100u) +#define VDC6_INP_EXT_SYNC_CNT_INP_H_EDGE_SEL_SHIFT (8u) +#define VDC6_INP_EXT_SYNC_CNT_INP_HS_INV (0x00010000u) +#define VDC6_INP_EXT_SYNC_CNT_INP_HS_INV_SHIFT (16u) +#define VDC6_INP_EXT_SYNC_CNT_INP_VS_INV (0x00100000u) +#define VDC6_INP_EXT_SYNC_CNT_INP_VS_INV_SHIFT (20u) +#define VDC6_INP_EXT_SYNC_CNT_INP_SWAP_ON (0x01000000u) +#define VDC6_INP_EXT_SYNC_CNT_INP_SWAP_ON_SHIFT (24u) +#define VDC6_INP_EXT_SYNC_CNT_INP_ENDIAN_ON (0x10000000u) +#define VDC6_INP_EXT_SYNC_CNT_INP_ENDIAN_ON_SHIFT (28u) +#define VDC6_INP_VSYNC_PH_ADJ_INP_FH25 (0x00000FFFu) +#define VDC6_INP_VSYNC_PH_ADJ_INP_FH25_SHIFT (0u) +#define VDC6_INP_VSYNC_PH_ADJ_INP_FH50 (0x0FFF0000u) +#define VDC6_INP_VSYNC_PH_ADJ_INP_FH50_SHIFT (16u) +#define VDC6_INP_DLY_ADJ_INP_HS_DLY (0x000000FFu) +#define VDC6_INP_DLY_ADJ_INP_HS_DLY_SHIFT (0u) +#define VDC6_INP_DLY_ADJ_INP_VS_DLY (0x0000FF00u) +#define VDC6_INP_DLY_ADJ_INP_VS_DLY_SHIFT (8u) +#define VDC6_INP_DLY_ADJ_INP_FLD_DLY (0x00FF0000u) +#define VDC6_INP_DLY_ADJ_INP_FLD_DLY_SHIFT (16u) +#define VDC6_INP_DLY_ADJ_INP_VS_DLY_L (0x07000000u) +#define VDC6_INP_DLY_ADJ_INP_VS_DLY_L_SHIFT (24u) +#define VDC6_IMGCNT_UPDATE_IMGCNT_VEN (0x00000001u) +#define VDC6_IMGCNT_UPDATE_IMGCNT_VEN_SHIFT (0u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_Y_GAIN (0x00000003u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_Y_GAIN_SHIFT (0u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_Y_TAP (0x00000030u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_Y_TAP_SHIFT (4u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_Y_TH (0x00007F00u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_Y_TH_SHIFT (8u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_ON (0x00010000u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_ON_SHIFT (16u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_MD (0x00100000u) +#define VDC6_IMGCNT_NR_CNT0_NR1D_MD_SHIFT (20u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CR_GAIN (0x00000003u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CR_GAIN_SHIFT (0u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CR_TAP (0x00000030u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CR_TAP_SHIFT (4u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CR_TH (0x00007F00u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CR_TH_SHIFT (8u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CB_GAIN (0x00030000u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CB_GAIN_SHIFT (16u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CB_TAP (0x00300000u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CB_TAP_SHIFT (20u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CB_TH (0x7F000000u) +#define VDC6_IMGCNT_NR_CNT1_NR1D_CB_TH_SHIFT (24u) +#define VDC6_IMGCNT_MTX_MODE_IMGCNT_MTX_MD (0x00000003u) +#define VDC6_IMGCNT_MTX_MODE_IMGCNT_MTX_MD_SHIFT (0u) +#define VDC6_IMGCNT_MTX_YG_ADJ0_IMGCNT_MTX_GG (0x000007FFu) +#define VDC6_IMGCNT_MTX_YG_ADJ0_IMGCNT_MTX_GG_SHIFT (0u) +#define VDC6_IMGCNT_MTX_YG_ADJ0_IMGCNT_MTX_YG (0x00FF0000u) +#define VDC6_IMGCNT_MTX_YG_ADJ0_IMGCNT_MTX_YG_SHIFT (16u) +#define VDC6_IMGCNT_MTX_YG_ADJ1_IMGCNT_MTX_GR (0x000007FFu) +#define VDC6_IMGCNT_MTX_YG_ADJ1_IMGCNT_MTX_GR_SHIFT (0u) +#define VDC6_IMGCNT_MTX_YG_ADJ1_IMGCNT_MTX_GB (0x07FF0000u) +#define VDC6_IMGCNT_MTX_YG_ADJ1_IMGCNT_MTX_GB_SHIFT (16u) +#define VDC6_IMGCNT_MTX_CBB_ADJ0_IMGCNT_MTX_BG (0x000007FFu) +#define VDC6_IMGCNT_MTX_CBB_ADJ0_IMGCNT_MTX_BG_SHIFT (0u) +#define VDC6_IMGCNT_MTX_CBB_ADJ0_IMGCNT_MTX_B (0x00FF0000u) +#define VDC6_IMGCNT_MTX_CBB_ADJ0_IMGCNT_MTX_B_SHIFT (16u) +#define VDC6_IMGCNT_MTX_CBB_ADJ1_IMGCNT_MTX_BR (0x000007FFu) +#define VDC6_IMGCNT_MTX_CBB_ADJ1_IMGCNT_MTX_BR_SHIFT (0u) +#define VDC6_IMGCNT_MTX_CBB_ADJ1_IMGCNT_MTX_BB (0x07FF0000u) +#define VDC6_IMGCNT_MTX_CBB_ADJ1_IMGCNT_MTX_BB_SHIFT (16u) +#define VDC6_IMGCNT_MTX_CRR_ADJ0_IMGCNT_MTX_RG (0x000007FFu) +#define VDC6_IMGCNT_MTX_CRR_ADJ0_IMGCNT_MTX_RG_SHIFT (0u) +#define VDC6_IMGCNT_MTX_CRR_ADJ0_IMGCNT_MTX_R (0x00FF0000u) +#define VDC6_IMGCNT_MTX_CRR_ADJ0_IMGCNT_MTX_R_SHIFT (16u) +#define VDC6_IMGCNT_MTX_CRR_ADJ1_IMGCNT_MTX_RR (0x000007FFu) +#define VDC6_IMGCNT_MTX_CRR_ADJ1_IMGCNT_MTX_RR_SHIFT (0u) +#define VDC6_IMGCNT_MTX_CRR_ADJ1_IMGCNT_MTX_RB (0x07FF0000u) +#define VDC6_IMGCNT_MTX_CRR_ADJ1_IMGCNT_MTX_RB_SHIFT (16u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_A (0x00000001u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_A_SHIFT (0u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_B (0x00000010u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_B_SHIFT (4u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_UPDATE (0x00000100u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_UPDATE_SHIFT (8u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_C (0x00001000u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_C_SHIFT (12u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_D (0x00002000u) +#define VDC6_SC0_SCL0_UPDATE_SC0_SCL0_VEN_D_SHIFT (13u) +#define VDC6_SC0_SCL0_FRC1_SC0_RES_VMASK_ON (0x00000001u) +#define VDC6_SC0_SCL0_FRC1_SC0_RES_VMASK_ON_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC1_SC0_RES_VMASK (0xFFFF0000u) +#define VDC6_SC0_SCL0_FRC1_SC0_RES_VMASK_SHIFT (16u) +#define VDC6_SC0_SCL0_FRC2_SC0_RES_VLACK_ON (0x00000001u) +#define VDC6_SC0_SCL0_FRC2_SC0_RES_VLACK_ON_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC2_SC0_RES_VLACK (0xFFFF0000u) +#define VDC6_SC0_SCL0_FRC2_SC0_RES_VLACK_SHIFT (16u) +#define VDC6_SC0_SCL0_FRC3_SC0_RES_VS_SEL (0x00000001u) +#define VDC6_SC0_SCL0_FRC3_SC0_RES_VS_SEL_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC4_SC0_RES_FH (0x000007FFu) +#define VDC6_SC0_SCL0_FRC4_SC0_RES_FH_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC4_SC0_RES_FV (0x07FF0000u) +#define VDC6_SC0_SCL0_FRC4_SC0_RES_FV_SHIFT (16u) +#define VDC6_SC0_SCL0_FRC5_SC0_RES_VSDLY (0x000000FFu) +#define VDC6_SC0_SCL0_FRC5_SC0_RES_VSDLY_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC5_SC0_RES_FLD_DLY_SEL (0x00000100u) +#define VDC6_SC0_SCL0_FRC5_SC0_RES_FLD_DLY_SEL_SHIFT (8u) +#define VDC6_SC0_SCL0_FRC6_SC0_RES_F_VW (0x000007FFu) +#define VDC6_SC0_SCL0_FRC6_SC0_RES_F_VW_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC6_SC0_RES_F_VS (0x07FF0000u) +#define VDC6_SC0_SCL0_FRC6_SC0_RES_F_VS_SHIFT (16u) +#define VDC6_SC0_SCL0_FRC7_SC0_RES_F_HW (0x000007FFu) +#define VDC6_SC0_SCL0_FRC7_SC0_RES_F_HW_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC7_SC0_RES_F_HS (0x07FF0000u) +#define VDC6_SC0_SCL0_FRC7_SC0_RES_F_HS_SHIFT (16u) +#define VDC6_SC0_SCL0_FRC9_SC0_RES_QVLACK (0x00000001u) +#define VDC6_SC0_SCL0_FRC9_SC0_RES_QVLACK_SHIFT (0u) +#define VDC6_SC0_SCL0_FRC9_SC0_RES_QVLOCK (0x00000010u) +#define VDC6_SC0_SCL0_FRC9_SC0_RES_QVLOCK_SHIFT (4u) +#define VDC6_SC0_SCL0_MON0_SC0_RES_LIN_STAT (0x07FFu) +#define VDC6_SC0_SCL0_MON0_SC0_RES_LIN_STAT_SHIFT (0u) +#define VDC6_SC0_SCL0_INT_SC0_RES_LINE (0x07FFu) +#define VDC6_SC0_SCL0_INT_SC0_RES_LINE_SHIFT (0u) +#define VDC6_SC0_SCL0_DS1_SC0_RES_DS_H_ON (0x00000001u) +#define VDC6_SC0_SCL0_DS1_SC0_RES_DS_H_ON_SHIFT (0u) +#define VDC6_SC0_SCL0_DS1_SC0_RES_DS_V_ON (0x00000010u) +#define VDC6_SC0_SCL0_DS1_SC0_RES_DS_V_ON_SHIFT (4u) +#define VDC6_SC0_SCL0_DS2_SC0_RES_VW (0x000007FFu) +#define VDC6_SC0_SCL0_DS2_SC0_RES_VW_SHIFT (0u) +#define VDC6_SC0_SCL0_DS2_SC0_RES_VS (0x07FF0000u) +#define VDC6_SC0_SCL0_DS2_SC0_RES_VS_SHIFT (16u) +#define VDC6_SC0_SCL0_DS3_SC0_RES_HW (0x00000FFFu) +#define VDC6_SC0_SCL0_DS3_SC0_RES_HW_SHIFT (0u) +#define VDC6_SC0_SCL0_DS3_SC0_RES_HS (0x07FF0000u) +#define VDC6_SC0_SCL0_DS3_SC0_RES_HS_SHIFT (16u) +#define VDC6_SC0_SCL0_DS4_SC0_RES_DS_H_RATIO (0x0000FFFFu) +#define VDC6_SC0_SCL0_DS4_SC0_RES_DS_H_RATIO_SHIFT (0u) +#define VDC6_SC0_SCL0_DS4_SC0_RES_DS_H_INTERPOTYP (0x10000000u) +#define VDC6_SC0_SCL0_DS4_SC0_RES_DS_H_INTERPOTYP_SHIFT (28u) +#define VDC6_SC0_SCL0_DS4_SC0_RES_PFIL_SEL (0x20000000u) +#define VDC6_SC0_SCL0_DS4_SC0_RES_PFIL_SEL_SHIFT (29u) +#define VDC6_SC0_SCL0_DS5_SC0_RES_BTM_INIPHASE (0x00000FFFu) +#define VDC6_SC0_SCL0_DS5_SC0_RES_BTM_INIPHASE_SHIFT (0u) +#define VDC6_SC0_SCL0_DS5_SC0_RES_TOP_INIPHASE (0x0FFF0000u) +#define VDC6_SC0_SCL0_DS5_SC0_RES_TOP_INIPHASE_SHIFT (16u) +#define VDC6_SC0_SCL0_DS5_SC0_RES_V_INTERPOTYP (0x10000000u) +#define VDC6_SC0_SCL0_DS5_SC0_RES_V_INTERPOTYP_SHIFT (28u) +#define VDC6_SC0_SCL0_DS6_SC0_RES_V_RATIO (0x0000FFFFu) +#define VDC6_SC0_SCL0_DS6_SC0_RES_V_RATIO_SHIFT (0u) +#define VDC6_SC0_SCL0_DS7_SC0_RES_OUT_HW (0x000007FFu) +#define VDC6_SC0_SCL0_DS7_SC0_RES_OUT_HW_SHIFT (0u) +#define VDC6_SC0_SCL0_DS7_SC0_RES_OUT_VW (0x07FF0000u) +#define VDC6_SC0_SCL0_DS7_SC0_RES_OUT_VW_SHIFT (16u) +#define VDC6_SC0_SCL0_US1_SC0_RES_US_H_ON (0x00000001u) +#define VDC6_SC0_SCL0_US1_SC0_RES_US_H_ON_SHIFT (0u) +#define VDC6_SC0_SCL0_US1_SC0_RES_US_V_ON (0x00000010u) +#define VDC6_SC0_SCL0_US1_SC0_RES_US_V_ON_SHIFT (4u) +#define VDC6_SC0_SCL0_US2_SC0_RES_P_VW (0x000007FFu) +#define VDC6_SC0_SCL0_US2_SC0_RES_P_VW_SHIFT (0u) +#define VDC6_SC0_SCL0_US2_SC0_RES_P_VS (0x07FF0000u) +#define VDC6_SC0_SCL0_US2_SC0_RES_P_VS_SHIFT (16u) +#define VDC6_SC0_SCL0_US3_SC0_RES_P_HW (0x000007FFu) +#define VDC6_SC0_SCL0_US3_SC0_RES_P_HW_SHIFT (0u) +#define VDC6_SC0_SCL0_US3_SC0_RES_P_HS (0x07FF0000u) +#define VDC6_SC0_SCL0_US3_SC0_RES_P_HS_SHIFT (16u) +#define VDC6_SC0_SCL0_US4_SC0_RES_IN_HW (0x000007FFu) +#define VDC6_SC0_SCL0_US4_SC0_RES_IN_HW_SHIFT (0u) +#define VDC6_SC0_SCL0_US4_SC0_RES_IN_VW (0x07FF0000u) +#define VDC6_SC0_SCL0_US4_SC0_RES_IN_VW_SHIFT (16u) +#define VDC6_SC0_SCL0_US5_SC0_RES_US_H_RATIO (0x0000FFFFu) +#define VDC6_SC0_SCL0_US5_SC0_RES_US_H_RATIO_SHIFT (0u) +#define VDC6_SC0_SCL0_US6_SC0_RES_US_HB_INIPHASE (0x00000FFFu) +#define VDC6_SC0_SCL0_US6_SC0_RES_US_HB_INIPHASE_SHIFT (0u) +#define VDC6_SC0_SCL0_US6_SC0_RES_US_HT_INIPHASE (0x0FFF0000u) +#define VDC6_SC0_SCL0_US6_SC0_RES_US_HT_INIPHASE_SHIFT (16u) +#define VDC6_SC0_SCL0_US6_SC0_RES_US_H_INTERPOTYP (0x10000000u) +#define VDC6_SC0_SCL0_US6_SC0_RES_US_H_INTERPOTYP_SHIFT (28u) +#define VDC6_SC0_SCL0_US7_SC0_RES_VCUT (0x000000FFu) +#define VDC6_SC0_SCL0_US7_SC0_RES_VCUT_SHIFT (0u) +#define VDC6_SC0_SCL0_US7_SC0_RES_HCUT (0x0000FF00u) +#define VDC6_SC0_SCL0_US7_SC0_RES_HCUT_SHIFT (8u) +#define VDC6_SC0_SCL0_US8_SC0_RES_DISP_ON (0x00000001u) +#define VDC6_SC0_SCL0_US8_SC0_RES_DISP_ON_SHIFT (0u) +#define VDC6_SC0_SCL0_US8_SC0_RES_IBUS_SYNC_SEL (0x00000010u) +#define VDC6_SC0_SCL0_US8_SC0_RES_IBUS_SYNC_SEL_SHIFT (4u) +#define VDC6_SC0_SCL0_OVR1_SC0_RES_BK_COL_B (0x000000FFu) +#define VDC6_SC0_SCL0_OVR1_SC0_RES_BK_COL_B_SHIFT (0u) +#define VDC6_SC0_SCL0_OVR1_SC0_RES_BK_COL_G (0x0000FF00u) +#define VDC6_SC0_SCL0_OVR1_SC0_RES_BK_COL_G_SHIFT (8u) +#define VDC6_SC0_SCL0_OVR1_SC0_RES_BK_COL_R (0x00FF0000u) +#define VDC6_SC0_SCL0_OVR1_SC0_RES_BK_COL_R_SHIFT (16u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_VEN_A (0x00000001u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_VEN_A_SHIFT (0u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_VEN_B (0x00000010u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_VEN_B_SHIFT (4u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_UPDATE_A (0x00010000u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_UPDATE_A_SHIFT (16u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_UPDATE_B (0x00100000u) +#define VDC6_SC0_SCL1_UPDATE_SC0_SCL1_UPDATE_B_SHIFT (20u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_BST_MD (0x00000001u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_BST_MD_SHIFT (0u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_LOOP (0x00000002u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_LOOP_SHIFT (1u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_MD (0x0000000Cu) +#define VDC6_SC0_SCL1_WR1_SC0_RES_MD_SHIFT (2u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_DS_WR_MD (0x00000070u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_DS_WR_MD_SHIFT (4u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_TB_ADD_MOD (0x00000080u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_TB_ADD_MOD_SHIFT (7u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_WRSWA (0x00070000u) +#define VDC6_SC0_SCL1_WR1_SC0_RES_WRSWA_SHIFT (16u) +#define VDC6_SC0_SCL1_WR2_SC0_RES_BASE (0xFFFFFFFFu) +#define VDC6_SC0_SCL1_WR2_SC0_RES_BASE_SHIFT (0u) +#define VDC6_SC0_SCL1_WR3_SC0_RES_FLM_NUM (0x000003FFu) +#define VDC6_SC0_SCL1_WR3_SC0_RES_FLM_NUM_SHIFT (0u) +#define VDC6_SC0_SCL1_WR3_SC0_RES_LN_OFF (0x7FFF0000u) +#define VDC6_SC0_SCL1_WR3_SC0_RES_LN_OFF_SHIFT (16u) +#define VDC6_SC0_SCL1_WR4_SC0_RES_FLM_OFF (0x007FFFFFu) +#define VDC6_SC0_SCL1_WR4_SC0_RES_FLM_OFF_SHIFT (0u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_WENB (0x00000001u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_WENB_SHIFT (0u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_FLD_SEL (0x00000010u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_FLD_SEL_SHIFT (4u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_FS_RATE (0x00000300u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_FS_RATE_SHIFT (8u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_INTER (0x00001000u) +#define VDC6_SC0_SCL1_WR5_SC0_RES_INTER_SHIFT (12u) +#define VDC6_SC0_SCL1_WR6_SC0_RES_BITDEC_ON (0x00000001u) +#define VDC6_SC0_SCL1_WR6_SC0_RES_BITDEC_ON_SHIFT (0u) +#define VDC6_SC0_SCL1_WR6_SC0_RES_DTH_ON (0x00000010u) +#define VDC6_SC0_SCL1_WR6_SC0_RES_DTH_ON_SHIFT (4u) +#define VDC6_SC0_SCL1_WR7_SC0_RES_FLM_CNT (0x000003FFu) +#define VDC6_SC0_SCL1_WR7_SC0_RES_FLM_CNT_SHIFT (0u) +#define VDC6_SC0_SCL1_WR7_SC0_RES_OVERFLOW (0x00010000u) +#define VDC6_SC0_SCL1_WR7_SC0_RES_OVERFLOW_SHIFT (16u) +#define VDC6_SC0_SCL1_WR8_SC0_RES_BASE_B (0xFFFFFFFFu) +#define VDC6_SC0_SCL1_WR8_SC0_RES_BASE_B_SHIFT (0u) +#define VDC6_SC0_SCL1_WR9_SC0_RES_FLM_NUM_B (0x000003FFu) +#define VDC6_SC0_SCL1_WR9_SC0_RES_FLM_NUM_B_SHIFT (0u) +#define VDC6_SC0_SCL1_WR9_SC0_RES_LN_OFF_B (0x7FFF0000u) +#define VDC6_SC0_SCL1_WR9_SC0_RES_LN_OFF_B_SHIFT (16u) +#define VDC6_SC0_SCL1_WR10_SC0_RES_FLM_OFF_B (0x007FFFFFu) +#define VDC6_SC0_SCL1_WR10_SC0_RES_FLM_OFF_B_SHIFT (0u) +#define VDC6_SC0_SCL1_WR11_SC0_RES_FLM_CNT_B (0x000003FFu) +#define VDC6_SC0_SCL1_WR11_SC0_RES_FLM_CNT_B_SHIFT (0u) +#define VDC6_SC0_SCL1_MON1_SC0_PBUF_NUM (0x00000300u) +#define VDC6_SC0_SCL1_MON1_SC0_PBUF_NUM_SHIFT (8u) +#define VDC6_SC0_SCL1_PBUF0_SC0_PBUF0_ADD (0xFFFFFFFFu) +#define VDC6_SC0_SCL1_PBUF0_SC0_PBUF0_ADD_SHIFT (0u) +#define VDC6_SC0_SCL1_PBUF1_SC0_PBUF1_ADD (0xFFFFFFFFu) +#define VDC6_SC0_SCL1_PBUF1_SC0_PBUF1_ADD_SHIFT (0u) +#define VDC6_SC0_SCL1_PBUF2_SC0_PBUF2_ADD (0xFFFFFFFFu) +#define VDC6_SC0_SCL1_PBUF2_SC0_PBUF2_ADD_SHIFT (0u) +#define VDC6_SC0_SCL1_PBUF3_SC0_PBUF3_ADD (0xFFFFFFFFu) +#define VDC6_SC0_SCL1_PBUF3_SC0_PBUF3_ADD_SHIFT (0u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF0 (0x00000001u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF0_SHIFT (0u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF1 (0x00000100u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF1_SHIFT (8u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF2 (0x00010000u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF2_SHIFT (16u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF3 (0x01000000u) +#define VDC6_SC0_SCL1_PBUF_FLD_SC0_FLD_INF3_SHIFT (24u) +#define VDC6_SC0_SCL1_PBUF_CNT_SC0_PBUF_RST (0x00010000u) +#define VDC6_SC0_SCL1_PBUF_CNT_SC0_PBUF_RST_SHIFT (16u) +#define VDC6_GR0_UPDATE_GR0_IBUS_VEN (0x00000001u) +#define VDC6_GR0_UPDATE_GR0_IBUS_VEN_SHIFT (0u) +#define VDC6_GR0_UPDATE_GR0_P_VEN (0x00000010u) +#define VDC6_GR0_UPDATE_GR0_P_VEN_SHIFT (4u) +#define VDC6_GR0_UPDATE_GR0_UPDATE (0x00000100u) +#define VDC6_GR0_UPDATE_GR0_UPDATE_SHIFT (8u) +#define VDC6_GR0_FLM_RD_GR0_R_ENB (0x00000001u) +#define VDC6_GR0_FLM_RD_GR0_R_ENB_SHIFT (0u) +#define VDC6_GR0_FLM1_GR0_BST_MD (0x00000001u) +#define VDC6_GR0_FLM1_GR0_BST_MD_SHIFT (0u) +#define VDC6_GR0_FLM1_GR0_IMR_FLM_INV (0x00000010u) +#define VDC6_GR0_FLM1_GR0_IMR_FLM_INV_SHIFT (4u) +#define VDC6_GR0_FLM1_GR0_FLM_SEL (0x00000300u) +#define VDC6_GR0_FLM1_GR0_FLM_SEL_SHIFT (8u) +#define VDC6_GR0_FLM1_GR0_LN_OFF_DIR (0x00010000u) +#define VDC6_GR0_FLM1_GR0_LN_OFF_DIR_SHIFT (16u) +#define VDC6_GR0_FLM1_GR0_FLD_SEL (0x80000000u) +#define VDC6_GR0_FLM1_GR0_FLD_SEL_SHIFT (31u) +#define VDC6_GR0_FLM2_GR0_BASE (0xFFFFFFFFu) +#define VDC6_GR0_FLM2_GR0_BASE_SHIFT (0u) +#define VDC6_GR0_FLM3_GR0_FLM_NUM (0x000003FFu) +#define VDC6_GR0_FLM3_GR0_FLM_NUM_SHIFT (0u) +#define VDC6_GR0_FLM3_GR0_LN_OFF (0x7FFF0000u) +#define VDC6_GR0_FLM3_GR0_LN_OFF_SHIFT (16u) +#define VDC6_GR0_FLM3_GR0_FLD_NXT (0x80000000u) +#define VDC6_GR0_FLM3_GR0_FLD_NXT_SHIFT (31u) +#define VDC6_GR0_FLM4_GR0_FLM_OFF (0x007FFFFFu) +#define VDC6_GR0_FLM4_GR0_FLM_OFF_SHIFT (0u) +#define VDC6_GR0_FLM5_GR0_FLM_LOOP (0x000007FFu) +#define VDC6_GR0_FLM5_GR0_FLM_LOOP_SHIFT (0u) +#define VDC6_GR0_FLM5_GR0_FLM_LNUM (0x07FF0000u) +#define VDC6_GR0_FLM5_GR0_FLM_LNUM_SHIFT (16u) +#define VDC6_GR0_FLM6_GR0_STA_POS (0x0000003Fu) +#define VDC6_GR0_FLM6_GR0_STA_POS_SHIFT (0u) +#define VDC6_GR0_FLM6_GR0_CNV444_MD (0x00000100u) +#define VDC6_GR0_FLM6_GR0_CNV444_MD_SHIFT (8u) +#define VDC6_GR0_FLM6_GR0_RDSWA (0x00001C00u) +#define VDC6_GR0_FLM6_GR0_RDSWA_SHIFT (10u) +#define VDC6_GR0_FLM6_GR0_YCC_SWAP (0x0000E000u) +#define VDC6_GR0_FLM6_GR0_YCC_SWAP_SHIFT (13u) +#define VDC6_GR0_FLM6_GR0_HW (0x07FF0000u) +#define VDC6_GR0_FLM6_GR0_HW_SHIFT (16u) +#define VDC6_GR0_FLM6_GR0_FORMAT (0xF0000000u) +#define VDC6_GR0_FLM6_GR0_FORMAT_SHIFT (28u) +#define VDC6_GR0_AB1_GR0_DISP_SEL (0x00000003u) +#define VDC6_GR0_AB1_GR0_DISP_SEL_SHIFT (0u) +#define VDC6_GR0_AB1_GR0_GRC_DISP_ON (0x00000010u) +#define VDC6_GR0_AB1_GR0_GRC_DISP_ON_SHIFT (4u) +#define VDC6_GR0_AB2_GR0_GRC_VW (0x000007FFu) +#define VDC6_GR0_AB2_GR0_GRC_VW_SHIFT (0u) +#define VDC6_GR0_AB2_GR0_GRC_VS (0x07FF0000u) +#define VDC6_GR0_AB2_GR0_GRC_VS_SHIFT (16u) +#define VDC6_GR0_AB3_GR0_GRC_HW (0x000007FFu) +#define VDC6_GR0_AB3_GR0_GRC_HW_SHIFT (0u) +#define VDC6_GR0_AB3_GR0_GRC_HS (0x07FF0000u) +#define VDC6_GR0_AB3_GR0_GRC_HS_SHIFT (16u) +#define VDC6_GR0_AB7_GR0_CK_ON (0x00000001u) +#define VDC6_GR0_AB7_GR0_CK_ON_SHIFT (0u) +#define VDC6_GR0_AB8_GR0_CK_KR (0x000000FFu) +#define VDC6_GR0_AB8_GR0_CK_KR_SHIFT (0u) +#define VDC6_GR0_AB8_GR0_CK_KB (0x0000FF00u) +#define VDC6_GR0_AB8_GR0_CK_KB_SHIFT (8u) +#define VDC6_GR0_AB8_GR0_CK_KG (0x00FF0000u) +#define VDC6_GR0_AB8_GR0_CK_KG_SHIFT (16u) +#define VDC6_GR0_AB8_GR0_CK_KCLUT (0xFF000000u) +#define VDC6_GR0_AB8_GR0_CK_KCLUT_SHIFT (24u) +#define VDC6_GR0_AB9_GR0_CK_R (0x000000FFu) +#define VDC6_GR0_AB9_GR0_CK_R_SHIFT (0u) +#define VDC6_GR0_AB9_GR0_CK_B (0x0000FF00u) +#define VDC6_GR0_AB9_GR0_CK_B_SHIFT (8u) +#define VDC6_GR0_AB9_GR0_CK_G (0x00FF0000u) +#define VDC6_GR0_AB9_GR0_CK_G_SHIFT (16u) +#define VDC6_GR0_AB9_GR0_CK_A (0xFF000000u) +#define VDC6_GR0_AB9_GR0_CK_A_SHIFT (24u) +#define VDC6_GR0_AB10_GR0_R0 (0x000000FFu) +#define VDC6_GR0_AB10_GR0_R0_SHIFT (0u) +#define VDC6_GR0_AB10_GR0_B0 (0x0000FF00u) +#define VDC6_GR0_AB10_GR0_B0_SHIFT (8u) +#define VDC6_GR0_AB10_GR0_G0 (0x00FF0000u) +#define VDC6_GR0_AB10_GR0_G0_SHIFT (16u) +#define VDC6_GR0_AB10_GR0_A0 (0xFF000000u) +#define VDC6_GR0_AB10_GR0_A0_SHIFT (24u) +#define VDC6_GR0_AB11_GR0_R1 (0x000000FFu) +#define VDC6_GR0_AB11_GR0_R1_SHIFT (0u) +#define VDC6_GR0_AB11_GR0_B1 (0x0000FF00u) +#define VDC6_GR0_AB11_GR0_B1_SHIFT (8u) +#define VDC6_GR0_AB11_GR0_G1 (0x00FF0000u) +#define VDC6_GR0_AB11_GR0_G1_SHIFT (16u) +#define VDC6_GR0_AB11_GR0_A1 (0xFF000000u) +#define VDC6_GR0_AB11_GR0_A1_SHIFT (24u) +#define VDC6_GR0_BASE_GR0_BASE_R (0x000000FFu) +#define VDC6_GR0_BASE_GR0_BASE_R_SHIFT (0u) +#define VDC6_GR0_BASE_GR0_BASE_B (0x0000FF00u) +#define VDC6_GR0_BASE_GR0_BASE_B_SHIFT (8u) +#define VDC6_GR0_BASE_GR0_BASE_G (0x00FF0000u) +#define VDC6_GR0_BASE_GR0_BASE_G_SHIFT (16u) +#define VDC6_GR0_CLUT_GR0_CLT_SEL (0x00010000u) +#define VDC6_GR0_CLUT_GR0_CLT_SEL_SHIFT (16u) +#define VDC6_ADJ0_UPDATE_ADJ0_VEN (0x00000001u) +#define VDC6_ADJ0_UPDATE_ADJ0_VEN_SHIFT (0u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_T2 (0x0000001Fu) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_T2_SHIFT (0u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_T1 (0x00001F00u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_T1_SHIFT (8u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_D (0x000F0000u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_D_SHIFT (16u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_ST (0x00F00000u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_ST_SHIFT (20u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_ON (0x01000000u) +#define VDC6_ADJ0_BKSTR_SET_BKSTR_ON_SHIFT (24u) +#define VDC6_ADJ0_ENH_TIM1_ENH_DISP_ON (0x00000001u) +#define VDC6_ADJ0_ENH_TIM1_ENH_DISP_ON_SHIFT (0u) +#define VDC6_ADJ0_ENH_TIM1_ENH_MD (0x00000010u) +#define VDC6_ADJ0_ENH_TIM1_ENH_MD_SHIFT (4u) +#define VDC6_ADJ0_ENH_TIM2_ENH_VW (0x000007FFu) +#define VDC6_ADJ0_ENH_TIM2_ENH_VW_SHIFT (0u) +#define VDC6_ADJ0_ENH_TIM2_ENH_VS (0x07FF0000u) +#define VDC6_ADJ0_ENH_TIM2_ENH_VS_SHIFT (16u) +#define VDC6_ADJ0_ENH_TIM3_ENH_HW (0x000007FFu) +#define VDC6_ADJ0_ENH_TIM3_ENH_HW_SHIFT (0u) +#define VDC6_ADJ0_ENH_TIM3_ENH_HS (0x07FF0000u) +#define VDC6_ADJ0_ENH_TIM3_ENH_HS_SHIFT (16u) +#define VDC6_ADJ0_ENH_SHP1_SHP_H1_CORE (0x0000007Fu) +#define VDC6_ADJ0_ENH_SHP1_SHP_H1_CORE_SHIFT (0u) +#define VDC6_ADJ0_ENH_SHP1_SHP_H_ON (0x00010000u) +#define VDC6_ADJ0_ENH_SHP1_SHP_H_ON_SHIFT (16u) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_GAIN_U (0x000000FFu) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_GAIN_U_SHIFT (0u) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_GAIN_O (0x0000FF00u) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_GAIN_O_SHIFT (8u) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_CLIP_U (0x00FF0000u) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_CLIP_U_SHIFT (16u) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_CLIP_O (0xFF000000u) +#define VDC6_ADJ0_ENH_SHP2_SHP_H1_CLIP_O_SHIFT (24u) +#define VDC6_ADJ0_ENH_SHP3_SHP_H2_CORE (0x0000007Fu) +#define VDC6_ADJ0_ENH_SHP3_SHP_H2_CORE_SHIFT (0u) +#define VDC6_ADJ0_ENH_SHP3_SHP_H2_LPF_SEL (0x00010000u) +#define VDC6_ADJ0_ENH_SHP3_SHP_H2_LPF_SEL_SHIFT (16u) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_GAIN_U (0x000000FFu) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_GAIN_U_SHIFT (0u) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_GAIN_O (0x0000FF00u) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_GAIN_O_SHIFT (8u) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_CLIP_U (0x00FF0000u) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_CLIP_U_SHIFT (16u) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_CLIP_O (0xFF000000u) +#define VDC6_ADJ0_ENH_SHP4_SHP_H2_CLIP_O_SHIFT (24u) +#define VDC6_ADJ0_ENH_SHP5_SHP_H3_CORE (0x0000007Fu) +#define VDC6_ADJ0_ENH_SHP5_SHP_H3_CORE_SHIFT (0u) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_GAIN_U (0x000000FFu) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_GAIN_U_SHIFT (0u) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_GAIN_O (0x0000FF00u) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_GAIN_O_SHIFT (8u) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_CLIP_U (0x00FF0000u) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_CLIP_U_SHIFT (16u) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_CLIP_O (0xFF000000u) +#define VDC6_ADJ0_ENH_SHP6_SHP_H3_CLIP_O_SHIFT (24u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_CORE (0x000000FFu) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_CORE_SHIFT (0u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_GAIN (0x0000FF00u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_GAIN_SHIFT (8u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_INC_ZERO (0x00FF0000u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_INC_ZERO_SHIFT (16u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_LPF_SEL (0x01000000u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H2_LPF_SEL_SHIFT (24u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H_ON (0x80000000u) +#define VDC6_ADJ0_ENH_LTI1_LTI_H_ON_SHIFT (31u) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_CORE (0x000000FFu) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_CORE_SHIFT (0u) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_GAIN (0x0000FF00u) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_GAIN_SHIFT (8u) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_INC_ZERO (0x00FF0000u) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_INC_ZERO_SHIFT (16u) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_MEDIAN_TAP_SEL (0x01000000u) +#define VDC6_ADJ0_ENH_LTI2_LTI_H4_MEDIAN_TAP_SEL_SHIFT (24u) +#define VDC6_ADJ0_MTX_MODE_ADJ0_MTX_MD (0x00000003u) +#define VDC6_ADJ0_MTX_MODE_ADJ0_MTX_MD_SHIFT (0u) +#define VDC6_ADJ0_MTX_YG_ADJ0_ADJ0_MTX_GG (0x000007FFu) +#define VDC6_ADJ0_MTX_YG_ADJ0_ADJ0_MTX_GG_SHIFT (0u) +#define VDC6_ADJ0_MTX_YG_ADJ0_ADJ0_MTX_YG (0x00FF0000u) +#define VDC6_ADJ0_MTX_YG_ADJ0_ADJ0_MTX_YG_SHIFT (16u) +#define VDC6_ADJ0_MTX_YG_ADJ1_ADJ0_MTX_GR (0x000007FFu) +#define VDC6_ADJ0_MTX_YG_ADJ1_ADJ0_MTX_GR_SHIFT (0u) +#define VDC6_ADJ0_MTX_YG_ADJ1_ADJ0_MTX_GB (0x07FF0000u) +#define VDC6_ADJ0_MTX_YG_ADJ1_ADJ0_MTX_GB_SHIFT (16u) +#define VDC6_ADJ0_MTX_CBB_ADJ0_ADJ0_MTX_BG (0x000007FFu) +#define VDC6_ADJ0_MTX_CBB_ADJ0_ADJ0_MTX_BG_SHIFT (0u) +#define VDC6_ADJ0_MTX_CBB_ADJ0_ADJ0_MTX_B (0x00FF0000u) +#define VDC6_ADJ0_MTX_CBB_ADJ0_ADJ0_MTX_B_SHIFT (16u) +#define VDC6_ADJ0_MTX_CBB_ADJ1_ADJ0_MTX_BR (0x000007FFu) +#define VDC6_ADJ0_MTX_CBB_ADJ1_ADJ0_MTX_BR_SHIFT (0u) +#define VDC6_ADJ0_MTX_CBB_ADJ1_ADJ0_MTX_BB (0x07FF0000u) +#define VDC6_ADJ0_MTX_CBB_ADJ1_ADJ0_MTX_BB_SHIFT (16u) +#define VDC6_ADJ0_MTX_CRR_ADJ0_ADJ0_MTX_RG (0x000007FFu) +#define VDC6_ADJ0_MTX_CRR_ADJ0_ADJ0_MTX_RG_SHIFT (0u) +#define VDC6_ADJ0_MTX_CRR_ADJ0_ADJ0_MTX_R (0x00FF0000u) +#define VDC6_ADJ0_MTX_CRR_ADJ0_ADJ0_MTX_R_SHIFT (16u) +#define VDC6_ADJ0_MTX_CRR_ADJ1_ADJ0_MTX_RR (0x000007FFu) +#define VDC6_ADJ0_MTX_CRR_ADJ1_ADJ0_MTX_RR_SHIFT (0u) +#define VDC6_ADJ0_MTX_CRR_ADJ1_ADJ0_MTX_RB (0x07FF0000u) +#define VDC6_ADJ0_MTX_CRR_ADJ1_ADJ0_MTX_RB_SHIFT (16u) +#define VDC6_GR2_UPDATE_GR2_IBUS_VEN (0x00000001u) +#define VDC6_GR2_UPDATE_GR2_IBUS_VEN_SHIFT (0u) +#define VDC6_GR2_UPDATE_GR2_P_VEN (0x00000010u) +#define VDC6_GR2_UPDATE_GR2_P_VEN_SHIFT (4u) +#define VDC6_GR2_UPDATE_GR2_UPDATE (0x00000100u) +#define VDC6_GR2_UPDATE_GR2_UPDATE_SHIFT (8u) +#define VDC6_GR2_FLM_RD_GR2_R_ENB (0x00000001u) +#define VDC6_GR2_FLM_RD_GR2_R_ENB_SHIFT (0u) +#define VDC6_GR2_FLM1_GR2_BST_MD (0x00000001u) +#define VDC6_GR2_FLM1_GR2_BST_MD_SHIFT (0u) +#define VDC6_GR2_FLM1_GR2_FLM_SEL (0x00000300u) +#define VDC6_GR2_FLM1_GR2_FLM_SEL_SHIFT (8u) +#define VDC6_GR2_FLM1_GR2_LN_OFF_DIR (0x00010000u) +#define VDC6_GR2_FLM1_GR2_LN_OFF_DIR_SHIFT (16u) +#define VDC6_GR2_FLM2_GR2_BASE (0xFFFFFFFFu) +#define VDC6_GR2_FLM2_GR2_BASE_SHIFT (0u) +#define VDC6_GR2_FLM3_GR2_FLM_NUM (0x000003FFu) +#define VDC6_GR2_FLM3_GR2_FLM_NUM_SHIFT (0u) +#define VDC6_GR2_FLM3_GR2_LN_OFF (0x7FFF0000u) +#define VDC6_GR2_FLM3_GR2_LN_OFF_SHIFT (16u) +#define VDC6_GR2_FLM4_GR2_FLM_OFF (0x007FFFFFu) +#define VDC6_GR2_FLM4_GR2_FLM_OFF_SHIFT (0u) +#define VDC6_GR2_FLM5_GR2_FLM_LOOP (0x000007FFu) +#define VDC6_GR2_FLM5_GR2_FLM_LOOP_SHIFT (0u) +#define VDC6_GR2_FLM5_GR2_FLM_LNUM (0x07FF0000u) +#define VDC6_GR2_FLM5_GR2_FLM_LNUM_SHIFT (16u) +#define VDC6_GR2_FLM6_GR2_STA_POS (0x0000003Fu) +#define VDC6_GR2_FLM6_GR2_STA_POS_SHIFT (0u) +#define VDC6_GR2_FLM6_GR2_RDSWA (0x00001C00u) +#define VDC6_GR2_FLM6_GR2_RDSWA_SHIFT (10u) +#define VDC6_GR2_FLM6_GR2_HW (0x07FF0000u) +#define VDC6_GR2_FLM6_GR2_HW_SHIFT (16u) +#define VDC6_GR2_FLM6_GR2_FORMAT (0xF0000000u) +#define VDC6_GR2_FLM6_GR2_FORMAT_SHIFT (28u) +#define VDC6_GR2_AB1_GR2_DISP_SEL (0x00000003u) +#define VDC6_GR2_AB1_GR2_DISP_SEL_SHIFT (0u) +#define VDC6_GR2_AB1_GR2_GRC_DISP_ON (0x00000010u) +#define VDC6_GR2_AB1_GR2_GRC_DISP_ON_SHIFT (4u) +#define VDC6_GR2_AB1_GR2_ARC_DISP_ON (0x00000100u) +#define VDC6_GR2_AB1_GR2_ARC_DISP_ON_SHIFT (8u) +#define VDC6_GR2_AB1_GR2_ARC_ON (0x00001000u) +#define VDC6_GR2_AB1_GR2_ARC_ON_SHIFT (12u) +#define VDC6_GR2_AB1_GR2_ACALC_MD (0x00004000u) +#define VDC6_GR2_AB1_GR2_ACALC_MD_SHIFT (14u) +#define VDC6_GR2_AB1_GR2_ARC_MUL (0x00008000u) +#define VDC6_GR2_AB1_GR2_ARC_MUL_SHIFT (15u) +#define VDC6_GR2_AB2_GR2_GRC_VW (0x000007FFu) +#define VDC6_GR2_AB2_GR2_GRC_VW_SHIFT (0u) +#define VDC6_GR2_AB2_GR2_GRC_VS (0x07FF0000u) +#define VDC6_GR2_AB2_GR2_GRC_VS_SHIFT (16u) +#define VDC6_GR2_AB3_GR2_GRC_HW (0x000007FFu) +#define VDC6_GR2_AB3_GR2_GRC_HW_SHIFT (0u) +#define VDC6_GR2_AB3_GR2_GRC_HS (0x07FF0000u) +#define VDC6_GR2_AB3_GR2_GRC_HS_SHIFT (16u) +#define VDC6_GR2_AB4_GR2_ARC_VW (0x000007FFu) +#define VDC6_GR2_AB4_GR2_ARC_VW_SHIFT (0u) +#define VDC6_GR2_AB4_GR2_ARC_VS (0x07FF0000u) +#define VDC6_GR2_AB4_GR2_ARC_VS_SHIFT (16u) +#define VDC6_GR2_AB5_GR2_ARC_HW (0x000007FFu) +#define VDC6_GR2_AB5_GR2_ARC_HW_SHIFT (0u) +#define VDC6_GR2_AB5_GR2_ARC_HS (0x07FF0000u) +#define VDC6_GR2_AB5_GR2_ARC_HS_SHIFT (16u) +#define VDC6_GR2_AB6_GR2_ARC_RATE (0x000000FFu) +#define VDC6_GR2_AB6_GR2_ARC_RATE_SHIFT (0u) +#define VDC6_GR2_AB6_GR2_ARC_COEF (0x00FF0000u) +#define VDC6_GR2_AB6_GR2_ARC_COEF_SHIFT (16u) +#define VDC6_GR2_AB6_GR2_ARC_MODE (0x01000000u) +#define VDC6_GR2_AB6_GR2_ARC_MODE_SHIFT (24u) +#define VDC6_GR2_AB7_GR2_CK_ON (0x00000001u) +#define VDC6_GR2_AB7_GR2_CK_ON_SHIFT (0u) +#define VDC6_GR2_AB7_GR2_ARC_DEF (0x00FF0000u) +#define VDC6_GR2_AB7_GR2_ARC_DEF_SHIFT (16u) +#define VDC6_GR2_AB8_GR2_CK_KR (0x000000FFu) +#define VDC6_GR2_AB8_GR2_CK_KR_SHIFT (0u) +#define VDC6_GR2_AB8_GR2_CK_KB (0x0000FF00u) +#define VDC6_GR2_AB8_GR2_CK_KB_SHIFT (8u) +#define VDC6_GR2_AB8_GR2_CK_KG (0x00FF0000u) +#define VDC6_GR2_AB8_GR2_CK_KG_SHIFT (16u) +#define VDC6_GR2_AB8_GR2_CK_KCLUT (0xFF000000u) +#define VDC6_GR2_AB8_GR2_CK_KCLUT_SHIFT (24u) +#define VDC6_GR2_AB9_GR2_CK_R (0x000000FFu) +#define VDC6_GR2_AB9_GR2_CK_R_SHIFT (0u) +#define VDC6_GR2_AB9_GR2_CK_B (0x0000FF00u) +#define VDC6_GR2_AB9_GR2_CK_B_SHIFT (8u) +#define VDC6_GR2_AB9_GR2_CK_G (0x00FF0000u) +#define VDC6_GR2_AB9_GR2_CK_G_SHIFT (16u) +#define VDC6_GR2_AB9_GR2_CK_A (0xFF000000u) +#define VDC6_GR2_AB9_GR2_CK_A_SHIFT (24u) +#define VDC6_GR2_AB10_GR2_R0 (0x000000FFu) +#define VDC6_GR2_AB10_GR2_R0_SHIFT (0u) +#define VDC6_GR2_AB10_GR2_B0 (0x0000FF00u) +#define VDC6_GR2_AB10_GR2_B0_SHIFT (8u) +#define VDC6_GR2_AB10_GR2_G0 (0x00FF0000u) +#define VDC6_GR2_AB10_GR2_G0_SHIFT (16u) +#define VDC6_GR2_AB10_GR2_A0 (0xFF000000u) +#define VDC6_GR2_AB10_GR2_A0_SHIFT (24u) +#define VDC6_GR2_AB11_GR2_R1 (0x000000FFu) +#define VDC6_GR2_AB11_GR2_R1_SHIFT (0u) +#define VDC6_GR2_AB11_GR2_B1 (0x0000FF00u) +#define VDC6_GR2_AB11_GR2_B1_SHIFT (8u) +#define VDC6_GR2_AB11_GR2_G1 (0x00FF0000u) +#define VDC6_GR2_AB11_GR2_G1_SHIFT (16u) +#define VDC6_GR2_AB11_GR2_A1 (0xFF000000u) +#define VDC6_GR2_AB11_GR2_A1_SHIFT (24u) +#define VDC6_GR2_BASE_GR2_BASE_R (0x000000FFu) +#define VDC6_GR2_BASE_GR2_BASE_R_SHIFT (0u) +#define VDC6_GR2_BASE_GR2_BASE_B (0x0000FF00u) +#define VDC6_GR2_BASE_GR2_BASE_B_SHIFT (8u) +#define VDC6_GR2_BASE_GR2_BASE_G (0x00FF0000u) +#define VDC6_GR2_BASE_GR2_BASE_G_SHIFT (16u) +#define VDC6_GR2_CLUT_GR2_CLT_SEL (0x00010000u) +#define VDC6_GR2_CLUT_GR2_CLT_SEL_SHIFT (16u) +#define VDC6_GR2_MON_GR2_ARC_ST (0x00000001u) +#define VDC6_GR2_MON_GR2_ARC_ST_SHIFT (0u) +#define VDC6_GR3_UPDATE_GR3_IBUS_VEN (0x00000001u) +#define VDC6_GR3_UPDATE_GR3_IBUS_VEN_SHIFT (0u) +#define VDC6_GR3_UPDATE_GR3_P_VEN (0x00000010u) +#define VDC6_GR3_UPDATE_GR3_P_VEN_SHIFT (4u) +#define VDC6_GR3_UPDATE_GR3_UPDATE (0x00000100u) +#define VDC6_GR3_UPDATE_GR3_UPDATE_SHIFT (8u) +#define VDC6_GR3_FLM_RD_GR3_R_ENB (0x00000001u) +#define VDC6_GR3_FLM_RD_GR3_R_ENB_SHIFT (0u) +#define VDC6_GR3_FLM1_GR3_BST_MD (0x00000001u) +#define VDC6_GR3_FLM1_GR3_BST_MD_SHIFT (0u) +#define VDC6_GR3_FLM1_GR3_FLM_SEL (0x00000300u) +#define VDC6_GR3_FLM1_GR3_FLM_SEL_SHIFT (8u) +#define VDC6_GR3_FLM1_GR3_LN_OFF_DIR (0x00010000u) +#define VDC6_GR3_FLM1_GR3_LN_OFF_DIR_SHIFT (16u) +#define VDC6_GR3_FLM2_GR3_BASE (0xFFFFFFFFu) +#define VDC6_GR3_FLM2_GR3_BASE_SHIFT (0u) +#define VDC6_GR3_FLM3_GR3_FLM_NUM (0x000003FFu) +#define VDC6_GR3_FLM3_GR3_FLM_NUM_SHIFT (0u) +#define VDC6_GR3_FLM3_GR3_LN_OFF (0x7FFF0000u) +#define VDC6_GR3_FLM3_GR3_LN_OFF_SHIFT (16u) +#define VDC6_GR3_FLM4_GR3_FLM_OFF (0x007FFFFFu) +#define VDC6_GR3_FLM4_GR3_FLM_OFF_SHIFT (0u) +#define VDC6_GR3_FLM5_GR3_FLM_LOOP (0x000007FFu) +#define VDC6_GR3_FLM5_GR3_FLM_LOOP_SHIFT (0u) +#define VDC6_GR3_FLM5_GR3_FLM_LNUM (0x07FF0000u) +#define VDC6_GR3_FLM5_GR3_FLM_LNUM_SHIFT (16u) +#define VDC6_GR3_FLM6_GR3_STA_POS (0x0000003Fu) +#define VDC6_GR3_FLM6_GR3_STA_POS_SHIFT (0u) +#define VDC6_GR3_FLM6_GR3_RDSWA (0x00001C00u) +#define VDC6_GR3_FLM6_GR3_RDSWA_SHIFT (10u) +#define VDC6_GR3_FLM6_GR3_HW (0x07FF0000u) +#define VDC6_GR3_FLM6_GR3_HW_SHIFT (16u) +#define VDC6_GR3_FLM6_GR3_FORMAT (0xF0000000u) +#define VDC6_GR3_FLM6_GR3_FORMAT_SHIFT (28u) +#define VDC6_GR3_AB1_GR3_DISP_SEL (0x00000003u) +#define VDC6_GR3_AB1_GR3_DISP_SEL_SHIFT (0u) +#define VDC6_GR3_AB1_GR3_GRC_DISP_ON (0x00000010u) +#define VDC6_GR3_AB1_GR3_GRC_DISP_ON_SHIFT (4u) +#define VDC6_GR3_AB1_GR3_ARC_DISP_ON (0x00000100u) +#define VDC6_GR3_AB1_GR3_ARC_DISP_ON_SHIFT (8u) +#define VDC6_GR3_AB1_GR3_ARC_ON (0x00001000u) +#define VDC6_GR3_AB1_GR3_ARC_ON_SHIFT (12u) +#define VDC6_GR3_AB1_GR3_ACALC_MD (0x00004000u) +#define VDC6_GR3_AB1_GR3_ACALC_MD_SHIFT (14u) +#define VDC6_GR3_AB1_GR3_ARC_MUL (0x00008000u) +#define VDC6_GR3_AB1_GR3_ARC_MUL_SHIFT (15u) +#define VDC6_GR3_AB2_GR3_GRC_VW (0x000007FFu) +#define VDC6_GR3_AB2_GR3_GRC_VW_SHIFT (0u) +#define VDC6_GR3_AB2_GR3_GRC_VS (0x07FF0000u) +#define VDC6_GR3_AB2_GR3_GRC_VS_SHIFT (16u) +#define VDC6_GR3_AB3_GR3_GRC_HW (0x000007FFu) +#define VDC6_GR3_AB3_GR3_GRC_HW_SHIFT (0u) +#define VDC6_GR3_AB3_GR3_GRC_HS (0x07FF0000u) +#define VDC6_GR3_AB3_GR3_GRC_HS_SHIFT (16u) +#define VDC6_GR3_AB4_GR3_ARC_VW (0x000007FFu) +#define VDC6_GR3_AB4_GR3_ARC_VW_SHIFT (0u) +#define VDC6_GR3_AB4_GR3_ARC_VS (0x07FF0000u) +#define VDC6_GR3_AB4_GR3_ARC_VS_SHIFT (16u) +#define VDC6_GR3_AB5_GR3_ARC_HW (0x000007FFu) +#define VDC6_GR3_AB5_GR3_ARC_HW_SHIFT (0u) +#define VDC6_GR3_AB5_GR3_ARC_HS (0x07FF0000u) +#define VDC6_GR3_AB5_GR3_ARC_HS_SHIFT (16u) +#define VDC6_GR3_AB6_GR3_ARC_RATE (0x000000FFu) +#define VDC6_GR3_AB6_GR3_ARC_RATE_SHIFT (0u) +#define VDC6_GR3_AB6_GR3_ARC_COEF (0x00FF0000u) +#define VDC6_GR3_AB6_GR3_ARC_COEF_SHIFT (16u) +#define VDC6_GR3_AB6_GR3_ARC_MODE (0x01000000u) +#define VDC6_GR3_AB6_GR3_ARC_MODE_SHIFT (24u) +#define VDC6_GR3_AB7_GR3_CK_ON (0x00000001u) +#define VDC6_GR3_AB7_GR3_CK_ON_SHIFT (0u) +#define VDC6_GR3_AB7_GR3_ARC_DEF (0x00FF0000u) +#define VDC6_GR3_AB7_GR3_ARC_DEF_SHIFT (16u) +#define VDC6_GR3_AB8_GR3_CK_KR (0x000000FFu) +#define VDC6_GR3_AB8_GR3_CK_KR_SHIFT (0u) +#define VDC6_GR3_AB8_GR3_CK_KB (0x0000FF00u) +#define VDC6_GR3_AB8_GR3_CK_KB_SHIFT (8u) +#define VDC6_GR3_AB8_GR3_CK_KG (0x00FF0000u) +#define VDC6_GR3_AB8_GR3_CK_KG_SHIFT (16u) +#define VDC6_GR3_AB8_GR3_CK_KCLUT (0xFF000000u) +#define VDC6_GR3_AB8_GR3_CK_KCLUT_SHIFT (24u) +#define VDC6_GR3_AB9_GR3_CK_R (0x000000FFu) +#define VDC6_GR3_AB9_GR3_CK_R_SHIFT (0u) +#define VDC6_GR3_AB9_GR3_CK_B (0x0000FF00u) +#define VDC6_GR3_AB9_GR3_CK_B_SHIFT (8u) +#define VDC6_GR3_AB9_GR3_CK_G (0x00FF0000u) +#define VDC6_GR3_AB9_GR3_CK_G_SHIFT (16u) +#define VDC6_GR3_AB9_GR3_CK_A (0xFF000000u) +#define VDC6_GR3_AB9_GR3_CK_A_SHIFT (24u) +#define VDC6_GR3_AB10_GR3_R0 (0x000000FFu) +#define VDC6_GR3_AB10_GR3_R0_SHIFT (0u) +#define VDC6_GR3_AB10_GR3_B0 (0x0000FF00u) +#define VDC6_GR3_AB10_GR3_B0_SHIFT (8u) +#define VDC6_GR3_AB10_GR3_G0 (0x00FF0000u) +#define VDC6_GR3_AB10_GR3_G0_SHIFT (16u) +#define VDC6_GR3_AB10_GR3_A0 (0xFF000000u) +#define VDC6_GR3_AB10_GR3_A0_SHIFT (24u) +#define VDC6_GR3_AB11_GR3_R1 (0x000000FFu) +#define VDC6_GR3_AB11_GR3_R1_SHIFT (0u) +#define VDC6_GR3_AB11_GR3_B1 (0x0000FF00u) +#define VDC6_GR3_AB11_GR3_B1_SHIFT (8u) +#define VDC6_GR3_AB11_GR3_G1 (0x00FF0000u) +#define VDC6_GR3_AB11_GR3_G1_SHIFT (16u) +#define VDC6_GR3_AB11_GR3_A1 (0xFF000000u) +#define VDC6_GR3_AB11_GR3_A1_SHIFT (24u) +#define VDC6_GR3_BASE_GR3_BASE_R (0x000000FFu) +#define VDC6_GR3_BASE_GR3_BASE_R_SHIFT (0u) +#define VDC6_GR3_BASE_GR3_BASE_B (0x0000FF00u) +#define VDC6_GR3_BASE_GR3_BASE_B_SHIFT (8u) +#define VDC6_GR3_BASE_GR3_BASE_G (0x00FF0000u) +#define VDC6_GR3_BASE_GR3_BASE_G_SHIFT (16u) +#define VDC6_GR3_CLUT_INT_GR3_LINE (0x000007FFu) +#define VDC6_GR3_CLUT_INT_GR3_LINE_SHIFT (0u) +#define VDC6_GR3_CLUT_INT_GR3_CLT_SEL (0x00010000u) +#define VDC6_GR3_CLUT_INT_GR3_CLT_SEL_SHIFT (16u) +#define VDC6_GR3_MON_GR3_ARC_ST (0x00000001u) +#define VDC6_GR3_MON_GR3_ARC_ST_SHIFT (0u) +#define VDC6_GR3_MON_GR3_LIN_STAT (0x07FF0000u) +#define VDC6_GR3_MON_GR3_LIN_STAT_SHIFT (16u) +#define VDC6_GAM_G_UPDATE_GAM_G_VEN (0x00000001u) +#define VDC6_GAM_G_UPDATE_GAM_G_VEN_SHIFT (0u) +#define VDC6_GAM_SW_GAM_ON (0x00000001u) +#define VDC6_GAM_SW_GAM_ON_SHIFT (0u) +#define VDC6_GAM_G_LUT1_GAM_G_GAIN_01 (0x000007FFu) +#define VDC6_GAM_G_LUT1_GAM_G_GAIN_01_SHIFT (0u) +#define VDC6_GAM_G_LUT1_GAM_G_GAIN_00 (0x07FF0000u) +#define VDC6_GAM_G_LUT1_GAM_G_GAIN_00_SHIFT (16u) +#define VDC6_GAM_G_LUT2_GAM_G_GAIN_03 (0x000007FFu) +#define VDC6_GAM_G_LUT2_GAM_G_GAIN_03_SHIFT (0u) +#define VDC6_GAM_G_LUT2_GAM_G_GAIN_02 (0x07FF0000u) +#define VDC6_GAM_G_LUT2_GAM_G_GAIN_02_SHIFT (16u) +#define VDC6_GAM_G_LUT3_GAM_G_GAIN_05 (0x000007FFu) +#define VDC6_GAM_G_LUT3_GAM_G_GAIN_05_SHIFT (0u) +#define VDC6_GAM_G_LUT3_GAM_G_GAIN_04 (0x07FF0000u) +#define VDC6_GAM_G_LUT3_GAM_G_GAIN_04_SHIFT (16u) +#define VDC6_GAM_G_LUT4_GAM_G_GAIN_07 (0x000007FFu) +#define VDC6_GAM_G_LUT4_GAM_G_GAIN_07_SHIFT (0u) +#define VDC6_GAM_G_LUT4_GAM_G_GAIN_06 (0x07FF0000u) +#define VDC6_GAM_G_LUT4_GAM_G_GAIN_06_SHIFT (16u) +#define VDC6_GAM_G_LUT5_GAM_G_GAIN_09 (0x000007FFu) +#define VDC6_GAM_G_LUT5_GAM_G_GAIN_09_SHIFT (0u) +#define VDC6_GAM_G_LUT5_GAM_G_GAIN_08 (0x07FF0000u) +#define VDC6_GAM_G_LUT5_GAM_G_GAIN_08_SHIFT (16u) +#define VDC6_GAM_G_LUT6_GAM_G_GAIN_11 (0x000007FFu) +#define VDC6_GAM_G_LUT6_GAM_G_GAIN_11_SHIFT (0u) +#define VDC6_GAM_G_LUT6_GAM_G_GAIN_10 (0x07FF0000u) +#define VDC6_GAM_G_LUT6_GAM_G_GAIN_10_SHIFT (16u) +#define VDC6_GAM_G_LUT7_GAM_G_GAIN_13 (0x000007FFu) +#define VDC6_GAM_G_LUT7_GAM_G_GAIN_13_SHIFT (0u) +#define VDC6_GAM_G_LUT7_GAM_G_GAIN_12 (0x07FF0000u) +#define VDC6_GAM_G_LUT7_GAM_G_GAIN_12_SHIFT (16u) +#define VDC6_GAM_G_LUT8_GAM_G_GAIN_15 (0x000007FFu) +#define VDC6_GAM_G_LUT8_GAM_G_GAIN_15_SHIFT (0u) +#define VDC6_GAM_G_LUT8_GAM_G_GAIN_14 (0x07FF0000u) +#define VDC6_GAM_G_LUT8_GAM_G_GAIN_14_SHIFT (16u) +#define VDC6_GAM_G_LUT9_GAM_G_GAIN_17 (0x000007FFu) +#define VDC6_GAM_G_LUT9_GAM_G_GAIN_17_SHIFT (0u) +#define VDC6_GAM_G_LUT9_GAM_G_GAIN_16 (0x07FF0000u) +#define VDC6_GAM_G_LUT9_GAM_G_GAIN_16_SHIFT (16u) +#define VDC6_GAM_G_LUT10_GAM_G_GAIN_19 (0x000007FFu) +#define VDC6_GAM_G_LUT10_GAM_G_GAIN_19_SHIFT (0u) +#define VDC6_GAM_G_LUT10_GAM_G_GAIN_18 (0x07FF0000u) +#define VDC6_GAM_G_LUT10_GAM_G_GAIN_18_SHIFT (16u) +#define VDC6_GAM_G_LUT11_GAM_G_GAIN_21 (0x000007FFu) +#define VDC6_GAM_G_LUT11_GAM_G_GAIN_21_SHIFT (0u) +#define VDC6_GAM_G_LUT11_GAM_G_GAIN_20 (0x07FF0000u) +#define VDC6_GAM_G_LUT11_GAM_G_GAIN_20_SHIFT (16u) +#define VDC6_GAM_G_LUT12_GAM_G_GAIN_23 (0x000007FFu) +#define VDC6_GAM_G_LUT12_GAM_G_GAIN_23_SHIFT (0u) +#define VDC6_GAM_G_LUT12_GAM_G_GAIN_22 (0x07FF0000u) +#define VDC6_GAM_G_LUT12_GAM_G_GAIN_22_SHIFT (16u) +#define VDC6_GAM_G_LUT13_GAM_G_GAIN_25 (0x000007FFu) +#define VDC6_GAM_G_LUT13_GAM_G_GAIN_25_SHIFT (0u) +#define VDC6_GAM_G_LUT13_GAM_G_GAIN_24 (0x07FF0000u) +#define VDC6_GAM_G_LUT13_GAM_G_GAIN_24_SHIFT (16u) +#define VDC6_GAM_G_LUT14_GAM_G_GAIN_27 (0x000007FFu) +#define VDC6_GAM_G_LUT14_GAM_G_GAIN_27_SHIFT (0u) +#define VDC6_GAM_G_LUT14_GAM_G_GAIN_26 (0x07FF0000u) +#define VDC6_GAM_G_LUT14_GAM_G_GAIN_26_SHIFT (16u) +#define VDC6_GAM_G_LUT15_GAM_G_GAIN_29 (0x000007FFu) +#define VDC6_GAM_G_LUT15_GAM_G_GAIN_29_SHIFT (0u) +#define VDC6_GAM_G_LUT15_GAM_G_GAIN_28 (0x07FF0000u) +#define VDC6_GAM_G_LUT15_GAM_G_GAIN_28_SHIFT (16u) +#define VDC6_GAM_G_LUT16_GAM_G_GAIN_31 (0x000007FFu) +#define VDC6_GAM_G_LUT16_GAM_G_GAIN_31_SHIFT (0u) +#define VDC6_GAM_G_LUT16_GAM_G_GAIN_30 (0x07FF0000u) +#define VDC6_GAM_G_LUT16_GAM_G_GAIN_30_SHIFT (16u) +#define VDC6_GAM_G_AREA1_GAM_G_TH_03 (0x000000FFu) +#define VDC6_GAM_G_AREA1_GAM_G_TH_03_SHIFT (0u) +#define VDC6_GAM_G_AREA1_GAM_G_TH_02 (0x0000FF00u) +#define VDC6_GAM_G_AREA1_GAM_G_TH_02_SHIFT (8u) +#define VDC6_GAM_G_AREA1_GAM_G_TH_01 (0x00FF0000u) +#define VDC6_GAM_G_AREA1_GAM_G_TH_01_SHIFT (16u) +#define VDC6_GAM_G_AREA2_GAM_G_TH_07 (0x000000FFu) +#define VDC6_GAM_G_AREA2_GAM_G_TH_07_SHIFT (0u) +#define VDC6_GAM_G_AREA2_GAM_G_TH_06 (0x0000FF00u) +#define VDC6_GAM_G_AREA2_GAM_G_TH_06_SHIFT (8u) +#define VDC6_GAM_G_AREA2_GAM_G_TH_05 (0x00FF0000u) +#define VDC6_GAM_G_AREA2_GAM_G_TH_05_SHIFT (16u) +#define VDC6_GAM_G_AREA2_GAM_G_TH_04 (0xFF000000u) +#define VDC6_GAM_G_AREA2_GAM_G_TH_04_SHIFT (24u) +#define VDC6_GAM_G_AREA3_GAM_G_TH_11 (0x000000FFu) +#define VDC6_GAM_G_AREA3_GAM_G_TH_11_SHIFT (0u) +#define VDC6_GAM_G_AREA3_GAM_G_TH_10 (0x0000FF00u) +#define VDC6_GAM_G_AREA3_GAM_G_TH_10_SHIFT (8u) +#define VDC6_GAM_G_AREA3_GAM_G_TH_09 (0x00FF0000u) +#define VDC6_GAM_G_AREA3_GAM_G_TH_09_SHIFT (16u) +#define VDC6_GAM_G_AREA3_GAM_G_TH_08 (0xFF000000u) +#define VDC6_GAM_G_AREA3_GAM_G_TH_08_SHIFT (24u) +#define VDC6_GAM_G_AREA4_GAM_G_TH_15 (0x000000FFu) +#define VDC6_GAM_G_AREA4_GAM_G_TH_15_SHIFT (0u) +#define VDC6_GAM_G_AREA4_GAM_G_TH_14 (0x0000FF00u) +#define VDC6_GAM_G_AREA4_GAM_G_TH_14_SHIFT (8u) +#define VDC6_GAM_G_AREA4_GAM_G_TH_13 (0x00FF0000u) +#define VDC6_GAM_G_AREA4_GAM_G_TH_13_SHIFT (16u) +#define VDC6_GAM_G_AREA4_GAM_G_TH_12 (0xFF000000u) +#define VDC6_GAM_G_AREA4_GAM_G_TH_12_SHIFT (24u) +#define VDC6_GAM_G_AREA5_GAM_G_TH_19 (0x000000FFu) +#define VDC6_GAM_G_AREA5_GAM_G_TH_19_SHIFT (0u) +#define VDC6_GAM_G_AREA5_GAM_G_TH_18 (0x0000FF00u) +#define VDC6_GAM_G_AREA5_GAM_G_TH_18_SHIFT (8u) +#define VDC6_GAM_G_AREA5_GAM_G_TH_17 (0x00FF0000u) +#define VDC6_GAM_G_AREA5_GAM_G_TH_17_SHIFT (16u) +#define VDC6_GAM_G_AREA5_GAM_G_TH_16 (0xFF000000u) +#define VDC6_GAM_G_AREA5_GAM_G_TH_16_SHIFT (24u) +#define VDC6_GAM_G_AREA6_GAM_G_TH_23 (0x000000FFu) +#define VDC6_GAM_G_AREA6_GAM_G_TH_23_SHIFT (0u) +#define VDC6_GAM_G_AREA6_GAM_G_TH_22 (0x0000FF00u) +#define VDC6_GAM_G_AREA6_GAM_G_TH_22_SHIFT (8u) +#define VDC6_GAM_G_AREA6_GAM_G_TH_21 (0x00FF0000u) +#define VDC6_GAM_G_AREA6_GAM_G_TH_21_SHIFT (16u) +#define VDC6_GAM_G_AREA6_GAM_G_TH_20 (0xFF000000u) +#define VDC6_GAM_G_AREA6_GAM_G_TH_20_SHIFT (24u) +#define VDC6_GAM_G_AREA7_GAM_G_TH_27 (0x000000FFu) +#define VDC6_GAM_G_AREA7_GAM_G_TH_27_SHIFT (0u) +#define VDC6_GAM_G_AREA7_GAM_G_TH_26 (0x0000FF00u) +#define VDC6_GAM_G_AREA7_GAM_G_TH_26_SHIFT (8u) +#define VDC6_GAM_G_AREA7_GAM_G_TH_25 (0x00FF0000u) +#define VDC6_GAM_G_AREA7_GAM_G_TH_25_SHIFT (16u) +#define VDC6_GAM_G_AREA7_GAM_G_TH_24 (0xFF000000u) +#define VDC6_GAM_G_AREA7_GAM_G_TH_24_SHIFT (24u) +#define VDC6_GAM_G_AREA8_GAM_G_TH_31 (0x000000FFu) +#define VDC6_GAM_G_AREA8_GAM_G_TH_31_SHIFT (0u) +#define VDC6_GAM_G_AREA8_GAM_G_TH_30 (0x0000FF00u) +#define VDC6_GAM_G_AREA8_GAM_G_TH_30_SHIFT (8u) +#define VDC6_GAM_G_AREA8_GAM_G_TH_29 (0x00FF0000u) +#define VDC6_GAM_G_AREA8_GAM_G_TH_29_SHIFT (16u) +#define VDC6_GAM_G_AREA8_GAM_G_TH_28 (0xFF000000u) +#define VDC6_GAM_G_AREA8_GAM_G_TH_28_SHIFT (24u) +#define VDC6_GAM_B_UPDATE_GAM_B_VEN (0x00000001u) +#define VDC6_GAM_B_UPDATE_GAM_B_VEN_SHIFT (0u) +#define VDC6_GAM_B_LUT1_GAM_B_GAIN_01 (0x000007FFu) +#define VDC6_GAM_B_LUT1_GAM_B_GAIN_01_SHIFT (0u) +#define VDC6_GAM_B_LUT1_GAM_B_GAIN_00 (0x07FF0000u) +#define VDC6_GAM_B_LUT1_GAM_B_GAIN_00_SHIFT (16u) +#define VDC6_GAM_B_LUT2_GAM_B_GAIN_03 (0x000007FFu) +#define VDC6_GAM_B_LUT2_GAM_B_GAIN_03_SHIFT (0u) +#define VDC6_GAM_B_LUT2_GAM_B_GAIN_02 (0x07FF0000u) +#define VDC6_GAM_B_LUT2_GAM_B_GAIN_02_SHIFT (16u) +#define VDC6_GAM_B_LUT3_GAM_B_GAIN_05 (0x000007FFu) +#define VDC6_GAM_B_LUT3_GAM_B_GAIN_05_SHIFT (0u) +#define VDC6_GAM_B_LUT3_GAM_B_GAIN_04 (0x07FF0000u) +#define VDC6_GAM_B_LUT3_GAM_B_GAIN_04_SHIFT (16u) +#define VDC6_GAM_B_LUT4_GAM_B_GAIN_07 (0x000007FFu) +#define VDC6_GAM_B_LUT4_GAM_B_GAIN_07_SHIFT (0u) +#define VDC6_GAM_B_LUT4_GAM_B_GAIN_06 (0x07FF0000u) +#define VDC6_GAM_B_LUT4_GAM_B_GAIN_06_SHIFT (16u) +#define VDC6_GAM_B_LUT5_GAM_B_GAIN_09 (0x000007FFu) +#define VDC6_GAM_B_LUT5_GAM_B_GAIN_09_SHIFT (0u) +#define VDC6_GAM_B_LUT5_GAM_B_GAIN_08 (0x07FF0000u) +#define VDC6_GAM_B_LUT5_GAM_B_GAIN_08_SHIFT (16u) +#define VDC6_GAM_B_LUT6_GAM_B_GAIN_11 (0x000007FFu) +#define VDC6_GAM_B_LUT6_GAM_B_GAIN_11_SHIFT (0u) +#define VDC6_GAM_B_LUT6_GAM_B_GAIN_10 (0x07FF0000u) +#define VDC6_GAM_B_LUT6_GAM_B_GAIN_10_SHIFT (16u) +#define VDC6_GAM_B_LUT7_GAM_B_GAIN_13 (0x000007FFu) +#define VDC6_GAM_B_LUT7_GAM_B_GAIN_13_SHIFT (0u) +#define VDC6_GAM_B_LUT7_GAM_B_GAIN_12 (0x07FF0000u) +#define VDC6_GAM_B_LUT7_GAM_B_GAIN_12_SHIFT (16u) +#define VDC6_GAM_B_LUT8_GAM_B_GAIN_15 (0x000007FFu) +#define VDC6_GAM_B_LUT8_GAM_B_GAIN_15_SHIFT (0u) +#define VDC6_GAM_B_LUT8_GAM_B_GAIN_14 (0x07FF0000u) +#define VDC6_GAM_B_LUT8_GAM_B_GAIN_14_SHIFT (16u) +#define VDC6_GAM_B_LUT9_GAM_B_GAIN_17 (0x000007FFu) +#define VDC6_GAM_B_LUT9_GAM_B_GAIN_17_SHIFT (0u) +#define VDC6_GAM_B_LUT9_GAM_B_GAIN_16 (0x07FF0000u) +#define VDC6_GAM_B_LUT9_GAM_B_GAIN_16_SHIFT (16u) +#define VDC6_GAM_B_LUT10_GAM_B_GAIN_19 (0x000007FFu) +#define VDC6_GAM_B_LUT10_GAM_B_GAIN_19_SHIFT (0u) +#define VDC6_GAM_B_LUT10_GAM_B_GAIN_18 (0x07FF0000u) +#define VDC6_GAM_B_LUT10_GAM_B_GAIN_18_SHIFT (16u) +#define VDC6_GAM_B_LUT11_GAM_B_GAIN_21 (0x000007FFu) +#define VDC6_GAM_B_LUT11_GAM_B_GAIN_21_SHIFT (0u) +#define VDC6_GAM_B_LUT11_GAM_B_GAIN_20 (0x07FF0000u) +#define VDC6_GAM_B_LUT11_GAM_B_GAIN_20_SHIFT (16u) +#define VDC6_GAM_B_LUT12_GAM_B_GAIN_23 (0x000007FFu) +#define VDC6_GAM_B_LUT12_GAM_B_GAIN_23_SHIFT (0u) +#define VDC6_GAM_B_LUT12_GAM_B_GAIN_22 (0x07FF0000u) +#define VDC6_GAM_B_LUT12_GAM_B_GAIN_22_SHIFT (16u) +#define VDC6_GAM_B_LUT13_GAM_B_GAIN_25 (0x000007FFu) +#define VDC6_GAM_B_LUT13_GAM_B_GAIN_25_SHIFT (0u) +#define VDC6_GAM_B_LUT13_GAM_B_GAIN_24 (0x07FF0000u) +#define VDC6_GAM_B_LUT13_GAM_B_GAIN_24_SHIFT (16u) +#define VDC6_GAM_B_LUT14_GAM_B_GAIN_27 (0x000007FFu) +#define VDC6_GAM_B_LUT14_GAM_B_GAIN_27_SHIFT (0u) +#define VDC6_GAM_B_LUT14_GAM_B_GAIN_26 (0x07FF0000u) +#define VDC6_GAM_B_LUT14_GAM_B_GAIN_26_SHIFT (16u) +#define VDC6_GAM_B_LUT15_GAM_B_GAIN_29 (0x000007FFu) +#define VDC6_GAM_B_LUT15_GAM_B_GAIN_29_SHIFT (0u) +#define VDC6_GAM_B_LUT15_GAM_B_GAIN_28 (0x07FF0000u) +#define VDC6_GAM_B_LUT15_GAM_B_GAIN_28_SHIFT (16u) +#define VDC6_GAM_B_LUT16_GAM_B_GAIN_31 (0x000007FFu) +#define VDC6_GAM_B_LUT16_GAM_B_GAIN_31_SHIFT (0u) +#define VDC6_GAM_B_LUT16_GAM_B_GAIN_30 (0x07FF0000u) +#define VDC6_GAM_B_LUT16_GAM_B_GAIN_30_SHIFT (16u) +#define VDC6_GAM_B_AREA1_GAM_B_TH_03 (0x000000FFu) +#define VDC6_GAM_B_AREA1_GAM_B_TH_03_SHIFT (0u) +#define VDC6_GAM_B_AREA1_GAM_B_TH_02 (0x0000FF00u) +#define VDC6_GAM_B_AREA1_GAM_B_TH_02_SHIFT (8u) +#define VDC6_GAM_B_AREA1_GAM_B_TH_01 (0x00FF0000u) +#define VDC6_GAM_B_AREA1_GAM_B_TH_01_SHIFT (16u) +#define VDC6_GAM_B_AREA2_GAM_B_TH_07 (0x000000FFu) +#define VDC6_GAM_B_AREA2_GAM_B_TH_07_SHIFT (0u) +#define VDC6_GAM_B_AREA2_GAM_B_TH_06 (0x0000FF00u) +#define VDC6_GAM_B_AREA2_GAM_B_TH_06_SHIFT (8u) +#define VDC6_GAM_B_AREA2_GAM_B_TH_05 (0x00FF0000u) +#define VDC6_GAM_B_AREA2_GAM_B_TH_05_SHIFT (16u) +#define VDC6_GAM_B_AREA2_GAM_B_TH_04 (0xFF000000u) +#define VDC6_GAM_B_AREA2_GAM_B_TH_04_SHIFT (24u) +#define VDC6_GAM_B_AREA3_GAM_B_TH_11 (0x000000FFu) +#define VDC6_GAM_B_AREA3_GAM_B_TH_11_SHIFT (0u) +#define VDC6_GAM_B_AREA3_GAM_B_TH_10 (0x0000FF00u) +#define VDC6_GAM_B_AREA3_GAM_B_TH_10_SHIFT (8u) +#define VDC6_GAM_B_AREA3_GAM_B_TH_09 (0x00FF0000u) +#define VDC6_GAM_B_AREA3_GAM_B_TH_09_SHIFT (16u) +#define VDC6_GAM_B_AREA3_GAM_B_TH_08 (0xFF000000u) +#define VDC6_GAM_B_AREA3_GAM_B_TH_08_SHIFT (24u) +#define VDC6_GAM_B_AREA4_GAM_B_TH_15 (0x000000FFu) +#define VDC6_GAM_B_AREA4_GAM_B_TH_15_SHIFT (0u) +#define VDC6_GAM_B_AREA4_GAM_B_TH_14 (0x0000FF00u) +#define VDC6_GAM_B_AREA4_GAM_B_TH_14_SHIFT (8u) +#define VDC6_GAM_B_AREA4_GAM_B_TH_13 (0x00FF0000u) +#define VDC6_GAM_B_AREA4_GAM_B_TH_13_SHIFT (16u) +#define VDC6_GAM_B_AREA4_GAM_B_TH_12 (0xFF000000u) +#define VDC6_GAM_B_AREA4_GAM_B_TH_12_SHIFT (24u) +#define VDC6_GAM_B_AREA5_GAM_B_TH_19 (0x000000FFu) +#define VDC6_GAM_B_AREA5_GAM_B_TH_19_SHIFT (0u) +#define VDC6_GAM_B_AREA5_GAM_B_TH_18 (0x0000FF00u) +#define VDC6_GAM_B_AREA5_GAM_B_TH_18_SHIFT (8u) +#define VDC6_GAM_B_AREA5_GAM_B_TH_17 (0x00FF0000u) +#define VDC6_GAM_B_AREA5_GAM_B_TH_17_SHIFT (16u) +#define VDC6_GAM_B_AREA5_GAM_B_TH_16 (0xFF000000u) +#define VDC6_GAM_B_AREA5_GAM_B_TH_16_SHIFT (24u) +#define VDC6_GAM_B_AREA6_GAM_B_TH_23 (0x000000FFu) +#define VDC6_GAM_B_AREA6_GAM_B_TH_23_SHIFT (0u) +#define VDC6_GAM_B_AREA6_GAM_B_TH_22 (0x0000FF00u) +#define VDC6_GAM_B_AREA6_GAM_B_TH_22_SHIFT (8u) +#define VDC6_GAM_B_AREA6_GAM_B_TH_21 (0x00FF0000u) +#define VDC6_GAM_B_AREA6_GAM_B_TH_21_SHIFT (16u) +#define VDC6_GAM_B_AREA6_GAM_B_TH_20 (0xFF000000u) +#define VDC6_GAM_B_AREA6_GAM_B_TH_20_SHIFT (24u) +#define VDC6_GAM_B_AREA7_GAM_B_TH_27 (0x000000FFu) +#define VDC6_GAM_B_AREA7_GAM_B_TH_27_SHIFT (0u) +#define VDC6_GAM_B_AREA7_GAM_B_TH_26 (0x0000FF00u) +#define VDC6_GAM_B_AREA7_GAM_B_TH_26_SHIFT (8u) +#define VDC6_GAM_B_AREA7_GAM_B_TH_25 (0x00FF0000u) +#define VDC6_GAM_B_AREA7_GAM_B_TH_25_SHIFT (16u) +#define VDC6_GAM_B_AREA7_GAM_B_TH_24 (0xFF000000u) +#define VDC6_GAM_B_AREA7_GAM_B_TH_24_SHIFT (24u) +#define VDC6_GAM_B_AREA8_GAM_B_TH_31 (0x000000FFu) +#define VDC6_GAM_B_AREA8_GAM_B_TH_31_SHIFT (0u) +#define VDC6_GAM_B_AREA8_GAM_B_TH_30 (0x0000FF00u) +#define VDC6_GAM_B_AREA8_GAM_B_TH_30_SHIFT (8u) +#define VDC6_GAM_B_AREA8_GAM_B_TH_29 (0x00FF0000u) +#define VDC6_GAM_B_AREA8_GAM_B_TH_29_SHIFT (16u) +#define VDC6_GAM_B_AREA8_GAM_B_TH_28 (0xFF000000u) +#define VDC6_GAM_B_AREA8_GAM_B_TH_28_SHIFT (24u) +#define VDC6_GAM_R_UPDATE_GAM_R_VEN (0x00000001u) +#define VDC6_GAM_R_UPDATE_GAM_R_VEN_SHIFT (0u) +#define VDC6_GAM_R_LUT1_GAM_R_GAIN_01 (0x000007FFu) +#define VDC6_GAM_R_LUT1_GAM_R_GAIN_01_SHIFT (0u) +#define VDC6_GAM_R_LUT1_GAM_R_GAIN_00 (0x07FF0000u) +#define VDC6_GAM_R_LUT1_GAM_R_GAIN_00_SHIFT (16u) +#define VDC6_GAM_R_LUT2_GAM_R_GAIN_03 (0x000007FFu) +#define VDC6_GAM_R_LUT2_GAM_R_GAIN_03_SHIFT (0u) +#define VDC6_GAM_R_LUT2_GAM_R_GAIN_02 (0x07FF0000u) +#define VDC6_GAM_R_LUT2_GAM_R_GAIN_02_SHIFT (16u) +#define VDC6_GAM_R_LUT3_GAM_R_GAIN_05 (0x000007FFu) +#define VDC6_GAM_R_LUT3_GAM_R_GAIN_05_SHIFT (0u) +#define VDC6_GAM_R_LUT3_GAM_R_GAIN_04 (0x07FF0000u) +#define VDC6_GAM_R_LUT3_GAM_R_GAIN_04_SHIFT (16u) +#define VDC6_GAM_R_LUT4_GAM_R_GAIN_07 (0x000007FFu) +#define VDC6_GAM_R_LUT4_GAM_R_GAIN_07_SHIFT (0u) +#define VDC6_GAM_R_LUT4_GAM_R_GAIN_06 (0x07FF0000u) +#define VDC6_GAM_R_LUT4_GAM_R_GAIN_06_SHIFT (16u) +#define VDC6_GAM_R_LUT5_GAM_R_GAIN_09 (0x000007FFu) +#define VDC6_GAM_R_LUT5_GAM_R_GAIN_09_SHIFT (0u) +#define VDC6_GAM_R_LUT5_GAM_R_GAIN_08 (0x07FF0000u) +#define VDC6_GAM_R_LUT5_GAM_R_GAIN_08_SHIFT (16u) +#define VDC6_GAM_R_LUT6_GAM_R_GAIN_11 (0x000007FFu) +#define VDC6_GAM_R_LUT6_GAM_R_GAIN_11_SHIFT (0u) +#define VDC6_GAM_R_LUT6_GAM_R_GAIN_10 (0x07FF0000u) +#define VDC6_GAM_R_LUT6_GAM_R_GAIN_10_SHIFT (16u) +#define VDC6_GAM_R_LUT7_GAM_R_GAIN_13 (0x000007FFu) +#define VDC6_GAM_R_LUT7_GAM_R_GAIN_13_SHIFT (0u) +#define VDC6_GAM_R_LUT7_GAM_R_GAIN_12 (0x07FF0000u) +#define VDC6_GAM_R_LUT7_GAM_R_GAIN_12_SHIFT (16u) +#define VDC6_GAM_R_LUT8_GAM_R_GAIN_15 (0x000007FFu) +#define VDC6_GAM_R_LUT8_GAM_R_GAIN_15_SHIFT (0u) +#define VDC6_GAM_R_LUT8_GAM_R_GAIN_14 (0x07FF0000u) +#define VDC6_GAM_R_LUT8_GAM_R_GAIN_14_SHIFT (16u) +#define VDC6_GAM_R_LUT9_GAM_R_GAIN_17 (0x000007FFu) +#define VDC6_GAM_R_LUT9_GAM_R_GAIN_17_SHIFT (0u) +#define VDC6_GAM_R_LUT9_GAM_R_GAIN_16 (0x07FF0000u) +#define VDC6_GAM_R_LUT9_GAM_R_GAIN_16_SHIFT (16u) +#define VDC6_GAM_R_LUT10_GAM_R_GAIN_19 (0x000007FFu) +#define VDC6_GAM_R_LUT10_GAM_R_GAIN_19_SHIFT (0u) +#define VDC6_GAM_R_LUT10_GAM_R_GAIN_18 (0x07FF0000u) +#define VDC6_GAM_R_LUT10_GAM_R_GAIN_18_SHIFT (16u) +#define VDC6_GAM_R_LUT11_GAM_R_GAIN_21 (0x000007FFu) +#define VDC6_GAM_R_LUT11_GAM_R_GAIN_21_SHIFT (0u) +#define VDC6_GAM_R_LUT11_GAM_R_GAIN_20 (0x07FF0000u) +#define VDC6_GAM_R_LUT11_GAM_R_GAIN_20_SHIFT (16u) +#define VDC6_GAM_R_LUT12_GAM_R_GAIN_23 (0x000007FFu) +#define VDC6_GAM_R_LUT12_GAM_R_GAIN_23_SHIFT (0u) +#define VDC6_GAM_R_LUT12_GAM_R_GAIN_22 (0x07FF0000u) +#define VDC6_GAM_R_LUT12_GAM_R_GAIN_22_SHIFT (16u) +#define VDC6_GAM_R_LUT13_GAM_R_GAIN_25 (0x000007FFu) +#define VDC6_GAM_R_LUT13_GAM_R_GAIN_25_SHIFT (0u) +#define VDC6_GAM_R_LUT13_GAM_R_GAIN_24 (0x07FF0000u) +#define VDC6_GAM_R_LUT13_GAM_R_GAIN_24_SHIFT (16u) +#define VDC6_GAM_R_LUT14_GAM_R_GAIN_27 (0x000007FFu) +#define VDC6_GAM_R_LUT14_GAM_R_GAIN_27_SHIFT (0u) +#define VDC6_GAM_R_LUT14_GAM_R_GAIN_26 (0x07FF0000u) +#define VDC6_GAM_R_LUT14_GAM_R_GAIN_26_SHIFT (16u) +#define VDC6_GAM_R_LUT15_GAM_R_GAIN_29 (0x000007FFu) +#define VDC6_GAM_R_LUT15_GAM_R_GAIN_29_SHIFT (0u) +#define VDC6_GAM_R_LUT15_GAM_R_GAIN_28 (0x07FF0000u) +#define VDC6_GAM_R_LUT15_GAM_R_GAIN_28_SHIFT (16u) +#define VDC6_GAM_R_LUT16_GAM_R_GAIN_31 (0x000007FFu) +#define VDC6_GAM_R_LUT16_GAM_R_GAIN_31_SHIFT (0u) +#define VDC6_GAM_R_LUT16_GAM_R_GAIN_30 (0x07FF0000u) +#define VDC6_GAM_R_LUT16_GAM_R_GAIN_30_SHIFT (16u) +#define VDC6_GAM_R_AREA1_GAM_R_TH_03 (0x000000FFu) +#define VDC6_GAM_R_AREA1_GAM_R_TH_03_SHIFT (0u) +#define VDC6_GAM_R_AREA1_GAM_R_TH_02 (0x0000FF00u) +#define VDC6_GAM_R_AREA1_GAM_R_TH_02_SHIFT (8u) +#define VDC6_GAM_R_AREA1_GAM_R_TH_01 (0x00FF0000u) +#define VDC6_GAM_R_AREA1_GAM_R_TH_01_SHIFT (16u) +#define VDC6_GAM_R_AREA2_GAM_R_TH_07 (0x000000FFu) +#define VDC6_GAM_R_AREA2_GAM_R_TH_07_SHIFT (0u) +#define VDC6_GAM_R_AREA2_GAM_R_TH_06 (0x0000FF00u) +#define VDC6_GAM_R_AREA2_GAM_R_TH_06_SHIFT (8u) +#define VDC6_GAM_R_AREA2_GAM_R_TH_05 (0x00FF0000u) +#define VDC6_GAM_R_AREA2_GAM_R_TH_05_SHIFT (16u) +#define VDC6_GAM_R_AREA2_GAM_R_TH_04 (0xFF000000u) +#define VDC6_GAM_R_AREA2_GAM_R_TH_04_SHIFT (24u) +#define VDC6_GAM_R_AREA3_GAM_R_TH_11 (0x000000FFu) +#define VDC6_GAM_R_AREA3_GAM_R_TH_11_SHIFT (0u) +#define VDC6_GAM_R_AREA3_GAM_R_TH_10 (0x0000FF00u) +#define VDC6_GAM_R_AREA3_GAM_R_TH_10_SHIFT (8u) +#define VDC6_GAM_R_AREA3_GAM_R_TH_09 (0x00FF0000u) +#define VDC6_GAM_R_AREA3_GAM_R_TH_09_SHIFT (16u) +#define VDC6_GAM_R_AREA3_GAM_R_TH_08 (0xFF000000u) +#define VDC6_GAM_R_AREA3_GAM_R_TH_08_SHIFT (24u) +#define VDC6_GAM_R_AREA4_GAM_R_TH_15 (0x000000FFu) +#define VDC6_GAM_R_AREA4_GAM_R_TH_15_SHIFT (0u) +#define VDC6_GAM_R_AREA4_GAM_R_TH_14 (0x0000FF00u) +#define VDC6_GAM_R_AREA4_GAM_R_TH_14_SHIFT (8u) +#define VDC6_GAM_R_AREA4_GAM_R_TH_13 (0x00FF0000u) +#define VDC6_GAM_R_AREA4_GAM_R_TH_13_SHIFT (16u) +#define VDC6_GAM_R_AREA4_GAM_R_TH_12 (0xFF000000u) +#define VDC6_GAM_R_AREA4_GAM_R_TH_12_SHIFT (24u) +#define VDC6_GAM_R_AREA5_GAM_R_TH_19 (0x000000FFu) +#define VDC6_GAM_R_AREA5_GAM_R_TH_19_SHIFT (0u) +#define VDC6_GAM_R_AREA5_GAM_R_TH_18 (0x0000FF00u) +#define VDC6_GAM_R_AREA5_GAM_R_TH_18_SHIFT (8u) +#define VDC6_GAM_R_AREA5_GAM_R_TH_17 (0x00FF0000u) +#define VDC6_GAM_R_AREA5_GAM_R_TH_17_SHIFT (16u) +#define VDC6_GAM_R_AREA5_GAM_R_TH_16 (0xFF000000u) +#define VDC6_GAM_R_AREA5_GAM_R_TH_16_SHIFT (24u) +#define VDC6_GAM_R_AREA6_GAM_R_TH_23 (0x000000FFu) +#define VDC6_GAM_R_AREA6_GAM_R_TH_23_SHIFT (0u) +#define VDC6_GAM_R_AREA6_GAM_R_TH_22 (0x0000FF00u) +#define VDC6_GAM_R_AREA6_GAM_R_TH_22_SHIFT (8u) +#define VDC6_GAM_R_AREA6_GAM_R_TH_21 (0x00FF0000u) +#define VDC6_GAM_R_AREA6_GAM_R_TH_21_SHIFT (16u) +#define VDC6_GAM_R_AREA6_GAM_R_TH_20 (0xFF000000u) +#define VDC6_GAM_R_AREA6_GAM_R_TH_20_SHIFT (24u) +#define VDC6_GAM_R_AREA7_GAM_R_TH_27 (0x000000FFu) +#define VDC6_GAM_R_AREA7_GAM_R_TH_27_SHIFT (0u) +#define VDC6_GAM_R_AREA7_GAM_R_TH_26 (0x0000FF00u) +#define VDC6_GAM_R_AREA7_GAM_R_TH_26_SHIFT (8u) +#define VDC6_GAM_R_AREA7_GAM_R_TH_25 (0x00FF0000u) +#define VDC6_GAM_R_AREA7_GAM_R_TH_25_SHIFT (16u) +#define VDC6_GAM_R_AREA7_GAM_R_TH_24 (0xFF000000u) +#define VDC6_GAM_R_AREA7_GAM_R_TH_24_SHIFT (24u) +#define VDC6_GAM_R_AREA8_GAM_R_TH_31 (0x000000FFu) +#define VDC6_GAM_R_AREA8_GAM_R_TH_31_SHIFT (0u) +#define VDC6_GAM_R_AREA8_GAM_R_TH_30 (0x0000FF00u) +#define VDC6_GAM_R_AREA8_GAM_R_TH_30_SHIFT (8u) +#define VDC6_GAM_R_AREA8_GAM_R_TH_29 (0x00FF0000u) +#define VDC6_GAM_R_AREA8_GAM_R_TH_29_SHIFT (16u) +#define VDC6_GAM_R_AREA8_GAM_R_TH_28 (0xFF000000u) +#define VDC6_GAM_R_AREA8_GAM_R_TH_28_SHIFT (24u) +#define VDC6_TCON_UPDATE_TCON_VEN (0x00000001u) +#define VDC6_TCON_UPDATE_TCON_VEN_SHIFT (0u) +#define VDC6_TCON_TIM_TCON_OFFSET (0x000007FFu) +#define VDC6_TCON_TIM_TCON_OFFSET_SHIFT (0u) +#define VDC6_TCON_TIM_TCON_HALF (0x07FF0000u) +#define VDC6_TCON_TIM_TCON_HALF_SHIFT (16u) +#define VDC6_TCON_TIM_STVA1_TCON_STVA_VW (0x000007FFu) +#define VDC6_TCON_TIM_STVA1_TCON_STVA_VW_SHIFT (0u) +#define VDC6_TCON_TIM_STVA1_TCON_STVA_VS (0x07FF0000u) +#define VDC6_TCON_TIM_STVA1_TCON_STVA_VS_SHIFT (16u) +#define VDC6_TCON_TIM_STVA2_TCON_STVA_SEL (0x00000007u) +#define VDC6_TCON_TIM_STVA2_TCON_STVA_SEL_SHIFT (0u) +#define VDC6_TCON_TIM_STVA2_TCON_STVA_INV (0x00000010u) +#define VDC6_TCON_TIM_STVA2_TCON_STVA_INV_SHIFT (4u) +#define VDC6_TCON_TIM_STVB1_TCON_STVB_VW (0x000007FFu) +#define VDC6_TCON_TIM_STVB1_TCON_STVB_VW_SHIFT (0u) +#define VDC6_TCON_TIM_STVB1_TCON_STVB_VS (0x07FF0000u) +#define VDC6_TCON_TIM_STVB1_TCON_STVB_VS_SHIFT (16u) +#define VDC6_TCON_TIM_STVB2_TCON_STVB_SEL (0x00000007u) +#define VDC6_TCON_TIM_STVB2_TCON_STVB_SEL_SHIFT (0u) +#define VDC6_TCON_TIM_STVB2_TCON_STVB_INV (0x00000010u) +#define VDC6_TCON_TIM_STVB2_TCON_STVB_INV_SHIFT (4u) +#define VDC6_TCON_TIM_STH1_TCON_STH_HW (0x000007FFu) +#define VDC6_TCON_TIM_STH1_TCON_STH_HW_SHIFT (0u) +#define VDC6_TCON_TIM_STH1_TCON_STH_HS (0x07FF0000u) +#define VDC6_TCON_TIM_STH1_TCON_STH_HS_SHIFT (16u) +#define VDC6_TCON_TIM_STH2_TCON_STH_SEL (0x00000007u) +#define VDC6_TCON_TIM_STH2_TCON_STH_SEL_SHIFT (0u) +#define VDC6_TCON_TIM_STH2_TCON_STH_INV (0x00000010u) +#define VDC6_TCON_TIM_STH2_TCON_STH_INV_SHIFT (4u) +#define VDC6_TCON_TIM_STH2_TCON_STH_HS_SEL (0x00000100u) +#define VDC6_TCON_TIM_STH2_TCON_STH_HS_SEL_SHIFT (8u) +#define VDC6_TCON_TIM_STB1_TCON_STB_HW (0x000007FFu) +#define VDC6_TCON_TIM_STB1_TCON_STB_HW_SHIFT (0u) +#define VDC6_TCON_TIM_STB1_TCON_STB_HS (0x07FF0000u) +#define VDC6_TCON_TIM_STB1_TCON_STB_HS_SHIFT (16u) +#define VDC6_TCON_TIM_STB2_TCON_STB_SEL (0x00000007u) +#define VDC6_TCON_TIM_STB2_TCON_STB_SEL_SHIFT (0u) +#define VDC6_TCON_TIM_STB2_TCON_STB_INV (0x00000010u) +#define VDC6_TCON_TIM_STB2_TCON_STB_INV_SHIFT (4u) +#define VDC6_TCON_TIM_STB2_TCON_STB_HS_SEL (0x00000100u) +#define VDC6_TCON_TIM_STB2_TCON_STB_HS_SEL_SHIFT (8u) +#define VDC6_TCON_TIM_CPV1_TCON_CPV_HW (0x000007FFu) +#define VDC6_TCON_TIM_CPV1_TCON_CPV_HW_SHIFT (0u) +#define VDC6_TCON_TIM_CPV1_TCON_CPV_HS (0x07FF0000u) +#define VDC6_TCON_TIM_CPV1_TCON_CPV_HS_SHIFT (16u) +#define VDC6_TCON_TIM_CPV2_TCON_CPV_SEL (0x00000007u) +#define VDC6_TCON_TIM_CPV2_TCON_CPV_SEL_SHIFT (0u) +#define VDC6_TCON_TIM_CPV2_TCON_CPV_INV (0x00000010u) +#define VDC6_TCON_TIM_CPV2_TCON_CPV_INV_SHIFT (4u) +#define VDC6_TCON_TIM_CPV2_TCON_CPV_HS_SEL (0x00000100u) +#define VDC6_TCON_TIM_CPV2_TCON_CPV_HS_SEL_SHIFT (8u) +#define VDC6_TCON_TIM_POLA1_TCON_POLA_HW (0x000007FFu) +#define VDC6_TCON_TIM_POLA1_TCON_POLA_HW_SHIFT (0u) +#define VDC6_TCON_TIM_POLA1_TCON_POLA_HS (0x07FF0000u) +#define VDC6_TCON_TIM_POLA1_TCON_POLA_HS_SHIFT (16u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_SEL (0x00000007u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_SEL_SHIFT (0u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_INV (0x00000010u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_INV_SHIFT (4u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_HS_SEL (0x00000100u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_HS_SEL_SHIFT (8u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_MD (0x00003000u) +#define VDC6_TCON_TIM_POLA2_TCON_POLA_MD_SHIFT (12u) +#define VDC6_TCON_TIM_POLB1_TCON_POLB_HW (0x000007FFu) +#define VDC6_TCON_TIM_POLB1_TCON_POLB_HW_SHIFT (0u) +#define VDC6_TCON_TIM_POLB1_TCON_POLB_HS (0x07FF0000u) +#define VDC6_TCON_TIM_POLB1_TCON_POLB_HS_SHIFT (16u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_SEL (0x00000007u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_SEL_SHIFT (0u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_INV (0x00000010u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_INV_SHIFT (4u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_HS_SEL (0x00000100u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_HS_SEL_SHIFT (8u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_MD (0x00003000u) +#define VDC6_TCON_TIM_POLB2_TCON_POLB_MD_SHIFT (12u) +#define VDC6_TCON_TIM_DE_TCON_DE_INV (0x00000001u) +#define VDC6_TCON_TIM_DE_TCON_DE_INV_SHIFT (0u) +#define VDC6_OUT_UPDATE_OUTCNT_VEN (0x00000001u) +#define VDC6_OUT_UPDATE_OUTCNT_VEN_SHIFT (0u) +#define VDC6_OUT_SET_OUT_PHASE (0x00000003u) +#define VDC6_OUT_SET_OUT_PHASE_SHIFT (0u) +#define VDC6_OUT_SET_OUT_DIR_SEL (0x00000010u) +#define VDC6_OUT_SET_OUT_DIR_SEL_SHIFT (4u) +#define VDC6_OUT_SET_OUT_FRQ_SEL (0x00000300u) +#define VDC6_OUT_SET_OUT_FRQ_SEL_SHIFT (8u) +#define VDC6_OUT_SET_OUT_FORMAT (0x00003000u) +#define VDC6_OUT_SET_OUT_FORMAT_SHIFT (12u) +#define VDC6_OUT_SET_OUT_SWAP_ON (0x01000000u) +#define VDC6_OUT_SET_OUT_SWAP_ON_SHIFT (24u) +#define VDC6_OUT_SET_OUT_ENDIAN_ON (0x10000000u) +#define VDC6_OUT_SET_OUT_ENDIAN_ON_SHIFT (28u) +#define VDC6_OUT_BRIGHT1_PBRT_G (0x000003FFu) +#define VDC6_OUT_BRIGHT1_PBRT_G_SHIFT (0u) +#define VDC6_OUT_BRIGHT2_PBRT_R (0x000003FFu) +#define VDC6_OUT_BRIGHT2_PBRT_R_SHIFT (0u) +#define VDC6_OUT_BRIGHT2_PBRT_B (0x03FF0000u) +#define VDC6_OUT_BRIGHT2_PBRT_B_SHIFT (16u) +#define VDC6_OUT_CONTRAST_CONT_R (0x000000FFu) +#define VDC6_OUT_CONTRAST_CONT_R_SHIFT (0u) +#define VDC6_OUT_CONTRAST_CONT_B (0x0000FF00u) +#define VDC6_OUT_CONTRAST_CONT_B_SHIFT (8u) +#define VDC6_OUT_CONTRAST_CONT_G (0x00FF0000u) +#define VDC6_OUT_CONTRAST_CONT_G_SHIFT (16u) +#define VDC6_OUT_PDTHA_PDTH_PD (0x00000003u) +#define VDC6_OUT_PDTHA_PDTH_PD_SHIFT (0u) +#define VDC6_OUT_PDTHA_PDTH_PC (0x00000030u) +#define VDC6_OUT_PDTHA_PDTH_PC_SHIFT (4u) +#define VDC6_OUT_PDTHA_PDTH_PB (0x00000300u) +#define VDC6_OUT_PDTHA_PDTH_PB_SHIFT (8u) +#define VDC6_OUT_PDTHA_PDTH_PA (0x00003000u) +#define VDC6_OUT_PDTHA_PDTH_PA_SHIFT (12u) +#define VDC6_OUT_PDTHA_PDTH_FORMAT (0x00030000u) +#define VDC6_OUT_PDTHA_PDTH_FORMAT_SHIFT (16u) +#define VDC6_OUT_PDTHA_PDTH_SEL (0x00300000u) +#define VDC6_OUT_PDTHA_PDTH_SEL_SHIFT (20u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_POLB_EDGE (0x00000001u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_POLB_EDGE_SHIFT (0u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_POLA_EDGE (0x00000002u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_POLA_EDGE_SHIFT (1u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_CPV_EDGE (0x00000004u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_CPV_EDGE_SHIFT (2u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STB_EDGE (0x00000008u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STB_EDGE_SHIFT (3u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STH_EDGE (0x00000010u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STH_EDGE_SHIFT (4u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STVB_EDGE (0x00000020u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STVB_EDGE_SHIFT (5u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STVA_EDGE (0x00000040u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_STVA_EDGE_SHIFT (6u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_LCD_EDGE (0x00000100u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_LCD_EDGE_SHIFT (8u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_FRONT_GAM (0x00001000u) +#define VDC6_OUT_CLK_PHASE_OUTCNT_FRONT_GAM_SHIFT (12u) +#define VDC6_SYSCNT_INT1_INT_STA0 (0x00000001u) +#define VDC6_SYSCNT_INT1_INT_STA0_SHIFT (0u) +#define VDC6_SYSCNT_INT1_INT_STA1 (0x00000010u) +#define VDC6_SYSCNT_INT1_INT_STA1_SHIFT (4u) +#define VDC6_SYSCNT_INT1_INT_STA2 (0x00000100u) +#define VDC6_SYSCNT_INT1_INT_STA2_SHIFT (8u) +#define VDC6_SYSCNT_INT1_INT_STA3 (0x00001000u) +#define VDC6_SYSCNT_INT1_INT_STA3_SHIFT (12u) +#define VDC6_SYSCNT_INT1_INT_STA4 (0x00010000u) +#define VDC6_SYSCNT_INT1_INT_STA4_SHIFT (16u) +#define VDC6_SYSCNT_INT1_INT_STA5 (0x00100000u) +#define VDC6_SYSCNT_INT1_INT_STA5_SHIFT (20u) +#define VDC6_SYSCNT_INT1_INT_STA6 (0x01000000u) +#define VDC6_SYSCNT_INT1_INT_STA6_SHIFT (24u) +#define VDC6_SYSCNT_INT1_INT_STA7 (0x10000000u) +#define VDC6_SYSCNT_INT1_INT_STA7_SHIFT (28u) +#define VDC6_SYSCNT_INT2_INT_STA8 (0x00000001u) +#define VDC6_SYSCNT_INT2_INT_STA8_SHIFT (0u) +#define VDC6_SYSCNT_INT2_INT_STA9 (0x00000010u) +#define VDC6_SYSCNT_INT2_INT_STA9_SHIFT (4u) +#define VDC6_SYSCNT_INT4_INT_OUT0_ON (0x00000001u) +#define VDC6_SYSCNT_INT4_INT_OUT0_ON_SHIFT (0u) +#define VDC6_SYSCNT_INT4_INT_OUT1_ON (0x00000010u) +#define VDC6_SYSCNT_INT4_INT_OUT1_ON_SHIFT (4u) +#define VDC6_SYSCNT_INT4_INT_OUT2_ON (0x00000100u) +#define VDC6_SYSCNT_INT4_INT_OUT2_ON_SHIFT (8u) +#define VDC6_SYSCNT_INT4_INT_OUT3_ON (0x00001000u) +#define VDC6_SYSCNT_INT4_INT_OUT3_ON_SHIFT (12u) +#define VDC6_SYSCNT_INT4_INT_OUT4_ON (0x00010000u) +#define VDC6_SYSCNT_INT4_INT_OUT4_ON_SHIFT (16u) +#define VDC6_SYSCNT_INT4_INT_OUT5_ON (0x00100000u) +#define VDC6_SYSCNT_INT4_INT_OUT5_ON_SHIFT (20u) +#define VDC6_SYSCNT_INT4_INT_OUT6_ON (0x01000000u) +#define VDC6_SYSCNT_INT4_INT_OUT6_ON_SHIFT (24u) +#define VDC6_SYSCNT_INT4_INT_OUT7_ON (0x10000000u) +#define VDC6_SYSCNT_INT4_INT_OUT7_ON_SHIFT (28u) +#define VDC6_SYSCNT_INT5_INT_OUT8_ON (0x00000001u) +#define VDC6_SYSCNT_INT5_INT_OUT8_ON_SHIFT (0u) +#define VDC6_SYSCNT_INT5_INT_OUT9_ON (0x00000010u) +#define VDC6_SYSCNT_INT5_INT_OUT9_ON_SHIFT (4u) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_DCDR (0x003Fu) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_DCDR_SHIFT (0u) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_ICKEN (0x0100u) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_ICKEN_SHIFT (8u) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_OCKSEL (0x0C00u) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_OCKSEL_SHIFT (10u) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_ICKSEL (0x3000u) +#define VDC6_SYSCNT_PANEL_CLK_PANEL_ICKSEL_SHIFT (12u) +#define VDC6_SYSCNT_CLUT_GR0_CLT_SEL_ST (0x0001u) +#define VDC6_SYSCNT_CLUT_GR0_CLT_SEL_ST_SHIFT (0u) +#define VDC6_SYSCNT_CLUT_GR2_CLT_SEL_ST (0x0100u) +#define VDC6_SYSCNT_CLUT_GR2_CLT_SEL_ST_SHIFT (8u) +#define VDC6_SYSCNT_CLUT_GR3_CLT_SEL_ST (0x1000u) +#define VDC6_SYSCNT_CLUT_GR3_CLT_SEL_ST_SHIFT (12u) +#define VDC6_GR_VIN_UPDATE_GR_VIN_P_VEN (0x00000010u) +#define VDC6_GR_VIN_UPDATE_GR_VIN_P_VEN_SHIFT (4u) +#define VDC6_GR_VIN_UPDATE_GR_VIN_UPDATE (0x00000100u) +#define VDC6_GR_VIN_UPDATE_GR_VIN_UPDATE_SHIFT (8u) +#define VDC6_GR_VIN_AB1_GR_VIN_DISP_SEL (0x00000003u) +#define VDC6_GR_VIN_AB1_GR_VIN_DISP_SEL_SHIFT (0u) +#define VDC6_GR_VIN_AB1_GR_VIN_SCL_UND_SEL (0x00000004u) +#define VDC6_GR_VIN_AB1_GR_VIN_SCL_UND_SEL_SHIFT (2u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vin_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vin_iobitmask.h new file mode 100644 index 0000000..ed63b13 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/vin_iobitmask.h @@ -0,0 +1,272 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef VIN_IOBITMASK_H +#define VIN_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define VIN_V0MC_ME (0x00000001u) +#define VIN_V0MC_ME_SHIFT (0u) +#define VIN_V0MC_BPS (0x00000002u) +#define VIN_V0MC_BPS_SHIFT (1u) +#define VIN_V0MC_IM (0x00000018u) +#define VIN_V0MC_IM_SHIFT (3u) +#define VIN_V0MC_EN (0x00000040u) +#define VIN_V0MC_EN_SHIFT (6u) +#define VIN_V0MC_DC (0x0000C000u) +#define VIN_V0MC_DC_SHIFT (14u) +#define VIN_V0MC_INF (0x00070000u) +#define VIN_V0MC_INF_SHIFT (16u) +#define VIN_V0MC_YCAL (0x00080000u) +#define VIN_V0MC_YCAL_SHIFT (19u) +#define VIN_V0MC_LUTE (0x00100000u) +#define VIN_V0MC_LUTE_SHIFT (20u) +#define VIN_V0MC_SCLE (0x04000000u) +#define VIN_V0MC_SCLE_SHIFT (26u) +#define VIN_V0MC_CLP (0x30000000u) +#define VIN_V0MC_CLP_SHIFT (28u) +#define VIN_V0MS_CA (0x00000001u) +#define VIN_V0MS_CA_SHIFT (0u) +#define VIN_V0MS_AV (0x00000002u) +#define VIN_V0MS_AV_SHIFT (1u) +#define VIN_V0MS_FS (0x00000004u) +#define VIN_V0MS_FS_SHIFT (2u) +#define VIN_V0MS_FBS (0x00000018u) +#define VIN_V0MS_FBS_SHIFT (3u) +#define VIN_V0FC_SC (0x00000001u) +#define VIN_V0FC_SC_SHIFT (0u) +#define VIN_V0FC_CC (0x00000002u) +#define VIN_V0FC_CC_SHIFT (1u) +#define VIN_V0SLPrC_SLPrC (0x000007FFu) +#define VIN_V0SLPrC_SLPrC_SHIFT (0u) +#define VIN_V0ELPrC_ELPrC (0x000007FFu) +#define VIN_V0ELPrC_ELPrC_SHIFT (0u) +#define VIN_V0SPPrC_SPPrC (0x000007FFu) +#define VIN_V0SPPrC_SPPrC_SHIFT (0u) +#define VIN_V0EPPrC_EPPrC (0x000007FFu) +#define VIN_V0EPPrC_EPPrC_SHIFT (0u) +#define VIN_V0CSI_IFMD_DES0 (0x02000000u) +#define VIN_V0CSI_IFMD_DES0_SHIFT (25u) +#define VIN_V0IS_IS (0x00001FF0u) +#define VIN_V0IS_IS_SHIFT (4u) +#define VIN_V0MB1_MB1 (0xFFFFFF80u) +#define VIN_V0MB1_MB1_SHIFT (7u) +#define VIN_V0MB2_MB2 (0xFFFFFF80u) +#define VIN_V0MB2_MB2_SHIFT (7u) +#define VIN_V0MB3_MB3 (0xFFFFFF80u) +#define VIN_V0MB3_MB3_SHIFT (7u) +#define VIN_V0LC_LC (0x00000FFFu) +#define VIN_V0LC_LC_SHIFT (0u) +#define VIN_V0IE_FOE (0x00000001u) +#define VIN_V0IE_FOE_SHIFT (0u) +#define VIN_V0IE_EFE (0x00000002u) +#define VIN_V0IE_EFE_SHIFT (1u) +#define VIN_V0IE_SIE (0x00000004u) +#define VIN_V0IE_SIE_SHIFT (2u) +#define VIN_V0IE_FIE (0x00000010u) +#define VIN_V0IE_FIE_SHIFT (4u) +#define VIN_V0IE_VRE (0x00010000u) +#define VIN_V0IE_VRE_SHIFT (16u) +#define VIN_V0IE_VFE (0x00020000u) +#define VIN_V0IE_VFE_SHIFT (17u) +#define VIN_V0IE_FIE2 (0x80000000u) +#define VIN_V0IE_FIE2_SHIFT (31u) +#define VIN_V0INTS_FOS (0x00000001u) +#define VIN_V0INTS_FOS_SHIFT (0u) +#define VIN_V0INTS_EFS (0x00000002u) +#define VIN_V0INTS_EFS_SHIFT (1u) +#define VIN_V0INTS_SIS (0x00000004u) +#define VIN_V0INTS_SIS_SHIFT (2u) +#define VIN_V0INTS_FIS (0x00000010u) +#define VIN_V0INTS_FIS_SHIFT (4u) +#define VIN_V0INTS_VRS (0x00010000u) +#define VIN_V0INTS_VRS_SHIFT (16u) +#define VIN_V0INTS_VFS (0x00020000u) +#define VIN_V0INTS_VFS_SHIFT (17u) +#define VIN_V0INTS_FIS2 (0x80000000u) +#define VIN_V0INTS_FIS2_SHIFT (31u) +#define VIN_V0SI_SI (0x000007FFu) +#define VIN_V0SI_SI_SHIFT (0u) +#define VIN_V0DMR_DTMD (0x00000003u) +#define VIN_V0DMR_DTMD_SHIFT (0u) +#define VIN_V0DMR_ABIT (0x00000004u) +#define VIN_V0DMR_ABIT_SHIFT (2u) +#define VIN_V0DMR_BPSM (0x00000010u) +#define VIN_V0DMR_BPSM_SHIFT (4u) +#define VIN_V0DMR_EXRGB (0x00000100u) +#define VIN_V0DMR_EXRGB_SHIFT (8u) +#define VIN_V0DMR_YC_THR (0x00000800u) +#define VIN_V0DMR_YC_THR_SHIFT (11u) +#define VIN_V0DMR_YMODE (0x00007000u) +#define VIN_V0DMR_YMODE_SHIFT (12u) +#define VIN_V0DMR_EVA (0x00010000u) +#define VIN_V0DMR_EVA_SHIFT (16u) +#define VIN_V0DMR_A8BIT (0xFF000000u) +#define VIN_V0DMR_A8BIT_SHIFT (24u) +#define VIN_V0DMR2_HLV (0x000007FFu) +#define VIN_V0DMR2_HLV_SHIFT (0u) +#define VIN_V0DMR2_VLV (0x0000F000u) +#define VIN_V0DMR2_VLV_SHIFT (12u) +#define VIN_V0DMR2_FTEH (0x00010000u) +#define VIN_V0DMR2_FTEH_SHIFT (16u) +#define VIN_V0DMR2_FTEV (0x00020000u) +#define VIN_V0DMR2_FTEV_SHIFT (17u) +#define VIN_V0UVAOF_UVAOF (0xFFFFFF80u) +#define VIN_V0UVAOF_UVAOF_SHIFT (7u) +#define VIN_V0CSCC1_CSUB (0x000000FFu) +#define VIN_V0CSCC1_CSUB_SHIFT (0u) +#define VIN_V0CSCC1_YSUB (0x0000FF00u) +#define VIN_V0CSCC1_YSUB_SHIFT (8u) +#define VIN_V0CSCC1_YMUL (0x03FF0000u) +#define VIN_V0CSCC1_YMUL_SHIFT (16u) +#define VIN_V0CSCC2_GCRMUL (0x000003FFu) +#define VIN_V0CSCC2_GCRMUL_SHIFT (0u) +#define VIN_V0CSCC2_RCRMUL (0x03FF0000u) +#define VIN_V0CSCC2_RCRMUL_SHIFT (16u) +#define VIN_V0CSCC3_BCBMUL (0x000003FFu) +#define VIN_V0CSCC3_BCBMUL_SHIFT (0u) +#define VIN_V0CSCC3_GCBMUL (0x03FF0000u) +#define VIN_V0CSCC3_GCBMUL_SHIFT (16u) +#define VIN_V0UDS_CTRL_NE_BCB (0x00010000u) +#define VIN_V0UDS_CTRL_NE_BCB_SHIFT (16u) +#define VIN_V0UDS_CTRL_NE_GY (0x00020000u) +#define VIN_V0UDS_CTRL_NE_GY_SHIFT (17u) +#define VIN_V0UDS_CTRL_NE_RCR (0x00040000u) +#define VIN_V0UDS_CTRL_NE_RCR_SHIFT (18u) +#define VIN_V0UDS_CTRL_BC (0x00100000u) +#define VIN_V0UDS_CTRL_BC_SHIFT (20u) +#define VIN_V0UDS_CTRL_AMD (0x40000000u) +#define VIN_V0UDS_CTRL_AMD_SHIFT (30u) +#define VIN_V0UDS_SCALE_VFRAC (0x00000FFFu) +#define VIN_V0UDS_SCALE_VFRAC_SHIFT (0u) +#define VIN_V0UDS_SCALE_VMANT (0x0000F000u) +#define VIN_V0UDS_SCALE_VMANT_SHIFT (12u) +#define VIN_V0UDS_SCALE_HFRAC (0x0FFF0000u) +#define VIN_V0UDS_SCALE_HFRAC_SHIFT (16u) +#define VIN_V0UDS_SCALE_HMANT (0xF0000000u) +#define VIN_V0UDS_SCALE_HMANT_SHIFT (28u) +#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_V (0x0000007Fu) +#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_V_SHIFT (0u) +#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_H (0x007F0000u) +#define VIN_V0UDS_PASS_BWIDTH_BWIDTH_H_SHIFT (16u) +#define VIN_V0UDS_CLIP_SIZE_CL_VSIZE (0x00000FFFu) +#define VIN_V0UDS_CLIP_SIZE_CL_VSIZE_SHIFT (0u) +#define VIN_V0UDS_CLIP_SIZE_CL_HSIZE (0x0FFF0000u) +#define VIN_V0UDS_CLIP_SIZE_CL_HSIZE_SHIFT (16u) +#define VIN_V0LUTP_LTCRPR (0x000003FFu) +#define VIN_V0LUTP_LTCRPR_SHIFT (0u) +#define VIN_V0LUTP_LTCBPR (0x000FFC00u) +#define VIN_V0LUTP_LTCBPR_SHIFT (10u) +#define VIN_V0LUTP_LTYPR (0x3FF00000u) +#define VIN_V0LUTP_LTYPR_SHIFT (20u) +#define VIN_V0LUTD_LTCRDT (0x000000FFu) +#define VIN_V0LUTD_LTCRDT_SHIFT (0u) +#define VIN_V0LUTD_LTCBDT (0x0000FF00u) +#define VIN_V0LUTD_LTCBDT_SHIFT (8u) +#define VIN_V0LUTD_LTYDT (0x00FF0000u) +#define VIN_V0LUTD_LTYDT_SHIFT (16u) +#define VIN_V0YCCR1_YCLRP (0x00001FFFu) +#define VIN_V0YCCR1_YCLRP_SHIFT (0u) +#define VIN_V0YCCR2_YCLGP (0x00001FFFu) +#define VIN_V0YCCR2_YCLGP_SHIFT (0u) +#define VIN_V0YCCR2_YCLBP (0x1FFF0000u) +#define VIN_V0YCCR2_YCLBP_SHIFT (16u) +#define VIN_V0YCCR3_YCLAP (0x00000FFFu) +#define VIN_V0YCCR3_YCLAP_SHIFT (0u) +#define VIN_V0YCCR3_YCLCEN (0x00010000u) +#define VIN_V0YCCR3_YCLCEN_SHIFT (16u) +#define VIN_V0YCCR3_YCLHEN (0x00800000u) +#define VIN_V0YCCR3_YCLHEN_SHIFT (23u) +#define VIN_V0YCCR3_YCLSFT (0x1F000000u) +#define VIN_V0YCCR3_YCLSFT_SHIFT (24u) +#define VIN_V0YCCR3_YEXPEN (0x80000000u) +#define VIN_V0YCCR3_YEXPEN_SHIFT (31u) +#define VIN_V0CBCCR1_CBCLRP (0x00001FFFu) +#define VIN_V0CBCCR1_CBCLRP_SHIFT (0u) +#define VIN_V0CBCCR2_CBCLGP (0x00001FFFu) +#define VIN_V0CBCCR2_CBCLGP_SHIFT (0u) +#define VIN_V0CBCCR2_CBCLBP (0x1FFF0000u) +#define VIN_V0CBCCR2_CBCLBP_SHIFT (16u) +#define VIN_V0CBCCR3_CBCLAP (0x00000FFFu) +#define VIN_V0CBCCR3_CBCLAP_SHIFT (0u) +#define VIN_V0CBCCR3_CBCLCEN (0x00010000u) +#define VIN_V0CBCCR3_CBCLCEN_SHIFT (16u) +#define VIN_V0CBCCR3_CBCLHEN (0x00800000u) +#define VIN_V0CBCCR3_CBCLHEN_SHIFT (23u) +#define VIN_V0CBCCR3_CBCLSFT (0x1F000000u) +#define VIN_V0CBCCR3_CBCLSFT_SHIFT (24u) +#define VIN_V0CBCCR3_CBEXPEN (0x80000000u) +#define VIN_V0CBCCR3_CBEXPEN_SHIFT (31u) +#define VIN_V0CRCCR1_CRCLRP (0x00001FFFu) +#define VIN_V0CRCCR1_CRCLRP_SHIFT (0u) +#define VIN_V0CRCCR2_CRCLGP (0x00001FFFu) +#define VIN_V0CRCCR2_CRCLGP_SHIFT (0u) +#define VIN_V0CRCCR2_CRCLBP (0x1FFF0000u) +#define VIN_V0CRCCR2_CRCLBP_SHIFT (16u) +#define VIN_V0CRCCR3_CRCLAP (0x00000FFFu) +#define VIN_V0CRCCR3_CRCLAP_SHIFT (0u) +#define VIN_V0CRCCR3_CRCLCEN (0x00010000u) +#define VIN_V0CRCCR3_CRCLCEN_SHIFT (16u) +#define VIN_V0CRCCR3_CRCLHEN (0x00800000u) +#define VIN_V0CRCCR3_CRCLHEN_SHIFT (23u) +#define VIN_V0CRCCR3_CRCLSFT (0x1F000000u) +#define VIN_V0CRCCR3_CRCLSFT_SHIFT (24u) +#define VIN_V0CRCCR3_CREXPEN (0x80000000u) +#define VIN_V0CRCCR3_CREXPEN_SHIFT (31u) +#define VIN_V0CSCE1_YMUL2 (0x00003FFFu) +#define VIN_V0CSCE1_YMUL2_SHIFT (0u) +#define VIN_V0CSCE2_CSUB2 (0x00000FFFu) +#define VIN_V0CSCE2_CSUB2_SHIFT (0u) +#define VIN_V0CSCE2_YSUB2 (0x0FFF0000u) +#define VIN_V0CSCE2_YSUB2_SHIFT (16u) +#define VIN_V0CSCE3_GCRMUL2 (0x00003FFFu) +#define VIN_V0CSCE3_GCRMUL2_SHIFT (0u) +#define VIN_V0CSCE3_RCRMUL2 (0x3FFF0000u) +#define VIN_V0CSCE3_RCRMUL2_SHIFT (16u) +#define VIN_V0CSCE4_BCBMUL2 (0x00003FFFu) +#define VIN_V0CSCE4_BCBMUL2_SHIFT (0u) +#define VIN_V0CSCE4_GCBMUL2 (0x3FFF0000u) +#define VIN_V0CSCE4_GCBMUL2_SHIFT (16u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/wdt_iobitmask.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/wdt_iobitmask.h new file mode 100644 index 0000000..ebb9fde --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iobitmasks/wdt_iobitmask.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO bitmask header +*******************************************************************************/ + +#ifndef WDT_IOBITMASK_H +#define WDT_IOBITMASK_H + + +/* ==== Mask values for IO registers ==== */ + +#define WDT_WTCSR_CKS (0x000Fu) +#define WDT_WTCSR_CKS_SHIFT (0u) +#define WDT_WTCSR_TME (0x0020u) +#define WDT_WTCSR_TME_SHIFT (5u) +#define WDT_WTCSR_WTIT (0x0040u) +#define WDT_WTCSR_WTIT_SHIFT (6u) +#define WDT_WTCSR_IOVF (0x0080u) +#define WDT_WTCSR_IOVF_SHIFT (7u) +#define WDT_WTCNT_WTCNT (0x00FFu) +#define WDT_WTCNT_WTCNT_SHIFT (0u) +#define WDT_WRCSR_RSTE (0x0040u) +#define WDT_WRCSR_RSTE_SHIFT (6u) +#define WDT_WRCSR_WOVF (0x0080u) +#define WDT_WRCSR_WOVF_SHIFT (7u) +#define WDT_PEER_PEE (0x00FFu) +#define WDT_PEER_PEE_SHIFT (0u) +#define WDT_PECR_PERIE (0x00FFu) +#define WDT_PECR_PERIE_SHIFT (0u) +#define WDT_PESR_PEF (0x00FFu) +#define WDT_PESR_PEF_SHIFT (0u) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefine.h new file mode 100644 index 0000000..1df80c7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefine.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef __RZA2M___IODEFINE_HEADER__ +#define __RZA2M___IODEFINE_HEADER__ + +#include "iodefines/adc_iodefine.h" +#include "iodefines/bsc_iodefine.h" +#include "iodefines/ceu_iodefine.h" +#include "iodefines/cpg_iodefine.h" +#include "iodefines/csi2link_iodefine.h" +#include "iodefines/dmac_iodefine.h" +#include "iodefines/drpk_iodefine.h" +#include "iodefines/drw_iodefine.h" +#include "iodefines/edmac_iodefine.h" +#include "iodefines/eptpc_iodefine.h" +#include "iodefines/etherc_iodefine.h" +#include "iodefines/gpio_iodefine.h" +#include "iodefines/gpt_iodefine.h" +#include "iodefines/hyper_iodefine.h" +#include "iodefines/imr_iodefine.h" +#include "iodefines/intc_iodefine.h" +#include "iodefines/irda_iodefine.h" +#include "iodefines/jcu_iodefine.h" +#include "iodefines/lvds_iodefine.h" +#include "iodefines/mtu_iodefine.h" +#include "iodefines/nandc_iodefine.h" +#include "iodefines/octa_iodefine.h" +#include "iodefines/ostm_iodefine.h" +#include "iodefines/pl_iodefine.h" +#include "iodefines/pmg_iodefine.h" +#include "iodefines/poeg_iodefine.h" +#include "iodefines/poe_iodefine.h" +#include "iodefines/prr_iodefine.h" +#include "iodefines/ptpedmac_iodefine.h" +#include "iodefines/rcanfd_iodefine.h" +#include "iodefines/rcan_iodefine.h" +#include "iodefines/riic_iodefine.h" +#include "iodefines/rspi_iodefine.h" +#include "iodefines/rtc_iodefine.h" +#include "iodefines/scifa_iodefine.h" +#include "iodefines/scim_iodefine.h" +#include "iodefines/sdmmc_iodefine.h" +#include "iodefines/spdif_iodefine.h" +#include "iodefines/spibsc_iodefine.h" +#include "iodefines/sprite_iodefine.h" +#include "iodefines/ssif_iodefine.h" +#include "iodefines/usb_iodefine.h" +#include "iodefines/vdc_iodefine.h" +#include "iodefines/vin_iodefine.h" +#include "iodefines/wdt_iodefine.h" + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/adc_iodefine.h new file mode 100644 index 0000000..411e9ec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/adc_iodefine.h @@ -0,0 +1,555 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef ADC_IODEFINE_H +#define ADC_IODEFINE_H + +struct st_adc +{ + union + { + unsigned short WORD; + struct + { + unsigned short DBLANS:5; + unsigned short :1; + unsigned short GBADIE:1; + unsigned short DBLE:1; + unsigned short EXTRG:1; + unsigned short TRGE:1; + unsigned short :1; + unsigned short :1; + unsigned short ADIE:1; + unsigned short ADCS:2; + unsigned short ADST:1; + } BIT; + } ADCSR; + char wk0[1]; + char wk1[1]; + union + { + unsigned short WORD; + struct + { + unsigned short ANSA0:8; + unsigned short :8; + } BIT; + } ADANSA0; + char wk2[2]; + union + { + unsigned short WORD; + struct + { + unsigned short ADS0:8; + unsigned short :8; + } BIT; + } ADADS0; + char wk3[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ADC_2_0:3; + unsigned char :4; + unsigned char AVEE:1; + } BIT; + } ADADC; + char wk4[1]; + union + { + unsigned short WORD; + struct + { + unsigned short :1; + unsigned short ADPRC:2; + unsigned short :1; + unsigned short :1; + unsigned short ACE:1; + unsigned short :2; + unsigned short DIAGVAL:2; + unsigned short DIAGLD:1; + unsigned short DIAGM:1; + unsigned short :3; + unsigned short ADRFMT:1; + } BIT; + } ADCER; + union + { + unsigned short WORD; + struct + { + unsigned short TRSB:6; + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + } BIT; + } ADSTRGR; + char wk5[2]; + union + { + unsigned short WORD; + struct + { + unsigned short ANSB0:8; + unsigned short :8; + } BIT; + } ADANSB0; + char wk6[2]; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDBLDR; + char wk7[2]; + char wk8[2]; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADRD; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR0; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR1; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR2; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR3; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR4; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR5; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR6; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDR7; + char wk9[2]; + char wk10[2]; + char wk11[2]; + char wk12[2]; + char wk13[2]; + char wk14[2]; + char wk15[2]; + char wk16[2]; + char wk17[2]; + char wk18[2]; + char wk19[2]; + char wk20[2]; + char wk21[2]; + char wk22[2]; + char wk23[2]; + char wk24[2]; + char wk25[2]; + char wk26[2]; + char wk27[2]; + char wk28[2]; + char wk29[2]; + char wk30[2]; + char wk31[2]; + char wk32[2]; + char wk33[2]; + char wk34[1]; + char wk35[1]; + char wk36[2]; + char wk37[2]; + char wk38[2]; + char wk39[2]; + char wk40[2]; + char wk41[2]; + char wk42[2]; + char wk43[2]; + char wk44[2]; + char wk45[2]; + char wk46[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ADNDIS:5; + unsigned char :3; + } BIT; + } ADDISCR; + char wk47[1]; + char wk48[1]; + char wk49[1]; + char wk50[1]; + char wk51[1]; + union + { + unsigned short WORD; + struct + { + unsigned short PGS:1; + unsigned short GBRSCN:1; + unsigned short :6; + unsigned short :1; + unsigned short :5; + unsigned short LGRRS:1; + unsigned short GBRP:1; + } BIT; + } ADGSPCR; + char wk52[2]; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDBLDRA; + union + { + unsigned short WORD; + struct + { + unsigned short AD:16; + } BIT; + } ADDBLDRB; + char wk53[1]; + char wk54[1]; + char wk55[1]; + char wk56[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MONCOMB:1; + unsigned char :3; + unsigned char MONCMPA:1; + unsigned char MONCMPB:1; + unsigned char :2; + } BIT; + } ADWINMON; + char wk57[3]; + union + { + unsigned short WORD; + struct + { + unsigned short :2; + unsigned short :7; + unsigned short CMPBE:1; + unsigned short :1; + unsigned short CMPAE:1; + unsigned short :1; + unsigned short CMPBIE:1; + unsigned short WCMPE:1; + unsigned short CMPAIE:1; + } BIT; + } ADCMPCR; + char wk58[1]; + char wk59[1]; + union + { + unsigned short WORD; + struct + { + unsigned short CMPCHA0:8; + unsigned short :8; + } BIT; + } ADCMPANSR0; + char wk60[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CMPLCHA0:8; + unsigned short :8; + } BIT; + } ADCMPLR0; + char wk61[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CMPD0:16; + } BIT; + } ADCMPDR0; + union + { + unsigned short WORD; + struct + { + unsigned short CMPD1:16; + } BIT; + } ADCMPDR1; + union + { + unsigned short WORD; + struct + { + unsigned short CMPSTCHA0:8; + unsigned short :8; + } BIT; + } ADCMPSR0; + char wk62[2]; + char wk63[1]; + char wk64[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char CMPCHB:6; + unsigned char :1; + unsigned char CMPLB:1; + } BIT; + } ADCMPBNSR; + char wk65[1]; + union + { + unsigned short WORD; + struct + { + unsigned short CMPLLB:16; + } BIT; + } ADWINLLB; + union + { + unsigned short WORD; + struct + { + unsigned short CMPULB:16; + } BIT; + } ADWINULB; + union + { + unsigned char BYTE; + struct + { + unsigned char CMPSTB:1; + unsigned char :7; + } BIT; + } ADCMPBSR; + char wk66[3]; + char wk67[2]; + char wk68[2]; + char wk69[2]; + char wk70[2]; + char wk71[2]; + char wk72[2]; + char wk73[2]; + char wk74[2]; + char wk75[2]; + char wk76[2]; + char wk77[2]; + char wk78[2]; + char wk79[2]; + char wk80[2]; + char wk81[2]; + char wk82[2]; + char wk83[1]; + char wk84[1]; + char wk85[1]; + char wk86[1]; + union + { + unsigned short WORD; + struct + { + unsigned short ANSC0:8; + unsigned short :8; + } BIT; + } ADANSC0; + char wk87[2]; + char wk88[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TRSC:6; + unsigned char GCADIE:1; + unsigned char GRCE:1; + } BIT; + } ADGCTRGR; + char wk89[3]; + char wk90[1]; + char wk91[1]; + char wk92[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR0; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR1; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR2; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR3; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR4; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR5; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR6; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR7; + char wk93[1]; + char wk94[1]; + char wk95[1]; + char wk96[1]; + char wk97[1]; + char wk98[1]; + char wk99[1]; + char wk100[1]; + char wk101[176]; + char wk102[2]; + char wk103[2]; + char wk104[12]; + char wk105[2]; + char wk106[2]; + char wk107[1]; + char wk108[1]; + char wk109[42]; + char wk110[1]; +}; + +#define ADC (*(volatile struct st_adc *)0xE8005800) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/bsc_iodefine.h new file mode 100644 index 0000000..62e2c7c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/bsc_iodefine.h @@ -0,0 +1,453 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef BSC_IODEFINE_H +#define BSC_IODEFINE_H + +struct st_bsc +{ + union + { + unsigned long LONG; + struct + { + unsigned long HIZCNT:1; + unsigned long HIZMEM:1; + unsigned long :7; + unsigned long DPRTY:2; + unsigned long :13; + unsigned long AL0:1; + unsigned long :3; + unsigned long TL0:1; + unsigned long :3; + } BIT; + } CMNCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS0BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS1BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS2BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS3BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS4BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS5BCR; + char wk0[4]; + char wk1[4]; + char wk2[4]; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :7; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS0WCR_0; + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long W:4; + unsigned long :5; + unsigned long BW:2; + unsigned long :2; + unsigned long BST:2; + unsigned long :10; + } BIT; + } CS0WCR_1; + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long W:4; + unsigned long :5; + unsigned long BW:2; + unsigned long :14; + } BIT; + } CS0WCR_2; + } CS0WCR; + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :3; + unsigned long WW:3; + unsigned long :1; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS1WCR_0; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long WR:4; + unsigned long :9; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS2WCR_0; + union + { + unsigned long LONG; + struct + { + unsigned long :7; + unsigned long A2CL:2; + unsigned long :23; + } BIT; + } CS2WCR_1; + } CS2WCR; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long WTRC:2; + unsigned long :1; + unsigned long TRWL:2; + unsigned long :2; + unsigned long A3CL:2; + unsigned long :1; + unsigned long WTRCD:2; + unsigned long :1; + unsigned long WTRP:2; + unsigned long :17; + } BIT; + } CS3WCR_1; + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long WR:4; + unsigned long :9; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS3WCR_0; + } CS3WCR; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :3; + unsigned long WW:3; + unsigned long :1; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS4WCR_0; + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long W:4; + unsigned long SW:2; + unsigned long :3; + unsigned long BW:2; + unsigned long :2; + unsigned long BST:2; + unsigned long :10; + } BIT; + } CS4WCR_1; + } CS4WCR; + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :3; + unsigned long WW:3; + unsigned long :1; + unsigned long MPXWBAS:1; + unsigned long SZSEL:1; + unsigned long :10; + } BIT; + } CS5WCR_0; + char wk3[4]; + char wk4[4]; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long A3COL:2; + unsigned long :1; + unsigned long A3ROW:2; + unsigned long :3; + unsigned long BACTV:1; + unsigned long PDOWN:1; + unsigned long RMODE:1; + unsigned long RFSH:1; + unsigned long :1; + unsigned long DEEP:1; + unsigned long :2; + unsigned long A2COL:2; + unsigned long :1; + unsigned long A2ROW:2; + unsigned long :11; + } BIT; + } SDCR; + union + { + unsigned long LONG; + struct + { + unsigned long RRC:3; + unsigned long CKS:3; + unsigned long CMIE:1; + unsigned long CMF:1; + unsigned long :24; + } BIT; + } RTCSR; + unsigned long RTCNT; + unsigned long RTCOR; + char wk6[4]; + unsigned long TOSCOR0; + unsigned long TOSCOR1; + unsigned long TOSCOR2; + unsigned long TOSCOR3; + unsigned long TOSCOR4; + unsigned long TOSCOR5; + char wk7[4]; + char wk8[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CS0TOSTF:1; + unsigned long CS1TOSTF:1; + unsigned long CS2TOSTF:1; + unsigned long CS3TOSTF:1; + unsigned long CS4TOSTF:1; + unsigned long CS5TOSTF:1; + unsigned long :26; + } BIT; + } TOSTR; + union + { + unsigned long LONG; + struct + { + unsigned long CS0TOEN:1; + unsigned long CS1TOEN:1; + unsigned long CS2TOEN:1; + unsigned long CS3TOEN:1; + unsigned long CS4TOEN:1; + unsigned long CS5TOEN:1; + unsigned long :26; + } BIT; + } TOENR; + char wk9[8]; + union + { + unsigned long LONG; + struct + { + unsigned long SDRIDLY:4; + unsigned long :12; + unsigned long SDRODLY:4; + unsigned long :12; + } BIT; + } ACADJ; + char wk10[2924]; + char wk11[4]; + char wk12[4]; + char wk13[4]; + char wk14[4]; + char wk15[4]; + char wk16[4]; + char wk17[228]; + char wk18[1]; +}; + +#define BSC (*(volatile struct st_bsc *)0x1F000000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ceu_iodefine.h new file mode 100644 index 0000000..635ee17 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ceu_iodefine.h @@ -0,0 +1,715 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef CEU_IODEFINE_H +#define CEU_IODEFINE_H + +struct st_ceu +{ + union + { + unsigned long LONG; + struct + { + unsigned long CE:1; + unsigned long :15; + unsigned long CPKIL:1; + unsigned long :15; + } BIT; + } CAPSR; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long CTNCP:1; + unsigned long :3; + unsigned long MTCM:2; + unsigned long :2; + unsigned long FDRP:8; + } BIT; + } CAPCR; + union + { + unsigned long LONG; + struct + { + unsigned long HDPOL:1; + unsigned long VDPOL:1; + unsigned long :2; + unsigned long JPG:2; + unsigned long :2; + unsigned long DTARY:2; + unsigned long :2; + unsigned long DTIF:1; + unsigned long :3; + unsigned long FLDPOL:1; + unsigned long :7; + unsigned long DSEL:1; + unsigned long FLDSEL:1; + unsigned long HDSEL:1; + unsigned long VDSEL:1; + unsigned long :4; + } BIT; + } CAMCR; + union + { + unsigned long LONG; + struct + { + unsigned long HCYL:14; + unsigned long :2; + unsigned long VCYL:14; + unsigned long :2; + } BIT; + } CMCYR; + union + { + unsigned long LONG; + struct + { + unsigned long HOFST:13; + unsigned long :3; + unsigned long VOFST:12; + unsigned long :4; + } BIT; + } CAMOR_A; + union + { + unsigned long LONG; + struct + { + unsigned long HWDTH:13; + unsigned long :3; + unsigned long VWDTH:12; + unsigned long :4; + } BIT; + } CAPWR_A; + union + { + unsigned long LONG; + struct + { + unsigned long FCI:2; + unsigned long :2; + unsigned long CIM:1; + unsigned long :3; + unsigned long IFS:1; + unsigned long :23; + } BIT; + } CAIFR; + char wk0[4]; + char wk1[4]; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RC:1; + unsigned long RS:1; + unsigned long :2; + unsigned long RVS:1; + unsigned long :27; + } BIT; + } CRCNTR; + union + { + unsigned long LONG; + struct + { + unsigned long RA:1; + unsigned long :31; + } BIT; + } CRCMPR; + union + { + unsigned long LONG; + struct + { + unsigned long HFRAC:12; + unsigned long HMANT:4; + unsigned long VFRAC:12; + unsigned long VMANT:4; + } BIT; + } CFLCR_A; + union + { + unsigned long LONG; + struct + { + unsigned long HFCLP:12; + unsigned long :4; + unsigned long VFCLP:12; + unsigned long :4; + } BIT; + } CFSZR_A; + union + { + unsigned long LONG; + struct + { + unsigned long CHDW:13; + unsigned long :19; + } BIT; + } CDWDR_A; + union + { + unsigned long LONG; + struct + { + unsigned long CAYR:32; + } BIT; + } CDAYR_A; + union + { + unsigned long LONG; + struct + { + unsigned long CACR:32; + } BIT; + } CDACR_A; + union + { + unsigned long LONG; + struct + { + unsigned long CBYR:32; + } BIT; + } CDBYR_A; + union + { + unsigned long LONG; + struct + { + unsigned long CBCR:32; + } BIT; + } CDBCR_A; + union + { + unsigned long LONG; + struct + { + unsigned long CBVS:23; + unsigned long :9; + } BIT; + } CBDSR_A; + char wk3[12]; + union + { + unsigned long LONG; + struct + { + unsigned long FWE:1; + unsigned long :4; + unsigned long FWV:27; + } BIT; + } CFWCR; + union + { + unsigned long LONG; + struct + { + unsigned long LPF:1; + unsigned long :31; + } BIT; + } CLFCR_A; + union + { + unsigned long LONG; + struct + { + unsigned long COBS:1; + unsigned long COWS:1; + unsigned long COLS:1; + unsigned long :1; + unsigned long CDS:1; + unsigned long :3; + unsigned long :1; + unsigned long :7; + unsigned long CBE:1; + unsigned long :15; + } BIT; + } CDOCR_A; + char wk4[4]; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CPEIE:1; + unsigned long CFEIE:1; + unsigned long :2; + unsigned long IGRWIE:1; + unsigned long :3; + unsigned long HDIE:1; + unsigned long VDIE:1; + unsigned long :2; + unsigned long CPBE1IE:1; + unsigned long CPBE2IE:1; + unsigned long CPBE3IE:1; + unsigned long CPBE4IE:1; + unsigned long CDTOFIE:1; + unsigned long IGHSIE:1; + unsigned long IGVSIE:1; + unsigned long :1; + unsigned long VBPIE:1; + unsigned long :1; + unsigned long :1; + unsigned long FWFIE:1; + unsigned long NHDIE:1; + unsigned long NVDIE:1; + unsigned long :6; + } BIT; + } CEIER; + union + { + unsigned long LONG; + struct + { + unsigned long CPE:1; + unsigned long CFE:1; + unsigned long :2; + unsigned long IGRW:1; + unsigned long :3; + unsigned long HD:1; + unsigned long VD:1; + unsigned long :2; + unsigned long CPBE1:1; + unsigned long CPBE2:1; + unsigned long CPBE3:1; + unsigned long CPBE4:1; + unsigned long CDTOF:1; + unsigned long IGHS:1; + unsigned long IGVS:1; + unsigned long :1; + unsigned long VBP:1; + unsigned long :1; + unsigned long :1; + unsigned long FWF:1; + unsigned long NHD:1; + unsigned long NVD:1; + unsigned long :6; + } BIT; + } CETCR; + char wk6[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CPTON:1; + unsigned long :7; + unsigned long :1; + unsigned long :1; + unsigned long :6; + unsigned long CPFLD:1; + unsigned long :7; + unsigned long CRST:1; + unsigned long :7; + } BIT; + } CSTSR; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CDSS:32; + } BIT; + } CDSSR; + char wk8[8]; + union + { + unsigned long LONG; + struct + { + unsigned long CAYR2:32; + } BIT; + } CDAYR2_A; + union + { + unsigned long LONG; + struct + { + unsigned long CACR2:32; + } BIT; + } CDACR2_A; + union + { + unsigned long LONG; + struct + { + unsigned long CBYR2:32; + } BIT; + } CDBYR2_A; + union + { + unsigned long LONG; + struct + { + unsigned long CBCR2:32; + } BIT; + } CDBCR2_A; + char wk9[3952]; + union + { + unsigned long LONG; + struct + { + unsigned long HOFST:13; + unsigned long :3; + unsigned long VOFST:12; + unsigned long :4; + } BIT; + } CAMOR_B; + union + { + unsigned long LONG; + struct + { + unsigned long HWDTH:13; + unsigned long :3; + unsigned long VWDTH:12; + unsigned long :4; + } BIT; + } CAPWR_B; + char wk10[24]; + union + { + unsigned long LONG; + struct + { + unsigned long HFRAC:12; + unsigned long HMANT:4; + unsigned long VFRAC:12; + unsigned long VMANT:4; + } BIT; + } CFLCR_B; + union + { + unsigned long LONG; + struct + { + unsigned long HFCLP:12; + unsigned long :4; + unsigned long VFCLP:12; + unsigned long :4; + } BIT; + } CFSZR_B; + union + { + unsigned long LONG; + struct + { + unsigned long CHDW:13; + unsigned long :19; + } BIT; + } CDWDR_B; + union + { + unsigned long LONG; + struct + { + unsigned long CAYR:32; + } BIT; + } CDAYR_B; + union + { + unsigned long LONG; + struct + { + unsigned long CACR:32; + } BIT; + } CDACR_B; + union + { + unsigned long LONG; + struct + { + unsigned long CBYR:32; + } BIT; + } CDBYR_B; + union + { + unsigned long LONG; + struct + { + unsigned long CBCR:32; + } BIT; + } CDBCR_B; + union + { + unsigned long LONG; + struct + { + unsigned long CBVS:23; + unsigned long :9; + } BIT; + } CBDSR_B; + char wk11[16]; + union + { + unsigned long LONG; + struct + { + unsigned long LPF:1; + unsigned long :31; + } BIT; + } CLFCR_B; + union + { + unsigned long LONG; + struct + { + unsigned long COBS:1; + unsigned long COWS:1; + unsigned long COLS:1; + unsigned long :1; + unsigned long CDS:1; + unsigned long :3; + unsigned long :1; + unsigned long :7; + unsigned long CBE:1; + unsigned long :15; + } BIT; + } CDOCR_B; + char wk12[4]; + char wk13[4]; + char wk14[32]; + union + { + unsigned long LONG; + struct + { + unsigned long CAYR2:32; + } BIT; + } CDAYR2_B; + union + { + unsigned long LONG; + struct + { + unsigned long CACR2:32; + } BIT; + } CDACR2_B; + union + { + unsigned long LONG; + struct + { + unsigned long CBYR2:32; + } BIT; + } CDBYR2_B; + union + { + unsigned long LONG; + struct + { + unsigned long CBCR2:32; + } BIT; + } CDBCR2_B; + char wk15[3952]; + union + { + unsigned long LONG; + struct + { + unsigned long HOFST:13; + unsigned long :3; + unsigned long VOFST:12; + unsigned long :4; + } BIT; + } CAMOR_M; + union + { + unsigned long LONG; + struct + { + unsigned long HWDTH:13; + unsigned long :3; + unsigned long VWDTH:12; + unsigned long :4; + } BIT; + } CAPWR_M; + char wk16[24]; + union + { + unsigned long LONG; + struct + { + unsigned long HFRAC:12; + unsigned long HMANT:4; + unsigned long VFRAC:12; + unsigned long VMANT:4; + } BIT; + } CFLCR_M; + union + { + unsigned long LONG; + struct + { + unsigned long HFCLP:12; + unsigned long :4; + unsigned long VFCLP:12; + unsigned long :4; + } BIT; + } CFSZR_M; + union + { + unsigned long LONG; + struct + { + unsigned long CHDW:13; + unsigned long :19; + } BIT; + } CDWDR_M; + union + { + unsigned long LONG; + struct + { + unsigned long CAYR:32; + } BIT; + } CDAYR_M; + union + { + unsigned long LONG; + struct + { + unsigned long CACR:32; + } BIT; + } CDACR_M; + union + { + unsigned long LONG; + struct + { + unsigned long CBYR:32; + } BIT; + } CDBYR_M; + union + { + unsigned long LONG; + struct + { + unsigned long CBCR:32; + } BIT; + } CDBCR_M; + union + { + unsigned long LONG; + struct + { + unsigned long CBVS:23; + unsigned long :9; + } BIT; + } CBDSR_M; + char wk17[16]; + union + { + unsigned long LONG; + struct + { + unsigned long LPF:1; + unsigned long :31; + } BIT; + } CLFCR_M; + union + { + unsigned long LONG; + struct + { + unsigned long COBS:1; + unsigned long COWS:1; + unsigned long COLS:1; + unsigned long :1; + unsigned long CDS:1; + unsigned long :3; + unsigned long :1; + unsigned long :7; + unsigned long CBE:1; + unsigned long :15; + } BIT; + } CDOCR_M; + char wk18[4]; + char wk19[4]; + char wk20[32]; + union + { + unsigned long LONG; + struct + { + unsigned long CAYR2:32; + } BIT; + } CDAYR2_M; + union + { + unsigned long LONG; + struct + { + unsigned long CACR2:32; + } BIT; + } CDACR2_M; + union + { + unsigned long LONG; + struct + { + unsigned long CBYR2:32; + } BIT; + } CDBYR2_M; + union + { + unsigned long LONG; + struct + { + unsigned long CBCR2:32; + } BIT; + } CDBCR2_M; +}; + +#define CEU (*(volatile struct st_ceu *)0xE8210000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/cpg_iodefine.h new file mode 100644 index 0000000..9c1e1ea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/cpg_iodefine.h @@ -0,0 +1,420 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef CPG_IODEFINE_H +#define CPG_IODEFINE_H + +struct st_cpg +{ + union + { + unsigned short WORD; + struct + { + unsigned short PFC:2; + unsigned short :1; + unsigned short :1; + unsigned short BFC:2; + unsigned short :2; + unsigned short IFC:2; + unsigned short :2; + unsigned short CKOEN:2; + unsigned short CKOEN2:1; + unsigned short :1; + } BIT; + } FRQCR; + char wk0[6]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char :1; + unsigned char :2; + unsigned char ISBUSY:1; + unsigned char :3; + } BIT; + } CPUSTS; + char wk1[7]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char DEEP:1; + unsigned char STBY:1; + } BIT; + } STBCR1; + char wk2[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char MSTP20:1; + unsigned char :6; + unsigned char HIZ:1; + } BIT; + } STBCR2; + char wk3[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char STBRQ10:1; + unsigned char STBRQ11:1; + unsigned char STBRQ12:1; + unsigned char STBRQ13:1; + unsigned char :1; + unsigned char STBRQ15:1; + unsigned char :1; + unsigned char :1; + } BIT; + } STBREQ1; + char wk4[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char STBRQ20:1; + unsigned char STBRQ21:1; + unsigned char STBRQ22:1; + unsigned char STBRQ23:1; + unsigned char STBRQ24:1; + unsigned char STBRQ25:1; + unsigned char STBRQ26:1; + unsigned char STBRQ27:1; + } BIT; + } STBREQ2; + char wk5[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char STBRQ30:1; + unsigned char STBRQ31:1; + unsigned char STBRQ32:1; + unsigned char STBRQ33:1; + unsigned char :4; + } BIT; + } STBREQ3; + char wk6[7]; + union + { + unsigned char BYTE; + struct + { + unsigned char STBAK10:1; + unsigned char STBAK11:1; + unsigned char STBAK12:1; + unsigned char STBAK13:1; + unsigned char :1; + unsigned char STBAK15:1; + unsigned char :1; + unsigned char :1; + } BIT; + } STBACK1; + char wk7[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char STBAK20:1; + unsigned char STBAK21:1; + unsigned char STBAK22:1; + unsigned char STBAK23:1; + unsigned char STBAK24:1; + unsigned char STBAK25:1; + unsigned char STBAK26:1; + unsigned char STBAK27:1; + } BIT; + } STBACK2; + char wk8[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char STBAK30:1; + unsigned char STBAK31:1; + unsigned char STBAK32:1; + unsigned char STBAK33:1; + unsigned char :4; + } BIT; + } STBACK3; + char wk9[183]; + union + { + unsigned short WORD; + struct + { + unsigned short CKIOSEL:2; + unsigned short :14; + } BIT; + } CKIOSEL; + char wk10[2]; + union + { + unsigned short WORD; + struct + { + unsigned short SPICR:2; + unsigned short :2; + unsigned short HYMCR:2; + unsigned short :2; + unsigned short OCTCR:2; + unsigned short :6; + } BIT; + } SCLKSEL; + char wk11[762]; + union + { + unsigned char BYTE; + struct + { + unsigned char VRAME0:1; + unsigned char VRAME1:1; + unsigned char VRAME2:1; + unsigned char VRAME3:1; + unsigned char VRAME4:1; + unsigned char :3; + } BIT; + } SYSCR1; + char wk12[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char VRAMWE0:1; + unsigned char VRAMWE1:1; + unsigned char VRAMWE2:1; + unsigned char VRAMWE3:1; + unsigned char VRAMWE4:1; + unsigned char :3; + } BIT; + } SYSCR2; + char wk13[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char RRAMWE0:1; + unsigned char RRAMWE1:1; + unsigned char RRAMWE2:1; + unsigned char RRAMWE3:1; + unsigned char :4; + } BIT; + } SYSCR3; + char wk14[23]; + union + { + unsigned char BYTE; + struct + { + unsigned char MSTP30:1; + unsigned char MSTP31:1; + unsigned char MSTP32:1; + unsigned char MSTP33:1; + unsigned char MSTP34:1; + unsigned char MSTP35:1; + unsigned char MSTP36:1; + unsigned char :1; + } BIT; + } STBCR3; + char wk15[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char MSTP40:1; + unsigned char MSTP41:1; + unsigned char MSTP42:1; + unsigned char MSTP43:1; + unsigned char MSTP44:1; + unsigned char MSTP45:1; + unsigned char MSTP46:1; + unsigned char MSTP47:1; + } BIT; + } STBCR4; + char wk16[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char MSTP51:1; + unsigned char MSTP52:1; + unsigned char MSTP53:1; + unsigned char :2; + unsigned char MSTP56:1; + unsigned char MSTP57:1; + } BIT; + } STBCR5; + char wk17[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char MSTP60:1; + unsigned char MSTP61:1; + unsigned char MSTP62:1; + unsigned char MSTP63:1; + unsigned char MSTP64:1; + unsigned char MSTP65:1; + unsigned char MSTP66:1; + unsigned char :1; + } BIT; + } STBCR6; + char wk18[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char MSTP70:1; + unsigned char MSTP71:1; + unsigned char MSTP72:1; + unsigned char MSTP73:1; + unsigned char :1; + unsigned char MSTP75:1; + unsigned char MSTP76:1; + unsigned char MSTP77:1; + } BIT; + } STBCR7; + char wk19[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char MSTP81:1; + unsigned char :1; + unsigned char MSTP83:1; + unsigned char MSTP84:1; + unsigned char MSTP85:1; + unsigned char MSTP86:1; + unsigned char MSTP87:1; + } BIT; + } STBCR8; + char wk20[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char MSTP90:1; + unsigned char MSTP91:1; + unsigned char MSTP92:1; + unsigned char MSTP93:1; + unsigned char :1; + unsigned char MSTP95:1; + unsigned char MSTP96:1; + unsigned char MSTP97:1; + } BIT; + } STBCR9; + char wk21[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char MSTP100:1; + unsigned char MSTP101:1; + unsigned char MSTP102:1; + unsigned char MSTP103:1; + unsigned char MSTP104:1; + unsigned char :1; + unsigned char :1; + unsigned char MSTP107:1; + } BIT; + } STBCR10; + char wk22[3]; + char wk23[1]; + char wk24[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char SRST10:1; + unsigned char SRST11:1; + unsigned char SRST12:1; + unsigned char SRST13:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char AXTALE:1; + } BIT; + } SWRSTCR1; + char wk25[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char SRST21:1; + unsigned char SRST22:1; + unsigned char SRST23:1; + unsigned char SRST24:1; + unsigned char SRST25:1; + unsigned char SRST26:1; + unsigned char :1; + } BIT; + } SWRSTCR2; +}; + +#define CPG (*(volatile struct st_cpg *)0xFCFE0010) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/csi2link_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/csi2link_iodefine.h new file mode 100644 index 0000000..e7fdcbe --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/csi2link_iodefine.h @@ -0,0 +1,753 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef CSI2LINK_IODEFINE_H +#define CSI2LINK_IODEFINE_H + +struct st_csi2link +{ + union + { + unsigned long LONG; + struct + { + unsigned long TREF:1; + unsigned long :31; + } BIT; + } TREF; + union + { + unsigned long LONG; + struct + { + unsigned long SRST:1; + unsigned long :31; + } BIT; + } SRST; + union + { + unsigned long LONG; + struct + { + unsigned long ENABLE_0:1; + unsigned long ENABLE_1:1; + unsigned long :1; + unsigned long :1; + unsigned long ENABLECLK:1; + unsigned long :11; + unsigned long RSTZ:1; + unsigned long SHUTDOWNZ:1; + unsigned long :14; + } BIT; + } PHYCNT; + union + { + unsigned long LONG; + struct + { + unsigned long CRC_EN:1; + unsigned long ECC_EN:1; + unsigned long :30; + } BIT; + } CHKSUM; + union + { + unsigned long LONG; + struct + { + unsigned long SEL_DT:6; + unsigned long SEL_DT_ON:1; + unsigned long :1; + unsigned long SEL_VC:2; + unsigned long :5; + unsigned long VCDT_EN:1; + unsigned long :6; + unsigned long :1; + unsigned long :1; + unsigned long :2; + unsigned long :5; + unsigned long :1; + } BIT; + } VCDT; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long DT_FE:6; + unsigned long :2; + unsigned long DT_FS:6; + unsigned long :2; + } BIT; + } FRDT; + union + { + unsigned long LONG; + struct + { + unsigned long FLD_EN:1; + unsigned long :3; + unsigned long FLD_DET_SEL:2; + unsigned long :10; + unsigned long FLD_NUM:16; + } BIT; + } FLD; + union + { + unsigned long LONG; + struct + { + unsigned long AUTO_STANDBY_EN:5; + unsigned long VD_MSK_EN:1; + unsigned long :2; + unsigned long VD_MSK_CYCLE:6; + unsigned long :18; + } BIT; + } ASTBY; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long LNGDT0:32; + } BIT; + } LNGDT0; + union + { + unsigned long LONG; + struct + { + unsigned long LNGDT1:32; + } BIT; + } LNGDT1; + union + { + unsigned long LONG; + struct + { + unsigned long IEN:32; + } BIT; + } INTEN; + union + { + unsigned long LONG; + struct + { + unsigned long ICL:32; + } BIT; + } INTCLOSE; + union + { + unsigned long LONG; + struct + { + unsigned long IST:32; + } BIT; + } INTSTATE; + union + { + unsigned long LONG; + struct + { + unsigned long IEST:16; + unsigned long :16; + } BIT; + } INTERRSTATE; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long DATA:16; + unsigned long ECC:8; + } BIT; + } SHPDAT; + union + { + unsigned long LONG; + struct + { + unsigned long NUM:4; + unsigned long :12; + unsigned long OVF:1; + unsigned long :15; + } BIT; + } SHPCNT; + union + { + unsigned long LONG; + struct + { + unsigned long :24; + unsigned long :1; + unsigned long REG_MONI_PACT_EN:1; + unsigned long :5; + unsigned long MONITOR_EN:1; + } BIT; + } LINKCNT; + union + { + unsigned long LONG; + struct + { + unsigned long L0SEL:2; + unsigned long L1SEL:2; + unsigned long :2; + unsigned long :2; + unsigned long :24; + } BIT; + } LSWAP; + char wk2[4]; + char wk3[4]; + char wk4[4]; + char wk5[12]; + char wk6[4]; + char wk7[8]; + union + { + unsigned long LONG; + struct + { + unsigned long ERRCONTROL_0:1; + unsigned long ERRCONTROL_1:1; + unsigned long :1; + unsigned long :1; + unsigned long :4; + unsigned long ERRESC_0:1; + unsigned long ERRESC_1:1; + unsigned long :1; + unsigned long :1; + unsigned long CL_ERRCONTROL:1; + unsigned long :19; + } BIT; + } PHEERM; + union + { + unsigned long LONG; + struct + { + unsigned long STOPSTATECLK:1; + unsigned long RXCLKACTIVEHS:1; + unsigned long RXULPSCLKNOT:1; + unsigned long ULPSACTIVENOTCLK:1; + unsigned long :28; + } BIT; + } PHCLM; + union + { + unsigned long LONG; + struct + { + unsigned long STOPSTATEDATA_0:1; + unsigned long STOPSTATEDATA_1:1; + unsigned long :1; + unsigned long :1; + unsigned long :4; + unsigned long RXULPSESC_0:1; + unsigned long RXULPSESC_1:1; + unsigned long :1; + unsigned long :1; + unsigned long ULPSACTIVENOT_0:1; + unsigned long ULPSACTIVENOT_1:1; + unsigned long :1; + unsigned long :1; + unsigned long :16; + } BIT; + } PHDLM; + char wk8[112]; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long :8; + } BIT; + } PH0M0; + union + { + unsigned long LONG; + struct + { + unsigned long PH_CNT:16; + unsigned long :16; + } BIT; + } PH0M1; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long :8; + } BIT; + } PH1M0; + union + { + unsigned long LONG; + struct + { + unsigned long PH_CNT:16; + unsigned long :16; + } BIT; + } PH1M1; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long :8; + } BIT; + } PH2M0; + union + { + unsigned long LONG; + struct + { + unsigned long PH_CNT:16; + unsigned long :16; + } BIT; + } PH2M1; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long :8; + } BIT; + } PH3M0; + union + { + unsigned long LONG; + struct + { + unsigned long PH_CNT:16; + unsigned long :16; + } BIT; + } PH3M1; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHRM0; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHRM1; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHRM2; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long CAL_PARITY:8; + } BIT; + } PHCM0; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long CAL_PARITY:8; + } BIT; + } PHCM1; + union + { + unsigned long LONG; + struct + { + unsigned long CAL_CRC:16; + unsigned long CRC:16; + } BIT; + } CRCM0; + union + { + unsigned long LONG; + struct + { + unsigned long CAL_CRC:16; + unsigned long CRC:16; + } BIT; + } CRCM1; + char wk10[16]; + union + { + unsigned long LONG; + struct + { + unsigned long ERRSOTHS_CNT:8; + unsigned long :24; + } BIT; + } SERRCNT; + union + { + unsigned long LONG; + struct + { + unsigned long ERRSOTSYNCHS:4; + unsigned long :28; + } BIT; + } SSERRCNT; + union + { + unsigned long LONG; + struct + { + unsigned long ECC_CRCT_CNT:8; + unsigned long :24; + } BIT; + } ECCCM; + union + { + unsigned long LONG; + struct + { + unsigned long ECC_ERR_CNT:8; + unsigned long :24; + } BIT; + } ECECM; + union + { + unsigned long LONG; + struct + { + unsigned long CRC_ERR_CNT:8; + unsigned long :24; + } BIT; + } CRCECM; + char wk11[12]; + union + { + unsigned long LONG; + struct + { + unsigned long LINE_CNT:16; + unsigned long :16; + } BIT; + } LCNT; + char wk12[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MONI_LINECNT:16; + unsigned long :16; + } BIT; + } LCNTM; + char wk13[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MONI_FCOUNT:16; + unsigned long :16; + } BIT; + } FCNTM; + char wk14[4]; + char wk15[8]; + union + { + unsigned long LONG; + struct + { + unsigned long RXDATAHS_0:8; + unsigned long RXDATAHS_1:8; + unsigned long :8; + unsigned long :8; + } BIT; + } PHYDIM; + union + { + unsigned long LONG; + struct + { + unsigned long RXSYNCHS_0_CNT:4; + unsigned long RXSYNCHS_1_CNT:4; + unsigned long :4; + unsigned long :4; + unsigned long RXACTIVEHS_0:1; + unsigned long RXACTIVEHS_1:1; + unsigned long :1; + unsigned long :1; + unsigned long RXVALIDHS_0:1; + unsigned long RXVALIDHS_1:1; + unsigned long :1; + unsigned long :1; + unsigned long :7; + unsigned long RXCLK_CNT:1; + } BIT; + } PHYIM; + char wk16[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CSIR_DAT:32; + } BIT; + } VINDM; + union + { + unsigned long LONG; + struct + { + unsigned long CSIR_HD_CNT:12; + unsigned long CSIR_VD_CNT:4; + unsigned long :12; + unsigned long :4; + } BIT; + } VINSM1; + char wk17[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CSIR_PE:1; + unsigned long :3; + unsigned long CSIR_PEB:4; + unsigned long CSIR_FLD:4; + unsigned long CSIR_TAG:2; + unsigned long CSIR_ERRC:1; + unsigned long CSIR_ERRE:1; + unsigned long :16; + } BIT; + } VINSM3; + union + { + unsigned long LONG; + struct + { + unsigned long ENABLE_0:1; + unsigned long ENABLE_1:1; + unsigned long :1; + unsigned long :1; + unsigned long ENABLECLK:1; + unsigned long :27; + } BIT; + } PHYOM; + char wk18[32]; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM1; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM2; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM3; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM4; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM5; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM6; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM7; + union + { + unsigned long LONG; + struct + { + unsigned long DT:6; + unsigned long VC:2; + unsigned long WC:16; + unsigned long ECC:8; + } BIT; + } PHM8; + char wk19[4]; + char wk20[4]; + char wk21[4]; + char wk22[4]; + char wk23[4]; + char wk24[4]; + char wk25[4]; + char wk26[4]; + char wk27[84]; + char wk28[4]; + char wk29[12]; + union + { + unsigned long LONG; + struct + { + unsigned long T_INIT_SLAVE:16; + unsigned long :16; + } BIT; + } PHYTIM1; + union + { + unsigned long LONG; + struct + { + unsigned long TCLK_PREPARE:5; + unsigned long :3; + unsigned long TCLK_SETTLE:6; + unsigned long :2; + unsigned long TCLK_MISS:5; + unsigned long :11; + } BIT; + } PHYTIM2; + union + { + unsigned long LONG; + struct + { + unsigned long THS_PREPARE:6; + unsigned long :2; + unsigned long THS_SETTLE:6; + unsigned long :18; + } BIT; + } PHYTIM3; + char wk30[4]; +}; + +#define CSI2LINK (*(volatile struct st_csi2link *)0xE8209000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/dmac_iodefine.h new file mode 100644 index 0000000..6f534fa --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/dmac_iodefine.h @@ -0,0 +1,6517 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef DMAC_IODEFINE_H +#define DMAC_IODEFINE_H + +struct st_dmac0 +{ + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_0S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_0S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_0S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_0S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_0S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_0S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_0S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_0S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_0S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_1S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_1S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_1S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_1S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_1S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_1S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_1S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_1S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_1S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_2S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_2S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_2S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_2S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_2S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_2S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_2S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_2S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_2S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_3S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_3S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_3S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_3S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_3S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_3S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_3S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_3S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_3S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_4S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_4S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_4S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_4S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_4S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_4S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_4S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_4S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_4S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_5S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_5S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_5S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_5S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_5S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_5S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_5S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_5S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_5S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_6S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_6S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_6S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_6S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_6S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_6S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_6S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_6S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_6S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_7S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_7S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_7S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_7S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_7S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_7S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_7S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_7S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_7S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_7S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_7S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_7S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_7S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_7S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_7S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_7S; + char wk0[256]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long LVINT:1; + unsigned long :14; + unsigned long LDPR:3; + unsigned long :1; + unsigned long LDCA:4; + unsigned long LWPR:3; + unsigned long :1; + unsigned long LWCA:4; + } BIT; + } DCTRL_0_7S; + char wk1[12]; + union + { + unsigned long LONG; + struct + { + unsigned long EN0:1; + unsigned long EN1:1; + unsigned long EN2:1; + unsigned long EN3:1; + unsigned long EN4:1; + unsigned long EN5:1; + unsigned long EN6:1; + unsigned long EN7:1; + unsigned long :24; + } BIT; + } DSTAT_EN_0_7S; + union + { + unsigned long LONG; + struct + { + unsigned long ER0:1; + unsigned long ER1:1; + unsigned long ER2:1; + unsigned long ER3:1; + unsigned long ER4:1; + unsigned long ER5:1; + unsigned long ER6:1; + unsigned long ER7:1; + unsigned long :24; + } BIT; + } DSTAT_ER_0_7S; + union + { + unsigned long LONG; + struct + { + unsigned long END0:1; + unsigned long END1:1; + unsigned long END2:1; + unsigned long END3:1; + unsigned long END4:1; + unsigned long END5:1; + unsigned long END6:1; + unsigned long END7:1; + unsigned long :24; + } BIT; + } DSTAT_END_0_7S; + union + { + unsigned long LONG; + struct + { + unsigned long TC0:1; + unsigned long TC1:1; + unsigned long TC2:1; + unsigned long TC3:1; + unsigned long TC4:1; + unsigned long TC5:1; + unsigned long TC6:1; + unsigned long TC7:1; + unsigned long :24; + } BIT; + } DSTAT_TC_0_7S; + union + { + unsigned long LONG; + struct + { + unsigned long SUS0:1; + unsigned long SUS1:1; + unsigned long SUS2:1; + unsigned long SUS3:1; + unsigned long SUS4:1; + unsigned long SUS5:1; + unsigned long SUS6:1; + unsigned long SUS7:1; + unsigned long :24; + } BIT; + } DSTAT_SUS_0_7S; + char wk2[220]; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_8S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_8S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_8S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_8S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_8S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_8S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_8S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_8S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_8S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_9S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_9S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_9S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_9S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_9S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_9S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_9S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_9S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_9S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_10S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_10S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_10S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_10S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_10S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_10S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_10S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_10S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_10S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_11S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_11S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_11S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_11S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_11S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_11S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_11S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_11S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_11S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_12S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_12S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_12S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_12S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_12S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_12S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_12S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_12S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_12S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_13S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_13S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_13S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_13S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_13S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_13S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_13S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_13S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_13S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_14S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_14S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_14S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_14S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_14S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_14S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_14S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_14S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_14S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_15S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_15S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_15S; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_15S; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_15S; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_15S; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_15S; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_15S; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_15S; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_15S; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_15S; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_15S; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_15S; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_15S; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_15S; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_15S; + char wk3[256]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long LVINT:1; + unsigned long :14; + unsigned long LDPR:3; + unsigned long :1; + unsigned long LDCA:4; + unsigned long LWPR:3; + unsigned long :1; + unsigned long LWCA:4; + } BIT; + } DCTRL_8_15S; + char wk4[12]; + union + { + unsigned long LONG; + struct + { + unsigned long EN8:1; + unsigned long EN9:1; + unsigned long EN10:1; + unsigned long EN11:1; + unsigned long EN12:1; + unsigned long EN13:1; + unsigned long EN14:1; + unsigned long EN15:1; + unsigned long :24; + } BIT; + } DSTAT_EN_8_15S; + union + { + unsigned long LONG; + struct + { + unsigned long ER8:1; + unsigned long ER9:1; + unsigned long ER10:1; + unsigned long ER11:1; + unsigned long ER12:1; + unsigned long ER13:1; + unsigned long ER14:1; + unsigned long ER15:1; + unsigned long :24; + } BIT; + } DSTAT_ER_8_15S; + union + { + unsigned long LONG; + struct + { + unsigned long END8:1; + unsigned long END9:1; + unsigned long END10:1; + unsigned long END11:1; + unsigned long END12:1; + unsigned long END13:1; + unsigned long END14:1; + unsigned long END15:1; + unsigned long :24; + } BIT; + } DSTAT_END_8_15S; + union + { + unsigned long LONG; + struct + { + unsigned long TC8:1; + unsigned long TC9:1; + unsigned long TC10:1; + unsigned long TC11:1; + unsigned long TC12:1; + unsigned long TC13:1; + unsigned long TC14:1; + unsigned long TC15:1; + unsigned long :24; + } BIT; + } DSTAT_TC_8_15S; + union + { + unsigned long LONG; + struct + { + unsigned long SUS8:1; + unsigned long SUS9:1; + unsigned long SUS10:1; + unsigned long SUS11:1; + unsigned long SUS12:1; + unsigned long SUS13:1; + unsigned long SUS14:1; + unsigned long SUS15:1; + unsigned long :24; + } BIT; + } DSTAT_SUS_8_15S; + char wk5[349964508]; + union + { + unsigned long LONG; + struct + { + unsigned long CH0_RID:2; + unsigned long CH0_MID:8; + unsigned long :6; + unsigned long CH1_RID:2; + unsigned long CH1_MID:8; + unsigned long :6; + } BIT; + } DMARS0S; + union + { + unsigned long LONG; + struct + { + unsigned long CH2_RID:2; + unsigned long CH2_MID:8; + unsigned long :6; + unsigned long CH3_RID:2; + unsigned long CH3_MID:8; + unsigned long :6; + } BIT; + } DMARS1S; + union + { + unsigned long LONG; + struct + { + unsigned long CH4_RID:2; + unsigned long CH4_MID:8; + unsigned long :6; + unsigned long CH5_RID:2; + unsigned long CH5_MID:8; + unsigned long :6; + } BIT; + } DMARS2S; + union + { + unsigned long LONG; + struct + { + unsigned long CH6_RID:2; + unsigned long CH6_MID:8; + unsigned long :6; + unsigned long CH7_RID:2; + unsigned long CH7_MID:8; + unsigned long :6; + } BIT; + } DMARS3S; + union + { + unsigned long LONG; + struct + { + unsigned long CH8_RID:2; + unsigned long CH8_MID:8; + unsigned long :6; + unsigned long CH9_RID:2; + unsigned long CH9_MID:8; + unsigned long :6; + } BIT; + } DMARS4S; + union + { + unsigned long LONG; + struct + { + unsigned long CH10_RID:2; + unsigned long CH10_MID:8; + unsigned long :6; + unsigned long CH11_RID:2; + unsigned long CH11_MID:8; + unsigned long :6; + } BIT; + } DMARS5S; + union + { + unsigned long LONG; + struct + { + unsigned long CH12_RID:2; + unsigned long CH12_MID:8; + unsigned long :6; + unsigned long CH13_RID:2; + unsigned long CH13_MID:8; + unsigned long :6; + } BIT; + } DMARS6S; + union + { + unsigned long LONG; + struct + { + unsigned long CH14_RID:2; + unsigned long CH14_MID:8; + unsigned long :6; + unsigned long CH15_RID:2; + unsigned long CH15_MID:8; + unsigned long :6; + } BIT; + } DMARS7S; +}; + +struct st_dmac1 +{ + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_0; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_0; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_0; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_0; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_0; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_0; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_0; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_0; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_1; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_1; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_1; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_1; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_1; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_1; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_1; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_1; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_2; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_2; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_2; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_2; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_2; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_2; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_2; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_2; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_2; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_2; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_2; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_2; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_3; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_3; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_3; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_3; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_3; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_3; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_3; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_3; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_3; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_3; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_3; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_3; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_4; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_4; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_4; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_4; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_4; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_4; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_4; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_4; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_4; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_4; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_4; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_4; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_5; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_5; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_5; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_5; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_5; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_5; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_5; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_5; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_5; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_5; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_5; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_5; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_6; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_6; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_6; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_6; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_6; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_6; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_6; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_6; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_6; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_6; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_6; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_6; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_7; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_7; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_7; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_7; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_7; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_7; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_7; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_7; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_7; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_7; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_7; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_7; + char wk0[256]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long LVINT:1; + unsigned long :14; + unsigned long LDPR:3; + unsigned long :1; + unsigned long LDCA:4; + unsigned long LWPR:3; + unsigned long :1; + unsigned long LWCA:4; + } BIT; + } DCTRL_0_7; + char wk1[12]; + union + { + unsigned long LONG; + struct + { + unsigned long EN0:1; + unsigned long EN1:1; + unsigned long EN2:1; + unsigned long EN3:1; + unsigned long EN4:1; + unsigned long EN5:1; + unsigned long EN6:1; + unsigned long EN7:1; + unsigned long :24; + } BIT; + } DSTAT_EN_0_7; + union + { + unsigned long LONG; + struct + { + unsigned long ER0:1; + unsigned long ER1:1; + unsigned long ER2:1; + unsigned long ER3:1; + unsigned long ER4:1; + unsigned long ER5:1; + unsigned long ER6:1; + unsigned long ER7:1; + unsigned long :24; + } BIT; + } DSTAT_ER_0_7; + union + { + unsigned long LONG; + struct + { + unsigned long END0:1; + unsigned long END1:1; + unsigned long END2:1; + unsigned long END3:1; + unsigned long END4:1; + unsigned long END5:1; + unsigned long END6:1; + unsigned long END7:1; + unsigned long :24; + } BIT; + } DSTAT_END_0_7; + union + { + unsigned long LONG; + struct + { + unsigned long TC0:1; + unsigned long TC1:1; + unsigned long TC2:1; + unsigned long TC3:1; + unsigned long TC4:1; + unsigned long TC5:1; + unsigned long TC6:1; + unsigned long TC7:1; + unsigned long :24; + } BIT; + } DSTAT_TC_0_7; + union + { + unsigned long LONG; + struct + { + unsigned long SUS0:1; + unsigned long SUS1:1; + unsigned long SUS2:1; + unsigned long SUS3:1; + unsigned long SUS4:1; + unsigned long SUS5:1; + unsigned long SUS6:1; + unsigned long SUS7:1; + unsigned long :24; + } BIT; + } DSTAT_SUS_0_7; + char wk2[220]; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_8; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_8; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_8; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_8; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_8; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_8; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_8; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_8; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_8; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_8; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_8; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_8; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_9; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_9; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_9; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_9; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_9; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_9; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_9; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_9; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_9; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_9; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_9; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_9; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_10; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_10; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_10; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_10; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_10; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_10; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_10; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_10; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_10; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_10; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_10; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_10; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_11; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_11; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_11; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_11; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_11; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_11; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_11; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_11; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_11; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_11; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_11; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_11; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_12; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_12; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_12; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_12; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_12; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_12; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_12; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_12; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_12; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_12; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_12; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_12; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_13; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_13; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_13; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_13; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_13; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_13; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_13; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_13; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_13; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_13; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_13; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_13; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_14; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_14; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_14; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_14; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_14; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_14; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_14; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_14; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_14; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_14; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_14; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_14; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N0SA_15; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_15; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_15; + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } N1SA_15; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_15; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_15; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTMSK:1; + unsigned long :15; + } BIT; + } CHSTAT_15; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long :1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :6; + unsigned long SETINTMSK:1; + unsigned long CLRINTMSK:1; + unsigned long :14; + } BIT; + } CHCTRL_15; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long :1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long :1; + unsigned long DEM:1; + unsigned long :1; + unsigned long :1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_15; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_15; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:3; + unsigned long :1; + unsigned long SCA:4; + unsigned long DPR:3; + unsigned long :1; + unsigned long DCA:4; + unsigned long :16; + } BIT; + } CHEXT_15; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_15; + char wk3[256]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long LVINT:1; + unsigned long :14; + unsigned long LDPR:3; + unsigned long :1; + unsigned long LDCA:4; + unsigned long LWPR:3; + unsigned long :1; + unsigned long LWCA:4; + } BIT; + } DCTRL_8_15; + char wk4[12]; + union + { + unsigned long LONG; + struct + { + unsigned long EN8:1; + unsigned long EN9:1; + unsigned long EN10:1; + unsigned long EN11:1; + unsigned long EN12:1; + unsigned long EN13:1; + unsigned long EN14:1; + unsigned long EN15:1; + unsigned long :24; + } BIT; + } DSTAT_EN_8_15; + union + { + unsigned long LONG; + struct + { + unsigned long ER8:1; + unsigned long ER9:1; + unsigned long ER10:1; + unsigned long ER11:1; + unsigned long ER12:1; + unsigned long ER13:1; + unsigned long ER14:1; + unsigned long ER15:1; + unsigned long :24; + } BIT; + } DSTAT_ER_8_15; + union + { + unsigned long LONG; + struct + { + unsigned long END8:1; + unsigned long END9:1; + unsigned long END10:1; + unsigned long END11:1; + unsigned long END12:1; + unsigned long END13:1; + unsigned long END14:1; + unsigned long END15:1; + unsigned long :24; + } BIT; + } DSTAT_END_8_15; + union + { + unsigned long LONG; + struct + { + unsigned long TC8:1; + unsigned long TC9:1; + unsigned long TC10:1; + unsigned long TC11:1; + unsigned long TC12:1; + unsigned long TC13:1; + unsigned long TC14:1; + unsigned long TC15:1; + unsigned long :24; + } BIT; + } DSTAT_TC_8_15; + union + { + unsigned long LONG; + struct + { + unsigned long SUS8:1; + unsigned long SUS9:1; + unsigned long SUS10:1; + unsigned long SUS11:1; + unsigned long SUS12:1; + unsigned long SUS13:1; + unsigned long SUS14:1; + unsigned long SUS15:1; + unsigned long :24; + } BIT; + } DSTAT_SUS_8_15; + char wk5[349944028]; + union + { + unsigned long LONG; + struct + { + unsigned long CH0_RID:2; + unsigned long CH0_MID:8; + unsigned long :6; + unsigned long CH1_RID:2; + unsigned long CH1_MID:8; + unsigned long :6; + } BIT; + } DMARS0; + union + { + unsigned long LONG; + struct + { + unsigned long CH2_RID:2; + unsigned long CH2_MID:8; + unsigned long :6; + unsigned long CH3_RID:2; + unsigned long CH3_MID:8; + unsigned long :6; + } BIT; + } DMARS1; + union + { + unsigned long LONG; + struct + { + unsigned long CH4_RID:2; + unsigned long CH4_MID:8; + unsigned long :6; + unsigned long CH5_RID:2; + unsigned long CH5_MID:8; + unsigned long :6; + } BIT; + } DMARS2; + union + { + unsigned long LONG; + struct + { + unsigned long CH6_RID:2; + unsigned long CH6_MID:8; + unsigned long :6; + unsigned long CH7_RID:2; + unsigned long CH7_MID:8; + unsigned long :6; + } BIT; + } DMARS3; + union + { + unsigned long LONG; + struct + { + unsigned long CH8_RID:2; + unsigned long CH8_MID:8; + unsigned long :6; + unsigned long CH9_RID:2; + unsigned long CH9_MID:8; + unsigned long :6; + } BIT; + } DMARS4; + union + { + unsigned long LONG; + struct + { + unsigned long CH10_RID:2; + unsigned long CH10_MID:8; + unsigned long :6; + unsigned long CH11_RID:2; + unsigned long CH11_MID:8; + unsigned long :6; + } BIT; + } DMARS5; + union + { + unsigned long LONG; + struct + { + unsigned long CH12_RID:2; + unsigned long CH12_MID:8; + unsigned long :6; + unsigned long CH13_RID:2; + unsigned long CH13_MID:8; + unsigned long :6; + } BIT; + } DMARS6; + union + { + unsigned long LONG; + struct + { + unsigned long CH14_RID:2; + unsigned long CH14_MID:8; + unsigned long :6; + unsigned long CH15_RID:2; + unsigned long CH15_MID:8; + unsigned long :6; + } BIT; + } DMARS7; +}; + +#define DMAC0 (*(volatile struct st_dmac0 *)0xE8220000) +#define DMAC1 (*(volatile struct st_dmac1 *)0xE8226000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drpk_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drpk_iodefine.h new file mode 100644 index 0000000..c2cb5ec --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drpk_iodefine.h @@ -0,0 +1,135 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef DRPK_IODEFINE_H +#define DRPK_IODEFINE_H + +struct st_drpk +{ + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long FIFODATA:32; + } BIT; + } FIFODATA0; + char wk0[508]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long FIFODATA:32; + } BIT; + } FIFODATA1; + char wk1[508]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long FIFODATA:32; + } BIT; + } FIFODATA2; + char wk2[508]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long FIFODATA:32; + } BIT; + } FIFODATA3; + char wk3[508]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long FIFODATA:32; + } BIT; + } FIFODATA4; + char wk4[508]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long FIFODATA:32; + } BIT; + } FIFODATA5; +}; + +#define DRPK (*(volatile struct st_drpk *)0xEAFD3000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drw_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drw_iodefine.h new file mode 100644 index 0000000..d152c3e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/drw_iodefine.h @@ -0,0 +1,531 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef DRW_IODEFINE_H +#define DRW_IODEFINE_H + +struct st_drw +{ + union + { + unsigned long LONG; + struct + { + unsigned long LIM1ENABLE:1; + unsigned long LIM2ENABLE:1; + unsigned long LIM3ENABLE:1; + unsigned long LIM4ENABLE:1; + unsigned long LIM5ENABLE:1; + unsigned long LIM6ENABLE:1; + unsigned long QUAD1ENABLE:1; + unsigned long QUAD2ENABLE:1; + unsigned long QUAD3ENABLE:1; + unsigned long LIM1THRESHOLD:1; + unsigned long LIM2THRESHOLD:1; + unsigned long LIM3THRESHOLD:1; + unsigned long LIM4THRESHOLD:1; + unsigned long LIM5THRESHOLD:1; + unsigned long LIM6THRESHOLD:1; + unsigned long BAND1ENABLE:1; + unsigned long BAND2ENABLE:1; + unsigned long UNION12:1; + unsigned long UNION34:1; + unsigned long UNION56:1; + unsigned long UNIONAB:1; + unsigned long UNIONCD:1; + unsigned long SPANABORT:1; + unsigned long SPANSTORE:1; + unsigned long :8; + } BIT; + } CONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long PATTERNENABLE:1; + unsigned long TEXTUREENABLE:1; + unsigned long PATTERNSOURCEL5:1; + unsigned long USEACB:1; + unsigned long READFORMAT_3_2:2; + unsigned long BSFA:1; + unsigned long BDFA:1; + unsigned long WRITEFORMAT_2:1; + unsigned long BSF:1; + unsigned long BDF:1; + unsigned long BSI:1; + unsigned long BDI:1; + unsigned long BC2:1; + unsigned long TEXTURECLAMPX:1; + unsigned long TEXTURECLAMPY:1; + unsigned long TEXTUREFILTERX:1; + unsigned long TEXTUREFILTERY:1; + unsigned long READFORMAT_1_0:2; + unsigned long WRITEFORMAT_1_0:2; + unsigned long WRITEALPHA:2; + unsigned long RLEENABLE:1; + unsigned long CLUTENABLE:1; + unsigned long COLKEYENABLE:1; + unsigned long CLUTFORMAT:1; + unsigned long BSIA:1; + unsigned long BDIA:1; + unsigned long RLEPIXELWIDTH:2; + } BIT; + } CONTROL2; + char wk0[8]; + union + { + unsigned long LONG; + struct + { + unsigned long LSTART:32; + } BIT; + } L1START; + union + { + unsigned long LONG; + struct + { + unsigned long LSTART:32; + } BIT; + } L2START; + union + { + unsigned long LONG; + struct + { + unsigned long LSTART:32; + } BIT; + } L3START; + union + { + unsigned long LONG; + struct + { + unsigned long LSTART:32; + } BIT; + } L4START; + union + { + unsigned long LONG; + struct + { + unsigned long LSTART:32; + } BIT; + } L5START; + union + { + unsigned long LONG; + struct + { + unsigned long LSTART:32; + } BIT; + } L6START; + union + { + unsigned long LONG; + struct + { + unsigned long LXADD:32; + } BIT; + } L1XADD; + union + { + unsigned long LONG; + struct + { + unsigned long LXADD:32; + } BIT; + } L2XADD; + union + { + unsigned long LONG; + struct + { + unsigned long LXADD:32; + } BIT; + } L3XADD; + union + { + unsigned long LONG; + struct + { + unsigned long LXADD:32; + } BIT; + } L4XADD; + union + { + unsigned long LONG; + struct + { + unsigned long LXADD:32; + } BIT; + } L5XADD; + union + { + unsigned long LONG; + struct + { + unsigned long LXADD:32; + } BIT; + } L6XADD; + union + { + unsigned long LONG; + struct + { + unsigned long LYADD:32; + } BIT; + } L1YADD; + union + { + unsigned long LONG; + struct + { + unsigned long LYADD:32; + } BIT; + } L2YADD; + union + { + unsigned long LONG; + struct + { + unsigned long LYADD:32; + } BIT; + } L3YADD; + union + { + unsigned long LONG; + struct + { + unsigned long LYADD:32; + } BIT; + } L4YADD; + union + { + unsigned long LONG; + struct + { + unsigned long LYADD:32; + } BIT; + } L5YADD; + union + { + unsigned long LONG; + struct + { + unsigned long LYADD:32; + } BIT; + } L6YADD; + union + { + unsigned long LONG; + struct + { + unsigned long LBAND:32; + } BIT; + } L1BAND; + union + { + unsigned long LONG; + struct + { + unsigned long LBAND:32; + } BIT; + } L2BAND; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long COLOR1B:8; + unsigned long COLOR1G:8; + unsigned long COLOR1R:8; + unsigned long COLOR1A:8; + } BIT; + } COLOR1; + union + { + unsigned long LONG; + struct + { + unsigned long COLOR2B:8; + unsigned long COLOR2G:8; + unsigned long COLOR2R:8; + unsigned long COLOR2A:8; + } BIT; + } COLOR2; + char wk2[8]; + union + { + unsigned long LONG; + struct + { + unsigned long PATTERN:8; + unsigned long :24; + } BIT; + } PATTERN; + union + { + unsigned long LONG; + struct + { + unsigned long SIZEX:16; + unsigned long SIZEY:16; + } BIT; + } SIZE; + union + { + unsigned long LONG; + struct + { + unsigned long PITCH:16; + unsigned long SSD:16; + } BIT; + } PITCH; + union + { + unsigned long LONG; + struct + { + unsigned long ORIGIN:32; + } BIT; + } ORIGIN; + char wk3[12]; + union + { + unsigned long LONG; + struct + { + unsigned long LUSTART:32; + } BIT; + } LUSTART; + union + { + unsigned long LONG; + struct + { + unsigned long LUXADD:32; + } BIT; + } LUXADD; + union + { + unsigned long LONG; + struct + { + unsigned long LUYADD:32; + } BIT; + } LUYADD; + union + { + unsigned long LONG; + struct + { + unsigned long LVSTARTI:32; + } BIT; + } LVSTARTI; + union + { + unsigned long LONG; + struct + { + unsigned long LVSTARTF:16; + unsigned long :16; + } BIT; + } LVSTARTF; + union + { + unsigned long LONG; + struct + { + unsigned long LVXADDI:32; + } BIT; + } LVXADDI; + union + { + unsigned long LONG; + struct + { + unsigned long LVYADDI:32; + } BIT; + } LVYADDI; + union + { + unsigned long LONG; + struct + { + unsigned long LVXADDF:16; + unsigned long LVYADDF:16; + } BIT; + } LVYXADDF; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TEXPITCH:11; + unsigned long :21; + } BIT; + } TEXPITCH; + union + { + unsigned long LONG; + struct + { + unsigned long TEXUMASK:11; + unsigned long TEXVMASK:21; + } BIT; + } TEXMASK; + union + { + unsigned long LONG; + struct + { + unsigned long TEXORIGIN:32; + } BIT; + } TEXORIGIN; + union + { + unsigned long LONG; + struct + { + unsigned long ENUMIRQEN:1; + unsigned long DLISTIRQEN:1; + unsigned long ENUMIRQCLR:1; + unsigned long DLISTIRQCLR:1; + unsigned long BUSIRQEN:1; + unsigned long BUSIRQCLR:1; + unsigned long :26; + } BIT; + } IRQCTL; + union + { + unsigned long LONG; + struct + { + unsigned long CENABLEFX:1; + unsigned long CFLUSHFX:1; + unsigned long CENABLETX:1; + unsigned long CFLUSHTX:1; + unsigned long :28; + } BIT; + } CACHECTL; + union + { + unsigned long LONG; + struct + { + unsigned long DLISTSTART:32; + } BIT; + } DLISTSTART; + union + { + unsigned long LONG; + struct + { + unsigned long PERFCOUNT:32; + } BIT; + } PERFCOUNT1; + union + { + unsigned long LONG; + struct + { + unsigned long PERFCOUNT:32; + } BIT; + } PERFCOUNT2; + union + { + unsigned long LONG; + struct + { + unsigned long PERFTRIGGER1:5; + unsigned long :11; + unsigned long PERFTRIGGER2:5; + unsigned long :11; + } BIT; + } PERFTRIGGER; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CLADDR:8; + unsigned long :24; + } BIT; + } TEXCLADDR; + union + { + unsigned long LONG; + struct + { + unsigned long CLDATA:32; + } BIT; + } TEXCLDATA; + union + { + unsigned long LONG; + struct + { + unsigned long CLOFFSET:8; + unsigned long :24; + } BIT; + } TEXCLOFFSET; + union + { + unsigned long LONG; + struct + { + unsigned long COLKEYB:8; + unsigned long COLKEYG:8; + unsigned long COLKEYR:8; + unsigned long :8; + } BIT; + } COLKEY; +}; + +#define DRW (*(volatile struct st_drw *)0xE820A000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/edmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/edmac_iodefine.h new file mode 100644 index 0000000..bc5c36c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/edmac_iodefine.h @@ -0,0 +1,322 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef EDMAC_IODEFINE_H +#define EDMAC_IODEFINE_H + +struct st_edmac +{ + union + { + unsigned long LONG; + struct + { + unsigned long SWR:1; + unsigned long :3; + unsigned long DL:2; + unsigned long DE:1; + unsigned long :25; + } BIT; + } EDMR; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TR:1; + unsigned long :31; + } BIT; + } EDTRR; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RR:1; + unsigned long :31; + } BIT; + } EDRRR; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TDLAR:32; + } BIT; + } TDLAR; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RDLAR:32; + } BIT; + } RDLAR; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CERF:1; + unsigned long PRE:1; + unsigned long RTSF:1; + unsigned long RTLF:1; + unsigned long RRF:1; + unsigned long :2; + unsigned long RMAF:1; + unsigned long TRO:1; + unsigned long CD:1; + unsigned long DLC:1; + unsigned long CND:1; + unsigned long :4; + unsigned long RFOF:1; + unsigned long RDE:1; + unsigned long FR:1; + unsigned long TFUF:1; + unsigned long TDE:1; + unsigned long TC:1; + unsigned long ECI:1; + unsigned long :1; + unsigned long RFCOF:1; + unsigned long RABT:1; + unsigned long TABT:1; + unsigned long :3; + unsigned long TWB:1; + unsigned long :1; + } BIT; + } EESR; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CERFIP:1; + unsigned long PREIP:1; + unsigned long RTSFIP:1; + unsigned long RTLFIP:1; + unsigned long RRFIP:1; + unsigned long :2; + unsigned long RMAFIP:1; + unsigned long TROIP:1; + unsigned long CDIP:1; + unsigned long DLCIP:1; + unsigned long CNDIP:1; + unsigned long :4; + unsigned long RFOFIP:1; + unsigned long RDEIP:1; + unsigned long FRIP:1; + unsigned long TFUFIP:1; + unsigned long TDEIP:1; + unsigned long TCIP:1; + unsigned long ECIIP:1; + unsigned long :1; + unsigned long RFCOFIP:1; + unsigned long RABTIP:1; + unsigned long TABTIP:1; + unsigned long :3; + unsigned long TWBIP:1; + unsigned long :1; + } BIT; + } EESIPR; + char wk6[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long RRFCE:1; + unsigned long :2; + unsigned long RMAFCE:1; + unsigned long :24; + } BIT; + } TRSCER; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MFC:16; + unsigned long :16; + } BIT; + } RMFCR; + char wk8[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TFT:11; + unsigned long :21; + } BIT; + } TFTR; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RFD:5; + unsigned long :3; + unsigned long TFD:5; + unsigned long :19; + } BIT; + } FDR; + char wk10[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RNR:1; + unsigned long :31; + } BIT; + } RMCR; + char wk11[8]; + union + { + unsigned long LONG; + struct + { + unsigned long UNDER:16; + unsigned long :16; + } BIT; + } TFUCR; + union + { + unsigned long LONG; + struct + { + unsigned long OVER:16; + unsigned long :16; + } BIT; + } RFOCR; + union + { + unsigned long LONG; + struct + { + unsigned long ELB:1; + unsigned long :31; + } BIT; + } IOSR; + union + { + unsigned long LONG; + struct + { + unsigned long RFDO:3; + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + } BIT; + } FCFTR; + char wk12[4]; + union + { + unsigned long LONG; + struct + { + unsigned long PADR:6; + unsigned long :10; + unsigned long PADS:2; + unsigned long :14; + } BIT; + } RPADIR; + union + { + unsigned long LONG; + struct + { + unsigned long TIS:1; + unsigned long :3; + unsigned long TIM:1; + unsigned long :27; + } BIT; + } TRIMD; + char wk13[72]; + union + { + unsigned long LONG; + struct + { + unsigned long RBWAR:32; + } BIT; + } RBWAR; + union + { + unsigned long LONG; + struct + { + unsigned long RDFAR:32; + } BIT; + } RDFAR; + char wk14[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TBRAR:32; + } BIT; + } TBRAR; + union + { + unsigned long LONG; + struct + { + unsigned long TDFAR:32; + } BIT; + } TDFAR; +}; + +#define EDMAC0 (*(volatile struct st_edmac *)0xE8204000) +#define EDMAC1 (*(volatile struct st_edmac *)0xE8204200) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/eptpc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/eptpc_iodefine.h new file mode 100644 index 0000000..d16156d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/eptpc_iodefine.h @@ -0,0 +1,1411 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef EPTPC_IODEFINE_H +#define EPTPC_IODEFINE_H + +struct st_eptpc +{ + union + { + unsigned long LONG; + struct + { + unsigned long RESET:1; + unsigned long :31; + } BIT; + } PTRSTR; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long SCLKSEL:3; + unsigned long :21; + } BIT; + } STCSELR; + union + { + unsigned long LONG; + struct + { + unsigned long BYPASS0:1; + unsigned long :15; + unsigned long BYPASS1:1; + unsigned long :15; + } BIT; + } BYPASS; + char wk0[2804]; + union + { + unsigned long LONG; + struct + { + unsigned long ST:1; + unsigned long SY0:1; + unsigned long SY1:1; + unsigned long PRC:1; + unsigned long :12; + unsigned long CYC0:1; + unsigned long CYC1:1; + unsigned long CYC2:1; + unsigned long CYC3:1; + unsigned long CYC4:1; + unsigned long CYC5:1; + unsigned long :10; + } BIT; + } MIESR; + union + { + unsigned long LONG; + struct + { + unsigned long ST:1; + unsigned long SY0:1; + unsigned long SY1:1; + unsigned long PR:1; + unsigned long :12; + unsigned long CYC0:1; + unsigned long CYC1:1; + unsigned long CYC2:1; + unsigned long CYC3:1; + unsigned long CYC4:1; + unsigned long CYC5:1; + unsigned long :10; + } BIT; + } MIEIPR; + char wk1[8]; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long PLSP:1; + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + } BIT; + } ELIPPR; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long PLSP:1; + unsigned long :7; + unsigned long PLSN:1; + unsigned long :7; + } BIT; + } ELIPACR; + char wk2[40]; + union + { + unsigned long LONG; + struct + { + unsigned long SYNC:1; + unsigned long SYNCOUT:1; + unsigned long :1; + unsigned long SYNTOUT:1; + unsigned long W10D:1; + unsigned long :27; + } BIT; + } STSR; + union + { + unsigned long LONG; + struct + { + unsigned long SYNC:1; + unsigned long SYNCOUT:1; + unsigned long :1; + unsigned long SYNTOUT:1; + unsigned long W10D:1; + unsigned long :27; + } BIT; + } STIPR; + char wk3[8]; + union + { + unsigned long LONG; + struct + { + unsigned long STCF:2; + unsigned long :30; + } BIT; + } STCFR; + union + { + unsigned long LONG; + struct + { + unsigned long WINT:8; + unsigned long :5; + unsigned long CMOD:1; + unsigned long :1; + unsigned long W10S:1; + unsigned long SYTH:4; + unsigned long DVTH:4; + unsigned long :4; + unsigned long ALEN0:1; + unsigned long ALEN1:1; + unsigned long :2; + } BIT; + } STMR; + union + { + unsigned long LONG; + struct + { + unsigned long SYNTOR:32; + } BIT; + } SYNTOR; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long IPTSEL0:1; + unsigned long IPTSEL1:1; + unsigned long IPTSEL2:1; + unsigned long IPTSEL3:1; + unsigned long IPTSEL4:1; + unsigned long IPTSEL5:1; + unsigned long :26; + } BIT; + } IPTSELR; + union + { + unsigned long LONG; + struct + { + unsigned long MINTEN0:1; + unsigned long MINTEN1:1; + unsigned long MINTEN2:1; + unsigned long MINTEN3:1; + unsigned long MINTEN4:1; + unsigned long MINTEN5:1; + unsigned long :26; + } BIT; + } MITSELR; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SYSEL:1; + unsigned long :31; + } BIT; + } STCHSELR; + char wk6[16]; + union + { + unsigned long LONG; + struct + { + unsigned long STR:1; + unsigned long :31; + } BIT; + } SYNSTARTR; + union + { + unsigned long LONG; + struct + { + unsigned long LOAD:1; + unsigned long :31; + } BIT; + } LCIVLDR; + char wk7[8]; + union + { + unsigned long LONG; + struct + { + unsigned long SYNTDARU:32; + } BIT; + } SYNTDARU; + union + { + unsigned long LONG; + struct + { + unsigned long SYNTDARL:32; + } BIT; + } SYNTDARL; + union + { + unsigned long LONG; + struct + { + unsigned long SYNTDBRU:32; + } BIT; + } SYNTDBRU; + union + { + unsigned long LONG; + struct + { + unsigned long SYNTDBRL:32; + } BIT; + } SYNTDBRL; + char wk8[16]; + union + { + unsigned long LONG; + struct + { + unsigned long LCIVRU:16; + unsigned long :16; + } BIT; + } LCIVRU; + union + { + unsigned long LONG; + struct + { + unsigned long LCIVRM:16; + unsigned long :16; + } BIT; + } LCIVRM; + union + { + unsigned long LONG; + struct + { + unsigned long LCIVRL:16; + unsigned long :16; + } BIT; + } LCIVRL; + char wk9[104]; + union + { + unsigned long LONG; + struct + { + unsigned long GW10:1; + unsigned long :31; + } BIT; + } GETW10R; + union + { + unsigned long LONG; + struct + { + unsigned long PLIMITRU:31; + unsigned long :1; + } BIT; + } PLIMITRU; + union + { + unsigned long LONG; + struct + { + unsigned long PLIMITRM:32; + } BIT; + } PLIMITRM; + union + { + unsigned long LONG; + struct + { + unsigned long PLIMITRL:32; + } BIT; + } PLIMITRL; + union + { + unsigned long LONG; + struct + { + unsigned long MLIMITRU:31; + unsigned long :1; + } BIT; + } MLIMITRU; + union + { + unsigned long LONG; + struct + { + unsigned long MLIMITRM:32; + } BIT; + } MLIMITRM; + union + { + unsigned long LONG; + struct + { + unsigned long MLIMITRL:32; + } BIT; + } MLIMITRL; + union + { + unsigned long LONG; + struct + { + unsigned long INFO:1; + unsigned long :31; + } BIT; + } GETINFOR; + char wk10[44]; + union + { + unsigned long LONG; + struct + { + unsigned long LCCVRU:16; + unsigned long :16; + } BIT; + } LCCVRU; + union + { + unsigned long LONG; + struct + { + unsigned long LCCVRM:32; + } BIT; + } LCCVRM; + union + { + unsigned long LONG; + struct + { + unsigned long LCCVRL:32; + } BIT; + } LCCVRL; + char wk11[148]; + union + { + unsigned long LONG; + struct + { + unsigned long PW10VRU:32; + } BIT; + } PW10VRU; + union + { + unsigned long LONG; + struct + { + unsigned long PW10VRM:32; + } BIT; + } PW10VRM; + union + { + unsigned long LONG; + struct + { + unsigned long PW10VRL:32; + } BIT; + } PW10VRL; + char wk12[180]; + union + { + unsigned long LONG; + struct + { + unsigned long MW10RU:32; + } BIT; + } MW10RU; + union + { + unsigned long LONG; + struct + { + unsigned long MW10RM:32; + } BIT; + } MW10RM; + union + { + unsigned long LONG; + struct + { + unsigned long MW10RL:32; + } BIT; + } MW10RL; + char wk13[36]; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRU0:32; + } BIT; + } TMSTTRU0; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRL0:32; + } BIT; + } TMSTTRL0; + union + { + unsigned long LONG; + struct + { + unsigned long TMCYCR0:32; + } BIT; + } TMCYCR0; + union + { + unsigned long LONG; + struct + { + unsigned long TMPLSR0:29; + unsigned long :3; + } BIT; + } TMPLSR0; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRU1:32; + } BIT; + } TMSTTRU1; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRL1:32; + } BIT; + } TMSTTRL1; + union + { + unsigned long LONG; + struct + { + unsigned long TMCYCR1:32; + } BIT; + } TMCYCR1; + union + { + unsigned long LONG; + struct + { + unsigned long TMPLSR1:29; + unsigned long :3; + } BIT; + } TMPLSR1; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRU2:32; + } BIT; + } TMSTTRU2; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRL2:32; + } BIT; + } TMSTTRL2; + union + { + unsigned long LONG; + struct + { + unsigned long TMCYCR2:32; + } BIT; + } TMCYCR2; + union + { + unsigned long LONG; + struct + { + unsigned long TMPLSR2:29; + unsigned long :3; + } BIT; + } TMPLSR2; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRU3:32; + } BIT; + } TMSTTRU3; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRL3:32; + } BIT; + } TMSTTRL3; + union + { + unsigned long LONG; + struct + { + unsigned long TMCYCR3:32; + } BIT; + } TMCYCR3; + union + { + unsigned long LONG; + struct + { + unsigned long TMPLSR3:29; + unsigned long :3; + } BIT; + } TMPLSR3; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRU4:32; + } BIT; + } TMSTTRU4; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRL4:32; + } BIT; + } TMSTTRL4; + union + { + unsigned long LONG; + struct + { + unsigned long TMCYCR4:32; + } BIT; + } TMCYCR4; + union + { + unsigned long LONG; + struct + { + unsigned long TMPLSR4:29; + unsigned long :3; + } BIT; + } TMPLSR4; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRU5:32; + } BIT; + } TMSTTRU5; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTTRL5:32; + } BIT; + } TMSTTRL5; + union + { + unsigned long LONG; + struct + { + unsigned long TMCYCR5:32; + } BIT; + } TMCYCR5; + union + { + unsigned long LONG; + struct + { + unsigned long TMPLSR5:29; + unsigned long :3; + } BIT; + } TMPLSR5; + char wk14[28]; + union + { + unsigned long LONG; + struct + { + unsigned long EN0:1; + unsigned long EN1:1; + unsigned long EN2:1; + unsigned long EN3:1; + unsigned long EN4:1; + unsigned long EN5:1; + unsigned long :26; + } BIT; + } TMSTARTR; + char wk15[128]; + union + { + unsigned long LONG; + struct + { + unsigned long OVRE0:1; + unsigned long OVRE1:1; + unsigned long OVRE2:1; + unsigned long OVRE3:1; + unsigned long :4; + unsigned long MACE:1; + unsigned long :19; + unsigned long URE0:1; + unsigned long URE1:1; + unsigned long :2; + } BIT; + } PRSR; + union + { + unsigned long LONG; + struct + { + unsigned long OVRE0:1; + unsigned long OVRE1:1; + unsigned long OVRE2:1; + unsigned long OVRE3:1; + unsigned long :4; + unsigned long MACE:1; + unsigned long :19; + unsigned long URE0:1; + unsigned long URE1:1; + unsigned long :2; + } BIT; + } PRIPR; + char wk16[8]; + union + { + unsigned long LONG; + struct + { + unsigned long PRMACRU0:24; + unsigned long :8; + } BIT; + } PRMACRU0; + union + { + unsigned long LONG; + struct + { + unsigned long PRMACRL0:24; + unsigned long :8; + } BIT; + } PRMACRL0; + union + { + unsigned long LONG; + struct + { + unsigned long PRMACRU1:24; + unsigned long :8; + } BIT; + } PRMACRU1; + union + { + unsigned long LONG; + struct + { + unsigned long PRMACRL1:24; + unsigned long :8; + } BIT; + } PRMACRL1; + union + { + unsigned long LONG; + struct + { + unsigned long TDIS:2; + unsigned long :30; + } BIT; + } TRNDISR; + char wk17[12]; + union + { + unsigned long LONG; + struct + { + unsigned long MOD:1; + unsigned long :7; + unsigned long FWD0:1; + unsigned long FWD1:1; + unsigned long :22; + } BIT; + } TRNMR; + union + { + unsigned long LONG; + struct + { + unsigned long THVAL:11; + unsigned long :21; + } BIT; + } TRNCTTDR; +}; + +struct st_eptpc0 +{ + union + { + unsigned long LONG; + struct + { + unsigned long OFMUD:1; + unsigned long INTCHG:1; + unsigned long MPDUD:1; + unsigned long :1; + unsigned long DRPTO:1; + unsigned long INTDEV:1; + unsigned long DRQOVR:1; + unsigned long :5; + unsigned long RECLP:1; + unsigned long :1; + unsigned long INFABT:1; + unsigned long :1; + unsigned long RESDN:1; + unsigned long GENDN:1; + unsigned long :14; + } BIT; + } SYSR; + union + { + unsigned long LONG; + struct + { + unsigned long OFMUD:1; + unsigned long INTCHG:1; + unsigned long MPDUD:1; + unsigned long :1; + unsigned long DRPTO:1; + unsigned long INTDEV:1; + unsigned long DRQOVR:1; + unsigned long :5; + unsigned long RECLP:1; + unsigned long :1; + unsigned long INFABT:1; + unsigned long :1; + unsigned long RESDN:1; + unsigned long GENDN:1; + unsigned long :14; + } BIT; + } SYIPR; + char wk0[8]; + union + { + unsigned long LONG; + struct + { + unsigned long SYMACRU:24; + unsigned long :8; + } BIT; + } SYMACRU; + union + { + unsigned long LONG; + struct + { + unsigned long SYMACRL:24; + unsigned long :8; + } BIT; + } SYMACRL; + union + { + unsigned long LONG; + struct + { + unsigned long CTL:8; + unsigned long :24; + } BIT; + } SYLLCCTLR; + union + { + unsigned long LONG; + struct + { + unsigned long SYIPADDRR:32; + } BIT; + } SYIPADDRR; + char wk1[32]; + union + { + unsigned long LONG; + struct + { + unsigned long VER:4; + unsigned long TRSP:4; + unsigned long :24; + } BIT; + } SYSPVRR; + union + { + unsigned long LONG; + struct + { + unsigned long DNUM:8; + unsigned long :24; + } BIT; + } SYDOMR; + char wk2[8]; + union + { + unsigned long LONG; + struct + { + unsigned long FLAG0:1; + unsigned long FLAG1:1; + unsigned long FLAG2:1; + unsigned long FLAG3:1; + unsigned long FLAG4:1; + unsigned long FLAG5:1; + unsigned long :2; + unsigned long FLAG8:1; + unsigned long :1; + unsigned long FLAG10:1; + unsigned long :2; + unsigned long FLAG13:1; + unsigned long FLAG14:1; + unsigned long :17; + } BIT; + } ANFR; + union + { + unsigned long LONG; + struct + { + unsigned long :10; + unsigned long FLAG10:1; + unsigned long :2; + unsigned long FLAG13:1; + unsigned long FLAG14:1; + unsigned long :17; + } BIT; + } SYNFR; + union + { + unsigned long LONG; + struct + { + unsigned long :10; + unsigned long FLAG10:1; + unsigned long :2; + unsigned long FLAG13:1; + unsigned long FLAG14:1; + unsigned long :17; + } BIT; + } DYRQFR; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long FLAG8:1; + unsigned long FLAG9:1; + unsigned long FLAG10:1; + unsigned long :2; + unsigned long FLAG13:1; + unsigned long FLAG14:1; + unsigned long :17; + } BIT; + } DYRPFR; + union + { + unsigned long LONG; + struct + { + unsigned long SYCIDRL:32; + } BIT; + } SYCIDRL; + union + { + unsigned long LONG; + struct + { + unsigned long SYCIDRU:32; + } BIT; + } SYCIDRU; + union + { + unsigned long LONG; + struct + { + unsigned long PNUM:16; + unsigned long :16; + } BIT; + } SYPNUMR; + char wk3[20]; + union + { + unsigned long LONG; + struct + { + unsigned long BMUP:1; + unsigned long STUP:1; + unsigned long ANUP:1; + unsigned long :29; + } BIT; + } SYRVLDR; + char wk4[12]; + union + { + unsigned long LONG; + struct + { + unsigned long ANCE:2; + unsigned long :2; + unsigned long SYNC:3; + unsigned long :1; + unsigned long FUP:3; + unsigned long :1; + unsigned long DRQ:3; + unsigned long :1; + unsigned long DRP:3; + unsigned long :1; + unsigned long PDRQ:3; + unsigned long :1; + unsigned long PDRP:3; + unsigned long :1; + unsigned long PDFUP:3; + unsigned long :1; + } BIT; + } SYRFL1R; + union + { + unsigned long LONG; + struct + { + unsigned long MAN:2; + unsigned long :2; + unsigned long SIG:2; + unsigned long :22; + unsigned long ILL:2; + unsigned long :2; + } BIT; + } SYRFL2R; + union + { + unsigned long LONG; + struct + { + unsigned long ANCE:1; + unsigned long :3; + unsigned long SYNC:1; + unsigned long :3; + unsigned long DRQ:1; + unsigned long :3; + unsigned long PDRQ:1; + unsigned long :19; + } BIT; + } SYTRENR; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MTCIDL:32; + } BIT; + } MTCIDL; + union + { + unsigned long LONG; + struct + { + unsigned long MTCIDU:32; + } BIT; + } MTCIDU; + union + { + unsigned long LONG; + struct + { + unsigned long PNUM:16; + unsigned long :16; + } BIT; + } MTPID; + char wk6[20]; + union + { + unsigned long LONG; + struct + { + unsigned long ANCE:8; + unsigned long SYNC:8; + unsigned long DREQ:8; + unsigned long :8; + } BIT; + } SYTLIR; + union + { + unsigned long LONG; + struct + { + unsigned long ANCE:8; + unsigned long SYNC:8; + unsigned long DRESP:8; + unsigned long :8; + } BIT; + } SYRLIR; + union + { + unsigned long LONG; + struct + { + unsigned long OFMRL:32; + } BIT; + } OFMRL; + union + { + unsigned long LONG; + struct + { + unsigned long OFMRU:32; + } BIT; + } OFMRU; + union + { + unsigned long LONG; + struct + { + unsigned long MPDRU:32; + } BIT; + } MPDRU; + union + { + unsigned long LONG; + struct + { + unsigned long MPDRL:32; + } BIT; + } MPDRL; + char wk7[8]; + union + { + unsigned long LONG; + struct + { + unsigned long GMPR2:8; + unsigned long :8; + unsigned long GMPR1:8; + unsigned long :8; + } BIT; + } GMPR; + union + { + unsigned long LONG; + struct + { + unsigned long GMCQR:32; + } BIT; + } GMCQR; + union + { + unsigned long LONG; + struct + { + unsigned long GMIDRU:32; + } BIT; + } GMIDRU; + union + { + unsigned long LONG; + struct + { + unsigned long GMIDRL:32; + } BIT; + } GMIDRL; + union + { + unsigned long LONG; + struct + { + unsigned long TSRC:8; + unsigned long :8; + unsigned long CUTO:16; + } BIT; + } CUOTSR; + union + { + unsigned long LONG; + struct + { + unsigned long SRMV:16; + unsigned long :16; + } BIT; + } SRR; + char wk8[8]; + union + { + unsigned long LONG; + struct + { + unsigned long PPMACRU:24; + unsigned long :8; + } BIT; + } PPMACRU; + union + { + unsigned long LONG; + struct + { + unsigned long PPMACRL:24; + unsigned long :8; + } BIT; + } PPMACRL; + union + { + unsigned long LONG; + struct + { + unsigned long PDMACRU:24; + unsigned long :8; + } BIT; + } PDMACRU; + union + { + unsigned long LONG; + struct + { + unsigned long PDMACRL:24; + unsigned long :8; + } BIT; + } PDMACRL; + union + { + unsigned long LONG; + struct + { + unsigned long TYPE:16; + unsigned long :16; + } BIT; + } PETYPER; + char wk9[12]; + union + { + unsigned long LONG; + struct + { + unsigned long PPIPR:32; + } BIT; + } PPIPR; + union + { + unsigned long LONG; + struct + { + unsigned long PDIPR:32; + } BIT; + } PDIPR; + union + { + unsigned long LONG; + struct + { + unsigned long EVTO:8; + unsigned long :24; + } BIT; + } PETOSR; + union + { + unsigned long LONG; + struct + { + unsigned long GETO:8; + unsigned long :24; + } BIT; + } PGTOSR; + union + { + unsigned long LONG; + struct + { + unsigned long PRTL:8; + unsigned long :24; + } BIT; + } PPTTLR; + union + { + unsigned long LONG; + struct + { + unsigned long PDTL:8; + unsigned long :24; + } BIT; + } PDTTLR; + union + { + unsigned long LONG; + struct + { + unsigned long EVUPT:16; + unsigned long :16; + } BIT; + } PEUDPR; + union + { + unsigned long LONG; + struct + { + unsigned long GEUPT:16; + unsigned long :16; + } BIT; + } PGUDPR; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:1; + unsigned long PRT:1; + unsigned long ENB:1; + unsigned long :13; + unsigned long EXTPRM:1; + unsigned long :15; + } BIT; + } FFLTR; + char wk10[28]; + union + { + unsigned long LONG; + struct + { + unsigned long FMAC0RU:24; + unsigned long :8; + } BIT; + } FMAC0RU; + union + { + unsigned long LONG; + struct + { + unsigned long FMAC0RL:24; + unsigned long :8; + } BIT; + } FMAC0RL; + union + { + unsigned long LONG; + struct + { + unsigned long FMAC1RU:24; + unsigned long :8; + } BIT; + } FMAC1RU; + union + { + unsigned long LONG; + struct + { + unsigned long FMAC1RL:24; + unsigned long :8; + } BIT; + } FMAC1RL; + char wk11[80]; + union + { + unsigned long LONG; + struct + { + unsigned long DASYMRU:16; + unsigned long :16; + } BIT; + } DASYMRU; + union + { + unsigned long LONG; + struct + { + unsigned long DASYMRL:32; + } BIT; + } DASYMRL; + union + { + unsigned long LONG; + struct + { + unsigned long EGP:16; + unsigned long INGP:16; + } BIT; + } TSLATR; + union + { + unsigned long LONG; + struct + { + unsigned long TCYC:8; + unsigned long :4; + unsigned long SBDIS:1; + unsigned long :3; + unsigned long FILDIS:1; + unsigned long :3; + unsigned long TCMOD:1; + unsigned long :11; + } BIT; + } SYCONFR; + union + { + unsigned long LONG; + struct + { + unsigned long FORM0:1; + unsigned long FORM1:1; + unsigned long :30; + } BIT; + } SYFORMR; + union + { + unsigned long LONG; + struct + { + unsigned long RSTOUTR:32; + } BIT; + } RSTOUTR; +}; + +#define EPTPC (*(volatile struct st_eptpc *)0xE8204500) +#define EPTPC0 (*(volatile struct st_eptpc0 *)0xE8205800) +#define EPTPC1 (*(volatile struct st_eptpc0 *)0xE8205C00) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/etherc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/etherc_iodefine.h new file mode 100644 index 0000000..3907fc9 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/etherc_iodefine.h @@ -0,0 +1,317 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef ETHERC_IODEFINE_H +#define ETHERC_IODEFINE_H + +struct st_etherc +{ + union + { + unsigned long LONG; + struct + { + unsigned long PRM:1; + unsigned long DM:1; + unsigned long RTM:1; + unsigned long ILB:1; + unsigned long :1; + unsigned long TE:1; + unsigned long RE:1; + unsigned long :2; + unsigned long MPDE:1; + unsigned long :2; + unsigned long PRCEF:1; + unsigned long :3; + unsigned long TXF:1; + unsigned long RXF:1; + unsigned long PFR:1; + unsigned long ZPF:1; + unsigned long TPC:1; + unsigned long :11; + } BIT; + } ECMR; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RFL:12; + unsigned long :20; + } BIT; + } RFLR; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long ICD:1; + unsigned long MPD:1; + unsigned long LCHNG:1; + unsigned long :1; + unsigned long PSRTO:1; + unsigned long BFR:1; + unsigned long :26; + } BIT; + } ECSR; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long ICDIP:1; + unsigned long MPDIP:1; + unsigned long LCHNGIP:1; + unsigned long :1; + unsigned long PSRTOIP:1; + unsigned long BFSIPR:1; + unsigned long :26; + } BIT; + } ECSIPR; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MDC:1; + unsigned long MMD:1; + unsigned long MDO:1; + unsigned long MDI:1; + unsigned long :28; + } BIT; + } PIR; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long LMON:1; + unsigned long :31; + } BIT; + } PSR; + char wk5[20]; + union + { + unsigned long LONG; + struct + { + unsigned long RMD:20; + unsigned long :12; + } BIT; + } RDMLR; + char wk6[12]; + union + { + unsigned long LONG; + struct + { + unsigned long IPG:5; + unsigned long :27; + } BIT; + } IPGR; + union + { + unsigned long LONG; + struct + { + unsigned long AP:16; + unsigned long :16; + } BIT; + } APR; + union + { + unsigned long LONG; + struct + { + unsigned long MP:16; + unsigned long :16; + } BIT; + } MPR; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RPAUSE:8; + unsigned long :24; + } BIT; + } RFCF; + union + { + unsigned long LONG; + struct + { + unsigned long TPAUSE:16; + unsigned long :16; + } BIT; + } TPAUSER; + union + { + unsigned long LONG; + struct + { + unsigned long TXP:8; + unsigned long :24; + } BIT; + } TPAUSECR; + union + { + unsigned long LONG; + struct + { + unsigned long BCF:16; + unsigned long :16; + } BIT; + } BCFRR; + char wk8[80]; + union + { + unsigned long LONG; + struct + { + unsigned long MAHR:32; + } BIT; + } MAHR; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MALR:16; + unsigned long :16; + } BIT; + } MALR; + char wk10[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TROCR:32; + } BIT; + } TROCR; + union + { + unsigned long LONG; + struct + { + unsigned long CDCR:32; + } BIT; + } CDCR; + union + { + unsigned long LONG; + struct + { + unsigned long LCCR:32; + } BIT; + } LCCR; + union + { + unsigned long LONG; + struct + { + unsigned long CNDCR:32; + } BIT; + } CNDCR; + char wk11[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CEFCR:32; + } BIT; + } CEFCR; + union + { + unsigned long LONG; + struct + { + unsigned long FRECR:32; + } BIT; + } FRECR; + union + { + unsigned long LONG; + struct + { + unsigned long TSFRCR:32; + } BIT; + } TSFRCR; + union + { + unsigned long LONG; + struct + { + unsigned long TLFRCR:32; + } BIT; + } TLFRCR; + union + { + unsigned long LONG; + struct + { + unsigned long RFCR:32; + } BIT; + } RFCR; + union + { + unsigned long LONG; + struct + { + unsigned long MAFCR:32; + } BIT; + } MAFCR; +}; + +#define ETHERC0 (*(volatile struct st_etherc *)0xE8204100) +#define ETHERC1 (*(volatile struct st_etherc *)0xE8204300) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpio_iodefine.h new file mode 100644 index 0000000..5668c46 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpio_iodefine.h @@ -0,0 +1,3670 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef GPIO_IODEFINE_H +#define GPIO_IODEFINE_H + +struct st_gpio +{ + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P00PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P01PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P02PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P03PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P04PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P05PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P06PFS; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P10PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P11PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P12PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P13PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P14PFS; + char wk1[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P20PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P21PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P22PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P23PFS; + char wk2[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P30PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P31PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P32PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P33PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P34PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P35PFS; + char wk3[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P40PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P41PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P42PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P43PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P44PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P45PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P46PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P47PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P50PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P51PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P52PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P53PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P54PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P55PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P56PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P57PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P60PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P61PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P62PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P63PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P64PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P65PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P66PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P67PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P70PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P71PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P72PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P73PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P74PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P75PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P76PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P77PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P80PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P81PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P82PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P83PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P84PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P85PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P86PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P87PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P90PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P91PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P92PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P93PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P94PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P95PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P96PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P97PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB5PFS; + char wk4[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PD7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE6PFS; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PG7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH6PFS; + char wk6[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PK0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PK1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PK2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PK3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PK4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PK5PFS; + char wk7[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL4PFS; + char wk8[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:3; + unsigned char :3; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM1PFS; + char wk9[85]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char PFSWE:1; + unsigned char B0WI:1; + } BIT; + } PWPR; + char wk10[1312]; + union + { + unsigned char BYTE; + struct + { + unsigned char PHYMODE0:1; + unsigned char PHYMODE1:1; + unsigned char :6; + } BIT; + } PFENET; + char wk11[223]; + union + { + unsigned long LONG; + struct + { + unsigned long POC0:1; + unsigned long :1; + unsigned long POC2:1; + unsigned long POC3:1; + unsigned long :4; + unsigned long POCSEL0:1; + unsigned long :1; + unsigned long :22; + } BIT; + } PPOC; + char wk12[28]; + union + { + unsigned long LONG; + struct + { + unsigned long SD0_CLK_DRV:2; + unsigned long SD0_CMD_DRV:2; + unsigned long SD0_DAT0_DRV:2; + unsigned long SD0_DAT1_DRV:2; + unsigned long SD0_DAT2_DRV:2; + unsigned long SD0_DAT3_DRV:2; + unsigned long SD0_CLK_TDSEL:2; + unsigned long :2; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :1; + } BIT; + } PSDMMC0; + char wk13[12]; + union + { + unsigned long LONG; + struct + { + unsigned long SD0_DAT4_DRV:2; + unsigned long SD0_DAT5_DRV:2; + unsigned long SD0_DAT6_DRV:2; + unsigned long SD0_DAT7_DRV:2; + unsigned long SD0_RSTN_DRV:2; + unsigned long :6; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :1; + } BIT; + } PSDMMC1; + char wk14[12]; + union + { + unsigned long LONG; + struct + { + unsigned long SD1_CLK_DRV:2; + unsigned long SD1_CMD_DRV:2; + unsigned long SD1_DAT0_DRV:2; + unsigned long SD1_DAT1_DRV:2; + unsigned long SD1_DAT2_DRV:2; + unsigned long SD1_DAT3_DRV:2; + unsigned long SD1_CLK_TDSEL:2; + unsigned long :2; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :3; + unsigned long :1; + } BIT; + } PSDMMC2; + char wk15[28]; + union + { + unsigned long LONG; + struct + { + unsigned long QSPI0_SPCLK_DRV:2; + unsigned long QSPI0_IO0_DRV:2; + unsigned long QSPI0_IO1_DRV:2; + unsigned long QSPI0_IO2_DRV:2; + unsigned long QSPI0_IO3_DRV:2; + unsigned long QSPI0_SSL_DRV:2; + unsigned long RPC_RESETN_DRV:2; + unsigned long RPC_WPN_DRV:2; + unsigned long QSPI1_SPCLK_DRV:2; + unsigned long QSPI1_IO0_DRV:2; + unsigned long QSPI1_IO1_DRV:2; + unsigned long QSPI1_IO2_DRV:2; + unsigned long QSPI1_IO3_DRV:2; + unsigned long QSPI1_SSL_DRV:2; + unsigned long :4; + } BIT; + } PSPIBSC; + char wk16[28]; + union + { + unsigned long LONG; + struct + { + unsigned long HOSEL:1; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :1; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + unsigned long :2; + } BIT; + } PHMOM0; + char wk17[28]; + char wk18[4]; + char wk19[28]; + union + { + unsigned long LONG; + struct + { + unsigned long ET0_EXOUT_SEL:1; + unsigned long ET1_EXOUT_SEL:1; + unsigned long VBUS0_SEL:1; + unsigned long VBUS1_SEL:1; + unsigned long :28; + } BIT; + } PMODEPFS; + char wk20[12]; + union + { + unsigned char BYTE; + struct + { + unsigned char CKIO_DRV:2; + unsigned char :6; + } BIT; + } PCKIO; +}; + +struct st_port0 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short :2; + } BIT; + } PDR; + char wk0[62]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char :1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char :1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char :1; + } BIT; + } PMR; + char wk3[191]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short :2; + } BIT; + } DSCR; +}; + +struct st_port1 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short :6; + } BIT; + } PDR; + char wk0[61]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char :3; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char :3; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char :3; + } BIT; + } PMR; + char wk3[192]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short :6; + } BIT; + } DSCR; +}; + +struct st_port2 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short :8; + } BIT; + } PDR; + char wk0[60]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char :4; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char :4; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char :4; + } BIT; + } PMR; + char wk3[193]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short :8; + } BIT; + } DSCR; +}; + +struct st_port3 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short :4; + } BIT; + } PDR; + char wk0[59]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char :2; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char :2; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char :2; + } BIT; + } PMR; + char wk3[194]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short :4; + } BIT; + } DSCR; +}; + +struct st_port4 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[58]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[195]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_port5 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[57]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[196]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_port6 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[56]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[197]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_port7 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[55]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[198]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_port8 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[54]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[199]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_port9 +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[53]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[200]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_porta +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[52]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[201]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_portb +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short :4; + } BIT; + } PDR; + char wk0[51]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char :2; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char :2; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char :2; + } BIT; + } PMR; + char wk3[202]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short :4; + } BIT; + } DSCR; +}; + +struct st_portc +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[50]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[203]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_portd +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[49]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[204]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_porte +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short :2; + } BIT; + } PDR; + char wk0[48]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char :1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char :1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char :1; + } BIT; + } PMR; + char wk3[205]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short :2; + } BIT; + } DSCR; +}; + +struct st_portf +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[47]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[206]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_portg +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[46]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[207]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_porth +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short :2; + } BIT; + } PDR; + char wk0[45]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char :1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char :1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char :1; + } BIT; + } PMR; + char wk3[208]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short :2; + } BIT; + } DSCR; +}; + +struct st_portj +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short PDR6:2; + unsigned short PDR7:2; + } BIT; + } PDR; + char wk0[44]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char PODR6:1; + unsigned char PODR7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char PIDR6:1; + unsigned char PIDR7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char PMR6:1; + unsigned char PMR7:1; + } BIT; + } PMR; + char wk3[209]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short DSCR6:2; + unsigned short DSCR7:2; + } BIT; + } DSCR; +}; + +struct st_portk +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short PDR5:2; + unsigned short :4; + } BIT; + } PDR; + char wk0[43]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char PODR5:1; + unsigned char :2; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char PIDR5:1; + unsigned char :2; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char PMR5:1; + unsigned char :2; + } BIT; + } PMR; + char wk3[210]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short DSCR5:2; + unsigned short :4; + } BIT; + } DSCR; +}; + +struct st_portl +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short PDR2:2; + unsigned short PDR3:2; + unsigned short PDR4:2; + unsigned short :6; + } BIT; + } PDR; + char wk0[42]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char PODR2:1; + unsigned char PODR3:1; + unsigned char PODR4:1; + unsigned char :3; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char PIDR2:1; + unsigned char PIDR3:1; + unsigned char PIDR4:1; + unsigned char :3; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char PMR2:1; + unsigned char PMR3:1; + unsigned char PMR4:1; + unsigned char :3; + } BIT; + } PMR; + char wk3[211]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short DSCR2:2; + unsigned short DSCR3:2; + unsigned short DSCR4:2; + unsigned short :6; + } BIT; + } DSCR; +}; + +struct st_portm +{ + union + { + unsigned short WORD; + struct + { + unsigned short PDR0:2; + unsigned short PDR1:2; + unsigned short :12; + } BIT; + } PDR; + char wk0[41]; + union + { + unsigned char BYTE; + struct + { + unsigned char PODR0:1; + unsigned char PODR1:1; + unsigned char :6; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PIDR0:1; + unsigned char PIDR1:1; + unsigned char :6; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char PMR0:1; + unsigned char PMR1:1; + unsigned char :6; + } BIT; + } PMR; + char wk3[212]; + union + { + unsigned short WORD; + struct + { + unsigned short DSCR0:2; + unsigned short DSCR1:2; + unsigned short :12; + } BIT; + } DSCR; +}; + +#define GPIO (*(volatile struct st_gpio *)0xFCFFE200) +#define PORT0 (*(volatile struct st_port0 *)0xFCFFE000) +#define PORT1 (*(volatile struct st_port1 *)0xFCFFE002) +#define PORT2 (*(volatile struct st_port2 *)0xFCFFE004) +#define PORT3 (*(volatile struct st_port3 *)0xFCFFE006) +#define PORT4 (*(volatile struct st_port4 *)0xFCFFE008) +#define PORT5 (*(volatile struct st_port5 *)0xFCFFE00A) +#define PORT6 (*(volatile struct st_port6 *)0xFCFFE00C) +#define PORT7 (*(volatile struct st_port7 *)0xFCFFE00E) +#define PORT8 (*(volatile struct st_port8 *)0xFCFFE010) +#define PORT9 (*(volatile struct st_port9 *)0xFCFFE012) +#define PORTA (*(volatile struct st_porta *)0xFCFFE014) +#define PORTB (*(volatile struct st_portb *)0xFCFFE016) +#define PORTC (*(volatile struct st_portc *)0xFCFFE018) +#define PORTD (*(volatile struct st_portd *)0xFCFFE01A) +#define PORTE (*(volatile struct st_porte *)0xFCFFE01C) +#define PORTF (*(volatile struct st_portf *)0xFCFFE01E) +#define PORTG (*(volatile struct st_portg *)0xFCFFE020) +#define PORTH (*(volatile struct st_porth *)0xFCFFE022) +#define PORTJ (*(volatile struct st_portj *)0xFCFFE024) +#define PORTK (*(volatile struct st_portk *)0xFCFFE026) +#define PORTL (*(volatile struct st_portl *)0xFCFFE028) +#define PORTM (*(volatile struct st_portm *)0xFCFFE02A) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpt_iodefine.h new file mode 100644 index 0000000..06a168a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/gpt_iodefine.h @@ -0,0 +1,789 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef GPT_IODEFINE_H +#define GPT_IODEFINE_H + +struct st_gpt +{ + union + { + unsigned char BYTE; + struct + { + unsigned char :7; + unsigned char EVCON:1; + } BIT; + } GTECR; + char wk0[15]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR0; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR1; + char wk2[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR2; + char wk3[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR3; + char wk4[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR4; + char wk5[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR5; + char wk6[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR6; + char wk7[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EVS:7; + unsigned short :9; + } BIT; + } GTESR7; +}; + +struct st_gpt32e +{ + union + { + unsigned long LONG; + struct + { + unsigned long WP:1; + unsigned long :7; + unsigned long PRKEY:8; + unsigned long :16; + } BIT; + } GTWP; + union + { + unsigned long LONG; + struct + { + unsigned long CSTRT0:1; + unsigned long CSTRT1:1; + unsigned long CSTRT2:1; + unsigned long CSTRT3:1; + unsigned long CSTRT4:1; + unsigned long CSTRT5:1; + unsigned long CSTRT6:1; + unsigned long CSTRT7:1; + unsigned long :24; + } BIT; + } GTSTR; + union + { + unsigned long LONG; + struct + { + unsigned long CSTOP0:1; + unsigned long CSTOP1:1; + unsigned long CSTOP2:1; + unsigned long CSTOP3:1; + unsigned long CSTOP4:1; + unsigned long CSTOP5:1; + unsigned long CSTOP6:1; + unsigned long CSTOP7:1; + unsigned long :24; + } BIT; + } GTSTP; + union + { + unsigned long LONG; + struct + { + unsigned long CCLR0:1; + unsigned long CCLR1:1; + unsigned long CCLR2:1; + unsigned long CCLR3:1; + unsigned long CCLR4:1; + unsigned long CCLR5:1; + unsigned long CCLR6:1; + unsigned long CCLR7:1; + unsigned long :24; + } BIT; + } GTCLR; + union + { + unsigned long LONG; + struct + { + unsigned long SSGTRGAR:1; + unsigned long SSGTRGAF:1; + unsigned long SSGTRGBR:1; + unsigned long SSGTRGBF:1; + unsigned long SSGTRGCR:1; + unsigned long SSGTRGCF:1; + unsigned long SSGTRGDR:1; + unsigned long SSGTRGDF:1; + unsigned long SSCARBL:1; + unsigned long SSCARBH:1; + unsigned long SSCAFBL:1; + unsigned long SSCAFBH:1; + unsigned long SSCBRAL:1; + unsigned long SSCBRAH:1; + unsigned long SSCBFAL:1; + unsigned long SSCBFAH:1; + unsigned long SSEVTA:1; + unsigned long SSEVTB:1; + unsigned long SSEVTC:1; + unsigned long SSEVTD:1; + unsigned long SSEVTE:1; + unsigned long SSEVTF:1; + unsigned long SSEVTG:1; + unsigned long SSEVTH:1; + unsigned long :7; + unsigned long CSTRT:1; + } BIT; + } GTSSR; + union + { + unsigned long LONG; + struct + { + unsigned long PSGTRGAR:1; + unsigned long PSGTRGAF:1; + unsigned long PSGTRGBR:1; + unsigned long PSGTRGBF:1; + unsigned long PSGTRGCR:1; + unsigned long PSGTRGCF:1; + unsigned long PSGTRGDR:1; + unsigned long PSGTRGDF:1; + unsigned long PSCARBL:1; + unsigned long PSCARBH:1; + unsigned long PSCAFBL:1; + unsigned long PSCAFBH:1; + unsigned long PSCBRAL:1; + unsigned long PSCBRAH:1; + unsigned long PSCBFAL:1; + unsigned long PSCBFAH:1; + unsigned long PSEVTA:1; + unsigned long PSEVTB:1; + unsigned long PSEVTC:1; + unsigned long PSEVTD:1; + unsigned long PSEVTE:1; + unsigned long PSEVTF:1; + unsigned long PSEVTG:1; + unsigned long PSEVTH:1; + unsigned long :7; + unsigned long CSTOP:1; + } BIT; + } GTPSR; + union + { + unsigned long LONG; + struct + { + unsigned long CSGTRGAR:1; + unsigned long CSGTRGAF:1; + unsigned long CSGTRGBR:1; + unsigned long CSGTRGBF:1; + unsigned long CSGTRGCR:1; + unsigned long CSGTRGCF:1; + unsigned long CSGTRGDR:1; + unsigned long CSGTRGDF:1; + unsigned long CSCARBL:1; + unsigned long CSCARBH:1; + unsigned long CSCAFBL:1; + unsigned long CSCAFBH:1; + unsigned long CSCBRAL:1; + unsigned long CSCBRAH:1; + unsigned long CSCBFAL:1; + unsigned long CSCBFAH:1; + unsigned long CSEVTA:1; + unsigned long CSEVTB:1; + unsigned long CSEVTC:1; + unsigned long CSEVTD:1; + unsigned long CSEVTE:1; + unsigned long CSEVTF:1; + unsigned long CSEVTG:1; + unsigned long CSEVTH:1; + unsigned long :7; + unsigned long CCLR:1; + } BIT; + } GTCSR; + union + { + unsigned long LONG; + struct + { + unsigned long USGTRGAR:1; + unsigned long USGTRGAF:1; + unsigned long USGTRGBR:1; + unsigned long USGTRGBF:1; + unsigned long USGTRGCR:1; + unsigned long USGTRGCF:1; + unsigned long USGTRGDR:1; + unsigned long USGTRGDF:1; + unsigned long USCARBL:1; + unsigned long USCARBH:1; + unsigned long USCAFBL:1; + unsigned long USCAFBH:1; + unsigned long USCBRAL:1; + unsigned long USCBRAH:1; + unsigned long USCBFAL:1; + unsigned long USCBFAH:1; + unsigned long USEVTA:1; + unsigned long USEVTB:1; + unsigned long USEVTC:1; + unsigned long USEVTD:1; + unsigned long USEVTE:1; + unsigned long USEVTF:1; + unsigned long USEVTG:1; + unsigned long USEVTH:1; + unsigned long :8; + } BIT; + } GTUPSR; + union + { + unsigned long LONG; + struct + { + unsigned long DSGTRGAR:1; + unsigned long DSGTRGAF:1; + unsigned long DSGTRGBR:1; + unsigned long DSGTRGBF:1; + unsigned long DSGTRGCR:1; + unsigned long DSGTRGCF:1; + unsigned long DSGTRGDR:1; + unsigned long DSGTRGDF:1; + unsigned long DSCARBL:1; + unsigned long DSCARBH:1; + unsigned long DSCAFBL:1; + unsigned long DSCAFBH:1; + unsigned long DSCBRAL:1; + unsigned long DSCBRAH:1; + unsigned long DSCBFAL:1; + unsigned long DSCBFAH:1; + unsigned long DSEVTA:1; + unsigned long DSEVTB:1; + unsigned long DSEVTC:1; + unsigned long DSEVTD:1; + unsigned long DSEVTE:1; + unsigned long DSEVTF:1; + unsigned long DSEVTG:1; + unsigned long DSEVTH:1; + unsigned long :8; + } BIT; + } GTDNSR; + union + { + unsigned long LONG; + struct + { + unsigned long ASGTRGAR:1; + unsigned long ASGTRGAF:1; + unsigned long ASGTRGBR:1; + unsigned long ASGTRGBF:1; + unsigned long ASGTRGCR:1; + unsigned long ASGTRGCF:1; + unsigned long ASGTRGDR:1; + unsigned long ASGTRGDF:1; + unsigned long ASCARBL:1; + unsigned long ASCARBH:1; + unsigned long ASCAFBL:1; + unsigned long ASCAFBH:1; + unsigned long ASCBRAL:1; + unsigned long ASCBRAH:1; + unsigned long ASCBFAL:1; + unsigned long ASCBFAH:1; + unsigned long ASEVTA:1; + unsigned long ASEVTB:1; + unsigned long ASEVTC:1; + unsigned long ASEVTD:1; + unsigned long ASEVTE:1; + unsigned long ASEVTF:1; + unsigned long ASEVTG:1; + unsigned long ASEVTH:1; + unsigned long :8; + } BIT; + } GTICASR; + union + { + unsigned long LONG; + struct + { + unsigned long BSGTRGAR:1; + unsigned long BSGTRGAF:1; + unsigned long BSGTRGBR:1; + unsigned long BSGTRGBF:1; + unsigned long BSGTRGCR:1; + unsigned long BSGTRGCF:1; + unsigned long BSGTRGDR:1; + unsigned long BSGTRGDF:1; + unsigned long BSCARBL:1; + unsigned long BSCARBH:1; + unsigned long BSCAFBL:1; + unsigned long BSCAFBH:1; + unsigned long BSCBRAL:1; + unsigned long BSCBRAH:1; + unsigned long BSCBFAL:1; + unsigned long BSCBFAH:1; + unsigned long BSEVTA:1; + unsigned long BSEVTB:1; + unsigned long BSEVTC:1; + unsigned long BSEVTD:1; + unsigned long BSEVTE:1; + unsigned long BSEVTF:1; + unsigned long BSEVTG:1; + unsigned long BSEVTH:1; + unsigned long :8; + } BIT; + } GTICBSR; + union + { + unsigned long LONG; + struct + { + unsigned long CST:1; + unsigned long :7; + unsigned long :1; + unsigned long :5; + unsigned long :1; + unsigned long :1; + unsigned long MD:3; + unsigned long :5; + unsigned long TPCS:3; + unsigned long :5; + } BIT; + } GTCR; + union + { + unsigned long LONG; + struct + { + unsigned long UD:1; + unsigned long UDF:1; + unsigned long :14; + unsigned long OADTY:2; + unsigned long OADTYF:1; + unsigned long OADTYR:1; + unsigned long :4; + unsigned long OBDTY:2; + unsigned long OBDTYF:1; + unsigned long OBDTYR:1; + unsigned long :4; + } BIT; + } GTUDDTYC; + union + { + unsigned long LONG; + struct + { + unsigned long GTIOA:5; + unsigned long :1; + unsigned long OADFLT:1; + unsigned long OAHLD:1; + unsigned long OAE:1; + unsigned long OADF:2; + unsigned long :2; + unsigned long NFAEN:1; + unsigned long NFCSA:2; + unsigned long GTIOB:5; + unsigned long :1; + unsigned long OBDFLT:1; + unsigned long OBHLD:1; + unsigned long OBE:1; + unsigned long OBDF:2; + unsigned long :2; + unsigned long NFBEN:1; + unsigned long NFCSB:2; + } BIT; + } GTIOR; + union + { + unsigned long LONG; + struct + { + unsigned long GTINTA:1; + unsigned long GTINTB:1; + unsigned long GTINTC:1; + unsigned long GTINTD:1; + unsigned long GTINTE:1; + unsigned long GTINTF:1; + unsigned long GTINTPR:2; + unsigned long :8; + unsigned long ADTRAUEN:1; + unsigned long ADTRADEN:1; + unsigned long ADTRBUEN:1; + unsigned long ADTRBDEN:1; + unsigned long :4; + unsigned long GRP:2; + unsigned long :2; + unsigned long GRPDTE:1; + unsigned long GRPABH:1; + unsigned long GRPABL:1; + unsigned long :1; + } BIT; + } GTINTAD; + union + { + unsigned long LONG; + struct + { + unsigned long TCFA:1; + unsigned long TCFB:1; + unsigned long TCFC:1; + unsigned long TCFD:1; + unsigned long TCFE:1; + unsigned long TCFF:1; + unsigned long TCFPO:1; + unsigned long TCFPU:1; + unsigned long ITCNT:3; + unsigned long :4; + unsigned long TUCF:1; + unsigned long ADTRAUF:1; + unsigned long ADTRADF:1; + unsigned long ADTRBUF:1; + unsigned long ADTRBDF:1; + unsigned long :4; + unsigned long ODF:1; + unsigned long :3; + unsigned long DTEF:1; + unsigned long OABHF:1; + unsigned long OABLF:1; + unsigned long :1; + } BIT; + } GTST; + union + { + unsigned long LONG; + struct + { + unsigned long BD:4; + unsigned long :12; + unsigned long CCRA:2; + unsigned long CCRB:2; + unsigned long PR:2; + unsigned long CCRSWT:1; + unsigned long :1; + unsigned long ADTTA:2; + unsigned long ADTDA:1; + unsigned long :1; + unsigned long ADTTB:2; + unsigned long ADTDB:1; + unsigned long :1; + } BIT; + } GTBER; + union + { + unsigned long LONG; + struct + { + unsigned long ITLA:1; + unsigned long ITLB:1; + unsigned long ITLC:1; + unsigned long ITLD:1; + unsigned long ITLE:1; + unsigned long ITLF:1; + unsigned long IVTC:2; + unsigned long IVTT:3; + unsigned long :1; + unsigned long ADTAL:1; + unsigned long :1; + unsigned long ADTBL:1; + unsigned long :17; + } BIT; + } GTITC; + union + { + unsigned long LONG; + struct + { + unsigned long GTCNT:32; + } BIT; + } GTCNT; + union + { + unsigned long LONG; + struct + { + unsigned long GTCCRA:32; + } BIT; + } GTCCRA; + union + { + unsigned long LONG; + struct + { + unsigned long GTCCRB:32; + } BIT; + } GTCCRB; + union + { + unsigned long LONG; + struct + { + unsigned long GTCCRC:32; + } BIT; + } GTCCRC; + union + { + unsigned long LONG; + struct + { + unsigned long GTCCRE:32; + } BIT; + } GTCCRE; + union + { + unsigned long LONG; + struct + { + unsigned long GTCCRD:32; + } BIT; + } GTCCRD; + union + { + unsigned long LONG; + struct + { + unsigned long GTCCRF:32; + } BIT; + } GTCCRF; + union + { + unsigned long LONG; + struct + { + unsigned long GTPR:32; + } BIT; + } GTPR; + union + { + unsigned long LONG; + struct + { + unsigned long GTPBR:32; + } BIT; + } GTPBR; + union + { + unsigned long LONG; + struct + { + unsigned long GTPDBR:32; + } BIT; + } GTPDBR; + union + { + unsigned long LONG; + struct + { + unsigned long GTADTRA:32; + } BIT; + } GTADTRA; + union + { + unsigned long LONG; + struct + { + unsigned long GTADTBRA:32; + } BIT; + } GTADTBRA; + union + { + unsigned long LONG; + struct + { + unsigned long GTADTDBRA:32; + } BIT; + } GTADTDBRA; + union + { + unsigned long LONG; + struct + { + unsigned long GTADTRB:32; + } BIT; + } GTADTRB; + union + { + unsigned long LONG; + struct + { + unsigned long GTADTBRB:32; + } BIT; + } GTADTBRB; + union + { + unsigned long LONG; + struct + { + unsigned long GTADTDBRB:32; + } BIT; + } GTADTDBRB; + union + { + unsigned long LONG; + struct + { + unsigned long TDE:1; + unsigned long :3; + unsigned long TDBUE:1; + unsigned long TDBDE:1; + unsigned long :2; + unsigned long TDFER:1; + unsigned long :23; + } BIT; + } GTDTCR; + union + { + unsigned long LONG; + struct + { + unsigned long GTDVU:32; + } BIT; + } GTDVU; + union + { + unsigned long LONG; + struct + { + unsigned long GTDVD:32; + } BIT; + } GTDVD; + union + { + unsigned long LONG; + struct + { + unsigned long GTDBU:32; + } BIT; + } GTDBU; + union + { + unsigned long LONG; + struct + { + unsigned long GTDBD:32; + } BIT; + } GTDBD; + union + { + unsigned long LONG; + struct + { + unsigned long SOS:2; + unsigned long :6; + unsigned long :1; + unsigned long :1; + unsigned long :22; + } BIT; + } GTSOS; + union + { + unsigned long LONG; + struct + { + unsigned long SOTR:1; + unsigned long :31; + } BIT; + } GTSOTR; +}; + +#define GPT (*(volatile struct st_gpt *)0xE8043800) +#define GPT32E0 (*(volatile struct st_gpt32e *)0xE8043000) +#define GPT32E1 (*(volatile struct st_gpt32e *)0xE8043100) +#define GPT32E2 (*(volatile struct st_gpt32e *)0xE8043200) +#define GPT32E3 (*(volatile struct st_gpt32e *)0xE8043300) +#define GPT32E4 (*(volatile struct st_gpt32e *)0xE8043400) +#define GPT32E5 (*(volatile struct st_gpt32e *)0xE8043500) +#define GPT32E6 (*(volatile struct st_gpt32e *)0xE8043600) +#define GPT32E7 (*(volatile struct st_gpt32e *)0xE8043700) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/hyper_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/hyper_iodefine.h new file mode 100644 index 0000000..89d0f99 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/hyper_iodefine.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef HYPER_IODEFINE_H +#define HYPER_IODEFINE_H + +struct st_hyper +{ + union + { + unsigned long LONG; + struct + { + unsigned long RACT:1; + unsigned long :7; + unsigned long RDECERR:1; + unsigned long RTRSERR:1; + unsigned long RRSTOERR:1; + unsigned long RDSSTALL:1; + unsigned long :4; + unsigned long WACT:1; + unsigned long :7; + unsigned long WDECERR:1; + unsigned long WTRSERR:1; + unsigned long WRSTOERR:1; + unsigned long :5; + } BIT; + } CSR; + union + { + unsigned long LONG; + struct + { + unsigned long RPCINTE:1; + unsigned long :30; + unsigned long INTP:1; + } BIT; + } IEN; + union + { + unsigned long LONG; + struct + { + unsigned long RPCINTS:1; + unsigned long :31; + } BIT; + } ISR; + char wk0[4]; + char wk1[4]; + char wk2[4]; + char wk3[8]; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long :2; + unsigned long :1; + unsigned long :1; + unsigned long :10; + unsigned long :1; + unsigned long :1; + unsigned long MAXLEN:9; + unsigned long :4; + unsigned long MAXEN:1; + } BIT; + } MCR0; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long :2; + unsigned long DEVTYPE:1; + unsigned long CRT:1; + unsigned long :10; + unsigned long :1; + unsigned long :1; + unsigned long MAXLEN:9; + unsigned long :4; + unsigned long MAXEN:1; + } BIT; + } MCR1; + char wk4[8]; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long :4; + unsigned long WCSH:4; + unsigned long RCSH:4; + unsigned long WCSS:4; + unsigned long RCSS:4; + unsigned long WCSHI:4; + unsigned long RCSHI:4; + } BIT; + } MTR0; + union + { + unsigned long LONG; + struct + { + unsigned long LTCY:4; + unsigned long :4; + unsigned long WCSH:4; + unsigned long RCSH:4; + unsigned long WCSS:4; + unsigned long RCSS:4; + unsigned long WCSHI:4; + unsigned long RCSHI:4; + } BIT; + } MTR1; + char wk5[12]; + char wk6[4]; + char wk7[4]; + char wk8[4]; + char wk9[4]; +}; + +#define HYPER (*(volatile struct st_hyper *)0x1F400000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/imr_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/imr_iodefine.h new file mode 100644 index 0000000..e0a212c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/imr_iodefine.h @@ -0,0 +1,422 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef IMR_IODEFINE_H +#define IMR_IODEFINE_H + +struct st_imr +{ + union + { + unsigned long LONG; + struct + { + unsigned long RS:1; + unsigned long ARS:1; + unsigned long SFE:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :9; + unsigned long SWRST:1; + unsigned long :16; + } BIT; + } CR; + union + { + unsigned long LONG; + struct + { + unsigned long TRA:1; + unsigned long IER:1; + unsigned long INT:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long DSA:1; + unsigned long SFS:1; + unsigned long :24; + } BIT; + } SR; + union + { + unsigned long LONG; + struct + { + unsigned long TRACLR:1; + unsigned long IERCLR:1; + unsigned long INTCLR:1; + unsigned long :1; + unsigned long :1; + unsigned long :27; + } BIT; + } SRCR; + union + { + unsigned long LONG; + struct + { + unsigned long TRAENB:1; + unsigned long IERENB:1; + unsigned long INTENB:1; + unsigned long :1; + unsigned long :1; + unsigned long :27; + } BIT; + } ICR; + union + { + unsigned long LONG; + struct + { + unsigned long TEAM:1; + unsigned long IEM:1; + unsigned long INM:1; + unsigned long :1; + unsigned long :1; + unsigned long :27; + } BIT; + } IMR; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DLP:32; + } BIT; + } DLPR; + char wk1[12]; + union + { + unsigned long LONG; + struct + { + unsigned long :3; + unsigned long DLSA:29; + } BIT; + } DLSAR; + union + { + unsigned long LONG; + struct + { + unsigned long :5; + unsigned long DSA:27; + } BIT; + } DSAR; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DST:14; + unsigned long :18; + } BIT; + } DSTR; + char wk3[8]; + union + { + unsigned long LONG; + struct + { + unsigned long :5; + unsigned long DSA2:27; + } BIT; + } DSAR2; + union + { + unsigned long LONG; + struct + { + unsigned long :3; + unsigned long DLSA2:29; + } BIT; + } DLSAR2; + char wk4[4]; + char wk5[4]; + char wk6[4]; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TME:1; + unsigned long BFE:1; + unsigned long AUTODG:1; + unsigned long AUTOSG:1; + unsigned long DXDYM:1; + unsigned long DUDVM:1; + unsigned long TCM:1; + unsigned long :25; + } BIT; + } TRIMR; + union + { + unsigned long LONG; + struct + { + unsigned long TMES:1; + unsigned long BFES:1; + unsigned long AUTODGS:1; + unsigned long AUTOSGS:1; + unsigned long DXDYMS:1; + unsigned long DUDVMS:1; + unsigned long TCMS:1; + unsigned long :25; + } BIT; + } TRIMSR; + union + { + unsigned long LONG; + struct + { + unsigned long TMEC:1; + unsigned long BFEC:1; + unsigned long AUTODGC:1; + unsigned long AUTOSGC:1; + unsigned long DXDYMC:1; + unsigned long DUDVMC:1; + unsigned long TCMC:1; + unsigned long :25; + } BIT; + } TRIMCR; + union + { + unsigned long LONG; + struct + { + unsigned long TCY:8; + unsigned long TCU:8; + unsigned long TCV:8; + unsigned long :2; + unsigned long :5; + unsigned long YCFORM:1; + } BIT; + } TRICR; + union + { + unsigned long LONG; + struct + { + unsigned long UVDPO:3; + unsigned long :5; + unsigned long DDP:1; + unsigned long :23; + } BIT; + } UVDPOR; + union + { + unsigned long LONG; + struct + { + unsigned long SVW:11; + unsigned long :5; + unsigned long SUW:11; + unsigned long :5; + } BIT; + } SUSR; + union + { + unsigned long LONG; + struct + { + unsigned long SVS:11; + unsigned long :21; + } BIT; + } SVSR; + char wk8[4]; + union + { + unsigned long LONG; + struct + { + unsigned long XMIN:13; + unsigned long :19; + } BIT; + } XMINR; + union + { + unsigned long LONG; + struct + { + unsigned long YMIN:13; + unsigned long :19; + } BIT; + } YMINR; + union + { + unsigned long LONG; + struct + { + unsigned long XMAX:13; + unsigned long :19; + } BIT; + } XMAXR; + union + { + unsigned long LONG; + struct + { + unsigned long YMAX:13; + unsigned long :19; + } BIT; + } YMAXR; + union + { + unsigned long LONG; + struct + { + unsigned long AMXS:13; + unsigned long :19; + } BIT; + } AMXSR; + union + { + unsigned long LONG; + struct + { + unsigned long AMYS:13; + unsigned long :19; + } BIT; + } AMYSR; + union + { + unsigned long LONG; + struct + { + unsigned long AMXO:13; + unsigned long :19; + } BIT; + } AMXOR; + union + { + unsigned long LONG; + struct + { + unsigned long AMYO:13; + unsigned long :19; + } BIT; + } AMYOR; + char wk9[16]; + char wk10[4]; + char wk11[4]; + char wk12[4]; + char wk13[4]; + char wk14[4]; + char wk15[4]; + char wk16[8]; + char wk17[4]; + char wk18[4]; + char wk19[4]; + char wk20[4]; + char wk21[32]; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long :1; + unsigned long :2; + unsigned long EMAM:1; + unsigned long :17; + unsigned long :1; + unsigned long :1; + } BIT; + } MACR1; + char wk22[4]; + char wk23[2296]; + union + { + unsigned long LONG; + struct + { + unsigned long LSPR:10; + unsigned long :22; + } BIT; + } LSPR; + union + { + unsigned long LONG; + struct + { + unsigned long LEPR:10; + unsigned long :22; + } BIT; + } LEPR; + union + { + unsigned long LONG; + struct + { + unsigned long LMSR:3; + unsigned long :29; + } BIT; + } LMSR; + char wk24[20]; + char wk25[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPPC:11; + unsigned long :21; + } BIT; + } LMSPPCR; + union + { + unsigned long LONG; + struct + { + unsigned long EPPC:11; + unsigned long :21; + } BIT; + } LMEPPCR; +}; + +#define IMR2 (*(volatile struct st_imr *)0xFCFF3008) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/intc_iodefine.h new file mode 100644 index 0000000..35c1c39 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/intc_iodefine.h @@ -0,0 +1,4686 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef INTC_IODEFINE_H +#define INTC_IODEFINE_H + +struct st_intc +{ + union + { + unsigned long LONG; + struct + { + unsigned long EnableGrp0:1; + unsigned long EnableGrp1:1; + unsigned long :30; + } BIT; + } GICD_CTLR; + union + { + unsigned long LONG; + struct + { + unsigned long ITLinesNumber:5; + unsigned long CPUNumber:3; + unsigned long :2; + unsigned long SecurityExtn:1; + unsigned long LSPI:5; + unsigned long :16; + } BIT; + } GICD_TYPER; + union + { + unsigned long LONG; + struct + { + unsigned long Implementer:12; + unsigned long Revision:4; + unsigned long Variant:4; + unsigned long :4; + unsigned long ProductID:8; + } BIT; + } GICD_IIDR; + char wk0[116]; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR0; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR1; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR2; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR3; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR4; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR5; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR6; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR7; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR8; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR9; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR10; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR11; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR12; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR13; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR14; + union + { + unsigned long LONG; + struct + { + unsigned long Securitystatusbits:32; + } BIT; + } GICD_IGROUPR15; + char wk1[64]; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER0; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER1; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER2; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER3; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER4; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER5; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER6; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER7; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER8; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER9; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER10; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER11; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER12; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER13; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER14; + union + { + unsigned long LONG; + struct + { + unsigned long Set_enablebits:32; + } BIT; + } GICD_ISENABLER15; + char wk2[64]; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER0; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER1; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER2; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER3; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER4; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER5; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER6; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER7; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER8; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER9; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER10; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER11; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER12; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER13; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER14; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_enablebits:32; + } BIT; + } GICD_ICENABLER15; + char wk3[64]; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR0; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR1; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR2; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR3; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR4; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR5; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR6; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR7; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR8; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR9; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR10; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR11; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR12; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR13; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR14; + union + { + unsigned long LONG; + struct + { + unsigned long Set_pendingbits:32; + } BIT; + } GICD_ISPENDR15; + char wk4[64]; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR0; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR1; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR2; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR3; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR4; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR5; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR6; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR7; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR8; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR9; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR10; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR11; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR12; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR13; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR14; + union + { + unsigned long LONG; + struct + { + unsigned long Clear_pendingbits:32; + } BIT; + } GICD_ICPENDR15; + char wk5[64]; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER0; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER1; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER2; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER3; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER4; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER5; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER6; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER7; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER8; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER9; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER10; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER11; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER12; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER13; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER14; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ISACTIVER15; + char wk6[64]; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER0; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER1; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER2; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER3; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER4; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER5; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER6; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER7; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER8; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER9; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER10; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER11; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER12; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER13; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER14; + union + { + unsigned long LONG; + struct + { + unsigned long Activebits:32; + } BIT; + } GICD_ICACTIVER15; + char wk7[64]; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR0; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR1; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR2; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR3; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR4; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR5; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR6; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR7; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR8; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR9; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR10; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR11; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR12; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR13; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR14; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR15; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR16; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR17; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR18; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR19; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR20; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR21; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR22; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR23; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR24; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR25; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR26; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR27; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR28; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR29; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR30; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR31; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR32; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR33; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR34; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR35; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR36; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR37; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR38; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR39; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR40; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR41; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR42; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR43; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR44; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR45; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR46; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR47; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR48; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR49; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR50; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR51; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR52; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR53; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR54; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR55; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR56; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR57; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR58; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR59; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR60; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR61; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR62; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR63; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR64; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR65; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR66; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR67; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR68; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR69; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR70; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR71; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR72; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR73; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR74; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR75; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR76; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR77; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR78; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR79; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR80; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR81; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR82; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR83; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR84; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR85; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR86; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR87; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR88; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR89; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR90; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR91; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR92; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR93; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR94; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR95; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR96; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR97; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR98; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR99; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR100; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR101; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR102; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR103; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR104; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR105; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR106; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR107; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR108; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR109; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR110; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR111; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR112; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR113; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR114; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR115; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR116; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR117; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR118; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR119; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR120; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR121; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR122; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR123; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR124; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR125; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR126; + union + { + unsigned long LONG; + struct + { + unsigned long Prioritybyteoffset0:8; + unsigned long Prioritybyteoffset1:8; + unsigned long Prioritybyteoffset2:8; + unsigned long Prioritybyteoffset3:8; + } BIT; + } GICD_IPRIORITYR127; + char wk8[512]; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR0; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR1; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR2; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR3; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR4; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR5; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR6; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR7; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR8; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR9; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR10; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR11; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR12; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR13; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR14; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR15; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR16; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR17; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR18; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR19; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR20; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR21; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR22; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR23; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR24; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR25; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR26; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR27; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR28; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR29; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR30; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR31; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR32; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR33; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR34; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR35; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR36; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR37; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR38; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR39; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR40; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR41; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR42; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR43; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR44; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR45; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR46; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR47; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR48; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR49; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR50; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR51; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR52; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR53; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR54; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR55; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR56; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR57; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR58; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR59; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR60; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR61; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR62; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR63; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR64; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR65; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR66; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR67; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR68; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR69; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR70; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR71; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR72; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR73; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR74; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR75; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR76; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR77; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR78; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR79; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR80; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR81; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR82; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR83; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR84; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR85; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR86; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR87; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR88; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR89; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR90; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR91; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR92; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR93; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR94; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR95; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR96; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR97; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR98; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR99; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR100; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR101; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR102; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR103; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR104; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR105; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR106; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR107; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR108; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR109; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR110; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR111; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR112; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR113; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR114; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR115; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR116; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR117; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR118; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR119; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR120; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR121; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR122; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR123; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR124; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR125; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR126; + union + { + unsigned long LONG; + struct + { + unsigned long CPUtargetsbyteoffset0:8; + unsigned long CPUtargetsbyteoffset1:8; + unsigned long CPUtargetsbyteoffset2:8; + unsigned long CPUtargetsbyteoffset3:8; + } BIT; + } GICD_ITARGETR127; + char wk9[512]; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR0; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR1; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR2; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR3; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR4; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR5; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR6; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR7; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR8; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR9; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR10; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR11; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR12; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR13; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR14; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR15; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR16; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR17; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR18; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR19; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR20; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR21; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR22; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR23; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR24; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR25; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR26; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR27; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR28; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR29; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR30; + union + { + unsigned long LONG; + struct + { + unsigned long Int_config:32; + } BIT; + } GICD_ICFGR31; + char wk10[128]; + union + { + unsigned long LONG; + struct + { + unsigned long ppi_status:16; + unsigned long :16; + } BIT; + } GICD_PPISR; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR0; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR1; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR2; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR3; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR4; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR5; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR6; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR7; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR8; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR9; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR10; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR11; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR12; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR13; + union + { + unsigned long LONG; + struct + { + unsigned long spi_status:32; + } BIT; + } GICD_SPISR14; + char wk11[448]; + union + { + unsigned long LONG; + struct + { + unsigned long SGIINTID:4; + unsigned long :11; + unsigned long NSATT:1; + unsigned long CPUTargetList:8; + unsigned long TargetListFilter:2; + unsigned long :6; + } BIT; + } GICD_SGIR; + char wk12[12]; + union + { + unsigned long LONG; + struct + { + unsigned long SGI0_Clers_pending:8; + unsigned long SGI1_Clers_pending:8; + unsigned long SGI2_Clers_pending:8; + unsigned long SGI3_Clers_pending:8; + } BIT; + } GICD_CPENDSGIR0; + union + { + unsigned long LONG; + struct + { + unsigned long SGI4_Clers_pending:8; + unsigned long SGI5_Clers_pending:8; + unsigned long SGI6_Clers_pending:8; + unsigned long SGI7_Clers_pending:8; + } BIT; + } GICD_CPENDSGIR1; + union + { + unsigned long LONG; + struct + { + unsigned long SGI8_Clers_pending:8; + unsigned long SGI9_Clers_pending:8; + unsigned long SGI10_Clers_pending:8; + unsigned long SGI11_Clers_pending:8; + } BIT; + } GICD_CPENDSGIR2; + union + { + unsigned long LONG; + struct + { + unsigned long SGI12_Clers_pending:8; + unsigned long SGI13_Clers_pending:8; + unsigned long SGI14_Clers_pending:8; + unsigned long SGI15_Clers_pending:8; + } BIT; + } GICD_CPENDSGIR3; + union + { + unsigned long LONG; + struct + { + unsigned long SGI0_Set_pending:8; + unsigned long SGI1_Set_pending:8; + unsigned long SGI2_Set_pending:8; + unsigned long SGI3_Set_pending:8; + } BIT; + } GICD_SPENDSGIR0; + union + { + unsigned long LONG; + struct + { + unsigned long SGI4_Set_pending:8; + unsigned long SGI5_Set_pending:8; + unsigned long SGI6_Set_pending:8; + unsigned long SGI7_Set_pending:8; + } BIT; + } GICD_SPENDSGIR1; + union + { + unsigned long LONG; + struct + { + unsigned long SGI8_Set_pending:8; + unsigned long SGI9_Set_pending:8; + unsigned long SGI10_Set_pending:8; + unsigned long SGI11_Set_pending:8; + } BIT; + } GICD_SPENDSGIR2; + union + { + unsigned long LONG; + struct + { + unsigned long SGI12_Set_pending:8; + unsigned long SGI13_Set_pending:8; + unsigned long SGI14_Set_pending:8; + unsigned long SGI15_Set_pending:8; + } BIT; + } GICD_SPENDSGIR3; + char wk13[160]; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_CCfield:4; + unsigned long ARM_Reserved:4; + unsigned long :24; + } BIT; + } GICD_PIDR4; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_Reserved:8; + unsigned long :24; + } BIT; + } GICD_PIDR5; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_Reserved:8; + unsigned long :24; + } BIT; + } GICD_PIDR6; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_Reserved:8; + unsigned long :24; + } BIT; + } GICD_PIDR7; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_DIDfield:8; + unsigned long :24; + } BIT; + } GICD_PIDR0; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_DIDfield:4; + unsigned long ARM_AIDfield:4; + unsigned long :24; + } BIT; + } GICD_PIDR1; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_AIDfield:3; + unsigned long ARM_UJEPfield:1; + unsigned long Arfield:4; + unsigned long :24; + } BIT; + } GICD_PIDR2; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_Reserved:4; + unsigned long ARM_Rfield:4; + unsigned long :24; + } BIT; + } GICD_PIDR3; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_FVPCD:8; + unsigned long :24; + } BIT; + } GICD_CIDR0; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_FVPCD:8; + unsigned long :24; + } BIT; + } GICD_CIDR1; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_FVPCD:8; + unsigned long :24; + } BIT; + } GICD_CIDR2; + union + { + unsigned long LONG; + struct + { + unsigned long ARM_FVPCD:8; + unsigned long :24; + } BIT; + } GICD_CIDR3; + union + { + unsigned long LONG; + struct + { + unsigned long EnableGrp0:1; + unsigned long EnableGrp1:1; + unsigned long AckCtl:1; + unsigned long FIQEn:1; + unsigned long CBPR:1; + unsigned long FIQBypDisGrp0:1; + unsigned long IRQBypDisGrp0:1; + unsigned long FIQBypDisGrp1:1; + unsigned long IRQBypDisGrp1:1; + unsigned long EOImodeS:1; + unsigned long EOImodeNS:1; + unsigned long :21; + } BIT; + } GICC_CTLR; + union + { + unsigned long LONG; + struct + { + unsigned long Priority:8; + unsigned long :24; + } BIT; + } GICC_PMR; + union + { + unsigned long LONG; + struct + { + unsigned long Binarypoint:3; + unsigned long :29; + } BIT; + } GICC_BPR; + union + { + unsigned long LONG; + struct + { + unsigned long InterruptID:10; + unsigned long CPUID:3; + unsigned long :19; + } BIT; + } GICC_IAR; + union + { + unsigned long LONG; + struct + { + unsigned long EOIINTID:10; + unsigned long CPUID:3; + unsigned long :19; + } BIT; + } GICC_EOIR; + union + { + unsigned long LONG; + struct + { + unsigned long Priority:8; + unsigned long :24; + } BIT; + } GICC_RPR; + union + { + unsigned long LONG; + struct + { + unsigned long PENDINTID:10; + unsigned long CPUID:3; + unsigned long :19; + } BIT; + } GICC_HPPIR; + union + { + unsigned long LONG; + struct + { + unsigned long Binarypoint:3; + unsigned long :29; + } BIT; + } GICC_ABPR; + union + { + unsigned long LONG; + struct + { + unsigned long InterruptID:10; + unsigned long CPUID:3; + unsigned long :19; + } BIT; + } GICC_AIAR; + union + { + unsigned long LONG; + struct + { + unsigned long InterruptID:10; + unsigned long CPUID:3; + unsigned long :19; + } BIT; + } GICC_AEOIR; + union + { + unsigned long LONG; + struct + { + unsigned long PENDINTID:10; + unsigned long CPUID:3; + unsigned long :19; + } BIT; + } GICC_AHPPIR; + char wk14[164]; + union + { + unsigned long LONG; + struct + { + unsigned long AP_Group0:32; + } BIT; + } GICC_APR0; + char wk15[12]; + union + { + unsigned long LONG; + struct + { + unsigned long AP_Group1:16; + unsigned long AP_Group0:16; + } BIT; + } GICC_NSAPR0; + char wk16[24]; + union + { + unsigned long LONG; + struct + { + unsigned long Implementer:12; + unsigned long Revision:4; + unsigned long Architectureversion:4; + unsigned long ProductID:12; + } BIT; + } GICC_IIDR; + char wk17[3840]; + union + { + unsigned long LONG; + struct + { + unsigned long InterruptID:10; + unsigned long CPUID:3; + unsigned long :19; + } BIT; + } GICC_DIR; + char wk18[350013436]; + union + { + unsigned short WORD; + struct + { + unsigned short :1; + unsigned short NMIF:1; + unsigned short :6; + unsigned short NMIE:1; + unsigned short :6; + unsigned short NMIL:1; + } BIT; + } ICR0; + union + { + unsigned short WORD; + struct + { + unsigned short IRQ00S:1; + unsigned short IRQ01S:1; + unsigned short IRQ10S:1; + unsigned short IRQ11S:1; + unsigned short IRQ20S:1; + unsigned short IRQ21S:1; + unsigned short IRQ30S:1; + unsigned short IRQ31S:1; + unsigned short IRQ40S:1; + unsigned short IRQ41S:1; + unsigned short IRQ50S:1; + unsigned short IRQ51S:1; + unsigned short IRQ60S:1; + unsigned short IRQ61S:1; + unsigned short IRQ70S:1; + unsigned short IRQ71S:1; + } BIT; + } ICR1; + union + { + unsigned short WORD; + struct + { + unsigned short IRQ0F:1; + unsigned short IRQ1F:1; + unsigned short IRQ2F:1; + unsigned short IRQ3F:1; + unsigned short IRQ4F:1; + unsigned short IRQ5F:1; + unsigned short IRQ6F:1; + unsigned short IRQ7F:1; + unsigned short :7; + unsigned short IRQMSK:1; + } BIT; + } IRQRR; + char wk19[2]; + char wk20[2]; + char wk21[6]; + union + { + unsigned short WORD; + struct + { + unsigned short DP:1; + unsigned short DM:1; + unsigned short :6; + unsigned short VBUSIN:1; + unsigned short OVRCLR:1; + unsigned short CC1_RD:1; + unsigned short CC2_RD:1; + unsigned short :4; + } BIT; + } SSTBCCR0; + union + { + unsigned short WORD; + struct + { + unsigned short DP:1; + unsigned short DM:1; + unsigned short :6; + unsigned short VBUSIN:1; + unsigned short OVRCLR:1; + unsigned short CC1_RD:1; + unsigned short CC2_RD:1; + unsigned short :4; + } BIT; + } SSTBCCR1; + union + { + unsigned short WORD; + struct + { + unsigned short DP:1; + unsigned short DM:1; + unsigned short :6; + unsigned short VBUSIN:1; + unsigned short OVRCLR:1; + unsigned short CC1_RD:1; + unsigned short CC2_RD:1; + unsigned short :4; + } BIT; + } SSTBCRR0; + union + { + unsigned short WORD; + struct + { + unsigned short DP:1; + unsigned short DM:1; + unsigned short :6; + unsigned short VBUSIN:1; + unsigned short OVRCLR:1; + unsigned short CC1_RD:1; + unsigned short CC2_RD:1; + unsigned short :4; + } BIT; + } SSTBCRR1; +}; + +#define INTC (*(volatile struct st_intc *)0xE8221000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/irda_iodefine.h new file mode 100644 index 0000000..f814e54 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/irda_iodefine.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef IRDA_IODEFINE_H +#define IRDA_IODEFINE_H + +struct st_irda +{ + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char IRRXINV:1; + unsigned char IRTXINV:1; + unsigned char IRCKS:3; + unsigned char IRE:1; + } BIT; + } IRCR; +}; + +#define IrDA (*(volatile struct st_irda *)0xE8014000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/jcu_iodefine.h new file mode 100644 index 0000000..6ca4dc1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/jcu_iodefine.h @@ -0,0 +1,430 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef JCU_IODEFINE_H +#define JCU_IODEFINE_H + +struct st_jcu +{ + union + { + unsigned char BYTE; + struct + { + unsigned char REDU:3; + unsigned char DSP:1; + unsigned char :4; + } BIT; + } JCMOD; + union + { + unsigned char BYTE; + struct + { + unsigned char JSRT:1; + unsigned char JRST:1; + unsigned char JEND:1; + unsigned char :4; + unsigned char BRST:1; + } BIT; + } JCCMD; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char QT1:2; + unsigned char QT2:2; + unsigned char QT3:2; + unsigned char :2; + } BIT; + } JCQTN; + union + { + unsigned char BYTE; + struct + { + unsigned char HTD1:1; + unsigned char HTA1:1; + unsigned char HTD2:1; + unsigned char HTA2:1; + unsigned char HTD3:1; + unsigned char HTA3:1; + unsigned char :2; + } BIT; + } JCHTN; + union + { + unsigned char BYTE; + struct + { + unsigned char DRIU:8; + } BIT; + } JCDRIU; + union + { + unsigned char BYTE; + struct + { + unsigned char DRID:8; + } BIT; + } JCDRID; + union + { + unsigned char BYTE; + struct + { + unsigned char VSZU:8; + } BIT; + } JCVSZU; + union + { + unsigned char BYTE; + struct + { + unsigned char VSZD:8; + } BIT; + } JCVSZD; + union + { + unsigned char BYTE; + struct + { + unsigned char HSZU:8; + } BIT; + } JCHSZU; + union + { + unsigned char BYTE; + struct + { + unsigned char HSZD:8; + } BIT; + } JCHSZD; + union + { + unsigned char BYTE; + struct + { + unsigned char DCU:8; + } BIT; + } JCDTCU; + union + { + unsigned char BYTE; + struct + { + unsigned char DCM:8; + } BIT; + } JCDTCM; + union + { + unsigned char BYTE; + struct + { + unsigned char DCD:8; + } BIT; + } JCDTCD; + union + { + unsigned char BYTE; + struct + { + unsigned char :3; + unsigned char INT3:1; + unsigned char :1; + unsigned char INT5:1; + unsigned char INT6:1; + unsigned char INT7:1; + } BIT; + } JINTE0; + union + { + unsigned char BYTE; + struct + { + unsigned char :3; + unsigned char INS3:1; + unsigned char :1; + unsigned char INS5:1; + unsigned char INS6:1; + unsigned char :1; + } BIT; + } JINTS0; + union + { + unsigned char BYTE; + struct + { + unsigned char ERR:4; + unsigned char :4; + } BIT; + } JCDERR; + union + { + unsigned char BYTE; + struct + { + unsigned char RST:1; + unsigned char :7; + } BIT; + } JCRST; + char wk1[1]; + char wk2[1]; + char wk3[44]; + union + { + unsigned long LONG; + struct + { + unsigned long DINSWAP:3; + unsigned long :1; + unsigned long DINLC:1; + unsigned long DINRCMD:1; + unsigned long DINRINI:1; + unsigned long :1; + unsigned long JOUTSWAP:3; + unsigned long :1; + unsigned long JOUTC:1; + unsigned long JOUTRCMD:1; + unsigned long JOUTRINI:1; + unsigned long :17; + } BIT; + } JIFECNT; + union + { + unsigned long LONG; + struct + { + unsigned long ESA:32; + } BIT; + } JIFESA; + union + { + unsigned long LONG; + struct + { + unsigned long ESMW:15; + unsigned long :17; + } BIT; + } JIFESOFST; + union + { + unsigned long LONG; + struct + { + unsigned long EDA:32; + } BIT; + } JIFEDA; + union + { + unsigned long LONG; + struct + { + unsigned long LINES:16; + unsigned long :16; + } BIT; + } JIFESLC; + union + { + unsigned long LONG; + struct + { + unsigned long JDATAS:16; + unsigned long :16; + } BIT; + } JIFEDDC; + union + { + unsigned long LONG; + struct + { + unsigned long DOUTSWAP:3; + unsigned long :1; + unsigned long DOUTLC:1; + unsigned long DOUTRCMD:1; + unsigned long DOUTRINI:1; + unsigned long :1; + unsigned long JINSWAP:3; + unsigned long :1; + unsigned long JINC:1; + unsigned long JINRCMD:1; + unsigned long JINRINI:1; + unsigned long :9; + unsigned long OPF:2; + unsigned long HINTER:2; + unsigned long VINTER:2; + unsigned long :2; + } BIT; + } JIFDCNT; + union + { + unsigned long LONG; + struct + { + unsigned long DSA:32; + } BIT; + } JIFDSA; + union + { + unsigned long LONG; + struct + { + unsigned long DDMW:15; + unsigned long :17; + } BIT; + } JIFDDOFST; + union + { + unsigned long LONG; + struct + { + unsigned long DDA:32; + } BIT; + } JIFDDA; + union + { + unsigned long LONG; + struct + { + unsigned long JDATAS:16; + unsigned long :16; + } BIT; + } JIFDSDC; + union + { + unsigned long LONG; + struct + { + unsigned long LINES:16; + unsigned long :16; + } BIT; + } JIFDDLC; + union + { + unsigned long LONG; + struct + { + unsigned long ALPHA:8; + unsigned long :24; + } BIT; + } JIFDADT; + char wk4[4]; + char wk5[4]; + char wk6[4]; + char wk7[4]; + char wk8[4]; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DOUTLEN:1; + unsigned long JINEN:1; + unsigned long DBTEN:1; + unsigned long :1; + unsigned long JOUTEN:1; + unsigned long DINLEN:1; + unsigned long CBTEN:1; + unsigned long :25; + } BIT; + } JINTE1; + union + { + unsigned long LONG; + struct + { + unsigned long DOUTLF:1; + unsigned long JINF:1; + unsigned long DBTF:1; + unsigned long :1; + unsigned long JOUTF:1; + unsigned long DINLF:1; + unsigned long CBTF:1; + unsigned long :25; + } BIT; + } JINTS1; + union + { + unsigned long LONG; + struct + { + unsigned long :15; + unsigned long DINYCHG:1; + unsigned long :15; + unsigned long :1; + } BIT; + } JIFESVSZ; + union + { + unsigned long LONG; + struct + { + unsigned long :15; + unsigned long DOUTYCHG:1; + unsigned long :15; + unsigned long :1; + } BIT; + } JIFESHSZ; + char wk10[100]; + unsigned char JCQTBL0; + char wk11[63]; + unsigned char JCQTBL1; + char wk12[63]; + unsigned char JCQTBL2; + char wk13[63]; + unsigned char JCQTBL3; + char wk14[63]; + unsigned char JCHTBD0; + char wk15[31]; + unsigned char JCHTBA0; + char wk16[223]; + unsigned char JCHTBD1; + char wk17[31]; + unsigned char JCHTBA1; +}; + +#define JCU (*(volatile struct st_jcu *)0xE8017000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/lvds_iodefine.h new file mode 100644 index 0000000..0d6bf8e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/lvds_iodefine.h @@ -0,0 +1,125 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef LVDS_IODEFINE_H +#define LVDS_IODEFINE_H + +struct st_lvds +{ + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long LVDS_UPDATE:1; + unsigned long :15; + } BIT; + } LVDS_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long LVDS_SEL0:4; + unsigned long LVDS_SEL1:4; + unsigned long LVDS_SEL2:4; + unsigned long :4; + unsigned long :4; + unsigned long :2; + unsigned long SYNC_POL:2; + unsigned long :2; + unsigned long :2; + unsigned long SYNC_MODE:1; + unsigned long :3; + } BIT; + } LVDSFCL; + char wk0[4]; + char wk1[4]; + char wk2[4]; + char wk3[4]; + char wk4[4]; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long :1; + unsigned long :2; + unsigned long LVDS_CLK_EN:1; + unsigned long :3; + unsigned long LVDS_ODIV_SET:2; + unsigned long LVDSPLL_TST:6; + unsigned long :2; + unsigned long :6; + unsigned long LVDS_IN_CLK_SEL:2; + unsigned long :1; + unsigned long :5; + } BIT; + } LCLKSELR; + union + { + unsigned long LONG; + struct + { + unsigned long LVDSPLL_PD:1; + unsigned long :3; + unsigned long LVDSPLL_OD:2; + unsigned long :2; + unsigned long LVDSPLL_RD:3; + unsigned long :2; + unsigned long :3; + unsigned long LVDSPLL_FD:7; + unsigned long :4; + unsigned long :4; + unsigned long :1; + } BIT; + } LPLLSETR; + char wk6[4]; + char wk7[4]; +}; + +#define LVDS (*(volatile struct st_lvds *)0xFCFF7A30) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/mtu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/mtu_iodefine.h new file mode 100644 index 0000000..c9a41bb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/mtu_iodefine.h @@ -0,0 +1,2093 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef MTU_IODEFINE_H +#define MTU_IODEFINE_H + +struct st_mtu +{ + union + { + unsigned char BYTE; + struct + { + unsigned char OE3B:1; + unsigned char OE4A:1; + unsigned char OE4B:1; + unsigned char OE3D:1; + unsigned char OE4C:1; + unsigned char OE4D:1; + unsigned char :2; + } BIT; + } TOERA; + char wk0[1]; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char UF:1; + unsigned char VF:1; + unsigned char WF:1; + unsigned char FB:1; + unsigned char P:1; + unsigned char N:1; + unsigned char BDC:1; + unsigned char :1; + } BIT; + } TGCRA; + union + { + unsigned char BYTE; + struct + { + unsigned char OLSP:1; + unsigned char OLSN:1; + unsigned char TOCS:1; + unsigned char TOCL:1; + unsigned char :2; + unsigned char PSYE:1; + unsigned char :1; + } BIT; + } TOCR1A; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char BF:2; + } BIT; + } TOCR2A; + char wk2[4]; + union + { + unsigned short WORD; + struct + { + unsigned short TCDRA:16; + } BIT; + } TCDRA; + union + { + unsigned short WORD; + struct + { + unsigned short TDDRA:16; + } BIT; + } TDDRA; + char wk3[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNTSA:16; + } BIT; + } TCNTSA; + union + { + unsigned short WORD; + struct + { + unsigned short TCBRA:16; + } BIT; + } TCBRA; + char wk4[12]; + union + { + unsigned char BYTE; + struct + { + unsigned char T4VCOR:3; + unsigned char T4VEN:1; + unsigned char T3ACOR:3; + unsigned char T3AEN:1; + } BIT; + } TITCR1A; + union + { + unsigned char BYTE; + struct + { + unsigned char T4VCNT:3; + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + } BIT; + } TITCNT1A; + union + { + unsigned char BYTE; + struct + { + unsigned char BTE:2; + unsigned char :6; + } BIT; + } TBTERA; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TDER:1; + unsigned char :7; + } BIT; + } TDERA; + char wk6[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char :2; + } BIT; + } TOLBRA; + char wk7[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char TITM:1; + unsigned char :7; + } BIT; + } TITMRA; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG4COR:3; + unsigned char :5; + } BIT; + } TITCR2A; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG4CNT:3; + unsigned char :5; + } BIT; + } TITCNT2A; + char wk8[35]; + union + { + unsigned char BYTE; + struct + { + unsigned char WRE:1; + unsigned char SCC:1; + unsigned char :5; + unsigned char CCE:1; + } BIT; + } TWCRA; + char wk9[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char DRS:1; + unsigned char :7; + } BIT; + } TMDR2A; + char wk10[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char CST0:1; + unsigned char CST1:1; + unsigned char CST2:1; + unsigned char CST8:1; + unsigned char :2; + unsigned char CST3:1; + unsigned char CST4:1; + } BIT; + } TSTRA; + union + { + unsigned char BYTE; + struct + { + unsigned char SYNC0:1; + unsigned char SYNC1:1; + unsigned char SYNC2:1; + unsigned char :3; + unsigned char SYNC3:1; + unsigned char SYNC4:1; + } BIT; + } TSYRA; + union + { + unsigned char BYTE; + struct + { + unsigned char SCH7:1; + unsigned char SCH6:1; + unsigned char :1; + unsigned char SCH4:1; + unsigned char SCH3:1; + unsigned char SCH2:1; + unsigned char SCH1:1; + unsigned char SCH0:1; + } BIT; + } TCSYSTR; + char wk11[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char RWE:1; + unsigned char :7; + } BIT; + } TRWERA; + char wk12[1925]; + union + { + unsigned char BYTE; + struct + { + unsigned char OE6B:1; + unsigned char OE7A:1; + unsigned char OE7B:1; + unsigned char OE6D:1; + unsigned char OE7C:1; + unsigned char OE7D:1; + unsigned char :2; + } BIT; + } TOERB; + char wk13[1]; + char wk14[1]; + char wk15[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char OLSP:1; + unsigned char OLSN:1; + unsigned char TOCS:1; + unsigned char TOCL:1; + unsigned char :2; + unsigned char PSYE:1; + unsigned char :1; + } BIT; + } TOCR1B; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char BF:2; + } BIT; + } TOCR2B; + char wk16[4]; + union + { + unsigned short WORD; + struct + { + unsigned short TCDRB:16; + } BIT; + } TCDRB; + union + { + unsigned short WORD; + struct + { + unsigned short TDDRB:16; + } BIT; + } TDDRB; + char wk17[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNTSB:16; + } BIT; + } TCNTSB; + union + { + unsigned short WORD; + struct + { + unsigned short TCBRB:16; + } BIT; + } TCBRB; + char wk18[12]; + union + { + unsigned char BYTE; + struct + { + unsigned char T7VCOR:3; + unsigned char T7VEN:1; + unsigned char T6ACOR:3; + unsigned char T6AEN:1; + } BIT; + } TITCR1B; + union + { + unsigned char BYTE; + struct + { + unsigned char T7VCNT:3; + unsigned char :1; + unsigned char T6ACNT:3; + unsigned char :1; + } BIT; + } TITCNT1B; + union + { + unsigned char BYTE; + struct + { + unsigned char BTE:2; + unsigned char :6; + } BIT; + } TBTERB; + char wk19[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TDER:1; + unsigned char :7; + } BIT; + } TDERB; + char wk20[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char :2; + } BIT; + } TOLBRB; + char wk21[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char TITM:1; + unsigned char :7; + } BIT; + } TITMRB; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG7COR:3; + unsigned char :5; + } BIT; + } TITCR2B; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG7CNT:3; + unsigned char :5; + } BIT; + } TITCNT2B; + char wk22[35]; + union + { + unsigned char BYTE; + struct + { + unsigned char WRE:1; + unsigned char SCC:1; + unsigned char :5; + unsigned char CCE:1; + } BIT; + } TWCRB; + char wk23[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char DRS:1; + unsigned char :7; + } BIT; + } TMDR2B; + char wk24[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char CST6:1; + unsigned char CST7:1; + } BIT; + } TSTRB; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char SYNC6:1; + unsigned char SYNC7:1; + } BIT; + } TSYRB; + char wk25[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char RWE:1; + unsigned char :7; + } BIT; + } TRWERB; +}; + +struct st_mtu0 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR0; + char wk0[8]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCSC:2; + unsigned char :2; + } BIT; + } NFCRC; + char wk1[102]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char BFE:1; + unsigned char :1; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk2[1]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNT:16; + } BIT; + } TCNT; + union + { + unsigned short WORD; + struct + { + unsigned short TGRA:16; + } BIT; + } TGRA; + union + { + unsigned short WORD; + struct + { + unsigned short TGRB:16; + } BIT; + } TGRB; + union + { + unsigned short WORD; + struct + { + unsigned short TGRC:16; + } BIT; + } TGRC; + union + { + unsigned short WORD; + struct + { + unsigned short TGRD:16; + } BIT; + } TGRD; + char wk3[16]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRE:16; + } BIT; + } TGRE; + union + { + unsigned short WORD; + struct + { + unsigned short TGRF:16; + } BIT; + } TGRF; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEE:1; + unsigned char TGIEF:1; + unsigned char :5; + unsigned char TTGE2:1; + } BIT; + } TIER2; + char wk4[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char TTSE:1; + unsigned char :5; + } BIT; + } TBTM; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; +}; + +struct st_mtu1 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR1; + char wk1[238]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk2[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char :1; + unsigned char :2; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + union + { + unsigned short WORD; + struct + { + unsigned short TCNT:16; + } BIT; + } TCNT; + union + { + unsigned short WORD; + struct + { + unsigned short TGRA:16; + } BIT; + } TGRA; + union + { + unsigned short WORD; + struct + { + unsigned short TGRB:16; + } BIT; + } TGRB; + char wk3[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char I1AE:1; + unsigned char I1BE:1; + unsigned char I2AE:1; + unsigned char I2BE:1; + unsigned char :4; + } BIT; + } TICCR; + union + { + unsigned char BYTE; + struct + { + unsigned char LWA:1; + unsigned char PHCKSEL:1; + unsigned char :6; + } BIT; + } TMDR3; + char wk4[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char PCB:2; + unsigned char :3; + } BIT; + } TCR2; + char wk5[11]; + union + { + unsigned long LONG; + struct + { + unsigned long TCNTLW:32; + } BIT; + } TCNTLW; + union + { + unsigned long LONG; + struct + { + unsigned long TGRALW:32; + } BIT; + } TGRALW; + union + { + unsigned long LONG; + struct + { + unsigned long TGRBLW:32; + } BIT; + } TGRBLW; +}; + +struct st_mtu2 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR2; + char wk0[365]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char :1; + unsigned char :2; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + union + { + unsigned short WORD; + struct + { + unsigned short TCNT:16; + } BIT; + } TCNT; + union + { + unsigned short WORD; + struct + { + unsigned short TGRA:16; + } BIT; + } TGRA; + union + { + unsigned short WORD; + struct + { + unsigned short TGRB:16; + } BIT; + } TGRB; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char PCB:2; + unsigned char :3; + } BIT; + } TCR2; +}; + +struct st_mtu3 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk3[7]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNT:16; + } BIT; + } TCNT; + char wk4[6]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRA:16; + } BIT; + } TGRA; + union + { + unsigned short WORD; + struct + { + unsigned short TGRB:16; + } BIT; + } TGRB; + char wk5[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRC:16; + } BIT; + } TGRC; + union + { + unsigned short WORD; + struct + { + unsigned short TGRD:16; + } BIT; + } TGRD; + char wk6[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk8[19]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk9[37]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRE:16; + } BIT; + } TGRE; + char wk10[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR3; +}; + +struct st_mtu4 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk3[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :1; + unsigned char TTGE2:1; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk4[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNT:16; + } BIT; + } TCNT; + char wk5[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRA:16; + } BIT; + } TGRA; + union + { + unsigned short WORD; + struct + { + unsigned short TGRB:16; + } BIT; + } TGRB; + char wk6[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRC:16; + } BIT; + } TGRC; + union + { + unsigned short WORD; + struct + { + unsigned short TGRD:16; + } BIT; + } TGRD; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk9[6]; + union + { + unsigned short WORD; + struct + { + unsigned short ITB4VE:1; + unsigned short ITB3AE:1; + unsigned short ITA4VE:1; + unsigned short ITA3AE:1; + unsigned short DT4BE:1; + unsigned short UT4BE:1; + unsigned short DT4AE:1; + unsigned short UT4AE:1; + unsigned short :6; + unsigned short BF:2; + } BIT; + } TADCR; + char wk10[2]; + union + { + unsigned short WORD; + struct + { + unsigned short TADCORA:16; + } BIT; + } TADCORA; + union + { + unsigned short WORD; + struct + { + unsigned short TADCORB:16; + } BIT; + } TADCORB; + union + { + unsigned short WORD; + struct + { + unsigned short TADCOBRA:16; + } BIT; + } TADCOBRA; + union + { + unsigned short WORD; + struct + { + unsigned short TADCOBRB:16; + } BIT; + } TADCOBRB; + char wk11[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk12[38]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRE:16; + } BIT; + } TGRE; + union + { + unsigned short WORD; + struct + { + unsigned short TGRF:16; + } BIT; + } TGRF; + char wk13[28]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR4; +}; + +struct st_mtu5 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFUEN:1; + unsigned char NFVEN:1; + unsigned char NFWEN:1; + unsigned char :1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR5; + char wk1[490]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNTU:16; + } BIT; + } TCNTU; + union + { + unsigned short WORD; + struct + { + unsigned short TGRU:16; + } BIT; + } TGRU; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRU; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char CKEG:2; + unsigned char :3; + } BIT; + } TCR2U; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORU; + char wk2[9]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNTV:16; + } BIT; + } TCNTV; + union + { + unsigned short WORD; + struct + { + unsigned short TGRV:16; + } BIT; + } TGRV; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRV; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char CKEG:2; + unsigned char :3; + } BIT; + } TCR2V; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORV; + char wk3[9]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNTW:16; + } BIT; + } TCNTW; + union + { + unsigned short WORD; + struct + { + unsigned short TGRW:16; + } BIT; + } TGRW; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRW; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char CKEG:2; + unsigned char :3; + } BIT; + } TCR2W; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORW; + char wk4[9]; + char wk5[1]; + char wk6[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIE5W:1; + unsigned char TGIE5V:1; + unsigned char TGIE5U:1; + unsigned char :5; + } BIT; + } TIER; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char CSTW5:1; + unsigned char CSTV5:1; + unsigned char CSTU5:1; + unsigned char :5; + } BIT; + } TSTR; + char wk8[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char CMPCLR5W:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5U:1; + unsigned char :5; + } BIT; + } TCNTCMPCLR; +}; + +struct st_mtu6 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk3[7]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNT:16; + } BIT; + } TCNT; + char wk4[6]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRA:16; + } BIT; + } TGRA; + union + { + unsigned short WORD; + struct + { + unsigned short TGRB:16; + } BIT; + } TGRB; + char wk5[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRC:16; + } BIT; + } TGRC; + union + { + unsigned short WORD; + struct + { + unsigned short TGRD:16; + } BIT; + } TGRD; + char wk6[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk8[19]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk9[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char CE2B:1; + unsigned char CE2A:1; + unsigned char CE1B:1; + unsigned char CE1A:1; + unsigned char CE0D:1; + unsigned char CE0C:1; + unsigned char CE0B:1; + unsigned char CE0A:1; + } BIT; + } TSYCR; + char wk10[33]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRE:16; + } BIT; + } TGRE; + char wk11[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR6; +}; + +struct st_mtu7 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk3[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :1; + unsigned char TTGE2:1; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk4[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TCNT:16; + } BIT; + } TCNT; + char wk5[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRA:16; + } BIT; + } TGRA; + union + { + unsigned short WORD; + struct + { + unsigned short TGRB:16; + } BIT; + } TGRB; + char wk6[8]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRC:16; + } BIT; + } TGRC; + union + { + unsigned short WORD; + struct + { + unsigned short TGRD:16; + } BIT; + } TGRD; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk9[6]; + union + { + unsigned short WORD; + struct + { + unsigned short ITB7VE:1; + unsigned short ITB6AE:1; + unsigned short ITA7VE:1; + unsigned short ITA6AE:1; + unsigned short DT7BE:1; + unsigned short UT7BE:1; + unsigned short DT7AE:1; + unsigned short UT7AE:1; + unsigned short :6; + unsigned short BF:2; + } BIT; + } TADCR; + char wk10[2]; + union + { + unsigned short WORD; + struct + { + unsigned short TADCORA:16; + } BIT; + } TADCORA; + union + { + unsigned short WORD; + struct + { + unsigned short TADCORB:16; + } BIT; + } TADCORB; + union + { + unsigned short WORD; + struct + { + unsigned short TADCOBRA:16; + } BIT; + } TADCOBRA; + union + { + unsigned short WORD; + struct + { + unsigned short TADCOBRB:16; + } BIT; + } TADCOBRB; + char wk11[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk12[38]; + union + { + unsigned short WORD; + struct + { + unsigned short TGRE:16; + } BIT; + } TGRE; + union + { + unsigned short WORD; + struct + { + unsigned short TGRF:16; + } BIT; + } TGRF; + char wk13[28]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR7; +}; + +struct st_mtu8 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR8; + char wk0[871]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :3; + } BIT; + } TIER; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk2[1]; + union + { + unsigned long LONG; + struct + { + unsigned long TCNT:32; + } BIT; + } TCNT; + union + { + unsigned long LONG; + struct + { + unsigned long TGRA:32; + } BIT; + } TGRA; + union + { + unsigned long LONG; + struct + { + unsigned long TGRB:32; + } BIT; + } TGRB; + union + { + unsigned long LONG; + struct + { + unsigned long TGRC:32; + } BIT; + } TGRC; + union + { + unsigned long LONG; + struct + { + unsigned long TGRD:32; + } BIT; + } TGRD; +}; + +struct st_mtut +{ + char wk0[1]; + char wk1[15]; + char wk2[1]; + char wk3[1]; + char wk4[1]; + char wk5[13]; + char wk6[1]; + char wk7[1]; + char wk8[1]; + char wk9[13]; + char wk10[1]; + char wk11[1]; + char wk12[1]; +}; + +#define MTU (*(volatile struct st_mtu *)0xE804120A) +#define MTU0 (*(volatile struct st_mtu0 *)0xE8041290) +#define MTU1 (*(volatile struct st_mtu1 *)0xE8041290) +#define MTU2 (*(volatile struct st_mtu2 *)0xE8041292) +#define MTU3 (*(volatile struct st_mtu3 *)0xE8041200) +#define MTU4 (*(volatile struct st_mtu4 *)0xE8041200) +#define MTU5 (*(volatile struct st_mtu5 *)0xE8041A94) +#define MTU6 (*(volatile struct st_mtu6 *)0xE8041A00) +#define MTU7 (*(volatile struct st_mtu7 *)0xE8041A00) +#define MTU8 (*(volatile struct st_mtu8 *)0xE8041298) +#define MTUT (*(volatile struct st_mtut *)0xE8041D00) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/nandc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/nandc_iodefine.h new file mode 100644 index 0000000..e0f559e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/nandc_iodefine.h @@ -0,0 +1,512 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef NANDC_IODEFINE_H +#define NANDC_IODEFINE_H + +struct st_nandc +{ + union + { + unsigned long LONG; + struct + { + unsigned long CMD_SEQ:6; + unsigned long INPUT_SEL:1; + unsigned long DATA_SEL:1; + unsigned long CMD_0:8; + unsigned long CMD_1:8; + unsigned long CMD_2:8; + } BIT; + } COMMAND; + union + { + unsigned long LONG; + struct + { + unsigned long READ_STATUS_EN:1; + unsigned long ECC_BLOCK_SIZE:2; + unsigned long :1; + unsigned long INT_EN:1; + unsigned long ECC_EN:1; + unsigned long BLOCK_SIZE:2; + unsigned long :4; + unsigned long :1; + unsigned long BBM_EN:1; + unsigned long PROT_EN:1; + unsigned long :1; + unsigned long ADDR0_AUTO_INCR:1; + unsigned long ADDR1_AUTO_INCR:1; + unsigned long :3; + unsigned long SMALL_BLOCK_EN:1; + unsigned long MLUN_EN:1; + unsigned long AUTO_READ_STAT_EN:1; + unsigned long :8; + } BIT; + } CONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long MEM0_ST:1; + unsigned long :7; + unsigned long CTRL_STAT:1; + unsigned long DATASIZE_ERROR_ST:1; + unsigned long DATA_REG_ST:1; + unsigned long :5; + unsigned long CMD_ID:8; + unsigned long :8; + } BIT; + } STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long STATE_MASK:8; + unsigned long ERROR_MASK:8; + unsigned long :16; + } BIT; + } STATUS_MASK; + union + { + unsigned long LONG; + struct + { + unsigned long PROT_INT_EN:1; + unsigned long CMD_END_INT_EN:1; + unsigned long DATA_REG_INT_EN:1; + unsigned long DMA_INT_EN:1; + unsigned long TRANS_ERR_EN:1; + unsigned long :1; + unsigned long PG_SZ_ERR_INT_EN:1; + unsigned long :1; + unsigned long MEM0_RDY_INT_EN:1; + unsigned long :7; + unsigned long STAT_ERR_INT0_EN:1; + unsigned long :7; + unsigned long ECC_INT0_EN:1; + unsigned long :7; + } BIT; + } INT_MASK; + union + { + unsigned long LONG; + struct + { + unsigned long PROT_INT_FL:1; + unsigned long CMD_END_INT_FL:1; + unsigned long DATA_REG_INT_FL:1; + unsigned long DMA_INT_FL:1; + unsigned long TRANS_ERR_FL:1; + unsigned long :1; + unsigned long PG_SZ_ERR_INT_FL:1; + unsigned long :1; + unsigned long MEM0_RDY_INT_FL:1; + unsigned long :7; + unsigned long STAT_ERR_INT0_FL:1; + unsigned long :7; + unsigned long ECC_INT0_FL:1; + unsigned long :7; + } BIT; + } INT_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long ECC_CAP:3; + unsigned long :5; + unsigned long ERR_THRESHOLD:6; + unsigned long :2; + unsigned long ECC_SEL:2; + unsigned long :14; + } BIT; + } ECC_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long ECC_OFFSET:16; + unsigned long :16; + } BIT; + } ECC_OFFSET; + union + { + unsigned long LONG; + struct + { + unsigned long ECC_ERROR_0:1; + unsigned long :7; + unsigned long ECC_UNC_0:1; + unsigned long :7; + unsigned long ECC_OVER_0:1; + unsigned long :15; + } BIT; + } ECC_STAT; + union + { + unsigned long LONG; + struct + { + unsigned long ADDR0_COL:16; + unsigned long :16; + } BIT; + } ADDR0_COL; + union + { + unsigned long LONG; + struct + { + unsigned long ADDR0_ROW:24; + unsigned long :8; + } BIT; + } ADDR0_ROW; + union + { + unsigned long LONG; + struct + { + unsigned long ADDR1_COL:16; + unsigned long :16; + } BIT; + } ADDR1_COL; + union + { + unsigned long LONG; + struct + { + unsigned long ADDR1_ROW:24; + unsigned long :8; + } BIT; + } ADDR1_ROW; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long FIFO_DATA:32; + } BIT; + } FIFO_DATA; + union + { + unsigned long LONG; + struct + { + unsigned long DATA_REG:32; + } BIT; + } DATA_REG; + union + { + unsigned long LONG; + struct + { + unsigned long DATA_REG_SIZE:2; + unsigned long :30; + } BIT; + } DATA_REG_SIZE; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long PTR_ADDR:10; + unsigned long :20; + } BIT; + } DEV0_PTR; + char wk1[28]; + union + { + unsigned long LONG; + struct + { + unsigned long DMA_ADDR_L:32; + } BIT; + } DMA_ADDR_L; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CNT_INIT:32; + } BIT; + } DMA_CNT; + union + { + unsigned long LONG; + struct + { + unsigned long DMA_READY:1; + unsigned long :1; + unsigned long DMA_BURST:3; + unsigned long DMA_MODE:1; + unsigned long :1; + unsigned long DMA_START:1; + unsigned long :24; + } BIT; + } DMA_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long RMP_INIT:1; + unsigned long :31; + } BIT; + } BBM_CTRL; + char wk3[12]; + union + { + unsigned long LONG; + struct + { + unsigned long DATA_SIZE:15; + unsigned long :17; + } BIT; + } DATA_SIZE; + union + { + unsigned long LONG; + struct + { + unsigned long TRWP:4; + unsigned long TRWH:4; + unsigned long :24; + } BIT; + } TIMINGS_ASYN; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TCCS:6; + unsigned long :2; + unsigned long TADL:6; + unsigned long :2; + unsigned long TRHW:6; + unsigned long :2; + unsigned long TWHR:6; + unsigned long :2; + } BIT; + } TIME_SEQ_0; + union + { + unsigned long LONG; + struct + { + unsigned long TWB:6; + unsigned long :2; + unsigned long TRR:6; + unsigned long :18; + } BIT; + } TIME_SEQ_1; + union + { + unsigned long LONG; + struct + { + unsigned long t0_d0:6; + unsigned long :2; + unsigned long t0_d1:6; + unsigned long :2; + unsigned long t0_d2:6; + unsigned long :2; + unsigned long t0_d3:6; + unsigned long :2; + } BIT; + } TIME_GEN_SEQ_0; + union + { + unsigned long LONG; + struct + { + unsigned long t0_d4:6; + unsigned long :2; + unsigned long t0_d5:6; + unsigned long :2; + unsigned long t0_d6:6; + unsigned long :2; + unsigned long t0_d7:6; + unsigned long :2; + } BIT; + } TIME_GEN_SEQ_1; + union + { + unsigned long LONG; + struct + { + unsigned long t0_d8:6; + unsigned long :2; + unsigned long t0_d9:6; + unsigned long :2; + unsigned long t0_d10:6; + unsigned long :2; + unsigned long t0_d11:6; + unsigned long :2; + } BIT; + } TIME_GEN_SEQ_2; + char wk5[12]; + union + { + unsigned long LONG; + struct + { + unsigned long FIFO_INIT:1; + unsigned long :31; + } BIT; + } FIFO_INIT; + union + { + unsigned long LONG; + struct + { + unsigned long DF_R_EMPTY:1; + unsigned long DF_W_FULL:1; + unsigned long CF_EMPTY:1; + unsigned long CF_FULL:1; + unsigned long CF_ACCPT_R:1; + unsigned long CF_ACCPT_W:1; + unsigned long DF_R_FULL:1; + unsigned long DF_W_EMPTY:1; + unsigned long :24; + } BIT; + } FIFO_STATE; + union + { + unsigned long LONG; + struct + { + unsigned long CMD0_EN:1; + unsigned long CMD1_EN:1; + unsigned long CMD2_EN:1; + unsigned long CMD3_EN:1; + unsigned long COL_A0:2; + unsigned long COL_A1:2; + unsigned long ROW_A0:2; + unsigned long ROW_A1:2; + unsigned long DATA_EN:1; + unsigned long DELAY_EN:2; + unsigned long IMD_SEQ:1; + unsigned long CMD_3:8; + unsigned long :8; + } BIT; + } GEN_SEQ_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long MLUN_IDX:3; + unsigned long :5; + unsigned long LUN_SEL:2; + unsigned long :22; + } BIT; + } MLUN; + union + { + unsigned long LONG; + struct + { + unsigned long DEV_SIZE:12; + unsigned long :20; + } BIT; + } DEV0_SIZE; + char wk6[80]; + union + { + unsigned long LONG; + struct + { + unsigned long DMA_TRIG_TLVL:8; + unsigned long :24; + } BIT; + } DMA_TRIG_TLVL; + char wk7[12]; + union + { + unsigned long LONG; + struct + { + unsigned long CMD_ID:8; + unsigned long :24; + } BIT; + } CMD_MARK; + union + { + unsigned long LONG; + struct + { + unsigned long MEM0_LUN:8; + unsigned long :24; + } BIT; + } LUN_STATUS0; + char wk8[8]; + union + { + unsigned long LONG; + struct + { + unsigned long t0_d12:6; + unsigned long :26; + } BIT; + } TIME_GEN_SEQ_3; + char wk9[20]; + union + { + unsigned long LONG; + struct + { + unsigned long ERR_LVL:6; + unsigned long :26; + } BIT; + } ECC_CNT; +}; + +#define NANDC (*(volatile struct st_nandc *)0xE822C000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/octa_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/octa_iodefine.h new file mode 100644 index 0000000..9743db5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/octa_iodefine.h @@ -0,0 +1,303 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef OCTA_IODEFINE_H +#define OCTA_IODEFINE_H + +struct st_octa +{ + union + { + unsigned long LONG; + struct + { + unsigned long DVCMD0:8; + unsigned long DVCMD1:8; + unsigned long :8; + unsigned long :8; + } BIT; + } DCR; + union + { + unsigned long LONG; + struct + { + unsigned long DVAD0:8; + unsigned long DVAD1:8; + unsigned long DVAD2:8; + unsigned long DVAD3:8; + } BIT; + } DAR; + union + { + unsigned long LONG; + struct + { + unsigned long DALEN:8; + unsigned long DMLEN:8; + unsigned long :3; + unsigned long ACDV:1; + unsigned long CMDLEN:3; + unsigned long DAOR:1; + unsigned long ADLEN:3; + unsigned long DOPI:1; + unsigned long ACDA:1; + unsigned long :1; + unsigned long :2; + } BIT; + } DCSR; + union + { + unsigned long LONG; + struct + { + unsigned long DV0SZ:30; + unsigned long DV0TYP:2; + } BIT; + } DSR0; + union + { + unsigned long LONG; + struct + { + unsigned long DV1SZ:30; + unsigned long DV1TYP:2; + } BIT; + } DSR1; + union + { + unsigned long LONG; + struct + { + unsigned long DV0DEL:8; + unsigned long DQSERAM:4; + unsigned long DQSESOPI:4; + unsigned long DV1DEL:8; + unsigned long DQSEDOPI:4; + unsigned long :4; + } BIT; + } MDTR; + union + { + unsigned long LONG; + struct + { + unsigned long CTP:32; + } BIT; + } ACTR; + union + { + unsigned long LONG; + struct + { + unsigned long CAD0:32; + } BIT; + } ACAR0; + union + { + unsigned long LONG; + struct + { + unsigned long CAD1:32; + } BIT; + } ACAR1; + char wk0[16]; + union + { + unsigned long LONG; + struct + { + unsigned long CTRW0:7; + unsigned long CTR0:1; + unsigned long DVRDCMD0:3; + unsigned long DVRDHI0:3; + unsigned long DVRDLO0:2; + unsigned long CTRW1:7; + unsigned long CTR1:1; + unsigned long DVRDCMD1:3; + unsigned long DVRDHI1:3; + unsigned long DVRDLO1:2; + } BIT; + } DRCSTR; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long DVWCMD0:3; + unsigned long DVWHI0:3; + unsigned long DVWLO0:2; + unsigned long :8; + unsigned long DVWCMD1:3; + unsigned long DVWHI1:3; + unsigned long DVWLO1:2; + } BIT; + } DWCSTR; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long DVSELCMD:3; + unsigned long DVSELHI:3; + unsigned long DVSELLO:2; + unsigned long :16; + } BIT; + } DCSTR; + union + { + unsigned long LONG; + struct + { + unsigned long DV0TTYP:2; + unsigned long DV1TTYP:2; + unsigned long DV0PC:1; + unsigned long DV1PC:1; + unsigned long :4; + unsigned long ACMEME:2; + unsigned long ACMODE:2; + unsigned long :17; + unsigned long DLFT:1; + } BIT; + } CDSR; + union + { + unsigned long LONG; + struct + { + unsigned long DV0RDL:8; + unsigned long DV0WDL:8; + unsigned long DV1RDL:8; + unsigned long DV1WDL:8; + } BIT; + } MDLR; + union + { + unsigned long LONG; + struct + { + unsigned long D0MRCMD0:8; + unsigned long D0MRCMD1:8; + unsigned long D0MWCMD0:8; + unsigned long D0MWCMD1:8; + } BIT; + } MRWCR0; + union + { + unsigned long LONG; + struct + { + unsigned long D1MRCMD0:8; + unsigned long D1MRCMD1:8; + unsigned long D1MWCMD0:8; + unsigned long D1MWCMD1:8; + } BIT; + } MRWCR1; + union + { + unsigned long LONG; + struct + { + unsigned long MRAL0:3; + unsigned long MRCL0:3; + unsigned long MRO0:1; + unsigned long :1; + unsigned long MWAL0:3; + unsigned long MWCL0:3; + unsigned long MWO0:1; + unsigned long :1; + unsigned long MRAL1:3; + unsigned long MRCL1:3; + unsigned long MRO1:1; + unsigned long :1; + unsigned long MWAL1:3; + unsigned long MWCL1:3; + unsigned long MWO1:1; + unsigned long :1; + } BIT; + } MRWCSR; + union + { + unsigned long LONG; + struct + { + unsigned long MRESR:8; + unsigned long MWESR:8; + unsigned long :16; + } BIT; + } ESR; + unsigned long CWNDR; + union + { + unsigned long LONG; + struct + { + unsigned long WD0:8; + unsigned long WD1:8; + unsigned long WD2:8; + unsigned long WD3:8; + } BIT; + } CWDR; + union + { + unsigned long LONG; + struct + { + unsigned long RD0:8; + unsigned long RD1:8; + unsigned long RD2:8; + unsigned long RD3:8; + } BIT; + } CRR; + char wk1[4]; + char wk2[4]; + char wk3[4]; + char wk4[4]; + char wk5[4]; + char wk6[4]; +}; + +#define OCTA (*(volatile struct st_octa *)0x1F401000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ostm_iodefine.h new file mode 100644 index 0000000..fca4b6d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ostm_iodefine.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef OSTM_IODEFINE_H +#define OSTM_IODEFINE_H + +struct st_ostm +{ + union + { + unsigned long LONG; + struct + { + unsigned long OSTMnCMP:32; + } BIT; + } OSTMnCMP; + union + { + unsigned long LONG; + struct + { + unsigned long OSTMnCNT:32; + } BIT; + } OSTMnCNT; + char wk0[1]; + char wk1[3]; + char wk2[1]; + char wk3[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char OSTMnTE:1; + unsigned char :7; + } BIT; + } OSTMnTE; + char wk4[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char OSTMnTS:1; + unsigned char :7; + } BIT; + } OSTMnTS; + char wk5[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char OSTMnTT:1; + unsigned char :7; + } BIT; + } OSTMnTT; + char wk6[7]; + union + { + unsigned char BYTE; + struct + { + unsigned char OSTMnMD0:1; + unsigned char OSTMnMD1:1; + unsigned char :6; + } BIT; + } OSTMnCTL; + char wk7[3]; + char wk8[1]; +}; + +#define OSTM0 (*(volatile struct st_ostm *)0xE803B000) +#define OSTM1 (*(volatile struct st_ostm *)0xE803C000) +#define OSTM2 (*(volatile struct st_ostm *)0xE803D000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pl_iodefine.h new file mode 100644 index 0000000..60cac1e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pl_iodefine.h @@ -0,0 +1,590 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef PL_IODEFINE_H +#define PL_IODEFINE_H + +struct st_pl +{ + union + { + unsigned long LONG; + struct + { + unsigned long RTLrelease:6; + unsigned long Partnumber:4; + unsigned long CACHEID:6; + unsigned long :8; + unsigned long Implementer:8; + } BIT; + } REG0_CACHE_ID; + union + { + unsigned long LONG; + struct + { + unsigned long L2cachelinelength1:2; + unsigned long :4; + unsigned long L2associativity1:1; + unsigned long Isize:5; + unsigned long L2cachelinelength0:2; + unsigned long :4; + unsigned long L2associativity0:1; + unsigned long Dsize:5; + unsigned long H:1; + unsigned long ctype:4; + unsigned long :2; + unsigned long Databanking:1; + } BIT; + } REG0_CACHE_TYPE; + char wk0[248]; + union + { + unsigned long LONG; + struct + { + unsigned long L2Cacheenable:1; + unsigned long :31; + } BIT; + } REG1_CONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long FullLineofZeroEnable:1; + unsigned long :9; + unsigned long HighPriorityforSOandDevReadsEnable:1; + unsigned long StorebufferdevicelimitationEnable:1; + unsigned long Exclusivecacheconfiguration:1; + unsigned long SharedAttributeInvalidateEnable:1; + unsigned long :2; + unsigned long Associativity:1; + unsigned long Waysize:3; + unsigned long Eventmonitorbusenable:1; + unsigned long Parityenable:1; + unsigned long Sharedattributeoverrideenable:1; + unsigned long Forcewriteallocate:2; + unsigned long Cachereplacementpolicy:1; + unsigned long Nonsecurelockdownenable:1; + unsigned long Nonsecureinterruptaccesscontrol:1; + unsigned long Dataprefetchenable:1; + unsigned long Instructionprefetchenable:1; + unsigned long EarlyBRESPenable:1; + unsigned long :1; + } BIT; + } REG1_AUX_CONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long RAMsetuplatency:3; + unsigned long :1; + unsigned long RAMreadaccesslatency:3; + unsigned long :1; + unsigned long RAMwriteaccesslatency:3; + unsigned long :21; + } BIT; + } REG1_TAG_RAM_CONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long RAMsetuplatency:3; + unsigned long :1; + unsigned long RAMreadaccesslatency:3; + unsigned long :1; + unsigned long RAMwriteaccesslatency:3; + unsigned long :21; + } BIT; + } REG1_DATA_RAM_CONTROL; + char wk1[240]; + union + { + unsigned long LONG; + struct + { + unsigned long Eventcounterenable:1; + unsigned long Counterreset:2; + unsigned long :29; + } BIT; + } REG2_EV_COUNTER_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long Eventcounterinterruptgeneration:2; + unsigned long Countereventsource:4; + unsigned long :26; + } BIT; + } REG2_EV_COUNTER1_CFG; + union + { + unsigned long LONG; + struct + { + unsigned long Eventcounterinterruptgeneration:2; + unsigned long Countereventsource:4; + unsigned long :26; + } BIT; + } REG2_EV_COUNTER0_CFG; + union + { + unsigned long LONG; + struct + { + unsigned long Countervalue:32; + } BIT; + } REG2_EV_COUNTER1; + union + { + unsigned long LONG; + struct + { + unsigned long Countervalue:32; + } BIT; + } REG2_EV_COUNTER0; + union + { + unsigned long LONG; + struct + { + unsigned long ECNTR:1; + unsigned long PARRT:1; + unsigned long PARRD:1; + unsigned long ERRWT:1; + unsigned long ERRWD:1; + unsigned long ERRRT:1; + unsigned long ERRRD:1; + unsigned long SLVERR:1; + unsigned long DECERR:1; + unsigned long :23; + } BIT; + } REG2_INT_MASK; + union + { + unsigned long LONG; + struct + { + unsigned long ECNTR:1; + unsigned long PARRT:1; + unsigned long PARRD:1; + unsigned long ERRWT:1; + unsigned long ERRWD:1; + unsigned long ERRRT:1; + unsigned long ERRRD:1; + unsigned long SLVERR:1; + unsigned long DECERR:1; + unsigned long :23; + } BIT; + } REG2_INT_MASK_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long ECNTR:1; + unsigned long PARRT:1; + unsigned long PARRD:1; + unsigned long ERRWT:1; + unsigned long ERRWD:1; + unsigned long ERRRT:1; + unsigned long ERRRD:1; + unsigned long SLVERR:1; + unsigned long DECERR:1; + unsigned long :23; + } BIT; + } REG2_INT_RAW_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long ECNTR:1; + unsigned long PARRT:1; + unsigned long PARRD:1; + unsigned long ERRWT:1; + unsigned long ERRWD:1; + unsigned long ERRRT:1; + unsigned long ERRRD:1; + unsigned long SLVERR:1; + unsigned long DECERR:1; + unsigned long :23; + } BIT; + } REG2_INT_CLEAR; + char wk2[1292]; + union + { + unsigned long LONG; + struct + { + unsigned long C:1; + unsigned long :31; + } BIT; + } REG7_CACHE_SYNC; + char wk3[60]; + union + { + unsigned long LONG; + struct + { + unsigned long C:1; + unsigned long :4; + unsigned long INDEX:9; + unsigned long TAG:18; + } BIT; + } REG7_INV_PA; + char wk4[8]; + union + { + unsigned long LONG; + struct + { + unsigned long Way_bits:8; + unsigned long :24; + } BIT; + } REG7_INV_WAY; + char wk5[48]; + union + { + unsigned long LONG; + struct + { + unsigned long C:1; + unsigned long :4; + unsigned long INDEX:9; + unsigned long TAG:18; + } BIT; + } REG7_CLEAN_PA; + char wk6[4]; + union + { + unsigned long LONG; + struct + { + unsigned long C:1; + unsigned long :4; + unsigned long INDEX:9; + unsigned long :14; + unsigned long Way:3; + unsigned long :1; + } BIT; + } REG7_CLEAN_INDEX; + union + { + unsigned long LONG; + struct + { + unsigned long Way_bits:8; + unsigned long :24; + } BIT; + } REG7_CLEAN_WAY; + char wk7[48]; + union + { + unsigned long LONG; + struct + { + unsigned long C:1; + unsigned long :4; + unsigned long INDEX:9; + unsigned long TAG:18; + } BIT; + } REG7_CLEAN_INV_PA; + char wk8[4]; + union + { + unsigned long LONG; + struct + { + unsigned long C:1; + unsigned long :4; + unsigned long INDEX:9; + unsigned long :14; + unsigned long Way:3; + unsigned long :1; + } BIT; + } REG7_CLEAN_INV_INDEX; + union + { + unsigned long LONG; + struct + { + unsigned long Way_bits:8; + unsigned long :24; + } BIT; + } REG7_CLEAN_INV_WAY; + char wk9[256]; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK000:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN0; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK000:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN0; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK001:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN1; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK001:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN1; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK002:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN2; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK002:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN2; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK003:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN3; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK003:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN3; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK004:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN4; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK004:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN4; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK005:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN5; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK005:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN5; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK006:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN6; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK006:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN6; + union + { + unsigned long LONG; + struct + { + unsigned long DATALOCK007:8; + unsigned long :24; + } BIT; + } REG9_D_LOCKDOWN7; + union + { + unsigned long LONG; + struct + { + unsigned long INSTRLOCK007:8; + unsigned long :24; + } BIT; + } REG9_I_LOCKDOWN7; + char wk10[16]; + union + { + unsigned long LONG; + struct + { + unsigned long lockdown_by_line_enable:1; + unsigned long :31; + } BIT; + } REG9_LOCK_LINE_EN; + union + { + unsigned long LONG; + struct + { + unsigned long unlock_all_lines_by_way_operation:8; + unsigned long :24; + } BIT; + } REG9_UNLOCK_WAY; + char wk11[680]; + union + { + unsigned long LONG; + struct + { + unsigned long address_filtering_enable:1; + unsigned long :19; + unsigned long address_filtering_start:12; + } BIT; + } REG12_ADDR_FILTERING_START; + union + { + unsigned long LONG; + struct + { + unsigned long :20; + unsigned long address_filtering_end:12; + } BIT; + } REG12_ADDR_FILTERING_END; + char wk12[824]; + union + { + unsigned long LONG; + struct + { + unsigned long DCL:1; + unsigned long DWB:1; + unsigned long SPNIDEN:1; + unsigned long :29; + } BIT; + } REG15_DEBUG_CTRL; + char wk13[28]; + union + { + unsigned long LONG; + struct + { + unsigned long Prefetchoffset:5; + unsigned long :16; + unsigned long NotsameIDonexclusivesequenceenable:1; + unsigned long :1; + unsigned long IncrdoubleLinefillenable:1; + unsigned long Prefetchdropenable:1; + unsigned long :2; + unsigned long DoublelinefillonWRAPreaddisable:1; + unsigned long Dataprefetchenable:1; + unsigned long Instructionprefetchenable:1; + unsigned long Doublelinefillenable:1; + unsigned long :1; + } BIT; + } REG15_PREFETCH_CTRL; + char wk14[28]; + union + { + unsigned long LONG; + struct + { + unsigned long standby_mode_en:1; + unsigned long dynamic_clk_gating_en:1; + unsigned long :30; + } BIT; + } REG15_POWER_CTRL; +}; + +#define pl310 (*(volatile struct st_pl *)0x1F003000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pmg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pmg_iodefine.h new file mode 100644 index 0000000..24d2c24 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/pmg_iodefine.h @@ -0,0 +1,210 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef PMG_IODEFINE_H +#define PMG_IODEFINE_H + +struct st_pmg +{ + union + { + unsigned char BYTE; + struct + { + unsigned char RRAMKP0:1; + unsigned char RRAMKP1:1; + unsigned char RRAMKP2:1; + unsigned char RRAMKP3:1; + unsigned char :3; + unsigned char :1; + } BIT; + } RRAMKP; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char RAMBOOT:1; + unsigned char EBUSKEEPE:1; + } BIT; + } DSCTR; + char wk1[1]; + union + { + unsigned short WORD; + struct + { + unsigned short P3_1:1; + unsigned short P3_3:1; + unsigned short P6_2:1; + unsigned short PE_1:1; + unsigned short PH_1:1; + unsigned short PG_2:1; + unsigned short RTCAR0:1; + unsigned short RTCAR1:1; + unsigned short NMI:1; + unsigned short PG_6:1; + unsigned short PH_0:1; + unsigned short PJ_1:1; + unsigned short PJ_5:1; + unsigned short PK_2:1; + unsigned short PK_4:1; + unsigned short :1; + } BIT; + } DSSSR; + union + { + unsigned short WORD; + struct + { + unsigned short P3_1E:1; + unsigned short P3_3E:1; + unsigned short P6_2E:1; + unsigned short PE_1E:1; + unsigned short PH_1E:1; + unsigned short PG_2E:1; + unsigned short :2; + unsigned short NMIE:1; + unsigned short PG_6E:1; + unsigned short PH_0E:1; + unsigned short PJ_1E:1; + unsigned short PJ_5E:1; + unsigned short PK_2E:1; + unsigned short PK_4E:1; + unsigned short :1; + } BIT; + } DSESR; + union + { + unsigned short WORD; + struct + { + unsigned short P3_1F:1; + unsigned short P3_3F:1; + unsigned short P6_2F:1; + unsigned short PE_1F:1; + unsigned short PH_1F:1; + unsigned short PG_2F:1; + unsigned short RTCARF0:1; + unsigned short RTCARF1:1; + unsigned short NMIF:1; + unsigned short PG_6F:1; + unsigned short PH_0F:1; + unsigned short PJ_1F:1; + unsigned short PJ_5F:1; + unsigned short PK_2F:1; + unsigned short PK_4F:1; + unsigned short IOKEEP:1; + } BIT; + } DSFR; + char wk2[2]; + char wk3[1]; + char wk4[1]; + union + { + unsigned short WORD; + struct + { + unsigned short CNTD:8; + unsigned short :6; + unsigned short :1; + unsigned short :1; + } BIT; + } DSCNT; + union + { + unsigned char BYTE; + struct + { + unsigned char GAIN0:1; + unsigned char :1; + unsigned char :6; + } BIT; + } XTALCTR; + char wk5[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char USBDSCE0:1; + unsigned char USBDSCE1:1; + unsigned char USBDSCE2:1; + unsigned char USBDSCE3:1; + unsigned char :4; + } BIT; + } USBDSSSR; + char wk6[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char USBDSF0:1; + unsigned char USBDSF1:1; + unsigned char USBDSF2:1; + unsigned char USBDSF3:1; + unsigned char :4; + } BIT; + } USBDSFR; + char wk7[11]; + char wk8[2]; + char wk9[2]; + char wk10[2]; + char wk11[10]; + union + { + unsigned short WORD; + struct + { + unsigned short RTC0XT:1; + unsigned short RTC1XT:1; + unsigned short :14; + } BIT; + } RTCXTALSEL; +}; + +#define PMG (*(volatile struct st_pmg *)0xFCFFC000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poe_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poe_iodefine.h new file mode 100644 index 0000000..8fee419 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poe_iodefine.h @@ -0,0 +1,219 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef POE_IODEFINE_H +#define POE_IODEFINE_H + +struct st_poe +{ + union + { + unsigned short WORD; + struct + { + unsigned short POE0M:2; + unsigned short :6; + unsigned short PIE1:1; + unsigned short :3; + unsigned short POE0F:1; + unsigned short :3; + } BIT; + } ICSR1; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short OIE1:1; + unsigned short OCE1:1; + unsigned short :5; + unsigned short OSF1:1; + } BIT; + } OCSR1; + union + { + unsigned short WORD; + struct + { + unsigned short POE4M:2; + unsigned short :6; + unsigned short PIE2:1; + unsigned short :3; + unsigned short POE4F:1; + unsigned short :3; + } BIT; + } ICSR2; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short OIE2:1; + unsigned short OCE2:1; + unsigned short :5; + unsigned short OSF2:1; + } BIT; + } OCSR2; + union + { + unsigned short WORD; + struct + { + unsigned short POE8M:2; + unsigned short :6; + unsigned short PIE3:1; + unsigned short POE8E:1; + unsigned short :2; + unsigned short POE8F:1; + unsigned short :3; + } BIT; + } ICSR3; + union + { + unsigned char BYTE; + struct + { + unsigned char MTUCH34HIZ:1; + unsigned char MTUCH67HIZ:1; + unsigned char MTUCH0HIZ:1; + unsigned char :5; + } BIT; + } SPOER; + union + { + unsigned char BYTE; + struct + { + unsigned char MTU0AZE:1; + unsigned char MTU0BZE:1; + unsigned char MTU0CZE:1; + unsigned char MTU0DZE:1; + unsigned char :4; + } BIT; + } POECR1; + union + { + unsigned short WORD; + struct + { + unsigned short MTU7BDZE:1; + unsigned short MTU7ACZE:1; + unsigned short MTU6BDZE:1; + unsigned short :5; + unsigned short MTU4BDZE:1; + unsigned short MTU4ACZE:1; + unsigned short MTU3BDZE:1; + unsigned short :5; + } BIT; + } POECR2; + char wk0[2]; + union + { + unsigned short WORD; + struct + { + unsigned short :2; + unsigned short IC2ADDMT34ZE:1; + unsigned short IC3ADDMT34ZE:1; + unsigned short IC4ADDMT34ZE:1; + unsigned short :4; + unsigned short IC1ADDMT67ZE:1; + unsigned short :1; + unsigned short IC3ADDMT67ZE:1; + unsigned short IC4ADDMT67ZE:1; + unsigned short :3; + } BIT; + } POECR4; + union + { + unsigned short WORD; + struct + { + unsigned short :1; + unsigned short IC1ADDMT0ZE:1; + unsigned short IC2ADDMT0ZE:1; + unsigned short :1; + unsigned short IC4ADDMT0ZE:1; + unsigned short :11; + } BIT; + } POECR5; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short POE10M:2; + unsigned short :6; + unsigned short PIE4:1; + unsigned short POE10E:1; + unsigned short :2; + unsigned short POE10F:1; + unsigned short :3; + } BIT; + } ICSR4; + char wk2[12]; + union + { + unsigned char BYTE; + struct + { + unsigned char M0ASEL:4; + unsigned char M0BSEL:4; + } BIT; + } M0SELR1; + union + { + unsigned char BYTE; + struct + { + unsigned char M0CSEL:4; + unsigned char M0DSEL:4; + } BIT; + } M0SELR2; +}; + +#define POE3 (*(volatile struct st_poe *)0xE8042000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poeg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poeg_iodefine.h new file mode 100644 index 0000000..5b91239 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/poeg_iodefine.h @@ -0,0 +1,131 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef POEG_IODEFINE_H +#define POEG_IODEFINE_H + +struct st_poeg +{ + union + { + unsigned long LONG; + struct + { + unsigned long PIDF:1; + unsigned long IOCF:1; + unsigned long :1; + unsigned long SSF:1; + unsigned long PIDE:1; + unsigned long IOCE:1; + unsigned long :10; + unsigned long ST:1; + unsigned long :11; + unsigned long INV:1; + unsigned long NFEN:1; + unsigned long NFCS:2; + } BIT; + } POEGGA; + char wk0[2044]; + union + { + unsigned long LONG; + struct + { + unsigned long PIDF:1; + unsigned long IOCF:1; + unsigned long :1; + unsigned long SSF:1; + unsigned long PIDE:1; + unsigned long IOCE:1; + unsigned long :10; + unsigned long ST:1; + unsigned long :11; + unsigned long INV:1; + unsigned long NFEN:1; + unsigned long NFCS:2; + } BIT; + } POEGGB; + char wk1[2044]; + union + { + unsigned long LONG; + struct + { + unsigned long PIDF:1; + unsigned long IOCF:1; + unsigned long :1; + unsigned long SSF:1; + unsigned long PIDE:1; + unsigned long IOCE:1; + unsigned long :10; + unsigned long ST:1; + unsigned long :11; + unsigned long INV:1; + unsigned long NFEN:1; + unsigned long NFCS:2; + } BIT; + } POEGGC; + char wk2[2044]; + union + { + unsigned long LONG; + struct + { + unsigned long PIDF:1; + unsigned long IOCF:1; + unsigned long :1; + unsigned long SSF:1; + unsigned long PIDE:1; + unsigned long IOCE:1; + unsigned long :10; + unsigned long ST:1; + unsigned long :11; + unsigned long INV:1; + unsigned long NFEN:1; + unsigned long NFCS:2; + } BIT; + } POEGGD; +}; + +#define POEG (*(volatile struct st_poeg *)0xE8044000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/prr_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/prr_iodefine.h new file mode 100644 index 0000000..7eec55c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/prr_iodefine.h @@ -0,0 +1,622 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef PRR_IODEFINE_H +#define PRR_IODEFINE_H + +struct st_prr +{ + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DID:32; + } BIT; + } BSID; + char wk1[4]; + char wk2[4]; + char wk3[4]; + char wk4[4]; + char wk5[488]; + char wk6[4]; + char wk7[4]; + char wk8[4]; + char wk9[4]; + char wk10[16]; + char wk11[4]; + char wk12[4]; + char wk13[4]; + char wk14[4]; + char wk15[4]; + char wk16[4]; + char wk17[4]; + char wk18[4]; + char wk19[4]; + char wk20[4]; + char wk21[4]; + char wk22[4]; + char wk23[4]; + char wk24[4]; + char wk25[4]; + char wk26[4]; + char wk27[4]; + char wk28[4]; + char wk29[4]; + char wk30[4]; + char wk31[4]; + char wk32[4]; + char wk33[4]; + char wk34[4]; + char wk35[4]; + char wk36[4]; + char wk37[4]; + char wk38[4]; + char wk39[4]; + char wk40[4]; + char wk41[4]; + char wk42[4]; + char wk43[352]; + char wk44[4]; + union + { + unsigned long LONG; + struct + { + unsigned long ETHAXCACHE:2; + unsigned long :14; + unsigned long JCUAWCACHE:4; + unsigned long :4; + unsigned long JCUARCACHE:4; + unsigned long :4; + } BIT; + } AXIBUSCTL0; + union + { + unsigned long LONG; + struct + { + unsigned long VINAWCACHE:4; + unsigned long :12; + unsigned long IMR20AWCACHE:4; + unsigned long :4; + unsigned long IMR20ARCACHE:4; + unsigned long :4; + } BIT; + } AXIBUSCTL1; + union + { + unsigned long LONG; + struct + { + unsigned long CEUAWCACHE:4; + unsigned long :28; + } BIT; + } AXIBUSCTL2; + union + { + unsigned long LONG; + struct + { + unsigned long SDMMC1AWCACHE:4; + unsigned long :4; + unsigned long SDMMC1ARCACHE:4; + unsigned long :4; + unsigned long SDMMC0AWCACHE:4; + unsigned long :4; + unsigned long SDMMC0ARCACHE:4; + unsigned long :4; + } BIT; + } AXIBUSCTL3; + union + { + unsigned long LONG; + struct + { + unsigned long DRPAWCACHE:4; + unsigned long :4; + unsigned long DRPARCACHE:4; + unsigned long :4; + unsigned long NANDAWCACHE:4; + unsigned long :4; + unsigned long NANDARCACHE:4; + unsigned long :4; + } BIT; + } AXIBUSCTL4; + union + { + unsigned long LONG; + struct + { + unsigned long D2D1AXCACHE:2; + unsigned long :14; + unsigned long D2D0AXCACHE:2; + unsigned long :14; + } BIT; + } AXIBUSCTL5; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long VDC602ARCACHE:4; + unsigned long :4; + unsigned long VDC601AWCACHE:4; + unsigned long :4; + unsigned long VDC601ARCACHE:4; + unsigned long :4; + } BIT; + } AXIBUSCTL6; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long VDC604ARCACHE:4; + unsigned long :20; + } BIT; + } AXIBUSCTL7; + char wk45[12]; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long CEURERREN:1; + unsigned long :7; + unsigned long VINRERREN:1; + unsigned long :3; + unsigned long IMR20RERREN:1; + unsigned long :7; + unsigned long JCURERREN:1; + unsigned long :3; + } BIT; + } AXIRERRCTL0; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long DRPRERREN:1; + unsigned long :3; + unsigned long NANDRERREN:1; + unsigned long :3; + unsigned long SDMMC1RERREN:1; + unsigned long :3; + unsigned long SDMMC0RERREN:1; + unsigned long :3; + } BIT; + } AXIRERRCTL1; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long VDC604RERREN:1; + unsigned long :7; + unsigned long VDC602RERREN:1; + unsigned long :3; + unsigned long VDC601RERREN:1; + unsigned long :3; + } BIT; + } AXIRERRCTL2; + char wk46[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long CEUBRESP:2; + unsigned long :6; + unsigned long VINBRESP:2; + unsigned long :2; + unsigned long IMR20BRESP:2; + unsigned long IMR20RRESP:2; + unsigned long :4; + unsigned long JCUBRESP:2; + unsigned long JCURRESP:2; + } BIT; + } AXIRERRST0; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long DRPBRESP:2; + unsigned long DRPRRESP:2; + unsigned long NANDBRESP:2; + unsigned long NANDRRESP:2; + unsigned long SDMMC1BRESP:2; + unsigned long SDMMC1RRESP:2; + unsigned long SDMMC0BRESP:2; + unsigned long SDMMC0RRESP:2; + } BIT; + } AXIRERRST1; + union + { + unsigned long LONG; + struct + { + unsigned long :18; + unsigned long VDC604RRESP:2; + unsigned long :6; + unsigned long VDC602RRESP:2; + unsigned long VDC601BRESP:2; + unsigned long VDC601RRESP:2; + } BIT; + } AXIRERRST2; + char wk47[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long CEUBRESPCLR:1; + unsigned long :3; + unsigned long SERBRESPCLR:1; + unsigned long :1; + unsigned long SERRRESPCLR:1; + unsigned long :1; + unsigned long VINBRESPCLR:1; + unsigned long :3; + unsigned long IMR20BRESPCLR:1; + unsigned long :1; + unsigned long IMR20RRESPCLR:1; + unsigned long :5; + unsigned long JCUBRESPCLR:1; + unsigned long :1; + unsigned long JCURRESPCLR:1; + unsigned long :1; + } BIT; + } AXIRERRCLR0; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long DRPBRESPCLR:1; + unsigned long :1; + unsigned long DRPRRESPCLR:1; + unsigned long :1; + unsigned long NANDBRESPCLR:1; + unsigned long :1; + unsigned long NANDRRESPCLR:1; + unsigned long :1; + unsigned long SDMMC1BRESPCLR:1; + unsigned long :1; + unsigned long SDMMC1RRESPCLR:1; + unsigned long :1; + unsigned long SDMMC0BRESPCLR:1; + unsigned long :1; + unsigned long SDMMC0RRESPCLR:1; + unsigned long :1; + } BIT; + } AXIRERRCLR1; + union + { + unsigned long LONG; + struct + { + unsigned long :18; + unsigned long VDC604RRESPCLR:1; + unsigned long :7; + unsigned long VDC602RRESPCLR:1; + unsigned long :1; + unsigned long VDC601BRESPCLR:1; + unsigned long :1; + unsigned long VDC601RRESPCLR:1; + unsigned long :1; + } BIT; + } AXIRERRCLR2; + char wk48[4]; + char wk49[4]; + char wk50[2972]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long VINAWNS:1; + unsigned long :7; + unsigned long IMR20AWNS:1; + unsigned long :3; + unsigned long IMR20ARNS:1; + unsigned long :3; + unsigned long ETHAxNS:1; + unsigned long :7; + unsigned long JCUAWNS:1; + unsigned long :3; + unsigned long JCUARNS:1; + unsigned long :2; + } BIT; + } MSTACCCTL0; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long SDMMC1AWNS:1; + unsigned long :3; + unsigned long SDMMC1ARNS:1; + unsigned long :3; + unsigned long SDMMC0AWNS:1; + unsigned long :3; + unsigned long SDMMC0ARNS:1; + unsigned long :3; + unsigned long CEUAWNS:1; + unsigned long :14; + } BIT; + } MSTACCCTL1; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long D2D1AxNS:1; + unsigned long :7; + unsigned long D2D0AxNS:1; + unsigned long :7; + unsigned long DRPAWNS:1; + unsigned long :3; + unsigned long DRPARNS:1; + unsigned long :3; + unsigned long NANDAWNS:1; + unsigned long :3; + unsigned long NANDARNS:1; + unsigned long :2; + } BIT; + } MSTACCCTL2; + union + { + unsigned long LONG; + struct + { + unsigned long :5; + unsigned long VDC604ARNS:1; + unsigned long :15; + unsigned long VDC602ARNS:1; + unsigned long :3; + unsigned long VDC601AWNS:1; + unsigned long :3; + unsigned long VDC601ARNS:1; + unsigned long :2; + } BIT; + } MSTACCCTL3; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long USB11AxNS:1; + unsigned long :7; + unsigned long USB10AxNS:1; + unsigned long :7; + unsigned long USB01AxNS:1; + unsigned long :7; + unsigned long USB00AxNS:1; + unsigned long :6; + } BIT; + } MSTACCCTL4; + char wk51[12]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long WDTNS:1; + unsigned long :1; + unsigned long INTC2NS:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long POEGNS:1; + unsigned long :1; + unsigned long POE3NS:1; + unsigned long :1; + unsigned long GPTNS:1; + unsigned long :1; + unsigned long MTU3NS:1; + unsigned long :1; + unsigned long IMR20NS:1; + unsigned long :1; + unsigned long VDC60NS:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long SYSNS:1; + unsigned long :1; + } BIT; + } SLVACCCTL0; + union + { + unsigned long LONG; + struct + { + unsigned long RSPINS:1; + unsigned long :1; + unsigned long JCUNS:1; + unsigned long :1; + unsigned long SCIFNS:1; + unsigned long :1; + unsigned long SCINS:1; + unsigned long :1; + unsigned long IRDANS:1; + unsigned long :1; + unsigned long ADNS:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long SENS:1; + unsigned long :1; + unsigned long RCANNS:1; + unsigned long :1; + unsigned long SPDIFNS:1; + unsigned long :1; + unsigned long SSIFNS:1; + unsigned long :1; + unsigned long OSTM2NS:1; + unsigned long :1; + unsigned long OSTM1NS:1; + unsigned long :1; + unsigned long OSTM0NS:1; + unsigned long :1; + unsigned long I2CNS:1; + unsigned long :1; + unsigned long GPIONS:1; + unsigned long :1; + } BIT; + } SLVACCCTL1; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long TSIPNS:1; + unsigned long :1; + unsigned long DRPNS:1; + unsigned long :1; + unsigned long CEUNS:1; + unsigned long :1; + unsigned long USB11NS:1; + unsigned long :1; + unsigned long USB10NS:1; + unsigned long :1; + unsigned long USB01NS:1; + unsigned long :1; + unsigned long USB00NS:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long VINNS:1; + unsigned long :1; + unsigned long MIPINS:1; + unsigned long :1; + unsigned long D2DNS:1; + unsigned long :3; + unsigned long ETHNS:1; + unsigned long :1; + } BIT; + } SLVACCCTL2; + union + { + unsigned long LONG; + struct + { + unsigned long :20; + unsigned long CSNS:1; + unsigned long :3; + unsigned long NANDNS:1; + unsigned long :1; + unsigned long SDMMC1NS:1; + unsigned long :1; + unsigned long SDMMC0NS:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + } BIT; + } SLVACCCTL3; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long VRAM4NS:1; + unsigned long :1; + unsigned long VRAM3NS:1; + unsigned long :1; + unsigned long VRAM2NS:1; + unsigned long :1; + unsigned long VRAM1NS:1; + unsigned long :1; + unsigned long VRAM0NS:1; + unsigned long :1; + unsigned long RRAMNS:1; + unsigned long :1; + unsigned long HYPRNS:1; + unsigned long :1; + unsigned long HYPNS:1; + unsigned long :1; + unsigned long OCTARNS:1; + unsigned long :1; + unsigned long OCTANS:1; + unsigned long :1; + unsigned long SPINS:1; + unsigned long :1; + unsigned long BSCNS:1; + unsigned long :1; + } BIT; + } SLVACCCTL4; + char wk52[460]; + char wk53[4]; +}; + +#define PRR (*(volatile struct st_prr *)0xFCFE8000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ptpedmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ptpedmac_iodefine.h new file mode 100644 index 0000000..4221bb4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ptpedmac_iodefine.h @@ -0,0 +1,288 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef PTPEDMAC_IODEFINE_H +#define PTPEDMAC_IODEFINE_H + +struct st_ptpedmac +{ + union + { + unsigned long LONG; + struct + { + unsigned long SWR:1; + unsigned long :3; + unsigned long DL:2; + unsigned long DE:1; + unsigned long :25; + } BIT; + } EDMR; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TR:1; + unsigned long :31; + } BIT; + } EDTRR; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RR:1; + unsigned long :31; + } BIT; + } EDRRR; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TDLAR:32; + } BIT; + } TDLAR; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RDLAR:32; + } BIT; + } RDLAR; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TYPE:4; + unsigned long PVER:1; + unsigned long :2; + unsigned long RPORT:1; + unsigned long MACE:1; + unsigned long :7; + unsigned long RFOF:1; + unsigned long RDE:1; + unsigned long FR:1; + unsigned long TFUF:1; + unsigned long TDE:1; + unsigned long TC:1; + unsigned long :2; + unsigned long RFCOF:1; + unsigned long :1; + unsigned long TABT:1; + unsigned long :3; + unsigned long TWB:1; + unsigned long :1; + } BIT; + } EESR; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long PVERIP:1; + unsigned long :2; + unsigned long RPORTIP:1; + unsigned long MACEIP:1; + unsigned long :7; + unsigned long RFOFIP:1; + unsigned long RDEIP:1; + unsigned long FRIP:1; + unsigned long TFUFIP:1; + unsigned long TDEIP:1; + unsigned long TCIP:1; + unsigned long :2; + unsigned long RFCOFIP:1; + unsigned long :1; + unsigned long TABTIP:1; + unsigned long :3; + unsigned long TWBIP:1; + unsigned long :1; + } BIT; + } EESIPR; + char wk6[4]; + char wk7[4]; + char wk8[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MFC:16; + unsigned long :16; + } BIT; + } RMFCR; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TFT:11; + unsigned long :21; + } BIT; + } TFTR; + char wk10[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RFD:5; + unsigned long :3; + unsigned long TFD:5; + unsigned long :19; + } BIT; + } FDR; + char wk11[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RNR:1; + unsigned long :31; + } BIT; + } RMCR; + char wk12[8]; + union + { + unsigned long LONG; + struct + { + unsigned long UNDER:16; + unsigned long :16; + } BIT; + } TFUCR; + union + { + unsigned long LONG; + struct + { + unsigned long OVER:16; + unsigned long :16; + } BIT; + } RFOCR; + char wk13[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RFDO:3; + unsigned long :13; + unsigned long RFFO:3; + unsigned long :13; + } BIT; + } FCFTR; + char wk14[4]; + union + { + unsigned long LONG; + struct + { + unsigned long PADR:6; + unsigned long :10; + unsigned long PADS:2; + unsigned long :14; + } BIT; + } RPADIR; + union + { + unsigned long LONG; + struct + { + unsigned long TIS:1; + unsigned long :3; + unsigned long TIM:1; + unsigned long :27; + } BIT; + } TRIMD; + char wk15[72]; + union + { + unsigned long LONG; + struct + { + unsigned long RBWAR:32; + } BIT; + } RBWAR; + union + { + unsigned long LONG; + struct + { + unsigned long RDFAR:32; + } BIT; + } RDFAR; + char wk16[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TBRAR:32; + } BIT; + } TBRAR; + union + { + unsigned long LONG; + struct + { + unsigned long TDFAR:32; + } BIT; + } TDFAR; +}; + +#define PTPEDMAC (*(volatile struct st_ptpedmac *)0xE8204400) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcan_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcan_iodefine.h new file mode 100644 index 0000000..7501596 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcan_iodefine.h @@ -0,0 +1,12211 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef RCAN_IODEFINE_H +#define RCAN_IODEFINE_H + +struct st_rcan +{ + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BRP:10; + unsigned long :6; + unsigned long TSEG1:4; + unsigned long TSEG2:3; + unsigned long :1; + unsigned long SJW:2; + unsigned long :6; + } BIT; + } RSCAN0C0CFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CHMDC:2; + unsigned char CSLPR:1; + unsigned char RTBO:1; + unsigned char :4; + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + unsigned char ALIE:1; + unsigned char TAIE:1; + unsigned char :4; + unsigned char BOM:2; + unsigned char ERRD:1; + unsigned char CTME:1; + unsigned char CTMS:2; + unsigned char :3; + unsigned char CRCT:1; + unsigned char :1; + } BIT; + } RSCAN0C0CTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CRSTSTS:1; + unsigned char CHLTSTS:1; + unsigned char CSLPSTS:1; + unsigned char EPSTS:1; + unsigned char BOSTS:1; + unsigned char TRMSTS:1; + unsigned char RECSTS:1; + unsigned char COMSTS:1; + unsigned char :8; + unsigned char REC:8; + unsigned char TEC:8; + } BIT; + } RSCAN0C0STS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BEF:1; + unsigned long EWF:1; + unsigned long EPF:1; + unsigned long BOEF:1; + unsigned long BORF:1; + unsigned long OVLF:1; + unsigned long BLF:1; + unsigned long ALF:1; + unsigned long SERR:1; + unsigned long FERR:1; + unsigned long AERR:1; + unsigned long CERR:1; + unsigned long B1ERR:1; + unsigned long B0ERR:1; + unsigned long ADERR:1; + unsigned long :1; + unsigned long CRCREG:15; + unsigned long :1; + } BIT; + } RSCAN0C0ERFL; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BRP:10; + unsigned long :6; + unsigned long TSEG1:4; + unsigned long TSEG2:3; + unsigned long :1; + unsigned long SJW:2; + unsigned long :6; + } BIT; + } RSCAN0C1CFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CHMDC:2; + unsigned char CSLPR:1; + unsigned char RTBO:1; + unsigned char :4; + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + unsigned char ALIE:1; + unsigned char TAIE:1; + unsigned char :4; + unsigned char BOM:2; + unsigned char ERRD:1; + unsigned char CTME:1; + unsigned char CTMS:2; + unsigned char :3; + unsigned char CRCT:1; + unsigned char :1; + } BIT; + } RSCAN0C1CTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CRSTSTS:1; + unsigned char CHLTSTS:1; + unsigned char CSLPSTS:1; + unsigned char EPSTS:1; + unsigned char BOSTS:1; + unsigned char TRMSTS:1; + unsigned char RECSTS:1; + unsigned char COMSTS:1; + unsigned char :8; + unsigned char REC:8; + unsigned char TEC:8; + } BIT; + } RSCAN0C1STS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BEF:1; + unsigned long EWF:1; + unsigned long EPF:1; + unsigned long BOEF:1; + unsigned long BORF:1; + unsigned long OVLF:1; + unsigned long BLF:1; + unsigned long ALF:1; + unsigned long SERR:1; + unsigned long FERR:1; + unsigned long AERR:1; + unsigned long CERR:1; + unsigned long B1ERR:1; + unsigned long B0ERR:1; + unsigned long ADERR:1; + unsigned long :1; + unsigned long CRCREG:15; + unsigned long :1; + } BIT; + } RSCAN0C1ERFL; + char wk0[100]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TPRI:1; + unsigned long DCE:1; + unsigned long DRE:1; + unsigned long MME:1; + unsigned long DCS:1; + unsigned long :2; + unsigned long TMTSCE:1; + unsigned long TSP:4; + unsigned long TSSS:1; + unsigned long TSBTCS:3; + unsigned long ITRCP:16; + } BIT; + } RSCAN0GCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char GMDC:2; + unsigned char GSLPR:1; + unsigned char :5; + unsigned char DEIE:1; + unsigned char MEIE:1; + unsigned char THLEIE:1; + unsigned char :5; + unsigned char TSRST:1; + unsigned char :7; + unsigned char :8; + } BIT; + } RSCAN0GCTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char GRSTSTS:1; + unsigned char GHLTSTS:1; + unsigned char GSLPSTS:1; + unsigned char GRAMINIT:1; + unsigned char :4; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char DEF:1; + unsigned char MES:1; + unsigned char THLES:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GERFL; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long TS:16; + unsigned long :16; + } BIT; + } RSCAN0GTSC; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char AFLPN:5; + unsigned char :3; + unsigned char AFLDAE:1; + unsigned char :7; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GAFLECTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char RNC1:8; + unsigned char RNC0:8; + } BIT; + } RSCAN0GAFLCFG0; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char NRXMB:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RMNB; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMNS0:1; + unsigned char RMNS1:1; + unsigned char RMNS2:1; + unsigned char RMNS3:1; + unsigned char RMNS4:1; + unsigned char RMNS5:1; + unsigned char RMNS6:1; + unsigned char RMNS7:1; + unsigned char RMNS8:1; + unsigned char RMNS9:1; + unsigned char RMNS10:1; + unsigned char RMNS11:1; + unsigned char RMNS12:1; + unsigned char RMNS13:1; + unsigned char RMNS14:1; + unsigned char RMNS15:1; + unsigned char RMNS16:1; + unsigned char RMNS17:1; + unsigned char RMNS18:1; + unsigned char RMNS19:1; + unsigned char RMNS20:1; + unsigned char RMNS21:1; + unsigned char RMNS22:1; + unsigned char RMNS23:1; + unsigned char RMNS24:1; + unsigned char RMNS25:1; + unsigned char RMNS26:1; + unsigned char RMNS27:1; + unsigned char RMNS28:1; + unsigned char RMNS29:1; + unsigned char RMNS30:1; + unsigned char RMNS31:1; + } BIT; + } RSCAN0RMND0; + char wk2[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC5; + char wk3[72]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS5; + char wk4[72]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR5; + char wk5[72]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0EMP:1; + unsigned char RF1EMP:1; + unsigned char RF2EMP:1; + unsigned char RF3EMP:1; + unsigned char RF4EMP:1; + unsigned char RF5EMP:1; + unsigned char RF6EMP:1; + unsigned char RF7EMP:1; + unsigned char CF0EMP:1; + unsigned char CF1EMP:1; + unsigned char CF2EMP:1; + unsigned char CF3EMP:1; + unsigned char CF4EMP:1; + unsigned char CF5EMP:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0FESTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0FLL:1; + unsigned char RF1FLL:1; + unsigned char RF2FLL:1; + unsigned char RF3FLL:1; + unsigned char RF4FLL:1; + unsigned char RF5FLL:1; + unsigned char RF6FLL:1; + unsigned char RF7FLL:1; + unsigned char CF0FLL:1; + unsigned char CF1FLL:1; + unsigned char CF2FLL:1; + unsigned char CF3FLL:1; + unsigned char CF4FLL:1; + unsigned char CF5FLL:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0FFSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0MLT:1; + unsigned char RF1MLT:1; + unsigned char RF2MLT:1; + unsigned char RF3MLT:1; + unsigned char RF4MLT:1; + unsigned char RF5MLT:1; + unsigned char RF6MLT:1; + unsigned char RF7MLT:1; + unsigned char CF0MLT:1; + unsigned char CF1MLT:1; + unsigned char CF2MLT:1; + unsigned char CF3MLT:1; + unsigned char CF4MLT:1; + unsigned char CF5MLT:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0FMSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0IF:1; + unsigned char RF1IF:1; + unsigned char RF2IF:1; + unsigned char RF3IF:1; + unsigned char RF4IF:1; + unsigned char RF5IF:1; + unsigned char RF6IF:1; + unsigned char RF7IF:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFISTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CF0RXIF:1; + unsigned char CF1RXIF:1; + unsigned char CF2RXIF:1; + unsigned char CF3RXIF:1; + unsigned char CF4RXIF:1; + unsigned char CF5RXIF:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFRISTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CF0TXIF:1; + unsigned char CF1TXIF:1; + unsigned char CF2TXIF:1; + unsigned char CF3TXIF:1; + unsigned char CF4TXIF:1; + unsigned char CF5TXIF:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFTISTS; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC0; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC2; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC3; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC4; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC5; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC6; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC7; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC8; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC9; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC10; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC11; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC12; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC13; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC14; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC15; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC16; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC17; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC18; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC19; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC20; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC21; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC22; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC23; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC24; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC25; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC26; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC27; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC28; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC29; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC30; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC31; + char wk6[96]; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS0; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS2; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS3; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS4; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS5; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS6; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS7; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS8; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS9; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS10; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS11; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS12; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS13; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS14; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS15; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS16; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS17; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS18; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS19; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS20; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS21; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS22; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS23; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS24; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS25; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS26; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS27; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS28; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS29; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS30; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS31; + char wk7[96]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTRSTS0:1; + unsigned char TMTRSTS1:1; + unsigned char TMTRSTS2:1; + unsigned char TMTRSTS3:1; + unsigned char TMTRSTS4:1; + unsigned char TMTRSTS5:1; + unsigned char TMTRSTS6:1; + unsigned char TMTRSTS7:1; + unsigned char TMTRSTS8:1; + unsigned char TMTRSTS9:1; + unsigned char TMTRSTS10:1; + unsigned char TMTRSTS11:1; + unsigned char TMTRSTS12:1; + unsigned char TMTRSTS13:1; + unsigned char TMTRSTS14:1; + unsigned char TMTRSTS15:1; + unsigned char TMTRSTS16:1; + unsigned char TMTRSTS17:1; + unsigned char TMTRSTS18:1; + unsigned char TMTRSTS19:1; + unsigned char TMTRSTS20:1; + unsigned char TMTRSTS21:1; + unsigned char TMTRSTS22:1; + unsigned char TMTRSTS23:1; + unsigned char TMTRSTS24:1; + unsigned char TMTRSTS25:1; + unsigned char TMTRSTS26:1; + unsigned char TMTRSTS27:1; + unsigned char TMTRSTS28:1; + unsigned char TMTRSTS29:1; + unsigned char TMTRSTS30:1; + unsigned char TMTRSTS31:1; + } BIT; + } RSCAN0TMTRSTS0; + char wk8[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTARSTS0:1; + unsigned char TMTARSTS1:1; + unsigned char TMTARSTS2:1; + unsigned char TMTARSTS3:1; + unsigned char TMTARSTS4:1; + unsigned char TMTARSTS5:1; + unsigned char TMTARSTS6:1; + unsigned char TMTARSTS7:1; + unsigned char TMTARSTS8:1; + unsigned char TMTARSTS9:1; + unsigned char TMTARSTS10:1; + unsigned char TMTARSTS11:1; + unsigned char TMTARSTS12:1; + unsigned char TMTARSTS13:1; + unsigned char TMTARSTS14:1; + unsigned char TMTARSTS15:1; + unsigned char TMTARSTS16:1; + unsigned char TMTARSTS17:1; + unsigned char TMTARSTS18:1; + unsigned char TMTARSTS19:1; + unsigned char TMTARSTS20:1; + unsigned char TMTARSTS21:1; + unsigned char TMTARSTS22:1; + unsigned char TMTARSTS23:1; + unsigned char TMTARSTS24:1; + unsigned char TMTARSTS25:1; + unsigned char TMTARSTS26:1; + unsigned char TMTARSTS27:1; + unsigned char TMTARSTS28:1; + unsigned char TMTARSTS29:1; + unsigned char TMTARSTS30:1; + unsigned char TMTARSTS31:1; + } BIT; + } RSCAN0TMTARSTS0; + char wk9[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTCSTS0:1; + unsigned char TMTCSTS1:1; + unsigned char TMTCSTS2:1; + unsigned char TMTCSTS3:1; + unsigned char TMTCSTS4:1; + unsigned char TMTCSTS5:1; + unsigned char TMTCSTS6:1; + unsigned char TMTCSTS7:1; + unsigned char TMTCSTS8:1; + unsigned char TMTCSTS9:1; + unsigned char TMTCSTS10:1; + unsigned char TMTCSTS11:1; + unsigned char TMTCSTS12:1; + unsigned char TMTCSTS13:1; + unsigned char TMTCSTS14:1; + unsigned char TMTCSTS15:1; + unsigned char TMTCSTS16:1; + unsigned char TMTCSTS17:1; + unsigned char TMTCSTS18:1; + unsigned char TMTCSTS19:1; + unsigned char TMTCSTS20:1; + unsigned char TMTCSTS21:1; + unsigned char TMTCSTS22:1; + unsigned char TMTCSTS23:1; + unsigned char TMTCSTS24:1; + unsigned char TMTCSTS25:1; + unsigned char TMTCSTS26:1; + unsigned char TMTCSTS27:1; + unsigned char TMTCSTS28:1; + unsigned char TMTCSTS29:1; + unsigned char TMTCSTS30:1; + unsigned char TMTCSTS31:1; + } BIT; + } RSCAN0TMTCSTS0; + char wk10[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTASTS0:1; + unsigned char TMTASTS1:1; + unsigned char TMTASTS2:1; + unsigned char TMTASTS3:1; + unsigned char TMTASTS4:1; + unsigned char TMTASTS5:1; + unsigned char TMTASTS6:1; + unsigned char TMTASTS7:1; + unsigned char TMTASTS8:1; + unsigned char TMTASTS9:1; + unsigned char TMTASTS10:1; + unsigned char TMTASTS11:1; + unsigned char TMTASTS12:1; + unsigned char TMTASTS13:1; + unsigned char TMTASTS14:1; + unsigned char TMTASTS15:1; + unsigned char TMTASTS16:1; + unsigned char TMTASTS17:1; + unsigned char TMTASTS18:1; + unsigned char TMTASTS19:1; + unsigned char TMTASTS20:1; + unsigned char TMTASTS21:1; + unsigned char TMTASTS22:1; + unsigned char TMTASTS23:1; + unsigned char TMTASTS24:1; + unsigned char TMTASTS25:1; + unsigned char TMTASTS26:1; + unsigned char TMTASTS27:1; + unsigned char TMTASTS28:1; + unsigned char TMTASTS29:1; + unsigned char TMTASTS30:1; + unsigned char TMTASTS31:1; + } BIT; + } RSCAN0TMTASTS0; + char wk11[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMIE0:1; + unsigned char TMIE1:1; + unsigned char TMIE2:1; + unsigned char TMIE3:1; + unsigned char TMIE4:1; + unsigned char TMIE5:1; + unsigned char TMIE6:1; + unsigned char TMIE7:1; + unsigned char TMIE8:1; + unsigned char TMIE9:1; + unsigned char TMIE10:1; + unsigned char TMIE11:1; + unsigned char TMIE12:1; + unsigned char TMIE13:1; + unsigned char TMIE14:1; + unsigned char TMIE15:1; + unsigned char TMIE16:1; + unsigned char TMIE17:1; + unsigned char TMIE18:1; + unsigned char TMIE19:1; + unsigned char TMIE20:1; + unsigned char TMIE21:1; + unsigned char TMIE22:1; + unsigned char TMIE23:1; + unsigned char TMIE24:1; + unsigned char TMIE25:1; + unsigned char TMIE26:1; + unsigned char TMIE27:1; + unsigned char TMIE28:1; + unsigned char TMIE29:1; + unsigned char TMIE30:1; + unsigned char TMIE31:1; + } BIT; + } RSCAN0TMIEC0; + char wk12[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQE:1; + unsigned char :7; + unsigned char TXQDC:4; + unsigned char TXQIE:1; + unsigned char TXQIM:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQE:1; + unsigned char :7; + unsigned char TXQDC:4; + unsigned char TXQIE:1; + unsigned char TXQIM:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQCC1; + char wk13[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQEMP:1; + unsigned char TXQFLL:1; + unsigned char TXQIF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQEMP:1; + unsigned char TXQFLL:1; + unsigned char TXQIF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQSTS1; + char wk14[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQPCTR1; + char wk15[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLE:1; + unsigned char :7; + unsigned char THLIE:1; + unsigned char THLIM:1; + unsigned char THLDTE:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLE:1; + unsigned char :7; + unsigned char THLIE:1; + unsigned char THLIM:1; + unsigned char THLDTE:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLCC1; + char wk16[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLEMP:1; + unsigned char THLFLL:1; + unsigned char THLELT:1; + unsigned char THLIF:1; + unsigned char :4; + unsigned char THLMC:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLEMP:1; + unsigned char THLFLL:1; + unsigned char THLELT:1; + unsigned char THLIF:1; + unsigned char :4; + unsigned char THLMC:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLSTS1; + char wk17[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLPCTR1; + char wk18[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TSIF0:1; + unsigned char TAIF0:1; + unsigned char TQIF0:1; + unsigned char CFTIF0:1; + unsigned char THIF0:1; + unsigned char :3; + unsigned char TSIF1:1; + unsigned char TAIF1:1; + unsigned char TQIF1:1; + unsigned char CFTIF1:1; + unsigned char THIF1:1; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GTINTSTS0; + char wk19[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char C0ICBCE:1; + unsigned char C1ICBCE:1; + unsigned char :6; + unsigned char :8; + unsigned char RTMPS:7; + unsigned char :1; + unsigned char :8; + } BIT; + } RSCAN0GTSTCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char ICBCTME:1; + unsigned char :1; + unsigned char RTME:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GTSTCTR; + char wk20[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char TSCCFG:2; + unsigned char :6; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GFDCFG; + char wk21[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long LOCK:16; + unsigned long :16; + } BIT; + } RSCAN0GLOCKK; + char wk22[124]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RCMC:1; + unsigned char :7; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GRMCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP0_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCAN0GAFLP1_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF0_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF1_31; + char wk23[1536]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF1_5; + char wk24[288]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF0_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF1_31; + char wk25[1536]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BT:3; + unsigned long BN:4; + unsigned long :1; + unsigned long TID:8; + unsigned long TMTS:16; + } BIT; + } RSCAN0THLACC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BT:3; + unsigned long BN:4; + unsigned long :1; + unsigned long TID:8; + unsigned long TMTS:16; + } BIT; + } RSCAN0THLACC1; + char wk26[248]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC32; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC33; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC34; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC35; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC36; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC37; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC38; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC39; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC40; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC41; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC42; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC43; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC44; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC45; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC46; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC47; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC48; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC49; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC50; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC51; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC52; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC53; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC54; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC55; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC56; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC57; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC58; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC59; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC60; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC61; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC62; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC63; +}; + +#define RCAN (*(volatile struct st_rcan *)0xE8020000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcanfd_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcanfd_iodefine.h new file mode 100644 index 0000000..b444372 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rcanfd_iodefine.h @@ -0,0 +1,20844 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef RCANFD_IODEFINE_H +#define RCANFD_IODEFINE_H + +struct st_rcanfd +{ + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long NBRP:10; + unsigned long :1; + unsigned long NSJW:5; + unsigned long NTSEG1:7; + unsigned long :1; + unsigned long NTSEG2:5; + unsigned long :3; + } BIT; + } RSCFD0CFDC0NCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CHMDC:2; + unsigned char CSLPR:1; + unsigned char RTBO:1; + unsigned char :4; + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + unsigned char ALIE:1; + unsigned char TAIE:1; + unsigned char EOCOIE:1; + unsigned char SOCOIE:1; + unsigned char TDCVFIE:1; + unsigned char :1; + unsigned char BOM:2; + unsigned char ERRD:1; + unsigned char CTME:1; + unsigned char CTMS:2; + unsigned char :3; + unsigned char CRCT:1; + unsigned char ROM:1; + } BIT; + } RSCFD0CFDC0CTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CRSTSTS:1; + unsigned char CHLTSTS:1; + unsigned char CSLPSTS:1; + unsigned char EPSTS:1; + unsigned char BOSTS:1; + unsigned char TRMSTS:1; + unsigned char RECSTS:1; + unsigned char COMSTS:1; + unsigned char ESIF:1; + unsigned char :7; + unsigned char REC:8; + unsigned char TEC:8; + } BIT; + } RSCFD0CFDC0STS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BEF:1; + unsigned long EWF:1; + unsigned long EPF:1; + unsigned long BOEF:1; + unsigned long BORF:1; + unsigned long OVLF:1; + unsigned long BLF:1; + unsigned long ALF:1; + unsigned long SERR:1; + unsigned long FERR:1; + unsigned long AERR:1; + unsigned long CERR:1; + unsigned long B1ERR:1; + unsigned long B0ERR:1; + unsigned long ADERR:1; + unsigned long :1; + unsigned long CRCREG:15; + unsigned long :1; + } BIT; + } RSCFD0CFDC0ERFL; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long NBRP:10; + unsigned long :1; + unsigned long NSJW:5; + unsigned long NTSEG1:7; + unsigned long :1; + unsigned long NTSEG2:5; + unsigned long :3; + } BIT; + } RSCFD0CFDC1NCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CHMDC:2; + unsigned char CSLPR:1; + unsigned char RTBO:1; + unsigned char :4; + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + unsigned char ALIE:1; + unsigned char TAIE:1; + unsigned char EOCOIE:1; + unsigned char SOCOIE:1; + unsigned char TDCVFIE:1; + unsigned char :1; + unsigned char BOM:2; + unsigned char ERRD:1; + unsigned char CTME:1; + unsigned char CTMS:2; + unsigned char :3; + unsigned char CRCT:1; + unsigned char ROM:1; + } BIT; + } RSCFD0CFDC1CTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CRSTSTS:1; + unsigned char CHLTSTS:1; + unsigned char CSLPSTS:1; + unsigned char EPSTS:1; + unsigned char BOSTS:1; + unsigned char TRMSTS:1; + unsigned char RECSTS:1; + unsigned char COMSTS:1; + unsigned char ESIF:1; + unsigned char :7; + unsigned char REC:8; + unsigned char TEC:8; + } BIT; + } RSCFD0CFDC1STS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BEF:1; + unsigned long EWF:1; + unsigned long EPF:1; + unsigned long BOEF:1; + unsigned long BORF:1; + unsigned long OVLF:1; + unsigned long BLF:1; + unsigned long ALF:1; + unsigned long SERR:1; + unsigned long FERR:1; + unsigned long AERR:1; + unsigned long CERR:1; + unsigned long B1ERR:1; + unsigned long B0ERR:1; + unsigned long ADERR:1; + unsigned long :1; + unsigned long CRCREG:15; + unsigned long :1; + } BIT; + } RSCFD0CFDC1ERFL; + char wk0[100]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TPRI:1; + unsigned long DCE:1; + unsigned long DRE:1; + unsigned long MME:1; + unsigned long DCS:1; + unsigned long CMPOC:1; + unsigned long :2; + unsigned long TSP:4; + unsigned long TSSS:1; + unsigned long TSBTCS:3; + unsigned long ITRCP:16; + } BIT; + } RSCFD0CFDGCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char GMDC:2; + unsigned char GSLPR:1; + unsigned char :5; + unsigned char DEIE:1; + unsigned char MEIE:1; + unsigned char THLEIE:1; + unsigned char CMPOFIE:1; + unsigned char :4; + unsigned char TSRST:1; + unsigned char :7; + unsigned char :8; + } BIT; + } RSCFD0CFDGCTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char GRSTSTS:1; + unsigned char GHLTSTS:1; + unsigned char GSLPSTS:1; + unsigned char GRAMINIT:1; + unsigned char :4; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDGSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char DEF:1; + unsigned char MES:1; + unsigned char THLES:1; + unsigned char CMPOF:1; + unsigned char :4; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDGERFL; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long TS:16; + unsigned long :16; + } BIT; + } RSCFD0CFDGTSC; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char AFLPN:5; + unsigned char :3; + unsigned char AFLDAE:1; + unsigned char :7; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDGAFLECTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char RNC1:8; + unsigned char RNC0:8; + } BIT; + } RSCFD0CFDGAFLCFG0; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char NRXMB:8; + unsigned char RMPLS:2; + unsigned char :6; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMNB; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMNS0:1; + unsigned char RMNS1:1; + unsigned char RMNS2:1; + unsigned char RMNS3:1; + unsigned char RMNS4:1; + unsigned char RMNS5:1; + unsigned char RMNS6:1; + unsigned char RMNS7:1; + unsigned char RMNS8:1; + unsigned char RMNS9:1; + unsigned char RMNS10:1; + unsigned char RMNS11:1; + unsigned char RMNS12:1; + unsigned char RMNS13:1; + unsigned char RMNS14:1; + unsigned char RMNS15:1; + unsigned char RMNS16:1; + unsigned char RMNS17:1; + unsigned char RMNS18:1; + unsigned char RMNS19:1; + unsigned char RMNS20:1; + unsigned char RMNS21:1; + unsigned char RMNS22:1; + unsigned char RMNS23:1; + unsigned char RMNS24:1; + unsigned char RMNS25:1; + unsigned char RMNS26:1; + unsigned char RMNS27:1; + unsigned char RMNS28:1; + unsigned char RMNS29:1; + unsigned char RMNS30:1; + unsigned char RMNS31:1; + } BIT; + } RSCFD0CFDRMND0; + char wk2[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :2; + unsigned char RFPLS:3; + unsigned char :1; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFCC7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFSTS7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFPCTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :1; + unsigned char CFPLS:3; + unsigned char :1; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCFD0CFDCFCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :1; + unsigned char CFPLS:3; + unsigned char :1; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCFD0CFDCFCC1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :1; + unsigned char CFPLS:3; + unsigned char :1; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCFD0CFDCFCC2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :1; + unsigned char CFPLS:3; + unsigned char :1; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCFD0CFDCFCC3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :1; + unsigned char CFPLS:3; + unsigned char :1; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCFD0CFDCFCC4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :1; + unsigned char CFPLS:3; + unsigned char :1; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCFD0CFDCFCC5; + char wk3[72]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFSTS5; + char wk4[72]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFPCTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFPCTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFPCTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFPCTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFPCTR5; + char wk5[72]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0EMP:1; + unsigned char RF1EMP:1; + unsigned char RF2EMP:1; + unsigned char RF3EMP:1; + unsigned char RF4EMP:1; + unsigned char RF5EMP:1; + unsigned char RF6EMP:1; + unsigned char RF7EMP:1; + unsigned char CF0EMP:1; + unsigned char CF1EMP:1; + unsigned char CF2EMP:1; + unsigned char CF3EMP:1; + unsigned char CF4EMP:1; + unsigned char CF5EMP:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDFESTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0FLL:1; + unsigned char RF1FLL:1; + unsigned char RF2FLL:1; + unsigned char RF3FLL:1; + unsigned char RF4FLL:1; + unsigned char RF5FLL:1; + unsigned char RF6FLL:1; + unsigned char RF7FLL:1; + unsigned char CF0FLL:1; + unsigned char CF1FLL:1; + unsigned char CF2FLL:1; + unsigned char CF3FLL:1; + unsigned char CF4FLL:1; + unsigned char CF5FLL:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDFFSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0MLT:1; + unsigned char RF1MLT:1; + unsigned char RF2MLT:1; + unsigned char RF3MLT:1; + unsigned char RF4MLT:1; + unsigned char RF5MLT:1; + unsigned char RF6MLT:1; + unsigned char RF7MLT:1; + unsigned char CF0MLT:1; + unsigned char CF1MLT:1; + unsigned char CF2MLT:1; + unsigned char CF3MLT:1; + unsigned char CF4MLT:1; + unsigned char CF5MLT:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDFMSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RF0IF:1; + unsigned char RF1IF:1; + unsigned char RF2IF:1; + unsigned char RF3IF:1; + unsigned char RF4IF:1; + unsigned char RF5IF:1; + unsigned char RF6IF:1; + unsigned char RF7IF:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFISTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CF0RXIF:1; + unsigned char CF1RXIF:1; + unsigned char CF2RXIF:1; + unsigned char CF3RXIF:1; + unsigned char CF4RXIF:1; + unsigned char CF5RXIF:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFRISTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CF0TXIF:1; + unsigned char CF1TXIF:1; + unsigned char CF2TXIF:1; + unsigned char CF3TXIF:1; + unsigned char CF4TXIF:1; + unsigned char CF5TXIF:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFTISTS; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC0; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC2; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC3; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC4; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC5; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC6; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC7; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC8; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC9; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC10; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC11; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC12; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC13; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC14; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC15; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC16; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC17; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC18; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC19; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC20; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC21; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC22; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC23; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC24; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC25; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC26; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC27; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC28; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC29; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC30; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCFD0CFDTMC31; + char wk6[96]; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS0; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS2; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS3; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS4; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS5; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS6; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS7; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS8; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS9; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS10; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS11; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS12; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS13; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS14; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS15; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS16; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS17; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS18; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS19; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS20; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS21; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS22; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS23; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS24; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS25; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS26; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS27; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS28; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS29; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS30; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCFD0CFDTMSTS31; + char wk7[96]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTRSTS0:1; + unsigned char TMTRSTS1:1; + unsigned char TMTRSTS2:1; + unsigned char TMTRSTS3:1; + unsigned char TMTRSTS4:1; + unsigned char TMTRSTS5:1; + unsigned char TMTRSTS6:1; + unsigned char TMTRSTS7:1; + unsigned char TMTRSTS8:1; + unsigned char TMTRSTS9:1; + unsigned char TMTRSTS10:1; + unsigned char TMTRSTS11:1; + unsigned char TMTRSTS12:1; + unsigned char TMTRSTS13:1; + unsigned char TMTRSTS14:1; + unsigned char TMTRSTS15:1; + unsigned char TMTRSTS16:1; + unsigned char TMTRSTS17:1; + unsigned char TMTRSTS18:1; + unsigned char TMTRSTS19:1; + unsigned char TMTRSTS20:1; + unsigned char TMTRSTS21:1; + unsigned char TMTRSTS22:1; + unsigned char TMTRSTS23:1; + unsigned char TMTRSTS24:1; + unsigned char TMTRSTS25:1; + unsigned char TMTRSTS26:1; + unsigned char TMTRSTS27:1; + unsigned char TMTRSTS28:1; + unsigned char TMTRSTS29:1; + unsigned char TMTRSTS30:1; + unsigned char TMTRSTS31:1; + } BIT; + } RSCFD0CFDTMTRSTS0; + char wk8[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTARSTS0:1; + unsigned char TMTARSTS1:1; + unsigned char TMTARSTS2:1; + unsigned char TMTARSTS3:1; + unsigned char TMTARSTS4:1; + unsigned char TMTARSTS5:1; + unsigned char TMTARSTS6:1; + unsigned char TMTARSTS7:1; + unsigned char TMTARSTS8:1; + unsigned char TMTARSTS9:1; + unsigned char TMTARSTS10:1; + unsigned char TMTARSTS11:1; + unsigned char TMTARSTS12:1; + unsigned char TMTARSTS13:1; + unsigned char TMTARSTS14:1; + unsigned char TMTARSTS15:1; + unsigned char TMTARSTS16:1; + unsigned char TMTARSTS17:1; + unsigned char TMTARSTS18:1; + unsigned char TMTARSTS19:1; + unsigned char TMTARSTS20:1; + unsigned char TMTARSTS21:1; + unsigned char TMTARSTS22:1; + unsigned char TMTARSTS23:1; + unsigned char TMTARSTS24:1; + unsigned char TMTARSTS25:1; + unsigned char TMTARSTS26:1; + unsigned char TMTARSTS27:1; + unsigned char TMTARSTS28:1; + unsigned char TMTARSTS29:1; + unsigned char TMTARSTS30:1; + unsigned char TMTARSTS31:1; + } BIT; + } RSCFD0CFDTMTARSTS0; + char wk9[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTCSTS0:1; + unsigned char TMTCSTS1:1; + unsigned char TMTCSTS2:1; + unsigned char TMTCSTS3:1; + unsigned char TMTCSTS4:1; + unsigned char TMTCSTS5:1; + unsigned char TMTCSTS6:1; + unsigned char TMTCSTS7:1; + unsigned char TMTCSTS8:1; + unsigned char TMTCSTS9:1; + unsigned char TMTCSTS10:1; + unsigned char TMTCSTS11:1; + unsigned char TMTCSTS12:1; + unsigned char TMTCSTS13:1; + unsigned char TMTCSTS14:1; + unsigned char TMTCSTS15:1; + unsigned char TMTCSTS16:1; + unsigned char TMTCSTS17:1; + unsigned char TMTCSTS18:1; + unsigned char TMTCSTS19:1; + unsigned char TMTCSTS20:1; + unsigned char TMTCSTS21:1; + unsigned char TMTCSTS22:1; + unsigned char TMTCSTS23:1; + unsigned char TMTCSTS24:1; + unsigned char TMTCSTS25:1; + unsigned char TMTCSTS26:1; + unsigned char TMTCSTS27:1; + unsigned char TMTCSTS28:1; + unsigned char TMTCSTS29:1; + unsigned char TMTCSTS30:1; + unsigned char TMTCSTS31:1; + } BIT; + } RSCFD0CFDTMTCSTS0; + char wk10[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMTASTS0:1; + unsigned char TMTASTS1:1; + unsigned char TMTASTS2:1; + unsigned char TMTASTS3:1; + unsigned char TMTASTS4:1; + unsigned char TMTASTS5:1; + unsigned char TMTASTS6:1; + unsigned char TMTASTS7:1; + unsigned char TMTASTS8:1; + unsigned char TMTASTS9:1; + unsigned char TMTASTS10:1; + unsigned char TMTASTS11:1; + unsigned char TMTASTS12:1; + unsigned char TMTASTS13:1; + unsigned char TMTASTS14:1; + unsigned char TMTASTS15:1; + unsigned char TMTASTS16:1; + unsigned char TMTASTS17:1; + unsigned char TMTASTS18:1; + unsigned char TMTASTS19:1; + unsigned char TMTASTS20:1; + unsigned char TMTASTS21:1; + unsigned char TMTASTS22:1; + unsigned char TMTASTS23:1; + unsigned char TMTASTS24:1; + unsigned char TMTASTS25:1; + unsigned char TMTASTS26:1; + unsigned char TMTASTS27:1; + unsigned char TMTASTS28:1; + unsigned char TMTASTS29:1; + unsigned char TMTASTS30:1; + unsigned char TMTASTS31:1; + } BIT; + } RSCFD0CFDTMTASTS0; + char wk11[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMIE0:1; + unsigned char TMIE1:1; + unsigned char TMIE2:1; + unsigned char TMIE3:1; + unsigned char TMIE4:1; + unsigned char TMIE5:1; + unsigned char TMIE6:1; + unsigned char TMIE7:1; + unsigned char TMIE8:1; + unsigned char TMIE9:1; + unsigned char TMIE10:1; + unsigned char TMIE11:1; + unsigned char TMIE12:1; + unsigned char TMIE13:1; + unsigned char TMIE14:1; + unsigned char TMIE15:1; + unsigned char TMIE16:1; + unsigned char TMIE17:1; + unsigned char TMIE18:1; + unsigned char TMIE19:1; + unsigned char TMIE20:1; + unsigned char TMIE21:1; + unsigned char TMIE22:1; + unsigned char TMIE23:1; + unsigned char TMIE24:1; + unsigned char TMIE25:1; + unsigned char TMIE26:1; + unsigned char TMIE27:1; + unsigned char TMIE28:1; + unsigned char TMIE29:1; + unsigned char TMIE30:1; + unsigned char TMIE31:1; + } BIT; + } RSCFD0CFDTMIEC0; + char wk12[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQE:1; + unsigned char :7; + unsigned char TXQDC:4; + unsigned char TXQIE:1; + unsigned char TXQIM:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTXQCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQE:1; + unsigned char :7; + unsigned char TXQDC:4; + unsigned char TXQIE:1; + unsigned char TXQIM:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTXQCC1; + char wk13[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQEMP:1; + unsigned char TXQFLL:1; + unsigned char TXQIF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTXQSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQEMP:1; + unsigned char TXQFLL:1; + unsigned char TXQIF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTXQSTS1; + char wk14[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTXQPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TXQPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTXQPCTR1; + char wk15[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLE:1; + unsigned char :7; + unsigned char THLIE:1; + unsigned char THLIM:1; + unsigned char THLDTE:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTHLCC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLE:1; + unsigned char :7; + unsigned char THLIE:1; + unsigned char THLIM:1; + unsigned char THLDTE:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTHLCC1; + char wk16[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLEMP:1; + unsigned char THLFLL:1; + unsigned char THLELT:1; + unsigned char THLIF:1; + unsigned char :4; + unsigned char THLMC:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTHLSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLEMP:1; + unsigned char THLFLL:1; + unsigned char THLELT:1; + unsigned char THLIF:1; + unsigned char :4; + unsigned char THLMC:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTHLSTS1; + char wk17[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTHLPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char THLPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTHLPCTR1; + char wk18[24]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TSIF0:1; + unsigned char TAIF0:1; + unsigned char TQIF0:1; + unsigned char CFTIF0:1; + unsigned char THIF0:1; + unsigned char :3; + unsigned char TSIF1:1; + unsigned char TAIF1:1; + unsigned char TQIF1:1; + unsigned char CFTIF1:1; + unsigned char THIF1:1; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDGTINTSTS0; + char wk19[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char C0ICBCE:1; + unsigned char C1ICBCE:1; + unsigned char :6; + unsigned char :8; + unsigned char RTMPS:7; + unsigned char :1; + unsigned char :8; + } BIT; + } RSCFD0CFDGTSTCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char ICBCTME:1; + unsigned char :1; + unsigned char RTME:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDGTSTCTR; + char wk20[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RPED:1; + unsigned char :7; + unsigned char TSCCFG:2; + unsigned char :6; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDGFDCFG; + char wk21[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned long LOCK:16; + unsigned long :16; + } BIT; + } RSCFD0CFDGLOCKK; + char wk22[16]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFDMAE0:1; + unsigned char RFDMAE1:1; + unsigned char RFDMAE2:1; + unsigned char RFDMAE3:1; + unsigned char RFDMAE4:1; + unsigned char RFDMAE5:1; + unsigned char RFDMAE6:1; + unsigned char RFDMAE7:1; + unsigned char CFDMAE0:1; + unsigned char CFDMAE1:1; + unsigned char CFDMAE2:1; + unsigned char CFDMAE3:1; + unsigned char CFDMAE4:1; + unsigned char CFDMAE5:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCDTCT; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFDMASTS0:1; + unsigned char RFDMASTS1:1; + unsigned char RFDMASTS2:1; + unsigned char RFDMASTS3:1; + unsigned char RFDMASTS4:1; + unsigned char RFDMASTS5:1; + unsigned char RFDMASTS6:1; + unsigned char RFDMASTS7:1; + unsigned char CFDMASTS0:1; + unsigned char CFDMASTS1:1; + unsigned char CFDMASTS2:1; + unsigned char CFDMASTS3:1; + unsigned char CFDMASTS4:1; + unsigned char CFDMASTS5:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCDTSTS; + char wk23[100]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RCMC:1; + unsigned char :7; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDGRMCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char DBRP:8; + unsigned char :8; + unsigned char DTSEG1:4; + unsigned char DTSEG2:3; + unsigned char :1; + unsigned char DSJW:3; + unsigned char :5; + } BIT; + } RSCFD0CFDC0DCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char EOCCFG:3; + unsigned char :5; + unsigned char TDCOC:1; + unsigned char TDCE:1; + unsigned char ESIC:1; + unsigned char :5; + unsigned char TDCO:7; + unsigned char :1; + unsigned char GWEN:1; + unsigned char GWFDF:1; + unsigned char GWBRS:1; + unsigned char TMME:1; + unsigned char FDOE:1; + unsigned char REFE:1; + unsigned char :2; + } BIT; + } RSCFD0CFDC0FDCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char EOCCLR:1; + unsigned char SOCCLR:1; + unsigned char :6; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDC0FDCTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TDCR:7; + unsigned char TDCVF:1; + unsigned char EOCO:1; + unsigned char SOCO:1; + unsigned char :6; + unsigned char EOC:8; + unsigned char SOC:8; + } BIT; + } RSCFD0CFDC0FDSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CRCREG:21; + unsigned long :3; + unsigned long SCNT:4; + unsigned long :4; + } BIT; + } RSCFD0CFDC0FDCRC; + char wk24[12]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char DBRP:8; + unsigned char :8; + unsigned char DTSEG1:4; + unsigned char DTSEG2:3; + unsigned char :1; + unsigned char DSJW:3; + unsigned char :5; + } BIT; + } RSCFD0CFDC1DCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char EOCCFG:3; + unsigned char :5; + unsigned char TDCOC:1; + unsigned char TDCE:1; + unsigned char ESIC:1; + unsigned char :5; + unsigned char TDCO:7; + unsigned char :1; + unsigned char GWEN:1; + unsigned char GWFDF:1; + unsigned char GWBRS:1; + unsigned char TMME:1; + unsigned char FDOE:1; + unsigned char REFE:1; + unsigned char :2; + } BIT; + } RSCFD0CFDC1FDCFG; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char EOCCLR:1; + unsigned char SOCCLR:1; + unsigned char :6; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDC1FDCTR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TDCR:7; + unsigned char TDCVF:1; + unsigned char EOCO:1; + unsigned char SOCO:1; + unsigned char :6; + unsigned char EOC:8; + unsigned char SOC:8; + } BIT; + } RSCFD0CFDC1FDSTS; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CRCREG:21; + unsigned long :3; + unsigned long SCNT:4; + unsigned long :4; + } BIT; + } RSCFD0CFDC1FDCRC; + char wk25[2764]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCFD0CFDGAFLID15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCFD0CFDGAFLM15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCFD0CFDGAFLP0_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long GAFLFDP:14; + unsigned long :18; + } BIT; + } RSCFD0CFDGAFLP1_15; + char wk26[3840]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCFD0CFDRMID31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCFD0CFDRMPTR31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RMESI:1; + unsigned char RMBRS:1; + unsigned char RMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRMFDSTS31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCFD0CFDRMDF0_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCFD0CFDRMDF1_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB8; + unsigned char RMDB9; + unsigned char RMDB10; + unsigned char RMDB11; + } BYTE; + } RSCFD0CFDRMDF2_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB12; + unsigned char RMDB13; + unsigned char RMDB14; + unsigned char RMDB15; + } BYTE; + } RSCFD0CFDRMDF3_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RMDB16; + unsigned char RMDB17; + unsigned char RMDB18; + unsigned char RMDB19; + } BYTE; + } RSCFD0CFDRMDF4_31; + char wk27[3072]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_0; + char wk28[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_1; + char wk29[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_2; + char wk30[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_3; + char wk31[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_4; + char wk32[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_5; + char wk33[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_6; + char wk34[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCFD0CFDRFID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCFD0CFDRFPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char RFESI:1; + unsigned char RFBRS:1; + unsigned char RFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDRFFDSTS7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCFD0CFDRFDF0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCFD0CFDRFDF1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB8; + unsigned char RFDB9; + unsigned char RFDB10; + unsigned char RFDB11; + } BYTE; + } RSCFD0CFDRFDF2_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB12; + unsigned char RFDB13; + unsigned char RFDB14; + unsigned char RFDB15; + } BYTE; + } RSCFD0CFDRFDF3_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB16; + unsigned char RFDB17; + unsigned char RFDB18; + unsigned char RFDB19; + } BYTE; + } RSCFD0CFDRFDF4_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB20; + unsigned char RFDB21; + unsigned char RFDB22; + unsigned char RFDB23; + } BYTE; + } RSCFD0CFDRFDF5_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB24; + unsigned char RFDB25; + unsigned char RFDB26; + unsigned char RFDB27; + } BYTE; + } RSCFD0CFDRFDF6_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB28; + unsigned char RFDB29; + unsigned char RFDB30; + unsigned char RFDB31; + } BYTE; + } RSCFD0CFDRFDF7_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB32; + unsigned char RFDB33; + unsigned char RFDB34; + unsigned char RFDB35; + } BYTE; + } RSCFD0CFDRFDF8_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB36; + unsigned char RFDB37; + unsigned char RFDB38; + unsigned char RFDB39; + } BYTE; + } RSCFD0CFDRFDF9_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB40; + unsigned char RFDB41; + unsigned char RFDB42; + unsigned char RFDB43; + } BYTE; + } RSCFD0CFDRFDF10_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB44; + unsigned char RFDB45; + unsigned char RFDB46; + unsigned char RFDB47; + } BYTE; + } RSCFD0CFDRFDF11_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB48; + unsigned char RFDB49; + unsigned char RFDB50; + unsigned char RFDB51; + } BYTE; + } RSCFD0CFDRFDF12_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB52; + unsigned char RFDB53; + unsigned char RFDB54; + unsigned char RFDB55; + } BYTE; + } RSCFD0CFDRFDF13_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB56; + unsigned char RFDB57; + unsigned char RFDB58; + unsigned char RFDB59; + } BYTE; + } RSCFD0CFDRFDF14_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char RFDB60; + unsigned char RFDB61; + unsigned char RFDB62; + unsigned char RFDB63; + } BYTE; + } RSCFD0CFDRFDF15_7; + char wk35[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCFD0CFDCFID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCFD0CFDCFPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFESI:1; + unsigned char CFBRS:1; + unsigned char CFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFFDCSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCFD0CFDCFDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCFD0CFDCFDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB8; + unsigned char CFDB9; + unsigned char CFDB10; + unsigned char CFDB11; + } BYTE; + } RSCFD0CFDCFDF2_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB12; + unsigned char CFDB13; + unsigned char CFDB14; + unsigned char CFDB15; + } BYTE; + } RSCFD0CFDCFDF3_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB16; + unsigned char CFDB17; + unsigned char CFDB18; + unsigned char CFDB19; + } BYTE; + } RSCFD0CFDCFDF4_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB20; + unsigned char CFDB21; + unsigned char CFDB22; + unsigned char CFDB23; + } BYTE; + } RSCFD0CFDCFDF5_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB24; + unsigned char CFDB25; + unsigned char CFDB26; + unsigned char CFDB27; + } BYTE; + } RSCFD0CFDCFDF6_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB28; + unsigned char CFDB29; + unsigned char CFDB30; + unsigned char CFDB31; + } BYTE; + } RSCFD0CFDCFDF7_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB32; + unsigned char CFDB33; + unsigned char CFDB34; + unsigned char CFDB35; + } BYTE; + } RSCFD0CFDCFDF8_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB36; + unsigned char CFDB37; + unsigned char CFDB38; + unsigned char CFDB39; + } BYTE; + } RSCFD0CFDCFDF9_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB40; + unsigned char CFDB41; + unsigned char CFDB42; + unsigned char CFDB43; + } BYTE; + } RSCFD0CFDCFDF10_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB44; + unsigned char CFDB45; + unsigned char CFDB46; + unsigned char CFDB47; + } BYTE; + } RSCFD0CFDCFDF11_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB48; + unsigned char CFDB49; + unsigned char CFDB50; + unsigned char CFDB51; + } BYTE; + } RSCFD0CFDCFDF12_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB52; + unsigned char CFDB53; + unsigned char CFDB54; + unsigned char CFDB55; + } BYTE; + } RSCFD0CFDCFDF13_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB56; + unsigned char CFDB57; + unsigned char CFDB58; + unsigned char CFDB59; + } BYTE; + } RSCFD0CFDCFDF14_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB60; + unsigned char CFDB61; + unsigned char CFDB62; + unsigned char CFDB63; + } BYTE; + } RSCFD0CFDCFDF15_0; + char wk36[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCFD0CFDCFID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCFD0CFDCFPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFESI:1; + unsigned char CFBRS:1; + unsigned char CFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFFDCSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCFD0CFDCFDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCFD0CFDCFDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB8; + unsigned char CFDB9; + unsigned char CFDB10; + unsigned char CFDB11; + } BYTE; + } RSCFD0CFDCFDF2_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB12; + unsigned char CFDB13; + unsigned char CFDB14; + unsigned char CFDB15; + } BYTE; + } RSCFD0CFDCFDF3_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB16; + unsigned char CFDB17; + unsigned char CFDB18; + unsigned char CFDB19; + } BYTE; + } RSCFD0CFDCFDF4_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB20; + unsigned char CFDB21; + unsigned char CFDB22; + unsigned char CFDB23; + } BYTE; + } RSCFD0CFDCFDF5_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB24; + unsigned char CFDB25; + unsigned char CFDB26; + unsigned char CFDB27; + } BYTE; + } RSCFD0CFDCFDF6_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB28; + unsigned char CFDB29; + unsigned char CFDB30; + unsigned char CFDB31; + } BYTE; + } RSCFD0CFDCFDF7_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB32; + unsigned char CFDB33; + unsigned char CFDB34; + unsigned char CFDB35; + } BYTE; + } RSCFD0CFDCFDF8_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB36; + unsigned char CFDB37; + unsigned char CFDB38; + unsigned char CFDB39; + } BYTE; + } RSCFD0CFDCFDF9_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB40; + unsigned char CFDB41; + unsigned char CFDB42; + unsigned char CFDB43; + } BYTE; + } RSCFD0CFDCFDF10_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB44; + unsigned char CFDB45; + unsigned char CFDB46; + unsigned char CFDB47; + } BYTE; + } RSCFD0CFDCFDF11_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB48; + unsigned char CFDB49; + unsigned char CFDB50; + unsigned char CFDB51; + } BYTE; + } RSCFD0CFDCFDF12_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB52; + unsigned char CFDB53; + unsigned char CFDB54; + unsigned char CFDB55; + } BYTE; + } RSCFD0CFDCFDF13_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB56; + unsigned char CFDB57; + unsigned char CFDB58; + unsigned char CFDB59; + } BYTE; + } RSCFD0CFDCFDF14_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB60; + unsigned char CFDB61; + unsigned char CFDB62; + unsigned char CFDB63; + } BYTE; + } RSCFD0CFDCFDF15_1; + char wk37[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCFD0CFDCFID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCFD0CFDCFPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFESI:1; + unsigned char CFBRS:1; + unsigned char CFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFFDCSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCFD0CFDCFDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCFD0CFDCFDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB8; + unsigned char CFDB9; + unsigned char CFDB10; + unsigned char CFDB11; + } BYTE; + } RSCFD0CFDCFDF2_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB12; + unsigned char CFDB13; + unsigned char CFDB14; + unsigned char CFDB15; + } BYTE; + } RSCFD0CFDCFDF3_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB16; + unsigned char CFDB17; + unsigned char CFDB18; + unsigned char CFDB19; + } BYTE; + } RSCFD0CFDCFDF4_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB20; + unsigned char CFDB21; + unsigned char CFDB22; + unsigned char CFDB23; + } BYTE; + } RSCFD0CFDCFDF5_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB24; + unsigned char CFDB25; + unsigned char CFDB26; + unsigned char CFDB27; + } BYTE; + } RSCFD0CFDCFDF6_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB28; + unsigned char CFDB29; + unsigned char CFDB30; + unsigned char CFDB31; + } BYTE; + } RSCFD0CFDCFDF7_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB32; + unsigned char CFDB33; + unsigned char CFDB34; + unsigned char CFDB35; + } BYTE; + } RSCFD0CFDCFDF8_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB36; + unsigned char CFDB37; + unsigned char CFDB38; + unsigned char CFDB39; + } BYTE; + } RSCFD0CFDCFDF9_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB40; + unsigned char CFDB41; + unsigned char CFDB42; + unsigned char CFDB43; + } BYTE; + } RSCFD0CFDCFDF10_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB44; + unsigned char CFDB45; + unsigned char CFDB46; + unsigned char CFDB47; + } BYTE; + } RSCFD0CFDCFDF11_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB48; + unsigned char CFDB49; + unsigned char CFDB50; + unsigned char CFDB51; + } BYTE; + } RSCFD0CFDCFDF12_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB52; + unsigned char CFDB53; + unsigned char CFDB54; + unsigned char CFDB55; + } BYTE; + } RSCFD0CFDCFDF13_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB56; + unsigned char CFDB57; + unsigned char CFDB58; + unsigned char CFDB59; + } BYTE; + } RSCFD0CFDCFDF14_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB60; + unsigned char CFDB61; + unsigned char CFDB62; + unsigned char CFDB63; + } BYTE; + } RSCFD0CFDCFDF15_2; + char wk38[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCFD0CFDCFID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCFD0CFDCFPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFESI:1; + unsigned char CFBRS:1; + unsigned char CFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFFDCSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCFD0CFDCFDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCFD0CFDCFDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB8; + unsigned char CFDB9; + unsigned char CFDB10; + unsigned char CFDB11; + } BYTE; + } RSCFD0CFDCFDF2_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB12; + unsigned char CFDB13; + unsigned char CFDB14; + unsigned char CFDB15; + } BYTE; + } RSCFD0CFDCFDF3_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB16; + unsigned char CFDB17; + unsigned char CFDB18; + unsigned char CFDB19; + } BYTE; + } RSCFD0CFDCFDF4_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB20; + unsigned char CFDB21; + unsigned char CFDB22; + unsigned char CFDB23; + } BYTE; + } RSCFD0CFDCFDF5_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB24; + unsigned char CFDB25; + unsigned char CFDB26; + unsigned char CFDB27; + } BYTE; + } RSCFD0CFDCFDF6_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB28; + unsigned char CFDB29; + unsigned char CFDB30; + unsigned char CFDB31; + } BYTE; + } RSCFD0CFDCFDF7_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB32; + unsigned char CFDB33; + unsigned char CFDB34; + unsigned char CFDB35; + } BYTE; + } RSCFD0CFDCFDF8_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB36; + unsigned char CFDB37; + unsigned char CFDB38; + unsigned char CFDB39; + } BYTE; + } RSCFD0CFDCFDF9_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB40; + unsigned char CFDB41; + unsigned char CFDB42; + unsigned char CFDB43; + } BYTE; + } RSCFD0CFDCFDF10_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB44; + unsigned char CFDB45; + unsigned char CFDB46; + unsigned char CFDB47; + } BYTE; + } RSCFD0CFDCFDF11_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB48; + unsigned char CFDB49; + unsigned char CFDB50; + unsigned char CFDB51; + } BYTE; + } RSCFD0CFDCFDF12_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB52; + unsigned char CFDB53; + unsigned char CFDB54; + unsigned char CFDB55; + } BYTE; + } RSCFD0CFDCFDF13_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB56; + unsigned char CFDB57; + unsigned char CFDB58; + unsigned char CFDB59; + } BYTE; + } RSCFD0CFDCFDF14_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB60; + unsigned char CFDB61; + unsigned char CFDB62; + unsigned char CFDB63; + } BYTE; + } RSCFD0CFDCFDF15_3; + char wk39[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCFD0CFDCFID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCFD0CFDCFPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFESI:1; + unsigned char CFBRS:1; + unsigned char CFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFFDCSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCFD0CFDCFDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCFD0CFDCFDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB8; + unsigned char CFDB9; + unsigned char CFDB10; + unsigned char CFDB11; + } BYTE; + } RSCFD0CFDCFDF2_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB12; + unsigned char CFDB13; + unsigned char CFDB14; + unsigned char CFDB15; + } BYTE; + } RSCFD0CFDCFDF3_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB16; + unsigned char CFDB17; + unsigned char CFDB18; + unsigned char CFDB19; + } BYTE; + } RSCFD0CFDCFDF4_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB20; + unsigned char CFDB21; + unsigned char CFDB22; + unsigned char CFDB23; + } BYTE; + } RSCFD0CFDCFDF5_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB24; + unsigned char CFDB25; + unsigned char CFDB26; + unsigned char CFDB27; + } BYTE; + } RSCFD0CFDCFDF6_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB28; + unsigned char CFDB29; + unsigned char CFDB30; + unsigned char CFDB31; + } BYTE; + } RSCFD0CFDCFDF7_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB32; + unsigned char CFDB33; + unsigned char CFDB34; + unsigned char CFDB35; + } BYTE; + } RSCFD0CFDCFDF8_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB36; + unsigned char CFDB37; + unsigned char CFDB38; + unsigned char CFDB39; + } BYTE; + } RSCFD0CFDCFDF9_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB40; + unsigned char CFDB41; + unsigned char CFDB42; + unsigned char CFDB43; + } BYTE; + } RSCFD0CFDCFDF10_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB44; + unsigned char CFDB45; + unsigned char CFDB46; + unsigned char CFDB47; + } BYTE; + } RSCFD0CFDCFDF11_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB48; + unsigned char CFDB49; + unsigned char CFDB50; + unsigned char CFDB51; + } BYTE; + } RSCFD0CFDCFDF12_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB52; + unsigned char CFDB53; + unsigned char CFDB54; + unsigned char CFDB55; + } BYTE; + } RSCFD0CFDCFDF13_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB56; + unsigned char CFDB57; + unsigned char CFDB58; + unsigned char CFDB59; + } BYTE; + } RSCFD0CFDCFDF14_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB60; + unsigned char CFDB61; + unsigned char CFDB62; + unsigned char CFDB63; + } BYTE; + } RSCFD0CFDCFDF15_4; + char wk40[52]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCFD0CFDCFID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCFD0CFDCFPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char CFESI:1; + unsigned char CFBRS:1; + unsigned char CFFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDCFFDCSTS5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCFD0CFDCFDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCFD0CFDCFDF1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB8; + unsigned char CFDB9; + unsigned char CFDB10; + unsigned char CFDB11; + } BYTE; + } RSCFD0CFDCFDF2_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB12; + unsigned char CFDB13; + unsigned char CFDB14; + unsigned char CFDB15; + } BYTE; + } RSCFD0CFDCFDF3_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB16; + unsigned char CFDB17; + unsigned char CFDB18; + unsigned char CFDB19; + } BYTE; + } RSCFD0CFDCFDF4_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB20; + unsigned char CFDB21; + unsigned char CFDB22; + unsigned char CFDB23; + } BYTE; + } RSCFD0CFDCFDF5_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB24; + unsigned char CFDB25; + unsigned char CFDB26; + unsigned char CFDB27; + } BYTE; + } RSCFD0CFDCFDF6_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB28; + unsigned char CFDB29; + unsigned char CFDB30; + unsigned char CFDB31; + } BYTE; + } RSCFD0CFDCFDF7_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB32; + unsigned char CFDB33; + unsigned char CFDB34; + unsigned char CFDB35; + } BYTE; + } RSCFD0CFDCFDF8_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB36; + unsigned char CFDB37; + unsigned char CFDB38; + unsigned char CFDB39; + } BYTE; + } RSCFD0CFDCFDF9_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB40; + unsigned char CFDB41; + unsigned char CFDB42; + unsigned char CFDB43; + } BYTE; + } RSCFD0CFDCFDF10_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB44; + unsigned char CFDB45; + unsigned char CFDB46; + unsigned char CFDB47; + } BYTE; + } RSCFD0CFDCFDF11_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB48; + unsigned char CFDB49; + unsigned char CFDB50; + unsigned char CFDB51; + } BYTE; + } RSCFD0CFDCFDF12_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB52; + unsigned char CFDB53; + unsigned char CFDB54; + unsigned char CFDB55; + } BYTE; + } RSCFD0CFDCFDF13_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB56; + unsigned char CFDB57; + unsigned char CFDB58; + unsigned char CFDB59; + } BYTE; + } RSCFD0CFDCFDF14_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char CFDB60; + unsigned char CFDB61; + unsigned char CFDB62; + unsigned char CFDB63; + } BYTE; + } RSCFD0CFDCFDF15_5; + char wk41[2356]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCFD0CFDTMID31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCFD0CFDTMPTR31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMESI:1; + unsigned char TMBRS:1; + unsigned char TMFDF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCFD0CFDTMFDCTR31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCFD0CFDTMDF0_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCFD0CFDTMDF1_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB8; + unsigned char TMDB9; + unsigned char TMDB10; + unsigned char TMDB11; + } BYTE; + } RSCFD0CFDTMDF2_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB12; + unsigned char TMDB13; + unsigned char TMDB14; + unsigned char TMDB15; + } BYTE; + } RSCFD0CFDTMDF3_31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char TMDB16; + unsigned char TMDB17; + unsigned char TMDB18; + unsigned char TMDB19; + } BYTE; + } RSCFD0CFDTMDF4_31; + char wk42[7168]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BT:3; + unsigned long BN:4; + unsigned long :1; + unsigned long TID:8; + unsigned long TMTS:16; + } BIT; + } RSCFD0CFDTHLACC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long BT:3; + unsigned long BN:4; + unsigned long :1; + unsigned long TID:8; + unsigned long TMTS:16; + } BIT; + } RSCFD0CFDTHLACC1; + char wk43[1016]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC4; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC5; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC6; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC7; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC8; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC9; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC10; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC11; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC12; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC13; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC14; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC15; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC16; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC17; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC18; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC19; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC20; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC21; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC22; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC23; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC24; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC25; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC26; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC27; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC28; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC29; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC30; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC31; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC32; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC33; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC34; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC35; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC36; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC37; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC38; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC39; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC40; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC41; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC42; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC43; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC44; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC45; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC46; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC47; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC48; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC49; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC50; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC51; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC52; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC53; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC54; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC55; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC56; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC57; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC58; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC59; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC60; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC61; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC62; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCFD0CFDRPGACC63; +}; + +#define RCANFD (*(volatile struct st_rcanfd *)0xE8020000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/riic_iodefine.h new file mode 100644 index 0000000..0980291 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/riic_iodefine.h @@ -0,0 +1,514 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef RIIC_IODEFINE_H +#define RIIC_IODEFINE_H + +struct st_riic +{ + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char SDAI:1; + unsigned char SCLI:1; + unsigned char SDAO:1; + unsigned char SCLO:1; + unsigned char SOWP:1; + unsigned char CLO:1; + unsigned char IICRST:1; + unsigned char ICE:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICCR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char :1; + unsigned char ST:1; + unsigned char RS:1; + unsigned char SP:1; + unsigned char :1; + unsigned char TRS:1; + unsigned char MST:1; + unsigned char BBSY:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICCR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char BC:3; + unsigned char BCWP:1; + unsigned char CKS:3; + unsigned char :1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICMR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMOS:1; + unsigned char TMOL:1; + unsigned char TMOH:1; + unsigned char :1; + unsigned char SDDL:3; + unsigned char DLCS:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICMR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char NF:2; + unsigned char ACKBR:1; + unsigned char ACKBT:1; + unsigned char ACKWP:1; + unsigned char RDRFS:1; + unsigned char WAIT:1; + unsigned char SMBE:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICMR3; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMOE:1; + unsigned char MALE:1; + unsigned char NALE:1; + unsigned char SALE:1; + unsigned char NACKE:1; + unsigned char NFE:1; + unsigned char SCLE:1; + unsigned char FMPE:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICFER; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char SAR0:1; + unsigned char SAR1:1; + unsigned char SAR2:1; + unsigned char GCE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char HOAE:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICSER; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMOIE:1; + unsigned char ALIE:1; + unsigned char STIE:1; + unsigned char SPIE:1; + unsigned char NAKIE:1; + unsigned char RIE:1; + unsigned char TEIE:1; + unsigned char TIE:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICIER; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char AAS0:1; + unsigned char AAS1:1; + unsigned char AAS2:1; + unsigned char GCA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char HOA:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICSR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char TMOF:1; + unsigned char AL:1; + unsigned char START:1; + unsigned char STOP:1; + unsigned char NACKF:1; + unsigned char RDRF:1; + unsigned char TEND:1; + unsigned char TDRE:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICSR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long SVA0:1; + unsigned long SVA:9; + unsigned long :5; + unsigned long FS0:1; + unsigned long :16; + } BIT; + } ICSAR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long SVA0:1; + unsigned long SVA:9; + unsigned long :5; + unsigned long FS1:1; + unsigned long :16; + } BIT; + } ICSAR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long SVA0:1; + unsigned long SVA:9; + unsigned long :5; + unsigned long FS2:1; + unsigned long :16; + } BIT; + } ICSAR2; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char BRL:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICBRL; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char BRH:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICBRH; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char DRT:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICDRT; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char DRR:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } ICDRR; +}; + +#define RIIC30 (*(volatile struct st_riic *)0xE803A000) +#define RIIC31 (*(volatile struct st_riic *)0xE803A400) +#define RIIC32 (*(volatile struct st_riic *)0xE803A800) +#define RIIC33 (*(volatile struct st_riic *)0xE803AC00) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rspi_iodefine.h new file mode 100644 index 0000000..d46f7f5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rspi_iodefine.h @@ -0,0 +1,343 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef RSPI_IODEFINE_H +#define RSPI_IODEFINE_H + +struct st_rspi +{ + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char MODFEN:1; + unsigned char MSTR:1; + unsigned char SPEIE:1; + unsigned char SPTIE:1; + unsigned char SPE:1; + unsigned char SPRIE:1; + } BIT; + } SPCR; + union + { + unsigned char BYTE; + struct + { + unsigned char SSL0P:1; + unsigned char :7; + } BIT; + } SSLP; + union + { + unsigned char BYTE; + struct + { + unsigned char SPLP:1; + unsigned char :3; + unsigned char MOIFV:1; + unsigned char MOIFE:1; + unsigned char :2; + } BIT; + } SPPCR; + union + { + unsigned char BYTE; + struct + { + unsigned char OVRF:1; + unsigned char :1; + unsigned char MODF:1; + unsigned char :2; + unsigned char SPTEF:1; + unsigned char TEND:1; + unsigned char SPRF:1; + } BIT; + } SPSR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned char SPD0:1; + unsigned char SPD1:1; + unsigned char SPD2:1; + unsigned char SPD3:1; + unsigned char SPD4:1; + unsigned char SPD5:1; + unsigned char SPD6:1; + unsigned char SPD7:1; + unsigned char SPD8:1; + unsigned char SPD9:1; + unsigned char SPD10:1; + unsigned char SPD11:1; + unsigned char SPD12:1; + unsigned char SPD13:1; + unsigned char SPD14:1; + unsigned char SPD15:1; + unsigned char SPD16:1; + unsigned char SPD17:1; + unsigned char SPD18:1; + unsigned char SPD19:1; + unsigned char SPD20:1; + unsigned char SPD21:1; + unsigned char SPD22:1; + unsigned char SPD23:1; + unsigned char SPD24:1; + unsigned char SPD25:1; + unsigned char SPD26:1; + unsigned char SPD27:1; + unsigned char SPD28:1; + unsigned char SPD29:1; + unsigned char SPD30:1; + unsigned char SPD31:1; + } BIT; + } SPDR; + union + { + unsigned char BYTE; + struct + { + unsigned char SPSLN0:1; + unsigned char SPSLN1:1; + unsigned char :6; + } BIT; + } SPSCR; + union + { + unsigned char BYTE; + struct + { + unsigned char SPCP0:1; + unsigned char SPCP1:1; + unsigned char :6; + } BIT; + } SPSSR; + union + { + unsigned char BYTE; + struct + { + unsigned char SPR0:1; + unsigned char SPR1:1; + unsigned char SPR2:1; + unsigned char SPR3:1; + unsigned char SPR4:1; + unsigned char SPR5:1; + unsigned char SPR6:1; + unsigned char SPR7:1; + } BIT; + } SPBR; + union + { + unsigned char BYTE; + struct + { + unsigned char :5; + unsigned char SPLW0:1; + unsigned char SPLW1:1; + unsigned char TXDMY:1; + } BIT; + } SPDCR; + union + { + unsigned char BYTE; + struct + { + unsigned char SCKDL0:1; + unsigned char SCKDL1:1; + unsigned char SCKDL2:1; + unsigned char :5; + } BIT; + } SPCKD; + union + { + unsigned char BYTE; + struct + { + unsigned char SLNDL0:1; + unsigned char SLNDL1:1; + unsigned char SLNDL2:1; + unsigned char :5; + } BIT; + } SSLND; + union + { + unsigned char BYTE; + struct + { + unsigned char SPNDL0:1; + unsigned char SPNDL1:1; + unsigned char SPNDL2:1; + unsigned char :5; + } BIT; + } SPND; + char wk0[1]; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV0:1; + unsigned short BRDV1:1; + unsigned short :3; + unsigned short SSLKP:1; + unsigned short SPB0:1; + unsigned short SPB1:1; + unsigned short SPB2:1; + unsigned short SPB3:1; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD0; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV0:1; + unsigned short BRDV1:1; + unsigned short :3; + unsigned short SSLKP:1; + unsigned short SPB0:1; + unsigned short SPB1:1; + unsigned short SPB2:1; + unsigned short SPB3:1; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD1; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV0:1; + unsigned short BRDV1:1; + unsigned short :3; + unsigned short SSLKP:1; + unsigned short SPB0:1; + unsigned short SPB1:1; + unsigned short SPB2:1; + unsigned short SPB3:1; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD2; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV0:1; + unsigned short BRDV1:1; + unsigned short :3; + unsigned short SSLKP:1; + unsigned short SPB0:1; + unsigned short SPB1:1; + unsigned short SPB2:1; + unsigned short SPB3:1; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD3; + char wk1[8]; + union + { + unsigned char BYTE; + struct + { + unsigned char RXTRG:3; + unsigned char :1; + unsigned char TXTRG:2; + unsigned char RXRST:1; + unsigned char TXRST:1; + } BIT; + } SPBFCR; + char wk2[1]; + union + { + unsigned short WORD; + struct + { + unsigned short R:6; + unsigned short :2; + unsigned short T:4; + unsigned short :4; + } BIT; + } SPBFDR; +}; + +#define RSPI0 (*(volatile struct st_rspi *)0xE800C800) +#define RSPI1 (*(volatile struct st_rspi *)0xE800D000) +#define RSPI2 (*(volatile struct st_rspi *)0xE800D800) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rtc_iodefine.h new file mode 100644 index 0000000..4f71731 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/rtc_iodefine.h @@ -0,0 +1,650 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef RTC_IODEFINE_H +#define RTC_IODEFINE_H + +struct st_rtc +{ + union + { + unsigned char BYTE; + struct + { + unsigned char F64HZ:1; + unsigned char F32HZ:1; + unsigned char F16HZ:1; + unsigned char F8HZ:1; + unsigned char F4HZ:1; + unsigned char F2HZ:1; + unsigned char F1HZ:1; + unsigned char :1; + } BIT; + } R64CNT; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char SEC1:4; + unsigned char SEC10:3; + unsigned char :1; + } BIT; + } RSECCNT; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MIN1:4; + unsigned char MIN10:3; + unsigned char :1; + } BIT; + } RMINCNT; + char wk2[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char HR1:4; + unsigned char HR10:2; + unsigned char PM:1; + unsigned char :1; + } BIT; + } RHRCNT; + char wk3[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char DAYW:3; + unsigned char :5; + } BIT; + } RWKCNT; + char wk4[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char DATE1:4; + unsigned char DATE10:2; + unsigned char :2; + } BIT; + } RDAYCNT; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MON1:4; + unsigned char MON10:1; + unsigned char :3; + } BIT; + } RMONCNT; + char wk6[1]; + union + { + unsigned short WORD; + struct + { + unsigned short YR1:4; + unsigned short YR10:4; + unsigned short :8; + } BIT; + } RYRCNT; + union + { + unsigned char BYTE; + struct + { + unsigned char SEC1:4; + unsigned char SEC10:3; + unsigned char ENB:1; + } BIT; + } RSECAR; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MIN1:4; + unsigned char MIN10:3; + unsigned char ENB:1; + } BIT; + } RMINAR; + char wk8[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char HR1:4; + unsigned char HR10:2; + unsigned char PM:1; + unsigned char ENB:1; + } BIT; + } RHRAR; + char wk9[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char DAYW:3; + unsigned char :4; + unsigned char ENB:1; + } BIT; + } RWKAR; + char wk10[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char DATE1:4; + unsigned char DATE10:2; + unsigned char :1; + unsigned char ENB:1; + } BIT; + } RDAYAR; + char wk11[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MON1:4; + unsigned char MON10:1; + unsigned char :2; + unsigned char ENB:1; + } BIT; + } RMONAR; + char wk12[1]; + union + { + unsigned short WORD; + struct + { + unsigned short YR1:4; + unsigned short YR10:4; + unsigned short :8; + } BIT; + } RYRAR; + union + { + unsigned char BYTE; + struct + { + unsigned char :7; + unsigned char ENB:1; + } BIT; + } RYRAREN; + char wk13[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char AF:1; + unsigned char CF:1; + unsigned char PF:1; + unsigned char :5; + } BIT; + } RSR; + char wk14[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char AIE:1; + unsigned char CIE:1; + unsigned char PIE:1; + unsigned char :1; + unsigned char PES:4; + } BIT; + } RCR1; + char wk15[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char START:1; + unsigned char RESET:1; + unsigned char ADJ30:1; + unsigned char :1; + unsigned char AADJE:1; + unsigned char AADJP:1; + unsigned char HR24:1; + unsigned char CNTMD:1; + } BIT; + } RCR2; + char wk16[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char RTCEN:1; + unsigned char :7; + } BIT; + } RCR3; + char wk17[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char RCKSEL:1; + unsigned char :7; + } BIT; + } RCR4; + char wk18[1]; + union + { + unsigned short WORD; + struct + { + unsigned short RFC:1; + unsigned short :15; + } BIT; + } RFRH; + union + { + unsigned short WORD; + struct + { + unsigned short RFC:16; + } BIT; + } RFRL; + union + { + unsigned char BYTE; + struct + { + unsigned char ADJ:6; + unsigned char PMADJ:2; + } BIT; + } RADJ; + char wk19[3]; + char wk20[1]; + char wk21[5]; + char wk22[1]; + char wk23[7]; + char wk24[1]; + char wk25[1]; + char wk26[1]; + char wk27[1]; + char wk28[1]; + char wk29[13]; + char wk30[1]; + char wk31[1]; + char wk32[1]; + char wk33[1]; + char wk34[1]; + char wk35[3]; + char wk36[1]; + char wk37[1]; + char wk38[1]; + char wk39[5]; + char wk40[1]; + char wk41[1]; + char wk42[1]; + char wk43[1]; + char wk44[1]; + char wk45[3]; + char wk46[1]; + char wk47[1]; + char wk48[1]; + char wk49[5]; + char wk50[1]; + char wk51[1]; + char wk52[1]; + char wk53[1]; + char wk54[1]; + char wk55[3]; + char wk56[1]; + char wk57[1]; + char wk58[1]; +}; + +struct st_rtc_bcnt +{ + union + { + unsigned char BYTE; + struct + { + unsigned char F64HZ:1; + unsigned char F32HZ:1; + unsigned char F16HZ:1; + unsigned char F8HZ:1; + unsigned char F4HZ:1; + unsigned char F2HZ:1; + unsigned char F1HZ:1; + unsigned char :1; + } BIT; + } R64CNT; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNT:8; + } BIT; + } BCNT0; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNT:8; + } BIT; + } BCNT1; + char wk2[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNT:8; + } BIT; + } BCNT2; + char wk3[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNT:8; + } BIT; + } BCNT3; + char wk4[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char DATE1:4; + unsigned char DATE10:2; + unsigned char :2; + } BIT; + } RDAYCNT; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MON1:4; + unsigned char MON10:1; + unsigned char :3; + } BIT; + } RMONCNT; + char wk6[1]; + union + { + unsigned short WORD; + struct + { + unsigned short YR1:4; + unsigned short YR10:4; + unsigned short :8; + } BIT; + } RYRCNT; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNTAR:8; + } BIT; + } BCNT0AR; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNTAR:8; + } BIT; + } BCNT1AR; + char wk8[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNTAR:8; + } BIT; + } BCNT2AR; + char wk9[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char BCNTAR:8; + } BIT; + } BCNT3AR; + char wk10[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char ENB:8; + } BIT; + } BCNT0AER; + char wk11[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char ENB:8; + } BIT; + } BCNT1AER; + char wk12[1]; + union + { + unsigned short WORD; + struct + { + unsigned short ENB:8; + unsigned short :8; + } BIT; + } BCNT2AER; + union + { + unsigned char BYTE; + struct + { + unsigned char ENB:8; + } BIT; + } BCNT3AER; + char wk13[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char AF:1; + unsigned char CF:1; + unsigned char PF:1; + unsigned char :5; + } BIT; + } RSR; + char wk14[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char AIE:1; + unsigned char CIE:1; + unsigned char PIE:1; + unsigned char :1; + unsigned char PES:4; + } BIT; + } RCR1; + char wk15[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char START:1; + unsigned char RESET:1; + unsigned char ADJ30:1; + unsigned char :1; + unsigned char AADJE:1; + unsigned char AADJP:1; + unsigned char HR24:1; + unsigned char CNTMD:1; + } BIT; + } RCR2; + char wk16[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char RTCEN:1; + unsigned char :7; + } BIT; + } RCR3; + char wk17[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char RCKSEL:1; + unsigned char :7; + } BIT; + } RCR4; + char wk18[1]; + union + { + unsigned short WORD; + struct + { + unsigned short RFC:1; + unsigned short :15; + } BIT; + } RFRH; + union + { + unsigned short WORD; + struct + { + unsigned short RFC:16; + } BIT; + } RFRL; + union + { + unsigned char BYTE; + struct + { + unsigned char ADJ:6; + unsigned char PMADJ:2; + } BIT; + } RADJ; + char wk19[3]; + char wk20[1]; + char wk21[5]; + char wk22[1]; + char wk23[7]; + char wk24[1]; + char wk25[1]; + char wk26[1]; + char wk27[1]; + char wk28[1]; + char wk29[13]; + char wk30[1]; + char wk31[1]; + char wk32[1]; + char wk33[1]; + char wk34[1]; + char wk35[3]; + char wk36[1]; + char wk37[1]; + char wk38[1]; + char wk39[5]; + char wk40[1]; + char wk41[1]; + char wk42[1]; + char wk43[1]; + char wk44[1]; + char wk45[3]; + char wk46[1]; + char wk47[1]; + char wk48[1]; + char wk49[5]; + char wk50[1]; + char wk51[1]; + char wk52[1]; + char wk53[1]; + char wk54[1]; + char wk55[3]; + char wk56[1]; + char wk57[1]; + char wk58[1]; +}; + +#define RTC0 (*(volatile struct st_rtc *)0xFCFFD000) +#define RTC1 (*(volatile struct st_rtc *)0xFCFF1000) +#define RTC_BCNT0 (*(volatile struct st_rtc_bcnt *)0xFCFFD000) +#define RTC_BCNT1 (*(volatile struct st_rtc_bcnt *)0xFCFF1000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scifa_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scifa_iodefine.h new file mode 100644 index 0000000..0664f44 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scifa_iodefine.h @@ -0,0 +1,224 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef SCIFA_IODEFINE_H +#define SCIFA_IODEFINE_H + +struct st_scifa +{ + union + { + unsigned short WORD; + struct + { + unsigned short CKS:2; + unsigned short :1; + unsigned short STOP:1; + unsigned short PM:1; + unsigned short PE:1; + unsigned short CHR:1; + unsigned short CM:1; + unsigned short :8; + } BIT; + } SMR; + union + { + union + { + unsigned char BYTE; + struct + { + unsigned char MDDR:8; + } BIT; + } MDDR; + union + { + unsigned char BYTE; + struct + { + unsigned char BRR:8; + } BIT; + } BRR; + } BRR_MDDR; + char wk0[1]; + union + { + unsigned short WORD; + struct + { + unsigned short CKE:2; + unsigned short TEIE:1; + unsigned short REIE:1; + unsigned short RE:1; + unsigned short TE:1; + unsigned short RIE:1; + unsigned short TIE:1; + unsigned short :8; + } BIT; + } SCR; + union + { + unsigned char BYTE; + struct + { + unsigned char FTDR:8; + } BIT; + } FTDR; + char wk1[1]; + union + { + unsigned short WORD; + struct + { + unsigned short DR:1; + unsigned short RDF:1; + unsigned short PER:1; + unsigned short FER:1; + unsigned short BRK:1; + unsigned short TDFE:1; + unsigned short TEND:1; + unsigned short ER:1; + unsigned short :8; + } BIT; + } FSR; + union + { + unsigned char BYTE; + struct + { + unsigned char FRDR:8; + } BIT; + } FRDR; + char wk2[1]; + union + { + unsigned short WORD; + struct + { + unsigned short LOOP:1; + unsigned short RFRST:1; + unsigned short TFRST:1; + unsigned short MCE:1; + unsigned short TTRG:2; + unsigned short RTRG:2; + unsigned short RSTRG:3; + unsigned short :5; + } BIT; + } FCR; + union + { + unsigned short WORD; + struct + { + unsigned short R:5; + unsigned short :3; + unsigned short T:5; + unsigned short :3; + } BIT; + } FDR; + union + { + unsigned short WORD; + struct + { + unsigned short SPB2DT:1; + unsigned short SPB2IO:1; + unsigned short SCKDT:1; + unsigned short SCKIO:1; + unsigned short CTS2DT:1; + unsigned short CTS2IO:1; + unsigned short RTS2DT:1; + unsigned short RTS2IO:1; + unsigned short :8; + } BIT; + } SPTR; + union + { + unsigned short WORD; + struct + { + unsigned short ORER:1; + unsigned short :1; + unsigned short FER:4; + unsigned short :2; + unsigned short PER:4; + unsigned short :4; + } BIT; + } LSR; + union + { + unsigned char BYTE; + struct + { + unsigned char ABCS0:1; + unsigned char :1; + unsigned char NFEN:1; + unsigned char DIR:1; + unsigned char MDDRS:1; + unsigned char BRME:1; + unsigned char :1; + unsigned char BGDM:1; + } BIT; + } SEMR; + char wk3[1]; + union + { + unsigned short WORD; + struct + { + unsigned short TFTC:5; + unsigned short :2; + unsigned short TTRGS:1; + unsigned short RFTC:5; + unsigned short :2; + unsigned short RTRGS:1; + } BIT; + } FTCR; +}; + +#define SCIFA0 (*(volatile struct st_scifa *)0xE8007000) +#define SCIFA1 (*(volatile struct st_scifa *)0xE8007800) +#define SCIFA2 (*(volatile struct st_scifa *)0xE8008000) +#define SCIFA3 (*(volatile struct st_scifa *)0xE8008800) +#define SCIFA4 (*(volatile struct st_scifa *)0xE8009000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scim_iodefine.h new file mode 100644 index 0000000..190ba4a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/scim_iodefine.h @@ -0,0 +1,248 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef SCIM_IODEFINE_H +#define SCIM_IODEFINE_H + +struct st_scim +{ + union + { + unsigned char BYTE; + struct + { + unsigned char CKS:2; + unsigned char MP:1; + unsigned char STOP:1; + unsigned char PM:1; + unsigned char PE:1; + unsigned char CHR:1; + unsigned char CM:1; + } BIT; + } SMR; + union + { + unsigned char BYTE; + struct + { + unsigned char BRR:8; + } BIT; + } BRR; + union + { + unsigned char BYTE; + struct + { + unsigned char CKE:2; + unsigned char TEIE:1; + unsigned char MPIE:1; + unsigned char RE:1; + unsigned char TE:1; + unsigned char RIE:1; + unsigned char TIE:1; + } BIT; + } SCR; + union + { + unsigned char BYTE; + struct + { + unsigned char TDR:8; + } BIT; + } TDR; + union + { + unsigned char BYTE; + struct + { + unsigned char MPBT:1; + unsigned char MPB:1; + unsigned char TEND:1; + unsigned char PER:1; + unsigned char FER:1; + unsigned char ORER:1; + unsigned char RDRF:1; + unsigned char TDRE:1; + } BIT; + } SSR; + union + { + unsigned char BYTE; + struct + { + unsigned char RDR:8; + } BIT; + } RDR; + union + { + unsigned char BYTE; + struct + { + unsigned char SMIF:1; + unsigned char :1; + unsigned char SINV:1; + unsigned char SDIR:1; + unsigned char CHR1:1; + unsigned char :2; + unsigned char BCP2:1; + } BIT; + } SCMR; + union + { + unsigned char BYTE; + struct + { + unsigned char ACS0:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ABCS:1; + unsigned char NFEN:1; + unsigned char BGDM:1; + unsigned char RXDESEL:1; + } BIT; + } SEMR; + union + { + unsigned char BYTE; + struct + { + unsigned char NFCS:3; + unsigned char :5; + } BIT; + } SNFR; + char wk0[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char CTSE:1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + unsigned char :1; + } BIT; + } SECR; + union + { + struct + { + union + { + unsigned short WORD; + struct + { + unsigned short TDRHL:16; + } BIT; + } TDRHL; + }W; + struct + { + union + { + unsigned char BYTE; + struct + { + unsigned char TDRH:8; + } BIT; + } TDRH; + union + { + unsigned char BYTE; + struct + { + unsigned char TDRL:8; + } BIT; + } TDRL; + }B; + } TDRHL; + union + { + struct + { + union + { + unsigned short WORD; + struct + { + unsigned short RDRHL:16; + } BIT; + } RDRHL; + }W; + struct + { + union + { + unsigned char BYTE; + struct + { + unsigned char RDRH:8; + } BIT; + } RDRH; + union + { + unsigned char BYTE; + struct + { + unsigned char RDRL:8; + } BIT; + } RDRL; + }B; + } RDRHL; + union + { + unsigned char BYTE; + struct + { + unsigned char MDDR:8; + } BIT; + } MDDR; +}; + +#define SCIM0 (*(volatile struct st_scim *)0xE800B000) +#define SCIM1 (*(volatile struct st_scim *)0xE800B800) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sdmmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sdmmc_iodefine.h new file mode 100644 index 0000000..9ee59db --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sdmmc_iodefine.h @@ -0,0 +1,2160 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef SDMMC_IODEFINE_H +#define SDMMC_IODEFINE_H + +struct st_sdmmc0 +{ + union + { + unsigned long LONG; + struct + { + unsigned long TAPEN:1; + unsigned long :15; + unsigned long TAPNUM:8; + unsigned long :8; + } BIT; + } SCC_DTCNTL; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TAPSET:8; + unsigned long :24; + } BIT; + } SCC_TAPSET; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DT2NSSET:8; + unsigned long DT2NESET:8; + unsigned long :16; + } BIT; + } SCC_DT2FF; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DTSEL:1; + unsigned long :31; + } BIT; + } SCC_CKSEL; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RVSEN:1; + unsigned long RVSW:1; + unsigned long :6; + unsigned long TAPSEL:8; + unsigned long :16; + } BIT; + } SCC_RVSCNTL; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long REQTAPDWN:1; + unsigned long REQTAPUP:1; + unsigned long RVSERR:1; + unsigned long :29; + } BIT; + } SCC_RVSREQ; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CMPNGD:9; + unsigned long :7; + unsigned long CMPNGU:9; + unsigned long :7; + } BIT; + } SCC_SMPCMP; + char wk6[4044]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CF:6; + unsigned long long C0:1; + unsigned long long C1:1; + unsigned long long MD0:1; + unsigned long long MD1:1; + unsigned long long MD2:1; + unsigned long long MD3:1; + unsigned long long MD4:1; + unsigned long long MD5:1; + unsigned long long MD6:1; + unsigned long long MD7:1; + unsigned long long :48; + } BIT; + } SD_CMD; + char wk7[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CF:32; + unsigned long long :32; + } BIT; + } SD_ARG; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CF:16; + unsigned long long :48; + } BIT; + } SD_ARG1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long STP:1; + unsigned long long :7; + unsigned long long SEC:1; + unsigned long long :7; + unsigned long long HPICMD:1; + unsigned long long HPIMODE:1; + unsigned long long :46; + } BIT; + } SD_STOP; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CNT:32; + unsigned long long :32; + } BIT; + } SD_SECCNT; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:64; + } BIT; + } SD_RSP10; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:16; + unsigned long long :48; + } BIT; + } SD_RSP1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:32; + unsigned long long :32; + } BIT; + } SD_RSP32; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:16; + unsigned long long :48; + } BIT; + } SD_RSP3; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:56; + unsigned long long :8; + } BIT; + } SD_RSP54; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:16; + unsigned long long :48; + } BIT; + } SD_RSP5; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:24; + unsigned long long :40; + } BIT; + } SD_RSP76; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:8; + unsigned long long :56; + } BIT; + } SD_RSP7; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long INFO0:1; + unsigned long long :1; + unsigned long long INFO2:1; + unsigned long long INFO3:1; + unsigned long long INFO4:1; + unsigned long long INFO5:1; + unsigned long long :1; + unsigned long long INFO7:1; + unsigned long long INFO8:1; + unsigned long long INFO9:1; + unsigned long long INFO10:1; + unsigned long long :5; + unsigned long long HPIRES:1; + unsigned long long :47; + } BIT; + } SD_INFO1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long ERR0:1; + unsigned long long ERR1:1; + unsigned long long ERR2:1; + unsigned long long ERR3:1; + unsigned long long ERR4:1; + unsigned long long ERR5:1; + unsigned long long ERR6:1; + unsigned long long DAT0:1; + unsigned long long BRE:1; + unsigned long long BWE:1; + unsigned long long :3; + unsigned long long SCLKDIVEN:1; + unsigned long long CBSY:1; + unsigned long long ILA:1; + unsigned long long :48; + } BIT; + } SD_INFO2; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IMASK0:1; + unsigned long long :1; + unsigned long long IMASK2:1; + unsigned long long IMASK3:1; + unsigned long long IMASK4:1; + unsigned long long :3; + unsigned long long IMASK8:1; + unsigned long long IMASK9:1; + unsigned long long :6; + unsigned long long IMASK16:1; + unsigned long long :47; + } BIT; + } SD_INFO1_MASK; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long EMASK0:1; + unsigned long long EMASK1:1; + unsigned long long EMASK2:1; + unsigned long long EMASK3:1; + unsigned long long EMASK4:1; + unsigned long long EMASK5:1; + unsigned long long EMASK6:1; + unsigned long long :1; + unsigned long long BMASK0:1; + unsigned long long BMASK1:1; + unsigned long long :5; + unsigned long long IMASK:1; + unsigned long long :48; + } BIT; + } SD_INFO2_MASK; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long DIV:8; + unsigned long long SCLKEN:1; + unsigned long long SDCLKOFFEN:1; + unsigned long long :54; + } BIT; + } SD_CLK_CTRL; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long LEN:10; + unsigned long long :54; + } BIT; + } SD_SIZE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CTOP21:1; + unsigned long long CTOP22:1; + unsigned long long CTOP23:1; + unsigned long long CTOP24:1; + unsigned long long TOP24:1; + unsigned long long TOP25:1; + unsigned long long TOP26:1; + unsigned long long TOP27:1; + unsigned long long TOUTMASK:1; + unsigned long long EXTOP:1; + unsigned long long :3; + unsigned long long WIDTH8:1; + unsigned long long :1; + unsigned long long WIDTH:1; + unsigned long long :48; + } BIT; + } SD_OPTION; + char wk8[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long E0:1; + unsigned long long E1:1; + unsigned long long E2:1; + unsigned long long E3:1; + unsigned long long E4:1; + unsigned long long E5:1; + unsigned long long :2; + unsigned long long E8:1; + unsigned long long E9:1; + unsigned long long E10:1; + unsigned long long E11:1; + unsigned long long E12:1; + unsigned long long E13:1; + unsigned long long E14:1; + unsigned long long :49; + } BIT; + } SD_ERR_STS1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long E0:1; + unsigned long long E1:1; + unsigned long long E2:1; + unsigned long long E3:1; + unsigned long long E4:1; + unsigned long long E5:1; + unsigned long long E6:1; + unsigned long long :57; + } BIT; + } SD_ERR_STS2; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long BUF:64; + } BIT; + } SD_BUF0; + char wk9[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IOMOD:1; + unsigned long long :1; + unsigned long long RWREQ:1; + unsigned long long :5; + unsigned long long IOABT:1; + unsigned long long C52PUB:1; + unsigned long long :54; + } BIT; + } SDIO_MODE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IOIRQ:1; + unsigned long long :13; + unsigned long long EXPUB52:1; + unsigned long long EXWT:1; + unsigned long long :48; + } BIT; + } SDIO_INFO1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IOMSK:1; + unsigned long long :13; + unsigned long long MEXPUB52:1; + unsigned long long MEXWT:1; + unsigned long long :48; + } BIT; + } SDIO_INFO1_MASK; + char wk10[632]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long :1; + unsigned long long DMASDRW:1; + unsigned long long :62; + } BIT; + } CC_EXT_MODE; + char wk11[24]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SDRST:1; + unsigned long long :63; + } BIT; + } SOFT_RST; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IP:8; + unsigned long long UR:8; + unsigned long long :48; + } BIT; + } VERSION; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long WMODE:1; + unsigned long long ENDIAN:1; + unsigned long long :6; + unsigned long long BUSWIDTH:1; + unsigned long long :55; + } BIT; + } HOST_MODE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long DDR:1; + unsigned long long :7; + unsigned long long NOCHKCR:1; + unsigned long long :55; + } BIT; + } SDIF_MODE; + char wk12[40]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long :1; + unsigned long long SD_RST:1; + unsigned long long :62; + } BIT; + } SD_STATUS; + char wk13[1080]; + char wk14[8]; + char wk15[16]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long :4; + unsigned long long BUS_WIDTH:2; + unsigned long long :10; + unsigned long long CH_NUM:2; + unsigned long long :46; + } BIT; + } DM_CM_DTRAN_MODE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long DM_START:1; + unsigned long long :63; + } BIT; + } DM_CM_DTRAN_CTRL; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQRST:1; + unsigned long long :7; + unsigned long long DTRANRST0:1; + unsigned long long DTRANRST1:1; + unsigned long long :54; + } BIT; + } DM_CM_RST; + char wk16[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQEND:1; + unsigned long long :15; + unsigned long long DTRANEND0:1; + unsigned long long :3; + unsigned long long DTRANEND1:1; + unsigned long long :43; + } BIT; + } DM_CM_INFO1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQEND_MASK:1; + unsigned long long :15; + unsigned long long DTRANEND0_MASK:1; + unsigned long long :3; + unsigned long long DTRANEND1_MASK:1; + unsigned long long :43; + } BIT; + } DM_CM_INFO1_MASK; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQERR:1; + unsigned long long :15; + unsigned long long DTRANERR0:1; + unsigned long long DTRANERR1:1; + unsigned long long :46; + } BIT; + } DM_CM_INFO2; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQERR_MASK:1; + unsigned long long :15; + unsigned long long DTRANERR0_MASK:1; + unsigned long long DTRANERR1_MASK:1; + unsigned long long :46; + } BIT; + } DM_CM_INFO2_MASK; + char wk17[32]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long :3; + unsigned long long DADDR:29; + unsigned long long :32; + } BIT; + } DM_DTRAN_ADDR; +}; + +struct st_sdmmc1 +{ + union + { + unsigned long LONG; + struct + { + unsigned long TAPEN:1; + unsigned long :15; + unsigned long TAPNUM:8; + unsigned long :8; + } BIT; + } SCC_DTCNTL; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TAPSET:8; + unsigned long :24; + } BIT; + } SCC_TAPSET; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DT2NSSET:8; + unsigned long DT2NESET:8; + unsigned long :16; + } BIT; + } SCC_DT2FF; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DTSEL:1; + unsigned long :31; + } BIT; + } SCC_CKSEL; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long RVSEN:1; + unsigned long RVSW:1; + unsigned long :6; + unsigned long TAPSEL:8; + unsigned long :16; + } BIT; + } SCC_RVSCNTL; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long REQTAPDWN:1; + unsigned long REQTAPUP:1; + unsigned long RVSERR:1; + unsigned long :29; + } BIT; + } SCC_RVSREQ; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long CMPNGD:9; + unsigned long :7; + unsigned long CMPNGU:9; + unsigned long :7; + } BIT; + } SCC_SMPCMP; + char wk6[4044]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CF:6; + unsigned long long C0:1; + unsigned long long C1:1; + unsigned long long MD0:1; + unsigned long long MD1:1; + unsigned long long MD2:1; + unsigned long long MD3:1; + unsigned long long MD4:1; + unsigned long long MD5:1; + unsigned long long MD6:1; + unsigned long long MD7:1; + unsigned long long :48; + } BIT; + } SD_CMD; + char wk7[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CF:32; + unsigned long long :32; + } BIT; + } SD_ARG; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CF:16; + unsigned long long :48; + } BIT; + } SD_ARG1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long STP:1; + unsigned long long :7; + unsigned long long SEC:1; + unsigned long long :7; + unsigned long long HPICMD:1; + unsigned long long HPIMODE:1; + unsigned long long :46; + } BIT; + } SD_STOP; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CNT:32; + unsigned long long :32; + } BIT; + } SD_SECCNT; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:64; + } BIT; + } SD_RSP10; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:16; + unsigned long long :48; + } BIT; + } SD_RSP1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:32; + unsigned long long :32; + } BIT; + } SD_RSP32; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:16; + unsigned long long :48; + } BIT; + } SD_RSP3; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:56; + unsigned long long :8; + } BIT; + } SD_RSP54; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:16; + unsigned long long :48; + } BIT; + } SD_RSP5; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:24; + unsigned long long :40; + } BIT; + } SD_RSP76; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long R:8; + unsigned long long :56; + } BIT; + } SD_RSP7; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long INFO0:1; + unsigned long long :1; + unsigned long long INFO2:1; + unsigned long long INFO3:1; + unsigned long long INFO4:1; + unsigned long long INFO5:1; + unsigned long long :1; + unsigned long long INFO7:1; + unsigned long long INFO8:1; + unsigned long long INFO9:1; + unsigned long long INFO10:1; + unsigned long long :5; + unsigned long long HPIRES:1; + unsigned long long :47; + } BIT; + } SD_INFO1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long ERR0:1; + unsigned long long ERR1:1; + unsigned long long ERR2:1; + unsigned long long ERR3:1; + unsigned long long ERR4:1; + unsigned long long ERR5:1; + unsigned long long ERR6:1; + unsigned long long DAT0:1; + unsigned long long BRE:1; + unsigned long long BWE:1; + unsigned long long :3; + unsigned long long SCLKDIVEN:1; + unsigned long long CBSY:1; + unsigned long long ILA:1; + unsigned long long :48; + } BIT; + } SD_INFO2; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IMASK0:1; + unsigned long long :1; + unsigned long long IMASK2:1; + unsigned long long IMASK3:1; + unsigned long long IMASK4:1; + unsigned long long :3; + unsigned long long IMASK8:1; + unsigned long long IMASK9:1; + unsigned long long :6; + unsigned long long IMASK16:1; + unsigned long long :47; + } BIT; + } SD_INFO1_MASK; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long EMASK0:1; + unsigned long long EMASK1:1; + unsigned long long EMASK2:1; + unsigned long long EMASK3:1; + unsigned long long EMASK4:1; + unsigned long long EMASK5:1; + unsigned long long EMASK6:1; + unsigned long long :1; + unsigned long long BMASK0:1; + unsigned long long BMASK1:1; + unsigned long long :5; + unsigned long long IMASK:1; + unsigned long long :48; + } BIT; + } SD_INFO2_MASK; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long DIV:8; + unsigned long long SCLKEN:1; + unsigned long long SDCLKOFFEN:1; + unsigned long long :54; + } BIT; + } SD_CLK_CTRL; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long LEN:10; + unsigned long long :54; + } BIT; + } SD_SIZE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long CTOP21:1; + unsigned long long CTOP22:1; + unsigned long long CTOP23:1; + unsigned long long CTOP24:1; + unsigned long long TOP24:1; + unsigned long long TOP25:1; + unsigned long long TOP26:1; + unsigned long long TOP27:1; + unsigned long long TOUTMASK:1; + unsigned long long EXTOP:1; + unsigned long long :3; + unsigned long long WIDTH8:1; + unsigned long long :1; + unsigned long long WIDTH:1; + unsigned long long :48; + } BIT; + } SD_OPTION; + char wk8[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long E0:1; + unsigned long long E1:1; + unsigned long long E2:1; + unsigned long long E3:1; + unsigned long long E4:1; + unsigned long long E5:1; + unsigned long long :2; + unsigned long long E8:1; + unsigned long long E9:1; + unsigned long long E10:1; + unsigned long long E11:1; + unsigned long long E12:1; + unsigned long long E13:1; + unsigned long long E14:1; + unsigned long long :49; + } BIT; + } SD_ERR_STS1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long E0:1; + unsigned long long E1:1; + unsigned long long E2:1; + unsigned long long E3:1; + unsigned long long E4:1; + unsigned long long E5:1; + unsigned long long E6:1; + unsigned long long :57; + } BIT; + } SD_ERR_STS2; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long BUF:64; + } BIT; + } SD_BUF0; + char wk9[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IOMOD:1; + unsigned long long :1; + unsigned long long RWREQ:1; + unsigned long long :5; + unsigned long long IOABT:1; + unsigned long long C52PUB:1; + unsigned long long :54; + } BIT; + } SDIO_MODE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IOIRQ:1; + unsigned long long :13; + unsigned long long EXPUB52:1; + unsigned long long EXWT:1; + unsigned long long :48; + } BIT; + } SDIO_INFO1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IOMSK:1; + unsigned long long :13; + unsigned long long MEXPUB52:1; + unsigned long long MEXWT:1; + unsigned long long :48; + } BIT; + } SDIO_INFO1_MASK; + char wk10[632]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long :1; + unsigned long long DMASDRW:1; + unsigned long long :62; + } BIT; + } CC_EXT_MODE; + char wk11[24]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SDRST:1; + unsigned long long :63; + } BIT; + } SOFT_RST; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long IP:8; + unsigned long long UR:8; + unsigned long long :48; + } BIT; + } VERSION; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long WMODE:1; + unsigned long long ENDIAN:1; + unsigned long long :6; + unsigned long long BUSWIDTH:1; + unsigned long long :55; + } BIT; + } HOST_MODE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long DDR:1; + unsigned long long :7; + unsigned long long NOCHKCR:1; + unsigned long long :55; + } BIT; + } SDIF_MODE; + char wk12[1128]; + char wk13[8]; + char wk14[16]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long :4; + unsigned long long BUS_WIDTH:2; + unsigned long long :10; + unsigned long long CH_NUM:2; + unsigned long long :46; + } BIT; + } DM_CM_DTRAN_MODE; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long DM_START:1; + unsigned long long :63; + } BIT; + } DM_CM_DTRAN_CTRL; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQRST:1; + unsigned long long :7; + unsigned long long DTRANRST0:1; + unsigned long long DTRANRST1:1; + unsigned long long :54; + } BIT; + } DM_CM_RST; + char wk15[8]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQEND:1; + unsigned long long :15; + unsigned long long DTRANEND0:1; + unsigned long long :3; + unsigned long long DTRANEND1:1; + unsigned long long :43; + } BIT; + } DM_CM_INFO1; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQEND_MASK:1; + unsigned long long :15; + unsigned long long DTRANEND0_MASK:1; + unsigned long long :3; + unsigned long long DTRANEND1_MASK:1; + unsigned long long :43; + } BIT; + } DM_CM_INFO1_MASK; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQERR:1; + unsigned long long :15; + unsigned long long DTRANERR0:1; + unsigned long long DTRANERR1:1; + unsigned long long :46; + } BIT; + } DM_CM_INFO2; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long SEQERR_MASK:1; + unsigned long long :15; + unsigned long long DTRANERR0_MASK:1; + unsigned long long DTRANERR1_MASK:1; + unsigned long long :46; + } BIT; + } DM_CM_INFO2_MASK; + char wk16[32]; + union + { + unsigned long long LONGLONG; + struct + { + unsigned long L; + unsigned long H; + } LONG; + struct + { + unsigned short LL; + unsigned short LH; + unsigned short HL; + unsigned short HH; + } WORD; + struct + { + unsigned long long :3; + unsigned long long DADDR:29; + unsigned long long :32; + } BIT; + } DM_DTRAN_ADDR; +}; + +#define SDMMC0 (*(volatile struct st_sdmmc0 *)0xE8227000) +#define SDMMC1 (*(volatile struct st_sdmmc1 *)0xE8229000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spdif_iodefine.h new file mode 100644 index 0000000..1cafd45 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spdif_iodefine.h @@ -0,0 +1,246 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef SPDIF_IODEFINE_H +#define SPDIF_IODEFINE_H + +struct st_spdif +{ + union + { + unsigned long LONG; + struct + { + unsigned long TLCA:24; + unsigned long :8; + } BIT; + } TLCA; + union + { + unsigned long LONG; + struct + { + unsigned long TRCA:24; + unsigned long :8; + } BIT; + } TRCA; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long CTL:5; + unsigned long :2; + unsigned long CATCD:8; + unsigned long SRCNO:4; + unsigned long CHNO:4; + unsigned long FS:4; + unsigned long CLAC:2; + unsigned long :2; + } BIT; + } TLCS; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long CTL:5; + unsigned long :2; + unsigned long CATCD:8; + unsigned long SRCNO:4; + unsigned long CHNO:4; + unsigned long FS:4; + unsigned long CLAC:2; + unsigned long :2; + } BIT; + } TRCS; + union + { + unsigned long LONG; + struct + { + unsigned long TUI:32; + } BIT; + } TUI; + union + { + unsigned long LONG; + struct + { + unsigned long RLCA:24; + unsigned long :8; + } BIT; + } RLCA; + union + { + unsigned long LONG; + struct + { + unsigned long RRCA:24; + unsigned long :8; + } BIT; + } RRCA; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long CTL:5; + unsigned long :2; + unsigned long CATCD:8; + unsigned long SRCNO:4; + unsigned long CHNO:4; + unsigned long FS:4; + unsigned long CLAC:2; + unsigned long :2; + } BIT; + } RLCS; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long CTL:5; + unsigned long :2; + unsigned long CATCD:8; + unsigned long SRCNO:4; + unsigned long CHNO:4; + unsigned long FS:4; + unsigned long CLAC:2; + unsigned long :2; + } BIT; + } RRCS; + union + { + unsigned long LONG; + struct + { + unsigned long RUI:32; + } BIT; + } RUI; + union + { + unsigned long LONG; + struct + { + unsigned long TCBI:1; + unsigned long TCSI:1; + unsigned long RCBI:1; + unsigned long RCSI:1; + unsigned long TUII:1; + unsigned long RUII:1; + unsigned long ABUI:1; + unsigned long ABOI:1; + unsigned long CSEI:1; + unsigned long PREI:1; + unsigned long PAEI:1; + unsigned long CREI:1; + unsigned long UBUI:1; + unsigned long UBOI:1; + unsigned long TEIE:1; + unsigned long REIE:1; + unsigned long TME:1; + unsigned long RME:1; + unsigned long AOS:1; + unsigned long NCSI:1; + unsigned long TDE:1; + unsigned long RDE:1; + unsigned long TASS:2; + unsigned long RASS:2; + unsigned long PB:1; + unsigned long :1; + unsigned long CKS:1; + unsigned long :3; + } BIT; + } CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long CBTX:1; + unsigned long CSTX:1; + unsigned long CBRX:1; + unsigned long CSRX:1; + unsigned long TUIR:1; + unsigned long RUIR:1; + unsigned long ABU:1; + unsigned long ABO:1; + unsigned long CSE:1; + unsigned long PREE:1; + unsigned long PARE:1; + unsigned long CE:1; + unsigned long UBU:1; + unsigned long UBO:1; + unsigned long TIS:1; + unsigned long RIS:1; + unsigned long CMD:1; + unsigned long :15; + } BIT; + } STAT; + union + { + unsigned long LONG; + struct + { + unsigned long TDAD:24; + unsigned long :8; + } BIT; + } TDAD; + union + { + unsigned long LONG; + struct + { + unsigned long RDAD:24; + unsigned long :8; + } BIT; + } RDAD; +}; + +#define SPDIF (*(volatile struct st_spdif *)0xE804F000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spibsc_iodefine.h new file mode 100644 index 0000000..9fd8036 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/spibsc_iodefine.h @@ -0,0 +1,435 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef SPIBSC_IODEFINE_H +#define SPIBSC_IODEFINE_H + +struct st_spibsc +{ + union + { + unsigned long LONG; + struct + { + unsigned long BSZ:2; + unsigned long :6; + unsigned long IO0FV:2; + unsigned long :2; + unsigned long IO2FV:2; + unsigned long IO3FV:2; + unsigned long MOIIO0:2; + unsigned long MOIIO1:2; + unsigned long MOIIO2:2; + unsigned long MOIIO3:2; + unsigned long :7; + unsigned long MD:1; + } BIT; + } CMNCR; + union + { + unsigned long LONG; + struct + { + unsigned long SCKDL:3; + unsigned long :5; + unsigned long SLNDL:3; + unsigned long :5; + unsigned long SPNDL:3; + unsigned long :13; + } BIT; + } SSLDR; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SSLE:1; + unsigned long :7; + unsigned long RBE:1; + unsigned long RCF:1; + unsigned long :6; + unsigned long RBURST:5; + unsigned long :3; + unsigned long SSLN:1; + unsigned long :7; + } BIT; + } DRCR; + union + { + unsigned long LONG; + struct + { + unsigned long OCMD:8; + unsigned long :8; + unsigned long CMD:8; + unsigned long :8; + } BIT; + } DRCMR; + union + { + unsigned long LONG; + struct + { + unsigned long EAC:3; + unsigned long :13; + unsigned long EAV:8; + unsigned long :8; + } BIT; + } DREAR; + union + { + unsigned long LONG; + struct + { + unsigned long OPD0:8; + unsigned long OPD1:8; + unsigned long OPD2:8; + unsigned long OPD3:8; + } BIT; + } DROPR; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long OPDE:4; + unsigned long ADE:4; + unsigned long OCDE:1; + unsigned long :1; + unsigned long CDE:1; + unsigned long DME:1; + unsigned long DRDB:2; + unsigned long :2; + unsigned long OPDB:2; + unsigned long :2; + unsigned long ADB:2; + unsigned long :2; + unsigned long OCDB:2; + unsigned long CDB:2; + } BIT; + } DRENR; + union + { + unsigned long LONG; + struct + { + unsigned long SPIE:1; + unsigned long SPIWE:1; + unsigned long SPIRE:1; + unsigned long :5; + unsigned long SSLKP:1; + unsigned long :23; + } BIT; + } SMCR; + union + { + unsigned long LONG; + struct + { + unsigned long OCMD:8; + unsigned long :8; + unsigned long CMD:8; + unsigned long :8; + } BIT; + } SMCMR; + union + { + unsigned long LONG; + struct + { + unsigned long ADR:32; + } BIT; + } SMADR; + union + { + unsigned long LONG; + struct + { + unsigned long OPD0:8; + unsigned long OPD1:8; + unsigned long OPD2:8; + unsigned long OPD3:8; + } BIT; + } SMOPR; + union + { + unsigned long LONG; + struct + { + unsigned long SPIDE:4; + unsigned long OPDE:4; + unsigned long ADE:4; + unsigned long OCDE:1; + unsigned long :1; + unsigned long CDE:1; + unsigned long DME:1; + unsigned long SPIDB:2; + unsigned long :2; + unsigned long OPDB:2; + unsigned long :2; + unsigned long ADB:2; + unsigned long :2; + unsigned long OCDB:2; + unsigned long CDB:2; + } BIT; + } SMENR; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDATA0:32; + } BIT; + } SMRDR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long RDATA1:32; + } BIT; + } SMRDR1; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long WDATA0:32; + } BIT; + } SMWDR0; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long WDATA1:32; + } BIT; + } SMWDR1; + union + { + unsigned long LONG; + struct + { + unsigned long TEND:1; + unsigned long SSLF:1; + unsigned long :30; + } BIT; + } CMNSR; + char wk2[12]; + union + { + unsigned long LONG; + struct + { + unsigned long DMCYC:5; + unsigned long :27; + } BIT; + } DRDMCR; + union + { + unsigned long LONG; + struct + { + unsigned long DRDRE:1; + unsigned long :3; + unsigned long OPDRE:1; + unsigned long :3; + unsigned long ADDRE:1; + unsigned long :3; + unsigned long HYPE:3; + unsigned long :17; + } BIT; + } DRDRENR; + union + { + unsigned long LONG; + struct + { + unsigned long DMCYC:5; + unsigned long :27; + } BIT; + } SMDMCR; + union + { + unsigned long LONG; + struct + { + unsigned long SPIDRE:1; + unsigned long :3; + unsigned long OPDRE:1; + unsigned long :3; + unsigned long ADDRE:1; + unsigned long :3; + unsigned long HYPE:3; + unsigned long :17; + } BIT; + } SMDRENR; + char wk3[8]; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ1:32; + } BIT; + } PHYADJ1; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ2:32; + } BIT; + } PHYADJ2; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long PHYMEM:2; + unsigned long WBUF:1; + unsigned long :1; + unsigned long WBUF2:1; + unsigned long :11; + unsigned long CKSEL:2; + unsigned long HS:1; + unsigned long :1; + unsigned long OCT:1; + unsigned long EXDS:1; + unsigned long OCTA_1_0:2; + unsigned long :6; + unsigned long ALT_ALIGN:1; + unsigned long CAL:1; + } BIT; + } PHYCNT; + union + { + unsigned long LONG; + struct + { + unsigned long :28; + unsigned long DDRTMG:2; + unsigned long :2; + } BIT; + } PHYOFFSET1; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long OCTTMG:3; + unsigned long :21; + } BIT; + } PHYOFFSET2; + union + { + unsigned long LONG; + struct + { + unsigned long INT:1; + unsigned long WPVAL:1; + unsigned long RSTVAL:1; + unsigned long :21; + unsigned long INTEN:1; + unsigned long WPEN:1; + unsigned long RSTEN:1; + unsigned long :5; + } BIT; + } PHYINT; +}; + +#define SPIBSC (*(volatile struct st_spibsc *)0x1F800000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sprite_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sprite_iodefine.h new file mode 100644 index 0000000..48e53f4 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/sprite_iodefine.h @@ -0,0 +1,1251 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef SPRITE_IODEFINE_H +#define SPRITE_IODEFINE_H + +struct st_sprite +{ + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0RBUSSEL:1; + unsigned long :31; + } BIT; + } SPEA0RLSL; + char wk0[12]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0RSTA0:32; + } BIT; + } SPEA0STA0; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0RPHA0:32; + } BIT; + } SPEA0PHA0; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0RCM0:2; + unsigned long :30; + } BIT; + } SPEA0RCM0; + char wk2[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0RUP0:1; + unsigned long :1; + unsigned long :30; + } BIT; + } SPEA0RUP; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0RDTH:3; + unsigned long :1; + unsigned long SPEA0RLEN:3; + unsigned long :25; + } BIT; + } SPEA0RCFG; + char wk4[180]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0EN0:1; + unsigned long SPEA0S0EN1:1; + unsigned long SPEA0S0EN2:1; + unsigned long SPEA0S0EN3:1; + unsigned long SPEA0S0EN4:1; + unsigned long SPEA0S0EN5:1; + unsigned long SPEA0S0EN6:1; + unsigned long SPEA0S0EN7:1; + unsigned long SPEA0S0EN8:1; + unsigned long SPEA0S0EN9:1; + unsigned long SPEA0S0EN10:1; + unsigned long SPEA0S0EN11:1; + unsigned long SPEA0S0EN12:1; + unsigned long SPEA0S0EN13:1; + unsigned long SPEA0S0EN14:1; + unsigned long SPEA0S0EN15:1; + unsigned long :16; + } BIT; + } SPEA0S0EN; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DS0:1; + unsigned long SPEA0S0DS1:1; + unsigned long SPEA0S0DS2:1; + unsigned long SPEA0S0DS3:1; + unsigned long SPEA0S0DS4:1; + unsigned long SPEA0S0DS5:1; + unsigned long SPEA0S0DS6:1; + unsigned long SPEA0S0DS7:1; + unsigned long SPEA0S0DS8:1; + unsigned long SPEA0S0DS9:1; + unsigned long SPEA0S0DS10:1; + unsigned long SPEA0S0DS11:1; + unsigned long SPEA0S0DS12:1; + unsigned long SPEA0S0DS13:1; + unsigned long SPEA0S0DS14:1; + unsigned long SPEA0S0DS15:1; + unsigned long :16; + } BIT; + } SPEA0S0DS; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0UP0:1; + unsigned long :31; + } BIT; + } SPEA0S0UP; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1EN0:1; + unsigned long SPEA0S1EN1:1; + unsigned long SPEA0S1EN2:1; + unsigned long SPEA0S1EN3:1; + unsigned long SPEA0S1EN4:1; + unsigned long SPEA0S1EN5:1; + unsigned long SPEA0S1EN6:1; + unsigned long SPEA0S1EN7:1; + unsigned long SPEA0S1EN8:1; + unsigned long SPEA0S1EN9:1; + unsigned long SPEA0S1EN10:1; + unsigned long SPEA0S1EN11:1; + unsigned long SPEA0S1EN12:1; + unsigned long SPEA0S1EN13:1; + unsigned long SPEA0S1EN14:1; + unsigned long SPEA0S1EN15:1; + unsigned long :16; + } BIT; + } SPEA0S1EN; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DS0:1; + unsigned long SPEA0S1DS1:1; + unsigned long SPEA0S1DS2:1; + unsigned long SPEA0S1DS3:1; + unsigned long SPEA0S1DS4:1; + unsigned long SPEA0S1DS5:1; + unsigned long SPEA0S1DS6:1; + unsigned long SPEA0S1DS7:1; + unsigned long SPEA0S1DS8:1; + unsigned long SPEA0S1DS9:1; + unsigned long SPEA0S1DS10:1; + unsigned long SPEA0S1DS11:1; + unsigned long SPEA0S1DS12:1; + unsigned long SPEA0S1DS13:1; + unsigned long SPEA0S1DS14:1; + unsigned long SPEA0S1DS15:1; + unsigned long :16; + } BIT; + } SPEA0S1DS; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1UP0:1; + unsigned long :31; + } BIT; + } SPEA0S1UP; + char wk6[740]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA0:32; + } BIT; + } SPEA0S0DA0; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH0:11; + unsigned long :6; + unsigned long SPEA0S0LYW0:10; + unsigned long :5; + } BIT; + } SPEA0S0LY0; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY0:13; + unsigned long :4; + unsigned long SPEA0S0PSX0:10; + unsigned long :5; + } BIT; + } SPEA0S0PS0; + char wk8[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA1:32; + } BIT; + } SPEA0S0DA1; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH1:11; + unsigned long :6; + unsigned long SPEA0S0LYW1:10; + unsigned long :5; + } BIT; + } SPEA0S0LY1; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY1:13; + unsigned long :4; + unsigned long SPEA0S0PSX1:10; + unsigned long :5; + } BIT; + } SPEA0S0PS1; + char wk10[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA2:32; + } BIT; + } SPEA0S0DA2; + char wk11[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH2:11; + unsigned long :6; + unsigned long SPEA0S0LYW2:10; + unsigned long :5; + } BIT; + } SPEA0S0LY2; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY2:13; + unsigned long :4; + unsigned long SPEA0S0PSX2:10; + unsigned long :5; + } BIT; + } SPEA0S0PS2; + char wk12[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA3:32; + } BIT; + } SPEA0S0DA3; + char wk13[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH3:11; + unsigned long :6; + unsigned long SPEA0S0LYW3:10; + unsigned long :5; + } BIT; + } SPEA0S0LY3; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY3:13; + unsigned long :4; + unsigned long SPEA0S0PSX3:10; + unsigned long :5; + } BIT; + } SPEA0S0PS3; + char wk14[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA4:32; + } BIT; + } SPEA0S0DA4; + char wk15[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH4:11; + unsigned long :6; + unsigned long SPEA0S0LYW4:10; + unsigned long :5; + } BIT; + } SPEA0S0LY4; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY4:13; + unsigned long :4; + unsigned long SPEA0S0PSX4:10; + unsigned long :5; + } BIT; + } SPEA0S0PS4; + char wk16[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA5:32; + } BIT; + } SPEA0S0DA5; + char wk17[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH5:11; + unsigned long :6; + unsigned long SPEA0S0LYW5:10; + unsigned long :5; + } BIT; + } SPEA0S0LY5; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY5:13; + unsigned long :4; + unsigned long SPEA0S0PSX5:10; + unsigned long :5; + } BIT; + } SPEA0S0PS5; + char wk18[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA6:32; + } BIT; + } SPEA0S0DA6; + char wk19[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH6:11; + unsigned long :6; + unsigned long SPEA0S0LYW6:10; + unsigned long :5; + } BIT; + } SPEA0S0LY6; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY6:13; + unsigned long :4; + unsigned long SPEA0S0PSX6:10; + unsigned long :5; + } BIT; + } SPEA0S0PS6; + char wk20[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA7:32; + } BIT; + } SPEA0S0DA7; + char wk21[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH7:11; + unsigned long :6; + unsigned long SPEA0S0LYW7:10; + unsigned long :5; + } BIT; + } SPEA0S0LY7; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY7:13; + unsigned long :4; + unsigned long SPEA0S0PSX7:10; + unsigned long :5; + } BIT; + } SPEA0S0PS7; + char wk22[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA8:32; + } BIT; + } SPEA0S0DA8; + char wk23[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH8:11; + unsigned long :6; + unsigned long SPEA0S0LYW8:10; + unsigned long :5; + } BIT; + } SPEA0S0LY8; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY8:13; + unsigned long :4; + unsigned long SPEA0S0PSX8:10; + unsigned long :5; + } BIT; + } SPEA0S0PS8; + char wk24[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA9:32; + } BIT; + } SPEA0S0DA9; + char wk25[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH9:11; + unsigned long :6; + unsigned long SPEA0S0LYW9:10; + unsigned long :5; + } BIT; + } SPEA0S0LY9; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY9:13; + unsigned long :4; + unsigned long SPEA0S0PSX9:10; + unsigned long :5; + } BIT; + } SPEA0S0PS9; + char wk26[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA10:32; + } BIT; + } SPEA0S0DA10; + char wk27[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH10:11; + unsigned long :6; + unsigned long SPEA0S0LYW10:10; + unsigned long :5; + } BIT; + } SPEA0S0LY10; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY10:13; + unsigned long :4; + unsigned long SPEA0S0PSX10:10; + unsigned long :5; + } BIT; + } SPEA0S0PS10; + char wk28[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA11:32; + } BIT; + } SPEA0S0DA11; + char wk29[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH11:11; + unsigned long :6; + unsigned long SPEA0S0LYW11:10; + unsigned long :5; + } BIT; + } SPEA0S0LY11; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY11:13; + unsigned long :4; + unsigned long SPEA0S0PSX11:10; + unsigned long :5; + } BIT; + } SPEA0S0PS11; + char wk30[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA12:32; + } BIT; + } SPEA0S0DA12; + char wk31[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH12:11; + unsigned long :6; + unsigned long SPEA0S0LYW12:10; + unsigned long :5; + } BIT; + } SPEA0S0LY12; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY12:13; + unsigned long :4; + unsigned long SPEA0S0PSX12:10; + unsigned long :5; + } BIT; + } SPEA0S0PS12; + char wk32[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA13:32; + } BIT; + } SPEA0S0DA13; + char wk33[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH13:11; + unsigned long :6; + unsigned long SPEA0S0LYW13:10; + unsigned long :5; + } BIT; + } SPEA0S0LY13; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY13:13; + unsigned long :4; + unsigned long SPEA0S0PSX13:10; + unsigned long :5; + } BIT; + } SPEA0S0PS13; + char wk34[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA14:32; + } BIT; + } SPEA0S0DA14; + char wk35[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH14:11; + unsigned long :6; + unsigned long SPEA0S0LYW14:10; + unsigned long :5; + } BIT; + } SPEA0S0LY14; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY14:13; + unsigned long :4; + unsigned long SPEA0S0PSX14:10; + unsigned long :5; + } BIT; + } SPEA0S0PS14; + char wk36[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0DA15:32; + } BIT; + } SPEA0S0DA15; + char wk37[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0LYH15:11; + unsigned long :6; + unsigned long SPEA0S0LYW15:10; + unsigned long :5; + } BIT; + } SPEA0S0LY15; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S0PSY15:13; + unsigned long :4; + unsigned long SPEA0S0PSX15:10; + unsigned long :5; + } BIT; + } SPEA0S0PS15; + char wk38[528]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA0:32; + } BIT; + } SPEA0S1DA0; + char wk39[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH0:11; + unsigned long :6; + unsigned long SPEA0S1LYW0:10; + unsigned long :5; + } BIT; + } SPEA0S1LY0; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY0:13; + unsigned long :4; + unsigned long SPEA0S1PSX0:10; + unsigned long :5; + } BIT; + } SPEA0S1PS0; + char wk40[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA1:32; + } BIT; + } SPEA0S1DA1; + char wk41[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH1:11; + unsigned long :6; + unsigned long SPEA0S1LYW1:10; + unsigned long :5; + } BIT; + } SPEA0S1LY1; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY1:13; + unsigned long :4; + unsigned long SPEA0S1PSX1:10; + unsigned long :5; + } BIT; + } SPEA0S1PS1; + char wk42[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA2:32; + } BIT; + } SPEA0S1DA2; + char wk43[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH2:11; + unsigned long :6; + unsigned long SPEA0S1LYW2:10; + unsigned long :5; + } BIT; + } SPEA0S1LY2; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY2:13; + unsigned long :4; + unsigned long SPEA0S1PSX2:10; + unsigned long :5; + } BIT; + } SPEA0S1PS2; + char wk44[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA3:32; + } BIT; + } SPEA0S1DA3; + char wk45[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH3:11; + unsigned long :6; + unsigned long SPEA0S1LYW3:10; + unsigned long :5; + } BIT; + } SPEA0S1LY3; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY3:13; + unsigned long :4; + unsigned long SPEA0S1PSX3:10; + unsigned long :5; + } BIT; + } SPEA0S1PS3; + char wk46[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA4:32; + } BIT; + } SPEA0S1DA4; + char wk47[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH4:11; + unsigned long :6; + unsigned long SPEA0S1LYW4:10; + unsigned long :5; + } BIT; + } SPEA0S1LY4; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY4:13; + unsigned long :4; + unsigned long SPEA0S1PSX4:10; + unsigned long :5; + } BIT; + } SPEA0S1PS4; + char wk48[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA5:32; + } BIT; + } SPEA0S1DA5; + char wk49[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH5:11; + unsigned long :6; + unsigned long SPEA0S1LYW5:10; + unsigned long :5; + } BIT; + } SPEA0S1LY5; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY5:13; + unsigned long :4; + unsigned long SPEA0S1PSX5:10; + unsigned long :5; + } BIT; + } SPEA0S1PS5; + char wk50[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA6:32; + } BIT; + } SPEA0S1DA6; + char wk51[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH6:11; + unsigned long :6; + unsigned long SPEA0S1LYW6:10; + unsigned long :5; + } BIT; + } SPEA0S1LY6; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY6:13; + unsigned long :4; + unsigned long SPEA0S1PSX6:10; + unsigned long :5; + } BIT; + } SPEA0S1PS6; + char wk52[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA7:32; + } BIT; + } SPEA0S1DA7; + char wk53[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH7:11; + unsigned long :6; + unsigned long SPEA0S1LYW7:10; + unsigned long :5; + } BIT; + } SPEA0S1LY7; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY7:13; + unsigned long :4; + unsigned long SPEA0S1PSX7:10; + unsigned long :5; + } BIT; + } SPEA0S1PS7; + char wk54[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA8:32; + } BIT; + } SPEA0S1DA8; + char wk55[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH8:11; + unsigned long :6; + unsigned long SPEA0S1LYW8:10; + unsigned long :5; + } BIT; + } SPEA0S1LY8; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY8:13; + unsigned long :4; + unsigned long SPEA0S1PSX8:10; + unsigned long :5; + } BIT; + } SPEA0S1PS8; + char wk56[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA9:32; + } BIT; + } SPEA0S1DA9; + char wk57[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH9:11; + unsigned long :6; + unsigned long SPEA0S1LYW9:10; + unsigned long :5; + } BIT; + } SPEA0S1LY9; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY9:13; + unsigned long :4; + unsigned long SPEA0S1PSX9:10; + unsigned long :5; + } BIT; + } SPEA0S1PS9; + char wk58[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA10:32; + } BIT; + } SPEA0S1DA10; + char wk59[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH10:11; + unsigned long :6; + unsigned long SPEA0S1LYW10:10; + unsigned long :5; + } BIT; + } SPEA0S1LY10; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY10:13; + unsigned long :4; + unsigned long SPEA0S1PSX10:10; + unsigned long :5; + } BIT; + } SPEA0S1PS10; + char wk60[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA11:32; + } BIT; + } SPEA0S1DA11; + char wk61[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH11:11; + unsigned long :6; + unsigned long SPEA0S1LYW11:10; + unsigned long :5; + } BIT; + } SPEA0S1LY11; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY11:13; + unsigned long :4; + unsigned long SPEA0S1PSX11:10; + unsigned long :5; + } BIT; + } SPEA0S1PS11; + char wk62[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA12:32; + } BIT; + } SPEA0S1DA12; + char wk63[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH12:11; + unsigned long :6; + unsigned long SPEA0S1LYW12:10; + unsigned long :5; + } BIT; + } SPEA0S1LY12; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY12:13; + unsigned long :4; + unsigned long SPEA0S1PSX12:10; + unsigned long :5; + } BIT; + } SPEA0S1PS12; + char wk64[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA13:32; + } BIT; + } SPEA0S1DA13; + char wk65[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH13:11; + unsigned long :6; + unsigned long SPEA0S1LYW13:10; + unsigned long :5; + } BIT; + } SPEA0S1LY13; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY13:13; + unsigned long :4; + unsigned long SPEA0S1PSX13:10; + unsigned long :5; + } BIT; + } SPEA0S1PS13; + char wk66[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA14:32; + } BIT; + } SPEA0S1DA14; + char wk67[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH14:11; + unsigned long :6; + unsigned long SPEA0S1LYW14:10; + unsigned long :5; + } BIT; + } SPEA0S1LY14; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY14:13; + unsigned long :4; + unsigned long SPEA0S1PSX14:10; + unsigned long :5; + } BIT; + } SPEA0S1PS14; + char wk68[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1DA15:32; + } BIT; + } SPEA0S1DA15; + char wk69[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1LYH15:11; + unsigned long :6; + unsigned long SPEA0S1LYW15:10; + unsigned long :5; + } BIT; + } SPEA0S1LY15; + union + { + unsigned long LONG; + struct + { + unsigned long SPEA0S1PSY15:13; + unsigned long :4; + unsigned long SPEA0S1PSX15:10; + unsigned long :5; + } BIT; + } SPEA0S1PS15; +}; + +#define SPRITE (*(volatile struct st_sprite *)0xE803E010) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ssif_iodefine.h new file mode 100644 index 0000000..814a9b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/ssif_iodefine.h @@ -0,0 +1,203 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef SSIF_IODEFINE_H +#define SSIF_IODEFINE_H + +struct st_ssif +{ + union + { + unsigned long LONG; + struct + { + unsigned long REN:1; + unsigned long TEN:1; + unsigned long :1; + unsigned long MUEN:1; + unsigned long CKDV:4; + unsigned long DEL:1; + unsigned long PDTA:1; + unsigned long SDTA:1; + unsigned long SPDP:1; + unsigned long LRCKP:1; + unsigned long BCKP:1; + unsigned long MST:1; + unsigned long :1; + unsigned long SWL:3; + unsigned long DWL:3; + unsigned long FRM:2; + unsigned long :1; + unsigned long IIEN:1; + unsigned long ROIEN:1; + unsigned long RUIEN:1; + unsigned long TOIEN:1; + unsigned long TUIEN:1; + unsigned long CKS:1; + unsigned long :1; + } BIT; + } SSICR; + union + { + unsigned long LONG; + struct + { + unsigned long :25; + unsigned long IIRQ:1; + unsigned long ROIRQ:1; + unsigned long RUIRQ:1; + unsigned long TOIRQ:1; + unsigned long TUIRQ:1; + unsigned long :2; + } BIT; + } SSISR; + char wk0[8]; + union + { + unsigned long LONG; + struct + { + unsigned long RFRST:1; + unsigned long TFRST:1; + unsigned long RIE:1; + unsigned long TIE:1; + unsigned long :4; + unsigned long RXDNCE:1; + unsigned long LRCKNCE:1; + unsigned long BCKNCE:1; + unsigned long BSW:1; + unsigned long :4; + unsigned long SSIRST:1; + unsigned long :13; + unsigned long :1; + unsigned long AUCKE:1; + } BIT; + } SSIFCR; + union + { + unsigned long LONG; + struct + { + unsigned long RDF:1; + unsigned long :7; + unsigned long RDC:6; + unsigned long :2; + unsigned long TDE:1; + unsigned long :7; + unsigned long TDC:6; + unsigned long :2; + } BIT; + } SSIFSR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long SSIFTDR:32; + } BIT; + } SSIFTDR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long SSIFRDR:32; + } BIT; + } SSIFRDR; + union + { + unsigned long LONG; + struct + { + unsigned long OMOD:2; + unsigned long :6; + unsigned long LRCONT:1; + unsigned long BCKASTP:1; + unsigned long :22; + } BIT; + } SSIOFR; + union + { + unsigned long LONG; + struct + { + unsigned long RDFS:5; + unsigned long :3; + unsigned long TDES:5; + unsigned long :19; + } BIT; + } SSISCR; + char wk1[16]; + char wk2[4]; + char wk3[4]; +}; + +#define SSIF0 (*(volatile struct st_ssif *)0xE8048000) +#define SSIF1 (*(volatile struct st_ssif *)0xE8048800) +#define SSIF2 (*(volatile struct st_ssif *)0xE8049000) +#define SSIF3 (*(volatile struct st_ssif *)0xE8049800) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/usb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/usb_iodefine.h new file mode 100644 index 0000000..a41661c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/usb_iodefine.h @@ -0,0 +1,2402 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef USB_IODEFINE_H +#define USB_IODEFINE_H + +struct st_usb00 +{ + unsigned long HCREVISION; + union + { + unsigned long LONG; + struct + { + unsigned long CBSR:2; + unsigned long PLE:1; + unsigned long IE:1; + unsigned long CLE:1; + unsigned long BLE:1; + unsigned long HCFS:2; + unsigned long :1; + unsigned long RWC:1; + unsigned long :1; + unsigned long :21; + } BIT; + } HCCONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long HCR:1; + unsigned long CLF:1; + unsigned long BLF:1; + unsigned long :1; + unsigned long :12; + unsigned long SOC:2; + unsigned long :14; + } BIT; + } HCCOMMANDSTATUS; + union + { + unsigned long LONG; + struct + { + unsigned long SO:1; + unsigned long WDH:1; + unsigned long SF:1; + unsigned long RD:1; + unsigned long UE:1; + unsigned long FNO:1; + unsigned long RHSC:1; + unsigned long :23; + unsigned long :1; + unsigned long :1; + } BIT; + } HCINTERRUPTSTATUS; + union + { + unsigned long LONG; + struct + { + unsigned long SOE:1; + unsigned long WDHE:1; + unsigned long SFE:1; + unsigned long RDE:1; + unsigned long UEE:1; + unsigned long FNOE:1; + unsigned long RHSCE:1; + unsigned long :23; + unsigned long OCE:1; + unsigned long MIE:1; + } BIT; + } HCINTERRUPTENABLE; + union + { + unsigned long LONG; + struct + { + unsigned long SOD:1; + unsigned long WDHD:1; + unsigned long SFD:1; + unsigned long RDD:1; + unsigned long UED:1; + unsigned long FNOD:1; + unsigned long RHSCD:1; + unsigned long :23; + unsigned long OCD:1; + unsigned long MID:1; + } BIT; + } HCINTERRUPTDISABLE; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long HcHCCA:24; + } BIT; + } HCHCCA; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long PECD:28; + } BIT; + } HCPERIODCURRENTED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long CHED:28; + } BIT; + } HCCONTROLHEADED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long CCED:28; + } BIT; + } HCCONTROLCURRENTED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long BHED:28; + } BIT; + } HCBULKHEADED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long BCED:28; + } BIT; + } HCBULKCURRENTED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long DH:28; + } BIT; + } HCDONEHEAD; + union + { + unsigned long LONG; + struct + { + unsigned long FI:14; + unsigned long :2; + unsigned long FSMPS:15; + unsigned long FIT:1; + } BIT; + } HCFMINTERVAL; + union + { + unsigned long LONG; + struct + { + unsigned long FR:14; + unsigned long :17; + unsigned long FRT:1; + } BIT; + } HCFMREMAINING; + union + { + unsigned long LONG; + struct + { + unsigned long FN:16; + unsigned long :16; + } BIT; + } HCFMNUMBER; + union + { + unsigned long LONG; + struct + { + unsigned long PS:14; + unsigned long :18; + } BIT; + } HCPERIODICSTART; + union + { + unsigned long LONG; + struct + { + unsigned long LST:12; + unsigned long :20; + } BIT; + } HCLSTHRESHOLD; + union + { + unsigned long LONG; + struct + { + unsigned long NDP:8; + unsigned long PSM:1; + unsigned long NPS:1; + unsigned long DT:1; + unsigned long OCPM:1; + unsigned long NOCP:1; + unsigned long :11; + unsigned long POTPGT:8; + } BIT; + } HCRHDESCRIPTORA; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long DR:1; + unsigned long :15; + unsigned long PPCM:1; + unsigned long :14; + } BIT; + } HCRHDESCRIPTORB; + union + { + unsigned long LONG; + struct + { + unsigned long LPS:1; + unsigned long OCI:1; + unsigned long :13; + unsigned long DRWE:1; + unsigned long LPSC:1; + unsigned long OCIC:1; + unsigned long :13; + unsigned long CRWE:1; + } BIT; + } HCRHSTATUS; + union + { + unsigned long LONG; + struct + { + unsigned long CCS:1; + unsigned long PES:1; + unsigned long PSS:1; + unsigned long POCI:1; + unsigned long PRS:1; + unsigned long :3; + unsigned long PPS:1; + unsigned long LSDA:1; + unsigned long :6; + unsigned long CSC:1; + unsigned long PESC:1; + unsigned long PSSC:1; + unsigned long OCIC:1; + unsigned long PRSC:1; + unsigned long :11; + } BIT; + } HCRHPORTSTATUS1; + char wk0[4]; + char wk1[164]; + union + { + unsigned long LONG; + struct + { + unsigned long CapabilityRegistersLength:8; + unsigned long :8; + unsigned long InterfaceVersionNumber:16; + } BIT; + } CAPL_VERSION; + union + { + unsigned long LONG; + struct + { + unsigned long N_PORTS:4; + unsigned long PPC:1; + unsigned long :2; + unsigned long PortRoutingRules:1; + unsigned long N_PCC:4; + unsigned long N_CC:4; + unsigned long P_INDICATOR:1; + unsigned long :3; + unsigned long DebugPortNumber:4; + unsigned long :8; + } BIT; + } HCSPARAMS; + union + { + unsigned long LONG; + struct + { + unsigned long AddressingCapability:1; + unsigned long ProgramableFrameListFlag:1; + unsigned long AsynchronousScheduleParkCapability:1; + unsigned long :1; + unsigned long IsochronousSchedulingThreshold:4; + unsigned long EECP:8; + unsigned long HardwarePrefetch:1; + unsigned long LinkPowerManagementCapability:1; + unsigned long PerPortChangeEventCapability:1; + unsigned long FramePeriodicListCapability:1; + unsigned long :12; + } BIT; + } HCCPARAMS; + union + { + unsigned long LONG; + struct + { + unsigned long CompanionPortRoute:32; + } BIT; + } HCSP_PORTROUTE; + char wk2[16]; + union + { + unsigned long LONG; + struct + { + unsigned long RS:1; + unsigned long HCRESET:1; + unsigned long FrameListSize:2; + unsigned long PeriodicScheduleEnable:1; + unsigned long AsynchronousScheduleEnable:1; + unsigned long InterruptonAsyncAdvanceDoorbell:1; + unsigned long :1; + unsigned long AsynchronousScheduleParkModeCount:2; + unsigned long :1; + unsigned long AsynchronousScheduleParkModeEnable:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long PerPortChangeEventsEnable:1; + unsigned long InterruptThresholdControl:8; + unsigned long HostInitiatedResumeDuration:4; + unsigned long :4; + } BIT; + } USBCMD; + union + { + unsigned long LONG; + struct + { + unsigned long USBINT:1; + unsigned long USBERRINT:1; + unsigned long PortChangeDetect:1; + unsigned long FrameListRollover:1; + unsigned long HostSystemError:1; + unsigned long InterruptonAsyncAdvance:1; + unsigned long :6; + unsigned long HCHalted:1; + unsigned long Reclamation:1; + unsigned long PeriodicScheduleStatus:1; + unsigned long AsynchronousScheduleStatus:1; + unsigned long Port1ChangeDetect:1; + unsigned long :15; + } BIT; + } USBSTS; + union + { + unsigned long LONG; + struct + { + unsigned long USBInterruptEnable:1; + unsigned long USBErrorInterruptEnable:1; + unsigned long PortChangeDetectEnable:1; + unsigned long FrameListRolloverEnable:1; + unsigned long HostSystemErrorEnable:1; + unsigned long InterruptonAsyncAdvanceEnable:1; + unsigned long :10; + unsigned long Port1ChangeEventEnable:1; + unsigned long :15; + } BIT; + } USBINTR; + union + { + unsigned long LONG; + struct + { + unsigned long FrameIndex:14; + unsigned long :18; + } BIT; + } FRINDEX; + union + { + unsigned long LONG; + struct + { + unsigned long CTRLDSSEGMENT:32; + } BIT; + } CTRLDSSEGMENT; + union + { + unsigned long LONG; + struct + { + unsigned long :12; + unsigned long BaseAddress:20; + } BIT; + } PERIODICLISTBASE; + union + { + unsigned long LONG; + struct + { + unsigned long :5; + unsigned long LPL:27; + } BIT; + } ASYNCLISTADDR; + char wk3[36]; + union + { + unsigned long LONG; + struct + { + unsigned long CF:1; + unsigned long :31; + } BIT; + } CONFIGFLAG; + union + { + unsigned long LONG; + struct + { + unsigned long CurrentConnectStatus:1; + unsigned long ConnectStatusChange:1; + unsigned long PortEnabled_Disabled:1; + unsigned long PortEnable_DisableChange:1; + unsigned long OvercurrentActive:1; + unsigned long OvercurrentChange:1; + unsigned long ForcePortResume:1; + unsigned long Suspend:1; + unsigned long PortReset:1; + unsigned long SuspendusingL1:1; + unsigned long LineStatus:2; + unsigned long PP:1; + unsigned long PortOwner:1; + unsigned long :2; + unsigned long PortTestControl:4; + unsigned long WKCNNT_E:1; + unsigned long WKDSCNNT_E:1; + unsigned long WKOC_E:1; + unsigned long SuspendStatus:2; + unsigned long DeviceAddress:7; + } BIT; + } PORTSC1; + char wk4[4]; + char wk5[132]; + char wk6[4]; + char wk7[12]; + union + { + unsigned long LONG; + struct + { + unsigned long AHB_INTEN:1; + unsigned long USBH_INTAEN:1; + unsigned long USBH_INTBEN:1; + unsigned long UCOM_INTEN:1; + unsigned long WAKEON_INTEN:1; + unsigned long :1; + unsigned long :26; + } BIT; + } INT_ENABLE; + union + { + unsigned long LONG; + struct + { + unsigned long AHB_INT:1; + unsigned long USBH_INTA:1; + unsigned long USBH_INTB:1; + unsigned long UCOM_INT:1; + unsigned long WAKEON_INT:1; + unsigned long :1; + unsigned long :26; + } BIT; + } INT_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long MAX_BURST_LEN:2; + unsigned long :2; + unsigned long ALIGN_ADDRESS:2; + unsigned long :2; + unsigned long PROT_MODE:1; + unsigned long :3; + unsigned long PROT_TYPE:4; + unsigned long :16; + } BIT; + } AHB_BUS_CTR; + union + { + unsigned long LONG; + struct + { + unsigned long USBH_RST:1; + unsigned long PLL_RST:1; + unsigned long DIRPD:1; + unsigned long :29; + } BIT; + } USBCTR; + char wk8[240]; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long :15; + unsigned long :1; + unsigned long :7; + unsigned long RPB_WEN:1; + unsigned long :3; + unsigned long PERI_CLK_MSK:1; + unsigned long HOST_CLK_MSK:1; + unsigned long :1; + unsigned long NONUSE_CLK_MSK:1; + } BIT; + } REGEN_CG_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long GLOBAL_SUSPENDM_P1:1; + unsigned long :1; + unsigned long :2; + unsigned long :6; + unsigned long :12; + unsigned long :1; + unsigned long WKCNNT_ENABLE:1; + unsigned long :6; + unsigned long SLEEPM_ENABLE:1; + unsigned long SUSPENDM_ENABLE:1; + } BIT; + } SPD_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long TIMER_RESUME:16; + unsigned long TIMER_CONNECT:16; + } BIT; + } SPD_RSM_TIMSET; + union + { + unsigned long LONG; + struct + { + unsigned long TIMER_OC:20; + unsigned long TIMER_SLEEP:9; + unsigned long :3; + } BIT; + } OC_SLP_TIMSET; + union + { + unsigned long LONG; + struct + { + unsigned long SBRN:8; + unsigned long FLADJ:8; + unsigned long PORTWAKECAP:16; + } BIT; + } SBRN_FLADJ_PW; + char wk10[4]; + char wk11[4]; + union + { + unsigned long LONG; + struct + { + unsigned long HIRD_SEL_P1:1; + unsigned long RETRY_ENABLE_NYET_P1:1; + unsigned long SLEEP_INT_EN_P1:1; + unsigned long REMOTEWAKE_EN_P1:1; + unsigned long NYET_RETRY_CNT_P1:4; + unsigned long :8; + unsigned long :11; + unsigned long :5; + } BIT; + } PORT_LPM_CTRL1; + char wk12[4]; + char wk13[24]; + char wk14[4]; + char wk15[4]; + char wk16[24]; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long :2; + unsigned long :5; + unsigned long DUR_CTRL:1; + unsigned long :1; + unsigned long :1; + unsigned long :4; + unsigned long :3; + unsigned long :5; + unsigned long :3; + unsigned long :4; + unsigned long :1; + } BIT; + } U2HC_EXT2; + char wk17[4]; + char wk18[4]; + char wk19[4]; + char wk20[144]; + char wk21[4]; + char wk22[4]; + char wk23[4]; + char wk24[1012]; + union + { + unsigned long LONG; + struct + { + unsigned long :30; + unsigned long :1; + unsigned long OTG_PERI:1; + } BIT; + } COMMCTRL; + union + { + unsigned long LONG; + struct + { + unsigned long IDCHG_STA:1; + unsigned long OCINT_STA:1; + unsigned long VBSTACHG_STA:1; + unsigned long VBSTAINT_STA:1; + unsigned long PDDETCHG1_STA:1; + unsigned long :1; + unsigned long CHGDETCHG1_STA:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long DMMONCHG_STA:1; + unsigned long DPMONCHG_STA:1; + unsigned long :1; + unsigned long :5; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :4; + } BIT; + } OBINTSTA; + union + { + unsigned long LONG; + struct + { + unsigned long IDCHG_EN:1; + unsigned long OCINT_EN:1; + unsigned long VBSTACHG_EN:1; + unsigned long VBSTAINT_EN:1; + unsigned long PDDETCHG1_EN:1; + unsigned long :1; + unsigned long CHGDETCHG1_EN:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long DMMONCHG_EN:1; + unsigned long DPMONCHG_EN:1; + unsigned long :1; + unsigned long :5; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :4; + } BIT; + } OBINTEN; + union + { + unsigned long LONG; + struct + { + unsigned long VBOUT:1; + unsigned long :3; + unsigned long VGPUO:1; + unsigned long :3; + unsigned long :1; + unsigned long :7; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long VBLVL:1; + unsigned long :7; + unsigned long VBSTA:1; + unsigned long :2; + } BIT; + } VBCTRL; + union + { + unsigned long LONG; + struct + { + unsigned long IDMON:1; + unsigned long :1; + unsigned long DMMON:1; + unsigned long DPMON:1; + unsigned long :2; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :6; + unsigned long DM_RPD:1; + unsigned long DMRPD_EN:1; + unsigned long DP_RPD:1; + unsigned long DPRPD_EN:1; + unsigned long DSDP:2; + unsigned long :2; + unsigned long :2; + unsigned long :6; + } BIT; + } LINECTRL1; + char wk25[4]; + char wk26[8]; + union + { + unsigned long LONG; + struct + { + unsigned long IDPSRCE:1; + unsigned long IDMSINKE:1; + unsigned long VDPSRCE:1; + unsigned long IDPSINKE:1; + unsigned long VDMSRCE:1; + unsigned long DCPMODE:1; + unsigned long :2; + unsigned long CHGDETSTS:1; + unsigned long PDDETSTS:1; + unsigned long :14; + unsigned long :1; + unsigned long :1; + unsigned long :6; + } BIT; + } BCCTRL1; + char wk27[4]; + char wk28[8]; + char wk29[4]; + char wk30[12]; + union + { + unsigned long LONG; + struct + { + unsigned long CC2_RA:1; + unsigned long CC2_RD:1; + unsigned long CC1_RA:1; + unsigned long CC1_RD:1; + unsigned long CC_LVL_STA:1; + unsigned long CC_PERI_STA:1; + unsigned long :1; + unsigned long :16; + unsigned long :1; + unsigned long CC_LVL_EN:1; + unsigned long CC_LVL:4; + unsigned long CC_LVL_CLR:1; + unsigned long :1; + unsigned long CC_INT_SEL:1; + } BIT; + } CC_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long UCLKSEL:1; + unsigned long :31; + } BIT; + } PHYCLK_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long FIXPHY:1; + unsigned long :31; + } BIT; + } PHYIF_CTRL; +}; + +struct st_usb01 +{ + union + { + unsigned short WORD; + struct + { + unsigned short USBE:1; + unsigned short :3; + unsigned short DPRPU:1; + unsigned short DRPD:1; + unsigned short :1; + unsigned short HSE:1; + unsigned short CNEN:1; + unsigned short :7; + } BIT; + } SYSCFG0; + union + { + unsigned short WORD; + struct + { + unsigned short BWAIT:6; + unsigned short :2; + unsigned short :6; + unsigned short :2; + } BIT; + } SYSCFG1; + union + { + unsigned short WORD; + struct + { + unsigned short LNST:2; + unsigned short :1; + unsigned short :11; + unsigned short :2; + } BIT; + } SYSSTS0; + char wk0[2]; + union + { + unsigned short WORD; + struct + { + unsigned short RHST:3; + unsigned short :5; + unsigned short WKUP:1; + unsigned short :1; + unsigned short :1; + unsigned short :4; + unsigned short BRST1:1; + } BIT; + } DVSTCTR0; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short UTST:4; + unsigned short :7; + unsigned short BRST3:1; + unsigned short :2; + unsigned short BRST2:1; + unsigned short :1; + } BIT; + } TESTMODE; + char wk2[6]; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + struct + { + unsigned char LL; + unsigned char LH; + unsigned char HL; + unsigned char HH; + } BYTE; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } CFIFO; + char wk3[8]; + union + { + unsigned short WORD; + struct + { + unsigned short CURPIPE:4; + unsigned short :1; + unsigned short ISEL:1; + unsigned short :2; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:2; + unsigned short :2; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } CFIFOSEL; + union + { + unsigned short WORD; + struct + { + unsigned short DTLN:12; + unsigned short :1; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } CFIFOCTR; + char wk4[4]; + union + { + unsigned short WORD; + struct + { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short :1; + unsigned short :1; + unsigned short MBW:2; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D0FIFOSEL; + union + { + unsigned short WORD; + struct + { + unsigned short DTLN:12; + unsigned short :1; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D0FIFOCTR; + union + { + unsigned short WORD; + struct + { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short :1; + unsigned short :1; + unsigned short MBW:2; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D1FIFOSEL; + union + { + unsigned short WORD; + struct + { + unsigned short DTLN:12; + unsigned short :1; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D1FIFOCTR; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short BRDYE:1; + unsigned short NRDYE:1; + unsigned short BEMPE:1; + unsigned short CTRE:1; + unsigned short DVSE:1; + unsigned short SOFE:1; + unsigned short RSME:1; + unsigned short VBSE:1; + } BIT; + } INTENB0; + char wk5[2]; + char wk6[2]; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBRDYE:16; + } BIT; + } BRDYENB; + union + { + unsigned short WORD; + struct + { + unsigned short PIPENRDYE:16; + } BIT; + } NRDYENB; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBEMPE:16; + } BIT; + } BEMPENB; + union + { + unsigned short WORD; + struct + { + unsigned short :2; + unsigned short SOFM:2; + unsigned short :1; + unsigned short :1; + unsigned short BRDYM:1; + unsigned short :9; + } BIT; + } SOFCFG; + char wk7[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CTSQ:3; + unsigned short VALID:1; + unsigned short DVSQ:3; + unsigned short VBSTS:1; + unsigned short BRDY:1; + unsigned short NRDY:1; + unsigned short BEMP:1; + unsigned short CTRT:1; + unsigned short DVST:1; + unsigned short SOFR:1; + unsigned short RESM:1; + unsigned short VBINT:1; + } BIT; + } INTSTS0; + char wk8[2]; + char wk9[2]; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBRDY:16; + } BIT; + } BRDYSTS; + union + { + unsigned short WORD; + struct + { + unsigned short PIPENRDY:16; + } BIT; + } NRDYSTS; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBEMP:16; + } BIT; + } BEMPSTS; + union + { + unsigned short WORD; + struct + { + unsigned short FRNM:11; + unsigned short :3; + unsigned short CRCE:1; + unsigned short OVRN:1; + } BIT; + } FRMNUM; + union + { + unsigned short WORD; + struct + { + unsigned short UFRNM:3; + unsigned short :12; + unsigned short DVCHG:1; + } BIT; + } UFRMNUM; + union + { + unsigned short WORD; + struct + { + unsigned short USBADDR:7; + unsigned short :1; + unsigned short STSRECOV0:3; + unsigned short :5; + } BIT; + } USBADDR; + char wk10[2]; + union + { + unsigned short WORD; + struct + { + unsigned short bmRequestType:8; + unsigned short bRequest:8; + } BIT; + } USBREQ; + union + { + unsigned short WORD; + struct + { + unsigned short wValue:16; + } BIT; + } USBVAL; + union + { + unsigned short WORD; + struct + { + unsigned short wIndex:16; + } BIT; + } USBINDX; + union + { + unsigned short WORD; + struct + { + unsigned short wLength:16; + } BIT; + } USBLENG; + union + { + unsigned short WORD; + struct + { + unsigned short :7; + unsigned short SHTNAK:1; + unsigned short CNTMD:1; + unsigned short :7; + } BIT; + } DCPCFG; + union + { + unsigned short WORD; + struct + { + unsigned short MXPS:7; + unsigned short :9; + } BIT; + } DCPMAXP; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short CCPL:1; + unsigned short :2; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short :6; + unsigned short BSTS:1; + } BIT; + } DCPCTR; + char wk11[2]; + union + { + unsigned short WORD; + struct + { + unsigned short PIPESEL:4; + unsigned short :12; + } BIT; + } PIPESEL; + char wk12[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EPNUM:4; + unsigned short DIR:1; + unsigned short :2; + unsigned short SHTNAK:1; + unsigned short CNTMD:1; + unsigned short DBLB:1; + unsigned short BFRE:1; + unsigned short :3; + unsigned short TYPE:2; + } BIT; + } PIPECFG; + union + { + unsigned short WORD; + struct + { + unsigned short BUFNMB:8; + unsigned short :2; + unsigned short BUFSIZE:5; + unsigned short :1; + } BIT; + } PIPEBUF; + union + { + unsigned short WORD; + struct + { + unsigned short MXPS:11; + unsigned short :5; + } BIT; + } PIPEMAXP; + union + { + unsigned short WORD; + struct + { + unsigned short IITV:3; + unsigned short :9; + unsigned short IFIS:1; + unsigned short :3; + } BIT; + } PIPEPERI; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE1CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE2CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE3CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE4CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE5CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE6CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE7CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE8CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE9CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPEACTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPEBCTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPECCTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPEDCTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPEECTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPEFCTR; + char wk13[2]; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE1TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE1TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE2TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE2TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE3TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE3TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE4TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE4TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE5TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE5TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPEBTRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPEBTRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPECTRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPECTRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPEDTRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPEDTRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPEETRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPEETRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPEFTRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPEFTRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE9TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE9TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPEATRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPEATRN; + char wk14[16]; + char wk15[2]; + char wk16[2]; + char wk17[2]; + char wk18[2]; + char wk19[2]; + char wk20[2]; + char wk21[2]; + char wk22[2]; + char wk23[2]; + char wk24[2]; + char wk25[2]; + char wk26[26]; + union + { + unsigned short WORD; + struct + { + unsigned short :7; + unsigned short HWUPM:1; + unsigned short :8; + } BIT; + } LPCTRL; + union + { + unsigned short WORD; + struct + { + unsigned short :14; + unsigned short SUSPM:1; + unsigned short :1; + } BIT; + } LPSTS; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short :2; + unsigned short :1; + unsigned short :2; + unsigned short :1; + unsigned short SusMon:1; + unsigned short :1; + } BIT; + } PHYFUNCTR; + char wk27[4]; + union + { + unsigned short WORD; + struct + { + unsigned short :9; + unsigned short DpPuDwn:1; + unsigned short DmPuDwn:1; + unsigned short :5; + } BIT; + } PHYOTGCTR; + char wk28[52]; + char wk29[2]; + char wk30[2]; + union + { + unsigned short WORD; + struct + { + unsigned short L1RESPEN:1; + unsigned short L1RESPMD:2; + unsigned short L1NEGOMD:1; + unsigned short DVSQ:4; + unsigned short HIRDTHR:4; + unsigned short :2; + unsigned short L1EXTMD:1; + unsigned short :1; + } BIT; + } PL1CTRL1; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short HIRDMON:4; + unsigned short RWEMON:1; + unsigned short :3; + } BIT; + } PL1CTRL2; + char wk31[2]; + char wk32[2]; + char wk33[20]; + char wk34[4]; + char wk35[4]; + char wk36[4]; + char wk37[660]; + union + { + unsigned long LONG; + struct + { + unsigned long SA_WD:32; + } BIT; + } N0SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_0; + union + { + unsigned long LONG; + struct + { + unsigned long SA_WD:32; + } BIT; + } N1SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_0; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } CHSTAT_0; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long CLRDER:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } CHCTRL_0; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:1; + unsigned long :2; + unsigned long REQD:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long :1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long TCM:1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_0; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_0; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:4; + unsigned long :4; + unsigned long DPR:4; + unsigned long :20; + } BIT; + } CHEXT_0; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_0; + union + { + unsigned long LONG; + struct + { + unsigned long SA_WD:32; + } BIT; + } N0SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N0DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N0TB_1; + union + { + unsigned long LONG; + struct + { + unsigned long SA_WD:32; + } BIT; + } N1SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } N1DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } N1TB_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } CRSA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } CRDA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } CRTB_1; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long TC:1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } CHSTAT_1; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long STG:1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long CLRTC:1; + unsigned long CLRDER:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } CHCTRL_1; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:1; + unsigned long :2; + unsigned long REQD:1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long :1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long TCM:1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } CHCFG_1; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } CHITVL_1; + union + { + unsigned long LONG; + struct + { + unsigned long SPR:4; + unsigned long :4; + unsigned long DPR:4; + unsigned long :20; + } BIT; + } CHEXT_1; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } NXLA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } CRLA_1; + char wk38[384]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } SCNT_0; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } SSKP_0; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DCNT_0; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DSKP_0; + char wk39[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } SCNT_1; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } SSKP_1; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DCNT_1; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DSKP_1; + char wk40[208]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long LVINT:1; + unsigned long :14; + unsigned long LDPR:4; + unsigned long :4; + unsigned long LWPR:4; + unsigned long :4; + } BIT; + } DCTRL; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long DITVL:8; + unsigned long :16; + } BIT; + } DSCITVL; + char wk41[8]; + union + { + unsigned long LONG; + struct + { + unsigned long EN0:1; + unsigned long EN1:1; + unsigned long :30; + } BIT; + } DST_EN; + union + { + unsigned long LONG; + struct + { + unsigned long ER0:1; + unsigned long ER1:1; + unsigned long :30; + } BIT; + } DST_ER; + union + { + unsigned long LONG; + struct + { + unsigned long END0:1; + unsigned long END1:1; + unsigned long :30; + } BIT; + } DST_END; + union + { + unsigned long LONG; + struct + { + unsigned long TC0:1; + unsigned long TC1:1; + unsigned long :30; + } BIT; + } DST_TC; + union + { + unsigned long LONG; + struct + { + unsigned long SUS0:1; + unsigned long SUS1:1; + unsigned long :30; + } BIT; + } DST_SUS; +}; + +#define USB00 (*(volatile struct st_usb00 *)0xE8218000) +#define USB10 (*(volatile struct st_usb00 *)0xE821A000) +#define USB01 (*(volatile struct st_usb01 *)0xE8219000) +#define USB11 (*(volatile struct st_usb01 *)0xE821B000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vdc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vdc_iodefine.h new file mode 100644 index 0000000..c57ef33 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vdc_iodefine.h @@ -0,0 +1,3158 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef VDC_IODEFINE_H +#define VDC_IODEFINE_H + +struct st_vdc +{ + union + { + unsigned long LONG; + struct + { + unsigned long INP_IMG_UPDATE:1; + unsigned long :3; + unsigned long INP_EXT_UPDATE:1; + unsigned long :27; + } BIT; + } INP_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long INP_HS_EDGE:1; + unsigned long :3; + unsigned long INP_VS_EDGE:1; + unsigned long :3; + unsigned long INP_PXD_EDGE:1; + unsigned long :3; + unsigned long INP_FORMAT:3; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long INP_SEL:1; + unsigned long :11; + } BIT; + } INP_SEL_CNT; + union + { + unsigned long LONG; + struct + { + unsigned long INP_H_POS:2; + unsigned long :2; + unsigned long INP_F525_625:1; + unsigned long :3; + unsigned long INP_H_EDGE_SEL:1; + unsigned long :7; + unsigned long INP_HS_INV:1; + unsigned long :3; + unsigned long INP_VS_INV:1; + unsigned long :3; + unsigned long INP_SWAP_ON:1; + unsigned long :3; + unsigned long INP_ENDIAN_ON:1; + unsigned long :3; + } BIT; + } INP_EXT_SYNC_CNT; + union + { + unsigned long LONG; + struct + { + unsigned long INP_FH25:12; + unsigned long :4; + unsigned long INP_FH50:12; + unsigned long :4; + } BIT; + } INP_VSYNC_PH_ADJ; + union + { + unsigned long LONG; + struct + { + unsigned long INP_HS_DLY:8; + unsigned long INP_VS_DLY:8; + unsigned long INP_FLD_DLY:8; + unsigned long INP_VS_DLY_L:3; + unsigned long :5; + } BIT; + } INP_DLY_ADJ; + char wk0[108]; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_VEN:1; + unsigned long :31; + } BIT; + } IMGCNT_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long NR1D_Y_GAIN:2; + unsigned long :2; + unsigned long NR1D_Y_TAP:2; + unsigned long :2; + unsigned long NR1D_Y_TH:7; + unsigned long :1; + unsigned long NR1D_ON:1; + unsigned long :3; + unsigned long NR1D_MD:1; + unsigned long :11; + } BIT; + } IMGCNT_NR_CNT0; + union + { + unsigned long LONG; + struct + { + unsigned long NR1D_CR_GAIN:2; + unsigned long :2; + unsigned long NR1D_CR_TAP:2; + unsigned long :2; + unsigned long NR1D_CR_TH:7; + unsigned long :1; + unsigned long NR1D_CB_GAIN:2; + unsigned long :2; + unsigned long NR1D_CB_TAP:2; + unsigned long :2; + unsigned long NR1D_CB_TH:7; + unsigned long :1; + } BIT; + } IMGCNT_NR_CNT1; + char wk1[20]; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_MTX_MD:2; + unsigned long :30; + } BIT; + } IMGCNT_MTX_MODE; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_MTX_GG:11; + unsigned long :5; + unsigned long IMGCNT_MTX_YG:8; + unsigned long :8; + } BIT; + } IMGCNT_MTX_YG_ADJ0; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_MTX_GR:11; + unsigned long :5; + unsigned long IMGCNT_MTX_GB:11; + unsigned long :5; + } BIT; + } IMGCNT_MTX_YG_ADJ1; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_MTX_BG:11; + unsigned long :5; + unsigned long IMGCNT_MTX_B:8; + unsigned long :8; + } BIT; + } IMGCNT_MTX_CBB_ADJ0; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_MTX_BR:11; + unsigned long :5; + unsigned long IMGCNT_MTX_BB:11; + unsigned long :5; + } BIT; + } IMGCNT_MTX_CBB_ADJ1; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_MTX_RG:11; + unsigned long :5; + unsigned long IMGCNT_MTX_R:8; + unsigned long :8; + } BIT; + } IMGCNT_MTX_CRR_ADJ0; + union + { + unsigned long LONG; + struct + { + unsigned long IMGCNT_MTX_RR:11; + unsigned long :5; + unsigned long IMGCNT_MTX_RB:11; + unsigned long :5; + } BIT; + } IMGCNT_MTX_CRR_ADJ1; + char wk2[4]; + char wk3[4]; + char wk4[60]; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_SCL0_VEN_A:1; + unsigned long :3; + unsigned long SC0_SCL0_VEN_B:1; + unsigned long :3; + unsigned long SC0_SCL0_UPDATE:1; + unsigned long :3; + unsigned long SC0_SCL0_VEN_C:1; + unsigned long SC0_SCL0_VEN_D:1; + unsigned long :18; + } BIT; + } SC0_SCL0_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_VMASK_ON:1; + unsigned long :15; + unsigned long SC0_RES_VMASK:16; + } BIT; + } SC0_SCL0_FRC1; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_VLACK_ON:1; + unsigned long :15; + unsigned long SC0_RES_VLACK:16; + } BIT; + } SC0_SCL0_FRC2; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_VS_SEL:1; + unsigned long :7; + unsigned long :1; + unsigned long :7; + unsigned long :1; + unsigned long :15; + } BIT; + } SC0_SCL0_FRC3; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_FH:11; + unsigned long :5; + unsigned long SC0_RES_FV:11; + unsigned long :5; + } BIT; + } SC0_SCL0_FRC4; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_VSDLY:8; + unsigned long SC0_RES_FLD_DLY_SEL:1; + unsigned long :23; + } BIT; + } SC0_SCL0_FRC5; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_F_VW:11; + unsigned long :5; + unsigned long SC0_RES_F_VS:11; + unsigned long :5; + } BIT; + } SC0_SCL0_FRC6; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_F_HW:11; + unsigned long :5; + unsigned long SC0_RES_F_HS:11; + unsigned long :5; + } BIT; + } SC0_SCL0_FRC7; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_QVLACK:1; + unsigned long :3; + unsigned long SC0_RES_QVLOCK:1; + unsigned long :27; + } BIT; + } SC0_SCL0_FRC9; + union + { + unsigned short WORD; + struct + { + unsigned short SC0_RES_LIN_STAT:11; + unsigned short :5; + } BIT; + } SC0_SCL0_MON0; + union + { + unsigned short WORD; + struct + { + unsigned short SC0_RES_LINE:11; + unsigned short :5; + } BIT; + } SC0_SCL0_INT; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_DS_H_ON:1; + unsigned long :3; + unsigned long SC0_RES_DS_V_ON:1; + unsigned long :27; + } BIT; + } SC0_SCL0_DS1; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_VW:11; + unsigned long :5; + unsigned long SC0_RES_VS:11; + unsigned long :5; + } BIT; + } SC0_SCL0_DS2; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_HW:12; + unsigned long :4; + unsigned long SC0_RES_HS:11; + unsigned long :5; + } BIT; + } SC0_SCL0_DS3; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_DS_H_RATIO:16; + unsigned long :12; + unsigned long SC0_RES_DS_H_INTERPOTYP:1; + unsigned long SC0_RES_PFIL_SEL:1; + unsigned long :2; + } BIT; + } SC0_SCL0_DS4; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_BTM_INIPHASE:12; + unsigned long :4; + unsigned long SC0_RES_TOP_INIPHASE:12; + unsigned long SC0_RES_V_INTERPOTYP:1; + unsigned long :3; + } BIT; + } SC0_SCL0_DS5; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_V_RATIO:16; + unsigned long :16; + } BIT; + } SC0_SCL0_DS6; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_OUT_HW:11; + unsigned long :5; + unsigned long SC0_RES_OUT_VW:11; + unsigned long :5; + } BIT; + } SC0_SCL0_DS7; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_US_H_ON:1; + unsigned long :3; + unsigned long SC0_RES_US_V_ON:1; + unsigned long :27; + } BIT; + } SC0_SCL0_US1; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_P_VW:11; + unsigned long :5; + unsigned long SC0_RES_P_VS:11; + unsigned long :5; + } BIT; + } SC0_SCL0_US2; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_P_HW:11; + unsigned long :5; + unsigned long SC0_RES_P_HS:11; + unsigned long :5; + } BIT; + } SC0_SCL0_US3; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_IN_HW:11; + unsigned long :5; + unsigned long SC0_RES_IN_VW:11; + unsigned long :5; + } BIT; + } SC0_SCL0_US4; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_US_H_RATIO:16; + unsigned long :16; + } BIT; + } SC0_SCL0_US5; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_US_HB_INIPHASE:12; + unsigned long :4; + unsigned long SC0_RES_US_HT_INIPHASE:12; + unsigned long SC0_RES_US_H_INTERPOTYP:1; + unsigned long :3; + } BIT; + } SC0_SCL0_US6; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_VCUT:8; + unsigned long SC0_RES_HCUT:8; + unsigned long :16; + } BIT; + } SC0_SCL0_US7; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_DISP_ON:1; + unsigned long :3; + unsigned long SC0_RES_IBUS_SYNC_SEL:1; + unsigned long :27; + } BIT; + } SC0_SCL0_US8; + char wk6[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_BK_COL_B:8; + unsigned long SC0_RES_BK_COL_G:8; + unsigned long SC0_RES_BK_COL_R:8; + unsigned long :8; + } BIT; + } SC0_SCL0_OVR1; + char wk7[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_SCL1_VEN_A:1; + unsigned long :3; + unsigned long SC0_SCL1_VEN_B:1; + unsigned long :11; + unsigned long SC0_SCL1_UPDATE_A:1; + unsigned long :3; + unsigned long SC0_SCL1_UPDATE_B:1; + unsigned long :11; + } BIT; + } SC0_SCL1_UPDATE; + char wk8[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_BST_MD:1; + unsigned long SC0_RES_LOOP:1; + unsigned long SC0_RES_MD:2; + unsigned long SC0_RES_DS_WR_MD:3; + unsigned long SC0_RES_TB_ADD_MOD:1; + unsigned long :8; + unsigned long SC0_RES_WRSWA:3; + unsigned long :13; + } BIT; + } SC0_SCL1_WR1; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_BASE:32; + } BIT; + } SC0_SCL1_WR2; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_FLM_NUM:10; + unsigned long :6; + unsigned long SC0_RES_LN_OFF:15; + unsigned long :1; + } BIT; + } SC0_SCL1_WR3; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_FLM_OFF:23; + unsigned long :9; + } BIT; + } SC0_SCL1_WR4; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_WENB:1; + unsigned long :3; + unsigned long SC0_RES_FLD_SEL:1; + unsigned long :3; + unsigned long SC0_RES_FS_RATE:2; + unsigned long :2; + unsigned long SC0_RES_INTER:1; + unsigned long :19; + } BIT; + } SC0_SCL1_WR5; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_BITDEC_ON:1; + unsigned long :3; + unsigned long SC0_RES_DTH_ON:1; + unsigned long :27; + } BIT; + } SC0_SCL1_WR6; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_FLM_CNT:10; + unsigned long :6; + unsigned long SC0_RES_OVERFLOW:1; + unsigned long :15; + } BIT; + } SC0_SCL1_WR7; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_BASE_B:32; + } BIT; + } SC0_SCL1_WR8; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_FLM_NUM_B:10; + unsigned long :6; + unsigned long SC0_RES_LN_OFF_B:15; + unsigned long :1; + } BIT; + } SC0_SCL1_WR9; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_FLM_OFF_B:23; + unsigned long :9; + } BIT; + } SC0_SCL1_WR10; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_RES_FLM_CNT_B:10; + unsigned long :22; + } BIT; + } SC0_SCL1_WR11; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long SC0_PBUF_NUM:2; + unsigned long :22; + } BIT; + } SC0_SCL1_MON1; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_PBUF0_ADD:32; + } BIT; + } SC0_SCL1_PBUF0; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_PBUF1_ADD:32; + } BIT; + } SC0_SCL1_PBUF1; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_PBUF2_ADD:32; + } BIT; + } SC0_SCL1_PBUF2; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_PBUF3_ADD:32; + } BIT; + } SC0_SCL1_PBUF3; + union + { + unsigned long LONG; + struct + { + unsigned long SC0_FLD_INF0:1; + unsigned long :7; + unsigned long SC0_FLD_INF1:1; + unsigned long :7; + unsigned long SC0_FLD_INF2:1; + unsigned long :7; + unsigned long SC0_FLD_INF3:1; + unsigned long :7; + } BIT; + } SC0_SCL1_PBUF_FLD; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long SC0_PBUF_RST:1; + unsigned long :15; + } BIT; + } SC0_SCL1_PBUF_CNT; + char wk10[44]; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_IBUS_VEN:1; + unsigned long :3; + unsigned long GR0_P_VEN:1; + unsigned long :3; + unsigned long GR0_UPDATE:1; + unsigned long :23; + } BIT; + } GR0_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_R_ENB:1; + unsigned long :31; + } BIT; + } GR0_FLM_RD; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_BST_MD:1; + unsigned long :3; + unsigned long GR0_IMR_FLM_INV:1; + unsigned long :3; + unsigned long GR0_FLM_SEL:2; + unsigned long :6; + unsigned long GR0_LN_OFF_DIR:1; + unsigned long :14; + unsigned long GR0_FLD_SEL:1; + } BIT; + } GR0_FLM1; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_BASE:32; + } BIT; + } GR0_FLM2; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_FLM_NUM:10; + unsigned long :6; + unsigned long GR0_LN_OFF:15; + unsigned long GR0_FLD_NXT:1; + } BIT; + } GR0_FLM3; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_FLM_OFF:23; + unsigned long :9; + } BIT; + } GR0_FLM4; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_FLM_LOOP:11; + unsigned long :5; + unsigned long GR0_FLM_LNUM:11; + unsigned long :5; + } BIT; + } GR0_FLM5; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_STA_POS:6; + unsigned long :2; + unsigned long GR0_CNV444_MD:1; + unsigned long :1; + unsigned long GR0_RDSWA:3; + unsigned long GR0_YCC_SWAP:3; + unsigned long GR0_HW:11; + unsigned long :1; + unsigned long GR0_FORMAT:4; + } BIT; + } GR0_FLM6; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_DISP_SEL:2; + unsigned long :2; + unsigned long GR0_GRC_DISP_ON:1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :9; + unsigned long :1; + unsigned long :1; + unsigned long :4; + unsigned long :1; + unsigned long :3; + } BIT; + } GR0_AB1; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_GRC_VW:11; + unsigned long :5; + unsigned long GR0_GRC_VS:11; + unsigned long :5; + } BIT; + } GR0_AB2; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_GRC_HW:11; + unsigned long :5; + unsigned long GR0_GRC_HS:11; + unsigned long :5; + } BIT; + } GR0_AB3; + char wk11[4]; + char wk12[4]; + char wk13[4]; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_CK_ON:1; + unsigned long :15; + unsigned long :8; + unsigned long :8; + } BIT; + } GR0_AB7; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_CK_KR:8; + unsigned long GR0_CK_KB:8; + unsigned long GR0_CK_KG:8; + unsigned long GR0_CK_KCLUT:8; + } BIT; + } GR0_AB8; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_CK_R:8; + unsigned long GR0_CK_B:8; + unsigned long GR0_CK_G:8; + unsigned long GR0_CK_A:8; + } BIT; + } GR0_AB9; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_R0:8; + unsigned long GR0_B0:8; + unsigned long GR0_G0:8; + unsigned long GR0_A0:8; + } BIT; + } GR0_AB10; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_R1:8; + unsigned long GR0_B1:8; + unsigned long GR0_G1:8; + unsigned long GR0_A1:8; + } BIT; + } GR0_AB11; + union + { + unsigned long LONG; + struct + { + unsigned long GR0_BASE_R:8; + unsigned long GR0_BASE_B:8; + unsigned long GR0_BASE_G:8; + unsigned long :8; + } BIT; + } GR0_BASE; + union + { + unsigned long LONG; + struct + { + unsigned long :11; + unsigned long :5; + unsigned long GR0_CLT_SEL:1; + unsigned long :15; + } BIT; + } GR0_CLUT; + char wk14[4]; + char wk15[40]; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_VEN:1; + unsigned long :31; + } BIT; + } ADJ0_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long BKSTR_T2:5; + unsigned long :3; + unsigned long BKSTR_T1:5; + unsigned long :3; + unsigned long BKSTR_D:4; + unsigned long BKSTR_ST:4; + unsigned long BKSTR_ON:1; + unsigned long :7; + } BIT; + } ADJ0_BKSTR_SET; + union + { + unsigned long LONG; + struct + { + unsigned long ENH_DISP_ON:1; + unsigned long :3; + unsigned long ENH_MD:1; + unsigned long :27; + } BIT; + } ADJ0_ENH_TIM1; + union + { + unsigned long LONG; + struct + { + unsigned long ENH_VW:11; + unsigned long :5; + unsigned long ENH_VS:11; + unsigned long :5; + } BIT; + } ADJ0_ENH_TIM2; + union + { + unsigned long LONG; + struct + { + unsigned long ENH_HW:11; + unsigned long :5; + unsigned long ENH_HS:11; + unsigned long :5; + } BIT; + } ADJ0_ENH_TIM3; + union + { + unsigned long LONG; + struct + { + unsigned long SHP_H1_CORE:7; + unsigned long :9; + unsigned long SHP_H_ON:1; + unsigned long :15; + } BIT; + } ADJ0_ENH_SHP1; + union + { + unsigned long LONG; + struct + { + unsigned long SHP_H1_GAIN_U:8; + unsigned long SHP_H1_GAIN_O:8; + unsigned long SHP_H1_CLIP_U:8; + unsigned long SHP_H1_CLIP_O:8; + } BIT; + } ADJ0_ENH_SHP2; + union + { + unsigned long LONG; + struct + { + unsigned long SHP_H2_CORE:7; + unsigned long :9; + unsigned long SHP_H2_LPF_SEL:1; + unsigned long :15; + } BIT; + } ADJ0_ENH_SHP3; + union + { + unsigned long LONG; + struct + { + unsigned long SHP_H2_GAIN_U:8; + unsigned long SHP_H2_GAIN_O:8; + unsigned long SHP_H2_CLIP_U:8; + unsigned long SHP_H2_CLIP_O:8; + } BIT; + } ADJ0_ENH_SHP4; + union + { + unsigned long LONG; + struct + { + unsigned long SHP_H3_CORE:7; + unsigned long :25; + } BIT; + } ADJ0_ENH_SHP5; + union + { + unsigned long LONG; + struct + { + unsigned long SHP_H3_GAIN_U:8; + unsigned long SHP_H3_GAIN_O:8; + unsigned long SHP_H3_CLIP_U:8; + unsigned long SHP_H3_CLIP_O:8; + } BIT; + } ADJ0_ENH_SHP6; + union + { + unsigned long LONG; + struct + { + unsigned long LTI_H2_CORE:8; + unsigned long LTI_H2_GAIN:8; + unsigned long LTI_H2_INC_ZERO:8; + unsigned long LTI_H2_LPF_SEL:1; + unsigned long :6; + unsigned long LTI_H_ON:1; + } BIT; + } ADJ0_ENH_LTI1; + union + { + unsigned long LONG; + struct + { + unsigned long LTI_H4_CORE:8; + unsigned long LTI_H4_GAIN:8; + unsigned long LTI_H4_INC_ZERO:8; + unsigned long LTI_H4_MEDIAN_TAP_SEL:1; + unsigned long :7; + } BIT; + } ADJ0_ENH_LTI2; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_MTX_MD:2; + unsigned long :30; + } BIT; + } ADJ0_MTX_MODE; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_MTX_GG:11; + unsigned long :5; + unsigned long ADJ0_MTX_YG:8; + unsigned long :8; + } BIT; + } ADJ0_MTX_YG_ADJ0; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_MTX_GR:11; + unsigned long :5; + unsigned long ADJ0_MTX_GB:11; + unsigned long :5; + } BIT; + } ADJ0_MTX_YG_ADJ1; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_MTX_BG:11; + unsigned long :5; + unsigned long ADJ0_MTX_B:8; + unsigned long :8; + } BIT; + } ADJ0_MTX_CBB_ADJ0; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_MTX_BR:11; + unsigned long :5; + unsigned long ADJ0_MTX_BB:11; + unsigned long :5; + } BIT; + } ADJ0_MTX_CBB_ADJ1; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_MTX_RG:11; + unsigned long :5; + unsigned long ADJ0_MTX_R:8; + unsigned long :8; + } BIT; + } ADJ0_MTX_CRR_ADJ0; + union + { + unsigned long LONG; + struct + { + unsigned long ADJ0_MTX_RR:11; + unsigned long :5; + unsigned long ADJ0_MTX_RB:11; + unsigned long :5; + } BIT; + } ADJ0_MTX_CRR_ADJ1; + char wk16[48]; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_IBUS_VEN:1; + unsigned long :3; + unsigned long GR2_P_VEN:1; + unsigned long :3; + unsigned long GR2_UPDATE:1; + unsigned long :23; + } BIT; + } GR2_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_R_ENB:1; + unsigned long :31; + } BIT; + } GR2_FLM_RD; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_BST_MD:1; + unsigned long :7; + unsigned long GR2_FLM_SEL:2; + unsigned long :6; + unsigned long GR2_LN_OFF_DIR:1; + unsigned long :15; + } BIT; + } GR2_FLM1; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_BASE:32; + } BIT; + } GR2_FLM2; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_FLM_NUM:10; + unsigned long :6; + unsigned long GR2_LN_OFF:15; + unsigned long :1; + } BIT; + } GR2_FLM3; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_FLM_OFF:23; + unsigned long :9; + } BIT; + } GR2_FLM4; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_FLM_LOOP:11; + unsigned long :5; + unsigned long GR2_FLM_LNUM:11; + unsigned long :5; + } BIT; + } GR2_FLM5; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_STA_POS:6; + unsigned long :4; + unsigned long GR2_RDSWA:3; + unsigned long :3; + unsigned long GR2_HW:11; + unsigned long :1; + unsigned long GR2_FORMAT:4; + } BIT; + } GR2_FLM6; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_DISP_SEL:2; + unsigned long :2; + unsigned long GR2_GRC_DISP_ON:1; + unsigned long :3; + unsigned long GR2_ARC_DISP_ON:1; + unsigned long :3; + unsigned long GR2_ARC_ON:1; + unsigned long :1; + unsigned long GR2_ACALC_MD:1; + unsigned long GR2_ARC_MUL:1; + unsigned long :16; + } BIT; + } GR2_AB1; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_GRC_VW:11; + unsigned long :5; + unsigned long GR2_GRC_VS:11; + unsigned long :5; + } BIT; + } GR2_AB2; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_GRC_HW:11; + unsigned long :5; + unsigned long GR2_GRC_HS:11; + unsigned long :5; + } BIT; + } GR2_AB3; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_ARC_VW:11; + unsigned long :5; + unsigned long GR2_ARC_VS:11; + unsigned long :5; + } BIT; + } GR2_AB4; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_ARC_HW:11; + unsigned long :5; + unsigned long GR2_ARC_HS:11; + unsigned long :5; + } BIT; + } GR2_AB5; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_ARC_RATE:8; + unsigned long :8; + unsigned long GR2_ARC_COEF:8; + unsigned long GR2_ARC_MODE:1; + unsigned long :7; + } BIT; + } GR2_AB6; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_CK_ON:1; + unsigned long :15; + unsigned long GR2_ARC_DEF:8; + unsigned long :8; + } BIT; + } GR2_AB7; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_CK_KR:8; + unsigned long GR2_CK_KB:8; + unsigned long GR2_CK_KG:8; + unsigned long GR2_CK_KCLUT:8; + } BIT; + } GR2_AB8; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_CK_R:8; + unsigned long GR2_CK_B:8; + unsigned long GR2_CK_G:8; + unsigned long GR2_CK_A:8; + } BIT; + } GR2_AB9; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_R0:8; + unsigned long GR2_B0:8; + unsigned long GR2_G0:8; + unsigned long GR2_A0:8; + } BIT; + } GR2_AB10; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_R1:8; + unsigned long GR2_B1:8; + unsigned long GR2_G1:8; + unsigned long GR2_A1:8; + } BIT; + } GR2_AB11; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_BASE_R:8; + unsigned long GR2_BASE_B:8; + unsigned long GR2_BASE_G:8; + unsigned long :8; + } BIT; + } GR2_BASE; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long GR2_CLT_SEL:1; + unsigned long :15; + } BIT; + } GR2_CLUT; + union + { + unsigned long LONG; + struct + { + unsigned long GR2_ARC_ST:1; + unsigned long :31; + } BIT; + } GR2_MON; + char wk17[40]; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_IBUS_VEN:1; + unsigned long :3; + unsigned long GR3_P_VEN:1; + unsigned long :3; + unsigned long GR3_UPDATE:1; + unsigned long :23; + } BIT; + } GR3_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_R_ENB:1; + unsigned long :31; + } BIT; + } GR3_FLM_RD; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_BST_MD:1; + unsigned long :7; + unsigned long GR3_FLM_SEL:2; + unsigned long :6; + unsigned long GR3_LN_OFF_DIR:1; + unsigned long :15; + } BIT; + } GR3_FLM1; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_BASE:32; + } BIT; + } GR3_FLM2; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_FLM_NUM:10; + unsigned long :6; + unsigned long GR3_LN_OFF:15; + unsigned long :1; + } BIT; + } GR3_FLM3; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_FLM_OFF:23; + unsigned long :9; + } BIT; + } GR3_FLM4; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_FLM_LOOP:11; + unsigned long :5; + unsigned long GR3_FLM_LNUM:11; + unsigned long :5; + } BIT; + } GR3_FLM5; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_STA_POS:6; + unsigned long :4; + unsigned long GR3_RDSWA:3; + unsigned long :3; + unsigned long GR3_HW:11; + unsigned long :1; + unsigned long GR3_FORMAT:4; + } BIT; + } GR3_FLM6; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_DISP_SEL:2; + unsigned long :2; + unsigned long GR3_GRC_DISP_ON:1; + unsigned long :3; + unsigned long GR3_ARC_DISP_ON:1; + unsigned long :3; + unsigned long GR3_ARC_ON:1; + unsigned long :1; + unsigned long GR3_ACALC_MD:1; + unsigned long GR3_ARC_MUL:1; + unsigned long :16; + } BIT; + } GR3_AB1; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_GRC_VW:11; + unsigned long :5; + unsigned long GR3_GRC_VS:11; + unsigned long :5; + } BIT; + } GR3_AB2; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_GRC_HW:11; + unsigned long :5; + unsigned long GR3_GRC_HS:11; + unsigned long :5; + } BIT; + } GR3_AB3; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_ARC_VW:11; + unsigned long :5; + unsigned long GR3_ARC_VS:11; + unsigned long :5; + } BIT; + } GR3_AB4; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_ARC_HW:11; + unsigned long :5; + unsigned long GR3_ARC_HS:11; + unsigned long :5; + } BIT; + } GR3_AB5; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_ARC_RATE:8; + unsigned long :8; + unsigned long GR3_ARC_COEF:8; + unsigned long GR3_ARC_MODE:1; + unsigned long :7; + } BIT; + } GR3_AB6; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_CK_ON:1; + unsigned long :15; + unsigned long GR3_ARC_DEF:8; + unsigned long :8; + } BIT; + } GR3_AB7; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_CK_KR:8; + unsigned long GR3_CK_KB:8; + unsigned long GR3_CK_KG:8; + unsigned long GR3_CK_KCLUT:8; + } BIT; + } GR3_AB8; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_CK_R:8; + unsigned long GR3_CK_B:8; + unsigned long GR3_CK_G:8; + unsigned long GR3_CK_A:8; + } BIT; + } GR3_AB9; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_R0:8; + unsigned long GR3_B0:8; + unsigned long GR3_G0:8; + unsigned long GR3_A0:8; + } BIT; + } GR3_AB10; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_R1:8; + unsigned long GR3_B1:8; + unsigned long GR3_G1:8; + unsigned long GR3_A1:8; + } BIT; + } GR3_AB11; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_BASE_R:8; + unsigned long GR3_BASE_B:8; + unsigned long GR3_BASE_G:8; + unsigned long :8; + } BIT; + } GR3_BASE; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_LINE:11; + unsigned long :5; + unsigned long GR3_CLT_SEL:1; + unsigned long :15; + } BIT; + } GR3_CLUT_INT; + union + { + unsigned long LONG; + struct + { + unsigned long GR3_ARC_ST:1; + unsigned long :15; + unsigned long GR3_LIN_STAT:11; + unsigned long :5; + } BIT; + } GR3_MON; + char wk18[40]; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_VEN:1; + unsigned long :31; + } BIT; + } GAM_G_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_ON:1; + unsigned long :31; + } BIT; + } GAM_SW; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_01:11; + unsigned long :5; + unsigned long GAM_G_GAIN_00:11; + unsigned long :5; + } BIT; + } GAM_G_LUT1; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_03:11; + unsigned long :5; + unsigned long GAM_G_GAIN_02:11; + unsigned long :5; + } BIT; + } GAM_G_LUT2; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_05:11; + unsigned long :5; + unsigned long GAM_G_GAIN_04:11; + unsigned long :5; + } BIT; + } GAM_G_LUT3; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_07:11; + unsigned long :5; + unsigned long GAM_G_GAIN_06:11; + unsigned long :5; + } BIT; + } GAM_G_LUT4; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_09:11; + unsigned long :5; + unsigned long GAM_G_GAIN_08:11; + unsigned long :5; + } BIT; + } GAM_G_LUT5; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_11:11; + unsigned long :5; + unsigned long GAM_G_GAIN_10:11; + unsigned long :5; + } BIT; + } GAM_G_LUT6; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_13:11; + unsigned long :5; + unsigned long GAM_G_GAIN_12:11; + unsigned long :5; + } BIT; + } GAM_G_LUT7; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_15:11; + unsigned long :5; + unsigned long GAM_G_GAIN_14:11; + unsigned long :5; + } BIT; + } GAM_G_LUT8; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_17:11; + unsigned long :5; + unsigned long GAM_G_GAIN_16:11; + unsigned long :5; + } BIT; + } GAM_G_LUT9; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_19:11; + unsigned long :5; + unsigned long GAM_G_GAIN_18:11; + unsigned long :5; + } BIT; + } GAM_G_LUT10; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_21:11; + unsigned long :5; + unsigned long GAM_G_GAIN_20:11; + unsigned long :5; + } BIT; + } GAM_G_LUT11; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_23:11; + unsigned long :5; + unsigned long GAM_G_GAIN_22:11; + unsigned long :5; + } BIT; + } GAM_G_LUT12; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_25:11; + unsigned long :5; + unsigned long GAM_G_GAIN_24:11; + unsigned long :5; + } BIT; + } GAM_G_LUT13; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_27:11; + unsigned long :5; + unsigned long GAM_G_GAIN_26:11; + unsigned long :5; + } BIT; + } GAM_G_LUT14; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_29:11; + unsigned long :5; + unsigned long GAM_G_GAIN_28:11; + unsigned long :5; + } BIT; + } GAM_G_LUT15; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_GAIN_31:11; + unsigned long :5; + unsigned long GAM_G_GAIN_30:11; + unsigned long :5; + } BIT; + } GAM_G_LUT16; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_03:8; + unsigned long GAM_G_TH_02:8; + unsigned long GAM_G_TH_01:8; + unsigned long :8; + } BIT; + } GAM_G_AREA1; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_07:8; + unsigned long GAM_G_TH_06:8; + unsigned long GAM_G_TH_05:8; + unsigned long GAM_G_TH_04:8; + } BIT; + } GAM_G_AREA2; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_11:8; + unsigned long GAM_G_TH_10:8; + unsigned long GAM_G_TH_09:8; + unsigned long GAM_G_TH_08:8; + } BIT; + } GAM_G_AREA3; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_15:8; + unsigned long GAM_G_TH_14:8; + unsigned long GAM_G_TH_13:8; + unsigned long GAM_G_TH_12:8; + } BIT; + } GAM_G_AREA4; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_19:8; + unsigned long GAM_G_TH_18:8; + unsigned long GAM_G_TH_17:8; + unsigned long GAM_G_TH_16:8; + } BIT; + } GAM_G_AREA5; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_23:8; + unsigned long GAM_G_TH_22:8; + unsigned long GAM_G_TH_21:8; + unsigned long GAM_G_TH_20:8; + } BIT; + } GAM_G_AREA6; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_27:8; + unsigned long GAM_G_TH_26:8; + unsigned long GAM_G_TH_25:8; + unsigned long GAM_G_TH_24:8; + } BIT; + } GAM_G_AREA7; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_G_TH_31:8; + unsigned long GAM_G_TH_30:8; + unsigned long GAM_G_TH_29:8; + unsigned long GAM_G_TH_28:8; + } BIT; + } GAM_G_AREA8; + char wk19[24]; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_VEN:1; + unsigned long :31; + } BIT; + } GAM_B_UPDATE; + char wk20[4]; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_01:11; + unsigned long :5; + unsigned long GAM_B_GAIN_00:11; + unsigned long :5; + } BIT; + } GAM_B_LUT1; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_03:11; + unsigned long :5; + unsigned long GAM_B_GAIN_02:11; + unsigned long :5; + } BIT; + } GAM_B_LUT2; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_05:11; + unsigned long :5; + unsigned long GAM_B_GAIN_04:11; + unsigned long :5; + } BIT; + } GAM_B_LUT3; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_07:11; + unsigned long :5; + unsigned long GAM_B_GAIN_06:11; + unsigned long :5; + } BIT; + } GAM_B_LUT4; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_09:11; + unsigned long :5; + unsigned long GAM_B_GAIN_08:11; + unsigned long :5; + } BIT; + } GAM_B_LUT5; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_11:11; + unsigned long :5; + unsigned long GAM_B_GAIN_10:11; + unsigned long :5; + } BIT; + } GAM_B_LUT6; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_13:11; + unsigned long :5; + unsigned long GAM_B_GAIN_12:11; + unsigned long :5; + } BIT; + } GAM_B_LUT7; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_15:11; + unsigned long :5; + unsigned long GAM_B_GAIN_14:11; + unsigned long :5; + } BIT; + } GAM_B_LUT8; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_17:11; + unsigned long :5; + unsigned long GAM_B_GAIN_16:11; + unsigned long :5; + } BIT; + } GAM_B_LUT9; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_19:11; + unsigned long :5; + unsigned long GAM_B_GAIN_18:11; + unsigned long :5; + } BIT; + } GAM_B_LUT10; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_21:11; + unsigned long :5; + unsigned long GAM_B_GAIN_20:11; + unsigned long :5; + } BIT; + } GAM_B_LUT11; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_23:11; + unsigned long :5; + unsigned long GAM_B_GAIN_22:11; + unsigned long :5; + } BIT; + } GAM_B_LUT12; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_25:11; + unsigned long :5; + unsigned long GAM_B_GAIN_24:11; + unsigned long :5; + } BIT; + } GAM_B_LUT13; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_27:11; + unsigned long :5; + unsigned long GAM_B_GAIN_26:11; + unsigned long :5; + } BIT; + } GAM_B_LUT14; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_29:11; + unsigned long :5; + unsigned long GAM_B_GAIN_28:11; + unsigned long :5; + } BIT; + } GAM_B_LUT15; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_GAIN_31:11; + unsigned long :5; + unsigned long GAM_B_GAIN_30:11; + unsigned long :5; + } BIT; + } GAM_B_LUT16; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_03:8; + unsigned long GAM_B_TH_02:8; + unsigned long GAM_B_TH_01:8; + unsigned long :8; + } BIT; + } GAM_B_AREA1; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_07:8; + unsigned long GAM_B_TH_06:8; + unsigned long GAM_B_TH_05:8; + unsigned long GAM_B_TH_04:8; + } BIT; + } GAM_B_AREA2; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_11:8; + unsigned long GAM_B_TH_10:8; + unsigned long GAM_B_TH_09:8; + unsigned long GAM_B_TH_08:8; + } BIT; + } GAM_B_AREA3; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_15:8; + unsigned long GAM_B_TH_14:8; + unsigned long GAM_B_TH_13:8; + unsigned long GAM_B_TH_12:8; + } BIT; + } GAM_B_AREA4; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_19:8; + unsigned long GAM_B_TH_18:8; + unsigned long GAM_B_TH_17:8; + unsigned long GAM_B_TH_16:8; + } BIT; + } GAM_B_AREA5; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_23:8; + unsigned long GAM_B_TH_22:8; + unsigned long GAM_B_TH_21:8; + unsigned long GAM_B_TH_20:8; + } BIT; + } GAM_B_AREA6; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_27:8; + unsigned long GAM_B_TH_26:8; + unsigned long GAM_B_TH_25:8; + unsigned long GAM_B_TH_24:8; + } BIT; + } GAM_B_AREA7; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_B_TH_31:8; + unsigned long GAM_B_TH_30:8; + unsigned long GAM_B_TH_29:8; + unsigned long GAM_B_TH_28:8; + } BIT; + } GAM_B_AREA8; + char wk21[24]; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_VEN:1; + unsigned long :31; + } BIT; + } GAM_R_UPDATE; + char wk22[4]; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_01:11; + unsigned long :5; + unsigned long GAM_R_GAIN_00:11; + unsigned long :5; + } BIT; + } GAM_R_LUT1; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_03:11; + unsigned long :5; + unsigned long GAM_R_GAIN_02:11; + unsigned long :5; + } BIT; + } GAM_R_LUT2; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_05:11; + unsigned long :5; + unsigned long GAM_R_GAIN_04:11; + unsigned long :5; + } BIT; + } GAM_R_LUT3; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_07:11; + unsigned long :5; + unsigned long GAM_R_GAIN_06:11; + unsigned long :5; + } BIT; + } GAM_R_LUT4; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_09:11; + unsigned long :5; + unsigned long GAM_R_GAIN_08:11; + unsigned long :5; + } BIT; + } GAM_R_LUT5; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_11:11; + unsigned long :5; + unsigned long GAM_R_GAIN_10:11; + unsigned long :5; + } BIT; + } GAM_R_LUT6; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_13:11; + unsigned long :5; + unsigned long GAM_R_GAIN_12:11; + unsigned long :5; + } BIT; + } GAM_R_LUT7; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_15:11; + unsigned long :5; + unsigned long GAM_R_GAIN_14:11; + unsigned long :5; + } BIT; + } GAM_R_LUT8; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_17:11; + unsigned long :5; + unsigned long GAM_R_GAIN_16:11; + unsigned long :5; + } BIT; + } GAM_R_LUT9; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_19:11; + unsigned long :5; + unsigned long GAM_R_GAIN_18:11; + unsigned long :5; + } BIT; + } GAM_R_LUT10; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_21:11; + unsigned long :5; + unsigned long GAM_R_GAIN_20:11; + unsigned long :5; + } BIT; + } GAM_R_LUT11; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_23:11; + unsigned long :5; + unsigned long GAM_R_GAIN_22:11; + unsigned long :5; + } BIT; + } GAM_R_LUT12; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_25:11; + unsigned long :5; + unsigned long GAM_R_GAIN_24:11; + unsigned long :5; + } BIT; + } GAM_R_LUT13; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_27:11; + unsigned long :5; + unsigned long GAM_R_GAIN_26:11; + unsigned long :5; + } BIT; + } GAM_R_LUT14; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_29:11; + unsigned long :5; + unsigned long GAM_R_GAIN_28:11; + unsigned long :5; + } BIT; + } GAM_R_LUT15; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_GAIN_31:11; + unsigned long :5; + unsigned long GAM_R_GAIN_30:11; + unsigned long :5; + } BIT; + } GAM_R_LUT16; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_03:8; + unsigned long GAM_R_TH_02:8; + unsigned long GAM_R_TH_01:8; + unsigned long :8; + } BIT; + } GAM_R_AREA1; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_07:8; + unsigned long GAM_R_TH_06:8; + unsigned long GAM_R_TH_05:8; + unsigned long GAM_R_TH_04:8; + } BIT; + } GAM_R_AREA2; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_11:8; + unsigned long GAM_R_TH_10:8; + unsigned long GAM_R_TH_09:8; + unsigned long GAM_R_TH_08:8; + } BIT; + } GAM_R_AREA3; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_15:8; + unsigned long GAM_R_TH_14:8; + unsigned long GAM_R_TH_13:8; + unsigned long GAM_R_TH_12:8; + } BIT; + } GAM_R_AREA4; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_19:8; + unsigned long GAM_R_TH_18:8; + unsigned long GAM_R_TH_17:8; + unsigned long GAM_R_TH_16:8; + } BIT; + } GAM_R_AREA5; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_23:8; + unsigned long GAM_R_TH_22:8; + unsigned long GAM_R_TH_21:8; + unsigned long GAM_R_TH_20:8; + } BIT; + } GAM_R_AREA6; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_27:8; + unsigned long GAM_R_TH_26:8; + unsigned long GAM_R_TH_25:8; + unsigned long GAM_R_TH_24:8; + } BIT; + } GAM_R_AREA7; + union + { + unsigned long LONG; + struct + { + unsigned long GAM_R_TH_31:8; + unsigned long GAM_R_TH_30:8; + unsigned long GAM_R_TH_29:8; + unsigned long GAM_R_TH_28:8; + } BIT; + } GAM_R_AREA8; + char wk23[24]; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_VEN:1; + unsigned long :31; + } BIT; + } TCON_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_OFFSET:11; + unsigned long :5; + unsigned long TCON_HALF:11; + unsigned long :5; + } BIT; + } TCON_TIM; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STVA_VW:11; + unsigned long :5; + unsigned long TCON_STVA_VS:11; + unsigned long :5; + } BIT; + } TCON_TIM_STVA1; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STVA_SEL:3; + unsigned long :1; + unsigned long TCON_STVA_INV:1; + unsigned long :27; + } BIT; + } TCON_TIM_STVA2; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STVB_VW:11; + unsigned long :5; + unsigned long TCON_STVB_VS:11; + unsigned long :5; + } BIT; + } TCON_TIM_STVB1; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STVB_SEL:3; + unsigned long :1; + unsigned long TCON_STVB_INV:1; + unsigned long :27; + } BIT; + } TCON_TIM_STVB2; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STH_HW:11; + unsigned long :5; + unsigned long TCON_STH_HS:11; + unsigned long :5; + } BIT; + } TCON_TIM_STH1; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STH_SEL:3; + unsigned long :1; + unsigned long TCON_STH_INV:1; + unsigned long :3; + unsigned long TCON_STH_HS_SEL:1; + unsigned long :23; + } BIT; + } TCON_TIM_STH2; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STB_HW:11; + unsigned long :5; + unsigned long TCON_STB_HS:11; + unsigned long :5; + } BIT; + } TCON_TIM_STB1; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_STB_SEL:3; + unsigned long :1; + unsigned long TCON_STB_INV:1; + unsigned long :3; + unsigned long TCON_STB_HS_SEL:1; + unsigned long :23; + } BIT; + } TCON_TIM_STB2; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_CPV_HW:11; + unsigned long :5; + unsigned long TCON_CPV_HS:11; + unsigned long :5; + } BIT; + } TCON_TIM_CPV1; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_CPV_SEL:3; + unsigned long :1; + unsigned long TCON_CPV_INV:1; + unsigned long :3; + unsigned long TCON_CPV_HS_SEL:1; + unsigned long :23; + } BIT; + } TCON_TIM_CPV2; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_POLA_HW:11; + unsigned long :5; + unsigned long TCON_POLA_HS:11; + unsigned long :5; + } BIT; + } TCON_TIM_POLA1; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_POLA_SEL:3; + unsigned long :1; + unsigned long TCON_POLA_INV:1; + unsigned long :3; + unsigned long TCON_POLA_HS_SEL:1; + unsigned long :3; + unsigned long TCON_POLA_MD:2; + unsigned long :18; + } BIT; + } TCON_TIM_POLA2; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_POLB_HW:11; + unsigned long :5; + unsigned long TCON_POLB_HS:11; + unsigned long :5; + } BIT; + } TCON_TIM_POLB1; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_POLB_SEL:3; + unsigned long :1; + unsigned long TCON_POLB_INV:1; + unsigned long :3; + unsigned long TCON_POLB_HS_SEL:1; + unsigned long :3; + unsigned long TCON_POLB_MD:2; + unsigned long :18; + } BIT; + } TCON_TIM_POLB2; + union + { + unsigned long LONG; + struct + { + unsigned long TCON_DE_INV:1; + unsigned long :31; + } BIT; + } TCON_TIM_DE; + char wk24[60]; + union + { + unsigned long LONG; + struct + { + unsigned long OUTCNT_VEN:1; + unsigned long :31; + } BIT; + } OUT_UPDATE; + union + { + unsigned long LONG; + struct + { + unsigned long OUT_PHASE:2; + unsigned long :2; + unsigned long OUT_DIR_SEL:1; + unsigned long :3; + unsigned long OUT_FRQ_SEL:2; + unsigned long :2; + unsigned long OUT_FORMAT:2; + unsigned long :2; + unsigned long :5; + unsigned long :2; + unsigned long :1; + unsigned long OUT_SWAP_ON:1; + unsigned long :3; + unsigned long OUT_ENDIAN_ON:1; + unsigned long :3; + } BIT; + } OUT_SET; + union + { + unsigned long LONG; + struct + { + unsigned long PBRT_G:10; + unsigned long :22; + } BIT; + } OUT_BRIGHT1; + union + { + unsigned long LONG; + struct + { + unsigned long PBRT_R:10; + unsigned long :6; + unsigned long PBRT_B:10; + unsigned long :6; + } BIT; + } OUT_BRIGHT2; + union + { + unsigned long LONG; + struct + { + unsigned long CONT_R:8; + unsigned long CONT_B:8; + unsigned long CONT_G:8; + unsigned long :8; + } BIT; + } OUT_CONTRAST; + union + { + unsigned long LONG; + struct + { + unsigned long PDTH_PD:2; + unsigned long :2; + unsigned long PDTH_PC:2; + unsigned long :2; + unsigned long PDTH_PB:2; + unsigned long :2; + unsigned long PDTH_PA:2; + unsigned long :2; + unsigned long PDTH_FORMAT:2; + unsigned long :2; + unsigned long PDTH_SEL:2; + unsigned long :10; + } BIT; + } OUT_PDTHA; + char wk25[12]; + union + { + unsigned long LONG; + struct + { + unsigned long OUTCNT_POLB_EDGE:1; + unsigned long OUTCNT_POLA_EDGE:1; + unsigned long OUTCNT_CPV_EDGE:1; + unsigned long OUTCNT_STB_EDGE:1; + unsigned long OUTCNT_STH_EDGE:1; + unsigned long OUTCNT_STVB_EDGE:1; + unsigned long OUTCNT_STVA_EDGE:1; + unsigned long :1; + unsigned long OUTCNT_LCD_EDGE:1; + unsigned long :3; + unsigned long OUTCNT_FRONT_GAM:1; + unsigned long :19; + } BIT; + } OUT_CLK_PHASE; + char wk26[88]; + union + { + unsigned long LONG; + struct + { + unsigned long INT_STA0:1; + unsigned long :3; + unsigned long INT_STA1:1; + unsigned long :3; + unsigned long INT_STA2:1; + unsigned long :3; + unsigned long INT_STA3:1; + unsigned long :3; + unsigned long INT_STA4:1; + unsigned long :3; + unsigned long INT_STA5:1; + unsigned long :3; + unsigned long INT_STA6:1; + unsigned long :3; + unsigned long INT_STA7:1; + unsigned long :3; + } BIT; + } SYSCNT_INT1; + union + { + unsigned long LONG; + struct + { + unsigned long INT_STA8:1; + unsigned long :3; + unsigned long INT_STA9:1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + } BIT; + } SYSCNT_INT2; + char wk27[4]; + union + { + unsigned long LONG; + struct + { + unsigned long INT_OUT0_ON:1; + unsigned long :3; + unsigned long INT_OUT1_ON:1; + unsigned long :3; + unsigned long INT_OUT2_ON:1; + unsigned long :3; + unsigned long INT_OUT3_ON:1; + unsigned long :3; + unsigned long INT_OUT4_ON:1; + unsigned long :3; + unsigned long INT_OUT5_ON:1; + unsigned long :3; + unsigned long INT_OUT6_ON:1; + unsigned long :3; + unsigned long INT_OUT7_ON:1; + unsigned long :3; + } BIT; + } SYSCNT_INT4; + union + { + unsigned long LONG; + struct + { + unsigned long INT_OUT8_ON:1; + unsigned long :3; + unsigned long INT_OUT9_ON:1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + } BIT; + } SYSCNT_INT5; + char wk28[4]; + union + { + unsigned short WORD; + struct + { + unsigned short PANEL_DCDR:6; + unsigned short :2; + unsigned short PANEL_ICKEN:1; + unsigned short :1; + unsigned short PANEL_OCKSEL:2; + unsigned short PANEL_ICKSEL:2; + unsigned short :2; + } BIT; + } SYSCNT_PANEL_CLK; + union + { + unsigned short WORD; + struct + { + unsigned short GR0_CLT_SEL_ST:1; + unsigned short :3; + unsigned short :1; + unsigned short :3; + unsigned short GR2_CLT_SEL_ST:1; + unsigned short :3; + unsigned short GR3_CLT_SEL_ST:1; + unsigned short :1; + unsigned short :1; + unsigned short :1; + } BIT; + } SYSCNT_CLUT; + char wk29[356]; + char wk30[4]; + char wk31[4]; + char wk32[4]; + char wk33[4]; + char wk34[4]; + char wk35[4]; + char wk36[4]; + char wk37[4]; + char wk38[4]; + char wk39[4]; + char wk40[2]; + char wk41[2]; + char wk42[4]; + char wk43[4]; + char wk44[4]; + char wk45[4]; + char wk46[4]; + char wk47[4]; + char wk48[4]; + char wk49[4]; + char wk50[4]; + char wk51[4]; + char wk52[4]; + char wk53[4]; + char wk54[4]; + char wk55[4]; + char wk56[4]; + char wk57[4]; + char wk58[4]; + char wk59[16]; + char wk60[4]; + char wk61[4]; + char wk62[4]; + char wk63[4]; + char wk64[4]; + char wk65[4]; + char wk66[4]; + char wk67[4]; + char wk68[4]; + char wk69[4]; + char wk70[4]; + char wk71[4]; + char wk72[4]; + char wk73[4]; + char wk74[4]; + char wk75[4]; + char wk76[4]; + char wk77[4]; + char wk78[4]; + char wk79[4]; + char wk80[4]; + char wk81[44]; + char wk82[4]; + char wk83[4]; + char wk84[4]; + char wk85[4]; + char wk86[4]; + char wk87[4]; + char wk88[4]; + char wk89[4]; + char wk90[4]; + char wk91[4]; + char wk92[4]; + char wk93[4]; + char wk94[4]; + char wk95[4]; + char wk96[4]; + char wk97[4]; + char wk98[4]; + char wk99[4]; + char wk100[4]; + char wk101[4]; + char wk102[4]; + char wk103[4]; + char wk104[40]; + char wk105[4]; + char wk106[4]; + char wk107[4]; + char wk108[4]; + char wk109[4]; + char wk110[4]; + char wk111[4]; + char wk112[4]; + char wk113[4]; + char wk114[4]; + char wk115[4]; + char wk116[4]; + char wk117[4]; + char wk118[4]; + char wk119[4]; + char wk120[4]; + char wk121[4]; + char wk122[4]; + char wk123[4]; + char wk124[4]; + char wk125[48]; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long GR_VIN_P_VEN:1; + unsigned long :3; + unsigned long GR_VIN_UPDATE:1; + unsigned long :23; + } BIT; + } GR_VIN_UPDATE; + char wk126[28]; + union + { + unsigned long LONG; + struct + { + unsigned long GR_VIN_DISP_SEL:2; + unsigned long GR_VIN_SCL_UND_SEL:1; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :19; + } BIT; + } GR_VIN_AB1; + char wk127[4]; + char wk128[4]; + char wk129[4]; + char wk130[4]; + char wk131[4]; + char wk132[4]; + char wk133[16]; + char wk134[4]; + char wk135[4]; + char wk136[4]; + char wk137[40]; + char wk138[4]; + char wk139[4]; + char wk140[4]; + char wk141[4]; + char wk142[4]; + char wk143[4]; + char wk144[4]; + char wk145[4]; + char wk146[4]; + char wk147[4]; + char wk148[2]; + char wk149[2]; + char wk150[4]; + char wk151[4]; + char wk152[4]; + char wk153[4]; + char wk154[4]; + char wk155[4]; + char wk156[4]; + char wk157[4]; + char wk158[4]; + char wk159[4]; + char wk160[4]; + char wk161[4]; + char wk162[4]; + char wk163[4]; + char wk164[4]; + char wk165[4]; + char wk166[4]; + char wk167[16]; + char wk168[4]; + char wk169[4]; + char wk170[4]; + char wk171[4]; + char wk172[4]; + char wk173[4]; + char wk174[4]; + char wk175[4]; + char wk176[4]; + char wk177[4]; + char wk178[4]; + char wk179[4]; + char wk180[4]; + char wk181[4]; + char wk182[4]; + char wk183[4]; + char wk184[4]; + char wk185[4]; + char wk186[4]; + char wk187[4]; + char wk188[4]; + char wk189[44]; + char wk190[4]; + char wk191[4]; + char wk192[4]; + char wk193[4]; + char wk194[4]; + char wk195[4]; + char wk196[4]; + char wk197[4]; + char wk198[4]; + char wk199[4]; + char wk200[4]; + char wk201[4]; + char wk202[4]; + char wk203[4]; + char wk204[4]; + char wk205[4]; + char wk206[4]; + char wk207[4]; + char wk208[4]; + char wk209[4]; + char wk210[4]; + char wk211[4]; +}; + +#define VDC6 (*(volatile struct st_vdc *)0xFCFF7400) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vin_iodefine.h new file mode 100644 index 0000000..4e47d7e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/vin_iodefine.h @@ -0,0 +1,574 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef VIN_IODEFINE_H +#define VIN_IODEFINE_H + +struct st_vin +{ + union + { + unsigned long LONG; + struct + { + unsigned long ME:1; + unsigned long BPS:1; + unsigned long :1; + unsigned long IM:2; + unsigned long :1; + unsigned long EN:1; + unsigned long :3; + unsigned long :1; + unsigned long :1; + unsigned long :2; + unsigned long DC:2; + unsigned long INF:3; + unsigned long YCAL:1; + unsigned long LUTE:1; + unsigned long :1; + unsigned long :4; + unsigned long SCLE:1; + unsigned long :1; + unsigned long CLP:2; + unsigned long :2; + } BIT; + } V0MC; + union + { + unsigned long LONG; + struct + { + unsigned long CA:1; + unsigned long AV:1; + unsigned long FS:1; + unsigned long FBS:2; + unsigned long :27; + } BIT; + } V0MS; + union + { + unsigned long LONG; + struct + { + unsigned long SC:1; + unsigned long CC:1; + unsigned long :30; + } BIT; + } V0FC; + union + { + unsigned long LONG; + struct + { + unsigned long SLPrC:11; + unsigned long :1; + unsigned long :20; + } BIT; + } V0SLPrC; + union + { + unsigned long LONG; + struct + { + unsigned long ELPrC:11; + unsigned long :1; + unsigned long :20; + } BIT; + } V0ELPrC; + union + { + unsigned long LONG; + struct + { + unsigned long SPPrC:11; + unsigned long :1; + unsigned long :20; + } BIT; + } V0SPPrC; + union + { + unsigned long LONG; + struct + { + unsigned long EPPrC:11; + unsigned long :1; + unsigned long :20; + } BIT; + } V0EPPrC; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long :21; + unsigned long DES0:1; + unsigned long :1; + unsigned long :5; + } BIT; + } V0CSI_IFMD; + char wk1[8]; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long IS:9; + unsigned long :19; + } BIT; + } V0IS; + union + { + unsigned long LONG; + struct + { + unsigned long :7; + unsigned long MB1:25; + } BIT; + } V0MB1; + union + { + unsigned long LONG; + struct + { + unsigned long :7; + unsigned long MB2:25; + } BIT; + } V0MB2; + union + { + unsigned long LONG; + struct + { + unsigned long :7; + unsigned long MB3:25; + } BIT; + } V0MB3; + union + { + unsigned long LONG; + struct + { + unsigned long LC:12; + unsigned long :20; + } BIT; + } V0LC; + union + { + unsigned long LONG; + struct + { + unsigned long FOE:1; + unsigned long EFE:1; + unsigned long SIE:1; + unsigned long :1; + unsigned long FIE:1; + unsigned long :11; + unsigned long VRE:1; + unsigned long VFE:1; + unsigned long :13; + unsigned long FIE2:1; + } BIT; + } V0IE; + union + { + unsigned long LONG; + struct + { + unsigned long FOS:1; + unsigned long EFS:1; + unsigned long SIS:1; + unsigned long :1; + unsigned long FIS:1; + unsigned long :11; + unsigned long VRS:1; + unsigned long VFS:1; + unsigned long :13; + unsigned long FIS2:1; + } BIT; + } V0INTS; + union + { + unsigned long LONG; + struct + { + unsigned long SI:11; + unsigned long :21; + } BIT; + } V0SI; + char wk2[12]; + union + { + unsigned long LONG; + struct + { + unsigned long DTMD:2; + unsigned long ABIT:1; + unsigned long :1; + unsigned long BPSM:1; + unsigned long :3; + unsigned long EXRGB:1; + unsigned long :2; + unsigned long YC_THR:1; + unsigned long YMODE:3; + unsigned long :1; + unsigned long EVA:1; + unsigned long :7; + unsigned long A8BIT:8; + } BIT; + } V0DMR; + union + { + unsigned long LONG; + struct + { + unsigned long HLV:11; + unsigned long :1; + unsigned long VLV:4; + unsigned long FTEH:1; + unsigned long FTEV:1; + unsigned long :4; + unsigned long :1; + unsigned long :1; + unsigned long :3; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + unsigned long :1; + } BIT; + } V0DMR2; + union + { + unsigned long LONG; + struct + { + unsigned long :7; + unsigned long UVAOF:25; + } BIT; + } V0UVAOF; + union + { + unsigned long LONG; + struct + { + unsigned long CSUB:8; + unsigned long YSUB:8; + unsigned long YMUL:10; + unsigned long :6; + } BIT; + } V0CSCC1; + union + { + unsigned long LONG; + struct + { + unsigned long GCRMUL:10; + unsigned long :6; + unsigned long RCRMUL:10; + unsigned long :6; + } BIT; + } V0CSCC2; + union + { + unsigned long LONG; + struct + { + unsigned long BCBMUL:10; + unsigned long :6; + unsigned long GCBMUL:10; + unsigned long :6; + } BIT; + } V0CSCC3; + char wk3[16]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long :1; + unsigned long :14; + unsigned long NE_BCB:1; + unsigned long NE_GY:1; + unsigned long NE_RCR:1; + unsigned long :1; + unsigned long BC:1; + unsigned long :7; + unsigned long :1; + unsigned long :1; + unsigned long AMD:1; + unsigned long :1; + } BIT; + } V0UDS_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long VFRAC:12; + unsigned long VMANT:4; + unsigned long HFRAC:12; + unsigned long HMANT:4; + } BIT; + } V0UDS_SCALE; + char wk4[8]; + union + { + unsigned long LONG; + struct + { + unsigned long BWIDTH_V:7; + unsigned long :9; + unsigned long BWIDTH_H:7; + unsigned long :9; + } BIT; + } V0UDS_PASS_BWIDTH; + char wk5[4]; + char wk6[4]; + char wk7[8]; + union + { + unsigned long LONG; + struct + { + unsigned long CL_VSIZE:12; + unsigned long :4; + unsigned long CL_HSIZE:12; + unsigned long :4; + } BIT; + } V0UDS_CLIP_SIZE; + char wk8[88]; + union + { + unsigned long LONG; + struct + { + unsigned long LTCRPR:10; + unsigned long LTCBPR:10; + unsigned long LTYPR:10; + unsigned long :2; + } BIT; + } V0LUTP; + union + { + unsigned long LONG; + struct + { + unsigned long LTCRDT:8; + unsigned long LTCBDT:8; + unsigned long LTYDT:8; + unsigned long :8; + } BIT; + } V0LUTD; + char wk9[288]; + union + { + unsigned long LONG; + struct + { + unsigned long YCLRP:13; + unsigned long :19; + } BIT; + } V0YCCR1; + union + { + unsigned long LONG; + struct + { + unsigned long YCLGP:13; + unsigned long :3; + unsigned long YCLBP:13; + unsigned long :3; + } BIT; + } V0YCCR2; + union + { + unsigned long LONG; + struct + { + unsigned long YCLAP:12; + unsigned long :4; + unsigned long YCLCEN:1; + unsigned long :6; + unsigned long YCLHEN:1; + unsigned long YCLSFT:5; + unsigned long :2; + unsigned long YEXPEN:1; + } BIT; + } V0YCCR3; + union + { + unsigned long LONG; + struct + { + unsigned long CBCLRP:13; + unsigned long :19; + } BIT; + } V0CBCCR1; + union + { + unsigned long LONG; + struct + { + unsigned long CBCLGP:13; + unsigned long :3; + unsigned long CBCLBP:13; + unsigned long :3; + } BIT; + } V0CBCCR2; + union + { + unsigned long LONG; + struct + { + unsigned long CBCLAP:12; + unsigned long :4; + unsigned long CBCLCEN:1; + unsigned long :6; + unsigned long CBCLHEN:1; + unsigned long CBCLSFT:5; + unsigned long :2; + unsigned long CBEXPEN:1; + } BIT; + } V0CBCCR3; + union + { + unsigned long LONG; + struct + { + unsigned long CRCLRP:13; + unsigned long :19; + } BIT; + } V0CRCCR1; + union + { + unsigned long LONG; + struct + { + unsigned long CRCLGP:13; + unsigned long :3; + unsigned long CRCLBP:13; + unsigned long :3; + } BIT; + } V0CRCCR2; + union + { + unsigned long LONG; + struct + { + unsigned long CRCLAP:12; + unsigned long :4; + unsigned long CRCLCEN:1; + unsigned long :6; + unsigned long CRCLHEN:1; + unsigned long CRCLSFT:5; + unsigned long :2; + unsigned long CREXPEN:1; + } BIT; + } V0CRCCR3; + char wk10[180]; + union + { + unsigned long LONG; + struct + { + unsigned long YMUL2:14; + unsigned long :18; + } BIT; + } V0CSCE1; + union + { + unsigned long LONG; + struct + { + unsigned long CSUB2:12; + unsigned long :4; + unsigned long YSUB2:12; + unsigned long :4; + } BIT; + } V0CSCE2; + union + { + unsigned long LONG; + struct + { + unsigned long GCRMUL2:14; + unsigned long :2; + unsigned long RCRMUL2:14; + unsigned long :2; + } BIT; + } V0CSCE3; + union + { + unsigned long LONG; + struct + { + unsigned long BCBMUL2:14; + unsigned long :2; + unsigned long GCBMUL2:14; + unsigned long :2; + } BIT; + } V0CSCE4; + char wk11[16]; + char wk12[4]; + char wk13[4]; + char wk14[4]; + char wk15[4]; + char wk16[4]; + char wk17[4]; + char wk18[4]; + char wk19[4]; + char wk20[4]; + char wk21[4]; + char wk22[4]; + char wk23[4]; + char wk24[4]; + char wk25[4]; + char wk26[4]; +}; + +#define VIN (*(volatile struct st_vin *)0xE803F000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/wdt_iodefine.h new file mode 100644 index 0000000..ad22dc6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/iodefine/iodefines/wdt_iodefine.h @@ -0,0 +1,145 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* Rev: 2.00 +* Description : IO define header +*******************************************************************************/ + +#ifndef WDT_IODEFINE_H +#define WDT_IODEFINE_H + +struct st_wdt +{ + union + { + unsigned short WORD; + struct + { + unsigned char L; + unsigned char H; + } BYTE; + struct + { + unsigned char CKS:4; + unsigned char :1; + unsigned char TME:1; + unsigned char WTIT:1; + unsigned char IOVF:1; + unsigned char :8; + } BIT; + } WTCSR; + union + { + unsigned short WORD; + struct + { + unsigned char L; + unsigned char H; + } BYTE; + struct + { + unsigned char WTCNT:8; + unsigned char :8; + } BIT; + } WTCNT; + union + { + unsigned short WORD; + struct + { + unsigned char L; + unsigned char H; + } BYTE; + struct + { + unsigned char :6; + unsigned char RSTE:1; + unsigned char WOVF:1; + unsigned char :8; + } BIT; + } WRCSR; + char wk0[26]; + union + { + unsigned short WORD; + struct + { + unsigned char L; + unsigned char H; + } BYTE; + struct + { + unsigned char PEE:8; + unsigned char :8; + } BIT; + } PEER; + union + { + unsigned short WORD; + struct + { + unsigned char L; + unsigned char H; + } BYTE; + struct + { + unsigned char PERIE:8; + unsigned char :8; + } BIT; + } PECR; + union + { + unsigned short WORD; + struct + { + unsigned char L; + unsigned char H; + } BYTE; + struct + { + unsigned char PEF:8; + unsigned char :8; + } BIT; + } PESR; + char wk1[10]; + char wk2[2]; +}; + +#define WDT (*(volatile struct st_wdt *)0xFCFE7000) + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/reg32_t.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/reg32_t.h new file mode 100644 index 0000000..5328dd6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/inc/reg32_t.h @@ -0,0 +1,26 @@ +/* Copyright (c) 2015-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __REG32_T +#define __REG32_T + +union reg32_t { + volatile uint32_t UINT32; + volatile uint16_t UINT16[2]; + volatile uint8_t UINT8[4]; +}; + + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/mbed_sf_boot.c new file mode 100644 index 0000000..804e477 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/mbed_sf_boot.c @@ -0,0 +1,1039 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2019-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/**************************************************************************//** +* @file mbed_sf_boot.c +* $Rev: $ +* $Date:: $ +* @brief RZ_A2 OctaFlash boot loader +******************************************************************************/ + +#if !defined(APPLICATION_ADDR) + #define APPLICATION_ADDR 0x50000000 +#endif + +#if (APPLICATION_ADDR != 0x50000000) +const char * boot_loader = (char *)0x50000000; + +#else /* (APPLICATION_ADDR == 0x50000000) */ + +#if defined (__CC_ARM) +#pragma arm section rodata = "BOOT_LOADER" +const char boot_loader[] __attribute__((used)) = +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +const char boot_loader[] __attribute__ ((section("BOOT_LOADER"), used)) = +#elif defined (__ICCARM__) +__root const char boot_loader[] @ 0x50000000 = +#else +const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) = +#endif +{ + 0x18,0xf0,0x9f,0xe5,0xfe,0xff,0xff,0xea,0xfe,0xff,0xff,0xea,0xfe,0xff,0xff,0xea, + 0xfe,0xff,0xff,0xea,0xfe,0xff,0xff,0xea,0xfe,0xff,0xff,0xea,0xfe,0xff,0xff,0xea, + 0x00,0x39,0x00,0x50,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 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0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, + 0x80,0x00,0x9f,0xe5,0x01,0x10,0xa0,0xe3,0x00,0x10,0x80,0xe5,0x00,0x10,0x90,0xe5, + 0x74,0x00,0x9f,0xe5,0x12,0x10,0xa0,0xe3,0xb0,0x10,0xc0,0xe1,0xb0,0x00,0xd0,0xe1, + 0x68,0x00,0x9f,0xe5,0x10,0x0f,0x0c,0xee,0x10,0x0f,0x11,0xee,0x02,0x0a,0xc0,0xe3, + 0x01,0x0a,0xc0,0xe3,0x04,0x00,0xc0,0xe3,0x01,0x00,0xc0,0xe3,0x10,0x0f,0x01,0xee, + 0x13,0x00,0x02,0xf1,0x48,0xd0,0x9f,0xe5,0x48,0xc0,0x9f,0xe5,0x3c,0xff,0x2f,0xe1, + 0x44,0x00,0x9f,0xe5,0x44,0x10,0x9f,0xe5,0x44,0xc0,0x9f,0xe5,0x3c,0xff,0x2f,0xe1, + 0x40,0xc0,0x9f,0xe5,0x3c,0xff,0x2f,0xe1,0x3c,0x00,0x9f,0xe5,0x3c,0x10,0x9f,0xe5, + 0x2c,0xc0,0x9f,0xe5,0x3c,0xff,0x2f,0xe1,0x34,0xc0,0x9f,0xe5,0x3c,0xff,0x2f,0xe1, + 0x30,0xc0,0x9f,0xe5,0x1c,0xff,0x2f,0xe1,0x80,0x3f,0x00,0x1f,0x10,0x00,0xfe,0xfc, + 0x00,0x00,0x00,0x50,0x00,0xd0,0x02,0x80,0x10,0x3c,0x00,0x50,0x6c,0x3c,0x00,0x50, + 0x44,0x3c,0x00,0x50,0x00,0x3a,0x00,0x50,0x00,0x40,0x02,0x80,0x54,0x3c,0x00,0x50, + 0x34,0x3c,0x00,0x50,0x60,0x40,0x02,0x80,0x00,0x40,0x00,0x50,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0xf0,0x5f,0x2d,0xe9,0x00,0x40,0xa0,0xe1,0x04,0x10,0x2d,0xe5,0x00,0x00,0x54,0xe3, + 0x03,0x00,0x00,0x1b,0x04,0x40,0x9d,0xe4,0x00,0x00,0x54,0xe3,0x3c,0x00,0x00,0x1b, + 0xf0,0x9f,0xbd,0xe8,0x04,0x00,0x94,0xe4,0x04,0x10,0x94,0xe4,0x00,0x20,0x41,0xe0, + 0x04,0x10,0x94,0xe4,0x00,0x00,0x50,0xe3,0x1e,0xff,0x2f,0x01,0xa2,0x32,0xb0,0xe1, + 0x12,0x00,0x00,0x0a,0x0d,0x00,0x00,0xea,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0xe0,0x1f,0xb0,0xe8,0xe0,0x1f,0xa1,0xe8,0x01,0x30,0x53,0xe2,0xfb,0xff,0xff,0x1a, + 0x1f,0x20,0x12,0xe2,0x1d,0x00,0x00,0x0a,0x18,0x00,0x00,0xea,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x30,0xd0,0xe4,0x01,0x30,0xc1,0xe4,0x01,0x20,0x52,0xe2,0xfb,0xff,0xff,0x1a, + 0xc3,0xff,0xff,0xea,0x04,0x10,0x94,0xe4,0x04,0x20,0x94,0xe4,0x01,0x20,0x42,0xe0, + 0x00,0x00,0x51,0xe3,0x1e,0xff,0x2f,0x01,0x00,0x00,0xa0,0xe3,0xa2,0x32,0xb0,0xe1, + 0x15,0x00,0x00,0x0a,0x00,0x50,0xa0,0xe3,0x00,0x60,0xa0,0xe3,0x00,0x70,0xa0,0xe3, + 0x00,0x80,0xa0,0xe3,0x00,0x90,0xa0,0xe3,0x00,0xa0,0xa0,0xe3,0x00,0xb0,0xa0,0xe3, + 0x0a,0x00,0x00,0xea,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0xe1,0x0f,0xa1,0xe8,0x01,0x30,0x53,0xe2,0xfc,0xff,0xff,0x1a,0x1f,0x20,0x12,0xe2, + 0x1d,0x00,0x00,0x0a,0x19,0x00,0x00,0xea,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3,0x00,0xf0,0x20,0xe3, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0xc1,0xe4,0x01,0x20,0x52,0xe2,0xfc,0xff,0xff,0x1a,0xc0,0xff,0xff,0xea, + 0x50,0x0f,0x11,0xee,0x03,0x06,0x80,0xe3,0x03,0x05,0x80,0xe3,0x03,0x01,0xc0,0xe3, + 0x50,0x0f,0x01,0xee,0x6f,0xf0,0x7f,0xf5,0x01,0x01,0xa0,0xe3,0x10,0x0a,0xe8,0xee, + 0x1e,0xff,0x2f,0xe1,0x00,0xb0,0x03,0x80,0x00,0xb0,0x03,0x80,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x60,0x40,0x02,0x80,0x60,0x40,0x02,0x80,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0xa0,0x00,0x00,0x50,0xfc,0x05,0x00,0x50,0x60,0x40,0x02,0x80, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x50, + 0x84,0x00,0x00,0x50,0x00,0x40,0x02,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00, +}; +#if defined (__CC_ARM) +#pragma arm section +#endif + +#endif /* APPLICATION_ADDR */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/mmu_RZ_A2M.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/mmu_RZ_A2M.c new file mode 100644 index 0000000..349f247 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/mmu_RZ_A2M.c @@ -0,0 +1,351 @@ +/**************************************************************************//** + * @file mmu_RZ_A2M.c + * @brief MMU Configuration for RZ_A2M Device Series + * @version V1.00 + * @date 6 Sep 2018 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * Copyright (c) 2018-2020 Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description + +== User's Manual:Hardware == + Memory Type +0xffffffff |--------------------------| ------------ + | Peripherals | Device +0xffff0000 |--------------------------| ------------ + | Page Fault | Fault +0xfd000000 |--------------------------| ------------ + | Peripherals | Device +0xfcfe0000 |--------------------------| ------------ + | Page Fault | Fault +0xfc040000 |--------------------------| ------------ + | Peripherals | Device +0xfc000000 |--------------------------| ------------ + | Page Fault | Fault +0xf0002000 |--------------------------| ------------ + | Cortex-A9 private area | Device +0xf0000000 |--------------------------| ------------ + | Page Fault | Fault +0xeb000000 |--------------------------| ------------ + | Peripherals | Device +0xea000000 |--------------------------| ------------ + | Page Fault | Fault +0xe8240000 |--------------------------| ------------ + | Peripherals | Device +0xe8200000 |--------------------------| ------------ + | Page Fault | Fault +0xe8050000 |--------------------------| ------------ + | Peripherals | Device +0xe8000000 |--------------------------| ------------ + | Page Fault | Fault +0x80400000 |--------------------------| ------------ + | On Chip RAM 4MB | RW +0x80000000 |--------------------------| ------------ + | Page Fault | Fault +0x70000000 |--------------------------| ------------ + | OctaRAM 256MB | RW +0x60000000 |--------------------------| ------------ + | OctaFlash 256MB | RO +0x50000000 |--------------------------| ------------ + | HyperRAM 256MB | RW +0x40000000 |--------------------------| ------------ + | HyperFlash 256MB | RO +0x30000000 |--------------------------| ------------ + | SPI multi I/O 256MB | RO +0x20000000 |--------------------------| ------------ + | Page Fault | Fault +0x1f809000 |--------------------------| ------------ + | Peripherals | Device +0x1f808000 |--------------------------| ------------ + | Page Fault | Fault +0x1f801000 |--------------------------| ------------ + | Peripherals | Device +0x1f800000 |--------------------------| ------------ + | Page Fault | Fault +0x1f402000 |--------------------------| ------------ + | Peripherals | Device +0x1f400000 |--------------------------| ------------ + | Page Fault | Fault +0x1f004000 |--------------------------| ------------ + | Peripherals | Device +0x1f000000 |--------------------------| ------------ + | Page Fault | Fault +0x1c000000 |--------------------------| ------------ + | Page Fault | Fault +0x18000000 |--------------------------| ------------ + | CS5 64MB | RW +0x14000000 |--------------------------| ------------ + | CS4 64MB | RW +0x10000000 |--------------------------| ------------ + | CS3 64MB | RW +0x0c000000 |--------------------------| ------------ + | CS2 64MB | RW +0x08000000 |--------------------------| ------------ + | CS1 64MB | RW +0x04000000 |--------------------------| ------------ + | CS0 64MB | RW +0x00000000 |--------------------------| ------------ + + +== Actual setting of MMU == + Memory Type +0xffffffff |--------------------------| ------------ + | Peripherals | Device +0xe8000000 |--------------------------| ------------ + | - | - +0x80400000 |--------------------------| ------------ + | On Chip RAM 4MB | RW +0x80000000 |--------------------------| ------------ + | - | - +0x70000000 |--------------------------| ------------ + | OctaRAM 256MB | RW +0x60000000 |--------------------------| ------------ + | OctaFlash 256MB | RO +0x50000000 |--------------------------| ------------ + | HyperRAM 256MB | RW +0x40000000 |--------------------------| ------------ + | HyperFlash 256MB | RO +0x30000000 |--------------------------| ------------ + | SPI multi I/O 256MB | RO +0x20000000 |--------------------------| ------------ + | Peripherals | Device +0x18000000 |--------------------------| ------------ + | - | - +0x10000000 |--------------------------| ------------ + | CS3 SDRAM 64MB | RW +0x0c000000 |--------------------------| ------------ + | - | - +0x00000000 |--------------------------| ------------ +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 +//There are no restrictions by privilege level (PL0 can access all memory) + + +#include "RZ_A2M.h" + +//Import symbols from linker +#if defined ( __ICCARM__ ) +__no_init uint32_t Image$$TTB$$ZI$$Base @ "TTB"; +__no_init uint32_t Image$$TTB_L2$$ZI$$Base @ "TTB_L2"; +#else +extern uint32_t Image$$TTB$$ZI$$Base; +extern uint32_t Image$$TTB_L2$$ZI$$Base; +extern uint32_t Image$$RW_DATA_NC$$Base; +extern uint32_t Image$$ZI_DATA_NC$$Limit; +#endif + +#define page4k_normal(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +#define page4k_normal_nc(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region); + +__STATIC_INLINE void MMU_TTSection_Va(uint32_t *ttb, uint32_t vaddress, uint32_t paddress, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = vaddress >> 20; + entry = (paddress & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +static void MMU_TTPage4k_local(uint32_t *ttb, uint32_t start_address, uint32_t size, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2) +{ + uint32_t base_address = start_address & 0xFF000000; + uint32_t section_count = (start_address & 0x00F00000) >> 20; + uint32_t rest_count = (size + OFFSET_4K - 1) / OFFSET_4K; + uint32_t count; + uint32_t count_adjust; + + if (rest_count == 0) { + return; + } + + if ((start_address & 0x000FFFFF) != 0) { + /* When "start_address" is not the beginning of the section. */ + count_adjust = 0x100 - ((start_address & 0x000FFFFF) / OFFSET_4K); + + count = rest_count; + if (count > count_adjust) { + count = count_adjust; + } + MMU_TTPage4k(ttb, start_address, count, descriptor_l1, + (uint32_t *)((uint32_t)ttb_l2 + (0x400 * section_count)), descriptor_l2); + rest_count -= count; + section_count++; + } + + while (rest_count > 0) { + count = rest_count; + if (count > 0x100) { + count = 0x100; + } + MMU_TTPage4k(ttb, base_address + (OFFSET_1M * section_count), count, descriptor_l1, + (uint32_t *)((uint32_t)ttb_l2 + (0x400 * section_count)), descriptor_l2); + rest_count -= count; + section_count++; + } +} + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; + + uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 + uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable + uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 + + uint32_t Page_L1_4k = 0x0; //generic + uint32_t Page_4k_Normal_RW; + uint32_t Page_4k_Normal_NC; + + uint32_t sram_non_cache_base; + uint32_t sram_non_cache_size; + +#if defined ( __ICCARM__ ) +#pragma section="NC_RAM" + sram_non_cache_base = (uint32_t)__section_begin("NC_RAM"); + sram_non_cache_size = (uint32_t)__section_end("NC_RAM") - (uint32_t)__section_begin("NC_RAM"); +#else + sram_non_cache_base = (uint32_t)&Image$$RW_DATA_NC$$Base; + sram_non_cache_size = (uint32_t)&Image$$ZI_DATA_NC$$Limit - (uint32_t)&Image$$RW_DATA_NC$$Base; +#endif + + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal_cod(Sect_Normal_Cod, region); + section_normal(Sect_Normal_RW, region); + section_normal_nc(Sect_Normal_NC, region); + + //Create descriptors for peripherals + section_device_rw(Sect_Device_RW, region); + //Create descriptors for 4k pages + page4k_normal(Page_L1_4k, Page_4k_Normal_RW, region); + page4k_normal_nc(Page_L1_4k, Page_4k_Normal_NC, region); + + /* + * Define MMU flat-map regions and attributes + * + */ + //Create 4GB of faulting entries + MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + // memory map. + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_SDRAM , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_SPI_IO ,256, Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_HYPER_FLASH ,256, Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_HYPER_RAM ,256, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_OCTA_FLASH ,256, Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_OCTA_RAM ,256, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_PERIPH_BASE0 ,384, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A2_PERIPH_BASE1 ,128, Sect_Device_RW); + + // SRAM + // Register all memory as cache. + MMU_TTPage4k_local(&Image$$TTB$$ZI$$Base, RZ_A2_ONCHIP_SRAM_BASE, 0x400000, Page_L1_4k, + (uint32_t *)&Image$$TTB_L2$$ZI$$Base, Page_4k_Normal_RW); + + // Overwrite non-cache if necessary. + MMU_TTPage4k_local(&Image$$TTB$$ZI$$Base, sram_non_cache_base, sram_non_cache_size, Page_L1_4k, + (uint32_t *)&Image$$TTB_L2$$ZI$$Base, Page_4k_Normal_NC); + + // Virtual address + MMU_TTSection_Va (&Image$$TTB$$ZI$$Base, RZ_A2_HYPER_FLASH_IO, RZ_A2_HYPER_FLASH ,256, Sect_Device_RW); + MMU_TTSection_Va (&Image$$TTB$$ZI$$Base, RZ_A2_OCTA_FLASH_NC, RZ_A2_OCTA_FLASH ,256, Sect_Normal_NC); + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x0 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x1 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x1 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 0x48); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/nvic_wrapper.c new file mode 100644 index 0000000..d0aeb16 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/nvic_wrapper.c @@ -0,0 +1,245 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2012-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/**************************************************************************//** +* @file nvic_wrapper.c +* $Rev: $ +* $Date:: $ +* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) +******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "MBRZA2M.h" +//#include "wdt_iodefine.h" +#include "nvic_wrapper.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */ +#define WDT_WTCNT_WRITE (0x5A00) +#define WDT_WTCSR_WRITE (0xA500) +#define WDT_WRCSR_WOVF_WRITE (0xA500) +#define WDT_WRCSR_RSTE_WRITE (0x5A00) + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + + + +/* ########################## NVIC functions #################################### */ +void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_SetBinaryPoint(PriorityGroup); +} + + +uint32_t NVIC_GetPriorityGrouping(void) +{ + return GIC_GetBinaryPoint(); +} + + +void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_EnableIRQ(IRQn); +} + + +void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_DisableIRQ(IRQn); +} + + +uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pending; + + pending = GIC_GetIRQStatus(IRQn); + pending = (pending & 0x00000001); + + return pending; +} + + +void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + GIC_SetPendingIRQ(IRQn); +} + + +void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + GIC_ClearPendingIRQ(IRQn); +} + + +uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + uint32_t active; + + active = GIC_GetIRQStatus(IRQn); + active = ((active >> 1) & 0x00000001); + + return active; +} + + +void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_SetPriority(IRQn, (priority << 3)); +} + + +uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + uint32_t priority_field; + + priority_field = GIC_GetPriority(IRQn); + priority_field = (priority_field >> 3); + return priority_field; +} + + +uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + +void NVIC_SystemReset(void) +{ + uint16_t reg; + uint16_t dummy_read; + /* Use Watch Dog Timer to system reset */ + + /* Set WT/IT bit of WTCSR to 1 = Watch Dog */ + /* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */ + reg = (WDT_WTCSR_WRITE | 0x0058); + WDT.WTCSR.WORD = reg; + + /* Clear Count reg */ + reg = (WDT_WTCNT_WRITE | 0x0000); + WDT.WTCNT.WORD = reg; + + /* Clear WOVF flag */ + dummy_read = WDT.WRCSR.WORD; + reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000)); + WDT.WRCSR.WORD = reg; + /* Enable Internal Reset */ + reg = (WDT_WRCSR_RSTE_WRITE | 0x005F); + WDT.WRCSR.WORD = reg; + + /* Watch Dog start */ + reg = (WDT_WTCSR_WRITE | 0x0078); + WDT.WTCSR.WORD = reg; + + while(1); /* wait Internal Reset */ +} + +/* ################################## SysTick function ############################################ */ +uint32_t SysTick_Config(uint32_t ticks) +{ + /* Not support this function */ + /* Use mbed Ticker */ + return (1); /* impossible */ +} + + +/* ##################################### Debug In/Output function ########################################### */ +uint32_t ITM_SendChar (uint32_t ch) +{ + /* Not support this function */ + /* Use mbed Serial */ + return (ch); +} + + +int32_t ITM_ReceiveChar (void) +{ + /* Not support this function */ + /* Use mbed Serial */ + return (-1); /* no character available */ +} + + +int32_t ITM_CheckChar (void) +{ + /* Not support this function */ + /* Use mbed Serial */ + return (0); /* no character available */ +} + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/octaram_init.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/octaram_init.c new file mode 100644 index 0000000..de9a2f8 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/octaram_init.c @@ -0,0 +1,293 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2019-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2019-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* File Name : octaram_init.c +*******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "r_typedefs.h" +#include "iodefine.h" +#include "mbed_drv_cfg.h" + + +#if(1) /******* Provisional (Remove this process when the bootloader is complete) ****** */ +#define OCTAINF_33MHZ 1 +#define OCTAINF_66MHZ 2 +#define OCTAINF_132MHZ 3 + +#define OCTAINF_XXMHZ OCTAINF_132MHZ + +#if defined(__ICCARM__) +#define RAM_CODE_SEC __ramfunc +#else +#define RAM_CODE_SEC __attribute__((section("RAM_CODE"))) +#endif + +static RAM_CODE_SEC void octa_spi_wren(void); +static RAM_CODE_SEC void octa_spi_wrcr2(uint32_t addr, uint32_t data); + +RAM_CODE_SEC void OctaFlash_Init(void); + +void OctaFlash_Init(void) +{ + volatile uint8_t dummy8; + + /* ---- STBCR9 Setting ---- */ + CPG.STBCR9.BIT.MSTP92 = 0; // Octa Memory Controller runs + dummy8 = CPG.STBCR9.BYTE; + (void)dummy8; + + /* ---- SCLKSEL Setting ---- */ + /* OCTCR: 11b -> G/2phy -> 132MHz */ + /* OCTCR: 10b -> B/2phy -> 66MHz */ + /* OCTCR: 01b -> P1/2phy -> 33MHz */ + /* OCTCR: 00b -> P0/2phy -> 16MHz */ +#if (OCTAINF_XXMHZ == OCTAINF_33MHZ) + CPG.SCLKSEL.BIT.OCTCR = 1; // Octa clock P1 +#elif (OCTAINF_XXMHZ == OCTAINF_66MHZ) + CPG.SCLKSEL.BIT.OCTCR = 2; // Octa clock B +#else // (OCTAINF_XXMHZ == OCTAINF_132MHZ) + CPG.SCLKSEL.BIT.OCTCR = 3; // Octa clock G +#endif + + /* ---- PHMOM0 Setting ---- */ + GPIO.PHMOM0.BIT.HOSEL = 1; /* Select Octa Memory Controller */ + + + // --------------------------------------- + // OctaFlash + // --------------------------------------- + /* ---- Device size register 0 ---- */ + OCTA.DSR0.BIT.DV0TYP = 0; + OCTA.DSR0.BIT.DV0SZ = OCTAFLASH_SIZE; + + /* ---- Set Dummy Cycle as 6 cycles ---- */ + octa_spi_wren(); +#if (OCTAINF_XXMHZ == OCTAINF_33MHZ) + octa_spi_wrcr2(0x00000300, 0x7); // 6 dummy cycles @33MHz +#elif (OCTAINF_XXMHZ == OCTAINF_66MHZ) + octa_spi_wrcr2(0x00000300, 0x6); // 8 dummy cycles @66MHz +#else // (OCTAINF_XXMHZ == OCTAINF_132MHZ) + octa_spi_wrcr2(0x00000300, 0x3); // 14 dummy cycles @132MHz +#endif + + /* ---- Set OctaFlash to DOPI mode ---- */ + octa_spi_wren(); + octa_spi_wrcr2(0x00000000, 0x2); // DTR OPI mode + + /* ---- Controller and device setting register ---- */ + OCTA.CDSR.BIT.DLFT = 1; + OCTA.CDSR.BIT.DV0TTYP = 2; // Device0 =DOPI mode + + /* ---- Memory Map read/write command register 0 ---- */ + OCTA.MRWCR0.BIT.D0MWCMD1 = 0x12; + OCTA.MRWCR0.BIT.D0MWCMD0 = 0xED; + OCTA.MRWCR0.BIT.D0MRCMD1 = 0xEE; + OCTA.MRWCR0.BIT.D0MRCMD0 = 0x11; + + /* ---- Memory Map read/write setting register ---- */ + OCTA.MRWCSR.BIT.MWO0 = 1; // write data order: byte1, byte0, byte3, byte2 + OCTA.MRWCSR.BIT.MWCL0 = 2; // 2 bytes command @Write + OCTA.MRWCSR.BIT.MWAL0 = 4; // 4 bytes address @Write + OCTA.MRWCSR.BIT.MRO0 = 1; // read data order: byte1, byte0, byte3, byte2 + OCTA.MRWCSR.BIT.MRCL0 = 2; // 2 bytes command @Read + OCTA.MRWCSR.BIT.MRAL0 = 4; // 4 bytes address @Read + + /* ---- Memory delay trim register ---- */ + OCTA.MDTR.BIT.DQSEDOPI = 0x6; + OCTA.MDTR.BIT.DV0DEL = 0x48; + + /* ---- Memory Map dummy length register ---- */ +#if (OCTAINF_XXMHZ == OCTAINF_33MHZ) + OCTA.MDLR.BIT.DV0RDL = 6; // 6 dummy cycles @33MHz +#elif (OCTAINF_XXMHZ == OCTAINF_66MHZ) + OCTA.MDLR.BIT.DV0RDL = 8; // 8 dummy cycles @66MHz +#else // (OCTAINF_XXMHZ == OCTAINF_132MHZ) + OCTA.MDLR.BIT.DV0RDL = 14; // 14 dummy cycles @132MHz +#endif + + /* ---- Device chip select timing setting register ---- */ + OCTA.DCSTR.BIT.DVSELLO = 0; + OCTA.DCSTR.BIT.DVSELHI = 5; + OCTA.DCSTR.BIT.DVSELCMD = 0; + + /* ---- Device Memory Map Write chip select timing setting register ---- */ + OCTA.DWCSTR.BIT.DVWLO0 = 0; + OCTA.DWCSTR.BIT.DVWHI0 = 2; + OCTA.DWCSTR.BIT.DVWCMD0 = 1; + + /* ---- Device Memory Map Read chip select timing setting register ---- */ + OCTA.DRCSTR.BIT.DVRDLO0 = 0; + OCTA.DRCSTR.BIT.DVRDHI0 = 5; + OCTA.DRCSTR.BIT.DVRDCMD0 = 1; + OCTA.DRCSTR.BIT.CTR0 = 0; + OCTA.DRCSTR.BIT.CTRW0 = 0x20; +} + +void octa_spi_wren(void) +{ + /* ---- Device command register ---- */ + OCTA.DCR.BIT.DVCMD0 = 0x06; // Write Enable + + /* ---- Device command setting register ---- */ + OCTA.DCSR.BIT.ACDA = 0; + OCTA.DCSR.BIT.DOPI = 1; + OCTA.DCSR.BIT.ADLEN = 0; + OCTA.DCSR.BIT.DAOR = 0; + OCTA.DCSR.BIT.CMDLEN = 1; + OCTA.DCSR.BIT.ACDV = 0; + OCTA.DCSR.BIT.DMLEN = 0; + OCTA.DCSR.BIT.DALEN = 0; + + /* ---- Configure write without data register ---- */ + OCTA.CWNDR = 0x00000000; +} + +void octa_spi_wrcr2(uint32_t addr, uint32_t data) +{ + /* ---- Device command register ---- */ + OCTA.DCR.BIT.DVCMD0 = 0x72; // Read Configuration Register 2 + + /* ---- Device address register ---- */ + OCTA.DAR.LONG = addr; + + /* ---- Device command setting register ---- */ + OCTA.DCSR.BIT.ACDA = 0; + OCTA.DCSR.BIT.DOPI = 1; + OCTA.DCSR.BIT.ADLEN = 4; + OCTA.DCSR.BIT.DAOR = 0; + OCTA.DCSR.BIT.CMDLEN = 1; + OCTA.DCSR.BIT.ACDV = 0; + OCTA.DCSR.BIT.DMLEN = 0; + OCTA.DCSR.BIT.DALEN = 1; + + /* ---- Configure write data register ---- */ + OCTA.CWDR.LONG = data; +} +#endif + +static void octa_ram_mode_register_write(uint16_t config) +{ + /* ---- Device command register ---- */ + OCTA.DCR.BIT.DVCMD1 = 0x40; // Mode Register Write + + /* ---- Device address register ---- */ + OCTA.DAR.LONG = 0x00040000; + + /* ---- Device command setting register ---- */ + OCTA.DCSR.BIT.ACDA = 0; + OCTA.DCSR.BIT.DOPI = 0; + OCTA.DCSR.BIT.ADLEN = 4; + OCTA.DCSR.BIT.DAOR = 1; + OCTA.DCSR.BIT.CMDLEN = 2; + OCTA.DCSR.BIT.ACDV = 1; + OCTA.DCSR.BIT.DMLEN = 0; + OCTA.DCSR.BIT.DALEN = 2; + + /* ---- Configure write data register ---- */ + OCTA.CWDR.LONG = (uint32_t)config; +} + +/****************************************************************************** +* Function Name: OctaRAM_Init +* Description : +* Arguments : none +* Return Value : none +******************************************************************************/ +void OctaRAM_Init(void) +{ + volatile uint8_t dummy8; + + CPG.STBCR9.BIT.MSTP92 = 0; + dummy8 = CPG.STBCR9.BYTE; + (void)dummy8; + + /* ---- Device size register 1 ---- */ + OCTA.DSR1.BIT.DV1TYP = 1; // TYPE=RAM + OCTA.DSR1.BIT.DV1SZ = OCTARAM_SIZE; // RAM size + + /* ---- Controller and device setting register ---- */ + OCTA.CDSR.BIT.DV1TTYP = 2; // Device1 =DOPI mode + + /* ---- Memory Map dummy length register ---- */ + OCTA.MDLR.BIT.DV1WDL = 5; // Device1 Write DUMMY = 5 + OCTA.MDLR.BIT.DV1RDL = 5; // Device1 Read DUMMY = 5 + + /* ---- Memory delay trim register ---- */ + OCTA.MDTR.BIT.DV1DEL = 40; // Device1 Delay 40 + OCTA.MDTR.BIT.DQSERAM = 6; // OM_DQS enable counter + + /* ---- Device Memory Map Read chip select timing setting register ---- */ + OCTA.DRCSTR.BIT.DVRDLO1 = 0; // Device1 select signal High timing setting = 1.5 clock cycles + OCTA.DRCSTR.BIT.DVRDHI1 = 5; // Device1 select signal High timing setting = 6.5 clock cycles + OCTA.DRCSTR.BIT.DVRDCMD1 = 0; // Device1 Command execution interval = 2 clock cycles + + /* ---- Device Memory Map Write chip select timing setting register ---- */ + OCTA.DWCSTR.BIT.DVWLO1 = 0; // Device1 select signal High timing setting = 1.5 clock cycles + OCTA.DWCSTR.BIT.DVWHI1 = 1; // Device1 select signal High timing setting = 2.5 clock cycles + OCTA.DWCSTR.BIT.DVWCMD1 = 0; // Device1 Command execution interval = 2 clock cycles + + /* ---- Memory Map read/write command register 1 ---- */ + /* Wrap Burst */ + OCTA.MRWCR1.BIT.D1MWCMD1 = 0x00; // write command + OCTA.MRWCR1.BIT.D1MRCMD1 = 0x80; // read command + + /* ---- Memory Map read/write setting register ---- */ + OCTA.MRWCSR.BIT.MWO1 = 1; // Device1 write order setting = Write order is byte1, byte0, byte3, byte2 + OCTA.MRWCSR.BIT.MWCL1 = 2; // Device1 write command length setting = 2 + OCTA.MRWCSR.BIT.MWAL1 = 4; // Device1 write address length setting = 4 + OCTA.MRWCSR.BIT.MRO1 = 1; // Device1 read order setting = Read order is byte1, byte0, byte3, byte2 + OCTA.MRWCSR.BIT.MRCL1 = 2; // Device1 read command length setting = 2 + OCTA.MRWCSR.BIT.MRAL1 = 4; // Device1 read address length setting = 4 + + GPIO.PHMOM0.BIT.HOSEL = 1; // Select Octa Memory Controller + + uint16_t config = 0x8021; // CR[15] Deep Power Down : 1 - Normal + // CR[14:12] Driver Strength : 000 - 100ohms + // CR[11:9] Reserved : 000 + // CR[8] DQSM Read Pre-Cycle : 0 - 0 clock + // CR[7:4] Latency Counter : 0010 - 5 clocks + // CR[3] Initial Access Latency : 0 - Variable Latency + // CR[2] CLK2 Input : 0 - No Support + // CR[1:0] Bust Wrap Length : 01 - 64 bytes + octa_ram_mode_register_write(config); +} + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/os_tick_ostm.c new file mode 100644 index 0000000..934ece1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/os_tick_ostm.c @@ -0,0 +1,197 @@ +/**************************************************************************//** + * @file os_tick_ostm.c + * @brief CMSIS OS Tick implementation for OS Timer + * @version V1.0.1 + * @date 19. September 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef MBED_CONF_RTOS_PRESENT + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include + +#include + + +// Define OS TImer interrupt priority +#ifndef OSTM_IRQ_PRIORITY +#define OSTM_IRQ_PRIORITY 0xFFU +#endif + +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0_IRQn) + + +static uint32_t OSTM_Clock; // Timer tick frequency +static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag + + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) +{ + uint32_t clock; + uint32_t prio; + uint32_t bits; + volatile uint8_t dummy_buf; + + if (freq == 0U) { + return (-1); + } + + OSTM_PendIRQ = 0U; + + // Get CPG.FRQCR[IFC] bits + clock = (CPG.FRQCR.WORD >> 8) & 0x03; + + // Determine Divider 2 output clock by using CM0_RENESAS_RZ_A2_P0_CLK + clock = (CM0_RENESAS_RZ_A2_P0_CLK * (2 << clock)); + + // Determine tick frequency + clock = clock / freq; + + // Save frequency for later + OSTM_Clock = clock; + + // Enable OSTM clock + CPG.STBCR3.BYTE &= ~(0x40u); /* [1], OSTM0, OSTM1, OSTM3, */ + /* MTU3, CAN-FD, ADC, GPT */ + dummy_buf = CPG.STBCR3.BYTE; /* (Dummy read) */ + (void)dummy_buf; + + // Stop the OSTM counter + OSTM.OSTMnTT.BYTE = 0x01U; + + // Set interval timer mode and disable interrupts when counting starts + OSTM.OSTMnCTL.BYTE = 0x00U; + + // Set compare value + OSTM.OSTMnCMP.LONG = clock - 1U; + + // Disable corresponding IRQ + IRQ_Disable (OSTM_IRQn); + IRQ_ClearPending(OSTM_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (OSTM_IRQn, 0xFFU); + + prio = IRQ_GetPriority (OSTM_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set OSTM interrupt priority + IRQ_SetPriority(OSTM_IRQn, prio-1U); + + // Set edge-triggered, non-secure, single CPU targeted IRQ + IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler); + + // Enable corresponding IRQ + IRQ_Enable (OSTM_IRQn); + + return (0); +} + +/// Enable OS Tick. +void OS_Tick_Enable (void) +{ + + if (OSTM_PendIRQ != 0U) { + OSTM_PendIRQ = 0U; + IRQ_SetPending (OSTM_IRQn); + } + + // Start the OSTM counter + OSTM.OSTMnTS.BYTE = 0x01U; +} + +/// Disable OS Tick. +void OS_Tick_Disable (void) +{ + + // Stop the OSTM counter + OSTM.OSTMnTT.BYTE = 0x01U; + + if (IRQ_GetPending(OSTM_IRQn) != 0) { + IRQ_ClearPending (OSTM_IRQn); + OSTM_PendIRQ = 1U; + } +} + +// Acknowledge OS Tick IRQ. +void OS_Tick_AcknowledgeIRQ (void) +{ + IRQ_ClearPending (OSTM_IRQn); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) +{ + return (OSTM_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) +{ + return (OSTM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) +{ + return (OSTM.OSTMnCMP.LONG + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) +{ + uint32_t cmp = OSTM.OSTMnCMP.LONG; + return (cmp - OSTM.OSTMnCNT.LONG); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) +{ + return (IRQ_GetPending(OSTM_IRQn)); +} + +// Get Cortex-A9 OS Timer interrupt number +IRQn_ID_t mbed_get_a9_tick_irqn(){ + return OSTM_IRQn; +} +#endif + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/system_RZ_A2M.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/system_RZ_A2M.c new file mode 100644 index 0000000..406535b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/system_RZ_A2M.c @@ -0,0 +1,350 @@ +/****************************************************************************** + * @file system_RZ_A2M_H.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2020 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RZ_A2M.h" +#include "RZ_A2_Init.h" +#include "irq_ctrl.h" +#include "mbed_drv_cfg.h" +#include "r_cache_lld_rza2m.h" + +extern void HyperRAM_Init(void); +extern void OctaRAM_Init(void); + +/* + Port 0 (P0) MD pin assignment + P0_0: MD_BOOT0 + P0_1: MD_BOOT1 + P0_2: MD_CLK + P0_3: MD_CLKS + */ + +#include "rza_io_regrw.h" +#include "iobitmask.h" +#include "rtc_iobitmask.h" +#include "usb_iobitmask.h" + +#define STARTUP_CFG_USB_PHY_PLL_DELAY_COUNT (500) + +#define IOREG_NONMASK_ACCESS (0xFFFFFFFFuL) +#define IOREG_NONSHIFT_ACCESS (0) + +#define R_PRV_RTC_COUNT (2) +#define R_PRV_USB_COUNT (2) + +static void disable_rtc(uint32_t ch) +{ + uint8_t dummy8; + uint32_t mask; + uint8_t shift; + static volatile struct st_rtc * const rtc[R_PRV_RTC_COUNT] = { + &RTC0, &RTC1 + }; + static const uint8_t mstp_mask[R_PRV_RTC_COUNT] ={ + CPG_STBCR5_MSTP53, CPG_STBCR5_MSTP52 + }; + static const uint8_t mstp_shift[R_PRV_RTC_COUNT] = { + CPG_STBCR5_MSTP53_SHIFT, CPG_STBCR5_MSTP52_SHIFT + }; + static const uint16_t rtcxtalsel_mask[R_PRV_RTC_COUNT] = { + PMG_RTCXTALSEL_RTC0XT, PMG_RTCXTALSEL_RTC1XT + }; + static const uint8_t rtcxtalsel_shift[R_PRV_RTC_COUNT] = { + PMG_RTCXTALSEL_RTC0XT_SHIFT, PMG_RTCXTALSEL_RTC1XT_SHIFT + }; + + /* channel check */ + if (ch >= R_PRV_RTC_COUNT) { + return; + } + + /* 1: select RTCXTAL for RTC (RCR4.RCKSEL = 0) */ + RZA_IO_RegWrite_8(&rtc[ch]->RCR4.BYTE, 0, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + RZA_IO_RegRead_8(&rtc[ch]->RCR4.BYTE, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + /* 2: disable RTC clock (RCR3.RTCEN = 0) */ + RZA_IO_RegWrite_8(&rtc[ch]->RCR3.BYTE, 0, RTC_RCR3_RTCEN_SHIFT, RTC_RCR3_RTCEN); + + /* Wait for successfully disabled */ + dummy8 = 1; + while (0 != dummy8) { + dummy8 = RZA_IO_RegRead_8(&rtc[ch]->RCR3.BYTE, RTC_RCR3_RTCEN_SHIFT, RTC_RCR3_RTCEN); + } + + /* 3: disable RTC clock while standby mode */ + mask = rtcxtalsel_mask[ch]; + shift = rtcxtalsel_shift[ch]; + RZA_IO_RegWrite_16(&PMG.RTCXTALSEL.WORD, 0, shift, mask); + RZA_IO_RegRead_16(&PMG.RTCXTALSEL.WORD, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + /* 4: Stop RTC module */ + mask = mstp_mask[ch]; + shift = mstp_shift[ch]; + RZA_IO_RegWrite_8(&CPG.STBCR5.BYTE, 1, shift, mask); + RZA_IO_RegRead_8(&CPG.STBCR5.BYTE, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); +} + +static void disable_usb(uint32_t ch) +{ + uint8_t dummy8; + uint32_t mask; + uint8_t shift; + + /* USB Host IO reg Top Address(ch0, ch1) */ + static volatile struct st_usb00 * const usb00_host[R_PRV_USB_COUNT] = { + &USB00, &USB10 + }; + + /* USB Function IO reg Top Address(ch0, ch1) */ + static volatile struct st_usb01 * const usb01_func[R_PRV_USB_COUNT] = { + &USB01, &USB11 + }; + + /* MSTP */ + static const uint8_t mstp_mask[R_PRV_USB_COUNT] = { + CPG_STBCR6_MSTP61, CPG_STBCR6_MSTP60 + }; + static const uint8_t mstp_shift[R_PRV_USB_COUNT] = { + CPG_STBCR6_MSTP61_SHIFT, CPG_STBCR6_MSTP60_SHIFT + }; + + /* STBREQ */ + static const uint8_t stbreq_mask[R_PRV_USB_COUNT] = { + (CPG_STBREQ3_STBRQ31 | CPG_STBREQ3_STBRQ30), (CPG_STBREQ3_STBRQ33 | CPG_STBREQ3_STBRQ32) + }; + static const uint8_t stbreq_shift[R_PRV_USB_COUNT] = { + CPG_STBREQ3_STBRQ30_SHIFT, CPG_STBREQ3_STBRQ32_SHIFT + }; + + /* STBACK */ + static const uint8_t stback_mask[R_PRV_USB_COUNT] = { + (CPG_STBACK3_STBAK31 | CPG_STBACK3_STBAK30), (CPG_STBACK3_STBAK33 | CPG_STBACK3_STBAK32) + }; + static const uint8_t stback_shift[R_PRV_USB_COUNT] = { + CPG_STBACK3_STBAK30_SHIFT, CPG_STBACK3_STBAK32_SHIFT + }; + + /* channel check */ + if (ch >= R_PRV_USB_COUNT) { + return; + } + + /* 1: Start USB module */ + + /* MSTP = 0 */ + mask = mstp_mask[ch]; + shift = mstp_shift[ch]; + RZA_IO_RegWrite_8(&CPG.STBCR6.BYTE, 0, shift, mask); + RZA_IO_RegRead_8(&CPG.STBCR6.BYTE, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + /* STBREQ = 0 */ + mask = stbreq_mask[ch]; + shift = stbreq_shift[ch]; + RZA_IO_RegWrite_8(&CPG.STBREQ3.BYTE, 0x0, shift, mask); + RZA_IO_RegRead_8(&CPG.STBREQ3.BYTE, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + /* check STBACK = 0 */ + mask = stback_mask[ch]; + shift = stback_shift[ch]; + dummy8 = 0x3; + while (0x0 != dummy8) { + dummy8 = RZA_IO_RegRead_8(&CPG.STBACK3.BYTE, shift, mask); + } + (void)dummy8; + + /* 2: Set the clock supplied to USBPHY to EXTAL clock (PHYCLK_CTRL.UCLKSEL = 0) */ + RZA_IO_RegWrite_32(&usb00_host[ch]->PHYCLK_CTRL.LONG, 0, USB_PHYCLK_CTRL_UCLKSEL_SHIFT, USB_PHYCLK_CTRL_UCLKSEL); + + /* 3: It can recover from deep standby by DP, DM change (PHYIF_CTRL.FIXPHY = 1) */ + RZA_IO_RegWrite_32(&usb00_host[ch]->PHYIF_CTRL.LONG, 1, USB_PHYIF_CTRL_FIXPHY_SHIFT, USB_PHYIF_CTRL_FIXPHY); + + /* 4: UTMI+PHY Normal Mode (LPSTS.SUSPM = 1) */ + RZA_IO_RegWrite_16(&usb01_func[ch]->LPSTS.WORD, 1, USB_LPSTS_SUSPM_SHIFT, USB_LPSTS_SUSPM); + + /* 5: UTMI + reset release (USBCTR.PLL_RST = 0) */ + RZA_IO_RegWrite_32(&usb00_host[ch]->USBCTR.LONG, 0, USB_USBCTR_PLL_RST_SHIFT, USB_USBCTR_PLL_RST); + + /* 6: wait 200us delay(Waiting for oscillation stabilization of USBPHY built-in PLL) */ + for (volatile int i = 0; i < STARTUP_CFG_USB_PHY_PLL_DELAY_COUNT; i++) { + ; + } + + /* 7: Pulldown resistance control is effective (LINECTRL1 = 0x000A0000) */ + RZA_IO_RegWrite_32( + &usb00_host[ch]->LINECTRL1.LONG, + (USB_LINECTRL1_DPRPD_EN | USB_LINECTRL1_DMRPD_EN), + IOREG_NONSHIFT_ACCESS, + IOREG_NONMASK_ACCESS); + + /* 8: USBPHY standby mode (USBCTR.DIRPD = 1) */ + RZA_IO_RegWrite_32(&usb00_host[ch]->USBCTR.LONG, 1, USB_USBCTR_DIRPD_SHIFT, USB_USBCTR_DIRPD); + + /* 9: Stop USB module */ + + /* STBREQ = 1 */ + mask = stbreq_mask[ch]; + shift = stbreq_shift[ch]; + RZA_IO_RegWrite_8(&CPG.STBREQ3.BYTE, 0x3, shift, mask); + RZA_IO_RegRead_8(&CPG.STBREQ3.BYTE, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + /* check STBACK = 1 */ + mask = stback_mask[ch]; + shift = stback_shift[ch]; + dummy8 = 0x0; + while (0x3 != dummy8) + { + dummy8 = RZA_IO_RegRead_8(&CPG.STBACK3.BYTE, shift, mask); + } + (void)dummy8; + + /* MSTP = 1 */ + mask = mstp_mask[ch]; + shift = mstp_shift[ch]; + RZA_IO_RegWrite_8(&CPG.STBCR6.BYTE, 1, shift, mask); + RZA_IO_RegRead_8(&CPG.STBCR6.BYTE, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); +} + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A2_I_CLK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ +} + +/*---------------------------------------------------------------------------- + IRQ Handler Register/Unregister + *----------------------------------------------------------------------------*/ +uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) +{ + return IRQ_SetHandler(irq, handler); +} + +uint32_t InterruptHandlerUnregister (IRQn_Type irq) +{ + return IRQ_SetHandler(irq, (IRQHandler_t)NULL); +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section may be overwritten afterwards. */ +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + volatile uint8_t dummy_buf_8b; + + // Enable SRAM write access + CPG.SYSCR3.BYTE = 0x0F; + dummy_buf_8b = CPG.SYSCR3.BYTE; + (void)dummy_buf_8b; + + RZ_A2_InitClock(); + RZ_A2_InitBus(); + +#if defined(USE_HYPERRAM) + HyperRAM_Init(); +#endif + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + +#if (__L2C_PRESENT == 1) + /* Initial setting of the level 2 cache */ + R_CACHE_L2Init(); + + /* DRP L2 Cache ON */ + PRR.AXIBUSCTL4.BIT.DRPARCACHE = 0xF; + PRR.AXIBUSCTL4.BIT.DRPAWCACHE = 0xF; +#endif + + // IRQ Initialize + IRQ_Initialize(); + + disable_rtc(0); + if (RTC_BCNT1.RCR2.BIT.START == 0) { + disable_rtc(1); + } + disable_usb(0); + disable_usb(1); + + volatile uint16_t dummy_buf_16b; + + // Clear the IOKEEP bit in DSFR + dummy_buf_16b = PMG.DSFR.WORD; + PMG.DSFR.BIT.IOKEEP = 0; + dummy_buf_16b = PMG.DSFR.WORD; + (void)dummy_buf_16b; +} + +void mbed_sdk_init(void) { + /* Initial setting of the level 1 cache */ + R_CACHE_L1Init(); +} + +void soft_reset(void) { + volatile uint16_t data; + WDT.WTCNT.WORD = 0x5A00; + data = WDT.WRCSR.WORD; + (void)data; + WDT.WTCNT.WORD = 0x5A00; + WDT.WRCSR.WORD = 0xA500; + WDT.WTCSR.WORD = 0xA578; + WDT.WRCSR.WORD = 0x5A40; + + while(1){} +} + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/system_RZ_A2M.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/system_RZ_A2M.h new file mode 100644 index 0000000..bc9042c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/device/system_RZ_A2M.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * @file system_RZ_A2M.h + * @brief CMSIS Device System Header File for ARM Cortex-A Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_RZ_A2M_H +#define __SYSTEM_RZ_A2M_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Interrupt Handler Register. + + Registers an Interrupt Handler into the IRQ Table. + */ +extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); + +/** + \brief Interrupt Handler Unregister. + + Unregisters an Interrupt Handler from the IRQ Table. + */ +extern uint32_t InterruptHandlerUnregister(IRQn_Type); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_RZ_A2M_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/mbed_drv_cfg.h new file mode 100644 index 0000000..6aa50fc --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/TARGET_GR_MANGO/mbed_drv_cfg.h @@ -0,0 +1,53 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DRV_CFG_H +#define MBED_DRV_CFG_H + +/* can_api.c */ +#define CAN_TEST_GLOBAL_CH 1 + +/* gpio_api.c */ +#define GPIO_GROUP_MAX 21 + +/* pwmout_api.c */ +#define FUNC_GENERAL_PWM_TIMER + +/* rtc_api.c */ +//#define USE_RTCX1_CLK +#define USE_EXTAL_CLK +#define RENESAS_RZ_A2_P0_CLK CM0_RENESAS_RZ_A2_P0_CLK + +/* flash (MX25UW12845GXDI00) */ +#define USE_OCTAFLASH +#define OCTAFLASH_BASE (0x50000000UL) /**< Flash Base Address */ +#define OCTAFLASH_SIZE (0x01000000UL) /**< Available Flash Memory */ +#define OCTAFLASH_PAGE_SIZE 256 /**< Flash Memory page size (interleaving off) */ + /**< Maximum size per one writing is 256 byte and minimum size per one writing is 1 byte */ +#define OCTAFLASH_SECTOR_SIZE 4096 /**< Flash Memory sector size (interleaving off) */ + +#define FLASH_BASE OCTAFLASH_BASE /**< Flash Base Address */ +#define FLASH_SIZE OCTAFLASH_SIZE /**< Available Flash Memory */ + +/* HyperRAM */ +//#define USE_HYPERRAM + +/* OctaRAM */ +#define USE_OCTARAM +#define OCTARAM_SIZE (0x00800000UL) /**< Available Memory */ + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBEndpoints_RZ_A2.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBEndpoints_RZ_A2.h new file mode 100644 index 0000000..31f55df --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBEndpoints_RZ_A2.h @@ -0,0 +1,84 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2020 ARM Limited, All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#define NUMBER_OF_LOGICAL_ENDPOINTS (16) +#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2) + +/* Define physical endpoint numbers */ + +/* Endpoint No. Type(s) MaxSiz DoubleBuf pipe */ +/* ---------------- --------- ------ --------- ---- */ +#define EP0OUT (0x00) /* Control 256 No 0 */ +#define EP0IN (0x80) /* Control 256 No 0 */ +#define EP1OUT (0x01) /* Int 64 No 6 */ +#define EP1IN (0x81) /* Int 64 No 7 */ +#define EP2OUT (0x02) /* Bulk 2048 Yes 3 */ +#define EP2IN (0x82) /* Bulk 2048 Yes 4 */ +#define EP3OUT (0x03) /* Bulk/Iso 2048 Yes 1 */ +#define EP3IN (0x83) /* Bulk/Iso 2048 Yes 2 */ +/*following EP is not configured in sample program*/ +#define EP6IN (0x86) /* Bulk 2048 Yes 5 */ +#define EP8IN (0x88) /* Int 64 No 8 */ +#define EP9IN (0x89) /* Bulk 512 Bulk 9 */ +#define EP10IN (0x8A) /* Int/Bulk 2048 Bulk 10 */ +#define EP11IN (0x8B) /* Bulk 2048 Yes 11 */ +#define EP12IN (0x8C) /* Bulk 2048 Yes 12 */ +#define EP13IN (0x8D) /* Bulk 2048 Yes 13 */ +#define EP14IN (0x8E) /* Bulk 2048 Yes 14 */ +#define EP15IN (0x8F) /* Bulk 2048 Yes 15 */ + +/* Maximum Packet sizes */ +#define MAX_PACKET_SIZE_EP0 (64) /*pipe0/pipe0: control */ +#define MAX_PACKET_SIZE_EP1 (64) /*pipe6/pipe7: interrupt */ +#define MAX_PACKET_SIZE_EP2 (512) /*pipe3/pipe4: bulk */ +#define MAX_PACKET_SIZE_EP3 (512) /*pipe1/pipe2: isochronous */ +#define MAX_PACKET_SIZE_EP6 (64) /*pipe5: Note *1 */ +#define MAX_PACKET_SIZE_EP8 (64) /*pipe7: Note *1 */ +#define MAX_PACKET_SIZE_EP9 (512) /*pipe8: Note *1 */ +#define MAX_PACKET_SIZE_EP10 (512) /*pipe9: Note *1 */ +#define MAX_PACKET_SIZE_EP11 (512) /*pipe10: Note *1 */ +#define MAX_PACKET_SIZE_EP12 (512) /*pipe11: Note *1 */ +#define MAX_PACKET_SIZE_EP13 (512) /*pipe12: Note *1 */ +#define MAX_PACKET_SIZE_EP14 (512) /*pipe13: Note *1 */ +#define MAX_PACKET_SIZE_EP15 (512) /*pipe14: Note *1 */ +/* Note *1: This pipe is not configure in sample program */ + + +/* Generic endpoints - intended to be portable accross devices */ +/* and be suitable for simple USB devices. */ + +/* Bulk endpoints */ +#define EPBULK_OUT (EP2OUT) +#define EPBULK_IN (EP2IN) +#define EPBULK_OUT_callback EP2_OUT_callback +#define EPBULK_IN_callback EP2_IN_callback +/* Interrupt endpoints */ +#define EPINT_OUT (EP1OUT) +#define EPINT_IN (EP1IN) +#define EPINT_OUT_callback EP1_OUT_callback +#define EPINT_IN_callback EP1_IN_callback +/* Isochronous endpoints */ +#define EPISO_OUT (EP3OUT) +#define EPISO_IN (EP3IN) +#define EPISO_OUT_callback EP3_OUT_callback +#define EPISO_IN_callback EP3_IN_callback + +#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2) +#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1) +#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3) + +/*EOF*/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhyHw.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhyHw.h new file mode 100644 index 0000000..c950c10 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhyHw.h @@ -0,0 +1,103 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2020 ARM Limited, All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USBPHYHW_H +#define USBPHYHW_H + +#include "mbed.h" +#include "USBPhy.h" + + +class USBPhyHw : public USBPhy { +public: + USBPhyHw(); + virtual ~USBPhyHw(); + virtual void init(USBPhyEvents *events); + virtual void deinit(); + virtual bool powered(); + virtual void connect(); + virtual void disconnect(); + virtual void configure(); + virtual void unconfigure(); + virtual void sof_enable(); + virtual void sof_disable(); + virtual void set_address(uint8_t address); + virtual void remote_wakeup(); + virtual const usb_ep_table_t *endpoint_table(); + + virtual uint32_t ep0_set_max_packet(uint32_t max_packet); + virtual void ep0_setup_read_result(uint8_t *buffer, uint32_t size); + virtual void ep0_read(uint8_t *data, uint32_t size); + virtual uint32_t ep0_read_result(); + virtual void ep0_write(uint8_t *buffer, uint32_t size); + virtual void ep0_stall(); + + virtual bool endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type); + virtual void endpoint_remove(usb_ep_t endpoint); + virtual void endpoint_stall(usb_ep_t endpoint); + virtual void endpoint_unstall(usb_ep_t endpoint); + + virtual bool endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size); + virtual uint32_t endpoint_read_result(usb_ep_t endpoint); + virtual bool endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size); + virtual void endpoint_abort(usb_ep_t endpoint); + + virtual void process(); + + static void set_usb_speed(uint8_t speed); // 0: Full Speed 1: HighSpeed + +private: +#define PIPE_NUM (16) + + typedef struct { + bool enable; + uint16_t status; + uint32_t req_size; + uint32_t data_cnt; + uint8_t *p_data; + } pipe_ctrl_t; + + USBPhyEvents *events; + pipe_ctrl_t pipe_ctrl[PIPE_NUM]; + uint16_t setup_buffer[32]; + + static void _usbisr(void); + void chg_curpipe(uint16_t pipe, uint16_t isel); + uint16_t is_set_frdy(uint16_t pipe, uint16_t isel); + uint8_t *read_fifo(uint16_t pipe, uint16_t count, uint8_t *read_p); + uint16_t read_data(uint16_t pipe); + void fifo_to_buf(uint16_t pipe); + uint8_t *write_fifo(uint16_t pipe, uint16_t count, uint8_t *write_p); + uint16_t write_data(uint16_t pipe); + void buf_to_fifo(uint16_t pipe); + uint16_t *get_pipectr_reg(uint16_t pipe); + uint16_t *get_pipetre_reg(uint16_t pipe); + uint16_t *get_pipetrn_reg(uint16_t pipe); + uint16_t get_pid(uint16_t pipe); + void set_mbw(uint16_t pipe, uint16_t data); + void set_pid(uint16_t pipe, uint16_t new_pid); + void cpu_delay_1us(uint16_t time); + uint16_t EP2PIPE(uint16_t endpoint); + uint16_t PIPE2EP(uint16_t pipe); + bool chk_vbsts(void); + void ctrl_end(uint16_t status); + void data_end(uint16_t pipe, uint16_t status); + void forced_termination(uint16_t pipe, uint16_t status); + +}; + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhy_RZ_A2.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhy_RZ_A2.cpp new file mode 100644 index 0000000..479511b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhy_RZ_A2.cpp @@ -0,0 +1,1428 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2020 ARM Limited, All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#if defined(DEVICE_USBDEVICE) && DEVICE_USBDEVICE + +extern "C" +{ +#include "r_typedefs.h" +#include "iodefine.h" +} +#include "USBPhyHw.h" +#include "USBDevice_Types.h" +#include "USBEndpoints_RZ_A2.h" +#include "USBPhy_RZ_A2_Def.h" +#include "pinmap.h" + +/**** User Selection ****/ +#if defined(TARGET_SEMB1402) +#define USB_FUNCTION_CH 0 +#else +#define USB_FUNCTION_CH 1 +#endif +#define USB_FUNCTION_HISPEED 1 // 1: High-Speed 0: Full-Speed + +#if (USB_FUNCTION_CH == 0) +#define USB_MX USB01 +#define USBX0 USB00 +#define USBFIX_IRQn USBFI0_IRQn +#define USBHIX_IRQn USBHI0_IRQn +#else +#define USB_MX USB11 +#define USBX0 USB10 +#define USBFIX_IRQn USBFI1_IRQn +#define USBHIX_IRQn USBHI1_IRQn +#endif + +/* There are maintenance routine of SHTNAK and BFRE bits in original sample program. +* This sample is not programmed. Do maintenance the "def_pipecfg" array if you want it. */ +const struct PIPECFGREC { + uint16_t endpoint; + uint16_t pipesel; + uint16_t pipecfg; + uint16_t pipebuf; + uint16_t pipemaxp; + uint16_t pipeperi; +} def_pipecfg[] = { + /* EP0OUT and EP0IN are configured by USB IP */ + { + EP1OUT, /* EP1: Host -> Func, INT */ + 6, + USB_TYPFIELD_INT | USB_BFREOFF | USB_CFG_DBLBOFF | USB_CFG_CNTMDON | USB_DIR_P_OUT | 1, + USB_BUF_SIZE(64) | 0x04u, + MAX_PACKET_SIZE_EP1, + 3, + }, + { + EP1IN, /* EP1: Host <- Func, INT */ + 7, + USB_TYPFIELD_INT | USB_BFREOFF | USB_CFG_DBLBOFF | USB_CFG_CNTMDOFF | USB_DIR_P_IN | 1, + USB_BUF_SIZE(64) | 0x05u, + MAX_PACKET_SIZE_EP1, + 3, + }, + { + EP2OUT, /* EP2: Host -> Func, BULK */ + 3, + USB_TYPFIELD_BULK | USB_BFREOFF | USB_CFG_DBLBON | USB_CFG_CNTMDON | USB_SHTNAKFIELD | USB_DIR_P_OUT | 2, + USB_BUF_SIZE(2048) | 0x30u, + MAX_PACKET_SIZE_EP2, + 0, + }, + { + EP2IN, /* EP2: Host <- Func, BULK */ + 4, + USB_TYPFIELD_BULK | USB_BFREOFF | USB_CFG_DBLBOFF | USB_CFG_CNTMDON | USB_DIR_P_IN | 2, + USB_BUF_SIZE(2048) | 0x50u, + MAX_PACKET_SIZE_EP2, + 0, + }, + { + EP3OUT, /* EP3: Host -> Func, ISO */ + 1, + USB_TYPFIELD_ISO | USB_BFREOFF | USB_CFG_DBLBON | USB_CFG_CNTMDOFF | USB_SHTNAKFIELD | USB_DIR_P_OUT | 3, + USB_BUF_SIZE(512) | 0x10u, + MAX_PACKET_SIZE_EP3, + 0, + }, + { + EP3IN, /* EP3: Host <- Func, ISO */ + 2, + USB_TYPFIELD_ISO | USB_BFREOFF | USB_CFG_DBLBON | USB_CFG_CNTMDOFF | USB_DIR_P_IN | 3, + USB_BUF_SIZE(512) | 0x20u, + MAX_PACKET_SIZE_EP3, + 0, + }, + { /* terminator */ + 0, 0, 0, 0, 0, 0 + }, +}; + +static USBPhyHw *instance; +static uint8_t _usb_speed = USB_FUNCTION_HISPEED; +static bool run_later_ctrl_comp = false; + +/*static*/ void USBPhyHw::set_usb_speed(uint8_t speed) +{ + _usb_speed = speed; +} + +USBPhy *get_usb_phy() +{ + static USBPhyHw usbphy; + return &usbphy; +} + +USBPhyHw::USBPhyHw(): events(NULL) +{ +} + +USBPhyHw::~USBPhyHw() +{ +} + +void USBPhyHw::init(USBPhyEvents *events) +{ + volatile uint8_t dummy_read; + + if (this->events == NULL) { + sleep_manager_lock_deep_sleep(); + } + this->events = events; + + /* registers me */ + instance = this; + + /* Disable IRQ */ + GIC_DisableIRQ(USBFIX_IRQn); + GIC_DisableIRQ(USBHIX_IRQn); + +#if (USB_FUNCTION_CH == 0) +#if defined(TARGET_SEMB1402) + pin_function(PC_1, 1); /* VBUSIN1 */ +#else + pin_function(P5_2, 3); /* VBUSIN1 */ +#endif + CPG.STBCR6.BIT.MSTP61 = 0; + dummy_read = CPG.STBCR6.BYTE; + CPG.STBREQ3.BYTE &= ~0x03; + dummy_read = CPG.STBREQ3.BYTE; +#else /* (USB_FUNCTION_CH == 1) */ +#if defined(TARGET_GR_MANGO) + pin_function(P2_2, 5); /* VBUSIN1 */ + DigitalOut usb_sel(P2_0); + usb_sel = 1; +#else + pin_function(PC_0, 1); /* VBUSIN1 */ +#endif + CPG.STBCR6.BIT.MSTP60 = 0; + dummy_read = CPG.STBCR6.BYTE; + CPG.STBREQ3.BYTE &= ~0x0C; + dummy_read = CPG.STBREQ3.BYTE; +#endif + (void)dummy_read; + +#if defined(TARGET_GR_MANGO) || defined(TARGET_RZ_A2M_SBEV) || defined(TARGET_SEMB1402) + USBX0.PHYCLK_CTRL.BIT.UCLKSEL = 0; /* EXTAL */ +#else + USBX0.PHYCLK_CTRL.BIT.UCLKSEL = 1; /* USB_X1 */ +#endif + + USBX0.PHYIF_CTRL.LONG = 0x00000000; + USBX0.COMMCTRL.BIT.OTG_PERI = 1; /* 0 : Host, 1 : Peri */ + USB_MX.LPSTS.WORD |= USB_SUSPENDM; + USBX0.USBCTR.LONG = 0x00000000; + cpu_delay_1us(100); /* 100us wait */ + +#if (0) + if (events != NULL) { + sleep_manager_unlock_deep_sleep(); + } +#endif + events = NULL; +} + +void USBPhyHw::deinit() +{ + volatile uint8_t dummy_read; + + disconnect(); + +#if (USB_FUNCTION_CH == 0) + CPG.STBCR6.BIT.MSTP61 = 1; +#else + CPG.STBCR6.BIT.MSTP60 = 1; +#endif + dummy_read = CPG.STBCR6.BYTE; + (void)dummy_read; +} + +bool USBPhyHw::powered() +{ + // return true if powered false otherwise. Devices which don't support + // this should always return true + return true; +} + +void USBPhyHw::connect() +{ + /* Setting MCU(USB interrupt init) register */ + InterruptHandlerRegister(USBFIX_IRQn, &_usbisr); + InterruptHandlerRegister(USBHIX_IRQn, &_usbisr); + GIC_EnableIRQ(USBFIX_IRQn); + GIC_EnableIRQ(USBHIX_IRQn); + GIC_SetConfiguration(USBFIX_IRQn, 1); + GIC_SetConfiguration(USBHIX_IRQn, 1); + GIC_SetPriority(USBFIX_IRQn, 5); + GIC_SetPriority(USBHIX_IRQn, 5); + + /* Setting USB relation register */ + USB_MX.SYSCFG0.WORD |= USB_USBE; + USB_MX.SYSCFG1.WORD = (7 & 0x003f); /* 7 : 9 access cycles waits */ + USB_MX.CFIFOSEL.WORD = USB_MBW_32; + USB_MX.D0FIFOSEL.WORD = USB_MBW_32; + USB_MX.D1FIFOSEL.WORD = USB_MBW_32; + USB_MX.INTENB0.WORD |= (USB_VBSE | USB_SOFE | USB_DVSE | USB_CTRE | USB_BEMPE | USB_NRDYE | USB_BRDYE); + /* Enable pullup on D+ */ + USB_MX.SYSCFG0.WORD |= USB_DPRPU; + if (_usb_speed == 0) { + USB_MX.SYSCFG0.WORD &= ~USB_HSE; + } else { + USB_MX.SYSCFG0.WORD |= USB_HSE; + } + USB_MX.SYSCFG0.WORD &= ~USB_DRPD; +} + +void USBPhyHw::disconnect() +{ + /* Disable USB */ + GIC_DisableIRQ(USBFIX_IRQn); + GIC_DisableIRQ(USBHIX_IRQn); + InterruptHandlerRegister(USBFIX_IRQn, NULL); + InterruptHandlerRegister(USBHIX_IRQn, NULL); + + USB_MX.INTSTS0.WORD = 0; + USB_MX.BRDYSTS.WORD = 0; + USB_MX.NRDYSTS.WORD = 0; + USB_MX.BEMPSTS.WORD = 0; + USB_MX.INTENB0.WORD = 0; + USB_MX.BRDYENB.WORD = 0; + USB_MX.NRDYENB.WORD = 0; + USB_MX.BEMPENB.WORD = 0; + + /* Disable pullup on D+ */ + USB_MX.SYSCFG0.WORD &= (~USB_DPRPU); /* Pull-up disable */ +} + +void USBPhyHw::configure() +{ +} + +void USBPhyHw::unconfigure() +{ +} + +void USBPhyHw::sof_enable() +{ + /* Enable SOF interrupt */ + USB_MX.INTENB0.WORD |= USB_SOFE; +} + +void USBPhyHw::sof_disable() +{ + /* Disable SOF interrupt */ + USB_MX.INTENB0.WORD &= ~USB_SOFE; +} + +void USBPhyHw::set_address(uint8_t address) +{ + if (address <= 127) { + set_pid(USB_PIPE0, USB_PID_BUF); /* Set BUF */ + } else { + set_pid(USB_PIPE0, USB_PID_STALL); /* Not specification */ + } +} + +void USBPhyHw::remote_wakeup() +{ +} + +const usb_ep_table_t *USBPhyHw::endpoint_table() +{ + static const usb_ep_table_t rza1_table = { + 1, // No cost per endpoint - everything allocated up front + { + {USB_EP_ATTR_ALLOW_CTRL | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, + {USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, + {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, + {USB_EP_ATTR_ALLOW_ISO | USB_EP_ATTR_DIR_IN_AND_OUT, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + } + }; + return &rza1_table; +} + +uint32_t USBPhyHw::ep0_set_max_packet(uint32_t max_packet) +{ + return MAX_PACKET_SIZE_EP0; +} + +void USBPhyHw::ep0_setup_read_result(uint8_t *buffer, uint32_t size) +{ + memcpy(buffer, setup_buffer, size); +} + +void USBPhyHw::ep0_read(uint8_t *data, uint32_t size) +{ + pipe_ctrl[USB_PIPE0].req_size = size; + pipe_ctrl[USB_PIPE0].data_cnt = size; + pipe_ctrl[USB_PIPE0].p_data = data; + + chg_curpipe(USB_PIPE0, USB_ISEL_READ); /* Switch FIFO and pipe number. */ + USB_MX.CFIFOCTR.WORD = USB_BCLR; /* Buffer clear */ + set_pid(USB_PIPE0, USB_PID_BUF); /* Set BUF */ + USB_MX.BRDYENB.WORD |= (1 << USB_PIPE0); /* Enable ready interrupt */ + USB_MX.NRDYENB.WORD |= (1 << USB_PIPE0); /* Enable not ready interrupt */ +} + +uint32_t USBPhyHw::ep0_read_result() +{ + return pipe_ctrl[USB_PIPE0].req_size; +} + +void USBPhyHw::ep0_write(uint8_t *buffer, uint32_t size) +{ + if ((buffer == NULL) || (size == 0)) { + set_pid(USB_PIPE0, USB_PID_BUF); /* Set BUF */ + return; + } + + pipe_ctrl[USB_PIPE0].req_size = size; + pipe_ctrl[USB_PIPE0].data_cnt = size; + pipe_ctrl[USB_PIPE0].p_data = buffer; + + chg_curpipe(USB_PIPE0, USB_ISEL_WRITE); /* Switch FIFO and pipe number. */ + USB_MX.CFIFOCTR.WORD = USB_BCLR; /* Buffer clear */ + /* Clear the PIPExBEMP status bit of the specified pipe to clear */ + USB_MX.BEMPSTS.WORD = (uint16_t)((~(1 << USB_PIPE0)) & BEMPSTS_MASK); + + /* Peripheral control sequence */ + switch (write_data(USB_PIPE0)) { + case USB_WRITING : /* Continue of data write */ + USB_MX.BRDYENB.WORD |= (1 << USB_PIPE0);/* Enable Ready interrupt */ + USB_MX.NRDYENB.WORD |= (1 << USB_PIPE0);/* Enable Not Ready Interrupt */ + set_pid(USB_PIPE0, USB_PID_BUF); + break; + case USB_WRITEEND : /* End of data write */ + case USB_WRITESHRT : /* End of data write */ + USB_MX.BEMPENB.WORD |= (1 << USB_PIPE0);/* Enable Empty Interrupt */ + USB_MX.NRDYENB.WORD |= (1 << USB_PIPE0);/* Enable Not Ready Interrupt */ + set_pid(USB_PIPE0, USB_PID_BUF); + break; + case USB_FIFOERROR : /* FIFO access error */ + ctrl_end((uint16_t)USB_DATA_ERR); + break; + default : + break; + } +} + +void USBPhyHw::ep0_stall() +{ + set_pid(USB_PIPE0, USB_PID_STALL); + run_later_ctrl_comp = false; +} + +bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type) +{ + const struct PIPECFGREC *cfg; + uint16_t pipe; + volatile uint16_t *p_reg; + + if ((endpoint == EP0OUT) || (endpoint == EP0IN)) { + return true; + } + + for (cfg = &def_pipecfg[0]; cfg->pipesel != 0; cfg++) { + if (cfg->endpoint == endpoint) { + break; + } + } + if (cfg->pipesel == 0) { + return false; + } + + pipe = (cfg->pipesel & USB_CURPIPE); + + /* Interrupt Disable */ + USB_MX.BRDYENB.WORD &= (~(1 << pipe)); /* Disable Ready Interrupt */ + USB_MX.NRDYENB.WORD &= (~(1 << pipe)); /* Disable Not Ready Interrupt */ + USB_MX.BEMPENB.WORD &= (~(1 << pipe)); /* Disable Empty Interrupt */ + + set_pid(pipe, USB_PID_NAK); + + /* CurrentPIPE Clear */ + if ((USB_MX.CFIFOSEL.WORD & USB_CURPIPE) == pipe) { + USB_MX.CFIFOSEL.WORD &= ~USB_CURPIPE; + } + if ((USB_MX.D0FIFOSEL.WORD & USB_CURPIPE) == pipe) { + USB_MX.D0FIFOSEL.WORD &= ~USB_CURPIPE; + } + if ((USB_MX.D1FIFOSEL.WORD & USB_CURPIPE) == pipe) { + USB_MX.D1FIFOSEL.WORD &= ~USB_CURPIPE; + } + + /* PIPE Configuration */ + USB_MX.PIPESEL.WORD = pipe; /* Pipe select */ + USB_MX.PIPECFG.WORD = cfg->pipecfg; + USB_MX.PIPEBUF.WORD = cfg->pipebuf; + USB_MX.PIPEMAXP.WORD = cfg->pipemaxp; + USB_MX.PIPEPERI.WORD = cfg->pipeperi; + + p_reg = get_pipectr_reg(pipe); + /* Set toggle bit to DATA0 */ + *p_reg |= USB_SQCLR; + /* Buffer Clear */ + *p_reg |= USB_ACLRM; + *p_reg &= ~USB_ACLRM; + + return true; +} + +void USBPhyHw::endpoint_remove(usb_ep_t endpoint) +{ + uint16_t pipe = EP2PIPE(endpoint); + + /* Interrupt Disable */ + USB_MX.BRDYENB.WORD &= (~(1 << pipe)); /* Disable Ready Interrupt */ + USB_MX.NRDYENB.WORD &= (~(1 << pipe)); /* Disable Not Ready Interrupt */ + USB_MX.BEMPENB.WORD &= (~(1 << pipe)); /* Disable Empty Interrupt */ + + set_pid(pipe, USB_PID_NAK); + + /* CurrentPIPE Clear */ + if ((USB_MX.CFIFOSEL.WORD & USB_CURPIPE) == pipe) { + USB_MX.CFIFOSEL.WORD &= ~USB_CURPIPE; + } + if ((USB_MX.D0FIFOSEL.WORD & USB_CURPIPE) == pipe) { + USB_MX.D0FIFOSEL.WORD &= ~USB_CURPIPE; + } + if ((USB_MX.D1FIFOSEL.WORD & USB_CURPIPE) == pipe) { + USB_MX.D1FIFOSEL.WORD &= ~USB_CURPIPE; + } + + /* PIPE Configuration */ + USB_MX.PIPESEL.WORD = pipe; /* Pipe select */ + USB_MX.PIPECFG.WORD = 0; + + pipe_ctrl[pipe].enable = false; + pipe_ctrl[pipe].status = USB_DATA_NONE; +} + +void USBPhyHw::endpoint_stall(usb_ep_t endpoint) +{ + uint16_t pipe = EP2PIPE(endpoint); + + set_pid(pipe, USB_PID_STALL); + + pipe_ctrl[pipe].enable = false; + pipe_ctrl[pipe].status = USB_DATA_STALL; +} + +void USBPhyHw::endpoint_unstall(usb_ep_t endpoint) +{ + uint16_t pipe = EP2PIPE(endpoint); + volatile uint16_t *p_reg; + + set_pid(pipe, USB_PID_NAK); + + p_reg = get_pipectr_reg(pipe); + /* Set toggle bit to DATA0 */ + *p_reg |= USB_SQCLR; + /* Buffer Clear */ + *p_reg |= USB_ACLRM; + *p_reg &= ~USB_ACLRM; + + pipe_ctrl[pipe].enable = false; + pipe_ctrl[pipe].status = USB_DATA_NONE; +} + +bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size) +{ + uint16_t mxps; + uint16_t trncnt; + volatile uint16_t *p_reg; + uint16_t pipe = EP2PIPE(endpoint); + + if (pipe_ctrl[pipe].status == USB_DATA_STALL) { + return false; + } + + pipe_ctrl[pipe].status = USB_DATA_READING; + pipe_ctrl[pipe].req_size = size; + pipe_ctrl[pipe].data_cnt = size; + pipe_ctrl[pipe].p_data = data; + pipe_ctrl[pipe].enable = true; + + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + + USB_MX.BEMPSTS.WORD = (uint16_t)((~(1 << pipe)) & BEMPSTS_MASK); /* BEMP Status Clear */ + USB_MX.BRDYSTS.WORD = (uint16_t)((~(1 << pipe)) & BRDYSTS_MASK); /* BRDY Status Clear */ + USB_MX.NRDYSTS.WORD = (uint16_t)((~(1 << pipe)) & NRDYSTS_MASK); /* NRDY Status Clear */ + + chg_curpipe(pipe, USB_ISEL_READ); /* Switch FIFO and pipe number. */ + USB_MX.CFIFOCTR.WORD = USB_BCLR; /* Clear BCLR */ + + if (size != 0) { + /* Max Packet Size */ + USB_MX.PIPESEL.WORD = pipe; /* Pipe select */ + mxps = (uint16_t)(USB_MX.PIPEMAXP.WORD & USB_MXPS); + /* Data size check */ + if ((size % mxps) == (uint32_t)0u) { + trncnt = (uint16_t)(size / mxps); + } else { + trncnt = (uint16_t)((size / mxps) + (uint32_t)1u); + } + + /* Set Transaction counter */ + p_reg = get_pipetre_reg(pipe); + if (p_reg != NULL) { + *p_reg |= USB_TRCLR; + } + p_reg = get_pipetrn_reg(pipe); + if (p_reg != NULL) { + *p_reg = trncnt; + } + p_reg = get_pipetre_reg(pipe); + if (p_reg != NULL) { + *p_reg |= USB_TRENB; + } + + p_reg = get_pipectr_reg(pipe); + /* Buffer Clear */ + *p_reg |= USB_ACLRM; + *p_reg &= ~USB_ACLRM; + } + + set_pid(pipe, USB_PID_BUF); /* Set BUF */ + USB_MX.BRDYENB.WORD |= (1 << pipe); /* Enable Ready Interrupt */ + USB_MX.NRDYENB.WORD |= (1 << pipe); /* Enable Not Ready Interrupt */ + + return true; +} + +uint32_t USBPhyHw::endpoint_read_result(usb_ep_t endpoint) +{ + uint16_t pipe = EP2PIPE(endpoint); + + return pipe_ctrl[pipe].req_size; +} + +bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size) +{ + volatile uint16_t *p_reg; + uint16_t pipe = EP2PIPE(endpoint); + + if (pipe_ctrl[pipe].status == USB_DATA_STALL) { + return false; + } + + pipe_ctrl[pipe].status = USB_DATA_WRITING; + pipe_ctrl[pipe].req_size = size; + pipe_ctrl[pipe].data_cnt = size; + pipe_ctrl[pipe].p_data = data; + pipe_ctrl[pipe].enable = true; + + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + + USB_MX.BEMPSTS.WORD = (uint16_t)((~(1 << pipe)) & BEMPSTS_MASK);/* BEMP Status Clear */ + USB_MX.BRDYSTS.WORD = (uint16_t)((~(1 << pipe)) & BRDYSTS_MASK);/* BRDY Status Clear */ + USB_MX.NRDYSTS.WORD = (uint16_t)((~(1 << pipe)) & NRDYSTS_MASK);/* NRDY Status Clear */ + + p_reg = get_pipectr_reg(pipe); + /* Buffer Clear */ + *p_reg |= USB_ACLRM; + *p_reg &= ~USB_ACLRM; + + buf_to_fifo(pipe); /* Buffer to FIFO data write */ + set_pid(pipe, USB_PID_BUF); /* Set BUF */ + + return true; +} + +void USBPhyHw::endpoint_abort(usb_ep_t endpoint) +{ + forced_termination(EP2PIPE(endpoint), (uint16_t)USB_DATA_NONE); +} + +void USBPhyHw::process() +{ + /* Register Save */ + uint16_t intsts0 = USB_MX.INTSTS0.WORD; + uint16_t brdysts = USB_MX.BRDYSTS.WORD; + uint16_t nrdysts = USB_MX.NRDYSTS.WORD; + uint16_t bempsts = USB_MX.BEMPSTS.WORD; + uint16_t intenb0 = USB_MX.INTENB0.WORD; + uint16_t brdyenb = USB_MX.BRDYENB.WORD; + uint16_t nrdyenb = USB_MX.NRDYENB.WORD; + uint16_t bempenb = USB_MX.BEMPENB.WORD; + + /* Interrupt status get */ + uint16_t ists0 = (uint16_t)(intsts0 & intenb0); + uint16_t bsts = (uint16_t)(brdysts & brdyenb); + uint16_t nsts = (uint16_t)(nrdysts & nrdyenb); + uint16_t ests = (uint16_t)(bempsts & bempenb); + + uint16_t i; + + if ((intsts0 & (USB_VBINT | USB_RESM | USB_SOFR | USB_DVST | + USB_CTRT | USB_BEMP | USB_NRDY | USB_BRDY)) == 0u) { + return; + } + + /***** Processing USB bus signal *****/ + /***** Resume signal *****/ + if ((ists0 & USB_RESM) == USB_RESM) { + USB_MX.INTSTS0.WORD = (uint16_t)~USB_RESM; + USB_MX.INTENB0.WORD &= (~USB_RSME); /* RESM interrupt disable */ + events->suspend(true); + } + + /***** Vbus change *****/ + else if ((ists0 & USB_VBINT) == USB_VBINT) { + USB_MX.INTSTS0.WORD = (uint16_t)~USB_VBINT; + if (chk_vbsts()) { + /* USB attach */ + USB_MX.SYSCFG0.WORD |= USB_CNEN; + } else { + /* USB detach */ + USB_MX.SYSCFG0.WORD &= (~USB_CNEN); + for (i = USB_MIN_PIPE_NO; i < PIPE_NUM; i++) { + if (pipe_ctrl[i].enable) { + forced_termination(i, (uint16_t)USB_DATA_NONE); + } + } + USB_MX.INTSTS0.WORD = 0; + USB_MX.BRDYSTS.WORD = 0; + USB_MX.NRDYSTS.WORD = 0; + USB_MX.BEMPSTS.WORD = 0; + USB_MX.BRDYENB.WORD = 0; + USB_MX.NRDYENB.WORD = 0; + USB_MX.BEMPENB.WORD = 0; + } + } + + /***** SOFR change *****/ + else if ((ists0 & USB_SOFR) == USB_SOFR) { + USB_MX.INTSTS0.WORD = (uint16_t)~USB_SOFR; + events->sof(USB_MX.FRMNUM.BIT.FRNM & USB_FRNM); + } + + /***** Processing device state *****/ + /***** DVST change *****/ + else if ((ists0 & USB_DVST) == USB_DVST) { + USB_MX.INTSTS0.WORD = (uint16_t)~USB_DVST; + + switch ((uint16_t)(intsts0 & USB_DVSQ)) { + case USB_DS_POWR : + break; + case USB_DS_DFLT : + USB_MX.DCPCFG.WORD = 0; /* DCP configuration register (0x5C) */ + USB_MX.DCPMAXP.WORD = MAX_PACKET_SIZE_EP0; /* DCP maxpacket size register (0x5E) */ + + events->reset(); + break; + case USB_DS_ADDS : + break; + case USB_DS_CNFG : + break; + case USB_DS_SPD_POWR : + case USB_DS_SPD_DFLT : + case USB_DS_SPD_ADDR : + case USB_DS_SPD_CNFG : + events->suspend(false); + break; + default : + break; + } + } + + /***** Processing PIPE0 data *****/ + else if (((ists0 & USB_BRDY) == USB_BRDY) && ((bsts & USB_BRDY0) == USB_BRDY0)) { + /* ==== BRDY PIPE0 ==== */ + USB_MX.BRDYSTS.WORD = (uint16_t)((~USB_BRDY0) & BRDYSTS_MASK); + + /* When operating by the peripheral function, usb_brdy_pipe() is executed with PIPEx request because */ + /* two BRDY messages are issued even when the demand of PIPE0 and PIPEx has been generated at the same time. */ + if ((USB_MX.CFIFOSEL.WORD & USB_ISEL_WRITE) == USB_ISEL_WRITE) { + switch (write_data(USB_PIPE0)) { + case USB_WRITEEND : + case USB_WRITESHRT : + USB_MX.BRDYENB.WORD &= (~(1 << USB_PIPE0)); + break; + case USB_WRITING : + set_pid(USB_PIPE0, USB_PID_BUF); + break; + case USB_FIFOERROR : + ctrl_end((uint16_t)USB_DATA_ERR); + break; + default : + break; + } + events->ep0_in(); + } else { + switch (read_data(USB_PIPE0)) { + case USB_READEND : + case USB_READSHRT : + USB_MX.BRDYENB.WORD &= (~(1 << USB_PIPE0)); + pipe_ctrl[USB_PIPE0].req_size -= pipe_ctrl[USB_PIPE0].data_cnt; + break; + case USB_READING : + set_pid(USB_PIPE0, USB_PID_BUF); + break; + case USB_READOVER : + ctrl_end((uint16_t)USB_DATA_OVR); + pipe_ctrl[USB_PIPE0].req_size -= pipe_ctrl[USB_PIPE0].data_cnt; + break; + case USB_FIFOERROR : + ctrl_end((uint16_t)USB_DATA_ERR); + break; + default : + break; + } + events->ep0_out(); + } + } + else if (((ists0 & USB_BEMP) == USB_BEMP) && ((ests & USB_BEMP0) == USB_BEMP0)) { + /* ==== BEMP PIPE0 ==== */ + USB_MX.BEMPSTS.WORD = (uint16_t)((~USB_BEMP0) & BEMPSTS_MASK); + + events->ep0_in(); + } + else if (((ists0 & USB_NRDY) == USB_NRDY) && ((nsts & USB_NRDY0) == USB_NRDY0)) { + /* ==== NRDY PIPE0 ==== */ + USB_MX.NRDYSTS.WORD = (uint16_t)((~USB_NRDY0) & NRDYSTS_MASK); + /* Non processing. */ + } + + /***** Processing setup transaction *****/ + else if ((ists0 & USB_CTRT) == USB_CTRT) { + USB_MX.INTSTS0.WORD = (uint16_t)~USB_CTRT; + + /* CTSQ bit changes later than CTRT bit for ASSP. */ + /* CTSQ reloading */ + uint16_t stginfo = (uint16_t)(intsts0 & USB_CTSQ); + if (stginfo != USB_CS_IDST) { + if (((USB_CS_RDDS == stginfo) || (USB_CS_WRDS == stginfo)) || (USB_CS_WRND == stginfo)) { + /* Save request register */ + uint16_t *bufO = &setup_buffer[0]; + + USB_MX.INTSTS0.WORD = (uint16_t)~USB_VALID; + *bufO++ = USB_MX.USBREQ.WORD; /* data[0] <= bmRequest, data[1] <= bmRequestType */ + *bufO++ = USB_MX.USBVAL.WORD; /* data[2] data[3] <= wValue */ + *bufO++ = USB_MX.USBINDX.WORD; /* data[4] data[5] <= wIndex */ + *bufO++ = USB_MX.USBLENG.WORD; /* data[6] data[7] <= wLength */ + } + } + + /* Switch on the control transfer stage (CTSQ). */ + switch (stginfo) { + case USB_CS_IDST : /* Idle or setup stage */ + break; + case USB_CS_RDDS : /* Control read data stage */ + events->ep0_setup(); + break; + case USB_CS_WRDS : /* Control write data stage */ + events->ep0_setup(); + break; + case USB_CS_WRND : /* Status stage of a control write where there is no data stage. */ + events->ep0_setup(); + run_later_ctrl_comp = true; + break; + case USB_CS_RDSS : /* Control read status stage */ + USB_MX.DCPCTR.WORD |= USB_CCPL; + break; + case USB_CS_WRSS : /* Control write status stage */ + USB_MX.DCPCTR.WORD |= USB_CCPL; + break; + case USB_CS_SQER : /* Control sequence error */ + default : /* Illegal */ + ctrl_end((uint16_t)USB_DATA_ERR); + break; + } + } + + /***** Processing PIPE1-MAX_PIPE_NO data *****/ + else if ((ists0 & USB_BRDY) == USB_BRDY) { + /* ==== BRDY PIPEx ==== */ + USB_MX.BRDYSTS.WORD = (uint16_t)((~bsts) & BRDYSTS_MASK); + + for (i = USB_MIN_PIPE_NO; i < PIPE_NUM; i++) { + if ((bsts & USB_BITSET(i)) != 0u) { + /* Interrupt check */ + if (pipe_ctrl[i].enable) { + USB_MX.PIPESEL.WORD = i; /* Pipe select */ + if (USB_BUF2FIFO == (uint16_t)(USB_MX.PIPECFG.WORD & USB_DIRFIELD)) { + /* write */ + buf_to_fifo(i); /* Buffer to FIFO data write */ + events->in(PIPE2EP(i)); + } else { + /* read */ + fifo_to_buf(i); /* FIFO to Buffer data read */ + events->out(PIPE2EP(i)); + } + } + } + } + } + else if ((ists0 & USB_BEMP) == USB_BEMP) { + /* ==== BEMP PIPEx ==== */ + USB_MX.BEMPSTS.WORD = (uint16_t)((~ests) & BEMPSTS_MASK); + + for (i = USB_MIN_PIPE_NO; i < PIPE_NUM; i++) { + if ((ests & USB_BITSET(i)) != 0) { + /* Interrupt check */ + if (pipe_ctrl[i].enable) { + /* MAX packet size error ? */ + if (((get_pid(i) & USB_PID_STALL) == USB_PID_STALL) || ((get_pid(i) & USB_PID_STALL2) == USB_PID_STALL2)) { + forced_termination(i, (uint16_t)USB_DATA_STALL); + } else { + if ((i >= USB_PIPE6) || ((*get_pipectr_reg(i) & USB_INBUFM) != USB_INBUFM)) { + data_end(i, (uint16_t)USB_DATA_NONE); /* End of data transfer */ + } else { + USB_MX.BEMPENB.WORD |= (1 << i); + } + } + events->in(PIPE2EP(i)); + } + } + } + } + else if ((ists0 & USB_NRDY) == USB_NRDY) { + /* ==== NRDY PIPEx ==== */ + USB_MX.NRDYSTS.WORD = (uint16_t)((~nsts) & NRDYSTS_MASK); + + for (i = USB_MIN_PIPE_NO; i < PIPE_NUM; i++) { + if ((nsts & USB_BITSET(i)) != 0) { + /* Interrupt check */ + if (pipe_ctrl[i].enable) { + if (((get_pid(i) & USB_PID_STALL) != USB_PID_STALL) && ((get_pid(i) & USB_PID_STALL2) != USB_PID_STALL2)) { + set_pid(i, USB_PID_BUF); + } + } + } + } + } + else { + /* Non processing. */ + } +} + +void USBPhyHw::_usbisr(void) +{ + GIC_DisableIRQ(USBFIX_IRQn); + GIC_DisableIRQ(USBHIX_IRQn); + + run_later_ctrl_comp = false; + + instance->events->start_process(); + + if (run_later_ctrl_comp) { + USB_MX.DCPCTR.WORD &= (~USB_PID); + USB_MX.DCPCTR.WORD |= USB_PID_BUF; + USB_MX.DCPCTR.WORD |= USB_CCPL; + } + + // Re-enable interrupt + GIC_ClearPendingIRQ(USBFIX_IRQn); + GIC_ClearPendingIRQ(USBHIX_IRQn); + GIC_EnableIRQ(USBFIX_IRQn); + GIC_EnableIRQ(USBHIX_IRQn); +} + +void USBPhyHw::chg_curpipe(uint16_t pipe, uint16_t isel) +{ + uint16_t buf; + + buf = USB_MX.CFIFOSEL.WORD; + buf &= (uint16_t)(~(USB_RCNT | USB_ISEL | USB_CURPIPE | USB_MBW)); + buf |= (uint16_t)((USB_RCNT | isel | pipe | USB_MBW_32) & (USB_RCNT | USB_ISEL | USB_CURPIPE | USB_MBW)); + USB_MX.CFIFOSEL.WORD = buf; + + do { + cpu_delay_1us(1); + buf = USB_MX.CFIFOSEL.WORD; + } while ((buf & (uint16_t)(USB_ISEL | USB_CURPIPE)) != (uint16_t)(isel | pipe)); +} + +uint16_t USBPhyHw::is_set_frdy(uint16_t pipe, uint16_t isel) +{ + uint16_t buffer; + int retry_cnt = 0; + + chg_curpipe(pipe, isel); /* Changes the FIFO port by the pipe. */ + for (retry_cnt = 0; retry_cnt < 10; retry_cnt++) { + buffer = USB_MX.CFIFOCTR.WORD; + if ((uint16_t)(buffer & USB_FRDY) == USB_FRDY) { + return (buffer); + } + cpu_delay_1us(1); + } + + return (USB_FIFOERROR); +} + +uint8_t *USBPhyHw::read_fifo(uint16_t pipe, uint16_t count, uint8_t *read_p) +{ + uint16_t even; + uint16_t odd; + uint32_t odd_byte_data_temp; + + for (even = (uint16_t)(count >> 2); (even != 0); --even) { + /* 32bit FIFO access */ + *((uint32_t *)read_p) = USB_MX.CFIFO.LONG; + read_p += sizeof(uint32_t); + } + odd = count % 4; + if (count < 4) { + odd = count; + } + if (odd != 0) { + /* 32bit FIFO access */ + odd_byte_data_temp = USB_MX.CFIFO.LONG; + /* Condition compilation by the difference of the endian */ + do { + *read_p = (uint8_t)(odd_byte_data_temp & 0x000000ff); + odd_byte_data_temp = odd_byte_data_temp >> 8; + /* Renewal read pointer */ + read_p += sizeof(uint8_t); + odd--; + } while (odd != 0); + } + + return read_p; +} + +uint16_t USBPhyHw::read_data(uint16_t pipe) +{ + uint16_t count; + uint16_t buffer; + uint16_t mxps; + uint16_t dtln; + uint16_t end_flag; + + /* Changes FIFO port by the pipe. */ + buffer = is_set_frdy(pipe, 0); + if (buffer == USB_FIFOERROR) { + return (USB_FIFOERROR); /* FIFO access error */ + } + dtln = (uint16_t)(buffer & USB_DTLN); + + /* Max Packet Size */ + if (pipe == USB_PIPE0) { + mxps = (uint16_t)(USB_MX.DCPMAXP.WORD & USB_MAXP); + } else { + USB_MX.PIPESEL.WORD = pipe; /* Pipe select */ + mxps = (uint16_t)(USB_MX.PIPEMAXP.WORD & USB_MXPS); + } + + if (pipe_ctrl[pipe].data_cnt < dtln) { + /* Buffer Over ? */ + end_flag = USB_READOVER; + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + count = (uint16_t)pipe_ctrl[pipe].data_cnt; + pipe_ctrl[pipe].data_cnt = dtln; + } else if (pipe_ctrl[pipe].data_cnt == dtln) { + /* Just Receive Size */ + count = dtln; + if ((count == 0) || ((dtln % mxps) != 0)) { + /* Just Receive Size */ + /* Peripheral Function */ + end_flag = USB_READSHRT; + } else { + end_flag = USB_READEND; + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + } + } else { + /* Continuous Receive data */ + count = dtln; + end_flag = USB_READING; + if (count == 0) { + /* Null Packet receive */ + end_flag = USB_READSHRT; + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + } + if ((count % mxps) != 0) { + /* Null Packet receive */ + end_flag = USB_READSHRT; + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + } + } + + if (dtln == 0) { /* 0 length packet */ + USB_MX.CFIFOCTR.WORD = USB_BCLR; /* Clear BCLR */ + } else { + pipe_ctrl[pipe].p_data = read_fifo(pipe, count, pipe_ctrl[pipe].p_data); + } + pipe_ctrl[pipe].data_cnt -= count; + + return end_flag; +} + +void USBPhyHw::fifo_to_buf(uint16_t pipe) +{ + /* Check FIFO access sequence */ + switch (read_data(pipe)) { + case USB_READING : /* Continue of data read */ + break; + case USB_READEND : /* End of data read */ + data_end(pipe, (uint16_t)USB_DATA_OK); + pipe_ctrl[pipe].req_size -= pipe_ctrl[pipe].data_cnt; + break; + case USB_READSHRT : /* End of data read */ + data_end(pipe, (uint16_t)USB_DATA_SHT); + pipe_ctrl[pipe].req_size -= pipe_ctrl[pipe].data_cnt; + break; + case USB_READOVER : /* Buffer over */ + forced_termination(pipe, (uint16_t)USB_DATA_OVR); + pipe_ctrl[pipe].req_size -= pipe_ctrl[pipe].data_cnt; + break; + case USB_FIFOERROR : /* FIFO access error */ + default: + forced_termination(pipe, (uint16_t)USB_DATA_ERR); + break; + } +} + +uint8_t *USBPhyHw::write_fifo(uint16_t pipe, uint16_t count, uint8_t *write_p) +{ + uint16_t even; + uint16_t odd; + + set_mbw(pipe, USB_MBW_32); /* 32bit access */ + for (even = (uint16_t)(count >> 2); (even != 0); --even) { + USB_MX.CFIFO.LONG = *((uint32_t *)write_p); + write_p += sizeof(uint32_t); + } + odd = count % 4; + if ((odd & (uint16_t)0x0002u) != 0u) { + set_mbw(pipe, USB_MBW_16); /* 16bit access */ + USB_MX.CFIFO.WORD.L = *((uint16_t *)write_p); + write_p += sizeof(uint16_t); + } + if ((odd & (uint16_t)0x0001u) != 0u) { + set_mbw(pipe, USB_MBW_8); /* 8bit access */ + USB_MX.CFIFO.BYTE.LL = *write_p; + write_p++; + } + + return write_p; +} + +uint16_t USBPhyHw::write_data(uint16_t pipe) +{ + uint16_t size; + uint16_t count; + uint16_t mxps; + uint16_t end_flag; + uint16_t buffer; + + /* Changes FIFO port by the pipe. */ + if (pipe == USB_PIPE0) { + buffer = is_set_frdy(pipe, USB_ISEL_WRITE); + } else { + buffer = is_set_frdy(pipe, 0); + } + + if (buffer == USB_FIFOERROR) { + return (USB_FIFOERROR); + } + + if (pipe == USB_PIPE0) { + /* Max Packet Size */ + mxps = (uint16_t)(USB_MX.DCPMAXP.WORD & USB_MAXP); + + /* Data buffer size */ + if ((USB_MX.DCPCFG.WORD & USB_CNTMDFIELD) == USB_CFG_CNTMDON) { + size = USB_PIPE0BUF; + } else { + size = mxps; + } + } else { + /* Max Packet Size */ + USB_MX.PIPESEL.WORD = pipe; /* Pipe select */ + mxps = (uint16_t)(USB_MX.PIPEMAXP.WORD & USB_MXPS); + + /* Data buffer size */ + if ((USB_MX.PIPECFG.WORD & USB_CNTMDFIELD) == USB_CFG_CNTMDON) { + size = (uint16_t)((uint16_t)((USB_MX.PIPEBUF.WORD >> USB_BUFSIZE_BIT) + 1) * USB_PIPEXBUF); + } else { + size = mxps; + } + } + + /* Data size check */ + if (pipe_ctrl[pipe].data_cnt <= (uint32_t)size) { + count = (uint16_t)pipe_ctrl[pipe].data_cnt; + if (count == 0) { + end_flag = USB_WRITESHRT; /* Null Packet is end of write */ + } else if ((count % mxps) != 0) { + end_flag = USB_WRITESHRT; /* Short Packet is end of write */ + } else { + end_flag = USB_WRITEEND; /* Just Send Size */ + } + } else { + /* Write continues */ + end_flag = USB_WRITING; + count = size; + } + + pipe_ctrl[pipe].p_data = write_fifo(pipe, count, pipe_ctrl[pipe].p_data); + + /* Check data count to remain */ + if (pipe_ctrl[pipe].data_cnt < (uint32_t)size) { + pipe_ctrl[pipe].data_cnt = 0u; /* Clear data count */ + + if ((USB_MX.CFIFOCTR.WORD & USB_BVAL) == 0u) { /* Check BVAL */ + USB_MX.CFIFOCTR.WORD |= USB_BVAL; /* Short Packet */ + } + } else { + pipe_ctrl[pipe].data_cnt -= count; /* Total data count - count */ + } + + return end_flag; +} + +void USBPhyHw::buf_to_fifo(uint16_t pipe) +{ + /* Disable Ready Interrupt */ + USB_MX.BRDYENB.WORD &= (~(1 << pipe)); + + /* Peripheral control sequence */ + switch (write_data(pipe)) { + case USB_WRITING: /* Continue of data write */ + USB_MX.BRDYENB.WORD |= (1 << pipe); /* Enable Ready Interrupt */ + USB_MX.NRDYENB.WORD |= (1 << pipe); /* Enable Not Ready Interrupt */ + break; + case USB_WRITEEND: /* End of data write */ + case USB_WRITESHRT: /* End of data write */ + USB_MX.BEMPENB.WORD |= (1 << pipe); /* Enable Empty Interrupt */ + USB_MX.NRDYENB.WORD |= (1 << pipe); /* Enable Not Ready Interrupt */ + break; + case USB_FIFOERROR: /* FIFO access error */ + default: + forced_termination(pipe, (uint16_t)USB_DATA_ERR); + break; + } +} + +uint16_t *USBPhyHw::get_pipectr_reg(uint16_t pipe) +{ + if (pipe == USB_PIPE0) { + return (uint16_t *) & (USB_MX.DCPCTR); + } else { + return (uint16_t *) & (USB_MX.PIPE1CTR) + (pipe - USB_PIPE1); + } +} + +uint16_t *USBPhyHw::get_pipetre_reg(uint16_t pipe) +{ + if ((pipe >= USB_PIPE1) && (pipe <= USB_PIPE5)) { + return (uint16_t *) & (USB_MX.PIPE1TRE) + ((pipe - USB_PIPE1) * 2); + } else if ((pipe >= USB_PIPE9) && (pipe <= USB_PIPE10)) { + return (uint16_t *) & (USB_MX.PIPE9TRE) + ((pipe - USB_PIPE9) * 2); + } else if ((pipe >= USB_PIPE11) && (pipe <= USB_PIPE15)) { + return (uint16_t *) & (USB_MX.PIPEBTRE) + ((pipe - USB_PIPE11) * 2); + } else { + return NULL; + } +} + +uint16_t *USBPhyHw::get_pipetrn_reg(uint16_t pipe) +{ + if ((pipe >= USB_PIPE1) && (pipe <= USB_PIPE5)) { + return (uint16_t *) & (USB_MX.PIPE1TRN) + ((pipe - USB_PIPE1) * 2); + } else if ((pipe >= USB_PIPE9) && (pipe <= USB_PIPE10)) { + return (uint16_t *) & (USB_MX.PIPE9TRN) + ((pipe - USB_PIPE9) * 2); + } else if ((pipe >= USB_PIPE11) && (pipe <= USB_PIPE15)) { + return (uint16_t *) & (USB_MX.PIPEBTRN) + ((pipe - USB_PIPE11) * 2); + } else { + return NULL; + } +} + +uint16_t USBPhyHw::get_pid(uint16_t pipe) +{ + volatile uint16_t *p_reg; + + p_reg = get_pipectr_reg(pipe); + return (uint16_t)(*p_reg & USB_PID); +} + +void USBPhyHw::set_mbw(uint16_t pipe, uint16_t data) +{ + USB_MX.CFIFOSEL.WORD &= (~USB_MBW); + if (data != 0) { + USB_MX.CFIFOSEL.WORD |= data; + } + (void)pipe; +} + +void USBPhyHw::set_pid(uint16_t pipe, uint16_t new_pid) +{ + volatile uint16_t *p_reg; + uint16_t old_pid; + + p_reg = get_pipectr_reg(pipe); + old_pid = get_pid(pipe); + + switch (new_pid) { + case USB_PID_STALL: + if ((old_pid & USB_PID_BUF) == USB_PID_BUF) { + *p_reg &= (~USB_PID); + *p_reg |= USB_PID_STALL2; + } else { + *p_reg &= (~USB_PID); + *p_reg |= new_pid; + } + break; + case USB_PID_BUF: + if (((old_pid & USB_PID_STALL) == USB_PID_STALL) || + ((old_pid & USB_PID_STALL2) == USB_PID_STALL2)) { + *p_reg &= (~USB_PID); + *p_reg |= USB_PID_NAK; + } + *p_reg &= (~USB_PID); + *p_reg |= new_pid; + break; + case USB_PID_NAK: + if ((old_pid & USB_PID_STALL2) == USB_PID_STALL2) { + *p_reg &= (~USB_PID); + *p_reg |= USB_PID_STALL; + } + *p_reg &= (~USB_PID); + *p_reg |= new_pid; + + do { + cpu_delay_1us(1); + p_reg = get_pipectr_reg(pipe); + } while ((*p_reg & USB_PBUSY) == USB_PBUSY); + break; + default: + *p_reg &= (~USB_PID); + *p_reg |= new_pid; + break; + } +} + +void USBPhyHw::cpu_delay_1us(uint16_t time) +{ + volatile uint32_t i = 48 * time; + + while (i > 0) { + i--; + } +} + +uint16_t USBPhyHw::EP2PIPE(uint16_t endpoint) +{ + const struct PIPECFGREC *cfg; + + for (cfg = &def_pipecfg[0]; cfg->pipesel != 0; cfg++) { + if (cfg->endpoint == endpoint) { + break; + } + } + return (cfg->pipesel & USB_CURPIPE); +} + +uint16_t USBPhyHw::PIPE2EP(uint16_t pipe) +{ + const struct PIPECFGREC *cfg; + + if (pipe == USB_PIPE0) { + return 0; + } + for (cfg = &def_pipecfg[0]; cfg->pipesel != 0; cfg++) { + if ((cfg->pipesel & USB_CURPIPE) == pipe) { + break; + } + } + return cfg->endpoint; +} + +bool USBPhyHw::chk_vbsts(void) +{ + uint16_t buf1; + uint16_t buf2; + uint16_t buf3; + bool connect_flg = false; + + /* VBUS chattering cut */ + do { + buf1 = USB_MX.INTSTS0.WORD; + cpu_delay_1us(10); + buf2 = USB_MX.INTSTS0.WORD; + cpu_delay_1us(10); + buf3 = USB_MX.INTSTS0.WORD; + } while (((buf1 & USB_VBSTS) != (buf2 & USB_VBSTS)) || ((buf2 & USB_VBSTS) != (buf3 & USB_VBSTS))); + + /* VBUS status judge */ + if ((buf1 & USB_VBSTS) != (uint16_t)0) { + connect_flg = true; + } + + return connect_flg; +} + +void USBPhyHw::ctrl_end(uint16_t status) +{ + /* Interrupt disable */ + USB_MX.BEMPENB.WORD &= (~(1 << USB_PIPE0)); /* Disable Empty Interrupt */ + USB_MX.BRDYENB.WORD &= (~(1 << USB_PIPE0)); /* Disable Ready Interrupt */ + USB_MX.NRDYENB.WORD &= (~(1 << USB_PIPE0)); /* Disable Not Ready Interrupt */ + + set_mbw(USB_PIPE0, USB_MBW_32); + + if ((status == USB_DATA_ERR) || (status == USB_DATA_OVR)) { + set_pid(USB_PIPE0, USB_PID_STALL); /* Request error */ + } else if (status == USB_DATA_STOP) { + set_pid(USB_PIPE0, USB_PID_NAK); /* Pipe stop */ + } else { + USB_MX.DCPCTR.WORD |= USB_CCPL; /* Set CCPL bit */ + } +} + +void USBPhyHw::data_end(uint16_t pipe, uint16_t status) +{ + volatile uint16_t *p_reg; + + /* Disable Interrupt */ + USB_MX.BRDYENB.WORD &= (~(1 << pipe)); /* Disable Ready Interrupt */ + USB_MX.NRDYENB.WORD &= (~(1 << pipe)); /* Disable Not Ready Interrupt */ + USB_MX.BEMPENB.WORD &= (~(1 << pipe)); /* Disable Empty Interrupt */ + + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + + /* Disable Transaction count */ + p_reg = get_pipetre_reg(pipe); + if (p_reg != NULL) { + *p_reg &= (~USB_TRENB); + *p_reg |= USB_TRCLR; + } + + if (pipe_ctrl[pipe].enable) { + /* Check PIPE TYPE */ + USB_MX.PIPESEL.WORD = pipe; /* Pipe select */ + if ((USB_MX.PIPECFG.WORD & USB_TYPFIELD) != USB_TYPFIELD_ISO) { + /* Transfer information set */ + pipe_ctrl[pipe].enable = false; + pipe_ctrl[pipe].status = status; + } else if ((uint16_t)(USB_MX.PIPECFG.WORD & USB_DIRFIELD) == USB_BUF2FIFO) { + /* ISO OUT Transfer (restart) */ + pipe_ctrl[pipe].status = USB_DATA_WRITING; + } else { + /* ISO IN Transfer (restart) */ + pipe_ctrl[pipe].status = USB_DATA_READING; + } + } +} + +void USBPhyHw::forced_termination(uint16_t pipe, uint16_t status) +{ + volatile uint16_t *p_reg; + + /* Disable Interrupt */ + USB_MX.BRDYENB.WORD &= (~(1 << pipe)); /* Disable Ready Interrupt */ + USB_MX.NRDYENB.WORD &= (~(1 << pipe)); /* Disable Not Ready Interrupt */ + USB_MX.BEMPENB.WORD &= (~(1 << pipe)); /* Disable Empty Interrupt */ + + set_pid(pipe, USB_PID_NAK); /* Set NAK */ + + /* Disable Transaction count */ + p_reg = get_pipetre_reg(pipe); + if (p_reg != NULL) { + *p_reg &= (~USB_TRENB); + *p_reg |= USB_TRCLR; + } + + set_mbw(pipe, USB_MBW_32); + + chg_curpipe(pipe, 0); /* Changes the FIFO port by the pipe. */ + + p_reg = get_pipectr_reg(pipe); + /* Buffer Clear */ + *p_reg |= USB_ACLRM; + *p_reg &= ~USB_ACLRM; + + pipe_ctrl[pipe].enable = false; + pipe_ctrl[pipe].status = status; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhy_RZ_A2_Def.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhy_RZ_A2_Def.h new file mode 100644 index 0000000..58b2d2a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/USBPhy_RZ_A2_Def.h @@ -0,0 +1,695 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2020 ARM Limited, All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef USBPHY_RZ_A2_DEF +#define USBPHY_RZ_A2_DEF + +/****************************************************************************** + Macro definitions + ******************************************************************************/ + +/* H/W function type */ +#define USB_BIT0 ((uint16_t)0x0001) +#define USB_BIT1 ((uint16_t)0x0002) +#define USB_BIT2 ((uint16_t)0x0004) +#define USB_BIT3 ((uint16_t)0x0008) +#define USB_BIT4 ((uint16_t)0x0010) +#define USB_BIT5 ((uint16_t)0x0020) +#define USB_BIT6 ((uint16_t)0x0040) +#define USB_BIT7 ((uint16_t)0x0080) +#define USB_BIT8 ((uint16_t)0x0100) +#define USB_BIT9 ((uint16_t)0x0200) +#define USB_BIT10 ((uint16_t)0x0400) +#define USB_BIT11 ((uint16_t)0x0800) +#define USB_BIT12 ((uint16_t)0x1000) +#define USB_BIT13 ((uint16_t)0x2000) +#define USB_BIT14 ((uint16_t)0x4000) +#define USB_BIT15 ((uint16_t)0x8000) +#define USB_BITSET(x) ((uint16_t)((uint16_t)1 << (x))) + +/* Start Pipe No */ +#define USB_MIN_PIPE_NO (1u) + +/* Pipe configuration table define */ +#define USB_EPL (6u) /* Pipe configuration table length */ +#define USB_TYPFIELD (0xC000u) /* Transfer type */ +#define USB_PERIODIC (0x8000u) /* Periodic pipe */ +#define USB_TYPFIELD_ISO (0xC000u) /* Isochronous */ +#define USB_TYPFIELD_INT (0x8000u) /* Interrupt */ +#define USB_TYPFIELD_BULK (0x4000u) /* Bulk */ +#define USB_NOUSE (0x0000u) /* Not configuration */ +#define USB_BFREFIELD (0x0400u) /* Buffer ready interrupt mode select */ +#define USB_BFREON (0x0400u) +#define USB_BFREOFF (0x0000u) +#define USB_DBLBFIELD (0x0200u) /* Double buffer mode select */ +#define USB_CFG_DBLBON (0x0200u) +#define USB_CFG_DBLBOFF (0x0000u) +#define USB_CNTMDFIELD (0x0100u) /* Continuous transfer mode select */ +#define USB_CFG_CNTMDON (0x0100u) +#define USB_CFG_CNTMDOFF (0x0000u) +#define USB_SHTNAKFIELD (0x0080u) /* Transfer end NAK */ +#define USB_DIRFIELD (0x0010u) /* Transfer direction select */ +#define USB_DIR_H_OUT (0x0010u) /* HOST OUT */ +#define USB_DIR_P_IN (0x0010u) /* PERI IN */ +#define USB_DIR_H_IN (0x0000u) /* HOST IN */ +#define USB_DIR_P_OUT (0x0000u) /* PERI OUT */ +#define USB_BUF2FIFO (0x0010u) /* Buffer --> FIFO */ +#define USB_FIFO2BUF (0x0000u) /* FIFO --> buffer */ +#define USB_EPNUMFIELD (0x000Fu) /* Endpoint number select */ +#define USB_MAX_EP_NO (15u) /* EP0 EP1 ... EP15 */ + +#define USB_BUF_SIZE(x) ((uint16_t)(((x) / 64u) - 1u) << 10u) +#define USB_BUF_NUMB(x) (x) + +/* FIFO read / write result */ +#define USB_FIFOERROR (0x00ffu) /* FIFO not ready */ +#define USB_WRITEEND (0x0000u) /* End of write (but packet may not be outputting) */ +#define USB_WRITESHRT (0x0001u) /* End of write (send short packet) */ +#define USB_WRITING (0x0002u) /* Write continues */ +#define USB_READEND (0x0000u) /* End of read */ +#define USB_READSHRT (0x0001u) /* Insufficient (receive short packet) */ +#define USB_READING (0x0002u) /* Read continues */ +#define USB_READOVER (0x0003u) /* Buffer size over */ + +/* Transfer status Type */ +#define USB_CTRL_END (0u) +#define USB_DATA_NONE (1u) +#define USB_DATA_WAIT (2u) +#define USB_DATA_OK (3u) +#define USB_DATA_SHT (4u) +#define USB_DATA_OVR (5u) +#define USB_DATA_STALL (6u) +#define USB_DATA_ERR (7u) +#define USB_DATA_STOP (8u) +#define USB_DATA_TMO (9u) +#define USB_CTRL_READING (17u) +#define USB_CTRL_WRITING (18u) +#define USB_DATA_READING (19u) +#define USB_DATA_WRITING (20u) + + +/* System Configuration Control Register */ +#define USB_SCKE (0x0400u) /* b10: USB clock enable */ +#define USB_CNEN (0x0100u) /* b8: Single end receiver */ +#define USB_HSE (0x0080u) /* b7: Hi-speed enable */ +#define USB_DCFM (0x0040u) /* b6: Function select */ +#define USB_DRPD (0x0020u) /* b5: D+/D- pull down control */ +#define USB_DPRPU (0x0010u) /* b4: D+ pull up control */ +#define USB_DMRPU (0x0008u) /* b3: D- pull up control */ /* For low speed */ +#define USB_USBE (0x0001u) /* b0: USB module enable */ + +/* CPU Bus Wait Register */ +#define USB_BWAIT (0x000Fu) /* b3-0: Bus wait bit */ +#define USB_BWAIT_15 (0x000Fu) /* 15 wait (access cycle 17) */ +#define USB_BWAIT_14 (0x000Eu) /* 14 wait (access cycle 16) */ +#define USB_BWAIT_13 (0x000Du) /* 13 wait (access cycle 15) */ +#define USB_BWAIT_12 (0x000Cu) /* 12 wait (access cycle 14) */ +#define USB_BWAIT_11 (0x000Bu) /* 11 wait (access cycle 13) */ +#define USB_BWAIT_10 (0x000Au) /* 10 wait (access cycle 12) */ +#define USB_BWAIT_9 (0x0009u) /* 9 wait (access cycle 11) */ +#define USB_BWAIT_8 (0x0008u) /* 8 wait (access cycle 10) */ +#define USB_BWAIT_7 (0x0007u) /* 7 wait (access cycle 9) */ +#define USB_BWAIT_6 (0x0006u) /* 6 wait (access cycle 8) */ +#define USB_BWAIT_5 (0x0005u) /* 5 wait (access cycle 7) */ +#define USB_BWAIT_4 (0x0004u) /* 4 wait (access cycle 6) */ +#define USB_BWAIT_3 (0x0003u) /* 3 wait (access cycle 5) */ +#define USB_BWAIT_2 (0x0002u) /* 2 wait (access cycle 4) */ +#define USB_BWAIT_1 (0x0001u) /* 1 wait (access cycle 3) */ +#define USB_BWAIT_0 (0x0000u) /* 0 wait (access cycle 2) */ + +/* System Configuration Status Register */ +#define USB_OVCMON (0xC000u) /* b15-14: Over-current monitor */ +#define USB_OVCBIT (0x8000u) /* b15-14: Over-current bit */ +#define USB_HTACT (0x0040u) /* b6: USB Host Sequencer Status Monitor */ +#define USB_SOFEA (0x0020u) /* b5: SOF monitor */ +#define USB_IDMON (0x0004u) /* b2: ID-pin monitor */ +#define USB_LNST (0x0003u) /* b1-0: D+, D- line status */ +#define USB_SE1 (0x0003u) /* SE1 */ +#define USB_FS_KSTS (0x0002u) /* Full-Speed K State */ +#define USB_FS_JSTS (0x0001u) /* Full-Speed J State */ +#define USB_LS_JSTS (0x0002u) /* Low-Speed J State */ +#define USB_LS_KSTS (0x0001u) /* Low-Speed K State */ +#define USB_SE0 (0x0000u) /* SE0 */ + +/* PLL Status Register */ +#define USB_PLLLOCK (0x0001u) + +/* Device State Control Register */ +#define USB_HNPBTOA (0x0800u) /* b11: Host negotiation protocol (BtoA) */ +#define USB_EXICEN (0x0400u) /* b10: EXICEN output terminal control */ +#define USB_VBUSEN (0x0200u) /* b9: VBUS output terminal control */ +#define USB_WKUP (0x0100u) /* b8: Remote wakeup */ +#define USB_RWUPE (0x0080u) /* b7: Remote wakeup sense */ +#define USB_USBRST (0x0040u) /* b6: USB reset enable */ +#define USB_RESUME (0x0020u) /* b5: Resume enable */ +#define USB_UACT (0x0010u) /* b4: USB bus enable */ +#define USB_RHST (0x0007u) /* b2-0: Reset handshake status */ +#define USB_HSPROC (0x0004u) /* HS handshake processing */ +#define USB_HSMODE (0x0003u) /* Hi-Speed mode */ +#define USB_FSMODE (0x0002u) /* Full-Speed mode */ +#define USB_LSMODE (0x0001u) /* Low-Speed mode */ +#define USB_UNDECID (0x0000u) /* Undecided */ + +/* Test Mode Register */ +#define USB_UTST (0x000Fu) /* b3-0: Test mode */ +#define USB_H_TST_F_EN (0x000Du) /* HOST TEST FORCE ENABLE */ +#define USB_H_TST_PACKET (0x000Cu) /* HOST TEST Packet */ +#define USB_H_TST_SE0_NAK (0x000Bu) /* HOST TEST SE0 NAK */ +#define USB_H_TST_K (0x000Au) /* HOST TEST K */ +#define USB_H_TST_J (0x0009u) /* HOST TEST J */ +#define USB_H_TST_NORMAL (0x0000u) /* HOST Normal Mode */ +#define USB_P_TST_PACKET (0x0004u) /* PERI TEST Packet */ +#define USB_P_TST_SE0_NAK (0x0003u) /* PERI TEST SE0 NAK */ +#define USB_P_TST_K (0x0002u) /* PERI TEST K */ +#define USB_P_TST_J (0x0001u) /* PERI TEST J */ +#define USB_P_TST_NORMAL (0x0000u) /* PERI Normal Mode */ + +/* CFIFO/DxFIFO Port Select Register */ +#define USB_RCNT (0x8000u) /* b15: Read count mode */ +#define USB_REW (0x4000u) /* b14: Buffer rewind */ +#define USB_DCLRM (0x2000u) /* b13: Automatic buffer clear mode */ +#define USB_DREQE (0x1000u) /* b12: DREQ output enable */ +#define USB_MBW (0x0C00u) /* b10: Maximum bit width for FIFO access */ +#define USB_MBW_32 (0x0800u) /* FIFO access : 32bit */ +#define USB_MBW_16 (0x0400u) /* FIFO access : 16bit */ +#define USB_MBW_8 (0x0000u) /* FIFO access : 8bit */ +#define USB_BIGEND (0x0100u) /* b8: Big endian mode */ +#define USB_FIFO_BIG (0x0100u) /* Big endian */ +#define USB_FIFO_LITTLE (0x0000u) /* Little endian */ +#define USB_ISEL (0x0020u) /* b5: DCP FIFO port direction select */ +#define USB_ISEL_WRITE (0x0020u) /* write */ +#define USB_ISEL_READ (0x0000u) /* read */ +#define USB_CURPIPE (0x000Fu) /* b2-0: PIPE select */ + +/* CFIFO/DxFIFO Port Control Register */ +#define USB_BVAL (0x8000u) /* b15: Buffer valid flag */ +#define USB_BCLR (0x4000u) /* b14: Buffer clear */ +#define USB_FRDY (0x2000u) /* b13: FIFO ready */ +#define USB_DTLN (0x0FFFu) /* b11-0: FIFO data length */ + +/* Interrupt Enable Register 0 */ +#define USB_VBSE (0x8000u) /* b15: VBUS interrupt */ +#define USB_RSME (0x4000u) /* b14: Resume interrupt */ +#define USB_SOFE (0x2000u) /* b13: Frame update interrupt */ +#define USB_DVSE (0x1000u) /* b12: Device state transition interrupt */ +#define USB_CTRE (0x0800u) /* b11: Control transfer stage transition interrupt */ +#define USB_BEMPE (0x0400u) /* b10: Buffer empty interrupt */ +#define USB_NRDYE (0x0200u) /* b9: Buffer notready interrupt */ +#define USB_BRDYE (0x0100u) /* b8: Buffer ready interrupt */ + +/* Interrupt Enable Register 1 */ +#define USB_OVRCRE (0x8000u) /* b15: Over-current interrupt */ +#define USB_BCHGE (0x4000u) /* b14: USB bus change interrupt */ +#define USB_DTCHE (0x1000u) /* b12: Detach sense interrupt */ +#define USB_ATTCHE (0x0800u) /* b11: Attach sense interrupt */ +#define USB_L1RSMENDE (0x0200u) /* b9: L1 resume completion interrupt */ +#define USB_LPMENDE (0x0100u) /* b8: LPM transaction completion interrupt */ +#define USB_EOFERRE (0x0040u) /* b6: EOF error interrupt */ +#define USB_SIGNE (0x0020u) /* b5: SETUP IGNORE interrupt */ +#define USB_SACKE (0x0010u) /* b4: SETUP ACK interrupt */ +#define USB_PDDETINTE (0x0001u) /* b0: PDDET detection interrupt */ + +/* BRDY Interrupt Enable/Status Register */ +#define USB_BRDY9 (0x0200u) /* b9: PIPE9 */ +#define USB_BRDY8 (0x0100u) /* b8: PIPE8 */ +#define USB_BRDY7 (0x0080u) /* b7: PIPE7 */ +#define USB_BRDY6 (0x0040u) /* b6: PIPE6 */ +#define USB_BRDY5 (0x0020u) /* b5: PIPE5 */ +#define USB_BRDY4 (0x0010u) /* b4: PIPE4 */ +#define USB_BRDY3 (0x0008u) /* b3: PIPE3 */ +#define USB_BRDY2 (0x0004u) /* b2: PIPE2 */ +#define USB_BRDY1 (0x0002u) /* b1: PIPE1 */ +#define USB_BRDY0 (0x0001u) /* b1: PIPE0 */ + +/* NRDY Interrupt Enable/Status Register */ +#define USB_NRDY9 (0x0200u) /* b9: PIPE9 */ +#define USB_NRDY8 (0x0100u) /* b8: PIPE8 */ +#define USB_NRDY7 (0x0080u) /* b7: PIPE7 */ +#define USB_NRDY6 (0x0040u) /* b6: PIPE6 */ +#define USB_NRDY5 (0x0020u) /* b5: PIPE5 */ +#define USB_NRDY4 (0x0010u) /* b4: PIPE4 */ +#define USB_NRDY3 (0x0008u) /* b3: PIPE3 */ +#define USB_NRDY2 (0x0004u) /* b2: PIPE2 */ +#define USB_NRDY1 (0x0002u) /* b1: PIPE1 */ +#define USB_NRDY0 (0x0001u) /* b1: PIPE0 */ + +/* BEMP Interrupt Enable/Status Register */ +#define USB_BEMP9 (0x0200u) /* b9: PIPE9 */ +#define USB_BEMP8 (0x0100u) /* b8: PIPE8 */ +#define USB_BEMP7 (0x0080u) /* b7: PIPE7 */ +#define USB_BEMP6 (0x0040u) /* b6: PIPE6 */ +#define USB_BEMP5 (0x0020u) /* b5: PIPE5 */ +#define USB_BEMP4 (0x0010u) /* b4: PIPE4 */ +#define USB_BEMP3 (0x0008u) /* b3: PIPE3 */ +#define USB_BEMP2 (0x0004u) /* b2: PIPE2 */ +#define USB_BEMP1 (0x0002u) /* b1: PIPE1 */ +#define USB_BEMP0 (0x0001u) /* b0: PIPE0 */ + +/* SOF Pin Configuration Register */ +#define USB_TRNENSEL (0x0100u) /* b8: Select transaction enable period */ +#define USB_BRDYM (0x0040u) /* b6: BRDY clear timing */ +#define USB_INTL (0x0020u) /* b5: Interrupt sense select */ +#define USB_EDGESTS (0x0010u) /* b4: */ +#define USB_SOFMODE (0x000Cu) /* b3-2: SOF pin select */ +#define USB_SOF_125US (0x0008u) /* SOF 125us Frame Signal */ +#define USB_SOF_1MS (0x0004u) /* SOF 1ms Frame Signal */ +#define USB_SOF_DISABLE (0x0000u) /* SOF Disable */ + +#define USB_HSEB (0x8000u) /* b15: CL only mode bit */ + +#define USB_REPSTART (0x0800u) /* b11: Terminator adjustment forcible starting bit */ +#define USB_REPSEL (0x0300u) /* b9-8: Terminator adjustment cycle setting */ +#define USB_REPSEL_128 (0x0300u) /* 128 sec */ +#define USB_REPSEL_64 (0x0200u) /* 64 sec */ +#define USB_REPSEL_16 (0x0100u) /* 16 sec */ +#define USB_REPSEL_NONE (0x0000u) /* - */ +#define USB_CLKSEL (0x0030u) /* b5-4: System clock setting */ +#define USB_CLKSEL_24 (0x0030u) /* 24MHz */ +#define USB_CLKSEL_20 (0x0020u) /* 20MHz */ +#define USB_CLKSEL_48 (0x0010u) /* 48MHz */ +#define USB_CLKSEL_30 (0x0000u) /* 30MHz */ +#define USB_CDPEN (0x0008u) /* b3: Charging downstream port enable */ +#define USB_PLLRESET (0x0002u) /* b1: PLL reset control */ +#define USB_DIRPD (0x0001u) /* b0: Power down control */ + +/* Interrupt Status Register 0 */ +#define USB_VBINT (0x8000u) /* b15: VBUS interrupt */ +#define USB_RESM (0x4000u) /* b14: Resume interrupt */ +#define USB_SOFR (0x2000u) /* b13: SOF update interrupt */ +#define USB_DVST (0x1000u) /* b12: Device state transition interrupt */ +#define USB_CTRT (0x0800u) /* b11: Control transfer stage transition interrupt */ +#define USB_BEMP (0x0400u) /* b10: Buffer empty interrupt */ +#define USB_NRDY (0x0200u) /* b9: Buffer notready interrupt */ +#define USB_BRDY (0x0100u) /* b8: Buffer ready interrupt */ +#define USB_VBSTS (0x0080u) /* b7: VBUS input port */ +#define USB_DVSQ (0x0070u) /* b6-4: Device state */ +#define USB_DS_SPD_CNFG (0x0070u) /* Suspend Configured */ +#define USB_DS_SPD_ADDR (0x0060u) /* Suspend Address */ +#define USB_DS_SPD_DFLT (0x0050u) /* Suspend Default */ +#define USB_DS_SPD_POWR (0x0040u) /* Suspend Powered */ +#define USB_DS_SUSP (0x0040u) /* Suspend */ +#define USB_DS_CNFG (0x0030u) /* Configured */ +#define USB_DS_ADDS (0x0020u) /* Address */ +#define USB_DS_DFLT (0x0010u) /* Default */ +#define USB_DS_POWR (0x0000u) /* Powered */ +#define USB_DVSQS (0x0030u) /* b5-4: Device state */ +#define USB_VALID (0x0008u) /* b3: Setup packet detect flag */ +#define USB_CTSQ (0x0007u) /* b2-0: Control transfer stage */ +#define USB_CS_SQER (0x0006u) /* Sequence error */ +#define USB_CS_WRND (0x0005u) /* Ctrl write nodata status stage */ +#define USB_CS_WRSS (0x0004u) /* Ctrl write status stage */ +#define USB_CS_WRDS (0x0003u) /* Ctrl write data stage */ +#define USB_CS_RDSS (0x0002u) /* Ctrl read status stage */ +#define USB_CS_RDDS (0x0001u) /* Ctrl read data stage */ +#define USB_CS_IDST (0x0000u) /* Idle or setup stage */ + +/* Interrupt Status Register 1 */ +#define USB_OVRCR (0x8000u) /* b15: Over-current interrupt */ +#define USB_BCHG (0x4000u) /* b14: USB bus change interrupt */ +#define USB_DTCH (0x1000u) /* b12: Detach sense interrupt */ +#define USB_ATTCH (0x0800u) /* b11: Attach sense interrupt */ +#define USB_L1RSMEND (0x0200u) /* b9: L1 resume completion interrupt */ +#define USB_LPMEND (0x0100u) /* b8: LPM transaction completion interrupt */ +#define USB_EOFERR (0x0040u) /* b6: EOF-error interrupt */ +#define USB_SIGN (0x0020u) /* b5: Setup ignore interrupt */ +#define USB_SACK (0x0010u) /* b4: Setup ack interrupt */ +#define USB_PDDETINT (0x0001u) /* b0: PDDET detection interrupt */ + +/* Frame Number Register */ +#define USB_OVRN (0x8000u) /* b15: Overrun error */ +#define USB_CRCE (0x4000u) /* b14: Received data error */ +#define USB_FRNM (0x07FFu) /* b10-0: Frame number */ + +/* Device State Change Register */ /* For USB0 */ +#define USB_DVCHG (0x8000u) /* b15: Device state change */ + +/* Micro Frame Number Register */ /* For USBHS */ +#define USB_UFRNM (0x0007u) /* b2-0: Micro frame number */ + +/* USB Address / Low Power Status Recovery Register */ +#define USB_STSRECOV (0x0F00u) /* b11-8: Status Recovery */ +#define USB_USBADDR_MASK (0x007Fu) /* b6-0: USB address */ + +/* USB Request Type Register */ +#define USB_BMREQUESTTYPE (0x00FFu) /* b7-0: USB_BMREQUESTTYPE */ +#define USB_BMREQUESTTYPEDIR (0x0080u) /* b7 : Data transfer direction */ +#define USB_BMREQUESTTYPETYPE (0x0060u) /* b6-5: Type */ +#define USB_BMREQUESTTYPERECIP (0x001Fu) /* b4-0: Recipient */ + +/* USB Request Value Register */ +#define USB_WVALUE (0xFFFFu) /* b15-0: wValue */ +#define USB_DT_TYPE (0xFF00u) +#define USB_GET_DT_TYPE(v) (((v) & USB_DT_TYPE) >> 8) +#define USB_DT_INDEX (0x00FFu) +#define USB_CONF_NUM (0x00FFu) +#define USB_ALT_SET (0x00FFu) + +/* USB Request Index Register */ +#define USB_WINDEX (0xFFFFu) /* b15-0: wIndex */ +#define USB_TEST_SELECT (0xFF00u) /* b15-b8: Test Mode Selectors */ +#define USB_TEST_J (0x0100u) /* Test_J */ +#define USB_TEST_K (0x0200u) /* Test_K */ +#define USB_TEST_SE0_NAK (0x0300u) /* Test_SE0_NAK */ +#define USB_TEST_PACKET (0x0400u) /* Test_Packet */ +#define USB_TEST_FORCE_ENABLE (0x0500u) /* Test_Force_Enable */ +#define USB_TEST_STSelectors (0x0600u) /* Standard test selectors */ +#define USB_TEST_RESERVED (0x4000u) /* Reserved */ +#define USB_TEST_VSTMODES (0xC000u) /* VendorSpecific test modes */ +#define USB_EP_DIR (0x0080u) /* b7: Endpoint Direction */ +#define USB_EP_DIR_IN (0x0080u) +#define USB_EP_DIR_OUT (0x0000u) + +/* USB Request Length Register */ +#define USB_WLENGTH (0xFFFFu) /* b15-0: wLength */ + +#define USB_TYPE (0xC000u) /* b15-14: Transfer type */ +#define USB_BFRE (0x0400u) /* b10: Buffer ready interrupt mode select */ + +#define USB_DEVSEL (0xF000u) /* b15-14: Device address select */ +#define USB_MAXP (0x007Fu) /* b6-0: Maxpacket size of default control pipe */ +#define USB_MXPS (0x07FFu) /* b10-0: Maxpacket size */ + +#define USB_BSTS (0x8000u) /* b15: Buffer status */ +#define USB_SUREQ (0x4000u) /* b14: Send USB request */ +#define USB_INBUFM (0x4000u) /* b14: IN buffer monitor (Only for PIPE1 to 5) */ +#define USB_CSCLR (0x2000u) /* b13: c-split status clear */ +#define USB_CSSTS (0x1000u) /* b12: c-split status */ +#define USB_SUREQCLR (0x0800u) /* b11: stop setup request */ +#define USB_ATREPM (0x0400u) /* b10: Auto repeat mode */ +#define USB_ACLRM (0x0200u) /* b9: buffer auto clear mode */ +#define USB_SQCLR (0x0100u) /* b8: Sequence bit clear */ +#define USB_SQSET (0x0080u) /* b7: Sequence bit set */ +#define USB_SQMON (0x0040u) /* b6: Sequence bit monitor */ +#define USB_PBUSY (0x0020u) /* b5: pipe busy */ +#define USB_PINGE (0x0010u) /* b4: ping enable */ +#define USB_CCPL (0x0004u) /* b2: Enable control transfer complete */ +#define USB_PID (0x0003u) /* b1-0: Response PID */ +#define USB_PID_STALL2 (0x0003u) /* STALL2 */ +#define USB_PID_STALL (0x0002u) /* STALL */ +#define USB_PID_BUF (0x0001u) /* BUF */ +#define USB_PID_NAK (0x0000u) /* NAK */ + +#define USB_PIPENM (0x0007u) /* b2-0: Pipe select */ + +#define USB_BUFSIZE (0x7C00u) /* b14-10: Pipe buffer size */ +#define USB_BUFNMB (0x007Fu) /* b6-0: Pipe buffer number */ +#define USB_PIPE0BUF (256u) +#define USB_PIPEXBUF (64u) + +#define USB_TRENB (0x0200u) /* b9: Transaction count enable */ +#define USB_TRCLR (0x0100u) /* b8: Transaction count clear */ +#define USB_TRNCNT (0xFFFFu) /* b15-0: Transaction counter */ + +#define USB_UPPHUB (0x7800u) /* b14-11: HUB register */ +#define USB_HUBPORT (0x0700u) /* b10-8: HUB port */ +#define USB_USBSPD (0x00C0u) /* b7-6: Device speed */ + +/********* USB0 Only ******************************************************************************/ + +/* PHY Crosspoint Adjustment Register */ +/* PHYSLEW */ +#define USB_SLEWF01 (0x0008u) /* b3: Cross point adjustment bit 01 */ +#define USB_SLEWF00 (0x0004u) /* b2: Cross point adjustment bit 00 */ +#define USB_SLEWR01 (0x0002u) /* b1: Cross point adjustment bit 01 */ +#define USB_SLEWR00 (0x0001u) /* b0: Cross point adjustment bit 00 */ + +/* Deep Standby USB Transceiver Control/Terminal Monitor Register */ +/* DPUSR0R */ +#define USB_DVBSTS0 (0x00800000u) /* b23: USB0 VBUS input */ +#define USB_DOVCB0 (0x00200000u) /* b21: USB0 OVRCURB input */ +#define USB_DOVCA0 (0x00100000u) /* b20: USB0 OVRCURA input */ +#define USB_DM0 (0x00200000u) /* b17: USB0 D- input */ +#define USB_DP0 (0x00100000u) /* b16: USB0 D+ input */ +#define USB_FIXPHY0 (0x00000010u) /* b4: USB0 transceiver output fixed bit */ +#define USB_DRPD0 (0x00000008u) /* b3: D+/D- pull down resistor control bit */ +#define USB_RPUE0 (0x00000002u) /* b1: DP pull up resistor control bit */ +#define USB_SRPC0 (0x00000001u) /* b0: USB0 single end receiver control bit */ + +/* Deep Standby USB Suspend/Resume Interrupt Register */ +/* DPUSR1R */ +#define USB_DVBINT0 (0x00800000u) /* b23: USB0 VBUS monitor bit */ +#define USB_DOVRCRB0 (0x00200000u) /* b21: USB0 OVRCURB DM monitor bit */ +#define USB_DOVRCRA0 (0x00100000u) /* b20: USB0 OVRCURA DM monitor bit */ +#define USB_DMINT0 (0x00020000u) /* b17: USB0 DM monitor bit */ +#define USB_DPINT0 (0x00010000u) /* b16: USB0 DP monitor bit */ +#define USB_DVBSE0 (0x00000080u) /* b7: USB0 VBUS interrupt enable */ +#define USB_DOVRCRBE0 (0x00000020u) /* b5: USB0 OVRCURB interrupt enable */ +#define USB_DOVRCRAE0 (0x00000010u) /* b4: USB0 OVRCURA interrupt enable */ +#define USB_DMINTE0 (0x00000002u) /* b1: USB0 DM interrupt enable */ +#define USB_DPINTE0 (0x00000001u) /* b0: USB0 DP interrupt enable */ + +/**************************************************************************************************/ + +/********* USBHS Only *****************************************************************************/ + +/* Low Power Control Register */ +/* LPCTRL */ +#define USB_HWUPM (0x0080u) /* b7: */ + +/* Low Power Status Register */ +/* LPSTS */ +#define USB_SUSPENDM (0x4000u) /* b14: UTMI SuspendM control */ + +/* PHY Single Access Read Data Register */ +/* SPRDAT */ +#define USB_PHYRDAT (0x00FFu) /* PHY read data bit */ + +/* Battery Charging Control Register */ +/* BCCTRL */ +#define USB_PDDETSTS (0x0200u) /* b9: PDDET status */ +#define USB_CHGDETSTS (0x0100u) /* b8: CHGDET status */ +#define USB_DCPMODE (0x0020u) /* b5: DCP mode control */ +#define USB_VDMSRCE (0x0010u) /* b4: VDMSRC control */ +#define USB_IDPSINKE (0x0008u) /* b3: IDPSINK control */ +#define USB_VDPSRCE (0x0004u) /* b2: VDPSRC control */ +#define USB_IDMSINKE (0x0002u) /* b1: IDMSINK control */ +#define USB_IDPSRCE (0x0001u) /* b0: IDPSRC control */ + +/* Function L1 Control Register 1 */ +/* PL1CTRL1 */ +#define USB_L1EXTMD (0x4000u) /* b14: PHY control mode */ +#define USB_DVSQEX (0x0080u) /* b7: DVSQ extension bit */ +#define USB_DVSQ (0x0070u) /* b6-4: Mirror of DVSQ */ +#define USB_L1NEGOMD (0x0008u) /* b3: L1 response negotiation control */ +#define USB_L1RESPMD (0x0006u) /* b2-1: L1 response mode */ +#define USB_L1RESPEN (0x0001u) /* b0: L1 response enable */ + +/* Function L1 Control Register 2 */ +/* PL1CTRL2 */ +#define USB_HSRDMON (0x0F00u) /* b12: RWE monitor bit */ +#define USB_RWEMON (0x1000u) /* b11-8: HIRD monitor bit */ + +/* Host L1 Control Register 1 */ +/* HL1CTRL1 */ +#define USB_L1STATUS (0x0006u) /* b2-1: L1 request completion state */ +#define USB_L1REQ (0x0001u) /* b0: L1 changes request bit + */ + +/* Host L1 Control Register 2 */ +/* HL1CTRL2 */ +#define USB_BESL (0x8000u) /* b15: BESL & Alternate HIRD bit */ +#define USB_L1RWE (0x1000u) /* b12: L1 RemoteWake enable for LPM tokens */ +#define USB_HSRD (0x0F00u) /* b11-8: HIRD bit for LPM tokens */ +#define USB_L1ADDR (0x000Fu) /* b3-0: DeviceAddress for LPM tokens */ + +/* PHY Timing Register 1 */ +/* PHYTRIM1 */ +#define USB_IMPOFFSET (0x7000u) /* b14-12: Terminator adjustment */ +#define USB_HSIUP (0x0F00u) /* b11-8: Output level setup of HS */ +#define USB_PCOMPENB (0x0080u) /* b7: PVDD starting detection setup */ +#define USB_DFALL (0x000Cu) /* b3-2: FS/LS falling output waveform compensation function setting */ +#define USB_DRISE (0x0003u) /* b1-0: FS/LS standup output waveform compensation function setting */ + +/* PHY Timing Register 2 */ +/* PHYTRIM2 */ +#define USB_DIS (0x7000u) /* b14-12: Disconnect disregard level setup */ +#define USB_PDR (0x0300u) /* b9-8: HS output compensation function setting */ +#define USB_HSRXENMODE (0x0080u) /* b7: HS reception permission control mode setup */ +#define USB_SQU (0x000Fu) /* b3-0: Squelch disregard level setup */ + +/* Deep Standby USB Register */ +/* DPUSR0R */ +#define USB_DVBSTSHM (0x00800000u) /* b23: VBUS input */ +#define USB_DOVCBHM (0x00200000u) /* b21: OVRCURB input */ +#define USB_DOVCAHM (0x00100000u) /* b20: OVRCURA input */ + +/* DPUSR1R */ +#define USB_DVBSTSH (0x00800000u) /* b23: Interruption factor return display of VBUS */ +#define USB_DOVCBH (0x00200000u) /* b21: Interruption factor return display of OVRCURB */ +#define USB_DOVCAH (0x00100000u) /* b20: Interruption factor return display of OVRCURA */ +#define USB_DVBSTSHE (0x00000080u) /* b7 : VBUS interrupt enable */ +#define USB_DOVCBHE (0x00000020u) /* b5 : OVRCURB interrupt enable */ +#define USB_DOVCAHE (0x00000010u) /* b4 : OVRCURA interrupt enable */ + +/**************************************************************************************************/ + +/* DMAx Pin Configuration Register */ +#define USB_DREQA (0x4000u) /* b14: Dreq active select */ +#define USB_BURST (0x2000u) /* b13: Burst mode */ +#define USB_DACKA (0x0400u) /* b10: Dack active select */ +#define USB_DFORM (0x0380u) /* b9-7: DMA mode select */ +#define USB_CPU_ADR_RD_WR (0x0000u) /* Address + RD/WR mode (CPU bus) */ +#define USB_CPU_DACK_RD_WR (0x0100u) /* DACK + RD/WR (CPU bus) */ +#define USB_CPU_DACK_ONLY (0x0180u) /* DACK only (CPU bus) */ +#define USB_SPLIT_DACK_ONLY (0x0200u) /* DACK only (SPLIT bus) */ +#define USB_DENDA (0x0040u) /* b6: Dend active select */ +#define USB_PKTM (0x0020u) /* b5: Packet mode */ +#define USB_DENDE (0x0010u) /* b4: Dend enable */ +#define USB_OBUS (0x0004u) /* b2: OUTbus mode */ + +/* USB IO Register Reserved bit mask */ +#define INTSTS1_MASK (0xD870u) /* INTSTS1 Reserved bit mask */ +#define BRDYSTS_MASK (0x03FFu) /* BRDYSTS Reserved bit mask */ +#define NRDYSTS_MASK (0x03FFu) /* NRDYSTS Reserved bit mask */ +#define BEMPSTS_MASK (0x03FFu) /* BEMPSTS Reserved bit mask */ + + + +/* USB Request Type Register */ +#define USB_BREQUEST (0xFF00u) /* b15-8 */ + +/* USB Standard request */ +#define USB_GET_STATUS (0x0000u) +#define USB_CLEAR_FEATURE (0x0100u) +#define USB_REQRESERVED (0x0200u) +#define USB_SET_FEATURE (0x0300u) +#define USB_REQRESERVED1 (0x0400u) +#define USB_SET_ADDRESS (0x0500u) +#define USB_GET_DESCRIPTOR (0x0600u) +#define USB_SET_DESCRIPTOR (0x0700u) +#define USB_GET_CONFIGURATION (0x0800u) +#define USB_SET_CONFIGURATION (0x0900u) +#define USB_GET_INTERFACE (0x0A00u) +#define USB_SET_INTERFACE (0x0B00u) +#define USB_SYNCH_FRAME (0x0C00u) + +/* USB_BMREQUESTTYPEDIR 0x0080u(b7) */ +#define USB_HOST_TO_DEV (0x0000u) +#define USB_DEV_TO_HOST (0x0080u) + +/* USB_BMREQUESTTYPETYPE 0x0060u(b6-5) */ +#define USB_STANDARD (0x0000u) +#define USB_CLASS (0x0020u) +#define USB_VENDOR (0x0040u) + +/* USB_BMREQUESTTYPERECIP 0x001Fu(b4-0) */ +#define USB_DEVICE (0x0000u) +#define USB_INTERFACE (0x0001u) +#define USB_ENDPOINT (0x0002u) +#define USB_OTHER (0x0003u) + +#define USB_NULL (0x0u) + +#define USB_IP0 (0) /* USB0 module */ +#define USB_IP1 (1) /* USB1 module */ + +/* USB pipe number */ +#define USB_PIPE0 (0x0u) +#define USB_PIPE1 (0x1u) +#define USB_PIPE2 (0x2u) +#define USB_PIPE3 (0x3u) +#define USB_PIPE4 (0x4u) +#define USB_PIPE5 (0x5u) +#define USB_PIPE6 (0x6u) +#define USB_PIPE7 (0x7u) +#define USB_PIPE8 (0x8u) +#define USB_PIPE9 (0x9u) +#define USB_PIPE10 (0xAu) +#define USB_PIPE11 (0xBu) +#define USB_PIPE12 (0xCu) +#define USB_PIPE13 (0xDu) +#define USB_PIPE14 (0xEu) +#define USB_PIPE15 (0xFu) + +#define USB_EP0 (0x0u) +#define USB_EP1 (0x1u) +#define USB_EP2 (0x2u) +#define USB_EP3 (0x3u) +#define USB_EP4 (0x4u) +#define USB_EP5 (0x5u) +#define USB_EP6 (0x6u) +#define USB_EP7 (0x7u) +#define USB_EP8 (0x8u) +#define USB_EP9 (0x9u) +#define USB_EP10 (0xAu) +#define USB_EP11 (0xBu) +#define USB_EP12 (0xCu) +#define USB_EP13 (0xDu) +#define USB_EP14 (0xEu) +#define USB_EP15 (0xFu) + +/* Descriptor type Define */ +#define USB_DT_DEVICE (0x01u) /* Configuration Descriptor */ +#define USB_DT_CONFIGURATION (0x02u) /* Configuration Descriptor */ +#define USB_DT_STRING (0x03u) /* Configuration Descriptor */ +#define USB_DT_INTERFACE (0x04u) /* Interface Descriptor */ +#define USB_DT_ENDPOINT (0x05u) /* Endpoint Descriptor */ +#define USB_DT_DEVICE_QUALIFIER (0x06u) /* Device Qualifier Descriptor */ +#define USB_DT_OTHER_SPEED_CONF (0x07u) /* Other Speed Configuration Descriptor */ +#define USB_DT_INTERFACE_POWER (0x08u) /* Interface Power Descriptor */ +#define USB_DT_OTGDESCRIPTOR (0x09u) /* OTG Descriptor */ +#define USB_DT_HUBDESCRIPTOR (0x29u) /* HUB descriptor */ + +/* Interface class Define */ +#define USB_IFCLS_NOT (0x00u) /* Un corresponding Class */ +#define USB_IFCLS_AUD (0x01u) /* Audio Class */ +#define USB_IFCLS_CDC (0x02u) /* CDC Class */ +#define USB_IFCLS_CDCC (0x02u) /* CDC-Control Class */ +#define USB_IFCLS_HID (0x03u) /* HID Class */ +#define USB_IFCLS_PHY (0x05u) /* Physical Class */ +#define USB_IFCLS_IMG (0x06u) /* Image Class */ +#define USB_IFCLS_PRN (0x07u) /* Printer Class */ +#define USB_IFCLS_MAS (0x08u) /* Mass Storage Class */ +#define USB_IFCLS_HUB (0x09u) /* HUB Class */ +#define USB_IFCLS_CDCD (0x0Au) /* CDC-Data Class */ +#define USB_IFCLS_CHIP (0x0Bu) /* Chip/Smart Card Class */ +#define USB_IFCLS_CNT (0x0Cu) /* Content-Security Class */ +#define USB_IFCLS_VID (0x0Du) /* Video Class */ +#define USB_IFCLS_DIAG (0xDCu) /* Diagnostic Device */ +#define USB_IFCLS_WIRE (0xE0u) /* Wireless Controller */ +#define USB_IFCLS_APL (0xFEu) /* Application-Specific */ +#define USB_IFCLS_VEN (0xFFu) /* Vendor-Specific Class */ + +/* Endpoint Descriptor Define */ +#define USB_EP_IN (0x80u) /* In Endpoint */ +#define USB_EP_OUT (0x00u) /* Out Endpoint */ +#define USB_EP_ISO (0x01u) /* Isochronous Transfer */ +#define USB_EP_BULK (0x02u) /* Bulk Transfer */ +#define USB_EP_INT (0x03u) /* Interrupt Transfer */ + +/* Configuration descriptor bit define */ +#define USB_CF_RESERVED (0x80u) /* Reserved(set to 1) */ +#define USB_CF_SELFP (0x40u) /* Self Powered */ +#define USB_CF_BUSP (0x00u) /* Bus Powered */ +#define USB_CF_RWUPON (0x20u) /* Remote Wake up ON */ +#define USB_CF_RWUPOFF (0x00u) /* Remote Wake up OFF */ + +/* Descriptor length Define */ +#define USB_DD_BLENGTH (18u) /* Device Descriptor Length */ +#define USB_CD_BLENGTH (9u) /* Configuration Descriptor Length */ +#define USB_ID_BLENGTH (9u) /* Interface Descriptor Length */ +#define USB_ED_BLENGTH (7u) /* Endpoint Descriptor Length */ + +#define USB_BUFSIZE_BIT (10u) + +/* other */ +#define USB_FUNCTION_CFIFO_USE (0x0000u) +#define USB_FUNCTION_D0FIFO_USE (0x1000u) +#define USB_FUNCTION_D1FIFO_USE (0x2000u) + + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/analogin_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/analogin_api.c new file mode 100644 index 0000000..543f14d --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/analogin_api.c @@ -0,0 +1,105 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_ANALOGIN +#include "mbed_assert.h" +#include "analogin_api.h" + +#include "cmsis.h" +#include "PeripheralPins.h" + +#include "iodefine.h" + +#define ANALOGIN_MEDIAN_FILTER 0 + +static volatile uint16_t *ADDR[] = { + &ADC.ADDR0.WORD, + &ADC.ADDR1.WORD, + &ADC.ADDR2.WORD, + &ADC.ADDR3.WORD, + &ADC.ADDR4.WORD, + &ADC.ADDR5.WORD, + &ADC.ADDR6.WORD, + &ADC.ADDR7.WORD, +}; + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + CPG.STBCR5.BIT.MSTP57 = 0; + + ADC.ADCSR.BIT.ADCS = 0x0; /* single scan mode */ + + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + + ADC.ADANSA0.WORD = (1 << obj->adc); + ADC.ADCSR.BIT.ADST = 0x1; + + // Wait end of conversion + while (ADC.ADCSR.BIT.ADST != 0) { + ; + + } + return *(ADDR[obj->adc]) & 0x0FFF; // 12 bits range +} + +#if ANALOGIN_MEDIAN_FILTER +static inline void order(uint32_t *a, uint32_t *b) { + if (*a > *b) { + uint32_t t = *a; + *a = *b; + *b = t; + } +} +#endif + +static inline uint32_t adc_read_u32(analogin_t *obj) { + uint32_t value; +#if ANALOGIN_MEDIAN_FILTER + uint32_t v1 = adc_read(obj); + uint32_t v2 = adc_read(obj); + uint32_t v3 = adc_read(obj); + order(&v1, &v2); + order(&v2, &v3); + order(&v1, &v2); + value = v2; +#else + value = adc_read(obj); +#endif + return value; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion +} + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return (float)value * (1.0f / (float)0x0FFF); // 12 bits range +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/RZ_A2_Init.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/RZ_A2_Init.h new file mode 100644 index 0000000..89aaaea --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/RZ_A2_Init.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2012-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/**************************************************************************//** +* @file RZ_A2_Init.h +* $Rev: 531 $ +* $Date:: 2013-04-16 13:07:35 +0900#$ +* @brief RZ_A2 Initialize +******************************************************************************/ + +#ifndef RZ_A2_INIT_H +#define RZ_A2_INIT_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include +#include "iodefine.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +void RZ_A2_SetSramWriteEnable(void); +void RZ_A2_InitClock(void); +int RZ_A2_IsClockMode0(void); +void RZ_A2_InitBus(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* RZ_A2_INIT_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/USBSerial_FileHandle.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/USBSerial_FileHandle.h new file mode 100644 index 0000000..cb4a67b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/USBSerial_FileHandle.h @@ -0,0 +1,191 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019-2020 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_USBSERIAL_FILEHANDLE_H +#define MBED_USBSERIAL_FILEHANDLE_H + +#include "platform/platform.h" +#include "platform/FileHandle.h" +#include "platform/NonCopyable.h" +#include "USBCDC.h" + +namespace mbed { + +class USBSerial_FileHandle: public USBCDC, public FileHandle, private NonCopyable { + +public: + + /** Constructor + * + * Construct this object optionally connecting and blocking until it is ready. + * + * @note Do not use this constructor in derived classes. + * + * @param connect_blocking true to perform a blocking connect, false to start in a disconnected state + * @param vendor_id Your vendor_id (default: 0x1f00) + * @param product_id Your product_id (default: 0x2012) + * @param product_release Your product_release (default: 0x0001) + */ + USBSerial_FileHandle(bool connect_blocking=true, uint16_t vendor_id=0x1f00, uint16_t product_id=0x2012, uint16_t product_release=0x0001) + : USBCDC(connect_blocking, vendor_id, product_id, product_release) {} + + /** Read the contents of a file into a buffer + * + * Devices acting as FileHandles should follow POSIX semantics: + * + * * if no data is available, and nonblocking set, return -EAGAIN + * * if no data is available, and blocking set, wait until some data is available + * * If any data is available, call returns immediately + * + * @param buffer The buffer to read in to + * @param size The number of bytes to read + * @return The number of bytes read, 0 at end of file, negative error on failure + */ + virtual ssize_t read(void *buffer, size_t size) { + uint32_t data_read = 0; + USBCDC::receive((uint8_t *)buffer, size, &data_read); + return (ssize_t)data_read; + } + + /** Write the contents of a buffer to a file + * + * Devices acting as FileHandles should follow POSIX semantics: + * + * * if blocking, block until all data is written + * * if no data can be written, and nonblocking set, return -EAGAIN + * * if some data can be written, and nonblocking set, write partial + * + * @param buffer The buffer to write from + * @param size The number of bytes to write + * @return The number of bytes written, negative error on failure + */ + virtual ssize_t write(const void *buffer, size_t size) { + USBCDC::send((uint8_t *)buffer, size); + return size; + } + + /** Move the file position to a given offset from from a given location + * + * @param offset The offset from whence to move to + * @param whence The start of where to seek + * SEEK_SET to start from beginning of file, + * SEEK_CUR to start from current position in file, + * SEEK_END to start from end of file + * @return The new offset of the file, negative error code on failure + */ + virtual off_t seek(off_t offset, int whence = SEEK_SET) { + return -ESPIPE; + } + + /** Close a file + * + * @return 0 on success, negative error code on failure + */ + virtual int close() { + return 0; + } + + /** Check if the file in an interactive terminal device + * + * @return True if the file is a terminal + * @return False if the file is not a terminal + * @return Negative error code on failure + */ + virtual int isatty() { + return true; + } + + /** Get the size of the file + * + * @return Size of the file in bytes + */ + virtual off_t size() { + return -EINVAL; + } + + /** Check for poll event flags + * You can use or ignore the input parameter. You can return all events + * or check just the events listed in events. + * Call is nonblocking - returns instantaneous state of events. + * Whenever an event occurs, the derived class should call the sigio() callback). + * + * @param events bitmask of poll events we're interested in - POLLIN/POLLOUT etc. + * + * @returns bitmask of poll events that have occurred. + */ + virtual short poll(short events) { + short revents = 0; + + USBCDC::lock(); + uint8_t size = 0; + if (!_rx_in_progress) { + size = _rx_size > 0xFF ? 0xFF : _rx_size; + } + USBCDC::unlock(); + + if (size != 0) { + revents |= POLLIN; + } + revents |= POLLOUT; + + return revents; + } + + /** Register a callback on state change of the file. + * + * The specified callback will be called on state changes such as when + * the file can be written to or read from. + * + * The callback may be called in an interrupt context and should not + * perform expensive operations. + * + * Note! This is not intended as an attach-like asynchronous API, but rather + * as a building block for constructing such functionality. + * + * The exact timing of when the registered function + * is called is not guaranteed and is susceptible to change. It should be used + * as a cue to make read/write/poll calls to find the current state. + * + * @param func Function to call on state change + */ + virtual void sigio(Callback func) { + core_util_critical_section_enter(); + _sigio_cb = func; + if (_sigio_cb) { + short current_events = poll(0x7FFF); + if (current_events) { + _sigio_cb(); + } + } + core_util_critical_section_exit(); + } + +protected: + virtual void data_rx() { + assert_locked(); + if (_sigio_cb) { + _sigio_cb.call(); + } + } + +private: + Callback _sigio_cb; + +}; +} //namespace mbed + +#endif //MBED_USBSERIAL_FILEHANDLE_H diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/cmsis_nvic.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/cmsis_nvic.h new file mode 100644 index 0000000..bde6f83 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/cmsis_nvic.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2015-2020 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +/* Copyright (c) 2015-2020 ARM Limited. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/dev_drv.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/dev_drv.h new file mode 100644 index 0000000..3b696f7 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/dev_drv.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2016-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2016-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/****************************************************************************** +* File Name : dev_drv.h +* $Rev: 127 $ +* $Date:: 2016-09-20 11:34:44 +0900#$ +* Description : Device driver header +******************************************************************************/ +#ifndef DEV_DRV_H +#define DEV_DRV_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* ==== Arguments, Return values ==== */ +#define DEVDRV_SUCCESS (0) /* Success */ +#define DEVDRV_ERROR (-1) /* Failure */ + +/* ==== Flags ==== */ +#define DEVDRV_FLAG_OFF (0) /* Flag OFF */ +#define DEVDRV_FLAG_ON (1) /* Flag ON */ + +/* ==== Channels ==== */ +typedef enum devdrv_ch +{ + DEVDRV_CH_0, /* Channel 0 */ + DEVDRV_CH_1, /* Channel 1 */ + DEVDRV_CH_2, /* Channel 2 */ + DEVDRV_CH_3, /* Channel 3 */ + DEVDRV_CH_4, /* Channel 4 */ + DEVDRV_CH_5, /* Channel 5 */ + DEVDRV_CH_6, /* Channel 6 */ + DEVDRV_CH_7, /* Channel 7 */ + DEVDRV_CH_8, /* Channel 8 */ + DEVDRV_CH_9, /* Channel 9 */ + DEVDRV_CH_10, /* Channel 10 */ + DEVDRV_CH_11, /* Channel 11 */ + DEVDRV_CH_12, /* Channel 12 */ + DEVDRV_CH_13, /* Channel 13 */ + DEVDRV_CH_14, /* Channel 14 */ + DEVDRV_CH_15 /* Channel 15 */ +} devdrv_ch_t; + +/****************************************************************************** +Variable Externs +******************************************************************************/ + + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +#endif /* DEV_DRV_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/nvic_wrapper.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/nvic_wrapper.h new file mode 100644 index 0000000..7703978 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/nvic_wrapper.h @@ -0,0 +1,99 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2012-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/**************************************************************************//** +* @file nvic_wrapper.h +* $Rev: $ +* $Date:: $ +* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9) +******************************************************************************/ + +#ifndef NVIC_WRAPPER_H +#define NVIC_WRAPPER_H + + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +/* NVIC functions */ +void NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +uint32_t NVIC_GetPriorityGrouping(void); +void NVIC_EnableIRQ(IRQn_Type IRQn); +void NVIC_DisableIRQ(IRQn_Type IRQn); +uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn); +void NVIC_SetPendingIRQ(IRQn_Type IRQn); +void NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t NVIC_GetActive(IRQn_Type IRQn); +void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority); +uint32_t NVIC_GetPriority(IRQn_Type IRQn); +uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority); +void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +void NVIC_SystemReset(void); +/* SysTick function */ +uint32_t SysTick_Config(uint32_t ticks); +/* Debug In/Output function */ +uint32_t ITM_SendChar (uint32_t ch); +int32_t ITM_ReceiveChar (void); +int32_t ITM_CheckChar (void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* NVIC_WRAPPER_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_l1_rza2m_asm.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_l1_rza2m_asm.h new file mode 100644 index 0000000..6d3694b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_l1_rza2m_asm.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* File Name : r_cache_l1_rza2m_asm.h +* Version : 1.0 +* Description : Definition of the Cortex-A9 Cache asm function. +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#if(1) /* Mbed */ +#include "core_ca.h" +#endif + +#ifndef R_CACHE_L1_RZA2M_ASM_H +#define R_CACHE_L1_RZA2M_ASM_H +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +#if(1) /* Mbed */ + +__STATIC_FORCEINLINE void r_cache_l1_cache_init(void) { + // Do nothing +} + +__STATIC_FORCEINLINE void r_cache_l1_i_inv_all(void) { + __set_ICIALLU(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +__STATIC_FORCEINLINE void r_cache_l1_d_cache_operation(uint32_t operation) { + L1C_CleanInvalidateCache(operation); +} + +__STATIC_FORCEINLINE void r_cache_l1_d_inv_mva(uint32_t line_addr) { + __set_DCIMVAC(line_addr); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +__STATIC_FORCEINLINE void r_cache_l1_d_clean_mva(uint32_t line_addr) { + __set_DCCMVAC(line_addr); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +__STATIC_FORCEINLINE void r_cache_l1_d_clean_inv_mva(uint32_t line_addr) { + __set_DCCIMVAC(line_addr); + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +__STATIC_FORCEINLINE void r_cache_l1_i_enable(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk); + __ISB(); +} + +__STATIC_FORCEINLINE void r_cache_l1_i_disable(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk)); + __ISB(); +} + +__STATIC_FORCEINLINE void r_cache_l1_d_enable(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_C_Msk); + __ISB(); +} + +__STATIC_FORCEINLINE void r_cache_l1_d_disable(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_C_Msk)); + __ISB(); +} + +__STATIC_FORCEINLINE void r_cache_l1_btac_enable(void) { + __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk); + __ISB(); +} + +__STATIC_FORCEINLINE void r_cache_l1_btac_disable(void) { + __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk)); + __ISB(); +} + +__STATIC_FORCEINLINE void r_cache_l1_btac_inv(void) { + __set_BPIALL(0); + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + +__STATIC_FORCEINLINE void r_cache_l1_prefetch_enable(void) { + __set_ACTRL( __get_ACTRL() | ACTLR_L1PE_Msk); +} + +__STATIC_FORCEINLINE void r_cache_l1_prefetch_disable(void) { + __set_ACTRL( __get_ACTRL() & (~ACTLR_L1PE_Msk)); +} +#else +extern void r_cache_l1_cache_init(void); +extern void r_cache_l1_i_inv_all(void); +extern void r_cache_l1_d_cache_operation(uint32_t operation); +extern void r_cache_l1_d_inv_mva(uint32_t line_addr); +extern void r_cache_l1_d_clean_mva(uint32_t line_addr); +extern void r_cache_l1_d_clean_inv_mva(uint32_t line_addr); +extern void r_cache_l1_i_enable(void); +extern void r_cache_l1_i_disable(void); +extern void r_cache_l1_d_enable(void); +extern void r_cache_l1_d_disable(void); +extern void r_cache_l1_btac_enable(void); +extern void r_cache_l1_btac_disable(void); +extern void r_cache_l1_btac_inv(void); +extern void r_cache_l1_prefetch_enable(void); +extern void r_cache_l1_prefetch_disable(void); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* R_CACHE_L1_RZA2M_ASM_H */ + +/* End of File */ + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_lld_rza2m.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_lld_rza2m.h new file mode 100644 index 0000000..6e314ac --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_lld_rza2m.h @@ -0,0 +1,430 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* File Name : r_cache_lld_rza2m.h +* Version : 1.0 +* Description : Definition of the Cortex-A9 Cache API function. +*******************************************************************************/ +/*********************************************************************//** +* @ingroup RENESAS_DRIVER_LIBRARY +* @defgroup R_CACHE_LLD_API CACHE RZA2 EBK_RZA2M Low Level Driver +* +* @section R_CACHE_LLD_API_SUMMARY Summary +* The cache interface provides cache control functionality. +* The cache interface can operate the primary cache of Cortex-A9 and the +* secondary cache of PL 310. +* @{ +************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include + +//#include "driver.h" + +#ifndef R_CACHE_LLD_RZA2M_H +#define R_CACHE_LLD_RZA2M_H + +/****************************************************************************** + Macro definitions + ******************************************************************************/ +/*!< Common error codes supported by all drivers */ +typedef enum +{ + DRV_SUCCESS = 0, /*!< No Error */ + DRV_ERROR = (-1), /*!< General error */ +} e_err_code_t; + +/* Version Number of API */ + +#define STDIO_CACHE_RZ_LLD_DRV_NAME ("LLD EBK_RZA2M CACHE") + +/** Major Version Number of API */ +#define STDIO_CACHE_RZ_LLD_VERSION_MAJOR (1) +/** Minor Version Number of API */ +#define STDIO_CACHE_RZ_LLD_VERSION_MINOR (2) +/** Minor Version Number of API */ +#define STDIO_CACHE_RZ_LLD_BUILD_NUM (0) +/** Unique ID */ +#define STDIO_CACHE_RZ_LLD_UID (111) + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/** + * @brief R_CACHE_L1Init initializes the Cortex-A9 cache. + * + * This function initializes cache of the Cortex-A9 in the following procedure. + * 1. Enable data cache of the Cortex-A9. + * 2. Enable instruction cache of the Cortex-A9. + * 3. Enable branch predicton of the Cortex-A9. + * 4. Enable prefetching of the Cortex-A9. + * + * @note This function does not perform cache invalidate operation. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1Init(void); + +/** + * @brief R_CACHE_L1InstInvalidAll performs invalidate operation to + * all cache lines of the Cortex-A9 instruction cache. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1InstInvalidAll(void); + +/** + * @brief R_CACHE_L1DataInvalidAll performs invalidate operation to + * all cache lines of the Cortex-A9 data cache. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1DataInvalidAll(void); + +/** + * @brief R_CACHE_L1DataCleanAll performs clean operation to + * all cache lines of the Cortex-A9 data cache. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1DataCleanAll(void); + +/** + * @brief R_CACHE_L1DataCleanInvalidAll performs combination of clean + * and invalidate operations to all cache lines of the Cortex-A9 data cache. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1DataCleanInvalidAll(void); + +/** + * @brief R_CACHE_L1DataInvalidLine performs invalidation operations + * on all cache lines included in the specified address range of + * the Cortex-A9 data cache. + * + * If this function receives an area that is not aligned with the + * cache line boundary, it extends the range to the entire cache + * line including the specified area. + * If the size is 0, doing anything and success is returned. + * If the end address exceeds 0xFFFFFFFF, an error is returned. + * + * @param[in] line_addr Starting address of cache operation(virtual address). + * @param[in] size Byte size from line_addr. + * + * @retval 0 DRV_SUCCESS + * @retval -1 DRV_ERROR + */ +extern e_err_code_t R_CACHE_L1DataInvalidLine(void* line_addr, uint32_t size); + +/** + * @brief R_CACHE_L1DataCleanLine performs clean operations + * on all cache lines included in the specified address range of + * the Cortex-A9 data cache. + * + * If this function receives an area that is not aligned with the + * cache line boundary, it extends the range to the entire cache + * line including the specified area. + * If the size is 0, doing anything and success is returned. + * If the end address exceeds 0xFFFFFFFF, an error is returned. + * + * @param[in] line_addr Starting address of cache operation(virtual address). + * @param[in] size Byte size from line_addr. + * + * @retval 0 DRV_SUCCESS + * @retval -1 DRV_ERROR + */ +extern e_err_code_t R_CACHE_L1DataCleanLine(void* line_addr, uint32_t size); + +/** + * @brief R_CACHE_L1DataCleanInvalidLine performs combination of clean + * and invalidate operations on all cache lines included in the specified + * address range of the Cortex-A9 data cache. + * + * If this function receives an area that is not aligned with the + * cache line boundary, it extends the range to the entire cache + * line including the specified area. + * If the size is 0, doing anything and success is returned. + * If the end address exceeds 0xFFFFFFFF, an error is returned. + * + * @param[in] line_addr Starting address of cache operation(virtual address). + * @param[in] size Byte size from line_addr. + * + * @retval 0 DRV_SUCCESS + * @retval -1 DRV_ERROR + */ +extern e_err_code_t R_CACHE_L1DataCleanInvalidLine(void* line_addr, uint32_t size); + +/** + * @brief R_CACHE_L1InstEnable enables instruction cache of the Cortex-A9. + * + * This function sets the following bit of the SCTLR register of the Cortex-A9. + * - bit12 : I bit + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1InstEnable(void); + +/** + * @brief R_CACHE_L1InstDisable disables instruction cache of the Cortex-A9. + * + * This function clears the following bit of the SCTLR register of the Cortex-A9. + * - bit12 : I bit + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1InstDisable(void); + +/** + * @brief R_CACHE_L1DataEnable enables data cache of the Cortex-A9. + * + * This function sets the following bit of the SCTLR register of the Cortex-A9. + * - bit2 : C bit + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1DataEnable(void); + +/** + * @brief R_CACHE_L1DataDisable disables data cache of the Cortex-A9. + * + * This function clears the following bit of the SCTLR register of the Cortex-A9. + * - bit2 : C bit + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1DataDisable(void); + +/** + * @brief R_CACHE_L1BtacEnable enables branch prediction of the Cortex-A9. + * + * This function sets the following bit of the SCTLR register of the Cortex-A9. + * - bit11 : Z bit + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1BtacEnable(void); + +/** + * @brief R_CACHE_L1BtacDisable disables branch prediction of the Cortex-A9. + * + * This function clears the following bit of the SCTLR register of the Cortex-A9. + * - bit11 : Z bit + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1BtacDisable(void); + +/** + * @brief R_CACHE_L1BtacInvalidate performs invalidation operations on the + * all entries of the Cortex-A9 branch predictor. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1BtacInvalidate(void); + +/** + * @brief R_CACHE_L1PrefetchEnable enables prefetching capability of the Cortex-A9. + * + * This function sets the following bit of the ACTLR register of the Cortex-A9. + * - bit2 : L1 Prefetch enable + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1PrefetchEnable(void); + +/** + * @brief R_CACHE_L1PrefetchDisable disables prefetching capability of the Cortex-A9. + * + * This function clears the following bit of the ACTLR register of the Cortex-A9. + * - bit2 : L1 Prefetch enable + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L1PrefetchDisable(void); + +/** + * @brief R_CACHE_L2Init initializes the PL310 cache. + * + * This function initializes the PL310 in the following procedure. + * 1. Disable cache of the PL310. + * 2. Enable prefetching capability of the PL310. + * 3. Invalidate all cache entries of the PL310. + * 4. Enable cache of the PL310. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2Init(void); + +/** + * @brief R_CACHE_L2CacheEnable enables cache of the PL310. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2CacheEnable(void); + +/** + * @brief R_CACHE_L2CacheDisable disables cache of the PL310. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2CacheDisable(void); + +/** + * @brief R_CACHE_L2PrefetchEnable enables prefetching capability of the PL310. + * + * This function sets the following bits of the REG15_PREFETCH_CTRL + * register of PL310. + * - bit28 : Data prefetch enable (If PL310_CFG_DATA_PREFETCH==1) + * - bit29 : Instruction prefetch enable (If PL310_CFG_INSTRUCTION_PREFETCH==1) + * - bit30 : Double linefill enable (If PL310_CFG_DOUBLE_LINE_FILL==1) + * + * Which bit to set depends on the macro setting in the configuration header + * file r_cache_rza2_config.h. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2PrefetchEnable(void); + +/** + * @brief R_CACHE_L2PrefetchDisable disables prefetching capability of the PL310. + * + * This function clears the following bits of the REG15_PREFETCH_CTRL + * register of PL310. + * - bit28 : Data prefetch enable + * - bit29 : Instruction prefetch enable + * - bit30 : Double linefill enable + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2PrefetchDisable(void); + +/** + * @brief R_CACHE_L2InvalidAll performs invalidate operation to + * all cache lines of the PL310 cache. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2InvalidAll(void); + +/** + * @brief R_CACHE_L2CleanAll performs clean operation to + * all cache lines of the PL310 cache. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2CleanAll(void); + +/** + * @brief R_CACHE_L2CleanInvalidAll performs combination of clean + * and invalidate operations to all cache lines of the PL310 cache. + * + * @param none + * + * @retval none + */ +extern void R_CACHE_L2CleanInvalidAll(void); + +/** + * @brief R_CACHE_GetVersion + * Gets the version number of this low-level driver + * @param[out] p_ver_info: returns the driver information + * @retval DRV_SUCCESS Always returned + */ +//extern int_t R_CACHE_GetVersion(st_ver_info_t *p_ver_info); + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/*********************************************************************//** +* @} +************************************************************************/ +#endif /* R_CACHE_LLD_RZA2M_H */ + +/* End of File */ + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_rza2_config.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_rza2_config.h new file mode 100644 index 0000000..764b3b3 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/inc/r_cache_rza2_config.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/****************************************************************************** +* File Name : r_cache_rza2_config.h +* Description : User modifyable CACHE configuration table +* (This file currently not updated by Smart Configurator) +******************************************************************************/ + +#ifndef R_CACHE_RZA2_CONFIG_H_ +#define R_CACHE_RZA2_CONFIG_H_ + +/****************************************************************************** +Configuration Options +*******************************************************************************/ + +/* select whether PL310 double line fill enable or disable + * 0 : Disable PL310 double line fill + * 1 : Enable PL310 double line fill + */ +#define PL310_CFG_DOUBLE_LINE_FILL (0) + +/* select whether PL310 instruction prefetch enable or disable + * 0 : Disable PL310 instruction prefetch + * 1 : Enable PL310 instruction prefetch + */ +#define PL310_CFG_INSTRUCTION_PREFETCH (0) + +/* select whether PL310 data prefetch enable or disable + * 0 : Disable PL310 data prefetch + * 1 : Enable PL310 data prefetch + */ +#define PL310_CFG_DATA_PREFETCH (0) + + +#endif /* R_CACHE_RZA2_CONFIG_H_ */ +/* END of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/src/lld/r_cache_lld_rza2m.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/src/lld/r_cache_lld_rza2m.c new file mode 100644 index 0000000..fe04bd1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_cache/src/lld/r_cache_lld_rza2m.c @@ -0,0 +1,726 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* File Name : r_cache_lld_rza2m.c +* Version : 1.0 +* Description : Declaration of the Cortex-A9 Cache API function. +*******************************************************************************/ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include "iodefine.h" +#include "iobitmask.h" +#include "rza_io_regrw.h" +#include "r_cache_lld_rza2m.h" +#include "r_cache_l1_rza2m_asm.h" +#include "r_cache_rza2_config.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define CACHE_PRV_ADDR_MAX (0xFFFFFFFFuLL) +#define CACHE_PRV_ADDR_MASK (0xFFFFFFFFuLL) + +#define CACHE_PRV_L1_OP_D_INV_ALL (0) +#define CACHE_PRV_L1_OP_D_CLEAN_ALL (1) +#define CACHE_PRV_L1_OP_D_CLEAN_INV_ALL (2) + +#define CACHE_PRV_CA9_LINE_SIZE (0x20u) +#define CACHE_PRV_CA9_LINE_MASK (0xFFFFFFE0u) + +#define CACHE_PRV_PL310_ALLWAYBITS_8 (0x00FFu) + +#define CACHE_PRV_PL310_CACHE_LINE_SIZE (0x20u) +#define CACHE_PRV_PL310_CACHE_LINE_MASK (0xFFFFFFE0u) + +#define CACHE_PRV_PL310_ALLINT (0x1FFu) + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ +#if(0) +/*! Version Information */ +static const st_drv_info_t gs_lld_info = +{ + { + ((STDIO_CACHE_RZ_LLD_VERSION_MAJOR << 16) + STDIO_CACHE_RZ_LLD_VERSION_MINOR) + }, + STDIO_CACHE_RZ_LLD_BUILD_NUM, + STDIO_CACHE_RZ_LLD_DRV_NAME +}; +#endif + +static void cache_l2_sync(void); + +/******************************************************************************* +* Function Name: R_CACHE_L1Init +* Description : Initialize Cortex-A9 cache. +* Arguments : none +* Return Value : none +* Note : Invalidate data cache must be executed by reset handler before +* processing of this function. +*******************************************************************************/ +void R_CACHE_L1Init(void) +{ + /* Enable I,D cache */ + R_CACHE_L1DataEnable(); + R_CACHE_L1InstEnable(); + + /* Enable branch prediction */ + R_CACHE_L1BtacEnable(); + + /* Enable prefetch */ + R_CACHE_L1PrefetchEnable(); + + r_cache_l1_cache_init(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1Init +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1InstInvalidAll +* Description : Invalidate whole of the Cortex-A9 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1InstInvalidAll(void) +{ + r_cache_l1_i_inv_all(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1InstInvalidAll +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataInvalidAll +* Description : Invalidate whole of the Cortex-A9 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1DataInvalidAll(void) +{ + r_cache_l1_d_cache_operation(CACHE_PRV_L1_OP_D_INV_ALL); + return; +} +/******************************************************************************* +End of function R_CACHE_L1DataInvalidAll +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataCleanAll +* Description : Clean whole of the Cortex-A9 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1DataCleanAll(void) +{ + r_cache_l1_d_cache_operation(CACHE_PRV_L1_OP_D_CLEAN_ALL); + return; +} +/******************************************************************************* +End of function R_CACHE_L1DataCleanAll +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataCleanInvalidAll +* Description : Clean&invalidate whole of the Cortex-A9 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1DataCleanInvalidAll(void) +{ + r_cache_l1_d_cache_operation(CACHE_PRV_L1_OP_D_CLEAN_INV_ALL); + return; +} +/******************************************************************************* +End of function R_CACHE_L1DataCleanInvalidAll +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataInvalidLine +* Description : Apply invalidate operation to the cache lines which is included +* in the specified address range. +* Arguments : line_addr - +* Starting address of cache operation (virtual address). +* size - +* The byte size from line_addr. +* Return Value : DRV_SUCCESS : successful +* DRV_ERROR : address overflow +*******************************************************************************/ +e_err_code_t R_CACHE_L1DataInvalidLine(void* line_addr, uint32_t size) +{ + e_err_code_t ret = DRV_SUCCESS; + + /* Casting void type address to uint32_t is valid because there is no loss of information. */ + uint32_t addr = (((uint32_t)line_addr) & CACHE_PRV_CA9_LINE_MASK); + + /* Casting void type address to uint64_t is valid because there is no loss of information. */ + uint64_t end_addr = ((uint64_t)((uint32_t)line_addr) & CACHE_PRV_ADDR_MASK) + ((uint64_t)size); + + if (CACHE_PRV_ADDR_MAX < end_addr) + { + ret = DRV_ERROR; + } + else + { + for ( ; addr < end_addr; addr += CACHE_PRV_CA9_LINE_SIZE) + { + r_cache_l1_d_inv_mva(addr); + } + } + return ret; +} +/******************************************************************************* +End of function R_CACHE_L1DataInvalidLine +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataCleanLine +* Description : Apply clean operation to the cache lines which is included +* in the specified address range. +* Arguments : line_addr - +* Starting address of cache operation (virtual address). +* size - +* The byte size from line_addr. +* Return Value : DRV_SUCCESS : successful +* DRV_ERROR : address overflow +*******************************************************************************/ +e_err_code_t R_CACHE_L1DataCleanLine(void* line_addr, uint32_t size) +{ + e_err_code_t ret = DRV_SUCCESS; + + /* Casting void type address to uint32_t is valid because there is no loss of information. */ + uint32_t addr = (((uint32_t)line_addr) & CACHE_PRV_CA9_LINE_MASK); + + /* Casting void type address to uint64_t is valid because there is no loss of information. */ + uint64_t end_addr = ((uint64_t)((uint32_t)line_addr) & CACHE_PRV_ADDR_MASK) + ((uint64_t)size); + + if (CACHE_PRV_ADDR_MAX < end_addr) + { + ret = DRV_ERROR; + } + else + { + for ( ; addr < end_addr; addr += CACHE_PRV_CA9_LINE_SIZE) + { + r_cache_l1_d_clean_mva(addr); + } + } + return ret; +} +/******************************************************************************* +End of function R_CACHE_L1DataCleanLine +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataCleanInvalidLine +* Description : Apply clean&invalidate operation to the cache lines which is +* included in the specified address range. +* Arguments : line_addr - +* Starting address of cache operation (virtual address). +* size - +* The byte size from line_addr. +* Return Value : DRV_SUCCESS : successful +* DRV_ERROR : address overflow +*******************************************************************************/ +e_err_code_t R_CACHE_L1DataCleanInvalidLine(void* line_addr, uint32_t size) +{ + e_err_code_t ret = DRV_SUCCESS; + + /* Casting void type address to uint32_t is valid because there is no loss of information. */ + uint32_t addr = (((uint32_t)line_addr) & CACHE_PRV_CA9_LINE_MASK); + + /* Casting void type address to uint64_t is valid because there is no loss of information. */ + uint64_t end_addr = ((uint64_t)((uint32_t)line_addr) & CACHE_PRV_ADDR_MASK) + ((uint64_t)size); + + if (CACHE_PRV_ADDR_MAX < end_addr) + { + ret = DRV_ERROR; + } + else + { + for ( ; addr < end_addr; addr += CACHE_PRV_CA9_LINE_SIZE) + { + r_cache_l1_d_clean_inv_mva(addr); + } + } + return ret; +} +/******************************************************************************* +End of function R_CACHE_L1DataCleanInvalidLine +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1InstEnable +* Description : Enable the Cortex-A9 L1 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1InstEnable(void) +{ + r_cache_l1_i_enable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1InstEnable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1InstDisable +* Description : Disable the Cortex-A9 L1 instruction cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1InstDisable(void) +{ + r_cache_l1_i_disable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1InstDisable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataEnable +* Description : Enable the Cortex-A9 L1 data cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1DataEnable(void) +{ + r_cache_l1_d_enable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1DataEnable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1DataDisable +* Description : Disable the Cortex-A9 L1 data cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1DataDisable(void) +{ + r_cache_l1_d_disable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1DataDisable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1BtacEnable +* Description : Enable the Cortex-A9 branch prediction. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1BtacEnable(void) +{ + r_cache_l1_btac_enable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1BtacEnable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1BtacDisable +* Description : Disable the Cortex-A9 branch prediction. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1BtacDisable(void) +{ + r_cache_l1_btac_disable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1BtacDisable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1BtacInvalidate +* Description : Invalidate the Cortex-A9 branch predictor. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1BtacInvalidate(void) +{ + r_cache_l1_btac_inv(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1BtacInvalidate +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1PrefetchEnable +* Description : Enable the Cortex-A9 instruction and data prefetching. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1PrefetchEnable(void) +{ + r_cache_l1_prefetch_enable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1PrefetchEnable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L1PrefetchDisable +* Description : Disable the Cortex-A9 instruction and data prefetching. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L1PrefetchDisable(void) +{ + r_cache_l1_prefetch_disable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L1PrefetchDisable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2Init +* Description : Initialize PL310. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2Init(void) +{ + /* You must disable the L2 cache by writing to the Control Register 1 before + * writing to the Auxiliary, Tag RAM Latency, or Data RAM Latency Control + * Register. + */ + R_CACHE_L2CacheDisable(); + + /* 1. Write to the Auxiliary, Tag RAM Latency, Data RAM Latency, Prefetch, + * and Power Control registers using a read-modify-write to set up global + * configurations: + */ + R_CACHE_L2PrefetchEnable(); + + /* 2. Secure write to the Invalidate by Way, offset 0x77C, to invalidate all + * entries in cache: + */ + R_CACHE_L2InvalidAll(); + + /* 3. Write to the Lockdown D and Lockdown I Register 9 if required. */ + /* use default */ + + /* 4. Write to interrupt clear register to clear any residual raw interrupts set. */ + RZA_IO_RegWrite_32(&pl310.REG2_INT_CLEAR.LONG, CACHE_PRV_PL310_ALLINT, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + /* 5. Write to the Interrupt Mask Register if you want to enable interrupts. */ + /* do nothing */ + + /* 6. Write to Control Register 1 with the LSB set to 1 to enable the cache. + */ + R_CACHE_L2CacheEnable(); + return; +} +/******************************************************************************* +End of function R_CACHE_L2Init +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2CacheEnable +* Description : Enable the PL310 L2 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2CacheEnable(void) +{ + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG1_CONTROL.LONG, 1, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + cache_l2_sync(); + return; +} +/******************************************************************************* +End of function R_CACHE_L2CacheEnable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2CacheDisable +* Description : Disable the PL310 L2 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2CacheDisable(void) +{ + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG1_CONTROL.LONG, 0, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + cache_l2_sync(); + return; +} +/******************************************************************************* +End of function R_CACHE_L2CacheDisable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2PrefetchEnable +* Description : Enable the PL310 instruction and data prefetching. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2PrefetchEnable(void) +{ + uint32_t reg32; + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + reg32 = RZA_IO_RegRead_32(&pl310.REG15_PREFETCH_CTRL.LONG, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + +#if defined(PL310_CFG_DOUBLE_LINE_FILL) && (PL310_CFG_DOUBLE_LINE_FILL==1) + reg32 |= (1u << PL310_REG15_PREFETCH_CTRL_Doublelinefillenable_SHIFT); +#elif defined(PL310_CFG_DOUBLE_LINE_FILL) && (PL310_CFG_DOUBLE_LINE_FILL==0) + reg32 &= (~(1u << PL310_REG15_PREFETCH_CTRL_Doublelinefillenable_SHIFT)); +#endif/*PL310_CFG_DOUBLE_LINE_FILL*/ + +#if defined(PL310_CFG_INSTRUCTION_PREFETCH) && (PL310_CFG_INSTRUCTION_PREFETCH==1) + reg32 |= (1u << PL310_REG15_PREFETCH_CTRL_Instructionprefetchenable_SHIFT); +#elif defined(PL310_CFG_INSTRUCTION_PREFETCH) && (PL310_CFG_INSTRUCTION_PREFETCH==0) + reg32 &= (~(1u << PL310_REG15_PREFETCH_CTRL_Instructionprefetchenable_SHIFT)); +#endif/*PL310_CFG_INSTRUCTION_PREFETCH*/ + +#if defined(PL310_CFG_DATA_PREFETCH) && (PL310_CFG_DATA_PREFETCH==1) + reg32 |= (1u << PL310_REG15_PREFETCH_CTRL_Dataprefetchenable_SHIFT); +#elif defined(PL310_CFG_DATA_PREFETCH) && (PL310_CFG_DATA_PREFETCH==0) + reg32 &= (~(1u << PL310_REG15_PREFETCH_CTRL_Dataprefetchenable_SHIFT)); +#endif/*PL310_CFG_DATA_PREFETCH*/ + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG15_PREFETCH_CTRL.LONG, reg32, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + cache_l2_sync(); + return; +} +/******************************************************************************* +End of function R_CACHE_L2PrefetchEnable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2PrefetchDisable +* Description : Disable the PL310 instruction and data prefetching. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2PrefetchDisable(void) +{ + uint32_t reg32; + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + reg32 = RZA_IO_RegRead_32(&pl310.REG15_PREFETCH_CTRL.LONG, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + reg32 &= (~(1u << PL310_REG15_PREFETCH_CTRL_Doublelinefillenable_SHIFT)); + reg32 &= (~(1u << PL310_REG15_PREFETCH_CTRL_Instructionprefetchenable_SHIFT)); + reg32 &= (~(1u << PL310_REG15_PREFETCH_CTRL_Dataprefetchenable_SHIFT)); + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG15_PREFETCH_CTRL.LONG, reg32, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + cache_l2_sync(); + return; +} +/******************************************************************************* +End of function R_CACHE_L2PrefetchDisable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2InvalidAll +* Description : Invalidate whole of the PL310 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2InvalidAll(void) +{ + uint32_t reg32; + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG7_INV_WAY.LONG, + CACHE_PRV_PL310_ALLWAYBITS_8, + PL310_REG7_INV_WAY_Way_bits_SHIFT, + PL310_REG7_INV_WAY_Way_bits); + + /* Wait until complete background operation */ + do + { + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + reg32 = RZA_IO_RegRead_32(&pl310.REG7_INV_WAY.LONG, + PL310_REG7_INV_WAY_Way_bits_SHIFT, + PL310_REG7_INV_WAY_Way_bits); + } while (0 != reg32); + cache_l2_sync(); + + return; +} +/******************************************************************************* +End of function R_CACHE_L2InvalidAll +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2CleanAll +* Description : Clean whole of the PL310 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2CleanAll(void) +{ + uint32_t reg32; + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG7_CLEAN_WAY.LONG, + CACHE_PRV_PL310_ALLWAYBITS_8, + PL310_REG7_CLEAN_WAY_Way_bits_SHIFT, + PL310_REG7_CLEAN_WAY_Way_bits); + + /* Wait until complete background operation */ + do + { + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + reg32 = RZA_IO_RegRead_32(&pl310.REG7_CLEAN_WAY.LONG, + PL310_REG7_CLEAN_WAY_Way_bits_SHIFT, + PL310_REG7_CLEAN_WAY_Way_bits); + } while (0 != reg32); + cache_l2_sync(); + + return; +} +/******************************************************************************* +End of function R_CACHE_L2CleanAll +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_L2CleanInvalidAll +* Description : Clean&invalidate whole of the PL310 cache. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CACHE_L2CleanInvalidAll(void) +{ + uint32_t reg32; + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG7_CLEAN_INV_WAY.LONG, + CACHE_PRV_PL310_ALLWAYBITS_8, + PL310_REG7_CLEAN_INV_WAY_Way_bits_SHIFT, + PL310_REG7_CLEAN_INV_WAY_Way_bits); + + /* Wait until complete background operation */ + do + { + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + reg32 = RZA_IO_RegRead_32(&pl310.REG7_CLEAN_INV_WAY.LONG, + PL310_REG7_CLEAN_INV_WAY_Way_bits_SHIFT, + PL310_REG7_CLEAN_INV_WAY_Way_bits); + } while (0 != reg32); + cache_l2_sync(); + + return; +} +/******************************************************************************* +End of function R_CACHE_L2CleanInvalidAll +*******************************************************************************/ + +/******************************************************************************* +* Function Name: cache_l2_sync +* Description : Perform a cache sync operation. +* Arguments : none +* Return Value : none +*******************************************************************************/ +static void cache_l2_sync(void) +{ + uint32_t reg32; + + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + RZA_IO_RegWrite_32(&pl310.REG7_CACHE_SYNC.LONG, 0, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + + do + { + /* Casting the pointer to a uint32_t type is valid because "unsigned long" is same 4byte unsigned integer type. */ + reg32 = RZA_IO_RegRead_32(&pl310.REG7_CACHE_SYNC.LONG, IOREG_NONSHIFT_ACCESS, IOREG_NONMASK_ACCESS); + } while (0 != reg32); + + return; +} +/******************************************************************************* +End of function cache_l2_sync +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_CACHE_GetVersion +* Description : Gets the version number of this low-level driver +* Arguments : p_ver_info[out] - returns the driver information +* Return Value : DRV_SUCCESS Always returned +*******************************************************************************/ +#if(0) +int_t R_CACHE_GetVersion(st_ver_info_t *p_ver_info) +{ + p_ver_info->lld.p_szdriver_name = gs_lld_info.p_szdriver_name; + p_ver_info->lld.version.sub.major = gs_lld_info.version.sub.major; + p_ver_info->lld.version.sub.minor = gs_lld_info.version.sub.minor; + p_ver_info->lld.build = gs_lld_info.build; + + return (DRV_SUCCESS); +} +#endif +/****************************************************************************** + * End of function R_CACHE_GetVersion + ******************************************************************************/ + +/* End of File */ + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_typedefs.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_typedefs.h new file mode 100644 index 0000000..d9e0d7c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_typedefs.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2017-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/* Copyright (c) 2017-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/******************************************************************************* +* File Name : r_typedefs.h +* $Rev: 149 $ +* $Date:: 2017-12-15 16:34:38 +0900#$ +* Description : basic type definition +******************************************************************************/ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include +#include + +#if defined(__ARM_NEON__) +#include +#endif /* __ARM_NEON__ */ + +#ifndef float32_t +typedef float float32_t; +#endif +#ifndef float64_t +typedef double float64_t; +#endif + +/****************************************************************************** +Typedef definitions +******************************************************************************/ +typedef char char_t; +#ifndef bool_t +typedef bool bool_t; +#endif +typedef int int_t; +typedef long double float128_t; +typedef signed long long_t; +typedef unsigned long ulong_t; + + +#endif /* R_TYPEDEFS_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/rza_io_regrw.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/rza_io_regrw.c new file mode 100644 index 0000000..feba284 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/rza_io_regrw.c @@ -0,0 +1,235 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/********************************************************************************************************************** + * File Name : rza_io_regrw.c + * Description : Low level register read/write + *********************************************************************************************************************/ + +/********************************************************************************************************************** + Includes , "Project Includes" + *********************************************************************************************************************/ +#include "r_typedefs.h" +#include "rza_io_regrw.h" + +/********************************************************************************************************************** + Private (static) variables and functions + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: RZA_IO_RegWrite_8 + * Description : IO register 8-bit write + * Arguments : volatile uint8_t * ioreg : IO register for writing + * : : Use register definition name of the iodefine.h + * : uint8_t write_value : Write value for the IO register + * : uint8_t shift : The number of left shifts to the target bit + * : uint32_t mask : Mask value for the IO register (Target bit : "1") + * Return Value : None + *********************************************************************************************************************/ +void RZA_IO_RegWrite_8(volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint32_t mask) +{ + uint8_t reg_value; + + if (IOREG_NONMASK_ACCESS != mask) + { + /* Read from register */ + reg_value = *ioreg; + + /* Modify value */ + reg_value = (uint8_t)((reg_value & (~mask)) | (uint8_t)(write_value << shift)); + } + else + { + reg_value = write_value; + } + + /* Write to register */ + *ioreg = reg_value; +} +/********************************************************************************************************************** + * End of function RZA_IO_RegWrite_8 + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: RZA_IO_RegWrite_16 + * Description : IO register 16-bit write + * Arguments : volatile uint16_t * ioreg : IO register for writing + * : : Use register definition name of the iodefine.h + * : uint16_t write_value : Write value for the IO register + * : uint16_t shift : The number of left shifts to the target bit + * : uint32_t mask : Mask value for the IO register (Target bit : "1") + * Return Value : None + *********************************************************************************************************************/ +void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint32_t mask) +{ + uint16_t reg_value; + + if (IOREG_NONMASK_ACCESS != mask) + { + /* Read from register */ + reg_value = *ioreg; + + /* Modify value */ + reg_value = (uint16_t)((reg_value & (~mask)) | (uint16_t)(write_value << shift)); + } + else + { + reg_value = write_value; + } + + /* Write to register */ + *ioreg = reg_value; +} +/********************************************************************************************************************** + * End of function RZA_IO_RegWrite_16 + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: RZA_IO_RegWrite_32 + * Description : IO register 32-bit write + * Arguments : volatile uint32_t * ioreg : IO register for writing + * : : Use register definition name of the iodefine.h + * : uint32_t write_value : Write value for the IO register + * : uint32_t shift : The number of left shifts to the target bit + * : uint32_t mask : Mask value for the IO register (Target bit : "1") + * Return Value : None + *********************************************************************************************************************/ +void RZA_IO_RegWrite_32(volatile unsigned long * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) +{ + uint32_t reg_value; + + if (IOREG_NONMASK_ACCESS != mask) + { + /* Read from register */ + reg_value = *ioreg; + + /* Modify value */ + reg_value = (uint32_t)((reg_value & (~mask)) | (uint32_t)(write_value << shift)); + } + else + { + reg_value = write_value; + } + + /* Write to register */ + *ioreg = reg_value; +} +/********************************************************************************************************************** + * End of function RZA_IO_RegWrite_32 + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: RZA_IO_RegRead_8 + * Description : IO register 8-bit read + * Arguments : volatile uint8_t * ioreg : IO register for reading + * : : Use register definition name of the iodefine.h + * : uint8_t shift : The number of right shifts to the target bit + * : uint32_t mask : Mask bit for the IO register (Target bit: "1") + * Return Value : uint8_t : Value of the obtained target bit + *********************************************************************************************************************/ +uint8_t RZA_IO_RegRead_8(volatile uint8_t * ioreg, uint8_t shift, uint32_t mask) +{ + uint8_t reg_value; + + /* Read from register */ + reg_value = *ioreg; + + if (IOREG_NONMASK_ACCESS != mask) + { + /* Clear other bit and Bit shift */ + reg_value = (uint8_t)((reg_value & mask) >> shift); + } + + return (reg_value); +} +/********************************************************************************************************************** + * End of function RZA_IO_RegRead_8 + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: RZA_IO_RegRead_16 + * Description : IO register 16-bit read + * Arguments : volatile uint16_t * ioreg : IO register for reading + * : : Use register definition name of the iodefine.h + * : uint16_t shift : The number of right shifts to the target bit + * : uint32_t mask : Mask bit for the IO register (Target bit: "1") + * Return Value : uint16_t : Value of the obtained target bit + *********************************************************************************************************************/ +uint16_t RZA_IO_RegRead_16(volatile uint16_t * ioreg, uint16_t shift, uint32_t mask) +{ + uint16_t reg_value; + + /* Read from register */ + reg_value = *ioreg; + + if (IOREG_NONMASK_ACCESS != mask) + { + /* Clear other bit and Bit shift */ + reg_value = (uint16_t)((reg_value & mask) >> shift); + } + + return (reg_value); +} +/********************************************************************************************************************** + * End of function RZA_IO_RegRead_16 + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Function Name: RZA_IO_RegRead_32 + * Description : IO register 32-bit read + * Arguments : volatile uint32_t * ioreg : IO register for reading + * : : Use register definition name of the iodefine.h + * : uint32_t shift : The number of right shifts to the target bit + * : uint32_t mask : Mask bit for the IO register (Target bit: "1") + * Return Value : uint32_t : Value of the obtained target bit + *********************************************************************************************************************/ +uint32_t RZA_IO_RegRead_32(volatile unsigned long * ioreg, uint32_t shift, uint32_t mask) +{ + uint32_t reg_value; + + /* Read from register */ + reg_value = *ioreg; + + if (IOREG_NONMASK_ACCESS != mask) + { + /* Clear other bit and Bit shift */ + reg_value = (reg_value & mask) >> shift; + } + + return (reg_value); +} +/********************************************************************************************************************** + * End of function RZA_IO_RegRead_32 + *********************************************************************************************************************/ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/rza_io_regrw.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/rza_io_regrw.h new file mode 100644 index 0000000..153ee82 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/rza_io_regrw.h @@ -0,0 +1,149 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2018-2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ +/********************************************************************************************************************** + * File Name : rza_io_regrw.h + * Description : Low level register read/write header + *********************************************************************************************************************/ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "r_typedefs.h" + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#ifndef RZA_IO_REGRW_H +#define RZA_IO_REGRW_H + +#define IOREG_NONMASK_ACCESS (0xFFFFFFFFuL) +#define IOREG_NONSHIFT_ACCESS (0) + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/****************************************************************************** + * @fn RZA_IO_RegWrite_8 + * @brief IO register 8-bit write + * To use macros defined in iodefine files is convenient. + * @param [in] ioreg: address for target register + * @param [in] write_value: value to be write + * @param [in] shift: target bit offset from LSB + * @param [in] mask: target data mask (bits position of '0' are leave alone) + * If no one need to keep previous value or shift, use + * IOREG_NONMASK_ACCESS instead. + *****************************************************************************/ +extern void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint32_t mask); + +/****************************************************************************** + * @fn RZA_IO_RegWrite_16 + * @brief IO register 16-bit write + * To use macros defined in iodefine files is convenient. + * @param [in] ioreg: address for target register + * @param [in] write_value: value to be write + * @param [in] shift: target bit offset from LSB + * @param [in] mask: target data mask (bits position of '0' are leave alone) + * If no one need to keep previous value or shift, use + * IOREG_NONMASK_ACCESS instead. + *****************************************************************************/ +extern void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint32_t mask); + +/****************************************************************************** + * @fn RZA_IO_RegWrite_32 + * @brief IO register 32-bit write + * To use macros defined in iodefine files is convenient. + * @param [in] ioreg: address for target register + * @param [in] write_value: value to be write + * @param [in] shift: target bit offset from LSB + * @param [in] mask: target data mask (bits position of '0' are leave alone) + * If no one need to keep previous value or shift, use + * IOREG_NONMASK_ACCESS instead. + *****************************************************************************/ +extern void RZA_IO_RegWrite_32(volatile unsigned long * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask); + +/****************************************************************************** + * @fn RZA_IO_RegRead_8 + * @brief IO register 8-bit read + * To use macros defined in iodefine files is convenient. + * @param [in] ioreg: address for target register + * @param [in] shift: target bit offset from LSB + * @param [in] mask: target data mask (masked before shift) + * If no one need to mask and shift, use + * IOREG_NONMASK_ACCESS instead. + * @retval read value from register + *****************************************************************************/ +extern uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint32_t mask); + +/****************************************************************************** + * @fn RZA_IO_RegRead_16 + * @brief IO register 16-bit read + * To use macros defined in iodefine files is convenient. + * @param [in] ioreg: address for target register + * @param [in] shift: target bit offset from LSB + * @param [in] mask: target data mask (masked before shift) + * If no one need to mask and shift, use + * IOREG_NONMASK_ACCESS instead. + * @retval read value from register + *****************************************************************************/ +extern uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint32_t mask); + +/****************************************************************************** + * @fn RZA_IO_RegRead_32 + * @brief IO register 32-bit read + * To use macros defined in iodefine files is convenient. + * @param [in] ioreg: address for target register + * @param [in] shift: target bit offset from LSB + * @param [in] mask: target data mask (masked before shift) + * If no one need to mask and shift, use + * IOREG_NONMASK_ACCESS instead. + * @retval read value from register + *****************************************************************************/ +extern uint32_t RZA_IO_RegRead_32 (volatile unsigned long * ioreg, uint32_t shift, uint32_t mask); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* RZA_IO_REGRW_H */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/target_override_console.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/target_override_console.cpp new file mode 100644 index 0000000..7b2b548 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/target_override_console.cpp @@ -0,0 +1,34 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019-2020 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(OVERRIDE_CONSOLE_USBSERIAL) + +#include "USBSerial_FileHandle.h" +#include "platform/mbed_wait_api.h" + +static mbed::USBSerial_FileHandle console(false); + +mbed::FileHandle *mbed::mbed_target_override_console(int fd) +{ + console.connect(); + for (int i = 0; (i < 50) && (console.ready() == false); i++) { + wait_ms(10); + } + return &console; +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/vfp_neon_push_pop.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/vfp_neon_push_pop.h new file mode 100644 index 0000000..a31c3f6 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/vfp_neon_push_pop.h @@ -0,0 +1,181 @@ +/* Copyright (c) 2016-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __VFP_NEON_PUSH_POP_H__ +#define __VFP_NEON_PUSH_POP_H__ + + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#pragma push +#pragma arm +static __asm void __vfp_neon_push(void) { + ARM + + VMRS R2,FPSCR + STMDB SP!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment + VSTMDB SP!,{D0-D15} + VSTMDB SP!,{D16-D31} + BX LR +} +#pragma pop + +#pragma push +#pragma arm +static __asm void __vfp_neon_pop(void) { + ARM + + VLDMIA SP!,{D16-D31} + VLDMIA SP!,{D0-D15} + LDR R2,[SP] + VMSR FPSCR,R2 + ADD SP,SP,#8 + BX LR +} +#pragma pop + + +#pragma push +#pragma arm +static __asm void __vfp_push(void) { + ARM + + VMRS R2,FPSCR + STMDB SP!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment + VSTMDB SP!,{D0-D15} + BX LR +} +#pragma pop + +#pragma push +#pragma arm +static __asm void __vfp_pop(void) { + ARM + + VLDMIA SP!,{D0-D15} + LDR R2,[SP] + VMSR FPSCR,R2 + ADD SP,SP,#8 + BX LR +} +#pragma pop + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ + +__arm static inline void __vfp_neon_push(void) { +__asm( + "ARM \n" + "VMRS R2,FPSCR \n" + "STMDB SP!,{R2,R4} \n" // Push FPSCR, maintain 8-byte alignment + "VSTMDB SP!,{D0-D15} \n" + "VSTMDB SP!,{D16-D31} \n" + "BX lr \n" ); +} + +__arm static inline void __vfp_neon_pop(void) { +__asm( + "ARM \n" + "VLDMIA SP!,{D16-D31} \n" + "VLDMIA SP!,{D0-D15} \n" + "LDR R2,[SP] \n" + "VMSR FPSCR,R2 \n" + "ADD SP,SP,#8 \n" + "BX lr \n" ); +} + +__arm static inline void __vfp_push(void) { +__asm( + "ARM \n" + "VMRS R2,FPSCR \n" + "STMDB SP!,{R2,R4} \n" // Push FPSCR, maintain 8-byte alignment + "VSTMDB SP!,{D0-D15} \n" + "BX lr \n" ); +} + +__arm static inline void __vfp_pop(void) { +__asm( + "ARM \n" + "VLDMIA SP!,{D0-D15} \n" + "LDR R2,[SP] \n" + "VMSR FPSCR,R2 \n" + "ADD SP,SP,#8 \n" + "BX lr \n" ); +} + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_push(void) +{ + __asm__ volatile ( + ".ARM;" + + "VMRS R2,FPSCR;" + "STMDB SP!,{R2,R4};" // Push FPSCR, maintain 8-byte alignment + "VSTMDB SP!,{D0-D15};" + "VSTMDB SP!,{D16-D31};" + : + : + : ); + return; +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_neon_pop(void) +{ + __asm__ volatile ( + ".ARM;" + + "VLDMIA SP!,{D16-D31};" + "VLDMIA SP!,{D0-D15};" + "LDR R2,[SP];" + "VMSR FPSCR,R2;" + "ADD SP,SP,#8;" + : + : + : ); + return; +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_push(void) +{ + __asm__ volatile ( + ".ARM;" + + "VMRS R2,FPSCR;" + "STMDB SP!,{R2,R4};" // Push FPSCR, maintain 8-byte alignment + "VSTMDB SP!,{D0-D15};" + : + : + : ); + return; +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __vfp_pop(void) +{ + __asm__ volatile ( + ".ARM;" + + "VLDMIA SP!,{D0-D15};" + "LDR R2,[SP];" + "VMSR FPSCR,R2;" + "ADD SP,SP,#8;" + : + : + : ); + return; +} + +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/flash_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/flash_api.c new file mode 100644 index 0000000..eb937f0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/flash_api.c @@ -0,0 +1,1125 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH +#include +#include "iodefine.h" +#include "iobitmask.h" +#include "mbed_drv_cfg.h" + +#if defined(__ICCARM__) +#define RAM_CODE_SEC __ramfunc +#else +#define RAM_CODE_SEC __attribute__((section("RAM_CODE"))) +#endif + +static RAM_CODE_SEC void cache_control(void); + +#if defined(USE_SERIAL_FLASH) +#include "spibsc.h" + +/* ---- serial flash command ---- */ +#if (FLASH_SIZE > 0x1000000) +#define SPIBSC_OUTPUT_ADDR SPIBSC_OUTPUT_ADDR_32 +#define SFLASHCMD_SECTOR_ERASE (0x21u) /* SE4B 4-byte address(1bit) */ +#define SFLASHCMD_PAGE_PROGRAM (0x12u) /* PP4B 4-byte address(1bit), data(1bit) */ +#else +#define SPIBSC_OUTPUT_ADDR SPIBSC_OUTPUT_ADDR_24 +#define SFLASHCMD_SECTOR_ERASE (0x20u) /* SE 3-byte address(1bit) */ +#define SFLASHCMD_PAGE_PROGRAM (0x02u) /* PP 3-byte address(1bit), data(1bit) */ +#endif +#define SFLASHCMD_READ_STATUS_REG (0x05u) /* RDSR data(1bit) */ +#define SFLASHCMD_WRITE_ENABLE (0x06u) /* WREN */ +/* ---- serial flash register definitions ---- */ +#define STREG_BUSY_BIT (0x01u) /* SR.[0]BUSY Erase/Write In Progress (RO) */ + +/* Definition of the base address for the MMU translation table */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +extern uint32_t Image$$TTB$$ZI$$Base; +#define TTB ((uint32_t)&Image$$TTB$$ZI$$Base) /* using linker symbol */ +#elif defined(__ICCARM__) +#pragma section="TTB" +#define TTB ((uint32_t)__section_begin("TTB")) +#endif + +typedef struct { + uint32_t cdb; /* bit-width : command */ + uint32_t ocdb; /* bit-width : optional command */ + uint32_t adb; /* bit-width : address */ + uint32_t opdb; /* bit-width : option data */ + uint32_t spidb; /* bit-width : data */ + + uint32_t cde; /* Enable : command */ + uint32_t ocde; /* Enable : optional command */ + uint32_t ade; /* Enable : address */ + uint32_t opde; /* Enable : option data */ + uint32_t spide; /* Enable : data */ + + uint32_t sslkp; /* SPBSSL level */ + uint32_t spire; /* Enable data read */ + uint32_t spiwe; /* Enable data write */ + + uint32_t dme; /* Enable : dummy cycle */ + + uint32_t addre; /* DDR enable : address */ + uint32_t opdre; /* DDR enable : option data */ + uint32_t spidre; /* DDR enable : data */ + + uint8_t dmdb; /* bit-width : dummy cycle */ + uint8_t dmcyc; /* number of dummy cycles */ + + uint8_t cmd; /* command */ + uint8_t ocmd; /* optional command */ + uint32_t addr; /* address */ + uint8_t opd[4]; /* option data 3/2/1/0 */ + uint32_t smrdr[2]; /* read data */ + uint32_t smwdr[2]; /* write data */ +} st_spibsc_spimd_reg_t; + +typedef struct { + uint32_t b0 : 1 ; /* bit 0 : - (0) */ + uint32_t b1 : 1 ; /* bit 1 : - (1) */ + uint32_t B : 1 ; /* bit 2 : B Memory region attribute bit */ + uint32_t C : 1 ; /* bit 3 : C Memory region attribute bit */ + uint32_t XN : 1 ; /* bit 4 : XN Execute-never bit */ + uint32_t Domain : 4 ; /* bit 8-5 : Domain Domain field */ + uint32_t b9 : 1 ; /* bit 9 : IMP IMPLEMENTATION DEFINED */ + uint32_t AP1_0 : 2 ; /* bit 11-10 : AP[1:0] Access permissions bits:bit1-0 */ + uint32_t TEX : 3 ; /* bit 14-12 : TEX[2:0] Memory region attribute bits */ + uint32_t AP2 : 1 ; /* bit 15 : AP[2] Access permissions bits:bit2 */ + uint32_t S : 1 ; /* bit 16 : S Shareable bit */ + uint32_t nG : 1 ; /* bit 17 : nG Not global bit */ + uint32_t b18 : 1 ; /* bit 18 : - (0) */ + uint32_t NS : 1 ; /* bit 19 : NS Non-secure bit */ + uint32_t base_addr : 12; /* bit 31-20 : PA[31:20] PA(physical address) bits:bit31-20 */ +} mmu_ttbl_desc_section_t; + +static mmu_ttbl_desc_section_t desc_tbl[(FLASH_SIZE >> 20)]; +static st_spibsc_spimd_reg_t spimd_reg; +static uint8_t write_tmp_buf[FLASH_PAGE_SIZE]; + +/* Global function for optimization */ +RAM_CODE_SEC int32_t _sector_erase(uint32_t addr); +RAM_CODE_SEC int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size); + +static RAM_CODE_SEC int32_t write_enable(void); +static RAM_CODE_SEC int32_t busy_wait(void); +static RAM_CODE_SEC int32_t read_register(uint8_t cmd, uint8_t * status); +static RAM_CODE_SEC int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size); +static RAM_CODE_SEC void spi_mode(void); +static RAM_CODE_SEC void ex_mode(void); +static RAM_CODE_SEC void clear_spimd_reg(volatile st_spibsc_spimd_reg_t * regset); +static RAM_CODE_SEC int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset); +static RAM_CODE_SEC uint32_t RegRead_32(volatile unsigned long * ioreg, uint32_t shift, uint32_t mask); +static RAM_CODE_SEC void RegWwrite_32(volatile unsigned long * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask); +static RAM_CODE_SEC void change_mmu_ttbl_spibsc(uint32_t type); +static RAM_CODE_SEC void spibsc_stop(void); + +int32_t _sector_erase(uint32_t addr) +{ + int32_t ret; + + core_util_critical_section_enter(); + spi_mode(); + + /* ---- Write enable ---- */ + ret = write_enable(); /* WREN Command */ + if (ret != 0) { + ex_mode(); + core_util_critical_section_exit(); + return ret; + } + + /* ---- spimd_reg init ---- */ + clear_spimd_reg(&spimd_reg); + + /* ---- command ---- */ + spimd_reg.cde = SPIBSC_OUTPUT_ENABLE; + spimd_reg.cdb = SPIBSC_1BIT; + spimd_reg.cmd = SFLASHCMD_SECTOR_ERASE; + + /* ---- address ---- */ + spimd_reg.ade = SPIBSC_OUTPUT_ADDR; + spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */ + spimd_reg.adb = SPIBSC_1BIT; + spimd_reg.addr = addr; + + ret = spibsc_transfer(&spimd_reg); + if (ret != 0) { + ex_mode(); + core_util_critical_section_exit(); + return ret; + } + + ret = busy_wait(); + + ex_mode(); + core_util_critical_section_exit(); + return ret; +} + +int32_t _page_program(uint32_t addr, const uint8_t * buf, int32_t size) +{ + int32_t ret; + int32_t program_size; + int32_t remainder; + int32_t idx = 0; + + while (size > 0) { + if (size > FLASH_PAGE_SIZE) { + program_size = FLASH_PAGE_SIZE; + } else { + program_size = size; + } + remainder = FLASH_PAGE_SIZE - (addr % FLASH_PAGE_SIZE); + if ((remainder != 0) && (program_size > remainder)) { + program_size = remainder; + } + + core_util_critical_section_enter(); + memcpy(write_tmp_buf, &buf[idx], program_size); + spi_mode(); + + /* ---- Write enable ---- */ + ret = write_enable(); /* WREN Command */ + if (ret != 0) { + ex_mode(); + core_util_critical_section_exit(); + return ret; + } + + /* ----------- 1. Command, Address ---------------*/ + /* ---- spimd_reg init ---- */ + clear_spimd_reg(&spimd_reg); + + /* ---- command ---- */ + spimd_reg.cde = SPIBSC_OUTPUT_ENABLE; + spimd_reg.cdb = SPIBSC_1BIT; + spimd_reg.cmd = SFLASHCMD_PAGE_PROGRAM; + + /* ---- address ---- */ + spimd_reg.ade = SPIBSC_OUTPUT_ADDR; + spimd_reg.addre = SPIBSC_SDR_TRANS; /* SDR */ + spimd_reg.adb = SPIBSC_1BIT; + spimd_reg.addr = addr; + + /* ---- Others ---- */ + spimd_reg.sslkp = SPIBSC_SPISSL_KEEP; /* SPBSSL level */ + + ret = spibsc_transfer(&spimd_reg); /* Command,Address */ + if (ret != 0) { + ex_mode(); + core_util_critical_section_exit(); + return ret; + } + + /* ----------- 2. Data ---------------*/ + ret = data_send(SPIBSC_1BIT, SPIBSC_SPISSL_NEGATE, write_tmp_buf, program_size); + if (ret != 0) { + ex_mode(); + core_util_critical_section_exit(); + return ret; + } + + ret = busy_wait(); + if (ret != 0) { + ex_mode(); + core_util_critical_section_exit(); + return ret; + } + + ex_mode(); + core_util_critical_section_exit(); + + addr += program_size; + idx += program_size; + size -= program_size; + } + + return ret; +} + +static int32_t write_enable(void) +{ + int32_t ret; + + /* ---- spimd_reg init ---- */ + clear_spimd_reg(&spimd_reg); + + /* ---- command ---- */ + spimd_reg.cde = SPIBSC_OUTPUT_ENABLE; + spimd_reg.cdb = SPIBSC_1BIT; + spimd_reg.cmd = SFLASHCMD_WRITE_ENABLE; + + ret = spibsc_transfer(&spimd_reg); + + return ret; +} + +static int32_t busy_wait(void) +{ + int32_t ret; + uint8_t st_reg; + + while (1) { + ret = read_register(SFLASHCMD_READ_STATUS_REG, &st_reg); + if (ret != 0) { + break; + } + if ((st_reg & STREG_BUSY_BIT) == 0) { + break; + } + } + + return ret; +} + +static int32_t read_register(uint8_t cmd, uint8_t * status) +{ + int32_t ret; + + /* ---- spimd_reg init ---- */ + clear_spimd_reg(&spimd_reg); + + /* ---- command ---- */ + spimd_reg.cde = SPIBSC_OUTPUT_ENABLE; + spimd_reg.cdb = SPIBSC_1BIT; + spimd_reg.cmd = cmd; + + /* ---- Others ---- */ + spimd_reg.sslkp = SPIBSC_SPISSL_NEGATE; /* SPBSSL level */ + spimd_reg.spire = SPIBSC_SPIDATA_ENABLE; /* read enable/disable */ + spimd_reg.spiwe = SPIBSC_SPIDATA_ENABLE; /* write enable/disable */ + + /* ---- data ---- */ + spimd_reg.spide = SPIBSC_OUTPUT_SPID_8; /* Enable(8bit) */ + spimd_reg.spidre = SPIBSC_SDR_TRANS; /* SDR */ + spimd_reg.spidb = SPIBSC_1BIT; + spimd_reg.smwdr[0] = 0x00; /* Output 0 in read status */ + spimd_reg.smwdr[1] = 0x00; /* Output 0 in read status */ + + ret = spibsc_transfer(&spimd_reg); + if (ret == 0) { + *status = (uint8_t)(spimd_reg.smrdr[0]); /* Data[7:0] */ + } + + return ret; +} + +static int32_t data_send(uint32_t bit_width, uint32_t spbssl_level, const uint8_t * buf, int32_t size) +{ + int32_t ret = 0; + int32_t unit; + uint8_t *buf_b; + uint16_t *buf_s; + uint32_t *buf_l; + + /* ---- spimd_reg init ---- */ + clear_spimd_reg(&spimd_reg); + + /* ---- Others ---- */ + spimd_reg.sslkp = SPIBSC_SPISSL_KEEP; /* SPBSSL level */ + spimd_reg.spiwe = SPIBSC_SPIDATA_ENABLE; /* write enable/disable */ + + /* ---- data ---- */ + spimd_reg.spidb = bit_width; + spimd_reg.spidre= SPIBSC_SDR_TRANS; /* SDR */ + + if (((uint32_t)size & 0x3) == 0) { + spimd_reg.spide = SPIBSC_OUTPUT_SPID_32; /* Enable(32bit) */ + unit = 4; + } else if (((uint32_t)size & 0x1) == 0) { + spimd_reg.spide = SPIBSC_OUTPUT_SPID_16; /* Enable(16bit) */ + unit = 2; + } else { + spimd_reg.spide = SPIBSC_OUTPUT_SPID_8; /* Enable(8bit) */ + unit = 1; + } + + while (size > 0) { + if (unit == 1) { + buf_b = (uint8_t *)buf; + spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_b) & 0x000000FF); + } else if (unit == 2) { + buf_s = (uint16_t *)buf; + spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)*buf_s) & 0x0000FFFF); + } else if (unit == 4) { + buf_l = (uint32_t *)buf; + spimd_reg.smwdr[0] = (uint32_t)(((uint32_t)(*buf_l)) & 0xfffffffful); + } else { + /* Do Nothing */ + } + + buf += unit; + size -= unit; + + if (size <= 0) { + spimd_reg.sslkp = spbssl_level; + } + + ret = spibsc_transfer(&spimd_reg); /* Data */ + if (ret != 0) { + return ret; + } + } + + return ret; +} + +static void spi_mode(void) +{ + volatile uint32_t dummy_read_32; + + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) { + /* ==== Change the MMU translation table SPI Multi-I/O bus space settings + for use in SPI operating mode ==== */ + change_mmu_ttbl_spibsc(0); + + /* ==== Cleaning and invalidation of cache ==== */ + cache_control(); + + /* ==== Switch to SPI operating mode ==== */ + spibsc_stop(); + + dummy_read_32 = SPIBSC.CMNCR.LONG; /* dummy read */ + /* SPI Mode */ + RegWwrite_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD); + dummy_read_32 = SPIBSC.CMNCR.LONG; /* dummy read */ + + } + (void)dummy_read_32; +} + +static void ex_mode(void) +{ + volatile uint32_t dummy_read_32; + + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_EXTRD) { + /* ==== Switch to external address space read mode and clear SPIBSC read cache ==== */ + spibsc_stop(); + + /* Flush SPIBSC's read cache */ + RegWwrite_32(&SPIBSC.DRCR.LONG, SPIBSC_DRCR_RCF_EXE, SPIBSC_DRCR_RCF_SHIFT, SPIBSC_DRCR_RCF); + dummy_read_32 = SPIBSC.DRCR.LONG; /* dummy read */ + + /* External address space read mode */ + RegWwrite_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_MD_EXTRD, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD); + dummy_read_32 = SPIBSC.CMNCR.LONG; /* dummy read */ + + /* ==== Change the MMU translation table SPI Multi-I/O bus space settings + for use in external address space read mode ==== */ + change_mmu_ttbl_spibsc(1); + + /* ==== Cleaning and invalidation of cache ==== */ + cache_control(); + } + (void)dummy_read_32; +} + +static void clear_spimd_reg(volatile st_spibsc_spimd_reg_t * regset) +{ + /* ---- command ---- */ + regset->cde = SPIBSC_OUTPUT_DISABLE; + regset->cdb = SPIBSC_1BIT; + regset->cmd = 0x00; + + /* ---- optional command ---- */ + regset->ocde = SPIBSC_OUTPUT_DISABLE; + regset->ocdb = SPIBSC_1BIT; + regset->ocmd = 0x00; + + /* ---- address ---- */ + regset->ade = SPIBSC_OUTPUT_DISABLE; + regset->addre = SPIBSC_SDR_TRANS; /* SDR */ + regset->adb = SPIBSC_1BIT; + regset->addr = 0x00000000; + + /* ---- option data ---- */ + regset->opde = SPIBSC_OUTPUT_DISABLE; + regset->opdre = SPIBSC_SDR_TRANS; /* SDR */ + regset->opdb = SPIBSC_1BIT; + regset->opd[0] = 0x00; /* OPD3 */ + regset->opd[1] = 0x00; /* OPD2 */ + regset->opd[2] = 0x00; /* OPD1 */ + regset->opd[3] = 0x00; /* OPD0 */ + + /* ---- dummy cycle ---- */ + regset->dme = SPIBSC_DUMMY_CYC_DISABLE; + regset->dmdb = SPIBSC_1BIT; + regset->dmcyc = SPIBSC_DUMMY_1CYC; + + /* ---- data ---- */ + regset->spide = SPIBSC_OUTPUT_DISABLE; + regset->spidre = SPIBSC_SDR_TRANS; /* SDR */ + regset->spidb = SPIBSC_1BIT; + + /* ---- Others ---- */ + regset->sslkp = SPIBSC_SPISSL_NEGATE; /* SPBSSL level */ + regset->spire = SPIBSC_SPIDATA_DISABLE; /* read enable/disable */ + regset->spiwe = SPIBSC_SPIDATA_DISABLE; /* write enable/disable */ +} + +static int32_t spibsc_transfer(st_spibsc_spimd_reg_t * regset) +{ + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD) != SPIBSC_CMNCR_MD_SPI) { + if (RegRead_32(&SPIBSC.CMNSR.LONG, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) { + return -1; + } + /* SPI Mode */ + RegWwrite_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_MD_SPI, SPIBSC_CMNCR_MD_SHIFT, SPIBSC_CMNCR_MD); + } + + if (RegRead_32(&SPIBSC.CMNSR.LONG, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) { + return -1; + } + + /* ---- Command ---- */ + /* Enable/Disable */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->cde, SPIBSC_SMENR_CDE_SHIFT, SPIBSC_SMENR_CDE); + if (regset->cde != SPIBSC_OUTPUT_DISABLE) { + /* Command */ + RegWwrite_32(&SPIBSC.SMCMR.LONG, regset->cmd, SPIBSC_SMCMR_CMD_SHIFT, SPIBSC_SMCMR_CMD); + /* Single/Dual/Quad */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->cdb, SPIBSC_SMENR_CDB_SHIFT, SPIBSC_SMENR_CDB); + } + + /* ---- Option Command ---- */ + /* Enable/Disable */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->ocde, SPIBSC_SMENR_OCDE_SHIFT, SPIBSC_SMENR_OCDE); + if (regset->ocde != SPIBSC_OUTPUT_DISABLE) { + /* Option Command */ + RegWwrite_32(&SPIBSC.SMCMR.LONG, regset->ocmd, SPIBSC_SMCMR_OCMD_SHIFT, SPIBSC_SMCMR_OCMD); + /* Single/Dual/Quad */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->ocdb, SPIBSC_SMENR_OCDB_SHIFT, SPIBSC_SMENR_OCDB); + } + + /* ---- Address ---- */ + /* Enable/Disable */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->ade, SPIBSC_SMENR_ADE_SHIFT, SPIBSC_SMENR_ADE); + if (regset->ade != SPIBSC_OUTPUT_DISABLE) { + /* Address */ + RegWwrite_32(&SPIBSC.SMADR.LONG, regset->addr, SPIBSC_SMADR_ADR_SHIFT, SPIBSC_SMADR_ADR); + /* Single/Dual/Quad */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->adb, SPIBSC_SMENR_ADB_SHIFT, SPIBSC_SMENR_ADB); + } + + /* ---- Option Data ---- */ + /* Enable/Disable */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->opde, SPIBSC_SMENR_OPDE_SHIFT, SPIBSC_SMENR_OPDE); + if (regset->opde != SPIBSC_OUTPUT_DISABLE) { + /* Option Data */ + RegWwrite_32(&SPIBSC.SMOPR.LONG, regset->opd[0], SPIBSC_SMOPR_OPD3_SHIFT, SPIBSC_SMOPR_OPD3); + RegWwrite_32(&SPIBSC.SMOPR.LONG, regset->opd[1], SPIBSC_SMOPR_OPD2_SHIFT, SPIBSC_SMOPR_OPD2); + RegWwrite_32(&SPIBSC.SMOPR.LONG, regset->opd[2], SPIBSC_SMOPR_OPD1_SHIFT, SPIBSC_SMOPR_OPD1); + RegWwrite_32(&SPIBSC.SMOPR.LONG, regset->opd[3], SPIBSC_SMOPR_OPD0_SHIFT, SPIBSC_SMOPR_OPD0); + /* Single/Dual/Quad */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->opdb, SPIBSC_SMENR_OPDB_SHIFT, SPIBSC_SMENR_OPDB); + } + + /* ---- Dummy ---- */ + /* Enable/Disable */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->dme, SPIBSC_SMENR_DME_SHIFT, SPIBSC_SMENR_DME); + if (regset->dme != SPIBSC_DUMMY_CYC_DISABLE) { + /* Dummy Cycle */ + RegWwrite_32(&SPIBSC.SMDMCR.LONG, regset->dmcyc, SPIBSC_SMDMCR_DMCYC_SHIFT, SPIBSC_SMDMCR_DMCYC); + } + + /* ---- Data ---- */ + /* Enable/Disable */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->spide, SPIBSC_SMENR_SPIDE_SHIFT, SPIBSC_SMENR_SPIDE); + if (regset->spide != SPIBSC_OUTPUT_DISABLE) { + if (SPIBSC_OUTPUT_SPID_8 == regset->spide) { + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) { + SPIBSC.SMWDR0.BYTE.LL = (uint8_t)(regset->smwdr[0]); + } else { + SPIBSC.SMWDR0.WORD.L = (uint16_t)(regset->smwdr[0]); + } + } else if (regset->spide == SPIBSC_OUTPUT_SPID_16) { + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) { + SPIBSC.SMWDR0.WORD.L = (uint16_t)(regset->smwdr[0]); + } else { + SPIBSC.SMWDR0.LONG = regset->smwdr[0]; + } + } else if (regset->spide == SPIBSC_OUTPUT_SPID_32) { + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) { + SPIBSC.SMWDR0.LONG = (uint32_t)(regset->smwdr[0]); + } else { + SPIBSC.SMWDR0.LONG = (uint32_t)(regset->smwdr[0]); + SPIBSC.SMWDR1.LONG = (uint32_t)(regset->smwdr[1]); /* valid in two serial-flash */ + } + } else { + /* none */ + } + + /* Single/Dual/Quad */ + RegWwrite_32(&SPIBSC.SMENR.LONG, regset->spidb, SPIBSC_SMENR_SPIDB_SHIFT, SPIBSC_SMENR_SPIDB); + } + + RegWwrite_32(&SPIBSC.SMCR.LONG, regset->sslkp, SPIBSC_SMCR_SSLKP_SHIFT, SPIBSC_SMCR_SSLKP); + + if ((regset->spidb != SPIBSC_1BIT) && (regset->spide != SPIBSC_OUTPUT_DISABLE)) { + if ((regset->spire == SPIBSC_SPIDATA_ENABLE) && (regset->spiwe == SPIBSC_SPIDATA_ENABLE)) { + /* not set in same time */ + return -1; + } + } + + RegWwrite_32(&SPIBSC.SMCR.LONG, regset->spire, SPIBSC_SMCR_SPIRE_SHIFT, SPIBSC_SMCR_SPIRE); + RegWwrite_32(&SPIBSC.SMCR.LONG, regset->spiwe, SPIBSC_SMCR_SPIWE_SHIFT, SPIBSC_SMCR_SPIWE); + + /* SDR Transmission/DDR Transmission Setting */ + RegWwrite_32(&SPIBSC.SMDRENR.LONG, regset->addre, SPIBSC_SMDRENR_ADDRE_SHIFT, SPIBSC_SMDRENR_ADDRE); + RegWwrite_32(&SPIBSC.SMDRENR.LONG, regset->opdre, SPIBSC_SMDRENR_OPDRE_SHIFT, SPIBSC_SMDRENR_OPDRE); + RegWwrite_32(&SPIBSC.SMDRENR.LONG, regset->spidre, SPIBSC_SMDRENR_SPIDRE_SHIFT, SPIBSC_SMDRENR_SPIDRE); + + /* execute after setting SPNDL bit */ + RegWwrite_32(&SPIBSC.SMCR.LONG, SPIBSC_SPI_ENABLE, SPIBSC_SMCR_SPIE_SHIFT, SPIBSC_SMCR_SPIE); + + /* wait for transfer-start */ + while (RegRead_32(&SPIBSC.CMNSR.LONG, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) { + /* wait for transfer-end */ + } + + if (SPIBSC_OUTPUT_SPID_8 == regset->spide) { + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) { + regset->smrdr[0] = SPIBSC.SMRDR0.BYTE.LL; + } else { + regset->smrdr[0] = SPIBSC.SMRDR0.WORD.L; /* valid in two serial-flash */ + } + } else if (regset->spide == SPIBSC_OUTPUT_SPID_16) { + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) { + regset->smrdr[0] = SPIBSC.SMRDR0.WORD.L; + } else { + regset->smrdr[0] = SPIBSC.SMRDR0.LONG; /* valid in two serial-flash */ + } + } else if (regset->spide == SPIBSC_OUTPUT_SPID_32) { + if (RegRead_32(&SPIBSC.CMNCR.LONG, SPIBSC_CMNCR_BSZ_SHIFT, SPIBSC_CMNCR_BSZ) == SPIBSC_CMNCR_BSZ_SINGLE) { + regset->smrdr[0] = SPIBSC.SMRDR0.LONG; + } else { + regset->smrdr[0] = SPIBSC.SMRDR0.LONG; /* valid in two serial-flash */ + regset->smrdr[1] = SPIBSC.SMRDR1.LONG; + } + } else { + /* none */ + } + + return 0; +} + +static uint32_t RegRead_32(volatile unsigned long * ioreg, uint32_t shift, uint32_t mask) +{ + uint32_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & mask) >> shift; /* Clear other bit and Bit shift */ + + return reg_value; +} + +static void RegWwrite_32(volatile unsigned long * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) +{ + uint32_t reg_value; + + reg_value = *ioreg; /* Read from register */ + reg_value = (reg_value & (~mask)) | (write_value << shift); /* Modify value */ + *ioreg = reg_value; /* Write to register */ +} + +static void change_mmu_ttbl_spibsc(uint32_t type) +{ + uint32_t index; /* Loop variable: table index */ + mmu_ttbl_desc_section_t desc; /* Loop variable: descriptor */ + mmu_ttbl_desc_section_t * table = (mmu_ttbl_desc_section_t *)TTB; + + /* ==== Modify SPI Multi-I/O bus space settings in the MMU translation table ==== */ + for (index = (FLASH_BASE >> 20); index < ((FLASH_BASE + FLASH_SIZE) >> 20); index++) { + /* Modify memory attribute descriptor */ + if (type == 0) { /* Spi */ + desc = table[index]; + desc_tbl[index - (FLASH_BASE >> 20)] = desc; + desc.AP1_0 = 0x0u; /* AP[2:0] = b'000 (No access) */ + desc.AP2 = 0x0u; + desc.XN = 0x1u; /* XN = 1 (Execute never) */ + } else { /* Xip */ + desc = desc_tbl[index - (FLASH_BASE >> 20)]; + } + /* Write descriptor back to translation table */ + table[index] = desc; + } +} + +static void spibsc_stop(void) +{ + if (((SPIBSC.DRCR.LONG & SPIBSC_DRCR_RBE) != 0) && + ((SPIBSC.DRCR.LONG & SPIBSC_DRCR_SSLE) != 0)) { + RegWwrite_32(&SPIBSC.DRCR.LONG, 1, SPIBSC_DRCR_SSLN_SHIFT, SPIBSC_DRCR_SSLN); + } + + while (RegRead_32(&SPIBSC.CMNSR.LONG, SPIBSC_CMNSR_SSLF_SHIFT, SPIBSC_CMNSR_SSLF) != SPIBSC_SSL_NEGATE) { + ; + } + + while (RegRead_32(&SPIBSC.CMNSR.LONG, SPIBSC_CMNSR_TEND_SHIFT, SPIBSC_CMNSR_TEND) != SPIBSC_TRANS_END) { + ; + } +} +#endif /* USE_SERIAL_FLASH */ + + +#if defined(USE_HYPERFLASH) +RAM_CODE_SEC int32_t _hyperflash_sector_erase(uint32_t addr); +RAM_CODE_SEC int32_t _hyperflash_page_program(uint32_t addr, const uint8_t * buf, int32_t size); + +static RAM_CODE_SEC void hyperflash_commandwrite(uint32_t caddr, uint16_t write_value); +static RAM_CODE_SEC void hyperflash_datawrite(uint32_t offset, uint16_t write_value); +static RAM_CODE_SEC uint16_t hyperflash_readstatus(void); +static RAM_CODE_SEC void hyperflash_write_word(uint32_t waddr, uint16_t wdata); + +int32_t _hyperflash_sector_erase(uint32_t addr) +{ + int32_t ret = 0; + uint16_t read_sr; + + core_util_critical_section_enter(); + + /** Word program sequence */ + hyperflash_commandwrite(0x555, 0x00AA); /** 1st bus cycle */ + hyperflash_commandwrite(0x2AA, 0x0055); /** 2nd bus cycle */ + hyperflash_commandwrite(0x555, 0x0080); /** 3rd bus cycle */ + hyperflash_commandwrite(0x555, 0x00AA); /** 4th bus cycle */ + hyperflash_commandwrite(0x2AA, 0x0055); /** 5th bus cycle */ + hyperflash_datawrite(addr, 0x0030); /** 6th bus cycle */ + + /** Wait for device ready asserted */ + while (1) { + /** Read status regster */ + read_sr = hyperflash_readstatus(); + if ((read_sr & 0x80) != 0) { + break; + } + } + + /** Evaluate erase status */ + hyperflash_commandwrite(0x555, 0x00D0); /** 1st bus cycle */ + + /** Wait for device ready asserted */ + while (1) { + /** Read status regster */ + read_sr = hyperflash_readstatus(); + if ((read_sr & 0x80) != 0) { + break; + } + } + + /** Sector erase error check */ + if ((read_sr & 0x01) == 0) { + ret = -1; /** erase error occured */ + } + + cache_control(); + core_util_critical_section_exit(); + + return ret; +} + +int32_t _hyperflash_page_program(uint32_t addr, const uint8_t * buf, int32_t size) +{ + uint16_t send_data; + uint32_t send_addr = addr; + int32_t idx = 0; + + /* Size check */ + if (size < 0) { + return -1; + } + if (size == 0) { + return 0; + } + + core_util_critical_section_enter(); + + /* Odd address */ + if ((send_addr & 0x1) != 0) { + send_addr -= 1; + send_data = (buf[idx] << 8) + (*(uint8_t *)send_addr); + idx += 1; + hyperflash_write_word(send_addr, send_data); + send_addr += 2; + } + + /* Write loop */ + while ((idx + 1) < size) { + send_data = (buf[idx + 1] << 8) + buf[idx]; + idx += 2; + hyperflash_write_word(send_addr, send_data); + send_addr += 2; + } + + /* Odd size */ + if (idx < size) { + send_data = (0xFF << 8) + buf[idx]; + hyperflash_write_word(send_addr, send_data); + } + + cache_control(); + core_util_critical_section_exit(); + + return 0; +} + +static void hyperflash_commandwrite(uint32_t caddr, uint16_t write_value) +{ + *(volatile uint16_t *)(RZ_A2_HYPER_FLASH_IO + (caddr << 1)) = write_value; +} + +static void hyperflash_datawrite(uint32_t offset, uint16_t write_value) +{ + *(volatile uint16_t *)(RZ_A2_HYPER_FLASH_IO + offset) = write_value; +} + +static uint16_t hyperflash_readstatus(void) +{ + uint16_t read_sr; + + hyperflash_commandwrite(0x555, 0x0070); /** 1st bus cycle */ + read_sr = *(volatile uint16_t *)(RZ_A2_HYPER_FLASH_IO); /** 2nd bus cycle */ + + return read_sr; +} + +static void hyperflash_write_word(uint32_t waddr, uint16_t wdata) +{ + uint16_t read_sr; + + /** Word program sequence */ + hyperflash_commandwrite(0x555, 0x00AA); /** 1st bus cycle */ + hyperflash_commandwrite(0x2AA, 0x0055); /** 2nd bus cycle */ + hyperflash_commandwrite(0x555, 0x00A0); /** 3rd bus cycle */ + hyperflash_datawrite(waddr, wdata); /** 4th bus cycle */ + + /** Wait for device ready asserted */ + while (1) { + /** Read status regster */ + read_sr = hyperflash_readstatus(); + if ((read_sr & 0x80) != 0) { + break; + } + } +} +#endif /* USE_HYPERFLASH */ + + +#if defined(USE_OCTAFLASH) +#define OFLASH_STATUS_WIP (0x00000001u) +#define OCTACFG_BUS_WIDTH 32 + +RAM_CODE_SEC int32_t _octaflash_sector_erase(uint32_t addr); +RAM_CODE_SEC int32_t _octaflash_page_program(uint32_t addr, const uint8_t * buf, int32_t size); + +static RAM_CODE_SEC void octaflash_wren(void); +static RAM_CODE_SEC uint32_t octaflash_rdsr(void); + +int32_t _octaflash_sector_erase(uint32_t addr) +{ + core_util_critical_section_enter(); + + /* ---- Write Enable ---- */ + octaflash_wren(); + + /* ---- Controller and device setting register ---- */ + OCTA.CDSR.BIT.DLFT = 1; + OCTA.CDSR.BIT.DV0TTYP = 2; /* DOPI */ + + /* ---- Device command register ---- */ + OCTA.DCR.BIT.DVCMD1 = 0x21; + OCTA.DCR.BIT.DVCMD0 = 0xDE; + + /* ---- Device address register ---- */ + OCTA.DAR.LONG = addr; + + /* ---- Device command setting register ---- */ + OCTA.DCSR.BIT.ACDA = 1; + OCTA.DCSR.BIT.DOPI = 0; + OCTA.DCSR.BIT.ADLEN = 4; + OCTA.DCSR.BIT.DAOR = 1; + OCTA.DCSR.BIT.CMDLEN = 2; + OCTA.DCSR.BIT.ACDV = 0; + OCTA.DCSR.BIT.DMLEN = 0; + OCTA.DCSR.BIT.DALEN = 0; + + /* ---- Configure write without data register ---- */ + OCTA.CWNDR = 0x00000000; + + while (octaflash_rdsr() & OFLASH_STATUS_WIP); + + core_util_critical_section_exit(); + + /* ==== Cleaning and invalidation of cache ==== */ + cache_control(); + + return 0; +} + +int32_t _octaflash_page_program(uint32_t addr, const uint8_t * buf, int32_t size) +{ + int32_t program_size; + int32_t remainder; + + while (size > 0) { + if (size > OCTAFLASH_PAGE_SIZE) { + program_size = OCTAFLASH_PAGE_SIZE; + } else { + program_size = size; + } + remainder = OCTAFLASH_PAGE_SIZE - (addr % OCTAFLASH_PAGE_SIZE); + if ((remainder != 0) && (program_size > remainder)) { + program_size = remainder; + } + if (program_size > OCTACFG_BUS_WIDTH) { + program_size = OCTACFG_BUS_WIDTH; + } + + core_util_critical_section_enter(); + + /* ---- Write Enable ---- */ + octaflash_wren(); + + for (int32_t i = 0; i < program_size; i++) { + *(volatile uint8_t*)(RZ_A2_OCTA_FLASH_NC + addr + i) = *(buf + i); + } + + while (octaflash_rdsr() & OFLASH_STATUS_WIP); + + core_util_critical_section_exit(); + + size -= program_size; + addr += program_size; + buf += program_size; + } + + /* ==== Cleaning and invalidation of cache ==== */ + cache_control(); + + return 0; +} + +static void octaflash_wren(void) +{ + /* ---- Controller and device setting register ---- */ + OCTA.CDSR.BIT.DLFT = 1; + OCTA.CDSR.BIT.DV0TTYP = 2; /* DOPI */ + + /* ---- Device command register ---- */ + OCTA.DCR.BIT.DVCMD1 = 0x06; + OCTA.DCR.BIT.DVCMD0 = 0xF9; + + /* ---- Device command setting register ---- */ + OCTA.DCSR.BIT.ACDA = 0; + OCTA.DCSR.BIT.DOPI = 1; + OCTA.DCSR.BIT.ADLEN = 0; + OCTA.DCSR.BIT.DAOR = 0; + OCTA.DCSR.BIT.CMDLEN = 2; + OCTA.DCSR.BIT.ACDV = 0; + OCTA.DCSR.BIT.DMLEN = 0; + OCTA.DCSR.BIT.DALEN = 0; + + /* ---- Configure write without data register ---- */ + OCTA.CWNDR = 0x00000000; +} + +static uint32_t octaflash_rdsr(void) +{ + uint32_t status; + + /* ---- Controller and device setting register ---- */ + OCTA.CDSR.BIT.DLFT = 1; + OCTA.CDSR.BIT.DV0TTYP = 2; /* DOPI */ + + /* ---- Device command register ---- */ + OCTA.DCR.BIT.DVCMD1 = 0x05; + OCTA.DCR.BIT.DVCMD0 = 0xFA; + + /* ---- Device address register ---- */ + OCTA.DAR.LONG = 0x00000000; + + /* ---- Device command setting register ---- */ + OCTA.DCSR.BIT.ACDA = 0; + OCTA.DCSR.BIT.DOPI = 1; + OCTA.DCSR.BIT.ADLEN = 4; + OCTA.DCSR.BIT.DAOR = 0; + OCTA.DCSR.BIT.CMDLEN = 2; + OCTA.DCSR.BIT.ACDV = 0; + OCTA.DCSR.BIT.DMLEN = 4; + OCTA.DCSR.BIT.DALEN = 1; + + /* ---- Configure read register ---- */ + status = OCTA.CRR.LONG; + + return status; +} + +#endif /* USE_OCTAFLASH */ + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ +#if defined(USE_OCTAFLASH) + if ((address >= OCTAFLASH_BASE) && (address < (OCTAFLASH_BASE + OCTAFLASH_SIZE))) { + return _octaflash_sector_erase(address - OCTAFLASH_BASE); + } +#endif /* USE_OCTAFLASH */ +#if defined(USE_HYPERFLASH) + if ((address >= HYPERFLASH_BASE) && (address < (HYPERFLASH_BASE + HYPERFLASH_SIZE))) { + return _hyperflash_sector_erase(address - HYPERFLASH_BASE); + } +#endif /* USE_HYPERFLASH */ +#if defined(USE_SERIAL_FLASH) + if ((address >= FLASH_BASE) && (address < (FLASH_BASE + FLASH_SIZE))) { + return _sector_erase(address - FLASH_BASE); + } +#endif /* USE_SERIAL_FLASH */ + return -1; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ +#if defined(USE_OCTAFLASH) + if ((address >= OCTAFLASH_BASE) && (address < (OCTAFLASH_BASE + OCTAFLASH_SIZE))) { + return _octaflash_page_program(address - OCTAFLASH_BASE, data, size); + } +#endif /* USE_OCTAFLASH */ +#if defined(USE_HYPERFLASH) + if ((address >= HYPERFLASH_BASE) && (address < (HYPERFLASH_BASE + HYPERFLASH_SIZE))) { + return _hyperflash_page_program(address - HYPERFLASH_BASE, data, size); + } +#endif /* USE_HYPERFLASH */ +#if defined(USE_SERIAL_FLASH) + if ((address >= FLASH_BASE) && (address < (FLASH_BASE + FLASH_SIZE))) { + return _page_program(address - FLASH_BASE, data, size); + } +#endif /* USE_SERIAL_FLASH */ + return -1; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ +#if defined(USE_OCTAFLASH) + if ((address >= OCTAFLASH_BASE) && (address < (OCTAFLASH_BASE + OCTAFLASH_SIZE))) { + return OCTAFLASH_SECTOR_SIZE; + } +#endif /* USE_OCTAFLASH */ +#if defined(USE_HYPERFLASH) + if ((address >= HYPERFLASH_BASE) && (address < (HYPERFLASH_BASE + HYPERFLASH_SIZE))) { + return HYPERFLASH_SECTOR_SIZE; + } +#endif /* USE_HYPERFLASH */ +#if defined(USE_SERIAL_FLASH) + if ((address >= FLASH_BASE) && (address < (FLASH_BASE + FLASH_SIZE))) { + return FLASH_SECTOR_SIZE; + } +#endif /* USE_SERIAL_FLASH */ + return MBED_FLASH_INVALID_SIZE; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ +#if defined(USE_OCTAFLASH) + return OCTAFLASH_PAGE_SIZE; +#else /* USE_OCTAFLASH */ + return 8; +#endif /* USE_OCTAFLASH */ +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ +#if defined(USE_HYPERFLASH) && defined(USE_SERIAL_FLASH) + return FLASH_BASE; +#elif defined(USE_SERIAL_FLASH) + return FLASH_BASE; +#elif defined(USE_HYPERFLASH) + return HYPERFLASH_BASE; +#elif defined(USE_OCTAFLASH) + return OCTAFLASH_BASE; +#else + return 0; +#endif +} + +uint32_t flash_get_size(const flash_t *obj) +{ +#if defined(USE_HYPERFLASH) && defined(USE_SERIAL_FLASH) + return 0x10000000 + HYPERFLASH_SIZE; +#elif defined(USE_SERIAL_FLASH) + return FLASH_SIZE; +#elif defined(USE_HYPERFLASH) + return HYPERFLASH_SIZE; +#elif defined(USE_OCTAFLASH) + return OCTAFLASH_SIZE; +#else + return 0; +#endif +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + +static void cache_control(void) +{ + unsigned int assoc; + + /* ==== Cleaning and invalidation of the L1 data cache ==== */ + L1C_CleanInvalidateDCacheAll(); + __DSB(); + + /* ==== Cleaning and invalidation of the L2 cache ==== */ + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while (L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); // poll invalidate + L2C_310->CACHE_SYNC = 0x0; + + /* ==== Invalidate all TLB entries ==== */ + __set_TLBIALL(0); + __DSB(); // ensure completion of the invalidation + __ISB(); // ensure instruction fetch path sees new state + + /* ==== Invalidate the L1 instruction cache ==== */ + __set_ICIALLU(0); + __DSB(); // ensure completion of the invalidation + __ISB(); // ensure instruction fetch path sees new I cache state +} + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_addrdefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_addrdefine.h new file mode 100644 index 0000000..36a3b38 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_addrdefine.h @@ -0,0 +1,29 @@ +/* Copyright (c) 2018-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __GPIO_ADDRDEFINE__ +#define __GPIO_ADDRDEFINE__ + +#define PORTm_base (0xFCFFE000uL) + +#define PDR(g) (volatile unsigned short *)(PORTm_base + 0x0000 + ((g)*2)) +#define PODR(g) (volatile unsigned char *)(PORTm_base + 0x0040 + ((g)*1)) +#define PIDR(g) (volatile unsigned char *)(PORTm_base + 0x0060 + ((g)*1)) +#define PMR(g) (volatile unsigned char *)(PORTm_base + 0x0080 + ((g)*1)) +#define DSCR(g) (volatile unsigned short *)(PORTm_base + 0x0140 + ((g)*2)) +#define PFS(g,n) (volatile unsigned char *)(PORTm_base + 0x0200 + ((g)*8) + n) + +#endif/*__GPIO_ADDRDEFINE__*/ + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_api.c new file mode 100644 index 0000000..ceb565c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_api.c @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_addrdefine.h" +#include "mbed_drv_cfg.h" + +uint32_t gpio_set(PinName pin) { + pin_function(pin, 0); + return (1 << PINNO(pin)); +} + +void gpio_init(gpio_t *obj, PinName pin) { + uint32_t reg_group = PINGROUP(pin); + + obj->pin = pin; + if (reg_group > GPIO_GROUP_MAX) return; + + obj->mask = gpio_set(pin); + obj->reg_dir = (volatile uint16_t *)PDR(reg_group); + obj->reg_set = (volatile uint8_t *)PODR(reg_group); + obj->reg_in = (volatile uint8_t *)PIDR(reg_group); +} + +void gpio_mode(gpio_t *obj, PinMode mode) { +/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */ +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + switch (direction) { + case PIN_INPUT : + *obj->reg_dir &= ~((uint16_t)(0x3 << (PINNO(obj->pin) * 2))); + *obj->reg_dir |= (0x2 << (PINNO(obj->pin) * 2)); + break; + case PIN_OUTPUT: + *obj->reg_dir |= (0x3 << (PINNO(obj->pin) * 2)); + break; + default: + /* do nothing */ + break; + } +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_irq_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_irq_api.c new file mode 100644 index 0000000..ffdf024 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_irq_api.c @@ -0,0 +1,189 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include + +#include "gpio_irq_api.h" +#include "iodefine.h" +#include "PeripheralPins.h" +#include "cmsis.h" +#include "gpio_addrdefine.h" + +#define CHANNEL_NUM 8 + +static void gpio_irq0(void); +static void gpio_irq1(void); +static void gpio_irq2(void); +static void gpio_irq3(void); +static void gpio_irq4(void); +static void gpio_irq5(void); +static void gpio_irq6(void); +static void gpio_irq7(void); + +static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL}; +static gpio_irq_handler irq_handler; +extern PinName gpio_multi_guard; + +static const IRQHandler irq_tbl[CHANNEL_NUM] = { + &gpio_irq0, + &gpio_irq1, + &gpio_irq2, + &gpio_irq3, + &gpio_irq4, + &gpio_irq5, + &gpio_irq6, + &gpio_irq7, +}; + +static void handle_interrupt_in(int irq_num) { + uint16_t irqs; + uint16_t edge_req; + gpio_irq_t *obj; + gpio_irq_event irq_event; + + irqs = INTC.IRQRR.WORD; + if (irqs & (1 << irq_num)) { + obj = channel_obj[irq_num]; + if (obj != NULL) { + edge_req = ((INTC.ICR1.WORD >> (obj->ch * 2)) & 3); + if (edge_req == 1) { + irq_event = IRQ_FALL; + } else if (edge_req == 2) { + irq_event = IRQ_RISE; + } else { + uint32_t mask = (1 << (obj->pin & 0x0F)); + __I uint8_t *reg_in = (volatile uint8_t *)PIDR(PINGROUP(obj->pin)); + + if ((*reg_in & mask) == 0) { + irq_event = IRQ_FALL; + } else { + irq_event = IRQ_RISE; + } + } + irq_handler(obj->port, irq_event); + } + INTC.IRQRR.WORD &= ~(1 << irq_num); + } +} + +static void gpio_irq0(void) { + handle_interrupt_in(0); +} + +static void gpio_irq1(void) { + handle_interrupt_in(1); +} + +static void gpio_irq2(void) { + handle_interrupt_in(2); +} + +static void gpio_irq3(void) { + handle_interrupt_in(3); +} + +static void gpio_irq4(void) { + handle_interrupt_in(4); +} + +static void gpio_irq5(void) { + handle_interrupt_in(5); +} + +static void gpio_irq6(void) { + handle_interrupt_in(6); +} + +static void gpio_irq7(void) { + handle_interrupt_in(7); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { + int shift; + if (pin == NC) return -1; + + obj->ch = pinmap_peripheral(pin, PinMap_IRQ); + obj->pin = (int)pin ; + obj->port = (int)id ; + + shift = obj->ch*2; + channel_obj[obj->ch] = obj; + irq_handler = handler; + + pinmap_pinout(pin, PinMap_IRQ); + gpio_multi_guard = pin; /* Set multi guard */ + + // INTC settings + InterruptHandlerRegister((IRQn_Type)(IRQ0_IRQn + obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]); + INTC.ICR1.WORD &= ~(0x3 << shift); + GIC_SetPriority((IRQn_Type)(IRQ0_IRQn + obj->ch), 5); + GIC_SetConfiguration((IRQn_Type)(IRQ0_IRQn + obj->ch), 1); + obj->int_enable = 1; + __enable_irq(); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) { + channel_obj[obj->ch] = NULL; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { + int shift = obj->ch*2; + uint16_t val = event == IRQ_RISE ? 2 : + event == IRQ_FALL ? 1 : 0; + uint16_t work_icr_val; + + /* check edge interrupt setting */ + work_icr_val = INTC.ICR1.WORD; + if (enable == 1) { + /* Set interrupt serect */ + work_icr_val |= (val << shift); + } else { + /* Clear interrupt serect */ + work_icr_val &= ~(val << shift); + } + + if ((work_icr_val & (3 << shift)) == 0) { + /* No edge interrupt setting */ + GIC_DisableIRQ((IRQn_Type)(IRQ0_IRQn + obj->ch)); + /* Clear Interrupt flags */ + INTC.IRQRR.WORD &= ~(1 << obj->ch); + INTC.ICR1.WORD = work_icr_val; + } else if (obj->int_enable == 1) { + INTC.ICR1.WORD = work_icr_val; + GIC_EnableIRQ((IRQn_Type)(IRQ0_IRQn + obj->ch)); + } else { + INTC.ICR1.WORD = work_icr_val; + } +} + +void gpio_irq_enable(gpio_irq_t *obj) { + int shift = obj->ch*2; + uint16_t work_icr_val = INTC.ICR1.WORD; + + /* check edge interrupt setting */ + if ((work_icr_val & (3 << shift)) != 0) { + GIC_EnableIRQ((IRQn_Type)(IRQ0_IRQn + obj->ch)); + } + obj->int_enable = 1; +} + +void gpio_irq_disable(gpio_irq_t *obj) { + GIC_DisableIRQ((IRQn_Type)(IRQ0_IRQn + obj->ch)); + obj->int_enable = 0; +} + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_object.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_object.h new file mode 100644 index 0000000..f715e09 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/gpio_object.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + + __IO uint16_t *reg_dir; + __IO uint8_t *reg_set; + __I uint8_t *reg_in; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + if (value != 0) { + *obj->reg_set |= obj->mask; + } else { + *obj->reg_set &= ~obj->mask; + } +} + +static inline int gpio_read(gpio_t *obj) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +static inline int gpio_is_connected(const gpio_t *obj) { + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/i2c_api.c new file mode 100644 index 0000000..8f99b01 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/i2c_api.c @@ -0,0 +1,1162 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_I2C +#include "mbed_assert.h" +#include "dma_api.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "PeripheralPins.h" +#include "r_typedefs.h" + +#include "iodefine.h" +#include "RZ_A2_Init.h" + +#define RIIC_COUNT (4) +static const volatile struct st_riic *RIIC[] = { + &RIIC30, &RIIC31, &RIIC32, &RIIC33 +}; + +/* RIICnCR1 */ +#define CR1_RST (1 << 6) +#define CR1_ICE (1 << 7) + +/* RIICnCR2 */ +#define CR2_ST (1 << 1) +#define CR2_RS (1 << 2) +#define CR2_SP (1 << 3) +#define CR2_TRS (1 << 5) +#define CR2_BBSY (1 << 7) + +/* RIICnMR3 */ +#define MR3_ACKBT (1 << 3) +#define MR3_ACKWP (1 << 4) +#define MR3_WAIT (1 << 6) + +/* RIICnSER */ +#define SER_SAR0E (1 << 0) + +/* RIICnSR1 */ +#define SR1_AAS0 (1 << 0) + +/* RIICnSR2 */ +#define SR2_START (1 << 2) +#define SR2_STOP (1 << 3) +#define SR2_NACKF (1 << 4) +#define SR2_RDRF (1 << 5) +#define SR2_TEND (1 << 6) +#define SR2_TDRE (1 << 7) + +#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ + +static inline int i2c_status(i2c_t *obj) { + return obj->i2c.i2c->ICSR2.BYTE.LL; +} + +static void i2c_reg_reset(i2c_t *obj) { + /* full reset */ + obj->i2c.i2c->ICCR1.BYTE.LL &= ~CR1_ICE; // CR1.ICE off + obj->i2c.i2c->ICCR1.BYTE.LL |= CR1_RST; // CR1.IICRST on + obj->i2c.i2c->ICCR1.BYTE.LL |= CR1_ICE; // CR1.ICE on + + obj->i2c.i2c->ICMR1.BYTE.LL = 0x08; // P_phi /x 9bit (including Ack) + obj->i2c.i2c->ICSER.BYTE.LL = 0x00; // no slave addr enabled + + /* set frequency */ + obj->i2c.i2c->ICMR1.BYTE.LL |= obj->i2c.pclk_bit; + obj->i2c.i2c->ICBRL.BYTE.LL = obj->i2c.width_low; + obj->i2c.i2c->ICBRH.BYTE.LL = obj->i2c.width_hi; + + obj->i2c.i2c->ICMR2.BYTE.LL = 0x07; + obj->i2c.i2c->ICMR3.BYTE.LL = 0x00; + + obj->i2c.i2c->ICFER.BYTE.LL = 0x72; // SCLE, NFE enabled, TMOT + obj->i2c.i2c->ICIER.BYTE.LL = 0x00; // no interrupt + + obj->i2c.i2c->ICCR1.LONG &= ~CR1_RST; // CR1.IICRST negate reset +} + +static inline int i2c_wait_RDRF(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_RDRF) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_wait_TDRE(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_TDRE) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_wait_TEND(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_TEND) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + + +static int i2c_wait_START(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_START) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_wait_STOP(i2c_t *obj) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_STOP) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + + return 0; +} + +static int i2c_set_STOP(i2c_t *obj) { + /* SR2.STOP = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_STOP; + /* Stop condition */ + obj->i2c.i2c->ICCR2.LONG |= CR2_SP; + + return 0; +} + +static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) { + /* SR2.NACKF = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_NACKF; + /* SR2.STOP = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_STOP; +} + +static void i2c_set_MR3_NACK(i2c_t *obj) { + /* send a NOT ACK */ + obj->i2c.i2c->ICMR3.LONG |= MR3_ACKWP; + obj->i2c.i2c->ICMR3.LONG |= MR3_ACKBT; + obj->i2c.i2c->ICMR3.LONG &= ~MR3_ACKWP; +} + +static void i2c_set_MR3_ACK(i2c_t *obj) { + /* send a ACK */ + obj->i2c.i2c->ICMR3.LONG |= MR3_ACKWP; + obj->i2c.i2c->ICMR3.LONG &= ~MR3_ACKBT; + obj->i2c.i2c->ICMR3.LONG &= ~MR3_ACKWP; +} + +static inline void i2c_power_enable(i2c_t *obj) { + volatile uint8_t dummy; + switch ((int)obj->i2c.index) { + case I2C_0: + CPG.STBCR8.BIT.MSTP87 = 0; + break; + case I2C_1: + CPG.STBCR8.BIT.MSTP86 = 0; + break; + case I2C_2: + CPG.STBCR8.BIT.MSTP85 = 0; + break; + case I2C_3: + CPG.STBCR8.BIT.MSTP84 = 0; + break; + } + dummy = CPG.STBCR8.BYTE; + (void)dummy; +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + /* determine the I2C to use */ + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c.index = pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c.index != NC); + + obj->i2c.i2c = (volatile struct st_riic *)RIIC[obj->i2c.index]; + + /* enable power */ + i2c_power_enable(obj); + + /* set default frequency at 100k */ + i2c_frequency(obj, 100000); + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + obj->i2c.last_stop_flag = 1; +} + +inline int i2c_start(i2c_t *obj) { + int timeout = 0; + + while ((obj->i2c.i2c->ICCR2.LONG & CR2_BBSY) != 0) { + timeout ++; + if (timeout >= obj->i2c.bbsy_wait_cnt) { + break; + } + } + /* Start Condition */ + obj->i2c.i2c->ICCR2.BYTE.LL |= CR2_ST; + + return 0; +} + +static inline int i2c_restart(i2c_t *obj) { + /* SR2.START = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_START; + /* ReStart condition */ + obj->i2c.i2c->ICCR2.LONG |= CR2_RS; + + return 0; +} + +inline int i2c_stop(i2c_t *obj) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + + return 0; +} + +static void i2c_set_err_noslave(i2c_t *obj) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->i2c.last_stop_flag = 1; +} + +static inline int i2c_do_write(i2c_t *obj, int value) { + int timeout = 0; + + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while ((i2c_status(obj) & SR2_TDRE) == 0) { + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + /* write the data */ + obj->i2c.i2c->ICDRT.LONG = value; + + return 0; +} + +static inline int i2c_read_address_write(i2c_t *obj, int value) { + int status; + + status = i2c_wait_TDRE(obj); + if (status == 0) { + /* write the data */ + obj->i2c.i2c->ICDRT.LONG = value; + } + + return status; + +} + +static inline int i2c_do_read(i2c_t *obj, int last) { + if (last == 2) { + /* this time is befor last byte read */ + /* Set MR3 WAIT bit is 1 */; + obj->i2c.i2c->ICMR3.LONG |= MR3_WAIT; + } else if (last == 1) { + i2c_set_MR3_NACK(obj); + } else { + i2c_set_MR3_ACK(obj); + } + + /* return the data */ + return (obj->i2c.i2c->ICDRR.LONG & 0xFF); +} + +void i2c_frequency(i2c_t *obj, int hz) { + float64_t pclk_val; + float64_t wait_utime; + volatile float64_t bps; + volatile float64_t L_time; /* H Width period */ + volatile float64_t H_time; /* L Width period */ + uint32_t tmp_L_width; + uint32_t tmp_H_width; + uint32_t remainder; + uint32_t wk_cks = 0; + + /* set PCLK */ + if (false == RZ_A2_IsClockMode0()) { + pclk_val = (float64_t)CM1_RENESAS_RZ_A2_P0_CLK; + } else { + pclk_val = (float64_t)CM0_RENESAS_RZ_A2_P0_CLK; + } + + /* Min 10kHz, Max 400kHz */ + if (hz < 10000) { + bps = 10000; + } else if (hz > 400000) { + bps = 400000; + } else { + bps = (float64_t)hz; + } + + /* Calculation L width time */ + L_time = (1 / (2 * bps)); /* Harf period of frequency */ + H_time = L_time; + + /* Check I2C mode of Speed */ + if (bps > 100000) { + /* Fast-mode */ + L_time -= 102E-9; /* Falling time of SCL clock. */ + H_time -= 138E-9; /* Rising time of SCL clock. */ + /* Check L wideth */ + if (L_time < 1.3E-6) { + /* Wnen L width less than 1.3us */ + /* Subtract Rise up and down time for SCL from H/L width */ + L_time = 1.3E-6; + H_time = (1 / bps) - L_time - 138E-9 - 102E-9; + } + } + + tmp_L_width = (uint32_t)(L_time * pclk_val * 10); + tmp_L_width >>= 1; + wk_cks++; + while (tmp_L_width >= 341) { + tmp_L_width >>= 1; + wk_cks++; + } + remainder = tmp_L_width % 10; + tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */ + + tmp_H_width = (uint32_t)(H_time * pclk_val * 10); + tmp_H_width >>= wk_cks; + if (remainder == 0) { + tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */ + } else { + remainder += tmp_H_width % 10; + tmp_H_width = (tmp_H_width / 10) - 3; + if (remainder > 10) { + tmp_H_width += 1; /* fine adjustment */ + } + } + /* timeout of BBSY bit is minimum low width by frequency */ + /* so timeout calculates "(low width) * 2" by frequency */ + wait_utime = (L_time * 2) * 1000000; + /* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */ + if (wait_utime <= 0.3) { + obj->i2c.bbsy_wait_cnt = 1; + } else { + obj->i2c.bbsy_wait_cnt = (int)(wait_utime / 0.3); + } + + + /* I2C Rate */ + obj->i2c.pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */ + obj->i2c.width_low = (uint8_t)(tmp_L_width | 0x000000E0); + obj->i2c.width_hi = (uint8_t)(tmp_H_width | 0x000000E0); + + /* full reset */ + i2c_reg_reset(obj); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count = 0; + int status; + int value; + + i2c_set_MR3_ACK(obj); + /* There is a STOP condition for last processing */ + if (obj->i2c.last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_BUS_BUSY; + } + } + obj->i2c.last_stop_flag = stop; + /* Send Slave address */ + status = i2c_read_address_write(obj, (address | 0x01)); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* wait RDRF */ + status = i2c_wait_RDRF(obj); + /* check ACK/NACK */ + if ((status != 0) || ((obj->i2c.i2c->ICSR2.LONG & SR2_NACKF) != 0)) { + /* Slave sends NACK */ + (void)i2c_set_STOP(obj); + /* dummy read */ + value = obj->i2c.i2c->ICDRR.LONG; + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->i2c.last_stop_flag = 1; + return I2C_ERROR_NO_SLAVE; + } + if (length != 0) { + /* Read in all except last byte */ + if (length > 2) { + /* dummy read */ + value = obj->i2c.i2c->ICDRR.LONG; + for (count = 0; count < (length - 1); count++) { + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* Recieve the data */ + if (count == (length - 2)) { + value = i2c_do_read(obj, 1); + } else if ((length >= 3) && (count == (length - 3))) { + value = i2c_do_read(obj, 2); + } else { + value = i2c_do_read(obj, 0); + } + data[count] = (char)value; + } + } else if (length == 2) { + /* Set MR3 WAIT bit is 1 */ + obj->i2c.i2c->ICMR3.LONG |= MR3_WAIT; + /* dummy read */ + value = obj->i2c.i2c->ICDRR.LONG; + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + i2c_set_MR3_NACK(obj); + data[count] = (char)obj->i2c.i2c->ICDRR.LONG; + count++; + } else { + /* length == 1 */ + /* Set MR3 WAIT bit is 1 */; + obj->i2c.i2c->ICMR3.LONG |= MR3_WAIT; + i2c_set_MR3_NACK(obj); + /* dummy read */ + value = obj->i2c.i2c->ICDRR.LONG; + } + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + + /* If not repeated start, send stop. */ + if (stop) { + (void)i2c_set_STOP(obj); + /* RIICnDRR read */ + value = (obj->i2c.i2c->ICDRR.LONG & 0xFF); + data[count] = (char)value; + /* RIICnMR3.WAIT = 0 */ + obj->i2c.i2c->ICMR3.LONG &= ~MR3_WAIT; + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + /* RIICnDRR read */ + value = (obj->i2c.i2c->ICDRR.LONG & 0xFF); + data[count] = (char)value; + /* RIICnMR3.WAIT = 0 */ + obj->i2c.i2c->ICMR3.LONG &= ~MR3_WAIT; + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_START; + } + } else { + /* If not repeated start, send stop. */ + if (stop) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_START; + } + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int cnt; + int status; + + /* There is a STOP condition for last processing */ + if (obj->i2c.last_stop_flag != 0) { + status = i2c_start(obj); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_BUS_BUSY; + } + } + obj->i2c.last_stop_flag = stop; + /* Send Slave address */ + status = i2c_do_write(obj, address); + if (status != 0) { + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* Wait send end */ + status = i2c_wait_TEND(obj); + if ((status != 0) || ((obj->i2c.i2c->ICSR2.LONG & SR2_NACKF) != 0)) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + /* Send Write data */ + for (cnt=0; cnti2c.i2c->ICSR2.LONG & SR2_NACKF) != 0)) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + return I2C_ERROR_NO_SLAVE; + } + } + } + /* If not repeated start, send stop. */ + if (stop) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_START; + + } + + return length; +} + +void i2c_reset(i2c_t *obj) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) { + int status; + int data; + + data = i2c_do_read(obj, last); + /* wait for it to arrive */ + status = i2c_wait_RDRF(obj); + if (status != 0) { + i2c_set_SR2_NACKF_STOP(obj); + return I2C_ERROR_NO_SLAVE; + } + + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) { + int ack = 0; + int status; + int timeout = 0; + + status = i2c_do_write(obj, (data & 0xFF)); + if (status != 0) { + i2c_set_SR2_NACKF_STOP(obj); + } else { + while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) { + timeout++; + if (timeout >= WAIT_TIMEOUT) { + return ack; + } + } + /* check ACK/NACK */ + if ((obj->i2c.i2c->ICSR2.LONG & SR2_NACKF) != 0) { + /* NACK */ + i2c_set_SR2_NACKF_STOP(obj); + } else { + ack = 1; + } + } + + return ack; +} + +void i2c_slave_mode(i2c_t *obj, int enable_slave) { + if (enable_slave != 0) { + obj->i2c.i2c->ICSER.LONG |= SER_SAR0E; // only slave addr 0 is enabled + } else { + obj->i2c.i2c->ICSER.LONG &= ~SER_SAR0E; // no slave addr enabled + } +} + +int i2c_slave_receive(i2c_t *obj) { + int status; + int retval; + + status = (obj->i2c.i2c->ICSR1.BYTE.LL & SR1_AAS0); + status |= (obj->i2c.i2c->ICCR2.BYTE.LL & CR2_TRS) >> 4; + + switch(status) { + case 0x01: + /* the master is writing to this slave */ + retval = 3; + break; + case 0x02: + /* the master is writing to all slave */ + retval = 2; + break; + case 0x03: + /* the master has requested a read from this slave */ + retval = 1; + break; + default : + /* no data */ + retval = 0; + break; + } + + return retval; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) { + int timeout = 0; + int count; + int break_flg = 0; + + if(length <= 0) { + return 0; + } + for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) { + /* There is no timeout, but the upper limit value is set to avoid an infinite loop. */ + while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) { + if ((i2c_status(obj) & SR2_STOP) != 0) { + break_flg = 1; + break; + } + timeout ++; + if (timeout >= WAIT_TIMEOUT) { + return -1; + } + } + if (break_flg == 0) { + if (count == 0) { + /* dummy read */ + (void)obj->i2c.i2c->ICDRR.LONG; + } else { + data[count - 1] = (char)(obj->i2c.i2c->ICDRR.LONG & 0xFF); + } + } + } + if (break_flg == 0) { + (void)i2c_wait_STOP(obj); + } else { + if ((i2c_status(obj) & SR2_RDRF) != 0) { + if (count <= 1) { + /* fail safe */ + /* dummy read */ + (void)obj->i2c.i2c->ICDRR.LONG; + } else { + data[count - 2] = (char)(obj->i2c.i2c->ICDRR.LONG & 0xFF); + } + } + } + /* SR2.STOP = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_STOP; + + return (count - 1); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + int count = 0; + int status = 0; + + if(length <= 0) { + return 0; + } + + while ((count < length) && (status == 0)) { + status = i2c_do_write(obj, data[count]); + if(status == 0) { + /* Wait send end */ + status = i2c_wait_TEND(obj); + if ((status != 0) || ((count < (length - 1)) && ((obj->i2c.i2c->ICSR2.LONG & SR2_NACKF) != 0))) { + /* NACK */ + break; + } + } + count++; + } + /* dummy read */ + (void)obj->i2c.i2c->ICDRR.LONG; + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + + return count; +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + obj->i2c.i2c->ICSAR0.LONG = (address & 0xfffffffe); +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if DEVICE_I2C_ASYNCH + +#define IRQ_NUM 4 +#define IRQ_TX 0 +#define IRQ_RX 1 +#define IRQ_ERR1 2 +#define IRQ_ERR2 3 + +static void i2c_irqs_set(i2c_t *obj, uint32_t enable); + +static void i2c0_tx_irq(void); +static void i2c1_tx_irq(void); +static void i2c2_tx_irq(void); +static void i2c3_tx_irq(void); +static void i2c0_rx_irq(void); +static void i2c1_rx_irq(void); +static void i2c2_rx_irq(void); +static void i2c3_rx_irq(void); +static void i2c0_al_irq(void); +static void i2c1_al_irq(void); +static void i2c2_al_irq(void); +static void i2c3_al_irq(void); +static void i2c0_to_irq(void); +static void i2c1_to_irq(void); +static void i2c2_to_irq(void); +static void i2c3_to_irq(void); + +static const IRQn_Type irq_set_tbl[RIIC_COUNT][IRQ_NUM] = { + {INTRIICTEI0_IRQn, INTRIICRI0_IRQn, INTRIICALI0_IRQn, INTRIICTMOI0_IRQn}, + {INTRIICTEI1_IRQn, INTRIICRI1_IRQn, INTRIICALI1_IRQn, INTRIICTMOI1_IRQn}, + {INTRIICTEI2_IRQn, INTRIICRI2_IRQn, INTRIICALI2_IRQn, INTRIICTMOI2_IRQn}, + {INTRIICTEI3_IRQn, INTRIICRI3_IRQn, INTRIICALI3_IRQn, INTRIICTMOI3_IRQn}, +}; + +static const IRQHandler hander_set_tbl[RIIC_COUNT][IRQ_NUM] = { + {i2c0_tx_irq, i2c0_rx_irq, i2c0_al_irq, i2c0_to_irq}, + {i2c1_tx_irq, i2c1_rx_irq, i2c1_al_irq, i2c1_to_irq}, + {i2c2_tx_irq, i2c2_rx_irq, i2c2_al_irq, i2c2_to_irq}, + {i2c3_tx_irq, i2c3_rx_irq, i2c3_al_irq, i2c3_to_irq}, +}; + +struct i2c_global_data_s { + i2c_t *async_obj; + uint32_t async_callback, event, shouldStop, address; +}; + +static struct i2c_global_data_s i2c_data[RIIC_COUNT]; + +static void i2c_transfer_finished(i2c_t *obj) +{ + i2c_irqs_set(obj, 0); + uint32_t index = obj->i2c.index; + i2c_data[index].event = I2C_EVENT_TRANSFER_COMPLETE; + i2c_data[index].async_obj = NULL; + ((void (*)())i2c_data[index].async_callback)(); +} + +static void i2c_tx_irq(uint32_t index) +{ + i2c_t *obj = i2c_data[index].async_obj; + if ((obj->i2c.i2c->ICSR2.LONG & SR2_NACKF)) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + if (obj->tx_buff.pos == obj->tx_buff.length) { + /* All datas have tranferred */ + + /* Clear TEND */ + obj->i2c.i2c->ICSR2.LONG &= ~(SR2_TEND); + + /* If not repeated start, send stop. */ + if (i2c_data[index].shouldStop && obj->rx_buff.length == 0) { + (void)i2c_set_STOP(obj); + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + i2c_transfer_finished(obj); + } else { + (void)i2c_restart(obj); + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_START; + if (obj->rx_buff.length) { + /* Ready to read */ + i2c_set_MR3_ACK(obj); + + /* Disable INTRIICTEI */ + obj->i2c.i2c->ICIER.BYTE.LL &= ~(1 << 6); + + /* Send Slave address */ + if (i2c_read_address_write(obj, (i2c_data[index].address | 0x01)) != 0) { + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + } else { + i2c_transfer_finished(obj); + } + } + } else { + /* Send next 1 byte */ + if (i2c_do_write(obj, *(uint8_t *)obj->tx_buff.buffer) != 0) { + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1; + ++obj->tx_buff.pos; + } +} + +static void i2c_rx_irq(uint32_t index) +{ + i2c_t *obj = i2c_data[index].async_obj; + if (obj->rx_buff.pos == SIZE_MAX) { + if ((obj->i2c.i2c->ICSR2.LONG & SR2_NACKF) != 0) { + /* Slave sends NACK */ + (void)i2c_set_STOP(obj); + /* dummy read */ + if (obj->i2c.i2c->ICDRR.LONG) {} + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + obj->i2c.last_stop_flag = 1; + + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } + if (obj->rx_buff.length == 1) { + /* length == 1 */ + /* Set MR3 WAIT bit is 1 */; + obj->i2c.i2c->ICMR3.LONG |= MR3_WAIT; + i2c_set_MR3_NACK(obj); + } else if (obj->rx_buff.length == 2) { + /* Set MR3 WAIT bit is 1 */ + obj->i2c.i2c->ICMR3.LONG |= MR3_WAIT; + } + /* dummy read */ + if (obj->i2c.i2c->ICDRR.LONG) {} + obj->rx_buff.pos = 0; + return; + } + if ((obj->i2c.i2c->ICSR2.LONG & SR2_NACKF) != 0) { + /* Slave sends NACK */ + i2c_set_err_noslave(obj); + i2c_data[index].event = I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_EARLY_NACK; + i2c_abort_asynch(obj); + ((void (*)())i2c_data[index].async_callback)(); + return; + } else { + switch (obj->rx_buff.length - obj->rx_buff.pos) { + case 1: + /* Finished */ + /* If not repeated start, send stop. */ + if (i2c_data[index].shouldStop) { + (void)i2c_set_STOP(obj); + /* RIICnDRR read */ + *(uint8_t *)obj->rx_buff.buffer = obj->i2c.i2c->ICDRR.LONG & 0xFF; + /* RIICnMR3.WAIT = 0 */ + obj->i2c.i2c->ICMR3.LONG &= ~MR3_WAIT; + (void)i2c_wait_STOP(obj); + i2c_set_SR2_NACKF_STOP(obj); + } else { + (void)i2c_restart(obj); + /* RIICnDRR read */ + *(uint8_t *)obj->rx_buff.buffer = obj->i2c.i2c->ICDRR.LONG & 0xFF; + /* RIICnMR3.WAIT = 0 */ + obj->i2c.i2c->ICMR3.LONG &= ~MR3_WAIT; + (void)i2c_wait_START(obj); + /* SR2.START = 0 */ + obj->i2c.i2c->ICSR2.LONG &= ~SR2_START; + } + + i2c_transfer_finished(obj); + return; + + case 2: + i2c_set_MR3_NACK(obj); + break; + + case 3: + /* this time is befor last byte read */ + /* Set MR3 WAIT bit is 1 */ + obj->i2c.i2c->ICMR3.LONG |= MR3_WAIT; + break; + + default: + i2c_set_MR3_ACK(obj); + break; + } + *(uint8_t *)obj->rx_buff.buffer = obj->i2c.i2c->ICDRR.LONG & 0xFF; + obj->rx_buff.buffer = (uint8_t *)obj->rx_buff.buffer + 1; + ++obj->rx_buff.pos; + } +} + +static void i2c_err_irq(uint32_t index) +{ + i2c_t *obj = i2c_data[index].async_obj; + i2c_abort_asynch(obj); + i2c_data[index].event = I2C_EVENT_ERROR; + ((void (*)())i2c_data[index].async_callback)(); +} + +/* TX handler */ +static void i2c0_tx_irq(void) +{ + i2c_tx_irq(0); +} + +static void i2c1_tx_irq(void) +{ + i2c_tx_irq(1); +} + +static void i2c2_tx_irq(void) +{ + i2c_tx_irq(2); +} + +static void i2c3_tx_irq(void) +{ + i2c_tx_irq(3); +} + +/* RX handler */ +static void i2c0_rx_irq(void) +{ + i2c_rx_irq(0); +} + +static void i2c1_rx_irq(void) +{ + i2c_rx_irq(1); +} + +static void i2c2_rx_irq(void) +{ + i2c_rx_irq(2); +} + +static void i2c3_rx_irq(void) +{ + i2c_rx_irq(3); +} + +/* Arbitration Lost handler */ +static void i2c0_al_irq(void) +{ + i2c_err_irq(0); +} + +static void i2c1_al_irq(void) +{ + i2c_err_irq(1); +} + +static void i2c2_al_irq(void) +{ + i2c_err_irq(2); +} + +static void i2c3_al_irq(void) +{ + i2c_err_irq(3); +} + +/* Timeout handler */ +static void i2c0_to_irq(void) +{ + i2c_err_irq(0); +} + +static void i2c1_to_irq(void) +{ + i2c_err_irq(1); +} + +static void i2c2_to_irq(void) +{ + i2c_err_irq(2); +} + +static void i2c3_to_irq(void) +{ + i2c_err_irq(3); +} + +static void i2c_irqs_set(i2c_t *obj, uint32_t enable) +{ + int i; + const IRQn_Type *irqTable = irq_set_tbl[obj->i2c.index]; + const IRQHandler *handlerTable = hander_set_tbl[obj->i2c.index]; + for (i = 0; i < IRQ_NUM; ++i) { + if (enable) { + InterruptHandlerRegister(irqTable[i], handlerTable[i]); + GIC_SetPriority(irqTable[i], 5); + if (i == 1) { + GIC_SetConfiguration(irqTable[i], 3); + } else { + GIC_SetConfiguration(irqTable[i], 1); + } + GIC_EnableIRQ(irqTable[i]); + } else { + GIC_DisableIRQ(irqTable[i]); + } + } + obj->i2c.i2c->ICIER.BYTE.LL = enable ? 0x63 : 0x00; +} + +/****************************************************************************** + * ASYNCHRONOUS HAL + ******************************************************************************/ + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + MBED_ASSERT(obj); + MBED_ASSERT(tx ? tx_length : 1); + MBED_ASSERT(rx ? rx_length : 1); + MBED_ASSERT((obj->i2c.i2c->ICSER.LONG & SER_SAR0E) == 0); /* Slave mode */ + + obj->tx_buff.buffer = (void *)tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = 8; + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = SIZE_MAX; + obj->rx_buff.width = 8; + i2c_data[obj->i2c.index].async_obj = obj; + i2c_data[obj->i2c.index].async_callback = handler; + i2c_data[obj->i2c.index].event = 0; + i2c_data[obj->i2c.index].shouldStop = stop; + i2c_data[obj->i2c.index].address = address; + i2c_irqs_set(obj, 1); + + /* There is a STOP condition for last processing */ + if (obj->i2c.last_stop_flag != 0) { + if (i2c_start(obj) != 0) { + i2c_set_err_noslave(obj); + i2c_data[obj->i2c.index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())handler)(); + return; + } + } + obj->i2c.last_stop_flag = stop; + + if (rx_length && tx_length == 0) { + /* Ready to read */ + i2c_set_MR3_ACK(obj); + + /* Disable INTRIICTEI */ + obj->i2c.i2c->ICIER.BYTE.LL &= ~(1 << 6); + + address |= 0x01; + } + /* Send Slave address */ + if (i2c_do_write(obj, address) != 0) { + i2c_set_err_noslave(obj); + i2c_data[obj->i2c.index].event = I2C_EVENT_ERROR | I2C_EVENT_ERROR_NO_SLAVE; + i2c_abort_asynch(obj); + ((void (*)())handler)(); + return; + } +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + return i2c_data[obj->i2c.index].event; +} + +uint8_t i2c_active(i2c_t *obj) +{ + return i2c_data[obj->i2c.index].async_obj != NULL; +} + +void i2c_abort_asynch(i2c_t *obj) +{ + i2c_data[obj->i2c.index].async_obj = NULL; + i2c_irqs_set(obj, 0); + i2c_reg_reset(obj); +} + +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/objects.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/objects.h new file mode 100644 index 0000000..78cacbb --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/objects.h @@ -0,0 +1,95 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct i2c_s { + volatile struct st_riic *i2c; + int index; + uint8_t pclk_bit; + uint8_t width_low; + uint8_t width_hi; + int bbsy_wait_cnt; + int last_stop_flag; +}; + +struct spi_s { + volatile struct st_rspi *spi; + uint32_t bits; + int index; +}; + +struct gpio_irq_s { + uint32_t port; + uint32_t pin; + uint32_t ch; + uint8_t int_enable; +}; + +struct port_s { + __IO uint16_t *reg_dir; + __IO uint8_t *reg_out; + __I uint8_t *reg_in; + PortName port; + uint32_t mask; +}; + +struct serial_s { + uint32_t ch; + volatile struct st_scifa* uart; +}; + +struct pwmout_s { + uint32_t ch; + volatile struct st_gpt32e *pwm; + int index; + int type; + float duty; +}; + +struct analogin_s { + ADCName adc; +}; + +struct can_s { + uint32_t ch; +}; + +struct trng_s { + uint8_t dummy; +}; + +struct flash_s { + uint8_t dummy; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/pinmap.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/pinmap.c new file mode 100644 index 0000000..7f9b1b1 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/pinmap.c @@ -0,0 +1,49 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "PeripheralPins.h" +#include "mbed_error.h" +#include "gpio_addrdefine.h" +#include "mbed_drv_cfg.h" + +PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */ + +void pin_function(PinName pin, int function) { + uint32_t reg_group = PINGROUP(pin); + uint32_t bitmask = (1 << PINNO(pin)); + + if (reg_group > GPIO_GROUP_MAX) return; + + if (gpio_multi_guard == pin) { + gpio_multi_guard = (PinName)NC; + return; + } + + if (function == 0) { + *PMR(reg_group) &= ~bitmask; + } else { + GPIO.PWPR.BIT.B0WI = 0; + GPIO.PWPR.BIT.PFSWE = 1; + *PFS(reg_group, PINNO(pin)) = function; + GPIO.PWPR.BIT.PFSWE = 0; + GPIO.PWPR.BIT.B0WI = 1; + *PMR(reg_group) |= bitmask; + } +} + +void pin_mode(PinName pin, PinMode mode) { +// if (pin == (PinName)NC) { return; } +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/port_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/port_api.c new file mode 100644 index 0000000..2af275e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/port_api.c @@ -0,0 +1,82 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "gpio_addrdefine.h" + +PinName port_pin(PortName port, int pin_n) { + return (PinName)((port * 0x10) + pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + uint32_t i; + + obj->port = port; + obj->mask = mask; + obj->reg_dir = (volatile uint16_t *)PDR(port); + obj->reg_out = (volatile uint8_t *)PODR(port); + obj->reg_in = (volatile uint8_t *)PIDR(port); + + // The function is set per pin: reuse gpio logic + for (i = 0; i < 8; i++) { + if (obj->mask & (1 << i)) { + gpio_set(port_pin(obj->port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i = 0; i < 8; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + uint32_t i; + + for (i = 0; i < 8; i++) { + if (obj->mask & (1 << i)) { + switch (dir) { + case PIN_INPUT : + *obj->reg_dir &= ~((uint16_t)(0x3 << (obj->port * 2))); + *obj->reg_dir |= (0x2 << (obj->port * 2)); + break; + case PIN_OUTPUT: + *obj->reg_dir |= (0x3 << (obj->port * 2)); + break; + default: + /* do nothing */ + break; + } + } + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) { + return (*obj->reg_in & obj->mask); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/pwmout_api.c new file mode 100644 index 0000000..62aaa24 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/pwmout_api.c @@ -0,0 +1,185 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_PWMOUT +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "PeripheralPins.h" +#include "RZ_A2_Init.h" +#include "iodefine.h" +#include "gpio_addrdefine.h" +#include "mbed_drv_cfg.h" + +static const volatile struct st_gpt32e *GPT32E[] = { + &GPT32E0, &GPT32E1, &GPT32E2, &GPT32E3, + &GPT32E4, &GPT32E5, &GPT32E6, &GPT32E7 +}; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // determine the channel + PWMName index = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(index != (PWMName)NC); + + CPG.STBCR3.BIT.MSTP30 = 0; + + pinmap_pinout(pin, PinMap_PWM); + + obj->index = index; + obj->type = (index & 0x01); + obj->pwm = (volatile struct st_gpt32e *)GPT32E[(index >> 1)]; + obj->duty = 0.0f; + + /* Set operating mode : saw-wave PWM mode */ + obj->pwm->GTCR.BIT.MD = 0x0; + + /* Set count direction : up */ + obj->pwm->GTUDDTYC.BIT.UDF = 0x1; + obj->pwm->GTUDDTYC.BIT.UD = 0x1; + obj->pwm->GTUDDTYC.BIT.UDF = 0x0; + + pwmout_period_us(obj, 1000); + + if (obj->type == 0) { + obj->pwm->GTIOR.BIT.GTIOA = 0x19; /* Set GTIOC pin function */ + obj->pwm->GTBER.BIT.CCRA = 0x01; /* Set buffer operation : Single buffer operation */ + obj->pwm->GTCCRA.LONG = 0; /* Set compare match value */ + obj->pwm->GTIOR.BIT.OAE = 0x1; /* Enable GTIOC pin output */ + } else { + obj->pwm->GTIOR.BIT.GTIOB = 0x19; /* Set GTIOC pin function */ + obj->pwm->GTBER.BIT.CCRB = 0x01; /* Set buffer operation : Single buffer operation */ + obj->pwm->GTCCRB.LONG = 0; /* Set compare match value */ + obj->pwm->GTIOR.BIT.OBE = 0x1; /* Enable GTIOC pin output */ + } + + /* Start count operation */ + obj->pwm->GTCR.BIT.CST = 0x01; +} + +void pwmout_free(pwmout_t* obj) { + pwmout_write(obj, 0); +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0f; + } else if (value > 1.0f) { + value = 1.0f; + } else { + // Do Nothing + } + + obj->duty = value; + + if (obj->type == 0) { + obj->pwm->GTCCRC.LONG = obj->pwm->GTPR.LONG * value; /* Set buffer value */ + obj->pwm->GTUDDTYC.BIT.OADTYF = 0x1; + if (value == 0.0f) { + obj->pwm->GTUDDTYC.BIT.OADTY = 0x2; + } else if (value == 1.0f) { + obj->pwm->GTUDDTYC.BIT.OADTY = 0x3; + } else { + obj->pwm->GTUDDTYC.BIT.OADTY = 0x0; + } + obj->pwm->GTUDDTYC.BIT.OADTYF = 0x0; + } else { + obj->pwm->GTCCRE.LONG = obj->pwm->GTPR.LONG * value; /* Set buffer value */ + obj->pwm->GTUDDTYC.BIT.OBDTYF = 0x1; + if (value == 0.0f) { + obj->pwm->GTUDDTYC.BIT.OBDTY = 0x2; + } else if (value == 1.0f) { + obj->pwm->GTUDDTYC.BIT.OBDTY = 0x3; + } else { + obj->pwm->GTUDDTYC.BIT.OBDTY = 0x0; + } + obj->pwm->GTUDDTYC.BIT.OBDTYF = 0x0; + } +} + +float pwmout_read(pwmout_t* obj) { + float value; + + if (obj->type == 0) { + value = (float)obj->pwm->GTCCRC.LONG / (float)obj->pwm->GTPR.LONG; + } else { + value = (float)obj->pwm->GTCCRE.LONG / (float)obj->pwm->GTPR.LONG; + } + + return (value > 1.0f) ? (1.0f) : (value); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + uint32_t pclk_base; + uint32_t wk_cycle; + + if (RZ_A2_IsClockMode0() == false) { + pclk_base = (uint32_t)CM1_RENESAS_RZ_A2_P1_CLK / 1000000; + } else { + pclk_base = (uint32_t)CM0_RENESAS_RZ_A2_P1_CLK / 1000000; + } + + uint32_t us_max = 0xFFFFFFFF / pclk_base; + + if ((uint32_t)us > us_max) { + us = us_max; + } else if (us < 1) { + us = 1; + } else { + // Do Nothing + } + + wk_cycle = pclk_base * us; + obj->pwm->GTCR.BIT.TPCS = 0x0; /* Select count clock */ + obj->pwm->GTPR.LONG = wk_cycle - 1; /* Set cycle */ + obj->pwm->GTCNT.LONG = 0; /* Set initial value for counter */ + + /* set duty again */ + pwmout_write(obj, obj->duty); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + float value = 0; + + if (RZ_A2_IsClockMode0() == false) { + value = (float)(us * ((uint32_t)CM0_RENESAS_RZ_A2_P0_CLK / 1000000)) / (float)(obj->pwm->GTPR.LONG + 1); + } else { + value = (float)(us * ((uint32_t)CM1_RENESAS_RZ_A2_P0_CLK / 1000000)) / (float)(obj->pwm->GTPR.LONG + 1); + } + pwmout_write(obj, value); +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/rtc_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/rtc_api.c new file mode 100644 index 0000000..0e94a0b --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/rtc_api.c @@ -0,0 +1,196 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "device.h" + +#if DEVICE_RTC + +#include "rtc_api.h" +#include "iodefine.h" +#include "mbed_drv_cfg.h" + +#ifdef USE_RTCX1_CLK +#elif defined(USE_EXTAL_CLK) +#else +#error Select RTC clock input ! +#endif + +#define READ_LOOP_MAX (2000) +#define TIME_ERROR_VAL (0u) + +/* + * Setup the RTC based on a time structure. + * The rtc_init function should be executed first. + * [in] + * None. + * [out] + * None. + */ +void rtc_init(void) +{ + volatile int i; + + CPG.STBCR5.BIT.MSTP52 = 0; + + // Set control register +#if defined(USE_RTCX1_CLK) + RTC_BCNT1.RCR4.BIT.RCKSEL = 0; + RTC_BCNT1.RCR3.BIT.RTCEN = 1; +#elif defined(USE_EXTAL_CLK) + PMG.RTCXTALSEL.BIT.RTC1XT = 1; + RTC_BCNT1.RCR4.BIT.RCKSEL = 1; + RTC_BCNT1.RCR3.BIT.RTCEN = 0; +#endif + + i = 0; + while (i < 1000) { + i++; + } + + RTC_BCNT1.RCR2.BIT.START = 0; + for (i = 0; (i < READ_LOOP_MAX) && (RTC_BCNT1.RCR2.BIT.START != 0); i++) { + ; + } + +#if defined(USE_EXTAL_CLK) + // Clockin = 24MHz + RTC_BCNT1.RFRH.WORD = 0x0001; + RTC_BCNT1.RFRL.WORD = 0x6E35; +#endif + + RTC_BCNT1.RCR2.BIT.CNTMD = 1; + for (i = 0; (i < READ_LOOP_MAX) && (RTC_BCNT1.RCR2.BIT.CNTMD != 1); i++) { + ; + } + + RTC_BCNT1.RCR2.BIT.RESET = 1; + for (i = 0; (i < READ_LOOP_MAX) && (RTC_BCNT1.RCR2.BIT.RESET != 0); i++) { + ; + } + + RTC_BCNT1.RCR1.BIT.AIE = 1; + RTC_BCNT1.RCR1.BIT.PIE = 0; + + RTC_BCNT1.RCR2.BIT.START = 1; + for (i = 0; (i < READ_LOOP_MAX) && (RTC_BCNT1.RCR2.BIT.START != 1); i++) { + ; + } +} + + +/* + * Release the RTC based on a time structure. + * @note This function does not stop the RTC from counting + * [in] + * None. + * [out] + * None. + */ +void rtc_free(void) +{ +#if defined(USE_EXTAL_CLK) + PMG.RTCXTALSEL.BIT.RTC1XT = 0; +#endif +} + + +/* + * Check the RTC has been enabled. + * Clock Control Register RTC_BCNT1.RCR1.BYTE(bit3): 0 = Disabled, 1 = Enabled. + * [in] + * None. + * [out] + * 0:Disabled, 1:Enabled. + */ +int rtc_isenabled(void) +{ + int ret_val = 0; + + if (RTC_BCNT1.RCR2.BIT.START == 1) { // RTC ON ? + ret_val = 1; + } + + return ret_val; +} + + +/* + * RTC read function. + * [in] + * None. + * [out] + * UNIX timestamp value. + */ +time_t rtc_read(void) +{ + time_t t; + + if (rtc_isenabled() != 0) { + RTC_BCNT1.RCR1.BIT.CIE = 0; // CIE = 0 + do { + RTC_BCNT1.RSR.BIT.CF = 0; + + // Read RTC register + t = ((time_t)RTC_BCNT1.BCNT0.BYTE << 0) + | ((time_t)RTC_BCNT1.BCNT1.BYTE << 8) + | ((time_t)RTC_BCNT1.BCNT2.BYTE << 16) + | ((time_t)RTC_BCNT1.BCNT3.BYTE << 24); + } while (RTC_BCNT1.RSR.BIT.CF != 0); + } else { + // Error + t = TIME_ERROR_VAL; + } + + return t; +} + +/* + * RTC write function + * [in] + * t:UNIX timestamp value + * [out] + * None. + */ +void rtc_write(time_t t) +{ + volatile int i; + + if (rtc_isenabled() != 0) { + RTC_BCNT1.RCR2.BIT.START = 0; + for (i = 0; (i < READ_LOOP_MAX) && (RTC_BCNT1.RCR2.BIT.START != 0); i++) { + ; + } + + RTC_BCNT1.RCR2.BIT.RESET = 1; + for (i = 0; (i < READ_LOOP_MAX) && (RTC_BCNT1.RCR2.BIT.RESET != 0); i++) { + ; + } + + RTC_BCNT1.BCNT0.BYTE = (uint8_t)(t >> 0); + RTC_BCNT1.BCNT1.BYTE = (uint8_t)(t >> 8); + RTC_BCNT1.BCNT2.BYTE = (uint8_t)(t >> 16); + RTC_BCNT1.BCNT3.BYTE = (uint8_t)(t >> 24); + + RTC_BCNT1.RCR2.BIT.START = 1; + for (i = 0; (i < READ_LOOP_MAX) && (RTC_BCNT1.RCR2.BIT.START != 1); i++) { + ; + } + } +} + +#endif /* DEVICE_RTC */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/serial_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/serial_api.c new file mode 100644 index 0000000..e706018 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/serial_api.c @@ -0,0 +1,763 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation + +#if DEVICE_SERIAL +#include "mbed_assert.h" +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "RZ_A2_Init.h" + +#include "iodefine.h" +#include "mbed_drv_cfg.h" +#include "mbed_critical.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ + +#define UART_NUM 5 +#define IRQ_NUM 3 + +static void uart0_tx_irq(void); +static void uart0_rx_irq(void); +static void uart0_er_irq(void); +static void uart1_tx_irq(void); +static void uart1_rx_irq(void); +static void uart1_er_irq(void); +static void uart2_tx_irq(void); +static void uart2_rx_irq(void); +static void uart2_er_irq(void); +static void uart3_tx_irq(void); +static void uart3_rx_irq(void); +static void uart3_er_irq(void); +static void uart4_tx_irq(void); +static void uart4_rx_irq(void); +static void uart4_er_irq(void); + +static uint8_t serial_available_buffer(serial_t *obj); +static void serial_irq_err_set(serial_t *obj, uint32_t enable); + +static volatile struct st_scifa* SCIFA[UART_NUM] = { + &SCIFA0, &SCIFA1, &SCIFA2, &SCIFA3, &SCIFA4 +}; + +int stdio_uart_inited = 0; +serial_t stdio_uart; +static uart_irq_handler irq_handler; + +struct serial_global_data_s { + uint32_t serial_irq_id; + gpio_t sw_rts, sw_cts; + serial_t *tranferring_obj, *receiving_obj; + uint32_t async_tx_callback, async_rx_callback; + int event, wanted_rx_events; +}; + +static struct serial_global_data_s uart_data[UART_NUM]; + +static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = { + {RXI0_IRQn, TXI0_IRQn, ERI0_IRQn}, + {RXI1_IRQn, TXI1_IRQn, ERI1_IRQn}, + {RXI2_IRQn, TXI2_IRQn, ERI2_IRQn}, + {RXI3_IRQn, TXI3_IRQn, ERI3_IRQn}, + {RXI4_IRQn, TXI4_IRQn, ERI4_IRQn}, +}; + +static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { + {uart0_rx_irq, uart0_tx_irq, uart0_er_irq}, + {uart1_rx_irq, uart1_tx_irq, uart1_er_irq}, + {uart2_rx_irq, uart2_tx_irq, uart2_er_irq}, + {uart3_rx_irq, uart3_tx_irq, uart3_er_irq}, + {uart4_rx_irq, uart4_tx_irq, uart4_er_irq}, +}; + + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + volatile uint8_t dummy_buf; + int is_stdio_uart = 0; + // determine the UART to use + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + uint32_t ch_no = pinmap_merge(uart_tx, uart_rx); + +#if defined(PRINTF_NOT_USE) + if ((int)ch_no == NC) { + obj->serial.ch = ch_no; + return; + } +#else + MBED_ASSERT((int)ch_no != NC); +#endif + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + obj->serial.ch = ch_no; + obj->serial.uart = SCIFA[ch_no]; + + /* ==== Module standby clear ==== */ + CPG.STBCR4.BYTE &= ~(0x80 >> ch_no); + dummy_buf = CPG.STBCR4.BYTE; + (void)dummy_buf; + + /* ==== SCIF initial setting ==== */ + /* --- Serial control register(SCR) setting --- */ + obj->serial.uart->SCR.WORD = 0x0000; /* SCIFA transmitting and receiving operations stop */ + + /* ---- FIFO control register (FCR) setting ---- */ + if ((int)uart_tx != NC) { /* Use transmit */ + /* Transmit FIFO reset */ + obj->serial.uart->FCR.BIT.TFRST = 0x01; + } + + if ((int)uart_rx != NC) { /* Use receive */ + /* Receive FIFO data register reset */ + obj->serial.uart->FCR.BIT.RFRST = 0x1; + } + + /* ---- Serial status register (FSR) setting ---- */ + obj->serial.uart->FSR.BIT.DR = 0x0; /* ER bit clear */ + obj->serial.uart->FSR.BIT.BRK = 0x0; /* BRK bit clear */ + obj->serial.uart->FSR.BIT.ER = 0x0; /* ER bit clear */ + + /* ---- Line status register (LSR) setting ---- */ + obj->serial.uart->LSR.BIT.ORER = 0x0; /* ORER bit clear */ + + /* ---- Serial control register (SCR) setting ---- */ + obj->serial.uart->SCR.BIT.CKE = 0x0; /* B'00 : Internal CLK */ + + serial_baud(obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + /* ---- Serial extension mode register (SEMR) setting ---- + b7 BGDM - Baud rate generator double-speed mode : Normal mode + b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ + + obj->serial.uart->SEMR.BIT.ABCS0 = 0x0; /* Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ + obj->serial.uart->SEMR.BIT.NFEN = 0x1; /* Noise Filter : Enable */ + obj->serial.uart->SEMR.BIT.DIR = 0x0; /* LSB first */ + obj->serial.uart->SEMR.BIT.MDDRS = 0x0; /* Select BRR register */ + obj->serial.uart->SEMR.BIT.BRME = 0x0; /* Bit Modulation Enable : Disable */ + obj->serial.uart->SEMR.BIT.BGDM = 0x0; /* Baud rate generator double-speed mode : Normal mode*/ + + obj->serial.uart->FCR.BIT.LOOP = 0x0; /* Loop-back test : Disabled */ + if ((int)uart_rx != NC) { + obj->serial.uart->FCR.BIT.RFRST = 0x0; /* Receive FIFO data register reset : Disabled */ + obj->serial.uart->SCR.BIT.TE = 0x1; /* transmitting operations is enabled */ + } else { + obj->serial.uart->FCR.BIT.RFRST = 0x1; /* Receive FIFO data register reset : Enable */ + } + if ((int)uart_tx != NC) { /* Use transmit */ + obj->serial.uart->FCR.BIT.TFRST = 0x0; /* Transmit FIFO data register reset : Disabled */ + obj->serial.uart->SCR.BIT.RE = 0x1; /* receiving operations is enabled */ + } else { + obj->serial.uart->FCR.BIT.TFRST = 0x1; /* Transmit FIFO data register reset : Enable */ + } + obj->serial.uart->FCR.BIT.MCE = 0x0; /* Modem control enable : Disabled */ + obj->serial.uart->FCR.BIT.TTRG = 0x3; /* Transmit FIFO data trigger : 0-data */ + obj->serial.uart->FCR.BIT.RTRG = 0x0; /* Receive FIFO data trigger : 1-data */ + obj->serial.uart->FCR.BIT.RSTRG = 0x0; /* RTS output active trigger : Initial value */ + + /* ---- Serial port register (SCR, SPTR) setting ---- */ + /* b1 SPB2IO - Serial port break output : Enabled + b0 SPB2DT - Serial port break data : High-level */ + + obj->serial.uart->SPTR.WORD |= 0x3; /* b1 SPB2IO - Serial port break output : Enabled */ + /* b0 SPB2DT - Serial port break data : High-level */ + + if ((int)uart_rx != NC) { + obj->serial.uart->SCR.BIT.TIE = 0x1; + obj->serial.uart->SCR.BIT.TE = 0x1; /* transmitting operations is enabled */ + } + if ((int)uart_tx != NC) { /* Use transmit */ + obj->serial.uart->SCR.BIT.RIE = 0x1; + obj->serial.uart->SCR.BIT.RE = 0x1; /* receiving operations is enabled */ + } + + is_stdio_uart = (ch_no == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + uint32_t idx; + uint32_t brr; + uint32_t mddr; + uint32_t wk_data = 8; + float wk_error; + +#if defined(PRINTF_NOT_USE) + if ((int)obj->serial.ch == NC) { + return; + } +#endif + + if (baudrate <= 0) { + return; + } + + for (idx = 0; idx <= 4; idx++) { + /* Calculate Bit Rate */ + brr = CM0_RENESAS_RZ_A2_P1_CLK / (wk_data * baudrate); + if (brr > 0) { + /* The maximum baud rate is (CM0_RENESAS_RZ_A2_P1_CLK / 8) */ + /* If the baud rate is more, brr is set to 0 */ + brr -= 1; + } + + /* When idx is 4 (CKS=3), it allows up to the limit value which can be adjusted with MDDR */ + if ((brr <= 255) || (idx == 4)) { + if (brr > 255) { + brr = 255; + } + + /* Calculate Modulation Duty */ + wk_error = (float)CM0_RENESAS_RZ_A2_P1_CLK / (float)(wk_data * baudrate * (brr + 1)); + mddr = (uint32_t)((256.0f / wk_error) + 0.5f); + if (mddr < 128) { + mddr = 128; /* MDDR >= 128 (Executed only when idx is 4) */ + } + + /* idx= 0: BGDM=1 ABCS0=1 CKS=0 */ + /* 1: BGDM=0 ABCS0=0 CKS=0 */ + /* 2: BGDM=0 ABCS0=0 CKS=1 */ + /* 3: BGDM=1 ABCS0=1 CKS=3 (Do not use CKS=2) */ + /* 4: BGDM=0 ABCS0=0 CKS=3 */ + if ((idx == 0) || (idx == 3)) { + obj->serial.uart->SEMR.BIT.BGDM = 0x1; /* Baud rate generator double-speed mode */ + obj->serial.uart->SEMR.BIT.ABCS0 = 0x1; /* 8 times the transfer rate as the base clock */ + obj->serial.uart->SMR.BIT.CKS = idx; /* Clock Select 0(1/1), 1(1/4), 2(1/16), 3(1/64) */ + } else { + obj->serial.uart->SEMR.BIT.BGDM = 0x0; /* Baud rate generator normal mode */ + obj->serial.uart->SEMR.BIT.ABCS0 = 0x0; /* 16 times the transfer rate as the base clock */ + obj->serial.uart->SMR.BIT.CKS = idx - 1; /* Clock Select 0(1/1), 1(1/4), 2(1/16), 3(1/64) */ + } + obj->serial.uart->SEMR.BIT.MDDRS = 0x0; /* Select BRR register */ + obj->serial.uart->BRR_MDDR.BRR.BYTE = (uint8_t)brr; /* Bit Rate */ + obj->serial.uart->SEMR.BIT.BRME = 0x0; /* Bit rate modulation is disabled */ + if (mddr <= 255) { + obj->serial.uart->SEMR.BIT.MDDRS = 0x1; /* Select MDDR register */ + obj->serial.uart->BRR_MDDR.MDDR.BYTE = (uint8_t)mddr; /* Modulation Duty */ + obj->serial.uart->SEMR.BIT.BRME = 0x1; /* Bit rate modulation is enabled */ + } + break; + } + wk_data = (wk_data << 2); + } +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { +#if defined(PRINTF_NOT_USE) + if ((int)obj->serial.ch == NC) { + return; + } +#endif + + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + MBED_ASSERT((data_bits == 8) || (data_bits == 7)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + + if (stop_bits == 1) { + obj->serial.uart->SMR.BIT.STOP = 0x0; /* Stop bit length : 1 stop bit */ + } else { + obj->serial.uart->SMR.BIT.STOP = 0x1; /* Stop bit length : 2 stop bits */ + } + + switch (parity) { + case ParityNone: + obj->serial.uart->SMR.BIT.PE = 0x0; /* Parity enable : Add and check are disabled */ + obj->serial.uart->SMR.BIT.PM = 0x0; /* Parity mode : even */ + break; + case ParityOdd: + obj->serial.uart->SMR.BIT.PE = 0x1; /* Parity enable : Add and check are enabled */ + obj->serial.uart->SMR.BIT.PM = 0x1; /* Parity mode : odd */ + break; + case ParityEven: + obj->serial.uart->SMR.BIT.PE = 0x1; /* Parity enable : Add and check are enabled */ + obj->serial.uart->SMR.BIT.PM = 0x0; /* Parity mode : even */ + break; + case ParityForced1: + case ParityForced0: + default: + obj->serial.uart->SMR.BIT.PE = 0x0; /* Parity enable : Add and check are disabled */ + obj->serial.uart->SMR.BIT.PM = 0x0; /* Parity mode : even */ + break; + } + + if (data_bits == 8) { + obj->serial.uart->SMR.BIT.CHR = 0x0; /* Character length : 8-bit data */ + } else { + obj->serial.uart->SMR.BIT.CHR = 0x1; /* Character length : 7-bit data */ + } + obj->serial.uart->SMR.BIT.CM = 0x0; /* Communication mode : Asynchronous mode */ +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ + +static void uart_tx_irq(uint32_t ch) { + serial_t *obj = uart_data[ch].tranferring_obj; + if (obj) { + int i = obj->tx_buff.length - obj->tx_buff.pos; + if (0 < i) { + if (serial_available_buffer(obj) < i) { + i = serial_available_buffer(obj); + } + do { + uint8_t c = *(uint8_t *)obj->tx_buff.buffer; + obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1; + ++obj->tx_buff.pos; + obj->serial.uart->FTDR.BYTE = c; + obj->serial.uart->FSR.WORD &= ~0x0060u; + } while (--i); + } else { + uart_data[ch].tranferring_obj = NULL; + uart_data[ch].event = SERIAL_EVENT_TX_COMPLETE; + ((void (*)())uart_data[ch].async_tx_callback)(); + } + } + + irq_handler(uart_data[ch].serial_irq_id, TxIrq); +} + +static void uart_rx_irq(uint32_t ch) { + serial_t *obj = uart_data[ch].receiving_obj; + if (obj) { + if (obj->serial.uart->LSR.BIT.ORER == 1) { + obj->serial.uart->LSR.BIT.ORER = 0; + if (uart_data[ch].wanted_rx_events & SERIAL_EVENT_RX_OVERRUN_ERROR) { + serial_rx_abort_asynch(obj); + uart_data[ch].event = SERIAL_EVENT_RX_OVERRUN_ERROR; + ((void (*)())uart_data[ch].async_rx_callback)(); + } + return; + } + int c = serial_getc(obj); + if (c != -1) { + ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos] = c; + ++obj->rx_buff.pos; + if (c == obj->char_match && ! obj->char_found) { + obj->char_found = 1; + if (obj->rx_buff.pos == obj->rx_buff.length) { + if (uart_data[ch].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) { + uart_data[ch].event = SERIAL_EVENT_RX_COMPLETE; + } + } + if (uart_data[ch].wanted_rx_events & SERIAL_EVENT_RX_CHARACTER_MATCH) { + uart_data[ch].event |= SERIAL_EVENT_RX_CHARACTER_MATCH; + } + if (uart_data[ch].event) { + uart_data[ch].receiving_obj = NULL; + ((void (*)())uart_data[ch].async_rx_callback)(); + } + } else if (obj->rx_buff.pos == obj->rx_buff.length) { + uart_data[ch].receiving_obj = NULL; + if (uart_data[ch].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) { + uart_data[ch].event = SERIAL_EVENT_RX_COMPLETE; + ((void (*)())uart_data[ch].async_rx_callback)(); + } + } + } else { + serial_rx_abort_asynch(obj); + if (uart_data[ch].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) { + uart_data[ch].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR; + if (obj->serial.uart->FSR.BIT.PER == 1) { + uart_data[ch].event = SERIAL_EVENT_RX_PARITY_ERROR; + } else if (obj->serial.uart->FSR.BIT.FER == 1) { + uart_data[ch].event = SERIAL_EVENT_RX_FRAMING_ERROR; + } + ((void (*)())uart_data[ch].async_rx_callback)(); + } + return; + } + } + + irq_handler(uart_data[ch].serial_irq_id, RxIrq); +} + +static void uart_err_irq(uint32_t ch) { + serial_t *obj = uart_data[ch].receiving_obj; + if (obj) { + serial_irq_err_set(obj, 0); + if (uart_data[ch].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) { + uart_data[ch].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR; + if (obj->serial.uart->FSR.BIT.PER == 1) { + uart_data[ch].event = SERIAL_EVENT_RX_PARITY_ERROR; + } else if (obj->serial.uart->FSR.BIT.FER == 1) { + uart_data[ch].event = SERIAL_EVENT_RX_FRAMING_ERROR; + } + ((void (*)())uart_data[ch].async_rx_callback)(); + } + serial_rx_abort_asynch(obj); + + core_util_critical_section_enter(); + if (obj->serial.uart->FSR.WORD & 0x009Cu) { + obj->serial.uart->FSR.WORD &=~0x009Cu; + } + if (obj->serial.uart->LSR.BIT.ORER == 1) { + obj->serial.uart->LSR.BIT.ORER = 0; + } + core_util_critical_section_exit(); + } +} + +static void uart0_tx_irq(void) { + uart_tx_irq(0); +} +static void uart0_rx_irq(void) { + uart_rx_irq(0); +} +static void uart0_er_irq(void) { + uart_err_irq(0); +} + +static void uart1_tx_irq(void) { + uart_tx_irq(1); +} +static void uart1_rx_irq(void) { + uart_rx_irq(1); +} +static void uart1_er_irq(void) { + uart_err_irq(1); +} + +static void uart2_tx_irq(void) { + uart_tx_irq(2); +} +static void uart2_rx_irq(void) { + uart_rx_irq(2); +} +static void uart2_er_irq(void) { + uart_err_irq(2); +} + +static void uart3_tx_irq(void) { + uart_tx_irq(3); +} +static void uart3_rx_irq(void) { + uart_rx_irq(3); +} +static void uart3_er_irq(void) { + uart_err_irq(3); +} + +static void uart4_tx_irq(void) { + uart_tx_irq(4); +} +static void uart4_rx_irq(void) { + uart_rx_irq(4); +} +static void uart4_er_irq(void) { + uart_err_irq(4); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + uart_data[obj->serial.ch].serial_irq_id = id; +} + +static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable) { + if (enable) { + InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler); + GIC_SetPriority(IRQn, 5); + GIC_EnableIRQ(IRQn); + } else { + GIC_DisableIRQ(IRQn); + } +} + +static void serial_irq_err_set(serial_t *obj, uint32_t enable) { + serial_irq_set_irq(irq_set_tbl[obj->serial.ch][2], hander_set_tbl[obj->serial.ch][2], enable); +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + IRQn_Type IRQn; + IRQHandler handler; + + IRQn = irq_set_tbl[obj->serial.ch][irq]; + handler = hander_set_tbl[obj->serial.ch][irq]; + + if (obj->serial.ch < UART_NUM) { + serial_irq_set_irq(IRQn, handler, enable); + } +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + int data; + +#if defined(PRINTF_NOT_USE) + if ((int)obj->serial.ch == NC) { + return 0; + } +#endif + /* Confirming receive error(ER,BRK,FER,PER,ORER) */ + if (((obj->serial.uart->FSR.WORD & 0x009Cu) != 0) || + (obj->serial.uart->LSR.BIT.ORER == 1)) { + /* ---- Detect receive error ---- */ + /* Disable reception */ + /* Reset receiving FIFO */ + /* Clearing FIFO reception reset */ + /* Error bit clear */ + /* Enable reception */ + obj->serial.uart->SCR.BIT.RE = 0; + obj->serial.uart->FCR.BIT.RFRST = 1; + obj->serial.uart->FCR.BIT.RFRST = 0; + obj->serial.uart->FSR.WORD &=~0x009Cu; + obj->serial.uart->LSR.BIT.ORER = 0; + obj->serial.uart->SCR.BIT.RE = 1; + return -1; + } + + /* Is there receive FIFO data? */ + while (obj->serial.uart->FSR.BIT.RDF == 0) { + /* Wait */ + } + + /* Read receive data */ + data = (int)((obj->serial.uart->FRDR.BYTE) & 0xFFu); + /* Clear DR,RDF */ + obj->serial.uart->FSR.BIT.RDF = 0; + + return data; +} + +void serial_putc(serial_t *obj, int c) { +#if defined(PRINTF_NOT_USE) + if ((int)obj->serial.ch == NC) { + return; + } +#endif + + /* Check if it is possible to transmit (TDFE flag) */ + while (obj->serial.uart->FSR.BIT.TDFE == 0) { + /* Wait */ + } + + /* Write the receiving data in TDR */ + obj->serial.uart->FTDR.BYTE = (uint8_t)c; + + /* Clear TDFE and TEND flag */ + obj->serial.uart->FSR.WORD &= ~0x0060u; +} + +int serial_readable(serial_t *obj) { + if (obj->serial.uart->FSR.BIT.RDF == 0) { + return 0; + } else { + return 1; + } +} + +int serial_writable(serial_t *obj) { +#if defined(PRINTF_NOT_USE) + if ((int)obj->serial.ch == NC) { + return 0; + } +#endif + if (obj->serial.uart->FSR.BIT.TDFE == 0) { + return 0; + } else { + return 1; + } +} + +void serial_clear(serial_t *obj) { +#if defined(PRINTF_NOT_USE) + if ((int)obj->serial.ch == NC) { + return; + } +#endif + core_util_critical_section_enter(); + obj->serial.uart->FCR.WORD |= 0x0006u; // TFRST = 1, RFRST = 1 + obj->serial.uart->FCR.WORD &= ~0x0006u; // TFRST = 0, RFRST = 0 + obj->serial.uart->FSR.WORD &= ~0x0093u; // ER, BRK, RDF, DR = 0 + core_util_critical_section_exit(); +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + core_util_critical_section_enter(); + obj->serial.uart->SCR.BIT.TE = 0; + core_util_critical_section_exit(); +} + +void serial_break_clear(serial_t *obj) { +#if defined(PRINTF_NOT_USE) + if ((int)obj->serial.ch == NC) { + return; + } +#endif + core_util_critical_section_enter(); + obj->serial.uart->SCR.BIT.TE = 1; + core_util_critical_section_exit(); +} + +#if DEVICE_SERIAL_FC +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { + // determine the UART to use + + if (type == FlowControlRTSCTS) { + core_util_critical_section_enter(); + obj->serial.uart->FCR.BIT.MCE = 0x1; // CTS/RTS enable + core_util_critical_section_exit(); + pinmap_pinout(rxflow, PinMap_UART_RTS); + pinmap_pinout(txflow, PinMap_UART_CTS); + } else { + core_util_critical_section_enter(); + obj->serial.uart->FCR.BIT.MCE = 0x0; // CTS/RTS diable + core_util_critical_section_exit(); + } +} +#endif + +static uint8_t serial_available_buffer(serial_t *obj) { + return 1; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} + +#if DEVICE_SERIAL_ASYNCH + +/****************************************************************************** + * ASYNCHRONOUS HAL + ******************************************************************************/ +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) { + int i; + buffer_t *buf = &obj->tx_buff; + struct serial_global_data_s *data = uart_data + obj->serial.ch; + + if (tx_length == 0) { + return 0; + } + + buf->buffer = (void *)tx; + buf->length = tx_length * tx_width / 8; + buf->pos = 0; + buf->width = tx_width; + data->tranferring_obj = obj; + data->async_tx_callback = handler; + serial_irq_set(obj, TxIrq, 1); + + while (!serial_writable(obj)); + i = buf->length; + if (serial_available_buffer(obj) < i) { + i = serial_available_buffer(obj); + } + do { + uint8_t c = *(uint8_t *)buf->buffer; + obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1; + ++buf->pos; + obj->serial.uart->FTDR.BYTE = c; + obj->serial.uart->FSR.WORD &= ~0x0060u; + } while (--i); + + return buf->length; +} + +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, + uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) { + buffer_t *buf = &obj->rx_buff; + struct serial_global_data_s *data = uart_data + obj->serial.ch; + + if (rx_length == 0) { + return; + } + + buf->buffer = rx; + buf->length = rx_length * rx_width / 8; + buf->pos = 0; + buf->width = rx_width; + obj->char_match = char_match; + obj->char_found = 0; + data->receiving_obj = obj; + data->async_rx_callback = handler; + data->event = 0; + data->wanted_rx_events = event; + + serial_irq_set(obj, RxIrq, 1); + serial_irq_err_set(obj, 1); +} + +uint8_t serial_tx_active(serial_t *obj) { + return uart_data[obj->serial.ch].tranferring_obj != NULL; +} + +uint8_t serial_rx_active(serial_t *obj) { + return uart_data[obj->serial.ch].receiving_obj != NULL; +} + +int serial_irq_handler_asynch(serial_t *obj) { + return uart_data[obj->serial.ch].event; +} + +void serial_tx_abort_asynch(serial_t *obj) { + uart_data[obj->serial.ch].tranferring_obj = NULL; + obj->serial.uart->FCR.BIT.TFRST = 1; + obj->serial.uart->FCR.BIT.TFRST = 0; +} + +void serial_rx_abort_asynch(serial_t *obj) { + uart_data[obj->serial.ch].receiving_obj = NULL; + obj->serial.uart->FCR.BIT.RFRST = 1; + obj->serial.uart->FCR.BIT.RFRST = 0; +} + +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/sleep.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/sleep.c new file mode 100644 index 0000000..8f3759f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/sleep.c @@ -0,0 +1,176 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" +#include "cmsis.h" +#include "mbed_interface.h" +#include "mbed_critical.h" +#include "iodefine.h" + +#if DEVICE_SLEEP +static volatile uint8_t wk_CPGSTBCR3; +static volatile uint8_t wk_CPGSTBCR4; +static volatile uint8_t wk_CPGSTBCR5; +static volatile uint8_t wk_CPGSTBCR6; +static volatile uint8_t wk_CPGSTBCR7; +static volatile uint8_t wk_CPGSTBCR8; +static volatile uint8_t wk_CPGSTBCR9; +static volatile uint8_t wk_CPGSTBCR10; + +typedef struct { + volatile uint8_t * p_wk_stbcr; + volatile uint8_t * p_stbcr; + volatile uint8_t * p_stbreq; + volatile uint8_t * p_stback; + uint8_t mstp; + uint8_t stbrq; +} module_stanby_t; + +static const module_stanby_t module_stanby[] = { + {&wk_CPGSTBCR5, &CPG.STBCR5.BYTE, &CPG.STBREQ1.BYTE, &CPG.STBACK1.BYTE, 0x40, 0x01}, /* CEU */ + {&wk_CPGSTBCR5, &CPG.STBCR5.BYTE, &CPG.STBREQ1.BYTE, &CPG.STBACK1.BYTE, 0x02, 0x08}, /* JCU */ + {&wk_CPGSTBCR6, &CPG.STBCR6.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x40, 0x80}, /* VIN */ + {&wk_CPGSTBCR6, &CPG.STBCR6.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x20, 0x40}, /* ethernet0 */ + {&wk_CPGSTBCR6, &CPG.STBCR6.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x10, 0x40}, /* ethernet1 */ + {&wk_CPGSTBCR6, &CPG.STBCR6.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x08, 0x40}, /* ethernet PTP */ + {&wk_CPGSTBCR6, &CPG.STBCR6.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x04, 0x40}, /* ethernet M */ + {&wk_CPGSTBCR6, &CPG.STBCR6.BYTE, &CPG.STBREQ3.BYTE, &CPG.STBACK3.BYTE, 0x02, 0x03}, /* USB host 0 */ + {&wk_CPGSTBCR6, &CPG.STBCR6.BYTE, &CPG.STBREQ3.BYTE, &CPG.STBACK3.BYTE, 0x01, 0x0C}, /* USB host 1 */ + {&wk_CPGSTBCR7, &CPG.STBCR7.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x80, 0x08}, /* IMR */ + {&wk_CPGSTBCR7, &CPG.STBCR7.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x40, 0x03}, /* DAVE-2D */ + {&wk_CPGSTBCR8, &CPG.STBCR8.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x02, 0x20}, /* VDC-6 */ + {&wk_CPGSTBCR9, &CPG.STBCR9.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x01, 0x10}, /* DRP */ + {&wk_CPGSTBCR10, &CPG.STBCR10.BYTE, &CPG.STBREQ2.BYTE, &CPG.STBACK2.BYTE, 0x10, 0x04}, /* NAND */ + {&wk_CPGSTBCR10, &CPG.STBCR10.BYTE, &CPG.STBREQ3.BYTE, &CPG.STBACK3.BYTE, 0x08, 0x04}, /* SD host 0 */ + {&wk_CPGSTBCR10, &CPG.STBCR10.BYTE, &CPG.STBREQ3.BYTE, &CPG.STBACK3.BYTE, 0x02, 0x02}, /* SD host 1 */ + {0, 0, 0, 0, 0} /* None */ +}; + +static void module_standby_in(void) { + volatile uint32_t cnt; + volatile uint8_t dummy_8; + const module_stanby_t * p_module = &module_stanby[0]; + + while (p_module->p_wk_stbcr != 0) { + if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) { + *p_module->p_stbreq |= p_module->stbrq; + dummy_8 = *p_module->p_stbreq; + for (cnt = 0; cnt < 1000; cnt++) { // wait time + if ((*p_module->p_stback & p_module->stbrq) == p_module->stbrq) { + break; + } + } + *p_module->p_stbcr |= p_module->mstp; + dummy_8 = *p_module->p_stbcr; + } + p_module++; + } + (void)dummy_8; +} + +static void module_standby_out(void) { + volatile uint32_t cnt; + volatile uint8_t dummy_8; + const module_stanby_t * p_module = &module_stanby[0]; + + while (p_module->p_wk_stbcr != 0) { + if ((*p_module->p_wk_stbcr & p_module->mstp) == 0) { + *p_module->p_stbreq &= ~(p_module->stbrq); + dummy_8 = *p_module->p_stbreq; + for (cnt = 0; cnt < 1000; cnt++) { + if ((*p_module->p_stback & p_module->stbrq) == 0) { + break; + } + } + } + p_module++; + } + (void)dummy_8; +} + +void hal_sleep(void) { + // Transition to Sleep Mode + __WFI(); +} + +void hal_deepsleep(void) { + volatile uint8_t dummy_8; + + core_util_critical_section_enter(); + /* For powerdown the peripheral module, save current standby control register values(just in case) */ + wk_CPGSTBCR3 = CPG.STBCR3.BYTE; + wk_CPGSTBCR4 = CPG.STBCR4.BYTE; + wk_CPGSTBCR5 = CPG.STBCR5.BYTE; + wk_CPGSTBCR6 = CPG.STBCR6.BYTE; + wk_CPGSTBCR7 = CPG.STBCR7.BYTE; + wk_CPGSTBCR8 = CPG.STBCR8.BYTE; + wk_CPGSTBCR9 = CPG.STBCR9.BYTE; + wk_CPGSTBCR10 = CPG.STBCR10.BYTE; + + /* non */ + CPG.STBCR3.BYTE = 0xFF; + dummy_8 = CPG.STBCR3.BYTE; + /* non */ + CPG.STBCR4.BYTE = 0xFF; + dummy_8 = CPG.STBCR4.BYTE; + /* Realtime Clock, CEU, JCU */ + CPG.STBCR5.BYTE |= ~(0x4A); + dummy_8 = CPG.STBCR5.BYTE; + /* VIN, ethernet0, ethernet1, ethernet PTP, ethernet M, USB host 0, USB host 1 */ + CPG.STBCR6.BYTE |= ~(0x7F); + dummy_8 = CPG.STBCR6.BYTE; + /* IMR, DAVE-2D */ + CPG.STBCR7.BYTE |= ~(0xC0); + dummy_8 = CPG.STBCR7.BYTE; + /* VDC-6 */ + CPG.STBCR8.BYTE |= ~(0x02); + dummy_8 = CPG.STBCR8.BYTE; + /* DRP */ + CPG.STBCR9.BYTE |= ~(0x01); + dummy_8 = CPG.STBCR9.BYTE; + /* NAND, SD host 0, SD host 1 */ + CPG.STBCR10.BYTE |= ~(0x1A); + dummy_8 = CPG.STBCR10.BYTE; + + module_standby_in(); + + // Transition to Sleep Mode + __WFI(); + + /* Revert standby control register values */ + CPG.STBCR3.BYTE = wk_CPGSTBCR3; + dummy_8 = CPG.STBCR3.BYTE; + CPG.STBCR4.BYTE = wk_CPGSTBCR4; + dummy_8 = CPG.STBCR4.BYTE; + CPG.STBCR5.BYTE = wk_CPGSTBCR5; + dummy_8 = CPG.STBCR5.BYTE; + CPG.STBCR6.BYTE = wk_CPGSTBCR6; + dummy_8 = CPG.STBCR6.BYTE; + CPG.STBCR7.BYTE = wk_CPGSTBCR7; + dummy_8 = CPG.STBCR7.BYTE; + CPG.STBCR8.BYTE = wk_CPGSTBCR8; + dummy_8 = CPG.STBCR8.BYTE; + CPG.STBCR9.BYTE = wk_CPGSTBCR9; + dummy_8 = CPG.STBCR9.BYTE; + CPG.STBCR10.BYTE = wk_CPGSTBCR10; + dummy_8 = CPG.STBCR10.BYTE; + + module_standby_out(); + core_util_critical_section_exit(); + + (void)dummy_8; +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/spi_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/spi_api.c new file mode 100644 index 0000000..141f924 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/spi_api.c @@ -0,0 +1,567 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if DEVICE_SPI +#include "mbed_assert.h" +#include + +#include "spi_api.h" +#include "cmsis.h" +#include "PeripheralPins.h" +#include "mbed_error.h" +#include "RZ_A2_Init.h" +#include "mbed_drv_cfg.h" + +static const volatile struct st_rspi *RSPI[] = { + &RSPI0, &RSPI1, &RSPI2 +}; + +static inline void spi_disable(spi_t *obj); +static inline void spi_enable(spi_t *obj); +static inline int spi_readable(spi_t *obj); +static inline void spi_write(spi_t *obj, int value); +static inline int spi_read(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + volatile uint8_t dummy; + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + uint32_t spi = pinmap_merge(spi_data, spi_cntl); + + MBED_ASSERT((int)spi != NC); + + obj->spi.spi = (struct st_rspi *)RSPI[spi]; + obj->spi.index = spi; + + // enable power and clocking + CPG.STBCR9.BYTE &= ~(0x80 >> spi); + dummy = CPG.STBCR9.BYTE; + (void)dummy; + + obj->spi.spi->SPCR.BYTE = 0x00; // CTRL to 0 + obj->spi.spi->SPSCR.BYTE = 0x00; // no sequential operation + obj->spi.spi->SSLP.BYTE = 0x00; // SSL 'L' active + obj->spi.spi->SPDCR.BYTE = 0x20; // byte access + obj->spi.spi->SPCKD.BYTE = 0x00; // SSL -> enable CLK delay : 1RSPCK + obj->spi.spi->SSLND.BYTE = 0x00; // CLK end -> SSL neg delay : 1RSPCK + obj->spi.spi->SPND.BYTE = 0x00; // delay between CMD : 1RSPCK + 2P1CLK + obj->spi.spi->SPPCR.BYTE = 0x20; // MOSI Idle fixed value equals 0 + obj->spi.spi->SPBFCR.BYTE = 0xf0; // and set trigger count: read 1, write 1 + obj->spi.spi->SPBFCR.BYTE = 0x30; // and reset buffer + + // pin out the spi pins + if ((int)mosi != NC) { + pinmap_pinout(mosi, PinMap_SPI_MOSI); + } + if ((int)miso != NC) { + pinmap_pinout(miso, PinMap_SPI_MISO); + } + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if ((int)ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + int DSS; // DSS (data select size) + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + uint16_t tmp = 0; + uint16_t mask = 0xf03; + uint16_t wk_spcmd0; + uint8_t splw; + + switch (mode) { + case 0: + case 1: + case 2: + case 3: + // Do Nothing + break; + default: + error("SPI format error"); + return; + } + + switch (bits) { + case 8: + DSS = 0x7; + splw = 0x20; + break; + case 16: + DSS = 0xf; + splw = 0x40; + break; + case 32: + DSS = 0x2; + splw = 0x60; + break; + default: + error("SPI module don't support other than 8/16/32bits"); + return; + } + tmp |= phase; + tmp |= (polarity << 1); + tmp |= (DSS << 8); + obj->spi.bits = bits; + + spi_disable(obj); + wk_spcmd0 = obj->spi.spi->SPCMD0.WORD; + wk_spcmd0 &= ~mask; + wk_spcmd0 |= (mask & tmp); + obj->spi.spi->SPCMD0.WORD = wk_spcmd0; + obj->spi.spi->SPDCR.BYTE = splw; + if (slave) { + obj->spi.spi->SPCR.BYTE &=~(1 << 3); // MSTR to 0 + } else { + obj->spi.spi->SPCR.BYTE |= (1 << 3); // MSTR to 1 + } + spi_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + uint32_t pclk_base; + uint32_t div; + uint32_t brdv = 0; + uint32_t hz_max; + uint32_t hz_min; + uint16_t mask = 0x000c; + uint16_t wk_spcmd0; + + /* set PCLK */ + if (RZ_A2_IsClockMode0() == false) { + pclk_base = CM1_RENESAS_RZ_A2_P1_CLK; + } else { + pclk_base = CM0_RENESAS_RZ_A2_P1_CLK; + } + + hz_min = pclk_base / 2 / 256 / 8; + hz_max = pclk_base / 2; + if ((uint32_t)hz < hz_min) { + hz = hz_min; + } + if ((uint32_t)hz > hz_max) { + hz = hz_max; + } + + div = (pclk_base / hz / 2); + while (div > 256) { + div >>= 1; + brdv++; + } + div -= 1; + brdv = (brdv << 2); + + spi_disable(obj); + obj->spi.spi->SPBR.BYTE = div; + wk_spcmd0 = obj->spi.spi->SPCMD0.WORD; + wk_spcmd0 &= ~mask; + wk_spcmd0 |= (mask & brdv); + obj->spi.spi->SPCMD0.WORD = wk_spcmd0; + spi_enable(obj); +} + +static inline void spi_disable(spi_t *obj) { + obj->spi.spi->SPCR.BYTE &= ~(1 << 6); // SPE to 0 +} + +static inline void spi_enable(spi_t *obj) { + obj->spi.spi->SPCR.BYTE |= (1 << 6); // SPE to 1 +} + +static inline int spi_readable(spi_t *obj) { + return obj->spi.spi->SPSR.BYTE & (1 << 7); // SPRF +} + +static inline int spi_tend(spi_t *obj) { + return obj->spi.spi->SPSR.BYTE & (1 << 6); // TEND +} + +static inline void spi_write(spi_t *obj, int value) { + if (obj->spi.bits == 8) { + obj->spi.spi->SPDR.BYTE.LL = (uint8_t)value; + } else if (obj->spi.bits == 16) { + obj->spi.spi->SPDR.WORD.L = (uint16_t)value; + } else { + obj->spi.spi->SPDR.LONG = (uint32_t)value; + } +} + +static inline int spi_read(spi_t *obj) { + int read_data; + + if (obj->spi.bits == 8) { + read_data = obj->spi.spi->SPDR.BYTE.LL; + } else if (obj->spi.bits == 16) { + read_data = obj->spi.spi->SPDR.WORD.L; + } else { + read_data = obj->spi.spi->SPDR.LONG; + } + + return read_data; +} + +int spi_master_write(spi_t *obj, int value) { + spi_write(obj, value); + while(!spi_tend(obj)); + return spi_read(obj); +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) { + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +int spi_slave_receive(spi_t *obj) { + return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return spi_read(obj); +} + +void spi_slave_write(spi_t *obj, int value) { + spi_write(obj, value); +} + +int spi_busy(spi_t *obj) { + return 0; +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#if DEVICE_SPI_ASYNCH + +#define SPI_NUM 3 +#define IRQ_NUM 2 + +static void spi_irqs_set(spi_t *obj, uint32_t enable); +static void spi_async_write(spi_t *obj); +static void spi_async_read(spi_t *obj); + +static void spi0_rx_irq(void); +static void spi0_er_irq(void); +static void spi1_rx_irq(void); +static void spi1_er_irq(void); +static void spi2_rx_irq(void); +static void spi2_er_irq(void); + +static const IRQn_Type irq_set_tbl[SPI_NUM][IRQ_NUM] = { + {SPRI0_IRQn, SPEI0_IRQn}, + {SPRI1_IRQn, SPEI1_IRQn}, + {SPRI2_IRQn, SPEI2_IRQn}, +}; + +static const IRQHandler hander_set_tbl[SPI_NUM][IRQ_NUM] = { + {spi0_rx_irq, spi0_er_irq}, + {spi1_rx_irq, spi1_er_irq}, + {spi2_rx_irq, spi2_er_irq}, +}; + +struct spi_global_data_s { + spi_t *async_obj; + uint32_t async_callback, event, wanted_events; +}; + +static struct spi_global_data_s spi_data[SPI_NUM]; + +static void spi_rx_irq(uint32_t index) +{ + spi_t *obj = spi_data[index].async_obj; + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + spi_async_read(obj); + } else { + if (obj->rx_buff.buffer && obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; + if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) { + spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE; + } + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + ((void (*)())spi_data[obj->spi.index].async_callback)(); + return; + } + spi_read(obj); + } + if (obj->tx_buff.buffer) { + if (obj->tx_buff.pos == obj->tx_buff.length) { + spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; + if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) { + spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE; + } + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + ((void (*)())spi_data[obj->spi.index].async_callback)(); + } else { + spi_async_write(obj); + } + } else { + if (obj->rx_buff.pos == obj->rx_buff.length) { + spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; + if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) { + spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE; + } + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + ((void (*)())spi_data[obj->spi.index].async_callback)(); + } else { + spi_async_write(obj); + } + } +} + +static void spi_err_irq(uint32_t index) +{ + spi_t *obj = spi_data[index].async_obj; + spi_abort_asynch(obj); + spi_data[index].event = SPI_EVENT_ERROR; + if (spi_data[index].wanted_events & SPI_EVENT_ERROR) { + ((void (*)())spi_data[index].async_callback)(); + } +} + +static void spi0_rx_irq(void) { + spi_rx_irq(0); +} +static void spi0_er_irq(void) { + spi_err_irq(0); +} +static void spi1_rx_irq(void) { + spi_rx_irq(1); +} +static void spi1_er_irq(void) { + spi_err_irq(1); +} +static void spi2_rx_irq(void) { + spi_rx_irq(2); +} +static void spi2_er_irq(void) { + spi_err_irq(2); +} + +static void spi_irqs_set(spi_t *obj, uint32_t enable) +{ + int i; + const IRQn_Type *irqTable = irq_set_tbl[obj->spi.index]; + const IRQHandler *handlerTable = hander_set_tbl[obj->spi.index]; + for (i = 0; i < IRQ_NUM; ++i) { + if (enable) { + InterruptHandlerRegister(irqTable[i], handlerTable[i]); + GIC_SetPriority(irqTable[i], 5); + GIC_SetConfiguration(irqTable[i], 1); + GIC_EnableIRQ(irqTable[i]); + } else { + GIC_DisableIRQ(irqTable[i]); + } + } + if (enable) { + obj->spi.spi->SPCR.BYTE |= (1 << 4) | (1 << 7); + } else { + obj->spi.spi->SPCR.BYTE &= ~((1 << 4) | (1 << 7)); + } +} + +static void spi_async_write(spi_t *obj) +{ + uint8_t **width8; + uint16_t **width16; + uint32_t **width32; + + if (obj->tx_buff.buffer) { + switch (obj->tx_buff.width) { + case 8: + width8 = (uint8_t **)&obj->tx_buff.buffer; + spi_write(obj, **width8); + ++*width8; + obj->tx_buff.pos += sizeof(uint8_t); + break; + + case 16: + width16 = (uint16_t **)&obj->tx_buff.buffer; + spi_write(obj, **width16); + ++*width16; + obj->tx_buff.pos += sizeof(uint16_t); + break; + + case 32: + width32 = (uint32_t **)&obj->tx_buff.buffer; + spi_write(obj, **width32); + ++*width32; + obj->tx_buff.pos += sizeof(uint32_t); + break; + + default: + MBED_ASSERT(0); + break; + } + } else { + spi_write(obj, SPI_FILL_WORD); + } +} + +static void spi_async_read(spi_t *obj) +{ + uint8_t **width8; + uint16_t **width16; + uint32_t **width32; + + switch (obj->rx_buff.width) { + case 8: + width8 = (uint8_t **)&obj->rx_buff.buffer; + **width8 = spi_read(obj); + ++*width8; + obj->rx_buff.pos += sizeof(uint8_t); + break; + + case 16: + width16 = (uint16_t **)&obj->rx_buff.buffer; + **width16 = spi_read(obj); + ++*width16; + obj->rx_buff.pos += sizeof(uint16_t); + break; + + case 32: + width32 = (uint32_t **)&obj->rx_buff.buffer; + **width32 = spi_read(obj); + ++*width32; + obj->rx_buff.pos += sizeof(uint32_t); + break; + + default: + MBED_ASSERT(0); + break; + } +} + +/****************************************************************************** + * ASYNCHRONOUS HAL + ******************************************************************************/ + +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + int i; + MBED_ASSERT(obj); + MBED_ASSERT(tx || rx); + MBED_ASSERT(tx && ! rx ? tx_length : 1); + MBED_ASSERT(rx && ! tx ? rx_length : 1); + MBED_ASSERT(obj->spi.spi->SPCR.BYTE & (1 << 3)); /* Slave mode */ + MBED_ASSERT(bit_width == 8 || bit_width == 16 || bit_width == 32); + + if (tx_length) { + obj->tx_buff.buffer = (void *)tx; + } else { + obj->tx_buff.buffer = NULL; + } + obj->tx_buff.length = tx_length * bit_width / 8; + obj->tx_buff.pos = 0; + obj->tx_buff.width = bit_width; + if (rx_length) { + obj->rx_buff.buffer = rx; + } else { + obj->rx_buff.buffer = NULL; + } + obj->rx_buff.length = rx_length * bit_width / 8; + obj->rx_buff.pos = 0; + obj->rx_buff.width = bit_width; + for (i = 0; i < (int)obj->rx_buff.length; i++) { + ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_CHAR; + } + + spi_data[obj->spi.index].async_callback = handler; + spi_data[obj->spi.index].async_obj = obj; + spi_data[obj->spi.index].event = 0; + spi_data[obj->spi.index].wanted_events = event; + + spi_irqs_set(obj, 1); + + spi_async_write(obj); +} + +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + return spi_data[obj->spi.index].event; +} + +uint8_t spi_active(spi_t *obj) +{ + return spi_data[obj->spi.index].async_obj != NULL; +} + +void spi_abort_asynch(spi_t *obj) +{ + spi_disable(obj); + spi_irqs_set(obj, 0); + spi_data[obj->spi.index].async_obj = NULL; + spi_enable(obj); +} + +#endif +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/spibsc.h b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/spibsc.h new file mode 100644 index 0000000..3b41226 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/spibsc.h @@ -0,0 +1,203 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2016-2020 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/****************************************************************************** +* File Name : spibsc.h +* $Rev: 125 $ +* $Date:: 2016-09-20 11:08:14 +0900#$ +* Description : +******************************************************************************/ +/* Copyright (c) 2016-2020 Renesas Electronics Corporation. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _SPIBSC_H_ +#define _SPIBSC_H_ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "r_typedefs.h" +#include "iodefine.h" + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define SPIBSC_COUNT (1u) + +#define SPIBSC_CMNCR_MD_EXTRD (0u) +#define SPIBSC_CMNCR_MD_SPI (1u) + +#define SPIBSC_OUTPUT_LOW (0u) +#define SPIBSC_OUTPUT_HIGH (1u) +#define SPIBSC_OUTPUT_LAST (2u) +#define SPIBSC_OUTPUT_HiZ (3u) + +#define SPIBSC_CMNCR_CPHAT_EVEN (0u) +#define SPIBSC_CMNCR_CPHAT_ODD (1u) + +#define SPIBSC_CMNCR_CPHAR_ODD (0u) +#define SPIBSC_CMNCR_CPHAR_EVEN (1u) + +#define SPIBSC_CMNCR_SSLP_LOW (0u) +#define SPIBSC_CMNCR_SSLP_HIGH (1u) + +#define SPIBSC_CMNCR_CPOL_LOW (0u) +#define SPIBSC_CMNCR_CPOL_HIGH (1u) + +#define SPIBSC_CMNCR_BSZ_SINGLE (0u) +#define SPIBSC_CMNCR_BSZ_DUAL (1u) + +#define SPIBSC_DELAY_1SPBCLK (0u) +#define SPIBSC_DELAY_2SPBCLK (1u) +#define SPIBSC_DELAY_3SPBCLK (2u) +#define SPIBSC_DELAY_4SPBCLK (3u) +#define SPIBSC_DELAY_5SPBCLK (4u) +#define SPIBSC_DELAY_6SPBCLK (5u) +#define SPIBSC_DELAY_7SPBCLK (6u) +#define SPIBSC_DELAY_8SPBCLK (7u) + + +#define SPIBSC_BURST_1 (0x00u) +#define SPIBSC_BURST_2 (0x01u) +#define SPIBSC_BURST_3 (0x02u) +#define SPIBSC_BURST_4 (0x03u) +#define SPIBSC_BURST_5 (0x04u) +#define SPIBSC_BURST_6 (0x05u) +#define SPIBSC_BURST_7 (0x06u) +#define SPIBSC_BURST_8 (0x07u) +#define SPIBSC_BURST_9 (0x08u) +#define SPIBSC_BURST_10 (0x09u) +#define SPIBSC_BURST_11 (0x0au) +#define SPIBSC_BURST_12 (0x0bu) +#define SPIBSC_BURST_13 (0x0cu) +#define SPIBSC_BURST_14 (0x0du) +#define SPIBSC_BURST_15 (0x0eu) +#define SPIBSC_BURST_16 (0x0fu) + +#define SPIBSC_BURST_DISABLE (0u) +#define SPIBSC_BURST_ENABLE (1u) + +#define SPIBSC_DRCR_RCF_EXE (1u) + +#define SPIBSC_SSL_NEGATE (0u) +#define SPIBSC_TRANS_END (1u) + +#define SPIBSC_1BIT (0u) +#define SPIBSC_2BIT (1u) +#define SPIBSC_4BIT (2u) + +#define SPIBSC_OUTPUT_DISABLE (0u) +#define SPIBSC_OUTPUT_ENABLE (1u) +#define SPIBSC_OUTPUT_ADDR_24 (0x07u) +#define SPIBSC_OUTPUT_ADDR_32 (0x0fu) +#define SPIBSC_OUTPUT_OPD_3 (0x08u) +#define SPIBSC_OUTPUT_OPD_32 (0x0cu) +#define SPIBSC_OUTPUT_OPD_321 (0x0eu) +#define SPIBSC_OUTPUT_OPD_3210 (0x0fu) + +#define SPIBSC_OUTPUT_SPID_8 (0x08u) +#define SPIBSC_OUTPUT_SPID_16 (0x0cu) +#define SPIBSC_OUTPUT_SPID_32 (0x0fu) + +#define SPIBSC_SPISSL_NEGATE (0u) +#define SPIBSC_SPISSL_KEEP (1u) + +#define SPIBSC_SPIDATA_DISABLE (0u) +#define SPIBSC_SPIDATA_ENABLE (1u) + +#define SPIBSC_SPI_DISABLE (0u) +#define SPIBSC_SPI_ENABLE (1u) + + +/* Use for setting of the DME bit of "data read enable register"(DRENR) */ +#define SPIBSC_DUMMY_CYC_DISABLE (0u) +#define SPIBSC_DUMMY_CYC_ENABLE (1u) + +/* Use for setting of the DMCYC [2:0] bit of "data read dummy cycle register"(DRDMCR) */ +#define SPIBSC_DUMMY_1CYC (0u) +#define SPIBSC_DUMMY_2CYC (1u) +#define SPIBSC_DUMMY_3CYC (2u) +#define SPIBSC_DUMMY_4CYC (3u) +#define SPIBSC_DUMMY_5CYC (4u) +#define SPIBSC_DUMMY_6CYC (5u) +#define SPIBSC_DUMMY_7CYC (6u) +#define SPIBSC_DUMMY_8CYC (7u) + +/* Use for setting of "data read DDR enable register"(DRDRENR) */ +#define SPIBSC_SDR_TRANS (0u) +#define SPIBSC_DDR_TRANS (1u) + +/* Use for setting the CKDLY regsiter */ +#define SPIBSC_CKDLY_DEFAULT (0x0000A504uL) /* Initial value */ +#define SPIBSC_CKDLY_TUNING (0x0000A50AuL) /* Shorten the data input setup time and extend the data hold time */ + +/* Use for setting the SPODLY regsiter */ +#define SPIBSC_SPODLY_DEFAULT (0xA5000000uL) /* Initial value */ +#define SPIBSC_SPODLY_TUNING (0xA5001111uL) /* Delay the data output delay/hold/buffer-on/buffer-off time */ + +/* Use for setting of the CAL bit of "Phy control register"(PHYCNT) */ +#define SPIBSC_CAL_DISABLE (0u) +#define SPIBSC_CAL_ENABLE (1u) + +/* Use for setting of the OCTA[1:0] bit of "Phy control register"(PHYCNT) */ +#define SPIBSC_OCTA_HYPER (0u) +#define SPIBSC_OCTA_ALTER_ALIG (1u) +#define SPIBSC_OCTA_ORDER_ALIG (2u) + +/* Use for setting of the EXDS bit of "Phy control register"(PHYCNT) */ +#define SPISBSC_PHYMEM_DATA_STROBE_DISABLE (0u) +#define SPISBSC_PHYMEM_DATA_STROBE_ENABLE (1u) + +/* Use for setting of the OCT bit of "Phy control register"(PHYCNT) */ +#define SPIBSC_PHYMEM_OCT_DDR_PROTOCOL_DISABLE (0u) +#define SPIBSC_PHYMEM_OCT_DDR_PROTOCOL_ENABLE (1u) + +/* Use for setting of the HS bit of "Phy control register"(PHYCNT) */ +#define SPIBSC_PHYMEM_HIGH_SPEED_DISABLE (0u) +#define SPIBSC_PHYMEM_HIGH_SPEED_ENABLE (1u) + +/* Use for setting of the WBUT and WBUF2 bits of "Phy control register"(PHYCNT) */ +#define SPIBSC_PHYMEM_WRITE_BUFFER_DISABLE (0u) +#define SPIBSC_PHYMEM_WRITE_BUFFER_ENABLE (1u) + +/* Use for setting of the PHYMEM[1:0]bit of "Phy control register"(PHYCNT) */ +#define SPIBSC_PHYMEM_SDR (0u) +#define SPIBSC_PHYMEM_DDR (1u) +#define SPIBSC_PHYMEM_HYPER (3u) + +#endif /* _SPIBSC_H_ */ + +/* End of File */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A2XX/us_ticker.c b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/us_ticker.c new file mode 100644 index 0000000..431e4ff --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A2XX/us_ticker.c @@ -0,0 +1,97 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "us_ticker_api.h" +#include "mbed_drv_cfg.h" + +#define SHIFT_NUM 5 /* P0/32 */ + +static int us_ticker_inited = 0; + +void us_ticker_init(void) +{ + GIC_DisableIRQ(OSTMI1_IRQn); + GIC_ClearPendingIRQ(OSTMI1_IRQn); + + /* Power Control for Peripherals */ + volatile uint8_t dummy_buf; + CPG.STBCR3.BYTE &= ~(0x20u); + dummy_buf = CPG.STBCR3.BYTE; /* (Dummy read) */ + (void)dummy_buf; + + if (us_ticker_inited) return; + us_ticker_inited = 1; + + // timer settings + OSTM1.OSTMnTT.BYTE = 0x01; /* Stop the counter and clears the OSTM1TE bit. */ + OSTM1.OSTMnCTL.BYTE = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ + + OSTM1.OSTMnTS.BYTE = 0x1; /* Start the counter and sets the OSTM0TE bit. */ + + // INTC settings + InterruptHandlerRegister(OSTMI1_IRQn, (void (*)(uint32_t))us_ticker_irq_handler); + GIC_SetPriority(OSTMI1_IRQn, 5); + GIC_SetConfiguration(OSTMI1_IRQn, 3); +} + +void us_ticker_free(void) +{ + GIC_DisableIRQ(OSTMI1_IRQn); + GIC_ClearPendingIRQ(OSTMI1_IRQn); + + /* Power Control for Peripherals */ + volatile uint8_t dummy_buf; + CPG.STBCR3.BYTE |= 0x20u; + dummy_buf = CPG.STBCR3.BYTE; /* (Dummy read) */ + (void)dummy_buf; +} + +uint32_t us_ticker_read() +{ + return (uint32_t)(OSTM1.OSTMnCNT.LONG >> SHIFT_NUM); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + OSTM1.OSTMnCMP.LONG = (uint32_t)(timestamp << SHIFT_NUM); + GIC_EnableIRQ(OSTMI1_IRQn); +} + +void us_ticker_fire_interrupt(void) +{ + GIC_SetPendingIRQ(OSTMI1_IRQn); + GIC_EnableIRQ(OSTMI1_IRQn); +} + +void us_ticker_disable_interrupt(void) +{ + GIC_DisableIRQ(OSTMI1_IRQn); +} + +void us_ticker_clear_interrupt(void) +{ + GIC_ClearPendingIRQ(OSTMI1_IRQn); +} + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + (uint32_t)((float)RENESAS_RZ_A2_P0_CLK * 2 / (float)(1 << SHIFT_NUM) + 0.5f), + (32 - SHIFT_NUM) + }; + return &info; +} + diff --git a/targets/targets.json b/targets/targets.json index c97cb63..37f4862 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -4075,7 +4075,7 @@ "extra_labels_add": [ "RZA1H", "MBRZA1H", - "RZ_A1_EMAC" + "RENESAS_EMAC" ], "components_add": [ "SD", @@ -4148,6 +4148,54 @@ "5501" ] }, + "RZ_A2XX": { + "inherits": ["Target"], + "core": "Cortex-A9", + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "extra_labels": ["RENESAS", "RZ_A2XX"], + "device_has": [ + "SLEEP", + "USTICKER", + "RTC", + "ANALOGIN", + "ETHERNET", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SERIAL_ASYNCH", + "SERIAL_FC", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "STDIO_MESSAGES", + "USBDEVICE" + ], + "program_cycle_s": 2 + }, + "GR_MANGO": { + "inherits": ["RZ_A2XX"], + "extra_labels_add": ["RZA2M", "MBRZA2M", "RENESAS_EMAC"], + "device_has_add": ["EMAC","FLASH"], + "release_versions": ["5"], + "device_name": "R7S921053", + "bootloader_supported": true, + "mbed_rom_start" : "0x50000000", + "mbed_rom_size" : "0x1000000", + "sectors": [[1342177280,4096]], + "overrides": { + "network-default-interface-type": "ETHERNET" + }, + "detect_code": [ + "5502" + ] + + }, "MAX32600MBED": { "inherits": [ "Target" diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index 739fb19..f357b8d 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -313891,6 +313891,50 @@ "sub_family": "RZ_A1LU", "vendor": "Renesas:117" }, + "R7S921053": { + "algorithms": [], + "family": "RZ_A", + "from_pack": { + "pack": "RZ_DFP", + "url": "http://www.keil.com/pack/", + "vendor": "Keil", + "version": "1.2.1" + }, + "memories": { + "IRAM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 33554432, + "start": 4194304, + "startup": false + } + }, + "name": "R7S921053", + "processor": { + "Symmetric": { + "core": "CortexA9", + "fpu": "DoublePrecision", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 0, + 4096 + ] + ], + "sub_family": "RZ_A2M", + "vendor": "Renesas:117" + }, "RC10001": { "algorithms": [], "family": "RC10000 Series",