diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
index 4609a92..d9695c8 100644
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -52,17 +52,24 @@
     #define STACK_SIZE  MBED_CONF_TARGET_BOOT_STACK_SIZE
 #endif
 
+#define ZBT_SRAM2_RAM_FIXED_SIZE  (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
+
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
 LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
-  ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   *(+RO)
-  }
-  ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   *(+RW +ZI)
-  }
-  ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
-  }
+    ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
+      *.o (RESET, +First)
+      *(InRoot$$Sections)
+      *(+RO)
+    }
+
+    ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+    RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
+      *(+RW +ZI)
+    }
+
+    ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
+    }
+
+    ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
+    }
 }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
index 936ee4a..d9f6289 100644
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -52,17 +52,24 @@
     #define STACK_SIZE  MBED_CONF_TARGET_BOOT_STACK_SIZE
 #endif
 
+#define ZBT_SRAM2_RAM_FIXED_SIZE  (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
+
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
 LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
-  ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   *(+RO)
-  }
-  ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   *(+RW +ZI)
-  }
-  ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
-  }
+    ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
+      *.o (RESET, +First)
+      *(InRoot$$Sections)
+      *(+RO)
+    }
+
+    ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+    RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
+      *(+RW +ZI)
+    }
+
+    ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
+    }
+
+    ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
+    }
 }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
index 6ad986d..55e7e57 100644
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -52,17 +52,24 @@
     #define STACK_SIZE  MBED_CONF_TARGET_BOOT_STACK_SIZE
 #endif
 
+#define ZBT_SRAM2_RAM_FIXED_SIZE  (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
+
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
 LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
-  ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   *(+RO)
-  }
-  ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   *(+RW +ZI)
-  }
-  ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
-  }
+    ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
+      *.o (RESET, +First)
+      *(InRoot$$Sections)
+      *(+RO)
+    }
+
+    ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+    RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
+      *(+RW +ZI)
+    }
+
+    ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
+    }
+
+    ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
+    }
 }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
index 121752f..1f0e8cd 100644
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -52,17 +52,24 @@
     #define STACK_SIZE  MBED_CONF_TARGET_BOOT_STACK_SIZE
 #endif
 
+#define ZBT_SRAM2_RAM_FIXED_SIZE  (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
+
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
 LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
-  ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   *(+RO)
-  }
-  ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   *(+RW +ZI)
-  }
-  ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
-  }
+    ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
+      *.o (RESET, +First)
+      *(InRoot$$Sections)
+      *(+RO)
+    }
+
+    ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+    RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
+      *(+RW +ZI)
+    }
+
+    ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
+    }
+
+    ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
+    }
 }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
index 369cce1..feb33e0 100644
--- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
+++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -52,17 +52,24 @@
     #define STACK_SIZE  MBED_CONF_TARGET_BOOT_STACK_SIZE
 #endif
 
+#define ZBT_SRAM2_RAM_FIXED_SIZE  (MBED_CONF_TARGET_BOOT_STACK_SIZE + NVIC_VECTORS_SIZE)
+
 ; The vector table is loaded at address 0x00000000 in Flash memory region.
 LR_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
-  ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   *(+RO)
-  }
-  ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
-  RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   *(+RW +ZI)
-  }
-  ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
-  }
+    ER_IROM1 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
+      *.o (RESET, +First)
+      *(InRoot$$Sections)
+      *(+RO)
+    }
+
+    ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
+    RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
+      *(+RW +ZI)
+    }
+
+    ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (ZBT_SRAM2_SIZE - ZBT_SRAM2_RAM_FIXED_SIZE - (AlignExpr(ImageLimit(RW_IRAM1), 16) - ZBT_SRAM2_START)) { ; Heap growing upward
+    }
+
+    ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
+    }
 }
diff --git a/targets/targets.json b/targets/targets.json
index 76f7fd7..60b0588 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -6415,6 +6415,17 @@
         ],
         "overrides": {
             "network-default-interface-type": "ETHERNET"
+        },
+        "supported_application_profiles" : ["full", "bare-metal"],
+        "supported_c_libs": {
+            "arm": [
+                "std",
+                "small"
+            ],
+            "gcc_arm": [
+                "std",
+                "small"
+            ]
         }
     },
     "FVP_MPS2_M0": {