diff --git a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/CMakeLists.txt b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/CMakeLists.txt index f9c711d..9d9ef33 100644 --- a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/CMakeLists.txt +++ b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/CMakeLists.txt @@ -1,8 +1,8 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -if("MIMXRT1050_EVK" IN_LIST MBED_TARGET_LABELS) - add_subdirectory(TARGET_MIMXRT1050_EVK) +if("MIMXRT1050_EVK" IN_LIST MBED_TARGET_LABELS OR "MIMXRT1060_EVK" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_MIMXRT10x0_EVK) endif() target_include_directories(mbed-emac diff --git a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/CMakeLists.txt b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/CMakeLists.txt deleted file mode 100644 index db07c9f..0000000 --- a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 ARM Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -target_sources(mbed-emac - PRIVATE - hardware_init.c -) diff --git a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c deleted file mode 100644 index 2f6e27f..0000000 --- a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT1050_EVK/hardware_init.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_gpio.h" -#include "fsl_iomuxc.h" -#include "fsl_clock.h" -#include "mbed_wait_api.h" - -/******************************************************************************* - * Code - ******************************************************************************/ -static void BOARD_InitModuleClock(void) -{ - const clock_enet_pll_config_t config = {true, false, 1}; - CLOCK_InitEnetPll(&config); -} - -void kinetis_init_eth_hardware(void) -{ - gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; - - CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ - - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ - 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ - 0xB0A9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ - 0x31u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/6 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Disabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ - 0xB0E9u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: max(200MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - IOMUXC_SetPinConfig( - IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ - 0xB829u); /* Slew Rate Field: Fast Slew Rate - Drive Strength Field: R0/5 - Speed Field: low(50MHz) - Open Drain Enable Field: Open Drain Enabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Pull - Pull Up / Down Config. Field: 100K Ohm Pull Up - Hyst. Enable Field: Hysteresis Disabled */ - - - BOARD_InitModuleClock(); - - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); - - GPIO_PinInit(GPIO1, 9, &gpio_config); - GPIO_PinInit(GPIO1, 10, &gpio_config); - /* pull up the ENET_INT before RESET. */ - GPIO_WritePinOutput(GPIO1, 10, 1); - GPIO_WritePinOutput(GPIO1, 9, 0); - wait_us(1 * 1000); - GPIO_WritePinOutput(GPIO1, 9, 1); -} - -/******************************************************************************* - * EOF - ******************************************************************************/ - - diff --git a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT10x0_EVK/CMakeLists.txt b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT10x0_EVK/CMakeLists.txt new file mode 100644 index 0000000..db07c9f --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT10x0_EVK/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-emac + PRIVATE + hardware_init.c +) diff --git a/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT10x0_EVK/hardware_init.c b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT10x0_EVK/hardware_init.c new file mode 100644 index 0000000..2f6e27f --- /dev/null +++ b/connectivity/drivers/emac/TARGET_NXP_EMAC/TARGET_IMX/TARGET_MIMXRT10x0_EVK/hardware_init.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" +#include "fsl_iomuxc.h" +#include "fsl_clock.h" +#include "mbed_wait_api.h" + +/******************************************************************************* + * Code + ******************************************************************************/ +static void BOARD_InitModuleClock(void) +{ + const clock_enet_pll_config_t config = {true, false, 1}; + CLOCK_InitEnetPll(&config); +} + +void kinetis_init_eth_hardware(void) +{ + gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode}; + + CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ + 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ + 0xB0A9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ + 0x31u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/6 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Disabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ + 0xB0E9u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: max(200MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + IOMUXC_SetPinConfig( + IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ + 0xB829u); /* Slew Rate Field: Fast Slew Rate + Drive Strength Field: R0/5 + Speed Field: low(50MHz) + Open Drain Enable Field: Open Drain Enabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Pull + Pull Up / Down Config. Field: 100K Ohm Pull Up + Hyst. Enable Field: Hysteresis Disabled */ + + + BOARD_InitModuleClock(); + + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); + + GPIO_PinInit(GPIO1, 9, &gpio_config); + GPIO_PinInit(GPIO1, 10, &gpio_config); + /* pull up the ENET_INT before RESET. */ + GPIO_WritePinOutput(GPIO1, 10, 1); + GPIO_WritePinOutput(GPIO1, 9, 0); + wait_us(1 * 1000); + GPIO_WritePinOutput(GPIO1, 9, 1); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ + + diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index bf7e742..b39783b 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -219,7 +219,7 @@ "pbuf-pool-size": 14, "mem-size": 65536 }, - "MIMXRT1050_EVK": { + "MIMXRT105X": { "mem-size": 36560 }, "PORTENTA_H7": { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt index fbceb07..2b43027 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt @@ -1,8 +1,6 @@ # Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -add_subdirectory(TARGET_EVK EXCLUDE_FROM_ALL) - if(${MBED_TOOLCHAIN} STREQUAL "ARM") set(STARTUP_FILE device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S) set(LINKER_FILE device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct) @@ -11,19 +9,31 @@ set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld) endif() -add_library(mbed-mimxrt1050-evk INTERFACE) +# Target for MIMXRT106x/106x common code. +add_library(mbed-mimxrt105x INTERFACE) -target_include_directories(mbed-mimxrt1050-evk +target_include_directories(mbed-mimxrt105x INTERFACE . device drivers ) -target_sources(mbed-mimxrt1050-evk +target_sources(mbed-mimxrt105x INTERFACE usb_device_ch9.c usb_device_class.c + analogin_api.c + serial_api.c + sleep.c + trng_api.c + us_ticker.c + fsl_clock_config.c + PeripheralPins.c + pinmap.c + specific.c + lpm.c + mbed_overrides.c device/system_MIMXRT1052.c @@ -60,7 +70,6 @@ drivers/fsl_flexio_uart_edma.c drivers/fsl_flexram.c drivers/fsl_flexspi.c - drivers/fsl_flexspi_nor_boot.c drivers/fsl_gpc.c drivers/fsl_gpio.c drivers/fsl_gpt.c @@ -97,12 +106,14 @@ ${STARTUP_FILE} ) -target_link_libraries(mbed-mimxrt1050-evk +target_link_libraries(mbed-mimxrt105x INTERFACE mbed-mcuxpresso-mcus - mbed-evk mbed-imx mbed-nxp-usb ) -mbed_set_linker_script(mbed-mimxrt1050-evk ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) +mbed_set_linker_script(mbed-mimxrt105x ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +add_subdirectory(TARGET_EVK EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_TEENSY_4X) \ No newline at end of file diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralNames.h new file mode 100644 index 0000000..fcf725a --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralNames.h @@ -0,0 +1,154 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_1 = 1, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, + UART_5 = 5, + UART_6 = 6, + UART_7 = 7, + UART_8 = 8 +} UARTName; + +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) +#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX +#else +#define STDIO_UART_TX CONSOLE_TX +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) +#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX +#else +#define STDIO_UART_RX CONSOLE_RX +#endif +#define STDIO_UART UART_1 + +#define SION_BIT_SHIFT (3) +#define DAISY_REG_SHIFT (4) +#define DAISY_REG_VALUE_SHIFT (16) + +typedef enum { + I2C_1 = 1, + I2C_2 = 2, + I2C_3 = 3, + I2C_4 = 4, +} I2CName; + +#define PWM_MODULE_SHIFT 2 +#define PWM_SHIFT 8 + +typedef enum { + PWM_1 = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 0 PWMA + PWM_2 = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 0 PWMB + PWM_3 = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 1 PWMA + PWM_4 = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 1 PWMB + PWM_5 = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 2 PWMA + PWM_6 = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 2 PWMB + PWM_7 = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 3 PWMA + PWM_8 = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 3 PWMB + PWM_9 = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 0 PWMA + PWM_10 = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 0 PWMB + PWM_11 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 1 PWMA + PWM_12 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 1 PWMB + PWM_13 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 2 PWMA + PWM_14 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 2 PWMB + PWM_15 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 3 PWMA + PWM_16 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 3 PWMB + PWM_17 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 0 PWMA + PWM_18 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 0 PWMB + PWM_19 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 1 PWMA + PWM_20 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 1 PWMB + PWM_21 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 2 PWMA + PWM_22 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 2 PWMB + PWM_23 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 3 PWMA + PWM_24 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 3 PWMB + PWM_25 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 0 PWMA + PWM_26 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 0 PWMB + PWM_27 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 1 PWMA + PWM_28 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 1 PWMB + PWM_29 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 2 PWMA + PWM_30 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 2 PWMB + PWM_31 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 3 PWMA + PWM_32 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1) // PWM4 Submodule 3 PWMB +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +typedef enum { + ADC1_0 = (1 << ADC_INSTANCE_SHIFT | 0), + ADC1_1 = (1 << ADC_INSTANCE_SHIFT | 1), + ADC1_2 = (1 << ADC_INSTANCE_SHIFT | 2), + ADC1_3 = (1 << ADC_INSTANCE_SHIFT | 3), + ADC1_4 = (1 << ADC_INSTANCE_SHIFT | 4), + ADC1_5 = (1 << ADC_INSTANCE_SHIFT | 5), + ADC1_6 = (1 << ADC_INSTANCE_SHIFT | 6), + ADC1_7 = (1 << ADC_INSTANCE_SHIFT | 7), + ADC1_8 = (1 << ADC_INSTANCE_SHIFT | 8), + ADC1_9 = (1 << ADC_INSTANCE_SHIFT | 9), + ADC1_10 = (1 << ADC_INSTANCE_SHIFT | 10), + ADC1_11 = (1 << ADC_INSTANCE_SHIFT | 11), + ADC1_12 = (1 << ADC_INSTANCE_SHIFT | 12), + ADC1_13 = (1 << ADC_INSTANCE_SHIFT | 13), + ADC1_14 = (1 << ADC_INSTANCE_SHIFT | 14), + ADC1_15 = (1 << ADC_INSTANCE_SHIFT | 15), + ADC2_0 = (2 << ADC_INSTANCE_SHIFT | 0), + ADC2_1 = (2 << ADC_INSTANCE_SHIFT | 1), + ADC2_2 = (2 << ADC_INSTANCE_SHIFT | 2), + ADC2_3 = (2 << ADC_INSTANCE_SHIFT | 3), + ADC2_4 = (2 << ADC_INSTANCE_SHIFT | 4), + ADC2_5 = (2 << ADC_INSTANCE_SHIFT | 5), + ADC2_6 = (2 << ADC_INSTANCE_SHIFT | 6), + ADC2_7 = (2 << ADC_INSTANCE_SHIFT | 7), + ADC2_8 = (2 << ADC_INSTANCE_SHIFT | 8), + ADC2_9 = (2 << ADC_INSTANCE_SHIFT | 9), + ADC2_10 = (2 << ADC_INSTANCE_SHIFT | 10), + ADC2_11 = (2 << ADC_INSTANCE_SHIFT | 11), + ADC2_12 = (2 << ADC_INSTANCE_SHIFT | 12), + ADC2_13 = (2 << ADC_INSTANCE_SHIFT | 13), + ADC2_14 = (2 << ADC_INSTANCE_SHIFT | 14), + ADC2_15 = (2 << ADC_INSTANCE_SHIFT | 15), +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_1 = 1, + SPI_2 = 2, + SPI_3 = 3, + SPI_4 = 4, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralPins.c new file mode 100644 index 0000000..6c867355 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralPins.c @@ -0,0 +1,115 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {GPIO_AD_B1_10, ADC1_15, 5}, + {GPIO_AD_B1_11, ADC2_0, 5}, + {GPIO_AD_B1_04, ADC1_9, 5}, + {GPIO_AD_B1_05, ADC1_10, 5}, + {GPIO_AD_B1_01, ADC1_6, 5}, + {GPIO_AD_B1_00, ADC1_5, 5}, + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {GPIO_AD_B1_01, I2C_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4D0 << DAISY_REG_SHIFT) | (1U << SION_BIT_SHIFT) | 3)}, + + // I2C3 is ALT1 of GPIO_AD_B1_06 + // GPIO_AD_B1_06 is daisy chain input 3 of I2C3 per the IOMUXC_LPI2C3_SDA_SELECT_INPUT register description + {GPIO_AD_B1_06, I2C_3, ((3U << DAISY_REG_VALUE_SHIFT) | (0x4E0 << DAISY_REG_SHIFT) | (1U << SION_BIT_SHIFT) | 1)}, + + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {GPIO_AD_B1_00, I2C_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4CC << DAISY_REG_SHIFT) | (1U << SION_BIT_SHIFT) | 3)}, + + // I2C3 is ALT1 of GPIO_AD_B1_07 + // GPIO_AD_B1_07 is daisy chain input 3 of I2C3 per the IOMUXC_LPI2C3_SCL_SELECT_INPUT register description + {GPIO_AD_B1_07, I2C_3, ((3U << DAISY_REG_VALUE_SHIFT) | (0x4DC << DAISY_REG_SHIFT) | (1U << SION_BIT_SHIFT) | 1)}, + + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {GPIO_AD_B0_12, UART_1, 2}, + {GPIO_AD_B1_06, UART_3, 2}, + {GPIO_AD_B0_02, UART_6, 2}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {GPIO_AD_B0_13, UART_1, 2}, + {GPIO_AD_B1_07, UART_3, 2}, + {GPIO_AD_B0_03, UART_6, 2}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {GPIO_SD_B0_00, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F0 << DAISY_REG_SHIFT) | 4)}, + {GPIO_AD_B0_00, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x510 << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_03, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x520 << DAISY_REG_SHIFT) | 3)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {GPIO_SD_B0_02, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F8 << DAISY_REG_SHIFT) | 4)}, + {GPIO_AD_B0_01, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x518 << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_02, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x528 << DAISY_REG_SHIFT) | 3)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {GPIO_SD_B0_03, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F4 << DAISY_REG_SHIFT) | 4)}, + {GPIO_AD_B0_02, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x514 << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_01, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x524 << DAISY_REG_SHIFT) | 3)}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {GPIO_SD_B0_01, SPI_1, ((0U << DAISY_REG_VALUE_SHIFT) | (0x4EC << DAISY_REG_SHIFT) | 4)}, + {GPIO_AD_B0_03, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x50C << DAISY_REG_SHIFT) | 7)}, + {GPIO_B0_00, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x51C << DAISY_REG_SHIFT) | 3)}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {GPIO_AD_B0_10, PWM_7, ((3U << DAISY_REG_VALUE_SHIFT) | (0x454 << DAISY_REG_SHIFT) | 1)}, + {GPIO_AD_B0_11, PWM_8, ((3U << DAISY_REG_VALUE_SHIFT) | (0x464 << DAISY_REG_SHIFT) | 1)}, + {GPIO_AD_B1_08, PWM_25, ((1U << DAISY_REG_VALUE_SHIFT) | (0x494 << DAISY_REG_SHIFT) | 1)}, + {GPIO_SD_B0_00, PWM_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x458 << DAISY_REG_SHIFT) | 1)}, + {GPIO_SD_B0_01, PWM_2, ((1U << DAISY_REG_VALUE_SHIFT) | (0x468 << DAISY_REG_SHIFT) | 1)}, + {NC , NC , 0} +}; + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/CMakeLists.txt index d347a82..a1776d8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/CMakeLists.txt +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/CMakeLists.txt @@ -1,30 +1,48 @@ # Copyright (c) 2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -add_library(mbed-evk INTERFACE) +# MIMXRT1050_EVK +add_library(mbed-mimxrt1050-evk INTERFACE) -target_include_directories(mbed-evk +target_include_directories(mbed-mimxrt1050-evk INTERFACE . - xip ) -target_sources(mbed-evk +target_sources(mbed-mimxrt1050-evk INTERFACE - analogin_api.c - flash_api.c - fsl_clock_config.c fsl_phy.c - lpm.c - mbed_overrides.c - PeripheralPins.c - pinmap.c - serial_api.c - sleep.c - specific.c - trng_api.c - us_ticker.c + fsl_flexspi_nor_boot.c - xip/evkbimxrt1050_flexspi_nor_config.c - xip/evkbimxrt1050_sdram_ini_dcd.c + TARGET_1050_EVK/flash_api.c + + TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.c + TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c ) + +target_link_libraries(mbed-mimxrt1050-evk + INTERFACE + mbed-mimxrt105x +) + +# MIMXRT1060_EVK +add_library(mbed-mimxrt1060-evk INTERFACE) + +target_include_directories(mbed-mimxrt1060-evk + INTERFACE + . +) + +target_sources(mbed-mimxrt1060-evk + INTERFACE + fsl_phy.c + fsl_flexspi_nor_boot.c + + TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.c + TARGET_1060_EVK/xip/dcd.c +) + +target_link_libraries(mbed-mimxrt1060-evk + INTERFACE + mbed-mimxrt105x +) \ No newline at end of file diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h deleted file mode 100644 index 1c63bb9..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralNames.h +++ /dev/null @@ -1,150 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - OSC32KCLK = 0, -} RTCName; - -typedef enum { - UART_1 = 1, - UART_2 = 2, - UART_3 = 3, - UART_4 = 4, -} UARTName; - -#if defined(MBED_CONF_TARGET_STDIO_UART_TX) -#define STDIO_UART_TX MBED_CONF_TARGET_STDIO_UART_TX -#else -#define STDIO_UART_TX CONSOLE_TX -#endif -#if defined(MBED_CONF_TARGET_STDIO_UART_RX) -#define STDIO_UART_RX MBED_CONF_TARGET_STDIO_UART_RX -#else -#define STDIO_UART_RX CONSOLE_RX -#endif -#define STDIO_UART UART_1 - -#define SION_BIT_SHIFT (3) -#define DAISY_REG_SHIFT (4) -#define DAISY_REG_VALUE_SHIFT (16) - -typedef enum { - I2C_1 = 1, - I2C_2 = 2, - I2C_3 = 3, - I2C_4 = 4, -} I2CName; - -#define PWM_MODULE_SHIFT 2 -#define PWM_SHIFT 8 - -typedef enum { - PWM_1 = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 0 PWMA - PWM_2 = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 0 PWMB - PWM_3 = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 1 PWMA - PWM_4 = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 1 PWMB - PWM_5 = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 2 PWMA - PWM_6 = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 2 PWMB - PWM_7 = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM1 Submodule 3 PWMA - PWM_8 = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM1 Submodule 3 PWMB - PWM_9 = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 0 PWMA - PWM_10 = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 0 PWMB - PWM_11 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 1 PWMA - PWM_12 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 1 PWMB - PWM_13 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 2 PWMA - PWM_14 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 2 PWMB - PWM_15 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM2 Submodule 3 PWMA - PWM_16 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM2 Submodule 3 PWMB - PWM_17 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 0 PWMA - PWM_18 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 0 PWMB - PWM_19 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 1 PWMA - PWM_20 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 1 PWMB - PWM_21 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 2 PWMA - PWM_22 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 2 PWMB - PWM_23 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM3 Submodule 3 PWMA - PWM_24 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1), // PWM3 Submodule 3 PWMB - PWM_25 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 0 PWMA - PWM_26 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 0 PWMB - PWM_27 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 1 PWMA - PWM_28 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 1 PWMB - PWM_29 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 2 PWMA - PWM_30 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1), // PWM4 Submodule 2 PWMB - PWM_31 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0), // PWM4 Submodule 3 PWMA - PWM_32 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1) // PWM4 Submodule 3 PWMB -} PWMName; - -#define ADC_INSTANCE_SHIFT 8 -typedef enum { - ADC1_0 = (1 << ADC_INSTANCE_SHIFT | 0), - ADC1_1 = (1 << ADC_INSTANCE_SHIFT | 1), - ADC1_2 = (1 << ADC_INSTANCE_SHIFT | 2), - ADC1_3 = (1 << ADC_INSTANCE_SHIFT | 3), - ADC1_4 = (1 << ADC_INSTANCE_SHIFT | 4), - ADC1_5 = (1 << ADC_INSTANCE_SHIFT | 5), - ADC1_6 = (1 << ADC_INSTANCE_SHIFT | 6), - ADC1_7 = (1 << ADC_INSTANCE_SHIFT | 7), - ADC1_8 = (1 << ADC_INSTANCE_SHIFT | 8), - ADC1_9 = (1 << ADC_INSTANCE_SHIFT | 9), - ADC1_10 = (1 << ADC_INSTANCE_SHIFT | 10), - ADC1_11 = (1 << ADC_INSTANCE_SHIFT | 11), - ADC1_12 = (1 << ADC_INSTANCE_SHIFT | 12), - ADC1_13 = (1 << ADC_INSTANCE_SHIFT | 13), - ADC1_14 = (1 << ADC_INSTANCE_SHIFT | 14), - ADC1_15 = (1 << ADC_INSTANCE_SHIFT | 15), - ADC2_0 = (2 << ADC_INSTANCE_SHIFT | 0), - ADC2_1 = (2 << ADC_INSTANCE_SHIFT | 1), - ADC2_2 = (2 << ADC_INSTANCE_SHIFT | 2), - ADC2_3 = (2 << ADC_INSTANCE_SHIFT | 3), - ADC2_4 = (2 << ADC_INSTANCE_SHIFT | 4), - ADC2_5 = (2 << ADC_INSTANCE_SHIFT | 5), - ADC2_6 = (2 << ADC_INSTANCE_SHIFT | 6), - ADC2_7 = (2 << ADC_INSTANCE_SHIFT | 7), - ADC2_8 = (2 << ADC_INSTANCE_SHIFT | 8), - ADC2_9 = (2 << ADC_INSTANCE_SHIFT | 9), - ADC2_10 = (2 << ADC_INSTANCE_SHIFT | 10), - ADC2_11 = (2 << ADC_INSTANCE_SHIFT | 11), - ADC2_12 = (2 << ADC_INSTANCE_SHIFT | 12), - ADC2_13 = (2 << ADC_INSTANCE_SHIFT | 13), - ADC2_14 = (2 << ADC_INSTANCE_SHIFT | 14), - ADC2_15 = (2 << ADC_INSTANCE_SHIFT | 15), -} ADCName; - -typedef enum { - DAC_0 = 0 -} DACName; - - -typedef enum { - SPI_1 = 1, - SPI_2 = 2, - SPI_3 = 3, - SPI_4 = 4, -} SPIName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c deleted file mode 100644 index 522ac50..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PeripheralPins.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "PeripheralPins.h" - -/************RTC***************/ -const PinMap PinMap_RTC[] = { - {NC, OSC32KCLK, 0}, -}; - -/************ADC***************/ -const PinMap PinMap_ADC[] = { - {GPIO_AD_B1_10, ADC1_15, 5}, - {GPIO_AD_B1_11, ADC2_0, 5}, - {GPIO_AD_B1_04, ADC1_9, 5}, - {GPIO_AD_B1_05, ADC1_10, 5}, - {GPIO_AD_B1_01, ADC1_6, 5}, - {GPIO_AD_B1_00, ADC1_5, 5}, - {NC , NC , 0} -}; - -/************DAC***************/ -const PinMap PinMap_DAC[] = { - {NC , NC , 0} -}; - -/************I2C***************/ -const PinMap PinMap_I2C_SDA[] = { - {GPIO_AD_B1_01, I2C_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4D0 << DAISY_REG_SHIFT) | (1U << SION_BIT_SHIFT) | 3)}, - {NC , NC , 0} -}; - -const PinMap PinMap_I2C_SCL[] = { - {GPIO_AD_B1_00, I2C_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4CC << DAISY_REG_SHIFT) | (1U << SION_BIT_SHIFT) | 3)}, - {NC , NC , 0} -}; - -/************UART***************/ -const PinMap PinMap_UART_TX[] = { - {GPIO_AD_B0_12, UART_1, 2}, - {GPIO_AD_B1_06, UART_3, 2}, - {NC , NC , 0} -}; - -const PinMap PinMap_UART_RX[] = { - {GPIO_AD_B0_13, UART_1, 2}, - {GPIO_AD_B1_07, UART_3, 2}, - {NC , NC , 0} -}; - -/************SPI***************/ -const PinMap PinMap_SPI_SCLK[] = { - {GPIO_SD_B0_00, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F0 << DAISY_REG_SHIFT) | 4)}, - {GPIO_AD_B0_00, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x510 << DAISY_REG_SHIFT) | 7)}, - {GPIO_B0_03, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x520 << DAISY_REG_SHIFT) | 3)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MOSI[] = { - {GPIO_SD_B0_02, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F8 << DAISY_REG_SHIFT) | 4)}, - {GPIO_AD_B0_01, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x518 << DAISY_REG_SHIFT) | 7)}, - {GPIO_B0_02, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x528 << DAISY_REG_SHIFT) | 3)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_MISO[] = { - {GPIO_SD_B0_03, SPI_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x4F4 << DAISY_REG_SHIFT) | 4)}, - {GPIO_AD_B0_02, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x514 << DAISY_REG_SHIFT) | 7)}, - {GPIO_B0_01, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x524 << DAISY_REG_SHIFT) | 3)}, - {NC , NC , 0} -}; - -const PinMap PinMap_SPI_SSEL[] = { - {GPIO_SD_B0_01, SPI_1, ((0U << DAISY_REG_VALUE_SHIFT) | (0x4EC << DAISY_REG_SHIFT) | 4)}, - {GPIO_AD_B0_03, SPI_3, ((0U << DAISY_REG_VALUE_SHIFT) | (0x50C << DAISY_REG_SHIFT) | 7)}, - {GPIO_B0_00, SPI_4, ((0U << DAISY_REG_VALUE_SHIFT) | (0x51C << DAISY_REG_SHIFT) | 3)}, - {NC , NC , 0} -}; - -/************PWM***************/ -const PinMap PinMap_PWM[] = { - {GPIO_AD_B0_10, PWM_7, ((3U << DAISY_REG_VALUE_SHIFT) | (0x454 << DAISY_REG_SHIFT) | 1)}, - {GPIO_AD_B0_11, PWM_8, ((3U << DAISY_REG_VALUE_SHIFT) | (0x464 << DAISY_REG_SHIFT) | 1)}, - {GPIO_AD_B1_08, PWM_25, ((1U << DAISY_REG_VALUE_SHIFT) | (0x494 << DAISY_REG_SHIFT) | 1)}, - {GPIO_SD_B0_00, PWM_1, ((1U << DAISY_REG_VALUE_SHIFT) | (0x458 << DAISY_REG_SHIFT) | 1)}, - {GPIO_SD_B0_01, PWM_2, ((1U << DAISY_REG_VALUE_SHIFT) | (0x468 << DAISY_REG_SHIFT) | 1)}, - {NC , NC , 0} -}; - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h index 67dbc3e..146a61a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h @@ -189,8 +189,11 @@ ARDUINO_UNO_D11 = GPIO_SD_B0_02, ARDUINO_UNO_D12 = GPIO_SD_B0_03, ARDUINO_UNO_D13 = GPIO_SD_B0_00, - ARDUINO_UNO_D14 = GPIO_AD_B0_01, - ARDUINO_UNO_D15 = GPIO_AD_B0_00, + + // Note: MIMXRT1050 EVKB Rev A connected D15 and D15 to AD_B0_01 and AD_B0_00 instead, but this did not comply + // with the standard as these pins do not have an I2C instance on them, so it was changed in Rev B. + ARDUINO_UNO_D14 = GPIO_AD_B1_01, + ARDUINO_UNO_D15 = GPIO_AD_B1_00, ARDUINO_UNO_A0 = GPIO_AD_B1_10, ARDUINO_UNO_A1 = GPIO_AD_B1_11, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/flash_api.c new file mode 100644 index 0000000..5a04864 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/flash_api.c @@ -0,0 +1,640 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "mbed_toolchain.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH + +#include "fsl_flexspi.h" +#include "fsl_cache.h" +#include "flash_defines.h" + +AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void)); +AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)); +AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_wait_bus_busy_ram(void)); +AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)); +AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t address, + const uint32_t *src, + uint32_t size)); +AT_QUICKACCESS_SECTION_CODE(void flexspi_nor_flash_read_data_ram(uint32_t addr, + uint32_t *buffer, + uint32_t size)); +AT_QUICKACCESS_SECTION_CODE(void *flexspi_memset(void *buf, int c, size_t n)); +/** + * @brief Set bytes in memory. If put this code in SRAM, Make sure this code + * does not call functions in Flash. + * + * @return pointer to start of buffer + */ +void *flexspi_memset(void *buf, int c, size_t n) +{ + /* do byte-sized initialization until word-aligned or finished */ + unsigned char *d_byte = (unsigned char *)buf; + unsigned char c_byte = (unsigned char)c; + + while (((unsigned int)d_byte) & 0x3) { + if (n == 0) { + return buf; + } + *(d_byte++) = c_byte; + n--; + }; + + /* do word-sized initialization as long as possible */ + + unsigned int *d_word = (unsigned int *)d_byte; + unsigned int c_word = (unsigned int)(unsigned char)c; + + c_word |= c_word << 8; + c_word |= c_word << 16; + + while (n >= sizeof(unsigned int)) { + *(d_word++) = c_word; + n -= sizeof(unsigned int); + } + + /* do byte-sized initialization until finished */ + + d_byte = (unsigned char *)d_word; + + while (n > 0) { + *(d_byte++) = c_byte; + n--; + } + + return buf; +} + +#ifdef HYPERFLASH_BOOT +AT_QUICKACCESS_SECTION_CODE(void flexspi_lower_clock_ram(void)); +AT_QUICKACCESS_SECTION_CODE(void flexspi_clock_update_ram(void)); +void flexspi_update_lut_ram(void) +{ + flexspi_config_t config; + + flexspi_memset(&config, 0, sizeof(config)); + + /*Get FLEXSPI default settings and configure the flexspi. */ + FLEXSPI_GetDefaultConfig(&config); + + /*Set AHB buffer size for reading data through AHB bus. */ + config.ahbConfig.enableAHBPrefetch = true; + /*Allow AHB read start address do not follow the alignment requirement. */ + config.ahbConfig.enableReadAddressOpt = true; + config.ahbConfig.enableAHBBufferable = true; + config.ahbConfig.enableAHBCachable = true; + /* enable diff clock and DQS */ + config.enableSckBDiffOpt = true; + config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad; + config.enableCombination = true; + FLEXSPI_Init(FLEXSPI, &config); + + /* Configure flash settings according to serial flash feature. */ + FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); + + /* Update LUT table. */ + FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); + + FLEXSPI_SoftwareReset(FLEXSPI); + + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { + } +} + +status_t flexspi_nor_write_enable_ram(uint32_t baseAddr) +{ + flexspi_transfer_t flashXfer; + status_t status = kStatus_Success; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + /* Write enable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + return status; +} + +status_t flexspi_nor_wait_bus_busy_ram(void) +{ + /* Wait status ready. */ + bool isBusy = false; + uint32_t readValue = 0; + status_t status = kStatus_Success; + flexspi_transfer_t flashXfer; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS; + flashXfer.data = &readValue; + flashXfer.dataSize = 2; + + do { + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + if (readValue & 0x8000) { + isBusy = false; + } else { + isBusy = true; + } + + if (readValue & 0x3200) { + status = kStatus_Fail; + break; + } + + } while (isBusy); + + return status; + +} + +status_t flexspi_nor_flash_erase_sector_ram(uint32_t address) +{ + status_t status = kStatus_Success; + flexspi_transfer_t flashXfer; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + /* Write enable */ + status = flexspi_nor_write_enable_ram(address); + if (status != kStatus_Success) { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 4; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + return status; +} + +void flexspi_lower_clock_ram(void) +{ + unsigned int reg = 0; + + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { + } + + FLEXSPI_Enable(FLEXSPI, false); + + /* Disable FlexSPI clock */ + CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK; + + /* flexspi clock 66M, DDR mode, internal clock 33M. */ + reg = CCM->CSCMR1; + reg &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK; + reg |= CCM_CSCMR1_FLEXSPI_PODF(3); + CCM->CSCMR1 = reg; + + /* Enable FlexSPI clock */ + CCM->CCGR6 |= CCM_CCGR6_CG5_MASK; + + FLEXSPI_Enable(FLEXSPI, true); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { + } +} + +void flexspi_clock_update_ram(void) +{ + /* Program finished, speed the clock to 133M. */ + /* Wait for bus idle before change flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { + } + FLEXSPI_Enable(FLEXSPI, false); + /* Disable FlexSPI clock */ + CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK; + + /* flexspi clock 260M, DDR mode, internal clock 130M. */ + CCM->CSCMR1 &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK; + + /* Enable FlexSPI clock */ + CCM->CCGR6 |= CCM_CCGR6_CG5_MASK; + + FLEXSPI_Enable(FLEXSPI, true); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { + } +} + +status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size) +{ + status_t status = kStatus_Success; + flexspi_transfer_t flashXfer; + uint32_t offset = 0; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + flexspi_lower_clock_ram(); + + while (size > 0) { + /* Write enable */ + status = flexspi_nor_write_enable_ram(address + offset); + + if (status != kStatus_Success) { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = address + offset; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 2; + flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM; + flashXfer.data = (uint32_t *)((uint32_t)src + offset); + flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + if (status != kStatus_Success) { + return status; + } + + size -= BOARD_FLASH_PAGE_SIZE; + offset += BOARD_FLASH_PAGE_SIZE; + } + + flexspi_clock_update_ram(); + + return status; +} + +#else +AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void)); +status_t flexspi_nor_enable_quad_mode_ram(void) +{ + flexspi_transfer_t flashXfer; + uint32_t writeValue = FLASH_QUAD_ENABLE; + status_t status = kStatus_Success; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + /* Write enable */ + status = flexspi_nor_write_enable_ram(0); + + if (status != kStatus_Success) { + return status; + } + + /* Enable quad mode. */ + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG; + flashXfer.data = &writeValue; + flashXfer.dataSize = 1; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + return status; +} + +void flexspi_update_lut_ram(void) +{ + flexspi_config_t config; + + flexspi_memset(&config, 0, sizeof(config)); + + /*Get FLEXSPI default settings and configure the flexspi. */ + FLEXSPI_GetDefaultConfig(&config); + + /*Set AHB buffer size for reading data through AHB bus. */ + config.ahbConfig.enableAHBPrefetch = true; + config.ahbConfig.enableAHBBufferable = true; + config.ahbConfig.enableReadAddressOpt = true; + config.ahbConfig.enableAHBCachable = true; + config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; + FLEXSPI_Init(FLEXSPI, &config); + + /* Configure flash settings according to serial flash feature. */ + FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); + + /* Update LUT table. */ + FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { + } + flexspi_nor_enable_quad_mode_ram(); +} + +status_t flexspi_nor_write_enable_ram(uint32_t baseAddr) +{ + flexspi_transfer_t flashXfer; + status_t status = kStatus_Success; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + /* Write enable */ + flashXfer.deviceAddress = baseAddr; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + return status; +} + +status_t flexspi_nor_wait_bus_busy_ram(void) +{ + /* Wait status ready. */ + bool isBusy; + uint32_t readValue; + status_t status = kStatus_Success; + flexspi_transfer_t flashXfer; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + flashXfer.deviceAddress = 0; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Read; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; + flashXfer.data = &readValue; + flashXfer.dataSize = 1; + + do { + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + if (FLASH_BUSY_STATUS_POL) { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) { + isBusy = true; + } else { + isBusy = false; + } + } else { + if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) { + isBusy = false; + } else { + isBusy = true; + } + } + + } while (isBusy); + + return status; +} + + +status_t flexspi_nor_flash_erase_sector_ram(uint32_t address) +{ + flexspi_transfer_t flashXfer; + status_t status = kStatus_Success; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + /* Write enable */ + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + flashXfer.deviceAddress = address; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Command; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + return status; +} + +status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size) +{ + flexspi_transfer_t flashXfer; + status_t status = kStatus_Success; + uint32_t offset = 0; + + flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); + + while (size > 0) { + /* Write enable */ + status = flexspi_nor_write_enable_ram(address + offset); + + if (status != kStatus_Success) { + return status; + } + + /* Prepare page program command */ + flashXfer.deviceAddress = address + offset; + flashXfer.port = kFLEXSPI_PortA1; + flashXfer.cmdType = kFLEXSPI_Write; + flashXfer.SeqNumber = 1; + flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; + flashXfer.data = (uint32_t *)((uint32_t)src + offset); + flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE; + + status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); + + if (status != kStatus_Success) { + return status; + } + + status = flexspi_nor_wait_bus_busy_ram(); + + if (status != kStatus_Success) { + return status; + } + + size -= BOARD_FLASH_PAGE_SIZE; + offset += BOARD_FLASH_PAGE_SIZE; + } + + /* Do software reset. */ + FLEXSPI_SoftwareReset(FLEXSPI); + + return status; +} + +#endif +void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size) +{ + memcpy(buffer, (void *)addr, size); +} + +int32_t flash_init(flash_t *obj) +{ + core_util_critical_section_enter(); + flexspi_update_lut_ram(); + core_util_critical_section_exit(); + + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + status_t status = kStatus_Success; + int32_t ret = 0; + + core_util_critical_section_enter(); + + status = flexspi_nor_flash_erase_sector_ram(address - FlexSPI_AMBA_BASE); + + if (status != kStatus_Success) { + ret = -1; + } else { + DCACHE_InvalidateByRange(address, BOARD_FLASH_SECTOR_SIZE); + } + + core_util_critical_section_exit(); + + return ret; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + status_t status = kStatus_Success; + int32_t ret = 0; + + core_util_critical_section_enter(); + + status = flexspi_nor_flash_page_program_ram(address - FlexSPI_AMBA_BASE, (uint32_t *)data, size); + + if (status != kStatus_Success) { + ret = -1; + } else { + DCACHE_InvalidateByRange(address, size); + } + + core_util_critical_section_exit(); + + return ret; +} + +int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) +{ + flexspi_nor_flash_read_data_ram(address, (uint32_t *)data, size); + + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + uint32_t sectorsize = MBED_FLASH_INVALID_SIZE; + uint32_t devicesize = BOARD_FLASHIAP_SIZE; + uint32_t startaddr = BOARD_FLASHIAP_START_ADDR; + + if ((address >= startaddr) && (address < (startaddr + devicesize))) { + sectorsize = BOARD_FLASH_SECTOR_SIZE; + } + + return sectorsize; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return BOARD_FLASH_PAGE_SIZE; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + return BOARD_FLASHIAP_START_ADDR; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return BOARD_FLASHIAP_SIZE; +} + +uint8_t flash_get_erase_value(const flash_t *obj) +{ + (void)obj; + + return 0xFF; +} + +#endif //DEVICE_FLASH + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/flash_defines.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/flash_defines.h new file mode 100644 index 0000000..656b80d --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/flash_defines.h @@ -0,0 +1,288 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _NXP_FLASH_DEFINES_H_ +#define _NXP_FLASH_DEFINES_H_ + +#include "fsl_common.h" + +#ifdef HYPERFLASH_BOOT /* 64MB Hyperflash */ +#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10 +#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP 12 +#define CUSTOM_LUT_LENGTH 64 + +static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { + /* Read Data */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), + + /* Write Data */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02), + /* Read Status */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), + + /* Write Enable */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + + /* Erase Sector */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), + + /* program page */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80), + + /* Erase chip */ + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), + // 1 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + // 2 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), + // 3 + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), + [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10), +}; + +flexspi_device_config_t deviceconfig = { + .flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */ + .isSck2Enabled = false, + .flashSize = (BOARD_FLASH_SIZE/1024), + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 0, + .CSSetupTime = 3, + .dataValidTime = 1, + .columnspace = 3, + .enableWordAddress = true, + .AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA, + .AWRSeqNumber = 1, + .ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA, + .ARDSeqNumber = 1, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .AHBWriteWaitInterval = 20, +}; +#else /* 8MB QSPI flash */ + +#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13 +#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1 +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2 +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6 +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4 +#define NOR_CMD_LUT_SEQ_IDX_READID 8 +#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9 +#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10 +#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11 +#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12 +#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5 +#define CUSTOM_LUT_LENGTH 60 +#define FLASH_QUAD_ENABLE 0x40 +#define FLASH_BUSY_STATUS_POL 1 +#define FLASH_BUSY_STATUS_OFFSET 0 + +static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { + /* Normal read mode -SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Fast read mode - SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Fast read quad mode - SDR */ + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), + + /* Read extend parameters */ + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Write Enable */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Erase Sector */ + [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + + /* Page Program - single mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Page Program - quad mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), + [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Read ID */ + [4 * NOR_CMD_LUT_SEQ_IDX_READID] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Enable Quad mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04), + + /* Enter QPI mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Exit QPI mode */ + [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), + + /* Read status register */ + [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), + + /* Erase whole chip */ + [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] = + FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), +}; + +flexspi_device_config_t deviceconfig = { + .flexspiRootClk = 120000000, + .flashSize = (BOARD_FLASH_SIZE/1024), + .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, + .CSInterval = 2, + .CSHoldTime = 3, + .CSSetupTime = 3, + .dataValidTime = 0, + .columnspace = 0, + .enableWordAddress = 0, + .AWRSeqIndex = 0, + .AWRSeqNumber = 0, + .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD, + .ARDSeqNumber = 1, + .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, + .AHBWriteWaitInterval = 0, +}; + +#endif /* HYPERFLASH_BOOT */ +#endif /* _NXP_FLASH_DEFINES_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.c new file mode 100644 index 0000000..104479f --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.c @@ -0,0 +1,80 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkbimxrt1050_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +#ifdef HYPERFLASH_BOOT +const flexspi_nor_config_t hyperflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {16u, 16u}, + .lookupTable = { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), + FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), + FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; +#else +const flexspi_nor_config_t qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 0u, + .configCmdEnable = 0u, + .controllerMiscOption = 0u, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .lutCustomSeqEnable = 0u, + .sflashA1Size = 0x00800000u, /* 8MB/64Mbit */ + .lookupTable = { + // Fast read sequence + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x02), + [2] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0), + [3] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0), + }, + }, +}; +#endif +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.h new file mode 100644 index 0000000..7b422d0 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_flexspi_nor_config.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ +#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c new file mode 100644 index 0000000..a2c0267 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c @@ -0,0 +1,320 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "evkbimxrt1050_sdram_ini_dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1052xxxxB +mcu_data: ksdk2_0 +processor_version: 0.0.19 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x30, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-117, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0xAC, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, + /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9, + /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, + /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.100, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.101, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.104, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.105, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.106, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.107, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.108, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.109, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.110, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.111, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.112, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.113, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.114, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.115, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.116, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.117, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h new file mode 100644 index 0000000..7f57e7c --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __EVKBIMXRT1050_SDRAM_INI_DCD__ +#define __EVKBIMXRT1050_SDRAM_INI_DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.0. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __EVKBIMXRT1050_SDRAM_INI_DCD__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/dcd.c new file mode 100644 index 0000000..74a9799 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/dcd.c @@ -0,0 +1,315 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1062xxxxA +package_id: MIMXRT1062DVL6A +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: MIMXRT1060-EVKB +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 + }; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/dcd.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/dcd.h new file mode 100644 index 0000000..8720000 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.c new file mode 100644 index 0000000..e552f11 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.c @@ -0,0 +1,70 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "evkbmimxrt1060_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_120MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.h new file mode 100644 index 0000000..76503d6 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1060_EVK/xip/evkbmimxrt1060_flexspi_nor_config.h @@ -0,0 +1,268 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ +#define __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq +{ + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, + kFlexSpiSerialClk_166MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum +{ + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource +{ + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum +{ + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum +{ + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum +{ + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence +{ + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum +{ + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig +{ + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t + configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/analogin_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/analogin_api.c deleted file mode 100644 index a80272c..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/analogin_api.c +++ /dev/null @@ -1,89 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "cmsis.h" -#include "pinmap.h" -#include "gpio_api.h" -#include "PeripheralNames.h" -#include "fsl_adc.h" -#include "PeripheralPins.h" - -/* Array of ADC peripheral base address. */ -static ADC_Type *const adc_addrs[] = ADC_BASE_PTRS; - -void analogin_init(analogin_t *obj, PinName pin) -{ - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; - adc_config_t adc_config; - gpio_t gpio; - - ADC_GetDefaultConfig(&adc_config); - ADC_Init(adc_addrs[instance], &adc_config); -#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) - ADC_EnableHardwareTrigger(adc_addrs[instance], false); -#endif - ADC_DoAutoCalibration(adc_addrs[instance]); - - /* Need to ensure the pin is in input mode */ - gpio_init(&gpio, pin); - gpio_dir(&gpio, PIN_INPUT); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; - adc_channel_config_t adc_channel_config; - - adc_channel_config.channelNumber = obj->adc & 0xF; - adc_channel_config.enableInterruptOnConversionCompleted = false; - - /* - When in software trigger mode, each conversion would be launched once calling the "ADC_ChannelConfigure()" - function, which works like writing a conversion command and executing it. For another channel's conversion, - just to change the "channelNumber" field in channel configuration structure, and call the function - "ADC_ChannelConfigure()"" again. - Also, the "enableInterruptOnConversionCompleted" inside the channel configuration structure is a parameter - for the conversion command. It takes affect just for the current conversion. If the interrupt is still required - for the following conversion, it is necessary to assert the "enableInterruptOnConversionCompleted" every - time for each command. - */ - ADC_SetChannelConfig(adc_addrs[instance], 0, &adc_channel_config); - while (0U == ADC_GetChannelStatusFlags(adc_addrs[instance], 0)) - { - } - return ADC_GetChannelConversionValue(adc_addrs[instance], 0); -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)0xFFFF); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_api.c deleted file mode 100644 index 5a04864..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_api.c +++ /dev/null @@ -1,640 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "flash_api.h" -#include "mbed_toolchain.h" -#include "mbed_critical.h" - -#if DEVICE_FLASH - -#include "fsl_flexspi.h" -#include "fsl_cache.h" -#include "flash_defines.h" - -AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void)); -AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)); -AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_wait_bus_busy_ram(void)); -AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)); -AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t address, - const uint32_t *src, - uint32_t size)); -AT_QUICKACCESS_SECTION_CODE(void flexspi_nor_flash_read_data_ram(uint32_t addr, - uint32_t *buffer, - uint32_t size)); -AT_QUICKACCESS_SECTION_CODE(void *flexspi_memset(void *buf, int c, size_t n)); -/** - * @brief Set bytes in memory. If put this code in SRAM, Make sure this code - * does not call functions in Flash. - * - * @return pointer to start of buffer - */ -void *flexspi_memset(void *buf, int c, size_t n) -{ - /* do byte-sized initialization until word-aligned or finished */ - unsigned char *d_byte = (unsigned char *)buf; - unsigned char c_byte = (unsigned char)c; - - while (((unsigned int)d_byte) & 0x3) { - if (n == 0) { - return buf; - } - *(d_byte++) = c_byte; - n--; - }; - - /* do word-sized initialization as long as possible */ - - unsigned int *d_word = (unsigned int *)d_byte; - unsigned int c_word = (unsigned int)(unsigned char)c; - - c_word |= c_word << 8; - c_word |= c_word << 16; - - while (n >= sizeof(unsigned int)) { - *(d_word++) = c_word; - n -= sizeof(unsigned int); - } - - /* do byte-sized initialization until finished */ - - d_byte = (unsigned char *)d_word; - - while (n > 0) { - *(d_byte++) = c_byte; - n--; - } - - return buf; -} - -#ifdef HYPERFLASH_BOOT -AT_QUICKACCESS_SECTION_CODE(void flexspi_lower_clock_ram(void)); -AT_QUICKACCESS_SECTION_CODE(void flexspi_clock_update_ram(void)); -void flexspi_update_lut_ram(void) -{ - flexspi_config_t config; - - flexspi_memset(&config, 0, sizeof(config)); - - /*Get FLEXSPI default settings and configure the flexspi. */ - FLEXSPI_GetDefaultConfig(&config); - - /*Set AHB buffer size for reading data through AHB bus. */ - config.ahbConfig.enableAHBPrefetch = true; - /*Allow AHB read start address do not follow the alignment requirement. */ - config.ahbConfig.enableReadAddressOpt = true; - config.ahbConfig.enableAHBBufferable = true; - config.ahbConfig.enableAHBCachable = true; - /* enable diff clock and DQS */ - config.enableSckBDiffOpt = true; - config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad; - config.enableCombination = true; - FLEXSPI_Init(FLEXSPI, &config); - - /* Configure flash settings according to serial flash feature. */ - FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); - - /* Update LUT table. */ - FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); - - FLEXSPI_SoftwareReset(FLEXSPI); - - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { - } -} - -status_t flexspi_nor_write_enable_ram(uint32_t baseAddr) -{ - flexspi_transfer_t flashXfer; - status_t status = kStatus_Success; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - - /* Write enable */ - flashXfer.deviceAddress = baseAddr; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 2; - flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE; - - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - return status; -} - -status_t flexspi_nor_wait_bus_busy_ram(void) -{ - /* Wait status ready. */ - bool isBusy = false; - uint32_t readValue = 0; - status_t status = kStatus_Success; - flexspi_transfer_t flashXfer; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - - flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 2; - flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS; - flashXfer.data = &readValue; - flashXfer.dataSize = 2; - - do { - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - if (status != kStatus_Success) { - return status; - } - - if (readValue & 0x8000) { - isBusy = false; - } else { - isBusy = true; - } - - if (readValue & 0x3200) { - status = kStatus_Fail; - break; - } - - } while (isBusy); - - return status; - -} - -status_t flexspi_nor_flash_erase_sector_ram(uint32_t address) -{ - status_t status = kStatus_Success; - flexspi_transfer_t flashXfer; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - - /* Write enable */ - status = flexspi_nor_write_enable_ram(address); - if (status != kStatus_Success) { - return status; - } - - flashXfer.deviceAddress = address; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 4; - flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR; - - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - if (status != kStatus_Success) { - return status; - } - - status = flexspi_nor_wait_bus_busy_ram(); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(FLEXSPI); - - return status; -} - -void flexspi_lower_clock_ram(void) -{ - unsigned int reg = 0; - - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { - } - - FLEXSPI_Enable(FLEXSPI, false); - - /* Disable FlexSPI clock */ - CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK; - - /* flexspi clock 66M, DDR mode, internal clock 33M. */ - reg = CCM->CSCMR1; - reg &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK; - reg |= CCM_CSCMR1_FLEXSPI_PODF(3); - CCM->CSCMR1 = reg; - - /* Enable FlexSPI clock */ - CCM->CCGR6 |= CCM_CCGR6_CG5_MASK; - - FLEXSPI_Enable(FLEXSPI, true); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(FLEXSPI); - - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { - } -} - -void flexspi_clock_update_ram(void) -{ - /* Program finished, speed the clock to 133M. */ - /* Wait for bus idle before change flash configuration. */ - while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { - } - FLEXSPI_Enable(FLEXSPI, false); - /* Disable FlexSPI clock */ - CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK; - - /* flexspi clock 260M, DDR mode, internal clock 130M. */ - CCM->CSCMR1 &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK; - - /* Enable FlexSPI clock */ - CCM->CCGR6 |= CCM_CCGR6_CG5_MASK; - - FLEXSPI_Enable(FLEXSPI, true); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(FLEXSPI); - - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { - } -} - -status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size) -{ - status_t status = kStatus_Success; - flexspi_transfer_t flashXfer; - uint32_t offset = 0; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - - flexspi_lower_clock_ram(); - - while (size > 0) { - /* Write enable */ - status = flexspi_nor_write_enable_ram(address + offset); - - if (status != kStatus_Success) { - return status; - } - - /* Prepare page program command */ - flashXfer.deviceAddress = address + offset; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 2; - flashXfer.seqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM; - flashXfer.data = (uint32_t *)((uint32_t)src + offset); - flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE; - - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - if (status != kStatus_Success) { - return status; - } - - status = flexspi_nor_wait_bus_busy_ram(); - - if (status != kStatus_Success) { - return status; - } - - size -= BOARD_FLASH_PAGE_SIZE; - offset += BOARD_FLASH_PAGE_SIZE; - } - - flexspi_clock_update_ram(); - - return status; -} - -#else -AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_enable_quad_mode_ram(void)); -status_t flexspi_nor_enable_quad_mode_ram(void) -{ - flexspi_transfer_t flashXfer; - uint32_t writeValue = FLASH_QUAD_ENABLE; - status_t status = kStatus_Success; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - /* Write enable */ - status = flexspi_nor_write_enable_ram(0); - - if (status != kStatus_Success) { - return status; - } - - /* Enable quad mode. */ - flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG; - flashXfer.data = &writeValue; - flashXfer.dataSize = 1; - - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - if (status != kStatus_Success) { - return status; - } - - status = flexspi_nor_wait_bus_busy_ram(); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(FLEXSPI); - - return status; -} - -void flexspi_update_lut_ram(void) -{ - flexspi_config_t config; - - flexspi_memset(&config, 0, sizeof(config)); - - /*Get FLEXSPI default settings and configure the flexspi. */ - FLEXSPI_GetDefaultConfig(&config); - - /*Set AHB buffer size for reading data through AHB bus. */ - config.ahbConfig.enableAHBPrefetch = true; - config.ahbConfig.enableAHBBufferable = true; - config.ahbConfig.enableReadAddressOpt = true; - config.ahbConfig.enableAHBCachable = true; - config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad; - FLEXSPI_Init(FLEXSPI, &config); - - /* Configure flash settings according to serial flash feature. */ - FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1); - - /* Update LUT table. */ - FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(FLEXSPI); - /* Wait for bus idle. */ - while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) { - } - flexspi_nor_enable_quad_mode_ram(); -} - -status_t flexspi_nor_write_enable_ram(uint32_t baseAddr) -{ - flexspi_transfer_t flashXfer; - status_t status = kStatus_Success; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - /* Write enable */ - flashXfer.deviceAddress = baseAddr; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; - - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - return status; -} - -status_t flexspi_nor_wait_bus_busy_ram(void) -{ - /* Wait status ready. */ - bool isBusy; - uint32_t readValue; - status_t status = kStatus_Success; - flexspi_transfer_t flashXfer; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - - flashXfer.deviceAddress = 0; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Read; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_READSTATUSREG; - flashXfer.data = &readValue; - flashXfer.dataSize = 1; - - do { - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - if (status != kStatus_Success) { - return status; - } - if (FLASH_BUSY_STATUS_POL) { - if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) { - isBusy = true; - } else { - isBusy = false; - } - } else { - if (readValue & (1U << FLASH_BUSY_STATUS_OFFSET)) { - isBusy = false; - } else { - isBusy = true; - } - } - - } while (isBusy); - - return status; -} - - -status_t flexspi_nor_flash_erase_sector_ram(uint32_t address) -{ - flexspi_transfer_t flashXfer; - status_t status = kStatus_Success; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - - /* Write enable */ - flashXfer.deviceAddress = address; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_WRITEENABLE; - - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - if (status != kStatus_Success) { - return status; - } - - flashXfer.deviceAddress = address; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Command; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_ERASESECTOR; - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - if (status != kStatus_Success) { - return status; - } - - status = flexspi_nor_wait_bus_busy_ram(); - - /* Do software reset. */ - FLEXSPI_SoftwareReset(FLEXSPI); - - return status; -} - -status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size) -{ - flexspi_transfer_t flashXfer; - status_t status = kStatus_Success; - uint32_t offset = 0; - - flexspi_memset(&flashXfer, 0, sizeof(flashXfer)); - - while (size > 0) { - /* Write enable */ - status = flexspi_nor_write_enable_ram(address + offset); - - if (status != kStatus_Success) { - return status; - } - - /* Prepare page program command */ - flashXfer.deviceAddress = address + offset; - flashXfer.port = kFLEXSPI_PortA1; - flashXfer.cmdType = kFLEXSPI_Write; - flashXfer.SeqNumber = 1; - flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD; - flashXfer.data = (uint32_t *)((uint32_t)src + offset); - flashXfer.dataSize = BOARD_FLASH_PAGE_SIZE; - - status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer); - - if (status != kStatus_Success) { - return status; - } - - status = flexspi_nor_wait_bus_busy_ram(); - - if (status != kStatus_Success) { - return status; - } - - size -= BOARD_FLASH_PAGE_SIZE; - offset += BOARD_FLASH_PAGE_SIZE; - } - - /* Do software reset. */ - FLEXSPI_SoftwareReset(FLEXSPI); - - return status; -} - -#endif -void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size) -{ - memcpy(buffer, (void *)addr, size); -} - -int32_t flash_init(flash_t *obj) -{ - core_util_critical_section_enter(); - flexspi_update_lut_ram(); - core_util_critical_section_exit(); - - return 0; -} - -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - status_t status = kStatus_Success; - int32_t ret = 0; - - core_util_critical_section_enter(); - - status = flexspi_nor_flash_erase_sector_ram(address - FlexSPI_AMBA_BASE); - - if (status != kStatus_Success) { - ret = -1; - } else { - DCACHE_InvalidateByRange(address, BOARD_FLASH_SECTOR_SIZE); - } - - core_util_critical_section_exit(); - - return ret; -} - -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - status_t status = kStatus_Success; - int32_t ret = 0; - - core_util_critical_section_enter(); - - status = flexspi_nor_flash_page_program_ram(address - FlexSPI_AMBA_BASE, (uint32_t *)data, size); - - if (status != kStatus_Success) { - ret = -1; - } else { - DCACHE_InvalidateByRange(address, size); - } - - core_util_critical_section_exit(); - - return ret; -} - -int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size) -{ - flexspi_nor_flash_read_data_ram(address, (uint32_t *)data, size); - - return 0; -} - -int32_t flash_free(flash_t *obj) -{ - return 0; -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - uint32_t sectorsize = MBED_FLASH_INVALID_SIZE; - uint32_t devicesize = BOARD_FLASHIAP_SIZE; - uint32_t startaddr = BOARD_FLASHIAP_START_ADDR; - - if ((address >= startaddr) && (address < (startaddr + devicesize))) { - sectorsize = BOARD_FLASH_SECTOR_SIZE; - } - - return sectorsize; -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - return BOARD_FLASH_PAGE_SIZE; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ - return BOARD_FLASHIAP_START_ADDR; -} - -uint32_t flash_get_size(const flash_t *obj) -{ - return BOARD_FLASHIAP_SIZE; -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0xFF; -} - -#endif //DEVICE_FLASH - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h deleted file mode 100644 index 656b80d..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h +++ /dev/null @@ -1,288 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _NXP_FLASH_DEFINES_H_ -#define _NXP_FLASH_DEFINES_H_ - -#include "fsl_common.h" - -#ifdef HYPERFLASH_BOOT /* 64MB Hyperflash */ -#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0 -#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1 -#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2 -#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4 -#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6 -#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10 -#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP 12 -#define CUSTOM_LUT_LENGTH 64 - -static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { - /* Read Data */ - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04), - - /* Write Data */ - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02), - /* Read Status */ - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0), - - /* Write Enable */ - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), - - /* Erase Sector */ - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00), - - /* program page */ - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80), - - /* Erase chip */ - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), - // 1 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), - // 2 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55), - // 3 - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05), - [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10), -}; - -flexspi_device_config_t deviceconfig = { - .flexspiRootClk = 42000000, /* 42MHZ SPI serial clock */ - .isSck2Enabled = false, - .flashSize = (BOARD_FLASH_SIZE/1024), - .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, - .CSInterval = 2, - .CSHoldTime = 0, - .CSSetupTime = 3, - .dataValidTime = 1, - .columnspace = 3, - .enableWordAddress = true, - .AWRSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA, - .AWRSeqNumber = 1, - .ARDSeqIndex = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA, - .ARDSeqNumber = 1, - .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, - .AHBWriteWaitInterval = 20, -}; -#else /* 8MB QSPI flash */ - -#define NOR_CMD_LUT_SEQ_IDX_READ_NORMAL 7 -#define NOR_CMD_LUT_SEQ_IDX_READ_FAST 13 -#define NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD 0 -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1 -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 2 -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 3 -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE 6 -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD 4 -#define NOR_CMD_LUT_SEQ_IDX_READID 8 -#define NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG 9 -#define NOR_CMD_LUT_SEQ_IDX_ENTERQPI 10 -#define NOR_CMD_LUT_SEQ_IDX_EXITQPI 11 -#define NOR_CMD_LUT_SEQ_IDX_READSTATUSREG 12 -#define NOR_CMD_LUT_SEQ_IDX_ERASECHIP 5 -#define CUSTOM_LUT_LENGTH 60 -#define FLASH_QUAD_ENABLE 0x40 -#define FLASH_BUSY_STATUS_POL 1 -#define FLASH_BUSY_STATUS_OFFSET 0 - -static uint32_t customLUT[CUSTOM_LUT_LENGTH] = { - /* Normal read mode -SDR */ - [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x03, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_READ_NORMAL + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Fast read mode - SDR */ - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x0B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 0x08, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Fast read quad mode - SDR */ - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD + 1] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 0x06, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04), - - /* Read extend parameters */ - [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUS] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Write Enable */ - [4 * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x06, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Erase Sector */ - [4 * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x20, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - - /* Page Program - single mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x02, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Page Program - quad mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x32, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18), - [4 * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_QUAD + 1] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Read ID */ - [4 * NOR_CMD_LUT_SEQ_IDX_READID] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Enable Quad mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_WRITESTATUSREG] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x01, kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04), - - /* Enter QPI mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_ENTERQPI] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Exit QPI mode */ - [4 * NOR_CMD_LUT_SEQ_IDX_EXITQPI] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), - - /* Read status register */ - [4 * NOR_CMD_LUT_SEQ_IDX_READSTATUSREG] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x05, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x04), - - /* Erase whole chip */ - [4 * NOR_CMD_LUT_SEQ_IDX_ERASECHIP] = - FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC7, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0), -}; - -flexspi_device_config_t deviceconfig = { - .flexspiRootClk = 120000000, - .flashSize = (BOARD_FLASH_SIZE/1024), - .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, - .CSInterval = 2, - .CSHoldTime = 3, - .CSSetupTime = 3, - .dataValidTime = 0, - .columnspace = 0, - .enableWordAddress = 0, - .AWRSeqIndex = 0, - .AWRSeqNumber = 0, - .ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST_QUAD, - .ARDSeqNumber = 1, - .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, - .AHBWriteWaitInterval = 0, -}; - -#endif /* HYPERFLASH_BOOT */ -#endif /* _NXP_FLASH_DEFINES_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c deleted file mode 100644 index d9a1fb3..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v5.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 0.0.0 -board: IMXRT1050-EVKB - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "fsl_clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL4.denom, value: '50'} -- {id: CCM_ANALOG.PLL4.div, value: '47'} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '40'} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); -/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif -/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 1); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - /* Disable pfd offset. */ - CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK; -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = - (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = CLOCK_GetCpuClkFreq(); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h deleted file mode 100644 index f213ac7..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_flexspi_nor_boot.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_flexspi_nor_boot.c new file mode 100644 index 0000000..09a59ed --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_flexspi_nor_boot.c @@ -0,0 +1,51 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi_nor_boot.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_device" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) + __attribute__((section(".boot_hdr.ivt"), used)) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.ivt" +#endif +/************************************* + * IVT Data + *************************************/ +const ivt image_vector_table = { + IVT_HEADER, /* IVT Header */ + IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ + IVT_RSVD, /* Reserved = 0 */ + (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ + (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ + (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ + IVT_RSVD /* Reserved = 0 */ +}; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) + __attribute__((section(".boot_hdr.boot_data"))) +#elif defined(__ICCARM__) +#pragma location=".boot_hdr.boot_data" +#endif +/************************************* + * Boot Data + *************************************/ +const BOOT_DATA_T boot_data = { + FLASH_BASE, /* boot start location */ + FLASH_SIZE, /* size */ + PLUGIN_FLAG, /* Plugin flag*/ + 0xFFFFFFFF /* empty - extra data word */ +}; +#endif + + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_flexspi_nor_boot.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_flexspi_nor_boot.h new file mode 100644 index 0000000..bd0fe64 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_flexspi_nor_boot.h @@ -0,0 +1,112 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FLEXSPI_NOR_BOOT_H__ +#define __FLEXSPI_NOR_BOOT_H__ + +#include +#include "device.h" +#undef __VECTOR_TABLE + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_DEVICE driver version 2.0.0. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/************************************* + * IVT Data + *************************************/ +typedef struct _ivt_ { + /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields + * (see @ref data) + */ + uint32_t hdr; + /** Absolute address of the first instruction to execute from the + * image + */ + uint32_t entry; + /** Reserved in this version of HAB: should be NULL. */ + uint32_t reserved1; + /** Absolute address of the image DCD: may be NULL. */ + uint32_t dcd; + /** Absolute address of the Boot Data: may be NULL, but not interpreted + * any further by HAB + */ + uint32_t boot_data; + /** Absolute address of the IVT.*/ + uint32_t self; + /** Absolute address of the image CSF.*/ + uint32_t csf; + /** Reserved in this version of HAB: should be zero. */ + uint32_t reserved2; +} ivt; + +#define IVT_MAJOR_VERSION 0x4 +#define IVT_MAJOR_VERSION_SHIFT 0x4 +#define IVT_MAJOR_VERSION_MASK 0xF +#define IVT_MINOR_VERSION 0x1 +#define IVT_MINOR_VERSION_SHIFT 0x0 +#define IVT_MINOR_VERSION_MASK 0xF + +#define IVT_VERSION(major, minor) \ + ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ + (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) + +/* IVT header */ +#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ +#define IVT_SIZE 0x2000 +#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) +#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) + +/* Set resume entry */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t __Vectors[]; + extern uint32_t Image$$RW_m_config_text$$Base[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) +#elif defined(__MCUXPRESSO) + extern uint32_t __Vectors[]; + extern uint32_t __boot_hdr_start__[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) +#define FLASH_BASE ((uint32_t)__boot_hdr_start__) +#elif defined(__ICCARM__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t m_boot_hdr_conf_start[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __FLASH_BASE[]; +#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) +#define FLASH_BASE ((uint32_t)__FLASH_BASE) +#endif + +#define DCD_ADDRESS dcd_data +#define BOOT_DATA_ADDRESS &boot_data +#define CSF_ADDRESS 0 +#define IVT_RSVD (uint32_t)(0x00000000) + +/************************************* + * Boot Data + *************************************/ +typedef struct _boot_data_ { + uint32_t start; /* boot start location */ + uint32_t size; /* size */ + uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ + uint32_t placeholder; /* placehoder to make even 0x10 size */ +}BOOT_DATA_T; + +#define FLASH_SIZE BOARD_FLASH_SIZE +#define PLUGIN_FLAG (uint32_t)0 + +/* External Variables */ +const BOOT_DATA_T boot_data; +extern const uint8_t dcd_data[]; + +#endif /* __FLEXSPI_NOR_BOOT_H__ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c deleted file mode 100644 index 420f15d..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.c +++ /dev/null @@ -1,534 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "lpm.h" -#include "fsl_gpc.h" -#include "fsl_dcdc.h" -#include "fsl_gpt.h" -#include "fsl_clock_config.h" -#include "mbed_critical.h" -#include "cmsis.h" -#include "specific.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define LPM_GPC_IMR_NUM (sizeof(GPC->IMR) / sizeof(GPC->IMR[0])) - -/******************************************************************************* - * Variables - ******************************************************************************/ - -uint32_t g_savedPrimask; -GPT_Type *vPortGetGptBase(void); -IRQn_Type vPortGetGptIrqn(void); - -/******************************************************************************* - * Code - ******************************************************************************/ -void EnableRegularLDO(void) -{ - /* Enable Regular LDO 2P5 and 1P1 */ - PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_LINREG_MASK; - PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_LINREG_MASK; -} - -void DisableRegularLDO(void) -{ - /* Disable Regular LDO 2P5 and 1P1 */ - PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_LINREG_MASK; - PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_LINREG_MASK; -} - -void EnableWeakLDO(void) -{ - /* Enable Weak LDO 2P5 and 1P1 */ - PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; - PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; - - SDK_DelayAtLeastUs(40); -} - -void DisableWeakLDO(void) -{ - /* Disable Weak LDO 2P5 and 1P1 */ - PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; - PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; -} - -void BandgapOn(void) -{ - /* Turn on regular bandgap and wait for stable */ - PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK; - while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0) - { - } - /* Low power band gap disable */ - XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; -} - -void BandgapOff(void) -{ - XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; - PMU->MISC0_SET = PMU_MISC0_REFTOP_PWD_MASK; -} - -/*! - * @brief Set CCM MUX node to certain value. - * - * @param mux Which mux node to set, see \ref clock_mux_t. - * @param value Clock mux value to set, different mux has different value range. - */ -void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value) -{ - uint32_t busyShift; - - busyShift = CCM_TUPLE_BUSY_SHIFT(mux); - CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | - (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); - - //assert(busyShift <= CCM_NO_BUSY_WAIT); - - /* Clock switch need Handshake? */ - if (CCM_NO_BUSY_WAIT != busyShift) - { - /* Wait until CCM internal handshake finish. */ - while (CCM->CDHIPR & (1U << busyShift)) - { - } - } -} - -/*! - * @brief Set CCM DIV node to certain value. - * - * @param divider Which div node to set, see \ref clock_div_t. - * @param value Clock div value to set, different divider has different value range. - */ -void CLOCK_SET_DIV(clock_div_t divider, uint32_t value) -{ - uint32_t busyShift; - - busyShift = CCM_TUPLE_BUSY_SHIFT(divider); - CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | - (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); - - //assert(busyShift <= CCM_NO_BUSY_WAIT); - - /* Clock switch need Handshake? */ - if (CCM_NO_BUSY_WAIT != busyShift) - { - /* Wait until CCM internal handshake finish. */ - while (CCM->CDHIPR & (1U << busyShift)) - { - } - } -} - -void ClockSelectXtalOsc(void) -{ - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); -} - -void ClockSelectRcOsc(void) -{ - /* Switch clock source to internal RC. */ - XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; -} - -void LPM_SetRunModeConfig(void) -{ - CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); -} - -void LPM_SetWaitModeConfig(void) -{ - uint32_t clpcr; - - /* - * ERR007265: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending - * by setting IOMUXC_GPR_GPR1_GINT. - * 2) Software should then unmask IRQ #41 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #41 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); - clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); - CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeWait) | CCM_CLPCR_MASK_SCU_IDLE_MASK | CCM_CLPCR_MASK_L2CC_IDLE_MASK | - CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK | - CCM_CLPCR_BYPASS_LPM_HS1_MASK; - GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); -} - -void LPM_SetStopModeConfig(void) -{ - uint32_t clpcr; - - /* - * ERR007265: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending - * by setting IOMUXC_GPR_GPR1_GINT. - * 2) Software should then unmask IRQ #41 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #41 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); - clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); - CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeStop) | CCM_CLPCR_MASK_L2CC_IDLE_MASK | CCM_CLPCR_MASK_SCU_IDLE_MASK | - CCM_CLPCR_VSTBY_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_SBYOS_MASK | - CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK; - GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); -} - -void LPM_OverDriveRun(void) -{ - /* CCM Mode */ - DCDC_BootIntoCCM(DCDC); - /* Connect internal the load resistor */ - DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; - /* Adjust SOC voltage to 1.275V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - - /* Disable FET ODRIVE */ - PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - BandgapOn(); - EnableRegularLDO(); - DisableWeakLDO(); - - ClockSetToOverDriveRun(); - SetRestoreClockGate(); -} - -void LPM_FullSpeedRun(void) -{ - /* CCM Mode */ - DCDC_BootIntoCCM(DCDC); - /* Connect internal the load resistor */ - DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; - /* Adjust SOC voltage to 1.275V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - - /* Disable FET ODRIVE */ - PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - BandgapOn(); - EnableRegularLDO(); - DisableWeakLDO(); - - ClockSetToFullSpeedRun(); - - /* Adjust SOC voltage to 1.15V */ - DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); -} - -void LPM_LowSpeedRun(void) -{ - /* CCM Mode */ - DCDC_BootIntoCCM(DCDC); - /* Connect internal the load resistor */ - DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; - /* Adjust SOC voltage to 1.275V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - - /* Disable FET ODRIVE */ - PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - BandgapOn(); - EnableRegularLDO(); - DisableWeakLDO(); - - ClockSetToLowSpeedRun(); - - /* Adjust SOC voltage to 1.15V */ - DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); -} - -void LPM_LowPowerRun(void) -{ - ClockSetToLowPowerRun(); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* Adjust SOC voltage to 0.95V */ - DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); - /* DCM Mode */ - DCDC_BootIntoDCM(DCDC); - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - /* Power Down output range comparator */ - DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - EnableWeakLDO(); - DisableRegularLDO(); - BandgapOff(); -} - -void LPM_EnterSystemIdle(void) -{ - LPM_SetWaitModeConfig(); - SetLowPowerClockGate(); - - ClockSetToSystemIdle(); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* DCDC to 1.15V */ - DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); - /* DCM Mode */ - DCDC_BootIntoDCM(DCDC); - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - /* Power Down output range comparator */ - DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - EnableRegularLDO(); - DisableWeakLDO(); - BandgapOn(); - - PeripheralEnterDozeMode(); -} - -void LPM_ExitSystemIdle(void) -{ - PeripheralExitDozeMode(); - LPM_SetRunModeConfig(); -} - -void LPM_EnterLowPowerIdle(void) -{ - LPM_SetWaitModeConfig(); - SetLowPowerClockGate(); - - ClockSetToLowPowerIdle(); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* Adjust SOC voltage to 0.95V */ - DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); - /* DCM Mode */ - DCDC_BootIntoDCM(DCDC); - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - /* Power Down output range comparator */ - DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - EnableWeakLDO(); - DisableRegularLDO(); - BandgapOff(); - - PeripheralEnterDozeMode(); -} - -void LPM_ExitLowPowerIdle(void) -{ - PeripheralExitDozeMode(); - LPM_SetRunModeConfig(); -} - -void LPM_EnterSuspend(void) -{ - uint32_t i; - uint32_t gpcIMR[LPM_GPC_IMR_NUM]; - - LPM_SetStopModeConfig(); - SetLowPowerClockGate(); - - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - - /* Turn off FlexRAM0 */ - GPC->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; - /* Turn off FlexRAM1 */ - PGC->MEGA_CTRL |= PGC_MEGA_CTRL_PCR_MASK; - - /* Clean and disable data cache to make sure context is saved into RAM */ - SCB_CleanDCache(); - SCB_DisableDCache(); - - /* Adjust LP voltage to 0.925V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - /* Switch DCDC to use DCDC internal OSC */ - DCDC_SetClockSource(DCDC, kDCDC_ClockInternalOsc); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* Power down CPU when requested */ - PGC->CPU_CTRL = PGC_CPU_CTRL_PCR_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - /* STOP_MODE config, turn off all analog except RTC in stop mode */ - PMU->MISC0_CLR = PMU_MISC0_STOP_MODE_CONFIG_MASK; - - /* Mask all GPC interrupts before enabling the RBC counters to - * avoid the counter starting too early if an interupt is already - * pending. - */ - for (i = 0; i < LPM_GPC_IMR_NUM; i++) - { - gpcIMR[i] = GPC->IMR[i]; - GPC->IMR[i] = 0xFFFFFFFFU; - } - - /* - * ERR006223: CCM: Failure to resuem from wait/stop mode with power gating - * Configure REG_BYPASS_COUNTER to 2 - * Enable the RBC bypass counter here to hold off the interrupts. RBC counter - * needs to be no less than 2. - */ - CCM->CCR = (CCM->CCR & ~CCM_CCR_REG_BYPASS_COUNT_MASK) | CCM_CCR_REG_BYPASS_COUNT(2); - CCM->CCR |= (CCM_CCR_OSCNT(0xAF) | CCM_CCR_COSC_EN_MASK | CCM_CCR_RBC_EN_MASK); - - /* Now delay for a short while (3usec) at this point - * so a short loop should be enough. This delay is required to ensure that - * the RBC counter can start counting in case an interrupt is already pending - * or in case an interrupt arrives just as ARM is about to assert DSM_request. - */ - SDK_DelayAtLeastUs(3); - - /* Recover all the GPC interrupts. */ - for (i = 0; i < LPM_GPC_IMR_NUM; i++) - { - GPC->IMR[i] = gpcIMR[i]; - } - - PeripheralEnterStopMode(); -} - -void LPM_EnterSNVS(void) -{ - SNVS->LPCR |= SNVS_LPCR_TOP_MASK; - while (1) /* Shutdown */ - { - } -} - -bool LPM_Init(void) -{ - uint32_t i; - uint32_t tmp_reg = 0; - - CLOCK_SetMode(kCLOCK_ModeRun); - - CCM->CGPR |= CCM_CGPR_INT_MEM_CLK_LPM_MASK; - - /* Enable RC OSC. It needs at least 4ms to be stable, so self tuning need to be enabled. */ - XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; - /* Configure RC OSC */ - XTALOSC24M->OSC_CONFIG0 = XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(0x4) | XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(0x2) | - XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(0xA7) | XTALOSC24M_OSC_CONFIG0_START_MASK | - XTALOSC24M_OSC_CONFIG0_ENABLE_MASK; - XTALOSC24M->OSC_CONFIG1 = XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(0x40) | XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(0x2DC); - /* Take some delay */ - SDK_DelayAtLeastUs(4000); - /* Add some hysteresis */ - tmp_reg = XTALOSC24M->OSC_CONFIG0; - tmp_reg &= ~(XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK | XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK); - tmp_reg |= XTALOSC24M_OSC_CONFIG0_HYST_PLUS(3) | XTALOSC24M_OSC_CONFIG0_HYST_MINUS(3); - XTALOSC24M->OSC_CONFIG0 = tmp_reg; - /* Set COUNT_1M_TRG */ - tmp_reg = XTALOSC24M->OSC_CONFIG2; - tmp_reg &= ~XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK; - tmp_reg |= XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(0x2d7); - XTALOSC24M->OSC_CONFIG2 = tmp_reg; - /* Hardware requires to read OSC_CONFIG0 or OSC_CONFIG1 to make OSC_CONFIG2 write work */ - tmp_reg = XTALOSC24M->OSC_CONFIG1; - XTALOSC24M->OSC_CONFIG1 = tmp_reg; - - /* ERR007265 */ - IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK; - - /* Initialize GPC to mask all IRQs */ - for (i = 0; i < LPM_GPC_IMR_NUM; i++) - { - GPC->IMR[i] = 0xFFFFFFFFU; - } - - return true; -} - -void LPM_Deinit(void) -{ - /* ERR007265 */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_GINT_MASK; -} - -void LPM_EnableWakeupSource(uint32_t irq) -{ - GPC_EnableIRQ(GPC, irq); -} - -void LPM_DisableWakeupSource(uint32_t irq) -{ - GPC_DisableIRQ(GPC, irq); -} - -GPT_Type *vPortGetGptBase(void) -{ - return GPT2; -} - -IRQn_Type vPortGetGptIrqn(void) -{ - return GPT2_IRQn; -} - -void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode) -{ - LPM_EnableWakeupSource(vPortGetGptIrqn()); - - LPM_EnterLowPowerIdle(); -} - -void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode) -{ - LPM_ExitLowPowerIdle(); - - LPM_OverDriveRun(); - - LPM_DisableWakeupSource(vPortGetGptIrqn()); -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h deleted file mode 100644 index ea20400..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/lpm.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPM_H_ -#define _LPM_H_ - -#include "fsl_clock.h" -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ -extern void vPortGPTIsr(void); -extern uint32_t g_savedPrimask; - -#define vPortGptIsr GPT1_IRQHandler - -#define CLOCK_CCM_HANDSHAKE_WAIT() \ - \ - do \ - { \ - while (CCM->CDHIPR != 0) \ - { \ - } \ - \ - } while (0) - -#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) -#define LPM_EnterCritical() \ - \ - do \ - { \ - g_savedPrimask = DisableGlobalIRQ(); \ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \ - \ - } while (0) - -#define LPM_ExitCritical() \ - \ - do \ - { \ - EnableGlobalIRQ(g_savedPrimask); \ - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; \ - \ - } while (0) - -#else -#define LPM_EnterCritical() -#define LPM_ExitCritical() -#endif - -/* Power mode definition of low power management. - * Waken up duration Off > Dsm > Idle > Wait > Run. - */ -typedef enum _lpm_power_mode -{ - LPM_PowerModeOverRun = 0, /* Over RUN mode, CPU won't stop running */ - - LPM_PowerModeFullRun, /* Full RUN mode, CPU won't stop running */ - - LPM_PowerModeLowSpeedRun, - - LPM_PowerModeLowPowerRun, - - LPM_PowerModeRunEnd = LPM_PowerModeLowPowerRun, - /* In system wait mode, cpu clock is gated. - * All peripheral can remain active, clock gating decided by CCGR setting. - * DRAM enters auto-refresh mode when there is no access. - */ - LPM_PowerModeSysIdle, /* System WAIT mode, also system low speed idle */ - - /* In low power idle mode, all PLL/PFD is off, cpu power is off. - * Analog modules running in low power mode. - * All high-speed peripherals are power gated - * Low speed peripherals can remain running at low frequency - * DRAM in self-refresh. - */ - LPM_PowerModeLPIdle, /* Low Power Idle mode */ - - /* In deep sleep mode, all PLL/PFD is off, XTAL is off, cpu power is off. - * All clocks are shut off except 32K RTC clock - * All high-speed peripherals are power gated - * Low speed peripherals are clock gated - * DRAM in self-refresh. - * If RTOS is used, systick will be disabled in DSM - */ - LPM_PowerModeSuspend, /* Deep Sleep mode, suspend. */ - - LPM_PowerModeSNVS, /* Power off mode, or shutdown mode */ - - LPM_PowerModeEnd = LPM_PowerModeSNVS -} lpm_power_mode_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value)); -AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_DIV(clock_div_t divider, uint32_t value)); - -/* Initialize the Low Power Management */ -bool LPM_Init(void); - -/* Deinitialize the Low Power Management */ -void LPM_Deinit(void); - -/* Enable wakeup source in low power mode */ -void LPM_EnableWakeupSource(uint32_t irq); - -/* Disable wakeup source in low power mode */ -void LPM_DisableWakeupSource(uint32_t irq); - -void ClockSelectXtalOsc(void); -void ClockSelectRcOsc(void); -void LPM_EnableWakeupSource(uint32_t irq); -void LPM_DisableWakeupSource(uint32_t irq); -void LPM_PreEnterWaitMode(void); -void LPM_PostExitWaitMode(void); -void LPM_PreEnterStopMode(void); -void LPM_PostExitStopMode(void); -void LPM_OverDriveRun(void); -void LPM_FullSpeedRun(void); -void LPM_LowSpeedRun(void); -void LPM_LowPowerRun(void); -void LPM_EnterSystemIdle(void); -void LPM_ExitSystemIdle(void); -void LPM_EnterLowPowerIdle(void); -void LPM_ExitLowPowerIdle(void); -void LPM_EnterSuspend(void); -void LPM_EnterSNVS(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _LPM_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c deleted file mode 100644 index 09c6652..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/mbed_overrides.c +++ /dev/null @@ -1,347 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2020 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "pinmap.h" -#include "fsl_clock_config.h" -#include "fsl_clock.h" -#include "fsl_xbara.h" -#include "fsl_iomuxc.h" -#include "fsl_gpio.h" -#include "lpm.h" -#include "usb_phy.h" -#include "usb_device_config.h" - -#define LPSPI_CLOCK_SOURCE_DIVIDER (7U) -#define LPI2C_CLOCK_SOURCE_DIVIDER (5U) - -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) - -uint8_t mbed_otp_mac_address(char *mac); -void mbed_default_mac_address(char *mac); - -/* MPU configuration. */ -void BOARD_ConfigMPU(void) -{ - /* Disable I cache and D cache */ - if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { - SCB_DisableICache(); - } - if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) { - SCB_DisableDCache(); - } - - /* Disable MPU */ - ARM_MPU_Disable(); - - /* MPU configure: - * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) - * API in mpu_armv7.h. - * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled. - * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. - * Use MACROS defined in mpu_armv7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO - * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. - * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache - * 0 x 0 0 Strongly Ordered shareable - * 0 x 0 1 Device shareable - * 0 0 1 0 Normal not shareable Outer and inner write through no write allocate - * 0 0 1 1 Normal not shareable Outer and inner write back no write allocate - * 0 1 1 0 Normal shareable Outer and inner write through no write allocate - * 0 1 1 1 Normal shareable Outer and inner write back no write allocate - * 1 0 0 0 Normal not shareable outer and inner noncache - * 1 1 0 0 Normal shareable outer and inner noncache - * 1 0 1 1 Normal not shareable outer and inner write back write/read acllocate - * 1 1 1 1 Normal shareable outer and inner write back write/read acllocate - * 2 x 0 0 Device not shareable - * Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy. - * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide - * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. - * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h. - */ - - /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - - /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); - -/* Region 2 setting */ -#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) - /* Setting Memory with Normal type, not shareable, outer/inner write back. */ - MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); -#endif - - /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ - MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); - - /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); - - /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ - MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); - -/* The define sets the cacheable memory to shareable, - * this suggestion is referred from chapter 2.2.1 Memory regions, - * types and attributes in Cortex-M7 Devices, Generic User Guide */ -#if defined(SDRAM_IS_SHAREABLE) - /* Region 7 setting: Memory with Normal type, shareable, outer/inner write back, write/read allocate */ - MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); -#else - /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back, write/read allocate */ - MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); -#endif - - /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be - * accessed by cache can be put here */ - /* Memory with Normal type, not shareable, non-cacheable */ - MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); - MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); - - /* Enable MPU */ - ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); - - /* Enable I cache and D cache */ - SCB_EnableDCache(); - SCB_EnableICache(); -} - -void BOARD_Init_PMIC_STBY_REQ(void) { - CLOCK_EnableClock(kCLOCK_IomuxcSnvs); /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */ - - /* GPIO configuration of PERI_PWREN on PMIC_STBY_REQ (pin L7) */ - gpio_pin_config_t PERI_PWREN_config = { - .direction = kGPIO_DigitalOutput, - .outputLogic = 0U, - .interruptMode = kGPIO_NoIntmode - }; - /* Initialize GPIO functionality on PMIC_STBY_REQ (pin L7) */ - GPIO_PinInit(GPIO5, 2U, &PERI_PWREN_config); - - IOMUXC_SetPinMux( - IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ is configured as GPIO5_IO02 */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinConfig( - IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ PAD functional properties : */ - 0x10B0U); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: R0/6 - Speed Field: medium(100MHz) - Open Drain Enable Field: Open Drain Disabled - Pull / Keep Enable Field: Pull/Keeper Enabled - Pull / Keep Select Field: Keeper - Pull Up / Down Config. Field: 100K Ohm Pull Down - Hyst. Enable Field: Hysteresis Disabled */ -} - -// called before main -void mbed_sdk_init() -{ - BOARD_ConfigMPU(); - BOARD_BootClockRUN(); - - /* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is - * connected to LCD power switch circuit. So it needs to be configured as a low-level output GPIO to reduce the - * current. */ - BOARD_Init_PMIC_STBY_REQ(); - - LPM_Init(); -} - -void spi_setup_clock() -{ - /*Set clock source for LPSPI*/ - CLOCK_SetMux(kCLOCK_LpspiMux, 1U); - CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLOCK_SOURCE_DIVIDER); -} - -uint32_t spi_get_clock(void) -{ - return (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (LPSPI_CLOCK_SOURCE_DIVIDER + 1U)); -} - -void us_ticker_setup_clock() -{ - /* Set PERCLK_CLK source to OSC_CLK*/ - CLOCK_SetMux(kCLOCK_PerclkMux, 1U); - /* Set PERCLK_CLK divider to 1 */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 0U); -} - -uint32_t us_ticker_get_clock() -{ - return CLOCK_GetFreq(kCLOCK_OscClk); -} - -void serial_setup_clock(void) -{ - /* Configure UART divider to default */ - CLOCK_SetMux(kCLOCK_UartMux, 1); /* Set UART source to OSC 24M */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ -} - -uint32_t serial_get_clock(void) -{ - uint32_t clock_freq; - - if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ { - clock_freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } else { - clock_freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); - } - - return clock_freq; -} - -void i2c_setup_clock() -{ - /* Select USB1 PLL (480 MHz) as master lpi2c clock source */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0U); - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER); -} - -uint32_t i2c_get_clock() -{ - return ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U)); -} - -void pwm_setup(uint32_t instance) -{ - /* Use default clock settings */ - /* Set the PWM Fault inputs to a low value */ - XBARA_Init(XBARA1); - - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault2); - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault3); - - switch (instance) { - case 1: - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault0); - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault1); - break; - case 2: - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm2Fault0); - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm2Fault1); - break; - case 3: - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm3Fault0); - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm3Fault1); - break; - case 4: - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm4Fault0); - XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm4Fault1); - break; - default: - break; - } -} - -uint32_t pwm_get_clock() -{ - return CLOCK_GetFreq(kCLOCK_IpgClk); -} - -// Change the NMI pin to an input. This allows NMI pin to -// be used as a low power mode wakeup. The application will -// need to change the pin back to NMI_b or wakeup only occurs once! -void NMI_Handler(void) -{ - pin_function(WAKEUP, 7); - pin_mode(WAKEUP, PullDefault); -} - -void mbed_mac_address(char *mac) { - if (mbed_otp_mac_address(mac)) { - return; - } else { - mbed_default_mac_address(mac); - } - return; -} - -uint8_t mbed_otp_mac_address(char *mac) { - /* Check if a valid MAC address is programmed to the fuse bank */ - if ((OCOTP->MAC0 != 0) && - (OCOTP->MAC1 != 0) && - (OCOTP->GP3 != 0)) { - uint16_t MAC[3]; // 3 16 bits words for the MAC - - // Read the MAC address from the OCOTP MAC registers - MAC[0] = (uint16_t)OCOTP->MAC0; // most significant half-word - MAC[1] = (uint16_t)OCOTP->MAC1; - MAC[2] = (uint16_t)OCOTP->GP3; // least significant half word - - // The network stack expects an array of 6 bytes - // so we copy, and shift and copy from the half-word array to the byte array - mac[0] = MAC[0] >> 8; - mac[1] = MAC[0]; - mac[2] = MAC[1] >> 8; - mac[3] = MAC[1]; - mac[4] = MAC[2] >> 8; - mac[5] = MAC[2]; - } else { - return 0; - } - return 1; -} - -void mbed_default_mac_address(char *mac) { - mac[0] = 0x00; - mac[1] = 0x02; - mac[2] = 0xF7; - mac[3] = 0xF0; - mac[4] = 0x00; - mac[5] = 0x00; - - return; -} - -void USB_DeviceClockInit(void) -{ - usb_phy_config_struct_t phyConfig = { - BOARD_USB_PHY_D_CAL, - BOARD_USB_PHY_TXCAL45DP, - BOARD_USB_PHY_TXCAL45DM, - }; - - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); - - USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, &phyConfig); -} - -uint32_t USB_DeviceGetIrqNumber(void) -{ - uint8_t irqNumber; - - uint8_t usbDeviceEhciIrq[] = USBHS_IRQS; - irqNumber = usbDeviceEhciIrq[CONTROLLER_ID - kUSB_ControllerEhci0]; - - return irqNumber; -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/pinmap.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/pinmap.c deleted file mode 100644 index 15c3f6e..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/pinmap.c +++ /dev/null @@ -1,159 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "PeripheralPins.h" -#include "mbed_error.h" -#include "fsl_clock.h" - -/* Array of IOMUX base address. */ -static uint32_t iomux_base_addrs[FSL_FEATURE_SOC_IGPIO_COUNT] = { 0x401F80BC, 0x401F813C, 0u, 0x401F8014, 0x400A8000 }; - -/* Get the IOMUX register address from the GPIO3 pin number */ -static uint32_t get_iomux_reg_base(PinName pin) -{ - int32_t gpio_pin = pin & 0xFF; - uint32_t retval = 0; - - if ((gpio_pin >= 0) && (gpio_pin < 12)) { - retval = 0x401F81D4 + (gpio_pin * 4); - } else if ((gpio_pin >= 12) && (gpio_pin < 18)) { - retval = 0x401F81BC + ((gpio_pin - 12) * 4); - } else if ((gpio_pin >= 18) && (gpio_pin < 28)) { - retval = 0x401F8094 + ((gpio_pin - 18) * 4); - } - - return retval; -} - -void pin_function(PinName pin, int function) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t muxregister = iomux_base_addrs[(pin >> GPIO_PORT_SHIFT) - 1]; - uint32_t daisyregister; - - CLOCK_EnableClock(kCLOCK_Iomuxc); - - /* Get mux register address */ - if (muxregister == 0) { - muxregister = get_iomux_reg_base(pin); - } else { - muxregister = muxregister + ((pin & 0xFF) * 4); - } - - /* Write to the mux register */ - *((volatile uint32_t *)muxregister) = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(function) | - IOMUXC_SW_MUX_CTL_PAD_SION((function >> SION_BIT_SHIFT) & 0x1); - - /* If required write to the input daisy register */ - daisyregister = (function >> DAISY_REG_SHIFT) & 0xFFF; - if (daisyregister != 0) { - daisyregister = daisyregister + 0x401F8000; - *((volatile uint32_t *)daisyregister) = IOMUXC_SELECT_INPUT_DAISY(((function >> DAISY_REG_VALUE_SHIFT) & 0xF)); - } -} - -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - uint32_t instance = pin >> GPIO_PORT_SHIFT; - uint32_t reg; - uint32_t muxregister = iomux_base_addrs[instance - 1]; - uint32_t configregister; - - if (muxregister == 0) { - muxregister = get_iomux_reg_base(pin); - } else { - muxregister = muxregister + ((pin & 0xFF) * 4); - } - - /* Get pad register address */ - if (instance == 5) { - configregister = muxregister + 0x10; - } else { - configregister = muxregister + 0x1F0; - } - - reg = *((volatile uint32_t *)configregister); - switch (mode) { - case PullNone: - /* Write 0 to the PUE bit & 1 to the PKE bit to set the pad to keeper mode */ - reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); - reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK); - break; - case PullDown: - /* Write 1 to PKE & PUE bit to enable the pull configuration and 0 to PUS bit for 100K pull down */ - reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); - reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); - break; - case PullUp_47K: - /* Write 1 to PKE & PUE bit to enable the pull configuration and 1 to PUS bit for 47K pull up*/ - reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); - reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(1); - reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); - break; - case PullUp_100K: - /* Write 1 to PKE & PUE bit to enable the pull configuration and 2 to PUS bit for 100K pull up*/ - reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); - reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2); - reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); - break; - case PullUp_22K: - /* Write 1 to PKE & PUE bit to enable the pull configuration and 3 to PUS bit for 22K pull up*/ - reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); - reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(3); - reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); - break; - default: - break; - } - - /* Below settings for DSE and SPEED fields per test results */ - reg = (reg & ~(IOMUXC_SW_PAD_CTL_PAD_DSE_MASK | IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)) | - IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2); - - /* Write value to the pad register */ - *((volatile uint32_t *)configregister) = reg; -} - -void pin_mode_opendrain(PinName pin, bool enable) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t instance = pin >> GPIO_PORT_SHIFT; - uint32_t muxregister = iomux_base_addrs[instance - 1]; - uint32_t configregister; - - if (muxregister == 0) { - muxregister = get_iomux_reg_base(pin); - } else { - muxregister = muxregister + ((pin & 0xFF) * 4); - } - - /* Get pad register address */ - if (instance == 5) { - configregister = muxregister + 0x10; - } else { - configregister = muxregister + 0x1F0; - } - - if (enable) { - *((volatile uint32_t *)configregister) |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK; - } else { - *((volatile uint32_t *)configregister) &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK; - } -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/serial_api.c deleted file mode 100644 index 0af83e9..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/serial_api.c +++ /dev/null @@ -1,382 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "serial_api.h" - -#if DEVICE_SERIAL - -// math.h required for floating point operations for baud rate calculation -#include -#include "mbed_assert.h" - -#include - -#include "cmsis.h" -#include "pinmap.h" -#include "fsl_lpuart.h" -#include "PeripheralPins.h" -#include "fsl_clock_config.h" - -/* LPUART starts from index 1 */ -static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0}; -static uart_irq_handler irq_handler; -/* Array of UART peripheral base address. */ -static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -extern void serial_setup_clock(void); -extern uint32_t serial_get_clock(void); - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); - uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - obj->index = pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)obj->index != NC); - - serial_setup_clock(); - - lpuart_config_t config; - LPUART_GetDefaultConfig(&config); - config.baudRate_Bps = 9600; - config.enableTx = false; - config.enableRx = false; - - LPUART_Init(uart_addrs[obj->index], &config, serial_get_clock()); - - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); - - if (tx != NC) { - LPUART_EnableTx(uart_addrs[obj->index], true); - pin_mode(tx, PullDefault); - } - if (rx != NC) { - LPUART_EnableRx(uart_addrs[obj->index], true); - pin_mode(rx, PullDefault); - } - - if (obj->index == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - LPUART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, serial_get_clock()); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - LPUART_Type *base = uart_addrs[obj->index]; - uint8_t temp; - /* Set bit count and parity mode. */ - temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); - if (parity != ParityNone) { - /* Enable Parity */ - temp |= (LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK); - if (parity == ParityOdd) { - temp |= LPUART_CTRL_PT_MASK; - } else if (parity == ParityEven) { - // PT=0 so nothing more to do - } else { - // Hardware does not support forced parity - MBED_ASSERT(0); - } - } - base->CTRL = temp; - -#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT - /* set stop bit per char */ - temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; - base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)--stop_bits); -#endif -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) -{ - LPUART_Type *base = uart_addrs[index]; - - /* If RX overrun. */ - if (LPUART_STAT_OR_MASK & base->STAT) { - /* Read base->D, otherwise the RX does not work. */ - (void)base->DATA; - LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); - } - - if (serial_irq_ids[index] != 0) { - if (transmit_empty) { - irq_handler(serial_irq_ids[index], TxIrq); - } - - if (receive_full) { - irq_handler(serial_irq_ids[index], RxIrq); - } - } -} - -void uart1_irq() -{ - uint32_t status_flags = LPUART1->STAT; - uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1); -} - -void uart2_irq() -{ - uint32_t status_flags = LPUART2->STAT; - uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 2); -} - -void uart3_irq() -{ - uint32_t status_flags = LPUART3->STAT; - uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 3); -} - -void uart4_irq() -{ - uint32_t status_flags = LPUART4->STAT; - uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 4); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS; - uint32_t vector = 0; - - switch (obj->index) { - case 1: - vector = (uint32_t)&uart1_irq; - break; - case 2: - vector = (uint32_t)&uart2_irq; - break; - case 3: - vector = (uint32_t)&uart3_irq; - break; - case 4: - vector = (uint32_t)&uart4_irq; - break; - default: - break; - } - - if (enable) { - switch (irq) { - case RxIrq: - LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable); - break; - case TxIrq: - LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable); - break; - default: - break; - } - NVIC_SetVector(uart_irqs[obj->index], vector); - NVIC_EnableIRQ(uart_irqs[obj->index]); - - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - switch (irq) { - case RxIrq: - LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable); - break; - case TxIrq: - LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable); - break; - default: - break; - } - switch (other_irq) { - case RxIrq: - all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_RxDataRegFullInterruptEnable) == 0); - break; - case TxIrq: - all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_TxDataRegEmptyInterruptEnable) == 0); - break; - default: - break; - } - if (all_disabled) - NVIC_DisableIRQ(uart_irqs[obj->index]); - } -} - -int serial_getc(serial_t *obj) -{ - uint8_t data; - - LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1); - return data; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)); - LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c); -} - -int serial_readable(serial_t *obj) -{ - uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]); - if (status_flags & kLPUART_RxOverrunFlag) { - LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag); - } - return (status_flags & kLPUART_RxDataRegFullFlag); -} - -int serial_writable(serial_t *obj) -{ - uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]); - if (status_flags & kLPUART_RxOverrunFlag) { - LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag); - } - return (status_flags & kLPUART_TxDataRegEmptyFlag); -} - -void serial_clear(serial_t *obj) -{ - -} - -void serial_pinout_tx(PinName tx) -{ - pinmap_pinout(tx, PinMap_UART_TX); -} - -void serial_break_set(serial_t *obj) -{ - uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK; -} - -void serial_break_clear(serial_t *obj) -{ - uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_TX; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_RX; -} - -const PinMap *serial_cts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_CTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_CTS; -} - -const PinMap *serial_rts_pinmap() -{ -#if !DEVICE_SERIAL_FC - static const PinMap PinMap_UART_RTS[] = { - {NC, NC, 0} - }; -#endif - - return PinMap_UART_RTS; -} - -static int serial_is_enabled(uint32_t uart_index) -{ - int clock_enabled = 0; - switch (uart_index) { - case 1: - clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG12_MASK) >> CCM_CCGR5_CG12_SHIFT; - break; - case 2: - clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG14_MASK) >> CCM_CCGR0_CG14_SHIFT; - break; - case 3: - clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG6_MASK) >> CCM_CCGR0_CG6_SHIFT; - break; - case 4: - clock_enabled = (CCM->CCGR1 & CCM_CCGR1_CG12_MASK) >> CCM_CCGR1_CG12_SHIFT; - break; - case 5: - clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG1_MASK) >> CCM_CCGR3_CG1_SHIFT; - break; - case 6: - clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG3_MASK) >> CCM_CCGR3_CG3_SHIFT; - break; - case 7: - clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG13_MASK) >> CCM_CCGR5_CG13_SHIFT; - break; - case 8: - clock_enabled = (CCM->CCGR6 & CCM_CCGR6_CG7_MASK) >> CCM_CCGR6_CG7_SHIFT; - break; - default: - break; - } - - return clock_enabled; -} - -bool serial_check_tx_ongoing() -{ - LPUART_Type *base; - int i; - bool uart_tx_ongoing = false; - - /* The first LPUART instance number is 1 */ - for (i = 1; i <= FSL_FEATURE_SOC_LPUART_COUNT; i++) { - /* First check if UART is enabled */ - if (!serial_is_enabled(i)) { - /* UART is not enabled, check the next instance */ - continue; - } - - base = uart_addrs[i]; - - /* Check if data is waiting to be written out of transmit buffer */ - if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) { - uart_tx_ongoing = true; - break; - } - } - - return uart_tx_ongoing; -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/sleep.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/sleep.c deleted file mode 100644 index 44e1ede..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/sleep.c +++ /dev/null @@ -1,47 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "fsl_clock.h" - -extern void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode); -extern void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode); -extern bool serial_check_tx_ongoing(); - -void hal_sleep(void) -{ - __DSB(); - __WFI(); - __ISB(); -} - -void hal_deepsleep(void) -{ - /* Check if any of the UART's is transmitting data */ - if (serial_check_tx_ongoing()) { - return; - } - - vPortPRE_SLEEP_PROCESSING(kCLOCK_ModeStop); - - __DSB(); - __WFI(); - __ISB(); - - vPortPOST_SLEEP_PROCESSING(kCLOCK_ModeStop); -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c deleted file mode 100644 index 5abd97c..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c +++ /dev/null @@ -1,615 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "specific.h" -#include "fsl_common.h" -#include "fsl_clock.h" -#include "lpm.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -const clock_arm_pll_config_t armPllConfig_PowerMode = { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_PowerMode = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_PowerMode = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; - -AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode)); - -#define NUMBER_OF_CCM_GATE_REGS 7 -static uint32_t clock_gate_values[NUMBER_OF_CCM_GATE_REGS]; - -void SwitchSystemClocks(lpm_power_mode_t power_mode) -{ -#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) - { - } - FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; - - /* Disable clock gate of flexspi. */ - CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK); -#endif - switch (power_mode) - { - case LPM_PowerModeOverRun: - CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0 - /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */ - //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); - //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL - CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK - break; - case LPM_PowerModeFullRun: - CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0 - /* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */ - CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); - CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL - CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK - break; - case LPM_PowerModeLowSpeedRun: - case LPM_PowerModeSysIdle: - CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz -#ifdef HYPERFLASH_BOOT - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode -#else - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 3); // FLEXSPI in SDR mode -#endif - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2 - /* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */ - CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 3); - CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // Switch PRE_PERIPH_CLK to SYS PLL - CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // Switch PERIPH_CLK to PRE_PERIPH_CLK - break; - case LPM_PowerModeLowPowerRun: - case LPM_PowerModeLPIdle: - CLOCK_SET_DIV(kCLOCK_PeriphClk2Div, 0); - CLOCK_SET_MUX(kCLOCK_PeriphClk2Mux, 1); // PERIPH_CLK2 mux to OSC - CLOCK_SET_MUX(kCLOCK_PeriphMux, 1); // PERIPH_CLK mux to PERIPH_CLK2 - CLOCK_SET_DIV(kCLOCK_SemcDiv, 0); - CLOCK_SET_MUX(kCLOCK_SemcMux, 0); // SEMC mux to PERIPH_CLK - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre - /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */ - //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 1); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); - //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - break; - default: - break; - } - -#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Enable clock gate of flexspi. */ - CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK); - -#ifdef HYPERFLASH_BOOT - if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode)) - { - FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19); - } - else - { - FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15); - } -#endif - - FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; - while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) - { - } - while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) - { - } -#endif -} - -void ClockSetToOverDriveRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - //ClockSelectXtalOsc(); - - /* Init ARM PLL */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - CLOCK_InitArmPll(&armPllConfig_PowerMode); - - /* Init SYS PLL*/ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - - /* Init USB1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; - - /* Init USB2 PLL*/ - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK; - while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - - /* Init AUDIO PLL */ - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - - /* Init VIDEO PLL */ - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - - /* Init ENET PLL */ - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeOverRun); - LPM_ExitCritical(); -} - -void ClockSetToFullSpeedRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectXtalOsc(); - - /* Init ARM PLL */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - CLOCK_InitArmPll(&armPllConfig_PowerMode); - - /* Init SYS PLL. */ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - - /* Init USB1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; - - /* Init USB2 PLL*/ - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK; - while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - - /* Init AUDIO PLL */ - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - - /* Init VIDEO PLL */ - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - - /* Init ENET PLL */ - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeFullRun); - LPM_ExitCritical(); -} - -void ClockSetToLowSpeedRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectXtalOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Init SYS PLL */ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - - /* Deinit SYS PLL PFD 0 1 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Deinit USB1 PLL */ - CLOCK_DeinitUsb1Pll(); - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowSpeedRun); - LPM_ExitCritical(); -} - -void ClockSetToLowPowerRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectRcOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Deinit SYS PLL */ - CLOCK_DeinitSysPll(); - - /* Deinit SYS PLL PFD 0 1 2 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - CLOCK_DeinitSysPfd(kCLOCK_Pfd2); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Power Down USB1 PLL */ - CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK; - CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK; - CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK; - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); -} - -void ClockSetToSystemIdle(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectXtalOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Init SYS PLL */ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - - /* Deinit SYS PLL PFD 0 1 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Deinit USB1 PLL */ - CLOCK_DeinitUsb1Pll(); - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeSysIdle); - LPM_ExitCritical(); -} - -void ClockSetToLowPowerIdle(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - //ClockSelectRcOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Deinit SYS PLL */ - CLOCK_DeinitSysPll(); - - /* Deinit SYS PLL PFD 0 1 2 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - CLOCK_DeinitSysPfd(kCLOCK_Pfd2); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Deinit USB1 PLL */ - CLOCK_DeinitUsb1Pll(); - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLPIdle); - LPM_ExitCritical(); -} - -void SetLowPowerClockGate(void) -{ - /* Save of the clock gate registers */ - clock_gate_values[0] = CCM->CCGR0; - clock_gate_values[1] = CCM->CCGR1; - clock_gate_values[2] = CCM->CCGR2; - clock_gate_values[3] = CCM->CCGR3; - clock_gate_values[4] = CCM->CCGR4; - clock_gate_values[5] = CCM->CCGR5; - clock_gate_values[6] = CCM->CCGR6; - - /* Set low power gate values */ - CCM->CCGR0 = CCM_CCGR0_CG0(1) | CCM_CCGR0_CG1(1) | CCM_CCGR0_CG3(3) | CCM_CCGR0_CG11(1) | CCM_CCGR0_CG12(1); - CCM->CCGR1 = CCM_CCGR1_CG9(3) | CCM_CCGR1_CG10(1) | CCM_CCGR1_CG13(1) | CCM_CCGR1_CG14(1) | CCM_CCGR1_CG15(1); - CCM->CCGR2 = CCM_CCGR2_CG2(1) | CCM_CCGR2_CG8(1) | CCM_CCGR2_CG9(1) | CCM_CCGR2_CG10(1); - CCM->CCGR3 = CCM_CCGR3_CG2(1) | CCM_CCGR3_CG4(1) | CCM_CCGR3_CG9(1) | CCM_CCGR3_CG14(3) | CCM_CCGR3_CG15(1); - CCM->CCGR4 = - CCM_CCGR4_CG1(1) | CCM_CCGR4_CG2(1) | CCM_CCGR4_CG4(1) | CCM_CCGR4_CG5(1) | CCM_CCGR4_CG6(1) | CCM_CCGR4_CG7(1); - CCM->CCGR5 = CCM_CCGR5_CG0(1) | CCM_CCGR5_CG1(1) | CCM_CCGR5_CG4(1) | CCM_CCGR5_CG6(1) | CCM_CCGR5_CG12(1) | - CCM_CCGR5_CG14(1) | CCM_CCGR5_CG15(1); - /* We can enable DCDC when need to config it and close it after configuration */ - CCM->CCGR6 = CCM_CCGR6_CG3(1) | CCM_CCGR6_CG4(1) | CCM_CCGR6_CG5(1) | CCM_CCGR6_CG9(1) | CCM_CCGR6_CG10(1) | - CCM_CCGR6_CG11(1); -} - -void SetRestoreClockGate(void) -{ - CCM->CCGR0 = clock_gate_values[0]; - CCM->CCGR1 = clock_gate_values[1]; - CCM->CCGR2 = clock_gate_values[2]; - CCM->CCGR3 = clock_gate_values[3]; - CCM->CCGR4 = clock_gate_values[4]; - CCM->CCGR5 = clock_gate_values[5]; - CCM->CCGR6 = clock_gate_values[6]; -} - -void PowerDownUSBPHY(void) -{ - USBPHY1->CTRL = 0xFFFFFFFF; - USBPHY2->CTRL = 0xFFFFFFFF; -} - -void ConfigUartRxPinToGpio(void) -{ - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, 0); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, - IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2) | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); -} - -void ReConfigUartRxPin(void) -{ - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_SW_PAD_CTL_PAD_SPEED(2)); -} - -#define GPR4_STOP_REQ_BITS \ - (IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) - -#define GPR4_STOP_ACK_BITS \ - (IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) - -#define GPR7_STOP_REQ_BITS \ - (IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) - -#define GPR7_STOP_ACK_BITS \ - (IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) - -#define GPR8_DOZE_BITS \ - (IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) - -#define GPR8_STOP_MODE_BITS \ - (IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) - -#define GPR12_DOZE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) - -#define GPR12_STOP_MODE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) - -void PeripheralEnterDozeMode(void) -{ - IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS; - IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS; -} - -void PeripheralExitDozeMode(void) -{ - IOMUXC_GPR->GPR8 = 0x00000000; - IOMUXC_GPR->GPR12 = 0x00000000; -} - -void PeripheralEnterStopMode(void) -{ - IOMUXC_GPR->GPR4 = IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK; - while ((IOMUXC_GPR->GPR4 & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) != IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) - { - } - IOMUXC_GPR->GPR4 = GPR4_STOP_REQ_BITS; - IOMUXC_GPR->GPR7 = GPR7_STOP_REQ_BITS; - IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS | GPR8_STOP_MODE_BITS; - IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS | GPR12_STOP_MODE_BITS; - while ((IOMUXC_GPR->GPR4 & GPR4_STOP_ACK_BITS) != GPR4_STOP_ACK_BITS) - { - } - while ((IOMUXC_GPR->GPR7 & GPR7_STOP_ACK_BITS) != GPR7_STOP_ACK_BITS) - { - } -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.h deleted file mode 100644 index cc384b4..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _SPECIFIC_H_ -#define _SPECIFIC_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define FLEXSPI_INST FLEXSPI -#define HAS_WAKEUP_PIN (1) - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -void ClockSetToOverDriveRun(void); -void ClockSetToFullSpeedRun(void); -void ClockSetToLowSpeedRun(void); -void ClockSetToLowPowerRun(void); -void ClockSetToSystemIdle(void); -void ClockSetToLowPowerIdle(void); - -void SetLowPowerClockGate(void); -void SetRestoreClockGate(void); -void PowerDownUSBPHY(void); -void ConfigUartRxPinToGpio(void); -void ReConfigUartRxPin(void); -void PeripheralEnterDozeMode(void); -void PeripheralExitDozeMode(void); -void PeripheralEnterStopMode(void); -void APP_PrintRunFrequency(int32_t run_freq_only); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _SPECIFIC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/trng_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/trng_api.c deleted file mode 100644 index f82ae02..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/trng_api.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * - * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#include -#include "cmsis.h" -#include "fsl_trng.h" -#include "trng_api.h" - -void trng_init(trng_t *obj) -{ - (void)obj; - trng_config_t trngConfig; - TRNG_GetDefaultConfig(&trngConfig); - TRNG_Init(TRNG, &trngConfig); -} - -void trng_free(trng_t *obj) -{ - (void)obj; - TRNG_Deinit(TRNG); -} - -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - (void)obj; - - if(TRNG_GetRandomData(TRNG, output, length) != kStatus_Success) { - return -1; - } - *output_length = length; - - return 0; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/us_ticker.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/us_ticker.c deleted file mode 100644 index 87c0dcc..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/us_ticker.c +++ /dev/null @@ -1,149 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "us_ticker_defines.h" -#include "fsl_pit.h" -#include "fsl_clock_config.h" - -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - 1000000, // 1 MHz - 32 // 32 bit counter - }; - return &info; -} - -static bool us_ticker_inited = false; - -extern void us_ticker_setup_clock(); -extern uint32_t us_ticker_get_clock(); - -static void pit_isr(void) -{ - PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); - PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); - PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_StopTimer(PIT, kPIT_Chnl_3); - - us_ticker_irq_handler(); -} - -/** Initialize the high frequency ticker - * - */ -void us_ticker_init(void) -{ - /* Common for ticker/timer. */ - uint32_t busClock; - - us_ticker_setup_clock(); - - busClock = us_ticker_get_clock(); - - /* Let the timer to count if re-init. */ - if (!us_ticker_inited) { - /* Structure to initialize PIT. */ - pit_config_t pitConfig; - - PIT_GetDefaultConfig(&pitConfig); - PIT_Init(PIT, &pitConfig); - - PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); - PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); - PIT_StartTimer(PIT, kPIT_Chnl_0); - PIT_StartTimer(PIT, kPIT_Chnl_1); - } - - /* Configure interrupt generation counters and disable ticker interrupts. */ - PIT_StopTimer(PIT, kPIT_Chnl_3); - PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); - PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT_IRQn, (uint32_t) pit_isr); - NVIC_EnableIRQ(PIT_IRQn); - PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); - - us_ticker_inited = true; -} - -/** Read the current counter - * - * @return The current timer's counter value in ticks - */ -uint32_t (us_ticker_read)() -{ - return us_ticker_read(); -} - -/** Disable us ticker interrupt - * - */ -void us_ticker_disable_interrupt(void) -{ - PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); -} - -/** Clear us ticker interrupt - * - */ -void us_ticker_clear_interrupt(void) -{ - PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); -} - -/** Set interrupt for specified timestamp - * - * @param timestamp The time in ticks when interrupt should be generated - */ -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - /* We get here absolute interrupt time which takes into account counter overflow. - * Since we use additional count-down timer to generate interrupt we need to calculate - * load value based on time-stamp. - */ - const uint32_t now_ticks = us_ticker_read(); - uint32_t delta_ticks = - timestamp >= now_ticks ? timestamp - now_ticks : (uint32_t)((uint64_t) timestamp + 0xFFFFFFFF - now_ticks); - - if (delta_ticks == 0) { - /* The requested delay is less than the minimum resolution of this counter. */ - delta_ticks = 1; - } - - PIT_StopTimer(PIT, kPIT_Chnl_3); - PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, delta_ticks); - PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); - PIT_StartTimer(PIT, kPIT_Chnl_3); - PIT_StartTimer(PIT, kPIT_Chnl_2); -} - -/** Fire us ticker interrupt - * - */ -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(PIT_IRQn); -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/us_ticker_defines.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/us_ticker_defines.h deleted file mode 100644 index 46c07de..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/us_ticker_defines.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef _NXP_US_TICKER_DEFINES_H_ -#define _NXP_US_TICKER_DEFINES_H_ - -#include "fsl_pit.h" - -#define US_TICKER_PERIOD_NUM 1 -#define US_TICKER_PERIOD_DEN 1 - -#define US_TICKER_MASK 0xFFFFFFFF - -/* Macro-optimised form of us_ticker_read */ -#define us_ticker_read() (~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1))) - -#endif /* _NXP_US_TICKER_DEFINES_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c deleted file mode 100644 index 104479f..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "evkbimxrt1050_flexspi_nor_config.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"), used)) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -#ifdef HYPERFLASH_BOOT -const flexspi_nor_config_t hyperflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .columnAddressWidth = 3u, - // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock - .controllerMiscOption = - (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) | - (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable), - .sflashPadType = kSerialFlash_8Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .sflashA1Size = 64u * 1024u * 1024u, - .dataValidTime = {16u, 16u}, - .lookupTable = { - // Read LUTs - FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18), - FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06), - FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), - }, - }, - .pageSize = 512u, - .sectorSize = 256u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = true, -}; -#else -const flexspi_nor_config_t qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .columnAddressWidth = 0u, - .configCmdEnable = 0u, - .controllerMiscOption = 0u, - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_133MHz, - .lutCustomSeqEnable = 0u, - .sflashA1Size = 0x00800000u, /* 8MB/64Mbit */ - .lookupTable = { - // Fast read sequence - [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), - [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x02), - [2] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0), - [3] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0), - }, - }, -}; -#endif -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h deleted file mode 100644 index 7b422d0..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ -#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ - -#include -#include -#include "fsl_common.h" - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/* FLEXSPI memory config block related defintions */ -#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian -#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 -#define FLEXSPI_CFG_BLK_SIZE (512) - -/* FLEXSPI Feature related definitions */ -#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 - -/* Lookup table related defintions */ -#define CMD_INDEX_READ 0 -#define CMD_INDEX_READSTATUS 1 -#define CMD_INDEX_WRITEENABLE 2 -#define CMD_INDEX_WRITE 4 - -#define CMD_LUT_SEQ_IDX_READ 0 -#define CMD_LUT_SEQ_IDX_READSTATUS 1 -#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 -#define CMD_LUT_SEQ_IDX_WRITE 9 - -#define CMD_SDR 0x01 -#define CMD_DDR 0x21 -#define RADDR_SDR 0x02 -#define RADDR_DDR 0x22 -#define CADDR_SDR 0x03 -#define CADDR_DDR 0x23 -#define MODE1_SDR 0x04 -#define MODE1_DDR 0x24 -#define MODE2_SDR 0x05 -#define MODE2_DDR 0x25 -#define MODE4_SDR 0x06 -#define MODE4_DDR 0x26 -#define MODE8_SDR 0x07 -#define MODE8_DDR 0x27 -#define WRITE_SDR 0x08 -#define WRITE_DDR 0x28 -#define READ_SDR 0x09 -#define READ_DDR 0x29 -#define LEARN_SDR 0x0A -#define LEARN_DDR 0x2A -#define DATSZ_SDR 0x0B -#define DATSZ_DDR 0x2B -#define DUMMY_SDR 0x0C -#define DUMMY_DDR 0x2C -#define DUMMY_RWDS_SDR 0x0D -#define DUMMY_RWDS_DDR 0x2D -#define JMP_ON_CS 0x1F -#define STOP 0 - -#define FLEXSPI_1PAD 0 -#define FLEXSPI_2PAD 1 -#define FLEXSPI_4PAD 2 -#define FLEXSPI_8PAD 3 - -#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ - (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ - FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) - -//!@brief Definitions for FlexSPI Serial Clock Frequency -typedef enum _FlexSpiSerialClockFreq -{ - kFlexSpiSerialClk_30MHz = 1, - kFlexSpiSerialClk_50MHz = 2, - kFlexSpiSerialClk_60MHz = 3, - kFlexSpiSerialClk_75MHz = 4, - kFlexSpiSerialClk_80MHz = 5, - kFlexSpiSerialClk_100MHz = 6, - kFlexSpiSerialClk_133MHz = 7, - kFlexSpiSerialClk_166MHz = 8, - kFlexSpiSerialClk_200MHz = 9, -} flexspi_serial_clk_freq_t; - -//!@brief FlexSPI clock configuration type -enum -{ - kFlexSpiClk_SDR, //!< Clock configure for SDR mode - kFlexSpiClk_DDR, //!< Clock configurat for DDR mode -}; - -//!@brief FlexSPI Read Sample Clock Source definition -typedef enum _FlashReadSampleClkSource -{ - kFlexSPIReadSampleClk_LoopbackInternally = 0, - kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, - kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, - kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, -} flexspi_read_sample_clk_t; - -//!@brief Misc feature bit definitions -enum -{ - kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable - kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable - kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable - kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable - kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable - kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable - kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. -}; - -//!@brief Flash Type Definition -enum -{ - kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR - kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND - kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH - kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND - kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs -}; - -//!@brief Flash Pad Definitions -enum -{ - kSerialFlash_1Pad = 1, - kSerialFlash_2Pads = 2, - kSerialFlash_4Pads = 4, - kSerialFlash_8Pads = 8, -}; - -//!@brief FlexSPI LUT Sequence structure -typedef struct _lut_sequence -{ - uint8_t seqNum; //!< Sequence Number, valid number: 1-16 - uint8_t seqId; //!< Sequence Index, valid number: 0-15 - uint16_t reserved; -} flexspi_lut_seq_t; - -//!@brief Flash Configuration Command Type -enum -{ - kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc - kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command - kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode - kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode - kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode - kDeviceConfigCmdType_Reset, //!< Reset device command -}; - -//!@brief FlexSPI Memory Configuration Block -typedef struct _FlexSPIConfig -{ - uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL - uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix - uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use - uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 - uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 - uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 - uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For - //! Serial NAND, need to refer to datasheet - uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable - uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, - //! Generic configuration, etc. - uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for - //! DPI/QPI/OPI switch or reset command - flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt - //! sequence number, [31:16] Reserved - uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration - uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable - uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe - flexspi_lut_seq_t - configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq - uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use - uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands - uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use - uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more - //! details - uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details - uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal - uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot - //! Chapter for more details - uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot - //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH - uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use - uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 - uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 - uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 - uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 - uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value - uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value - uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value - uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value - uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command - uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands - uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns - uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 - uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - - //! busy flag is 0 when flash device is busy - uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences - flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences - uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use -} flexspi_mem_config_t; - -/* */ -#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 -#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 -#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 -#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 -#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 -#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 -#define NOR_CMD_INDEX_DUMMY 6 //!< 6 -#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 - -#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ - CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ - 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ - CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ - 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ - CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block -#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ - 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block -#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ - 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk - -/* - * Serial NOR configuration block - */ -typedef struct _flexspi_nor_config -{ - flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI - uint32_t pageSize; //!< Page size of Serial NOR - uint32_t sectorSize; //!< Sector size of Serial NOR - uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command - uint8_t isUniformBlockSize; //!< Sector/Block size is the same - uint8_t reserved0[2]; //!< Reserved for future use - uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 - uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command - uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false - uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution - uint32_t blockSize; //!< Block size - uint32_t reserve2[11]; //!< Reserved for future use -} flexspi_nor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c deleted file mode 100644 index a2c0267..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#include "evkbimxrt1050_sdram_ini_dcd.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_board" -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.dcd_data"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.dcd_data" -#endif - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: DCDx V2.0 -processor: MIMXRT1052xxxxB -mcu_data: ksdk2_0 -processor_version: 0.0.19 -output_format: c_array - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ -/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ -const uint8_t dcd_data[] = { - /* HEADER */ - /* Tag */ - 0xD2, - /* Image Length */ - 0x04, 0x30, - /* Version */ - 0x41, - - /* COMMANDS */ - - /* group: 'Imported Commands' */ - /* #1.1-117, command header bytes for merged 'Write - value' command */ - 0xCC, 0x03, 0xAC, 0x04, - /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ - 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, - /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ - 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, - /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1D0000, size: 4 */ - 0x40, 0x0D, 0x81, 0x00, 0x00, 0x1D, 0x00, 0x00, - /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ - 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, - /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, - /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, - /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, - /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, - /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, - /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, - /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, - /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, - /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, - /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, - /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, - /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, - /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, - /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, - /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, - /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, - /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, - /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, - /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, - /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, - /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, - /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, - /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, - /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, - /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, - /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, - /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, - /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, - /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, - /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, - /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, - /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, - /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, - /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, - /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, - /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, - /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, - /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, - /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, size: 4 */ - 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, - /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xB4, 0x00, 0x00, 0x00, 0x00, - /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, value: 0x00, size: 4 */ - 0x40, 0x1F, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, - /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, - /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, - /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, - /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, - /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, - /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, - /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, - /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, - /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, - /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, - /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, - /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, - /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, - /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, - /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, - /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, - /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, - /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, - /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, - /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, - /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, - /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, - /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, - /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, - /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, - /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, - /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, - /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, - /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, - /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, - /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, - /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, - /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, - /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, - /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, - /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, - /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, - /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, - /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, - /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, - /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0xA4, 0x00, 0x01, 0x10, 0xF9, - /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, value: 0x110F9, size: 4 */ - 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, - /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ - 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, - /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */ - 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, - /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */ - 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, - /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, - /* #1.99, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, - /* #1.100, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, - /* #1.101, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, - /* #1.102, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ - 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, - /* #1.103, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ - 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, - /* #1.104, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ - 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, - /* #1.105, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ - 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, - /* #1.106, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, - /* #1.107, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ - 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, - /* #1.108, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ - 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, - /* #1.109, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ - 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, - /* #1.110, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ - 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, - /* #1.111, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ - 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, - /* #1.112, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ - 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, - /* #1.113, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ - 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, - /* #1.114, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ - 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, - /* #1.115, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ - 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, - /* #1.116, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #1.117, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, - /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #3.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #5.1-2, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x14, 0x04, - /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, - /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #7.1-3, command header bytes for merged 'Write - value' command */ - 0xCC, 0x00, 0x1C, 0x04, - /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ - 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, - /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, - /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, - /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, - /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ - 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; -/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ - -#else -const uint8_t dcd_data[] = {0x00}; -#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ -#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h deleted file mode 100644 index 7f57e7c..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_sdram_ini_dcd.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*********************************************************************************************************************** - * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file - * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. - **********************************************************************************************************************/ - -#ifndef __EVKBIMXRT1050_SDRAM_INI_DCD__ -#define __EVKBIMXRT1050_SDRAM_INI_DCD__ - -#include - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_BOARD driver version 2.0.0. */ -#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/************************************* - * DCD Data - *************************************/ -#define DCD_TAG_HEADER (0xD2) -#define DCD_VERSION (0x41) -#define DCD_TAG_HEADER_SHIFT (24) -#define DCD_ARRAY_SIZE 1 - -#endif /* __EVKBIMXRT1050_SDRAM_INI_DCD__ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/CMakeLists.txt new file mode 100644 index 0000000..7d38d5d --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/CMakeLists.txt @@ -0,0 +1,19 @@ + +# Target for Teensy 4.x common files +add_library(mbed-teensy-4x INTERFACE) +target_sources(mbed-teensy-4x INTERFACE + bootdata.c) +target_include_directories(mbed-teensy-4x INTERFACE .) +target_link_libraries(mbed-teensy-4x INTERFACE + mbed-mimxrt105x) + +# Target for Teensy 4.0 +add_library(mbed-teensy-40 INTERFACE) +target_link_libraries(mbed-teensy-40 INTERFACE + mbed-teensy-4x) +target_include_directories(mbed-teensy-40 INTERFACE TARGET_TEENSY_40) + +# Target for Teensy 4.1 +add_library(mbed-teensy-41 INTERFACE) +target_link_libraries(mbed-teensy-41 INTERFACE + mbed-teensy-4x) \ No newline at end of file diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/TARGET_TEENSY_40/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/TARGET_TEENSY_40/PinNames.h new file mode 100644 index 0000000..c7c9d52 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/TARGET_TEENSY_40/PinNames.h @@ -0,0 +1,260 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* MBED TARGET LIST: MIMXRT1050_EVK */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 +#define GPIO_MUX_PORT 5 + +typedef enum { + WAKEUP = ((5 << GPIO_PORT_SHIFT) | 0), + PMIC_ON_REQ = ((5 << GPIO_PORT_SHIFT) | 1), + PMIC_STBY_REQ = ((5 << GPIO_PORT_SHIFT) | 2), + + GPIO_EMC_00 = ((4 << GPIO_PORT_SHIFT) | 0), + GPIO_EMC_01 = ((4 << GPIO_PORT_SHIFT) | 1), + GPIO_EMC_02 = ((4 << GPIO_PORT_SHIFT) | 2), + GPIO_EMC_03 = ((4 << GPIO_PORT_SHIFT) | 3), + GPIO_EMC_04 = ((4 << GPIO_PORT_SHIFT) | 4), + GPIO_EMC_05 = ((4 << GPIO_PORT_SHIFT) | 5), + GPIO_EMC_06 = ((4 << GPIO_PORT_SHIFT) | 6), + GPIO_EMC_07 = ((4 << GPIO_PORT_SHIFT) | 7), + GPIO_EMC_08 = ((4 << GPIO_PORT_SHIFT) | 8), + GPIO_EMC_09 = ((4 << GPIO_PORT_SHIFT) | 9), + GPIO_EMC_10 = ((4 << GPIO_PORT_SHIFT) | 10), + GPIO_EMC_11 = ((4 << GPIO_PORT_SHIFT) | 11), + GPIO_EMC_12 = ((4 << GPIO_PORT_SHIFT) | 12), + GPIO_EMC_13 = ((4 << GPIO_PORT_SHIFT) | 13), + GPIO_EMC_14 = ((4 << GPIO_PORT_SHIFT) | 14), + GPIO_EMC_15 = ((4 << GPIO_PORT_SHIFT) | 15), + GPIO_EMC_16 = ((4 << GPIO_PORT_SHIFT) | 16), + GPIO_EMC_17 = ((4 << GPIO_PORT_SHIFT) | 17), + GPIO_EMC_18 = ((4 << GPIO_PORT_SHIFT) | 18), + GPIO_EMC_19 = ((4 << GPIO_PORT_SHIFT) | 19), + GPIO_EMC_20 = ((4 << GPIO_PORT_SHIFT) | 20), + GPIO_EMC_21 = ((4 << GPIO_PORT_SHIFT) | 21), + GPIO_EMC_22 = ((4 << GPIO_PORT_SHIFT) | 22), + GPIO_EMC_23 = ((4 << GPIO_PORT_SHIFT) | 23), + GPIO_EMC_24 = ((4 << GPIO_PORT_SHIFT) | 24), + GPIO_EMC_25 = ((4 << GPIO_PORT_SHIFT) | 25), + GPIO_EMC_26 = ((4 << GPIO_PORT_SHIFT) | 26), + GPIO_EMC_27 = ((4 << GPIO_PORT_SHIFT) | 27), + GPIO_EMC_28 = ((4 << GPIO_PORT_SHIFT) | 28), + GPIO_EMC_29 = ((4 << GPIO_PORT_SHIFT) | 29), + GPIO_EMC_30 = ((4 << GPIO_PORT_SHIFT) | 30), + GPIO_EMC_31 = ((4 << GPIO_PORT_SHIFT) | 31), + GPIO_EMC_32 = ((3 << GPIO_PORT_SHIFT) | 18), + GPIO_EMC_33 = ((3 << GPIO_PORT_SHIFT) | 19), + GPIO_EMC_34 = ((3 << GPIO_PORT_SHIFT) | 20), + GPIO_EMC_35 = ((3 << GPIO_PORT_SHIFT) | 21), + GPIO_EMC_36 = ((3 << GPIO_PORT_SHIFT) | 22), + GPIO_EMC_37 = ((3 << GPIO_PORT_SHIFT) | 23), + GPIO_EMC_38 = ((3 << GPIO_PORT_SHIFT) | 24), + GPIO_EMC_39 = ((3 << GPIO_PORT_SHIFT) | 25), + GPIO_EMC_40 = ((3 << GPIO_PORT_SHIFT) | 26), + GPIO_EMC_41 = ((3 << GPIO_PORT_SHIFT) | 27), + + GPIO_AD_B0_00 = ((1 << GPIO_PORT_SHIFT) | 0), + GPIO_AD_B0_01 = ((1 << GPIO_PORT_SHIFT) | 1), + GPIO_AD_B0_02 = ((1 << GPIO_PORT_SHIFT) | 2), + GPIO_AD_B0_03 = ((1 << GPIO_PORT_SHIFT) | 3), + GPIO_AD_B0_04 = ((1 << GPIO_PORT_SHIFT) | 4), + GPIO_AD_B0_05 = ((1 << GPIO_PORT_SHIFT) | 5), + GPIO_AD_B0_06 = ((1 << GPIO_PORT_SHIFT) | 6), + GPIO_AD_B0_07 = ((1 << GPIO_PORT_SHIFT) | 7), + GPIO_AD_B0_08 = ((1 << GPIO_PORT_SHIFT) | 8), + GPIO_AD_B0_09 = ((1 << GPIO_PORT_SHIFT) | 9), + GPIO_AD_B0_10 = ((1 << GPIO_PORT_SHIFT) | 10), + GPIO_AD_B0_11 = ((1 << GPIO_PORT_SHIFT) | 11), + GPIO_AD_B0_12 = ((1 << GPIO_PORT_SHIFT) | 12), + GPIO_AD_B0_13 = ((1 << GPIO_PORT_SHIFT) | 13), + GPIO_AD_B0_14 = ((1 << GPIO_PORT_SHIFT) | 14), + GPIO_AD_B0_15 = ((1 << GPIO_PORT_SHIFT) | 15), + + GPIO_AD_B1_00 = ((1 << GPIO_PORT_SHIFT) | 16), + GPIO_AD_B1_01 = ((1 << GPIO_PORT_SHIFT) | 17), + GPIO_AD_B1_02 = ((1 << GPIO_PORT_SHIFT) | 18), + GPIO_AD_B1_03 = ((1 << GPIO_PORT_SHIFT) | 19), + GPIO_AD_B1_04 = ((1 << GPIO_PORT_SHIFT) | 20), + GPIO_AD_B1_05 = ((1 << GPIO_PORT_SHIFT) | 21), + GPIO_AD_B1_06 = ((1 << GPIO_PORT_SHIFT) | 22), + GPIO_AD_B1_07 = ((1 << GPIO_PORT_SHIFT) | 23), + GPIO_AD_B1_08 = ((1 << GPIO_PORT_SHIFT) | 24), + GPIO_AD_B1_09 = ((1 << GPIO_PORT_SHIFT) | 25), + GPIO_AD_B1_10 = ((1 << GPIO_PORT_SHIFT) | 26), + GPIO_AD_B1_11 = ((1 << GPIO_PORT_SHIFT) | 27), + GPIO_AD_B1_12 = ((1 << GPIO_PORT_SHIFT) | 28), + GPIO_AD_B1_13 = ((1 << GPIO_PORT_SHIFT) | 29), + GPIO_AD_B1_14 = ((1 << GPIO_PORT_SHIFT) | 30), + GPIO_AD_B1_15 = ((1 << GPIO_PORT_SHIFT) | 31), + + GPIO_B0_00 = ((2 << GPIO_PORT_SHIFT) | 0), + GPIO_B0_01 = ((2 << GPIO_PORT_SHIFT) | 1), + GPIO_B0_02 = ((2 << GPIO_PORT_SHIFT) | 2), + GPIO_B0_03 = ((2 << GPIO_PORT_SHIFT) | 3), + GPIO_B0_04 = ((2 << GPIO_PORT_SHIFT) | 4), + GPIO_B0_05 = ((2 << GPIO_PORT_SHIFT) | 5), + GPIO_B0_06 = ((2 << GPIO_PORT_SHIFT) | 6), + GPIO_B0_07 = ((2 << GPIO_PORT_SHIFT) | 7), + GPIO_B0_08 = ((2 << GPIO_PORT_SHIFT) | 8), + GPIO_B0_09 = ((2 << GPIO_PORT_SHIFT) | 9), + GPIO_B0_10 = ((2 << GPIO_PORT_SHIFT) | 10), + GPIO_B0_11 = ((2 << GPIO_PORT_SHIFT) | 11), + GPIO_B0_12 = ((2 << GPIO_PORT_SHIFT) | 12), + GPIO_B0_13 = ((2 << GPIO_PORT_SHIFT) | 13), + GPIO_B0_14 = ((2 << GPIO_PORT_SHIFT) | 14), + GPIO_B0_15 = ((2 << GPIO_PORT_SHIFT) | 15), + + GPIO_B1_00 = ((2 << GPIO_PORT_SHIFT) | 16), + GPIO_B1_01 = ((2 << GPIO_PORT_SHIFT) | 17), + GPIO_B1_02 = ((2 << GPIO_PORT_SHIFT) | 18), + GPIO_B1_03 = ((2 << GPIO_PORT_SHIFT) | 19), + GPIO_B1_04 = ((2 << GPIO_PORT_SHIFT) | 20), + GPIO_B1_05 = ((2 << GPIO_PORT_SHIFT) | 21), + GPIO_B1_06 = ((2 << GPIO_PORT_SHIFT) | 22), + GPIO_B1_07 = ((2 << GPIO_PORT_SHIFT) | 23), + GPIO_B1_08 = ((2 << GPIO_PORT_SHIFT) | 24), + GPIO_B1_09 = ((2 << GPIO_PORT_SHIFT) | 25), + GPIO_B1_10 = ((2 << GPIO_PORT_SHIFT) | 26), + GPIO_B1_11 = ((2 << GPIO_PORT_SHIFT) | 27), + GPIO_B1_12 = ((2 << GPIO_PORT_SHIFT) | 28), + GPIO_B1_13 = ((2 << GPIO_PORT_SHIFT) | 29), + GPIO_B1_14 = ((2 << GPIO_PORT_SHIFT) | 30), + GPIO_B1_15 = ((2 << GPIO_PORT_SHIFT) | 31), + + GPIO_SD_B0_00 = ((3 << GPIO_PORT_SHIFT) | 12), + GPIO_SD_B0_01 = ((3 << GPIO_PORT_SHIFT) | 13), + GPIO_SD_B0_02 = ((3 << GPIO_PORT_SHIFT) | 14), + GPIO_SD_B0_03 = ((3 << GPIO_PORT_SHIFT) | 15), + GPIO_SD_B0_04 = ((3 << GPIO_PORT_SHIFT) | 16), + GPIO_SD_B0_05 = ((3 << GPIO_PORT_SHIFT) | 17), + + GPIO_SD_B1_00 = ((3 << GPIO_PORT_SHIFT) | 0), + GPIO_SD_B1_01 = ((3 << GPIO_PORT_SHIFT) | 1), + GPIO_SD_B1_02 = ((3 << GPIO_PORT_SHIFT) | 2), + GPIO_SD_B1_03 = ((3 << GPIO_PORT_SHIFT) | 3), + GPIO_SD_B1_04 = ((3 << GPIO_PORT_SHIFT) | 4), + GPIO_SD_B1_05 = ((3 << GPIO_PORT_SHIFT) | 5), + GPIO_SD_B1_06 = ((3 << GPIO_PORT_SHIFT) | 6), + GPIO_SD_B1_07 = ((3 << GPIO_PORT_SHIFT) | 7), + GPIO_SD_B1_08 = ((3 << GPIO_PORT_SHIFT) | 8), + GPIO_SD_B1_09 = ((3 << GPIO_PORT_SHIFT) | 9), + GPIO_SD_B1_10 = ((3 << GPIO_PORT_SHIFT) | 10), + GPIO_SD_B1_11 = ((3 << GPIO_PORT_SHIFT) | 11), + + // Teensy 4.0 pin names ------------------------------------- + // Digital + D0 = GPIO_AD_B0_03, + D1 = GPIO_AD_B0_02, + D2 = GPIO_EMC_04, + D3 = GPIO_EMC_05, + D4 = GPIO_EMC_06, + D5 = GPIO_EMC_08, + D6 = GPIO_B0_10, + D7 = GPIO_B1_01, + D8 = GPIO_B1_00, + D9 = GPIO_B0_11, + D10 = GPIO_B0_00, + D11 = GPIO_B0_02, + D12 = GPIO_B0_01, + D13 = GPIO_B0_03, + D14 = GPIO_AD_B1_02, + D15 = GPIO_AD_B1_03, + D16 = GPIO_AD_B1_07, + D17 = GPIO_AD_B1_06, + D18 = GPIO_AD_B1_01, + D19 = GPIO_AD_B1_00, + D20 = GPIO_AD_B1_10, + D21 = GPIO_AD_B1_11, + D22 = GPIO_AD_B1_08, + D23 = GPIO_AD_B1_09, + D24 = GPIO_AD_B0_12, + D25 = GPIO_AD_B0_13, + D26 = GPIO_AD_B1_14, + D27 = GPIO_AD_B1_15, + D28 = GPIO_EMC_32, + D29 = GPIO_EMC_31, + D30 = GPIO_EMC_37, + D31 = GPIO_EMC_36, + D32 = GPIO_B0_12, + D33 = GPIO_EMC_07, + D34 = GPIO_SD_B0_03, + D35 = GPIO_SD_B0_02, + D36 = GPIO_SD_B0_01, + D37 = GPIO_SD_B0_00, + D38 = GPIO_SD_B0_05, + D39 = GPIO_SD_B0_04, + + // Analog + A0 = GPIO_AD_B1_02, + A1 = GPIO_AD_B1_03, + A2 = GPIO_AD_B1_07, + A3 = GPIO_AD_B1_06, + A4 = GPIO_AD_B1_01, + A5 = GPIO_AD_B1_00, + A6 = GPIO_AD_B1_10, + A7 = GPIO_AD_B1_11, + A8 = GPIO_AD_B1_08, + A9 = GPIO_AD_B1_09, + A10 = GPIO_AD_B0_12, + A11 = GPIO_AD_B0_13, + A12 = GPIO_AD_B1_14, + A13 = GPIO_AD_B1_15, + + // Standard aliases ------------------------------------- + + // Even though the UART console is not used by default, we still provide mappings on the standard Arduino pins + CONSOLE_TX = D1, + CONSOLE_RX = D0, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 D13 +#define USER_LED LED1 + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp_47K = 2, + PullUp_100K = 3, + PullUp_22K = 4, + PullDefault = PullUp_47K, + PullUp = PullUp_47K +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/bootdata.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/bootdata.c new file mode 100644 index 0000000..237a715 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/bootdata.c @@ -0,0 +1,242 @@ +// This file is adapted from bootdata.c in the Teensy4 Arduino core. +// https://github.com/PaulStoffregen/cores/blob/a2368ad57e9470608a234d942c55a2278c6cd72b/teensy4/bootdata.c +// The only changes made were: +// - Section names had to be modified to match what is expected by Mbed's linker script. +// - #define names had to be modified to match Mbed +// - _flashimagelen replaced with __USED_FLASH_END +// - ResetHandler replaced with Reset_Handler + +/* Teensyduino Core Library + * http://www.pjrc.com/teensy/ + * Copyright (c) 2017 PJRC.COM, LLC. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * 1. The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * 2. If the Software is incorporated into a build system that allows + * selection among a list of target devices, then similar target + * devices manufactured by PJRC.COM must be included in the list of + * target devices and selectable in the same manner. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +extern void Reset_Handler(void); +extern unsigned long _estack; +extern unsigned long __USED_FLASH_END; + + + +__attribute__ ((section(".boot_hdr.boot_data"), used)) +const uint32_t BootData[3] = { + 0x60000000, + (uint32_t)&__USED_FLASH_END, + 0 +}; + + +__attribute__ ((section(".csf"), used)) +const uint32_t hab_csf[768]; // placeholder for HAB signature + + +__attribute__ ((section(".boot_hdr.ivt"), used)) +const uint32_t ImageVectorTable[8] = { + 0x432000D1, // header + (uint32_t)&Reset_Handler,// program entry + 0, // reserved + 0, // dcd + (uint32_t)BootData, // abs address of boot data + (uint32_t)ImageVectorTable, // self + (uint32_t)hab_csf, // command sequence file + 0 // reserved +}; + +__attribute__ ((section(".boot_hdr.conf"), used)) +uint32_t FlexSPI_NOR_Config[128] = { + // 448 byte common FlexSPI configuration block, 8.6.3.1 page 223 (RT1060 rev 0) + // MCU_Flashloader_Reference_Manual.pdf, 8.2.1, Table 8-2, page 72-75 + 0x42464346, // Tag 0x00 + 0x56010000, // Version + 0, // reserved + 0x00030301, // columnAdressWidth,dataSetupTime,dataHoldTime,readSampleClkSrc + + 0x00000000, // waitTimeCfgCommands,-,deviceModeCfgEnable + 0, // deviceModeSeq + 0, // deviceModeArg + 0x00000000, // -,-,-,configCmdEnable + + 0, // configCmdSeqs 0x20 + 0, + 0, + 0, + + 0, // cfgCmdArgs 0x30 + 0, + 0, + 0, + + 0x00000000, // controllerMiscOption 0x40 + 0x00080401, // lutCustomSeqEnable,serialClkFreq,sflashPadType,deviceType + 0, // reserved + 0, // reserved + +#if defined(TARGET_TEENSY_40) + 0x00200000, // sflashA1Size 0x50 +#elif defined(TARGET_TEENSY_41) + 0x00800000, // sflashA1Size 0x50 +#else +#error "Unknow flash chip size"; +#endif + 0, // sflashA2Size + 0, // sflashB1Size + 0, // sflashB2Size + + 0, // csPadSettingOverride 0x60 + 0, // sclkPadSettingOverride + 0, // dataPadSettingOverride + 0, // dqsPadSettingOverride + + 0, // timeoutInMs 0x70 + 0, // commandInterval + 0, // dataValidTime + 0x00000000, // busyBitPolarity,busyOffset + + 0x0A1804EB, // lookupTable[0] 0x80 + 0x26043206, // lookupTable[1] + 0, // lookupTable[2] + 0, // lookupTable[3] + + 0x24040405, // lookupTable[4] 0x90 + 0, // lookupTable[5] + 0, // lookupTable[6] + 0, // lookupTable[7] + + 0, // lookupTable[8] 0xA0 + 0, // lookupTable[9] + 0, // lookupTable[10] + 0, // lookupTable[11] + + 0x00000406, // lookupTable[12] 0xB0 + 0, // lookupTable[13] + 0, // lookupTable[14] + 0, // lookupTable[15] + + 0, // lookupTable[16] 0xC0 + 0, // lookupTable[17] + 0, // lookupTable[18] + 0, // lookupTable[19] + + 0x08180420, // lookupTable[20] 0xD0 + 0, // lookupTable[21] + 0, // lookupTable[22] + 0, // lookupTable[23] + + 0, // lookupTable[24] 0xE0 + 0, // lookupTable[25] + 0, // lookupTable[26] + 0, // lookupTable[27] + + 0, // lookupTable[28] 0xF0 + 0, // lookupTable[29] + 0, // lookupTable[30] + 0, // lookupTable[31] + + 0x081804D8, // lookupTable[32] 0x100 + 0, // lookupTable[33] + 0, // lookupTable[34] + 0, // lookupTable[35] + + 0x08180402, // lookupTable[36] 0x110 + 0x00002004, // lookupTable[37] + 0, // lookupTable[38] + 0, // lookupTable[39] + + 0, // lookupTable[40] 0x120 + 0, // lookupTable[41] + 0, // lookupTable[42] + 0, // lookupTable[43] + + 0x00000460, // lookupTable[44] 0x130 + 0, // lookupTable[45] + 0, // lookupTable[46] + 0, // lookupTable[47] + + 0, // lookupTable[48] 0x140 + 0, // lookupTable[49] + 0, // lookupTable[50] + 0, // lookupTable[51] + + 0, // lookupTable[52] 0x150 + 0, // lookupTable[53] + 0, // lookupTable[54] + 0, // lookupTable[55] + + 0, // lookupTable[56] 0x160 + 0, // lookupTable[57] + 0, // lookupTable[58] + 0, // lookupTable[59] + + 0, // lookupTable[60] 0x170 + 0, // lookupTable[61] + 0, // lookupTable[62] + 0, // lookupTable[63] + + 0, // LUT 0: Read 0x180 + 0, // LUT 1: ReadStatus + 0, // LUT 3: WriteEnable + 0, // LUT 5: EraseSector + + 0, // LUT 9: PageProgram 0x190 + 0, // LUT 11: ChipErase + 0, // LUT 15: Dummy + 0, // LUT unused? + + 0, // LUT unused? 0x1A0 + 0, // LUT unused? + 0, // LUT unused? + 0, // LUT unused? + + 0, // reserved 0x1B0 + 0, // reserved + 0, // reserved + 0, // reserved + + // 64 byte Serial NOR configuration block, 8.6.3.2, page 346 + + 256, // pageSize 0x1C0 + 4096, // sectorSize + 1, // ipCmdSerialClkFreq + 0, // reserved + + 0x00010000, // block size 0x1D0 + 0, // reserved + 0, // reserved + 0, // reserved + + 0, // reserved 0x1E0 + 0, // reserved + 0, // reserved + 0, // reserved + + 0, // reserved 0x1F0 + 0, // reserved + 0, // reserved + 0 // reserved +}; \ No newline at end of file diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/device.h new file mode 100644 index 0000000..4dd30f8 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/device.h @@ -0,0 +1,30 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +/* CMSIS defines this, we use it as linker symbol, undefined it and let a linker symbol + to be as vector table */ +#undef __VECTOR_TABLE + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/analogin_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/analogin_api.c new file mode 100644 index 0000000..a80272c --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/analogin_api.c @@ -0,0 +1,89 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "cmsis.h" +#include "pinmap.h" +#include "gpio_api.h" +#include "PeripheralNames.h" +#include "fsl_adc.h" +#include "PeripheralPins.h" + +/* Array of ADC peripheral base address. */ +static ADC_Type *const adc_addrs[] = ADC_BASE_PTRS; + +void analogin_init(analogin_t *obj, PinName pin) +{ + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; + adc_config_t adc_config; + gpio_t gpio; + + ADC_GetDefaultConfig(&adc_config); + ADC_Init(adc_addrs[instance], &adc_config); +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + ADC_EnableHardwareTrigger(adc_addrs[instance], false); +#endif + ADC_DoAutoCalibration(adc_addrs[instance]); + + /* Need to ensure the pin is in input mode */ + gpio_init(&gpio, pin); + gpio_dir(&gpio, PIN_INPUT); +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; + adc_channel_config_t adc_channel_config; + + adc_channel_config.channelNumber = obj->adc & 0xF; + adc_channel_config.enableInterruptOnConversionCompleted = false; + + /* + When in software trigger mode, each conversion would be launched once calling the "ADC_ChannelConfigure()" + function, which works like writing a conversion command and executing it. For another channel's conversion, + just to change the "channelNumber" field in channel configuration structure, and call the function + "ADC_ChannelConfigure()"" again. + Also, the "enableInterruptOnConversionCompleted" inside the channel configuration structure is a parameter + for the conversion command. It takes affect just for the current conversion. If the interrupt is still required + for the following conversion, it is necessary to assert the "enableInterruptOnConversionCompleted" every + time for each command. + */ + ADC_SetChannelConfig(adc_addrs[instance], 0, &adc_channel_config); + while (0U == ADC_GetChannelStatusFlags(adc_addrs[instance], 0)) + { + } + return ADC_GetChannelConversionValue(adc_addrs[instance], 0); +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = analogin_read_u16(obj); + return (float)value * (1.0f / (float)0xFFFF); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld index 496d04b..0684eb4 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld @@ -59,11 +59,18 @@ m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 m_text (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 #endif - m_text2 (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 - m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + +#if MIMXRT105X_BOARD_HAS_EXTERNAL_RAM + /* Use the external RAM as main memory */ + m_data (RW) : ORIGIN = 0x80000000, LENGTH = MIMXRT105X_EXTERNAL_RAM_SIZE +#else + /* Use OCRAM as main memory. */ + m_data (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +#endif + + m_itcm (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 - m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 - m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 + m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 } /* Define output sections */ @@ -80,7 +87,7 @@ ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); - .ivt : AT(ivt_begin) + .ivt : { . = ALIGN(8); KEEP(* (.boot_hdr.ivt)) /* ivt section */ @@ -196,12 +203,12 @@ . += M_VECTOR_RAM_SIZE; . = ALIGN(8); __interrupts_ram_end__ = .; /* Define a global symbol at data end */ - } > m_data2 + } > m_dtcm __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; - .data : AT(__DATA_ROM) + .data : { . = ALIGN(8); __DATA_RAM = .; @@ -212,29 +219,29 @@ KEEP(*(.jcr*)) . = ALIGN(8); __data_end__ = .; /* define a global symbol at data end */ - } > m_data + } > m_data AT> m_text __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ - .ram_function : AT(__ram_function_flash_start) + .ram_function : { . = ALIGN(32); __ram_function_start__ = .; *(CodeQuickAccess) . = ALIGN(128); __ram_function_end__ = .; - } > m_text2 + } > m_itcm AT> m_text __ram_function_size = SIZEOF(.ram_function); __NDATA_ROM = __ram_function_flash_start + SIZEOF(.ram_function); - .ncache.init : AT(__NDATA_ROM) + .ncache.init : { __noncachedata_start__ = .; /* create a global symbol at ncache data start */ *(NonCacheable.init) . = ALIGN(8); __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_ncache + } > m_ncache AT> m_text . = __noncachedata_init_end__; .ncache : { @@ -243,9 +250,20 @@ __noncachedata_end__ = .; /* define a global symbol at ncache data end */ } > m_ncache - __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + __TEXT_CSF_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + + .csf : + { + FILL(0xFF) + . = ALIGN(1024); + KEEP(*(.csf)) + __text_csf_end = .; + } > m_text + + __USED_FLASH_END = __TEXT_CSF_ROM + SIZEOF(.csf); + text_end = ORIGIN(m_text) + LENGTH(m_text); - ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + ASSERT(__USED_FLASH_END <= text_end, "Code and data initializers exceed flash size!") /* Uninitialized data section */ .bss : @@ -287,6 +305,6 @@ .ARM.attributes 0 : { *(.ARM.attributes) } - ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") + ASSERT(__StackLimit >= __HeapLimit, "Stack, heap, and globals exceed main RAM size!") } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/cmsis_nvic.h index f2a763a..36dabbd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/cmsis_nvic.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/cmsis_nvic.h @@ -42,6 +42,10 @@ #define NVIC_NUM_VECTORS (16 + 160) // CORE + MCU Peripherals #define NVIC_RAM_VECTOR_ADDRESS (__VECTOR_RAM) // Vectors positioned at start of RAM -#define MBED_RAM_SIZE 0x01E00000 // from linker script +#ifdef MIMXRT105X_BOARD_HAS_EXTERNAL_RAM +#define MBED_RAM_SIZE MIMXRT105X_EXTERNAL_RAM_SIZE +#else +#define MBED_RAM_SIZE 0x00040000 +#endif #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c deleted file mode 100644 index 09a59ed..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_flexspi_nor_boot.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.xip_device" -#endif - -#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) - __attribute__((section(".boot_hdr.ivt"), used)) -#elif defined(__ICCARM__) -#pragma location=".boot_hdr.ivt" -#endif -/************************************* - * IVT Data - *************************************/ -const ivt image_vector_table = { - IVT_HEADER, /* IVT Header */ - IMAGE_ENTRY_ADDRESS, /* Image Entry Function */ - IVT_RSVD, /* Reserved = 0 */ - (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ - (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ - (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ - IVT_RSVD /* Reserved = 0 */ -}; - -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) - __attribute__((section(".boot_hdr.boot_data"))) -#elif defined(__ICCARM__) -#pragma location=".boot_hdr.boot_data" -#endif -/************************************* - * Boot Data - *************************************/ -const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ - PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ -}; -#endif - - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h deleted file mode 100644 index bd0fe64..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi_nor_boot.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __FLEXSPI_NOR_BOOT_H__ -#define __FLEXSPI_NOR_BOOT_H__ - -#include -#include "device.h" -#undef __VECTOR_TABLE - -/*! @name Driver version */ -/*@{*/ -/*! @brief XIP_DEVICE driver version 2.0.0. */ -#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/************************************* - * IVT Data - *************************************/ -typedef struct _ivt_ { - /** @ref hdr with tag #HAB_TAG_IVT, length and HAB version fields - * (see @ref data) - */ - uint32_t hdr; - /** Absolute address of the first instruction to execute from the - * image - */ - uint32_t entry; - /** Reserved in this version of HAB: should be NULL. */ - uint32_t reserved1; - /** Absolute address of the image DCD: may be NULL. */ - uint32_t dcd; - /** Absolute address of the Boot Data: may be NULL, but not interpreted - * any further by HAB - */ - uint32_t boot_data; - /** Absolute address of the IVT.*/ - uint32_t self; - /** Absolute address of the image CSF.*/ - uint32_t csf; - /** Reserved in this version of HAB: should be zero. */ - uint32_t reserved2; -} ivt; - -#define IVT_MAJOR_VERSION 0x4 -#define IVT_MAJOR_VERSION_SHIFT 0x4 -#define IVT_MAJOR_VERSION_MASK 0xF -#define IVT_MINOR_VERSION 0x1 -#define IVT_MINOR_VERSION_SHIFT 0x0 -#define IVT_MINOR_VERSION_MASK 0xF - -#define IVT_VERSION(major, minor) \ - ((((major) & IVT_MAJOR_VERSION_MASK) << IVT_MAJOR_VERSION_SHIFT) | \ - (((minor) & IVT_MINOR_VERSION_MASK) << IVT_MINOR_VERSION_SHIFT)) - -/* IVT header */ -#define IVT_TAG_HEADER 0xD1 /**< Image Vector Table */ -#define IVT_SIZE 0x2000 -#define IVT_PAR IVT_VERSION(IVT_MAJOR_VERSION, IVT_MINOR_VERSION) -#define IVT_HEADER (IVT_TAG_HEADER | (IVT_SIZE << 8) | (IVT_PAR << 24)) - -/* Set resume entry */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t __Vectors[]; - extern uint32_t Image$$RW_m_config_text$$Base[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) -#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base) -#elif defined(__MCUXPRESSO) - extern uint32_t __Vectors[]; - extern uint32_t __boot_hdr_start__[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__Vectors) -#define FLASH_BASE ((uint32_t)__boot_hdr_start__) -#elif defined(__ICCARM__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t m_boot_hdr_conf_start[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start) -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __FLASH_BASE[]; -#define IMAGE_ENTRY_ADDRESS ((uint32_t)__VECTOR_TABLE) -#define FLASH_BASE ((uint32_t)__FLASH_BASE) -#endif - -#define DCD_ADDRESS dcd_data -#define BOOT_DATA_ADDRESS &boot_data -#define CSF_ADDRESS 0 -#define IVT_RSVD (uint32_t)(0x00000000) - -/************************************* - * Boot Data - *************************************/ -typedef struct _boot_data_ { - uint32_t start; /* boot start location */ - uint32_t size; /* size */ - uint32_t plugin; /* plugin flag - 1 if downloaded application is plugin */ - uint32_t placeholder; /* placehoder to make even 0x10 size */ -}BOOT_DATA_T; - -#define FLASH_SIZE BOARD_FLASH_SIZE -#define PLUGIN_FLAG (uint32_t)0 - -/* External Variables */ -const BOOT_DATA_T boot_data; -extern const uint8_t dcd_data[]; - -#endif /* __FLEXSPI_NOR_BOOT_H__ */ - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.c new file mode 100644 index 0000000..d9a1fb3 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.c @@ -0,0 +1,471 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v5.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: IMXRT1050-EVKB + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "fsl_clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { + .loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); +/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left + * unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif +/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left + * unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left + * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as + * well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); + /* Disable pfd offset. */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK; +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left + * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as + * well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = + (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Tx clock source. */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_GetCpuClkFreq(); +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.h new file mode 100644 index 0000000..f213ac7 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.h @@ -0,0 +1,119 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.c new file mode 100644 index 0000000..420f15d --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.c @@ -0,0 +1,534 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "lpm.h" +#include "fsl_gpc.h" +#include "fsl_dcdc.h" +#include "fsl_gpt.h" +#include "fsl_clock_config.h" +#include "mbed_critical.h" +#include "cmsis.h" +#include "specific.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define LPM_GPC_IMR_NUM (sizeof(GPC->IMR) / sizeof(GPC->IMR[0])) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +uint32_t g_savedPrimask; +GPT_Type *vPortGetGptBase(void); +IRQn_Type vPortGetGptIrqn(void); + +/******************************************************************************* + * Code + ******************************************************************************/ +void EnableRegularLDO(void) +{ + /* Enable Regular LDO 2P5 and 1P1 */ + PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_LINREG_MASK; + PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_LINREG_MASK; +} + +void DisableRegularLDO(void) +{ + /* Disable Regular LDO 2P5 and 1P1 */ + PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_LINREG_MASK; + PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_LINREG_MASK; +} + +void EnableWeakLDO(void) +{ + /* Enable Weak LDO 2P5 and 1P1 */ + PMU->REG_2P5_SET = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; + PMU->REG_1P1_SET = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; + + SDK_DelayAtLeastUs(40); +} + +void DisableWeakLDO(void) +{ + /* Disable Weak LDO 2P5 and 1P1 */ + PMU->REG_2P5_CLR = PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; + PMU->REG_1P1_CLR = PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; +} + +void BandgapOn(void) +{ + /* Turn on regular bandgap and wait for stable */ + PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK; + while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0) + { + } + /* Low power band gap disable */ + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; +} + +void BandgapOff(void) +{ + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; + PMU->MISC0_SET = PMU_MISC0_REFTOP_PWD_MASK; +} + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + //assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +void CLOCK_SET_DIV(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + //assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +void ClockSelectXtalOsc(void) +{ + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); +} + +void ClockSelectRcOsc(void) +{ + /* Switch clock source to internal RC. */ + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; +} + +void LPM_SetRunModeConfig(void) +{ + CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); +} + +void LPM_SetWaitModeConfig(void) +{ + uint32_t clpcr; + + /* + * ERR007265: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending + * by setting IOMUXC_GPR_GPR1_GINT. + * 2) Software should then unmask IRQ #41 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #41 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); + clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); + CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeWait) | CCM_CLPCR_MASK_SCU_IDLE_MASK | CCM_CLPCR_MASK_L2CC_IDLE_MASK | + CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK | + CCM_CLPCR_BYPASS_LPM_HS1_MASK; + GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); +} + +void LPM_SetStopModeConfig(void) +{ + uint32_t clpcr; + + /* + * ERR007265: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending + * by setting IOMUXC_GPR_GPR1_GINT. + * 2) Software should then unmask IRQ #41 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #41 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); + clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); + CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeStop) | CCM_CLPCR_MASK_L2CC_IDLE_MASK | CCM_CLPCR_MASK_SCU_IDLE_MASK | + CCM_CLPCR_VSTBY_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_SBYOS_MASK | + CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK; + GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); +} + +void LPM_OverDriveRun(void) +{ + /* CCM Mode */ + DCDC_BootIntoCCM(DCDC); + /* Connect internal the load resistor */ + DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; + /* Adjust SOC voltage to 1.275V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + + /* Disable FET ODRIVE */ + PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; + + BandgapOn(); + EnableRegularLDO(); + DisableWeakLDO(); + + ClockSetToOverDriveRun(); + SetRestoreClockGate(); +} + +void LPM_FullSpeedRun(void) +{ + /* CCM Mode */ + DCDC_BootIntoCCM(DCDC); + /* Connect internal the load resistor */ + DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; + /* Adjust SOC voltage to 1.275V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + + /* Disable FET ODRIVE */ + PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; + + BandgapOn(); + EnableRegularLDO(); + DisableWeakLDO(); + + ClockSetToFullSpeedRun(); + + /* Adjust SOC voltage to 1.15V */ + DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); +} + +void LPM_LowSpeedRun(void) +{ + /* CCM Mode */ + DCDC_BootIntoCCM(DCDC); + /* Connect internal the load resistor */ + DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; + /* Adjust SOC voltage to 1.275V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + + /* Disable FET ODRIVE */ + PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; + + BandgapOn(); + EnableRegularLDO(); + DisableWeakLDO(); + + ClockSetToLowSpeedRun(); + + /* Adjust SOC voltage to 1.15V */ + DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); +} + +void LPM_LowPowerRun(void) +{ + ClockSetToLowPowerRun(); + + /* Power down USBPHY */ + PowerDownUSBPHY(); + + /* Adjust SOC voltage to 0.95V */ + DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); + /* DCM Mode */ + DCDC_BootIntoDCM(DCDC); + /* Disconnect internal the load resistor */ + DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; + /* Power Down output range comparator */ + DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; + + /* Enable FET ODRIVE */ + PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; + + EnableWeakLDO(); + DisableRegularLDO(); + BandgapOff(); +} + +void LPM_EnterSystemIdle(void) +{ + LPM_SetWaitModeConfig(); + SetLowPowerClockGate(); + + ClockSetToSystemIdle(); + + /* Power down USBPHY */ + PowerDownUSBPHY(); + + /* DCDC to 1.15V */ + DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); + /* DCM Mode */ + DCDC_BootIntoDCM(DCDC); + /* Disconnect internal the load resistor */ + DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; + /* Power Down output range comparator */ + DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; + + /* Enable FET ODRIVE */ + PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; + + EnableRegularLDO(); + DisableWeakLDO(); + BandgapOn(); + + PeripheralEnterDozeMode(); +} + +void LPM_ExitSystemIdle(void) +{ + PeripheralExitDozeMode(); + LPM_SetRunModeConfig(); +} + +void LPM_EnterLowPowerIdle(void) +{ + LPM_SetWaitModeConfig(); + SetLowPowerClockGate(); + + ClockSetToLowPowerIdle(); + + /* Power down USBPHY */ + PowerDownUSBPHY(); + + /* Adjust SOC voltage to 0.95V */ + DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); + /* DCM Mode */ + DCDC_BootIntoDCM(DCDC); + /* Disconnect internal the load resistor */ + DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; + /* Power Down output range comparator */ + DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; + + /* Enable FET ODRIVE */ + PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; + + EnableWeakLDO(); + DisableRegularLDO(); + BandgapOff(); + + PeripheralEnterDozeMode(); +} + +void LPM_ExitLowPowerIdle(void) +{ + PeripheralExitDozeMode(); + LPM_SetRunModeConfig(); +} + +void LPM_EnterSuspend(void) +{ + uint32_t i; + uint32_t gpcIMR[LPM_GPC_IMR_NUM]; + + LPM_SetStopModeConfig(); + SetLowPowerClockGate(); + + /* Disconnect internal the load resistor */ + DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; + + /* Turn off FlexRAM0 */ + GPC->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; + /* Turn off FlexRAM1 */ + PGC->MEGA_CTRL |= PGC_MEGA_CTRL_PCR_MASK; + + /* Clean and disable data cache to make sure context is saved into RAM */ + SCB_CleanDCache(); + SCB_DisableDCache(); + + /* Adjust LP voltage to 0.925V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + /* Switch DCDC to use DCDC internal OSC */ + DCDC_SetClockSource(DCDC, kDCDC_ClockInternalOsc); + + /* Power down USBPHY */ + PowerDownUSBPHY(); + + /* Power down CPU when requested */ + PGC->CPU_CTRL = PGC_CPU_CTRL_PCR_MASK; + + /* Enable FET ODRIVE */ + PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; + /* STOP_MODE config, turn off all analog except RTC in stop mode */ + PMU->MISC0_CLR = PMU_MISC0_STOP_MODE_CONFIG_MASK; + + /* Mask all GPC interrupts before enabling the RBC counters to + * avoid the counter starting too early if an interupt is already + * pending. + */ + for (i = 0; i < LPM_GPC_IMR_NUM; i++) + { + gpcIMR[i] = GPC->IMR[i]; + GPC->IMR[i] = 0xFFFFFFFFU; + } + + /* + * ERR006223: CCM: Failure to resuem from wait/stop mode with power gating + * Configure REG_BYPASS_COUNTER to 2 + * Enable the RBC bypass counter here to hold off the interrupts. RBC counter + * needs to be no less than 2. + */ + CCM->CCR = (CCM->CCR & ~CCM_CCR_REG_BYPASS_COUNT_MASK) | CCM_CCR_REG_BYPASS_COUNT(2); + CCM->CCR |= (CCM_CCR_OSCNT(0xAF) | CCM_CCR_COSC_EN_MASK | CCM_CCR_RBC_EN_MASK); + + /* Now delay for a short while (3usec) at this point + * so a short loop should be enough. This delay is required to ensure that + * the RBC counter can start counting in case an interrupt is already pending + * or in case an interrupt arrives just as ARM is about to assert DSM_request. + */ + SDK_DelayAtLeastUs(3); + + /* Recover all the GPC interrupts. */ + for (i = 0; i < LPM_GPC_IMR_NUM; i++) + { + GPC->IMR[i] = gpcIMR[i]; + } + + PeripheralEnterStopMode(); +} + +void LPM_EnterSNVS(void) +{ + SNVS->LPCR |= SNVS_LPCR_TOP_MASK; + while (1) /* Shutdown */ + { + } +} + +bool LPM_Init(void) +{ + uint32_t i; + uint32_t tmp_reg = 0; + + CLOCK_SetMode(kCLOCK_ModeRun); + + CCM->CGPR |= CCM_CGPR_INT_MEM_CLK_LPM_MASK; + + /* Enable RC OSC. It needs at least 4ms to be stable, so self tuning need to be enabled. */ + XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; + /* Configure RC OSC */ + XTALOSC24M->OSC_CONFIG0 = XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(0x4) | XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(0x2) | + XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(0xA7) | XTALOSC24M_OSC_CONFIG0_START_MASK | + XTALOSC24M_OSC_CONFIG0_ENABLE_MASK; + XTALOSC24M->OSC_CONFIG1 = XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(0x40) | XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(0x2DC); + /* Take some delay */ + SDK_DelayAtLeastUs(4000); + /* Add some hysteresis */ + tmp_reg = XTALOSC24M->OSC_CONFIG0; + tmp_reg &= ~(XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK | XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK); + tmp_reg |= XTALOSC24M_OSC_CONFIG0_HYST_PLUS(3) | XTALOSC24M_OSC_CONFIG0_HYST_MINUS(3); + XTALOSC24M->OSC_CONFIG0 = tmp_reg; + /* Set COUNT_1M_TRG */ + tmp_reg = XTALOSC24M->OSC_CONFIG2; + tmp_reg &= ~XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK; + tmp_reg |= XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(0x2d7); + XTALOSC24M->OSC_CONFIG2 = tmp_reg; + /* Hardware requires to read OSC_CONFIG0 or OSC_CONFIG1 to make OSC_CONFIG2 write work */ + tmp_reg = XTALOSC24M->OSC_CONFIG1; + XTALOSC24M->OSC_CONFIG1 = tmp_reg; + + /* ERR007265 */ + IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK; + + /* Initialize GPC to mask all IRQs */ + for (i = 0; i < LPM_GPC_IMR_NUM; i++) + { + GPC->IMR[i] = 0xFFFFFFFFU; + } + + return true; +} + +void LPM_Deinit(void) +{ + /* ERR007265 */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_GINT_MASK; +} + +void LPM_EnableWakeupSource(uint32_t irq) +{ + GPC_EnableIRQ(GPC, irq); +} + +void LPM_DisableWakeupSource(uint32_t irq) +{ + GPC_DisableIRQ(GPC, irq); +} + +GPT_Type *vPortGetGptBase(void) +{ + return GPT2; +} + +IRQn_Type vPortGetGptIrqn(void) +{ + return GPT2_IRQn; +} + +void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode) +{ + LPM_EnableWakeupSource(vPortGetGptIrqn()); + + LPM_EnterLowPowerIdle(); +} + +void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode) +{ + LPM_ExitLowPowerIdle(); + + LPM_OverDriveRun(); + + LPM_DisableWakeupSource(vPortGetGptIrqn()); +} + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.h new file mode 100644 index 0000000..ea20400 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.h @@ -0,0 +1,145 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPM_H_ +#define _LPM_H_ + +#include "fsl_clock.h" +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ +extern void vPortGPTIsr(void); +extern uint32_t g_savedPrimask; + +#define vPortGptIsr GPT1_IRQHandler + +#define CLOCK_CCM_HANDSHAKE_WAIT() \ + \ + do \ + { \ + while (CCM->CDHIPR != 0) \ + { \ + } \ + \ + } while (0) + +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) +#define LPM_EnterCritical() \ + \ + do \ + { \ + g_savedPrimask = DisableGlobalIRQ(); \ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \ + \ + } while (0) + +#define LPM_ExitCritical() \ + \ + do \ + { \ + EnableGlobalIRQ(g_savedPrimask); \ + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; \ + \ + } while (0) + +#else +#define LPM_EnterCritical() +#define LPM_ExitCritical() +#endif + +/* Power mode definition of low power management. + * Waken up duration Off > Dsm > Idle > Wait > Run. + */ +typedef enum _lpm_power_mode +{ + LPM_PowerModeOverRun = 0, /* Over RUN mode, CPU won't stop running */ + + LPM_PowerModeFullRun, /* Full RUN mode, CPU won't stop running */ + + LPM_PowerModeLowSpeedRun, + + LPM_PowerModeLowPowerRun, + + LPM_PowerModeRunEnd = LPM_PowerModeLowPowerRun, + /* In system wait mode, cpu clock is gated. + * All peripheral can remain active, clock gating decided by CCGR setting. + * DRAM enters auto-refresh mode when there is no access. + */ + LPM_PowerModeSysIdle, /* System WAIT mode, also system low speed idle */ + + /* In low power idle mode, all PLL/PFD is off, cpu power is off. + * Analog modules running in low power mode. + * All high-speed peripherals are power gated + * Low speed peripherals can remain running at low frequency + * DRAM in self-refresh. + */ + LPM_PowerModeLPIdle, /* Low Power Idle mode */ + + /* In deep sleep mode, all PLL/PFD is off, XTAL is off, cpu power is off. + * All clocks are shut off except 32K RTC clock + * All high-speed peripherals are power gated + * Low speed peripherals are clock gated + * DRAM in self-refresh. + * If RTOS is used, systick will be disabled in DSM + */ + LPM_PowerModeSuspend, /* Deep Sleep mode, suspend. */ + + LPM_PowerModeSNVS, /* Power off mode, or shutdown mode */ + + LPM_PowerModeEnd = LPM_PowerModeSNVS +} lpm_power_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value)); +AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_DIV(clock_div_t divider, uint32_t value)); + +/* Initialize the Low Power Management */ +bool LPM_Init(void); + +/* Deinitialize the Low Power Management */ +void LPM_Deinit(void); + +/* Enable wakeup source in low power mode */ +void LPM_EnableWakeupSource(uint32_t irq); + +/* Disable wakeup source in low power mode */ +void LPM_DisableWakeupSource(uint32_t irq); + +void ClockSelectXtalOsc(void); +void ClockSelectRcOsc(void); +void LPM_EnableWakeupSource(uint32_t irq); +void LPM_DisableWakeupSource(uint32_t irq); +void LPM_PreEnterWaitMode(void); +void LPM_PostExitWaitMode(void); +void LPM_PreEnterStopMode(void); +void LPM_PostExitStopMode(void); +void LPM_OverDriveRun(void); +void LPM_FullSpeedRun(void); +void LPM_LowSpeedRun(void); +void LPM_LowPowerRun(void); +void LPM_EnterSystemIdle(void); +void LPM_ExitSystemIdle(void); +void LPM_EnterLowPowerIdle(void); +void LPM_ExitLowPowerIdle(void); +void LPM_EnterSuspend(void); +void LPM_EnterSNVS(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _LPM_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mbed_overrides.c new file mode 100644 index 0000000..fbe9eb1 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mbed_overrides.c @@ -0,0 +1,349 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pinmap.h" +#include "fsl_clock_config.h" +#include "fsl_clock.h" +#include "fsl_xbara.h" +#include "fsl_iomuxc.h" +#include "fsl_gpio.h" +#include "lpm.h" +#include "usb_phy.h" +#include "usb_device_config.h" + +#define LPSPI_CLOCK_SOURCE_DIVIDER (7U) +#define LPI2C_CLOCK_SOURCE_DIVIDER (5U) + +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) + +uint8_t mbed_otp_mac_address(char *mac); +void mbed_default_mac_address(char *mac); + +/* MPU configuration. */ +void BOARD_ConfigMPU(void) +{ + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_DisableICache(); + } + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_DisableDCache(); + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. + * Use MACROS defined in mpu_armv7.h: ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write back no write allocate + * 1 0 0 0 Normal not shareable outer and inner noncache + * 1 1 0 0 Normal shareable outer and inner noncache + * 1 0 1 1 Normal not shareable outer and inner write back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in mpu_armv7.h. + */ + + /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + +/* Region 2 setting */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Setting Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); +#endif + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +/* The define sets the cacheable memory to shareable, + * this suggestion is referred from chapter 2.2.1 Memory regions, + * types and attributes in Cortex-M7 Devices, Generic User Guide */ +#if defined(SDRAM_IS_SHAREABLE) + /* Region 7 setting: Memory with Normal type, shareable, outer/inner write back, write/read allocate */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); +#else + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back, write/read allocate */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); +#endif + + /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be + * accessed by cache can be put here */ + /* Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + +void BOARD_Init_PMIC_STBY_REQ(void) { + CLOCK_EnableClock(kCLOCK_IomuxcSnvs); /* iomuxc_snvs clock (iomuxc_snvs_clk_enable): 0x03U */ + + /* GPIO configuration of PERI_PWREN on PMIC_STBY_REQ (pin L7) */ + gpio_pin_config_t PERI_PWREN_config = { + .direction = kGPIO_DigitalOutput, + .outputLogic = 0U, + .interruptMode = kGPIO_NoIntmode + }; + /* Initialize GPIO functionality on PMIC_STBY_REQ (pin L7) */ + GPIO_PinInit(GPIO5, 2U, &PERI_PWREN_config); + + IOMUXC_SetPinMux( + IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ is configured as GPIO5_IO02 */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinConfig( + IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02, /* PMIC_STBY_REQ PAD functional properties : */ + 0x10B0U); /* Slew Rate Field: Slow Slew Rate + Drive Strength Field: R0/6 + Speed Field: medium(100MHz) + Open Drain Enable Field: Open Drain Disabled + Pull / Keep Enable Field: Pull/Keeper Enabled + Pull / Keep Select Field: Keeper + Pull Up / Down Config. Field: 100K Ohm Pull Down + Hyst. Enable Field: Hysteresis Disabled */ +} + +// called before main +void mbed_sdk_init() +{ + BOARD_ConfigMPU(); + BOARD_BootClockRUN(); + +#if TARGET_EVK + /* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is + * connected to LCD power switch circuit. So it needs to be configured as a low-level output GPIO to reduce the + * current. */ + BOARD_Init_PMIC_STBY_REQ(); +#endif + + LPM_Init(); +} + +void spi_setup_clock() +{ + /*Set clock source for LPSPI*/ + CLOCK_SetMux(kCLOCK_LpspiMux, 1U); + CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLOCK_SOURCE_DIVIDER); +} + +uint32_t spi_get_clock(void) +{ + return (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (LPSPI_CLOCK_SOURCE_DIVIDER + 1U)); +} + +void us_ticker_setup_clock() +{ + /* Set PERCLK_CLK source to OSC_CLK*/ + CLOCK_SetMux(kCLOCK_PerclkMux, 1U); + /* Set PERCLK_CLK divider to 1 */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 0U); +} + +uint32_t us_ticker_get_clock() +{ + return CLOCK_GetFreq(kCLOCK_OscClk); +} + +void serial_setup_clock(void) +{ + /* Configure UART divider to default */ + CLOCK_SetMux(kCLOCK_UartMux, 1); /* Set UART source to OSC 24M */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ +} + +uint32_t serial_get_clock(void) +{ + uint32_t clock_freq; + + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ { + clock_freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } else { + clock_freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + + return clock_freq; +} + +void i2c_setup_clock() +{ + /* Select USB1 PLL (480 MHz) as master lpi2c clock source */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0U); + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER); +} + +uint32_t i2c_get_clock() +{ + return ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U)); +} + +void pwm_setup(uint32_t instance) +{ + /* Use default clock settings */ + /* Set the PWM Fault inputs to a low value */ + XBARA_Init(XBARA1); + + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault2); + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1234Fault3); + + switch (instance) { + case 1: + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault0); + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm1Fault1); + break; + case 2: + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm2Fault0); + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm2Fault1); + break; + case 3: + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm3Fault0); + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm3Fault1); + break; + case 4: + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm4Fault0); + XBARA_SetSignalsConnection(XBARA1, kXBARA1_InputLogicHigh, kXBARA1_OutputFlexpwm4Fault1); + break; + default: + break; + } +} + +uint32_t pwm_get_clock() +{ + return CLOCK_GetFreq(kCLOCK_IpgClk); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + pin_function(WAKEUP, 7); + pin_mode(WAKEUP, PullDefault); +} + +void mbed_mac_address(char *mac) { + if (mbed_otp_mac_address(mac)) { + return; + } else { + mbed_default_mac_address(mac); + } + return; +} + +uint8_t mbed_otp_mac_address(char *mac) { + /* Check if a valid MAC address is programmed to the fuse bank */ + if ((OCOTP->MAC0 != 0) && + (OCOTP->MAC1 != 0) && + (OCOTP->GP3 != 0)) { + uint16_t MAC[3]; // 3 16 bits words for the MAC + + // Read the MAC address from the OCOTP MAC registers + MAC[0] = (uint16_t)OCOTP->MAC0; // most significant half-word + MAC[1] = (uint16_t)OCOTP->MAC1; + MAC[2] = (uint16_t)OCOTP->GP3; // least significant half word + + // The network stack expects an array of 6 bytes + // so we copy, and shift and copy from the half-word array to the byte array + mac[0] = MAC[0] >> 8; + mac[1] = MAC[0]; + mac[2] = MAC[1] >> 8; + mac[3] = MAC[1]; + mac[4] = MAC[2] >> 8; + mac[5] = MAC[2]; + } else { + return 0; + } + return 1; +} + +void mbed_default_mac_address(char *mac) { + mac[0] = 0x00; + mac[1] = 0x02; + mac[2] = 0xF7; + mac[3] = 0xF0; + mac[4] = 0x00; + mac[5] = 0x00; + + return; +} + +void USB_DeviceClockInit(void) +{ + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, 480000000U); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, 480000000U); + + USB_EhciPhyInit(CONTROLLER_ID, BOARD_XTAL0_CLK_HZ, &phyConfig); +} + +uint32_t USB_DeviceGetIrqNumber(void) +{ + uint8_t irqNumber; + + uint8_t usbDeviceEhciIrq[] = USBHS_IRQS; + irqNumber = usbDeviceEhciIrq[CONTROLLER_ID - kUSB_ControllerEhci0]; + + return irqNumber; +} + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/pinmap.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/pinmap.c new file mode 100644 index 0000000..15c3f6e --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/pinmap.c @@ -0,0 +1,159 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "PeripheralPins.h" +#include "mbed_error.h" +#include "fsl_clock.h" + +/* Array of IOMUX base address. */ +static uint32_t iomux_base_addrs[FSL_FEATURE_SOC_IGPIO_COUNT] = { 0x401F80BC, 0x401F813C, 0u, 0x401F8014, 0x400A8000 }; + +/* Get the IOMUX register address from the GPIO3 pin number */ +static uint32_t get_iomux_reg_base(PinName pin) +{ + int32_t gpio_pin = pin & 0xFF; + uint32_t retval = 0; + + if ((gpio_pin >= 0) && (gpio_pin < 12)) { + retval = 0x401F81D4 + (gpio_pin * 4); + } else if ((gpio_pin >= 12) && (gpio_pin < 18)) { + retval = 0x401F81BC + ((gpio_pin - 12) * 4); + } else if ((gpio_pin >= 18) && (gpio_pin < 28)) { + retval = 0x401F8094 + ((gpio_pin - 18) * 4); + } + + return retval; +} + +void pin_function(PinName pin, int function) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t muxregister = iomux_base_addrs[(pin >> GPIO_PORT_SHIFT) - 1]; + uint32_t daisyregister; + + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* Get mux register address */ + if (muxregister == 0) { + muxregister = get_iomux_reg_base(pin); + } else { + muxregister = muxregister + ((pin & 0xFF) * 4); + } + + /* Write to the mux register */ + *((volatile uint32_t *)muxregister) = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(function) | + IOMUXC_SW_MUX_CTL_PAD_SION((function >> SION_BIT_SHIFT) & 0x1); + + /* If required write to the input daisy register */ + daisyregister = (function >> DAISY_REG_SHIFT) & 0xFFF; + if (daisyregister != 0) { + daisyregister = daisyregister + 0x401F8000; + *((volatile uint32_t *)daisyregister) = IOMUXC_SELECT_INPUT_DAISY(((function >> DAISY_REG_VALUE_SHIFT) & 0xF)); + } +} + +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t instance = pin >> GPIO_PORT_SHIFT; + uint32_t reg; + uint32_t muxregister = iomux_base_addrs[instance - 1]; + uint32_t configregister; + + if (muxregister == 0) { + muxregister = get_iomux_reg_base(pin); + } else { + muxregister = muxregister + ((pin & 0xFF) * 4); + } + + /* Get pad register address */ + if (instance == 5) { + configregister = muxregister + 0x10; + } else { + configregister = muxregister + 0x1F0; + } + + reg = *((volatile uint32_t *)configregister); + switch (mode) { + case PullNone: + /* Write 0 to the PUE bit & 1 to the PKE bit to set the pad to keeper mode */ + reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK); + break; + case PullDown: + /* Write 1 to PKE & PUE bit to enable the pull configuration and 0 to PUS bit for 100K pull down */ + reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); + reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + break; + case PullUp_47K: + /* Write 1 to PKE & PUE bit to enable the pull configuration and 1 to PUS bit for 47K pull up*/ + reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); + reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(1); + reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + break; + case PullUp_100K: + /* Write 1 to PKE & PUE bit to enable the pull configuration and 2 to PUS bit for 100K pull up*/ + reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); + reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2); + reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + break; + case PullUp_22K: + /* Write 1 to PKE & PUE bit to enable the pull configuration and 3 to PUS bit for 22K pull up*/ + reg &= ~(IOMUXC_SW_PAD_CTL_PAD_PUS_MASK); + reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(3); + reg |= (IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); + break; + default: + break; + } + + /* Below settings for DSE and SPEED fields per test results */ + reg = (reg & ~(IOMUXC_SW_PAD_CTL_PAD_DSE_MASK | IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK)) | + IOMUXC_SW_PAD_CTL_PAD_DSE(6) | IOMUXC_SW_PAD_CTL_PAD_SPEED(2); + + /* Write value to the pad register */ + *((volatile uint32_t *)configregister) = reg; +} + +void pin_mode_opendrain(PinName pin, bool enable) +{ + MBED_ASSERT(pin != (PinName)NC); + + uint32_t instance = pin >> GPIO_PORT_SHIFT; + uint32_t muxregister = iomux_base_addrs[instance - 1]; + uint32_t configregister; + + if (muxregister == 0) { + muxregister = get_iomux_reg_base(pin); + } else { + muxregister = muxregister + ((pin & 0xFF) * 4); + } + + /* Get pad register address */ + if (instance == 5) { + configregister = muxregister + 0x10; + } else { + configregister = muxregister + 0x1F0; + } + + if (enable) { + *((volatile uint32_t *)configregister) |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK; + } else { + *((volatile uint32_t *)configregister) &= ~IOMUXC_SW_PAD_CTL_PAD_ODE_MASK; + } +} + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/serial_api.c new file mode 100644 index 0000000..0af83e9 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/serial_api.c @@ -0,0 +1,382 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_lpuart.h" +#include "PeripheralPins.h" +#include "fsl_clock_config.h" + +/* LPUART starts from index 1 */ +static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0}; +static uart_irq_handler irq_handler; +/* Array of UART peripheral base address. */ +static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +extern void serial_setup_clock(void); +extern uint32_t serial_get_clock(void); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + + serial_setup_clock(); + + lpuart_config_t config; + LPUART_GetDefaultConfig(&config); + config.baudRate_Bps = 9600; + config.enableTx = false; + config.enableRx = false; + + LPUART_Init(uart_addrs[obj->index], &config, serial_get_clock()); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + LPUART_EnableTx(uart_addrs[obj->index], true); + pin_mode(tx, PullDefault); + } + if (rx != NC) { + LPUART_EnableRx(uart_addrs[obj->index], true); + pin_mode(rx, PullDefault); + } + + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) +{ + LPUART_Deinit(uart_addrs[obj->index]); + serial_irq_ids[obj->index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, serial_get_clock()); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + LPUART_Type *base = uart_addrs[obj->index]; + uint8_t temp; + /* Set bit count and parity mode. */ + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); + if (parity != ParityNone) { + /* Enable Parity */ + temp |= (LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK); + if (parity == ParityOdd) { + temp |= LPUART_CTRL_PT_MASK; + } else if (parity == ParityEven) { + // PT=0 so nothing more to do + } else { + // Hardware does not support forced parity + MBED_ASSERT(0); + } + } + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)--stop_bits); +#endif +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) +{ + LPUART_Type *base = uart_addrs[index]; + + /* If RX overrun. */ + if (LPUART_STAT_OR_MASK & base->STAT) { + /* Read base->D, otherwise the RX does not work. */ + (void)base->DATA; + LPUART_ClearStatusFlags(base, kLPUART_RxOverrunFlag); + } + + if (serial_irq_ids[index] != 0) { + if (transmit_empty) { + irq_handler(serial_irq_ids[index], TxIrq); + } + + if (receive_full) { + irq_handler(serial_irq_ids[index], RxIrq); + } + } +} + +void uart1_irq() +{ + uint32_t status_flags = LPUART1->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 1); +} + +void uart2_irq() +{ + uint32_t status_flags = LPUART2->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 2); +} + +void uart3_irq() +{ + uint32_t status_flags = LPUART3->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 3); +} + +void uart4_irq() +{ + uint32_t status_flags = LPUART4->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 4); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type uart_irqs[] = LPUART_RX_TX_IRQS; + uint32_t vector = 0; + + switch (obj->index) { + case 1: + vector = (uint32_t)&uart1_irq; + break; + case 2: + vector = (uint32_t)&uart2_irq; + break; + case 3: + vector = (uint32_t)&uart3_irq; + break; + case 4: + vector = (uint32_t)&uart4_irq; + break; + default: + break; + } + + if (enable) { + switch (irq) { + case RxIrq: + LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + LPUART_EnableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + NVIC_SetVector(uart_irqs[obj->index], vector); + NVIC_EnableIRQ(uart_irqs[obj->index]); + + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + switch (irq) { + case RxIrq: + LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + LPUART_DisableInterrupts(uart_addrs[obj->index], kLPUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + switch (other_irq) { + case RxIrq: + all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_RxDataRegFullInterruptEnable) == 0); + break; + case TxIrq: + all_disabled = ((LPUART_GetEnabledInterrupts(uart_addrs[obj->index]) & kLPUART_TxDataRegEmptyInterruptEnable) == 0); + break; + default: + break; + } + if (all_disabled) + NVIC_DisableIRQ(uart_irqs[obj->index]); + } +} + +int serial_getc(serial_t *obj) +{ + uint8_t data; + + LPUART_ReadBlocking(uart_addrs[obj->index], &data, 1); + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)); + LPUART_WriteByte(uart_addrs[obj->index], (uint8_t)c); +} + +int serial_readable(serial_t *obj) +{ + uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kLPUART_RxOverrunFlag) { + LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag); + } + return (status_flags & kLPUART_RxDataRegFullFlag); +} + +int serial_writable(serial_t *obj) +{ + uint32_t status_flags = LPUART_GetStatusFlags(uart_addrs[obj->index]); + if (status_flags & kLPUART_RxOverrunFlag) { + LPUART_ClearStatusFlags(uart_addrs[obj->index], kLPUART_RxOverrunFlag); + } + return (status_flags & kLPUART_TxDataRegEmptyFlag); +} + +void serial_clear(serial_t *obj) +{ + +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + uart_addrs[obj->index]->CTRL |= LPUART_CTRL_SBK_MASK; +} + +void serial_break_clear(serial_t *obj) +{ + uart_addrs[obj->index]->CTRL &= ~LPUART_CTRL_SBK_MASK; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_CTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ +#if !DEVICE_SERIAL_FC + static const PinMap PinMap_UART_RTS[] = { + {NC, NC, 0} + }; +#endif + + return PinMap_UART_RTS; +} + +static int serial_is_enabled(uint32_t uart_index) +{ + int clock_enabled = 0; + switch (uart_index) { + case 1: + clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG12_MASK) >> CCM_CCGR5_CG12_SHIFT; + break; + case 2: + clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG14_MASK) >> CCM_CCGR0_CG14_SHIFT; + break; + case 3: + clock_enabled = (CCM->CCGR0 & CCM_CCGR0_CG6_MASK) >> CCM_CCGR0_CG6_SHIFT; + break; + case 4: + clock_enabled = (CCM->CCGR1 & CCM_CCGR1_CG12_MASK) >> CCM_CCGR1_CG12_SHIFT; + break; + case 5: + clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG1_MASK) >> CCM_CCGR3_CG1_SHIFT; + break; + case 6: + clock_enabled = (CCM->CCGR3 & CCM_CCGR3_CG3_MASK) >> CCM_CCGR3_CG3_SHIFT; + break; + case 7: + clock_enabled = (CCM->CCGR5 & CCM_CCGR5_CG13_MASK) >> CCM_CCGR5_CG13_SHIFT; + break; + case 8: + clock_enabled = (CCM->CCGR6 & CCM_CCGR6_CG7_MASK) >> CCM_CCGR6_CG7_SHIFT; + break; + default: + break; + } + + return clock_enabled; +} + +bool serial_check_tx_ongoing() +{ + LPUART_Type *base; + int i; + bool uart_tx_ongoing = false; + + /* The first LPUART instance number is 1 */ + for (i = 1; i <= FSL_FEATURE_SOC_LPUART_COUNT; i++) { + /* First check if UART is enabled */ + if (!serial_is_enabled(i)) { + /* UART is not enabled, check the next instance */ + continue; + } + + base = uart_addrs[i]; + + /* Check if data is waiting to be written out of transmit buffer */ + if (!(kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags((LPUART_Type *)base))) { + uart_tx_ongoing = true; + break; + } + } + + return uart_tx_ongoing; +} + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/sleep.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/sleep.c new file mode 100644 index 0000000..44e1ede --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/sleep.c @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "sleep_api.h" +#include "cmsis.h" +#include "fsl_clock.h" + +extern void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode); +extern void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode); +extern bool serial_check_tx_ongoing(); + +void hal_sleep(void) +{ + __DSB(); + __WFI(); + __ISB(); +} + +void hal_deepsleep(void) +{ + /* Check if any of the UART's is transmitting data */ + if (serial_check_tx_ongoing()) { + return; + } + + vPortPRE_SLEEP_PROCESSING(kCLOCK_ModeStop); + + __DSB(); + __WFI(); + __ISB(); + + vPortPOST_SLEEP_PROCESSING(kCLOCK_ModeStop); +} + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.c new file mode 100644 index 0000000..5abd97c --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.c @@ -0,0 +1,615 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "specific.h" +#include "fsl_common.h" +#include "fsl_clock.h" +#include "lpm.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +const clock_arm_pll_config_t armPllConfig_PowerMode = { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; +const clock_sys_pll_config_t sysPllConfig_PowerMode = { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; +const clock_usb_pll_config_t usb1PllConfig_PowerMode = { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ +}; + +AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode)); + +#define NUMBER_OF_CCM_GATE_REGS 7 +static uint32_t clock_gate_values[NUMBER_OF_CCM_GATE_REGS]; + +void SwitchSystemClocks(lpm_power_mode_t power_mode) +{ +#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) + { + } + FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; + + /* Disable clock gate of flexspi. */ + CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK); +#endif + switch (power_mode) + { + case LPM_PowerModeOverRun: + CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz + CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode + CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0 + /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */ + //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1); + CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); + CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); + //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK + CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL + CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK + break; + case LPM_PowerModeFullRun: + CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz + CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode + CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0 + /* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */ + CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1); + CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); + CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); + CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK + CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL + CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK + break; + case LPM_PowerModeLowSpeedRun: + case LPM_PowerModeSysIdle: + CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz +#ifdef HYPERFLASH_BOOT + CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode +#else + CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 3); // FLEXSPI in SDR mode +#endif + CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2 + /* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */ + CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0); + CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); + CLOCK_SET_DIV(kCLOCK_AhbDiv, 3); + CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK + CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // Switch PRE_PERIPH_CLK to SYS PLL + CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // Switch PERIPH_CLK to PRE_PERIPH_CLK + break; + case LPM_PowerModeLowPowerRun: + case LPM_PowerModeLPIdle: + CLOCK_SET_DIV(kCLOCK_PeriphClk2Div, 0); + CLOCK_SET_MUX(kCLOCK_PeriphClk2Mux, 1); // PERIPH_CLK2 mux to OSC + CLOCK_SET_MUX(kCLOCK_PeriphMux, 1); // PERIPH_CLK mux to PERIPH_CLK2 + CLOCK_SET_DIV(kCLOCK_SemcDiv, 0); + CLOCK_SET_MUX(kCLOCK_SemcMux, 0); // SEMC mux to PERIPH_CLK + CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode + CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre + /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */ + //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0); + CLOCK_SET_DIV(kCLOCK_IpgDiv, 1); + CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); + //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK + break; + default: + break; + } + +#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Enable clock gate of flexspi. */ + CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK); + +#ifdef HYPERFLASH_BOOT + if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode)) + { + FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19); + } + else + { + FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15); + } +#endif + + FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) + { + } + while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) + { + } +#endif +} + +void ClockSetToOverDriveRun(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + LPM_ExitCritical(); + //ClockSelectXtalOsc(); + + /* Init ARM PLL */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + CLOCK_InitArmPll(&armPllConfig_PowerMode); + + /* Init SYS PLL*/ + CLOCK_InitSysPll(&sysPllConfig_PowerMode); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); + + /* Init USB1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + + /* Init USB2 PLL*/ + CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK; + CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK; + CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK; + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK; + + /* Init AUDIO PLL */ + CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; + CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; + CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; + + /* Init VIDEO PLL */ + CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; + CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + + /* Init ENET PLL */ + CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK; + CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; + CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK; + CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK; + + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeOverRun); + LPM_ExitCritical(); +} + +void ClockSetToFullSpeedRun(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + LPM_ExitCritical(); + ClockSelectXtalOsc(); + + /* Init ARM PLL */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + CLOCK_InitArmPll(&armPllConfig_PowerMode); + + /* Init SYS PLL. */ + CLOCK_InitSysPll(&sysPllConfig_PowerMode); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); + + /* Init USB1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + + /* Init USB2 PLL*/ + CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK; + CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK; + CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK; + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK; + + /* Init AUDIO PLL */ + CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; + CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; + CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; + + /* Init VIDEO PLL */ + CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; + CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + + /* Init ENET PLL */ + CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK; + CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; + CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK; + CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } + CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK; + + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeFullRun); + LPM_ExitCritical(); +} + +void ClockSetToLowSpeedRun(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + LPM_ExitCritical(); + ClockSelectXtalOsc(); + + /* Deinit ARM PLL */ + CLOCK_DeinitArmPll(); + + /* Init SYS PLL */ + CLOCK_InitSysPll(&sysPllConfig_PowerMode); + + /* Deinit SYS PLL PFD 0 1 3 */ + CLOCK_DeinitSysPfd(kCLOCK_Pfd0); + CLOCK_DeinitSysPfd(kCLOCK_Pfd1); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + CLOCK_DeinitSysPfd(kCLOCK_Pfd3); + + /* Deinit USB1 PLL */ + CLOCK_DeinitUsb1Pll(); + + /* Deinit USB1 PLL PFD 0 1 2 3 */ + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); + + /* Deinit USB2 PLL */ + CLOCK_DeinitUsb2Pll(); + + /* Deinit AUDIO PLL */ + CLOCK_DeinitAudioPll(); + + /* Deinit VIDEO PLL */ + CLOCK_DeinitVideoPll(); + + /* Deinit ENET PLL */ + CLOCK_DeinitEnetPll(); + + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLowSpeedRun); + LPM_ExitCritical(); +} + +void ClockSetToLowPowerRun(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + LPM_ExitCritical(); + ClockSelectRcOsc(); + + /* Deinit ARM PLL */ + CLOCK_DeinitArmPll(); + + /* Deinit SYS PLL */ + CLOCK_DeinitSysPll(); + + /* Deinit SYS PLL PFD 0 1 2 3 */ + CLOCK_DeinitSysPfd(kCLOCK_Pfd0); + CLOCK_DeinitSysPfd(kCLOCK_Pfd1); + CLOCK_DeinitSysPfd(kCLOCK_Pfd2); + CLOCK_DeinitSysPfd(kCLOCK_Pfd3); + + /* Power Down USB1 PLL */ + CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK; + CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK; + CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK; + + /* Deinit USB1 PLL PFD 0 1 2 3 */ + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); + + /* Deinit USB2 PLL */ + CLOCK_DeinitUsb2Pll(); + + /* Deinit AUDIO PLL */ + CLOCK_DeinitAudioPll(); + + /* Deinit VIDEO PLL */ + CLOCK_DeinitVideoPll(); + + /* Deinit ENET PLL */ + CLOCK_DeinitEnetPll(); +} + +void ClockSetToSystemIdle(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + LPM_ExitCritical(); + ClockSelectXtalOsc(); + + /* Deinit ARM PLL */ + CLOCK_DeinitArmPll(); + + /* Init SYS PLL */ + CLOCK_InitSysPll(&sysPllConfig_PowerMode); + + /* Deinit SYS PLL PFD 0 1 3 */ + CLOCK_DeinitSysPfd(kCLOCK_Pfd0); + CLOCK_DeinitSysPfd(kCLOCK_Pfd1); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); + CLOCK_DeinitSysPfd(kCLOCK_Pfd3); + + /* Deinit USB1 PLL */ + CLOCK_DeinitUsb1Pll(); + + /* Deinit USB1 PLL PFD 0 1 2 3 */ + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); + + /* Deinit USB2 PLL */ + CLOCK_DeinitUsb2Pll(); + + /* Deinit AUDIO PLL */ + CLOCK_DeinitAudioPll(); + + /* Deinit VIDEO PLL */ + CLOCK_DeinitVideoPll(); + + /* Deinit ENET PLL */ + CLOCK_DeinitEnetPll(); + + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeSysIdle); + LPM_ExitCritical(); +} + +void ClockSetToLowPowerIdle(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + LPM_ExitCritical(); + //ClockSelectRcOsc(); + + /* Deinit ARM PLL */ + CLOCK_DeinitArmPll(); + + /* Deinit SYS PLL */ + CLOCK_DeinitSysPll(); + + /* Deinit SYS PLL PFD 0 1 2 3 */ + CLOCK_DeinitSysPfd(kCLOCK_Pfd0); + CLOCK_DeinitSysPfd(kCLOCK_Pfd1); + CLOCK_DeinitSysPfd(kCLOCK_Pfd2); + CLOCK_DeinitSysPfd(kCLOCK_Pfd3); + + /* Deinit USB1 PLL */ + CLOCK_DeinitUsb1Pll(); + + /* Deinit USB1 PLL PFD 0 1 2 3 */ + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); + CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); + + /* Deinit USB2 PLL */ + CLOCK_DeinitUsb2Pll(); + + /* Deinit AUDIO PLL */ + CLOCK_DeinitAudioPll(); + + /* Deinit VIDEO PLL */ + CLOCK_DeinitVideoPll(); + + /* Deinit ENET PLL */ + CLOCK_DeinitEnetPll(); + + LPM_EnterCritical(); + SwitchSystemClocks(LPM_PowerModeLPIdle); + LPM_ExitCritical(); +} + +void SetLowPowerClockGate(void) +{ + /* Save of the clock gate registers */ + clock_gate_values[0] = CCM->CCGR0; + clock_gate_values[1] = CCM->CCGR1; + clock_gate_values[2] = CCM->CCGR2; + clock_gate_values[3] = CCM->CCGR3; + clock_gate_values[4] = CCM->CCGR4; + clock_gate_values[5] = CCM->CCGR5; + clock_gate_values[6] = CCM->CCGR6; + + /* Set low power gate values */ + CCM->CCGR0 = CCM_CCGR0_CG0(1) | CCM_CCGR0_CG1(1) | CCM_CCGR0_CG3(3) | CCM_CCGR0_CG11(1) | CCM_CCGR0_CG12(1); + CCM->CCGR1 = CCM_CCGR1_CG9(3) | CCM_CCGR1_CG10(1) | CCM_CCGR1_CG13(1) | CCM_CCGR1_CG14(1) | CCM_CCGR1_CG15(1); + CCM->CCGR2 = CCM_CCGR2_CG2(1) | CCM_CCGR2_CG8(1) | CCM_CCGR2_CG9(1) | CCM_CCGR2_CG10(1); + CCM->CCGR3 = CCM_CCGR3_CG2(1) | CCM_CCGR3_CG4(1) | CCM_CCGR3_CG9(1) | CCM_CCGR3_CG14(3) | CCM_CCGR3_CG15(1); + CCM->CCGR4 = + CCM_CCGR4_CG1(1) | CCM_CCGR4_CG2(1) | CCM_CCGR4_CG4(1) | CCM_CCGR4_CG5(1) | CCM_CCGR4_CG6(1) | CCM_CCGR4_CG7(1); + CCM->CCGR5 = CCM_CCGR5_CG0(1) | CCM_CCGR5_CG1(1) | CCM_CCGR5_CG4(1) | CCM_CCGR5_CG6(1) | CCM_CCGR5_CG12(1) | + CCM_CCGR5_CG14(1) | CCM_CCGR5_CG15(1); + /* We can enable DCDC when need to config it and close it after configuration */ + CCM->CCGR6 = CCM_CCGR6_CG3(1) | CCM_CCGR6_CG4(1) | CCM_CCGR6_CG5(1) | CCM_CCGR6_CG9(1) | CCM_CCGR6_CG10(1) | + CCM_CCGR6_CG11(1); +} + +void SetRestoreClockGate(void) +{ + CCM->CCGR0 = clock_gate_values[0]; + CCM->CCGR1 = clock_gate_values[1]; + CCM->CCGR2 = clock_gate_values[2]; + CCM->CCGR3 = clock_gate_values[3]; + CCM->CCGR4 = clock_gate_values[4]; + CCM->CCGR5 = clock_gate_values[5]; + CCM->CCGR6 = clock_gate_values[6]; +} + +void PowerDownUSBPHY(void) +{ + USBPHY1->CTRL = 0xFFFFFFFF; + USBPHY2->CTRL = 0xFFFFFFFF; +} + +void ConfigUartRxPinToGpio(void) +{ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, 0); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2) | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); +} + +void ReConfigUartRxPin(void) +{ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_SW_PAD_CTL_PAD_SPEED(2)); +} + +#define GPR4_STOP_REQ_BITS \ + (IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) + +#define GPR4_STOP_ACK_BITS \ + (IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) + +#define GPR7_STOP_REQ_BITS \ + (IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) + +#define GPR7_STOP_ACK_BITS \ + (IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) + +#define GPR8_DOZE_BITS \ + (IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) + +#define GPR8_STOP_MODE_BITS \ + (IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) + +#define GPR12_DOZE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) + +#define GPR12_STOP_MODE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) + +void PeripheralEnterDozeMode(void) +{ + IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS; + IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS; +} + +void PeripheralExitDozeMode(void) +{ + IOMUXC_GPR->GPR8 = 0x00000000; + IOMUXC_GPR->GPR12 = 0x00000000; +} + +void PeripheralEnterStopMode(void) +{ + IOMUXC_GPR->GPR4 = IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK; + while ((IOMUXC_GPR->GPR4 & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) != IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) + { + } + IOMUXC_GPR->GPR4 = GPR4_STOP_REQ_BITS; + IOMUXC_GPR->GPR7 = GPR7_STOP_REQ_BITS; + IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS | GPR8_STOP_MODE_BITS; + IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS | GPR12_STOP_MODE_BITS; + while ((IOMUXC_GPR->GPR4 & GPR4_STOP_ACK_BITS) != GPR4_STOP_ACK_BITS) + { + } + while ((IOMUXC_GPR->GPR7 & GPR7_STOP_ACK_BITS) != GPR7_STOP_ACK_BITS) + { + } +} + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.h new file mode 100644 index 0000000..cc384b4 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.h @@ -0,0 +1,49 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _SPECIFIC_H_ +#define _SPECIFIC_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FLEXSPI_INST FLEXSPI +#define HAS_WAKEUP_PIN (1) + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void ClockSetToOverDriveRun(void); +void ClockSetToFullSpeedRun(void); +void ClockSetToLowSpeedRun(void); +void ClockSetToLowPowerRun(void); +void ClockSetToSystemIdle(void); +void ClockSetToLowPowerIdle(void); + +void SetLowPowerClockGate(void); +void SetRestoreClockGate(void); +void PowerDownUSBPHY(void); +void ConfigUartRxPinToGpio(void); +void ReConfigUartRxPin(void); +void PeripheralEnterDozeMode(void); +void PeripheralExitDozeMode(void); +void PeripheralEnterStopMode(void); +void APP_PrintRunFrequency(int32_t run_freq_only); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _SPECIFIC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/trng_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/trng_api.c new file mode 100644 index 0000000..f82ae02 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/trng_api.c @@ -0,0 +1,49 @@ +/* + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#include +#include "cmsis.h" +#include "fsl_trng.h" +#include "trng_api.h" + +void trng_init(trng_t *obj) +{ + (void)obj; + trng_config_t trngConfig; + TRNG_GetDefaultConfig(&trngConfig); + TRNG_Init(TRNG, &trngConfig); +} + +void trng_free(trng_t *obj) +{ + (void)obj; + TRNG_Deinit(TRNG); +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + (void)obj; + + if(TRNG_GetRandomData(TRNG, output, length) != kStatus_Success) { + return -1; + } + *output_length = length; + + return 0; +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker.c new file mode 100644 index 0000000..87c0dcc --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker.c @@ -0,0 +1,149 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "us_ticker_defines.h" +#include "fsl_pit.h" +#include "fsl_clock_config.h" + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + 1000000, // 1 MHz + 32 // 32 bit counter + }; + return &info; +} + +static bool us_ticker_inited = false; + +extern void us_ticker_setup_clock(); +extern uint32_t us_ticker_get_clock(); + +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + +/** Initialize the high frequency ticker + * + */ +void us_ticker_init(void) +{ + /* Common for ticker/timer. */ + uint32_t busClock; + + us_ticker_setup_clock(); + + busClock = us_ticker_get_clock(); + + /* Let the timer to count if re-init. */ + if (!us_ticker_inited) { + /* Structure to initialize PIT. */ + pit_config_t pitConfig; + + PIT_GetDefaultConfig(&pitConfig); + PIT_Init(PIT, &pitConfig); + + PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); + PIT_StartTimer(PIT, kPIT_Chnl_0); + PIT_StartTimer(PIT, kPIT_Chnl_1); + } + + /* Configure interrupt generation counters and disable ticker interrupts. */ + PIT_StopTimer(PIT, kPIT_Chnl_3); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); + NVIC_SetVector(PIT_IRQn, (uint32_t) pit_isr); + NVIC_EnableIRQ(PIT_IRQn); + PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); + + us_ticker_inited = true; +} + +/** Read the current counter + * + * @return The current timer's counter value in ticks + */ +uint32_t (us_ticker_read)() +{ + return us_ticker_read(); +} + +/** Disable us ticker interrupt + * + */ +void us_ticker_disable_interrupt(void) +{ + PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); +} + +/** Clear us ticker interrupt + * + */ +void us_ticker_clear_interrupt(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); +} + +/** Set interrupt for specified timestamp + * + * @param timestamp The time in ticks when interrupt should be generated + */ +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + /* We get here absolute interrupt time which takes into account counter overflow. + * Since we use additional count-down timer to generate interrupt we need to calculate + * load value based on time-stamp. + */ + const uint32_t now_ticks = us_ticker_read(); + uint32_t delta_ticks = + timestamp >= now_ticks ? timestamp - now_ticks : (uint32_t)((uint64_t) timestamp + 0xFFFFFFFF - now_ticks); + + if (delta_ticks == 0) { + /* The requested delay is less than the minimum resolution of this counter. */ + delta_ticks = 1; + } + + PIT_StopTimer(PIT, kPIT_Chnl_3); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, delta_ticks); + PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); + PIT_StartTimer(PIT, kPIT_Chnl_3); + PIT_StartTimer(PIT, kPIT_Chnl_2); +} + +/** Fire us ticker interrupt + * + */ +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(PIT_IRQn); +} + +void us_ticker_free(void) +{ + +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker_defines.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker_defines.h new file mode 100644 index 0000000..46c07de --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker_defines.h @@ -0,0 +1,30 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef _NXP_US_TICKER_DEFINES_H_ +#define _NXP_US_TICKER_DEFINES_H_ + +#include "fsl_pit.h" + +#define US_TICKER_PERIOD_NUM 1 +#define US_TICKER_PERIOD_DEN 1 + +#define US_TICKER_MASK 0xFFFFFFFF + +/* Macro-optimised form of us_ticker_read */ +#define us_ticker_read() (~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1))) + +#endif /* _NXP_US_TICKER_DEFINES_H_ */ diff --git a/targets/targets.json b/targets/targets.json index f26eff2..cbec7aa 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5008,40 +5008,32 @@ "mbed_ram_start": "0x20000000", "mbed_ram_size": "0x10000" }, - "MIMXRT1050_EVK": { - "supported_form_factors": [ - "ARDUINO_UNO" - ], + "MIMXRT105X": { "core": "Cortex-M7FD", "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" + "GCC_ARM" ], "supported_application_profiles": [ "full", "bare-metal" ], + "public": false, "extra_labels": [ "NXP", "MCUXpresso_MCUS", - "EVK", "MIMXRT1050", "IMX", "NXP_EMAC", - "USB" + "USB" ], - "is_disk_virtual": true, "macros": [ "CPU_MIMXRT1052DVL6B", "FSL_RTOS_MBED", "XIP_BOOT_HEADER_ENABLE=1", "XIP_EXTERNAL_FLASH=1", - "XIP_BOOT_HEADER_DCD_ENABLE=1", "HYPERFLASH_BOOT", "FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1", "SKIP_SYSCLK_INIT", - "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE", "__STARTUP_INITIALIZE_RAMFUNCTION", "__STARTUP_INITIALIZE_NONCACHEDATA", "MBED_MPU_CUSTOM", @@ -5054,14 +5046,10 @@ "inherits": [ "Target" ], - "detect_code": [ - "0227" - ], "device_has": [ "RTC", "SLEEP", "USTICKER", - "LPTICKER", "ANALOGIN", "EMAC", "I2C", @@ -5078,22 +5066,87 @@ "STDIO_MESSAGES", "TRNG", "WATCHDOG", - "FLASH", "USBDEVICE" ], - "release_versions": [ - "5" - ], "features": [ "LWIP" ], "device_name": "MIMXRT1052", - "bootloader_supported": true, "overrides": { - "deep-sleep-latency": 10, + "deep-sleep-latency": 10 + } + }, + "MIMXRT1050_EVK": { + "inherits": [ + "MIMXRT105X" + ], + "extra_labels_add": [ + "EVK", + "1050_EVK" + ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "macros_add": [ + "XIP_BOOT_HEADER_DCD_ENABLE=1", + "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE", + "MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=1", + "MIMXRT105X_EXTERNAL_RAM_SIZE=0x01E00000" + ], + "device_has_add": [ + "LPTICKER", + "FLASH" + ], + "detect_code": [ + "0227" + ], + "overrides": { + "network-default-interface-type": "ETHERNET" + }, + "bootloader_supported": true + }, + "MIMXRT1060_EVK": { + "inherits": [ + "MIMXRT105X" + ], + "extra_labels_add": [ + "EVK", + "1060_EVK" + ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "macros_add": [ + "XIP_BOOT_HEADER_DCD_ENABLE=1", + "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE", + "MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=1", + "MIMXRT105X_EXTERNAL_RAM_SIZE=0x01E00000", + "MBED_APP_SIZE=0x800000" + ], + "overrides": { "network-default-interface-type": "ETHERNET" } }, + "TEENSY_40": { + "inherits": [ + "MIMXRT105X" + ], + "extra_labels_add": [ + "TEENSY_4X", + "TEENSY_40" + ], + "macros_add": [ + "MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=0", + "MBED_APP_SIZE=0x1f0000" + ], + "overrides": { + "console-usb": true, + "console-uart": false + }, + "device_has_remove": [ + "EMAC" + ] + }, "MIMXRT1170_EVK": { "supported_form_factors": [ "ARDUINO_UNO" diff --git a/targets/upload_method_cfg/MIMXRT1060_EVK.cmake b/targets/upload_method_cfg/MIMXRT1060_EVK.cmake new file mode 100644 index 0000000..cc7a65b --- /dev/null +++ b/targets/upload_method_cfg/MIMXRT1060_EVK.cmake @@ -0,0 +1,41 @@ +# Mbed OS upload method configuration file for target MIMXRT1060_EVK. +# To change any of these parameters from their default values, set them in your build script between where you +# include app.cmake and where you add mbed os as a subdirectory. +# +# Notes: +# 1. Using the JLINK upload method requires either converting the board's LPC-Link into a J-Link, or +# connecting an external J-Link probe. See here for conversion instructions: https://www.segger.com/products/debug-probes/j-link/models/other-j-links/lpc-link-2/ +# Also, a relatively new version of the J-Link software is needed (7.82 confirmed working), so try updating +# it if you get any errors. +# 2. pyocd seems glitchy for this device. Sometimes it works great, sometimes you get 'no ACK received.' +# Might be related to pyOCD#861? + +# General config parameters +# ------------------------------------------------------------- +set(UPLOAD_METHOD_DEFAULT JLINK) + +# Config options for JLINK +# ------------------------------------------------------------- +set(JLINK_UPLOAD_ENABLED TRUE) +set(JLINK_CPU_NAME MIMXRT1062xxx5B?BankAddr=0x60000000&Loader=QSPI) # Extra parameters needed to select correct flash loader +set(JLINK_UPLOAD_INTERFACE SWD) +set(JLINK_CLOCK_SPEED 4000) + +# Config options for PYOCD +# ------------------------------------------------------------- +set(PYOCD_UPLOAD_ENABLED TRUE) +set(PYOCD_TARGET_NAME mimxrt1060) # Note: This seems to use QSPI. There does not seem to be a pyocd equivalent for hyperflash. +set(PYOCD_CLOCK_SPEED 4000k) + +# Config options for REDLINK +# ------------------------------------------------------------- +set(REDLINK_UPLOAD_ENABLED TRUE) +set(REDLINK_PART_NUMBER MIMXRT1062xxxxA) +set(REDLINK_PART_XML_DIR ${CMAKE_CURRENT_LIST_DIR}/redlink_cfgs) +set(REDLINK_CLOCK_SPEED 4000) +set(REDLINK_CONNECT_ARGS + --connectscript=RT1060_connect.scp + --reset= + --coreindex 0 + --cache disable + --no-packed) \ No newline at end of file diff --git a/targets/upload_method_cfg/redlink_cfgs/MIMXRT1062xxxxA.xml b/targets/upload_method_cfg/redlink_cfgs/MIMXRT1062xxxxA.xml new file mode 100644 index 0000000..80f9641 --- /dev/null +++ b/targets/upload_method_cfg/redlink_cfgs/MIMXRT1062xxxxA.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/targets/upload_method_cfg/redlink_cfgs/MIMXRT1062xxxxA_part.xml b/targets/upload_method_cfg/redlink_cfgs/MIMXRT1062xxxxA_part.xml new file mode 100644 index 0000000..14417fd --- /dev/null +++ b/targets/upload_method_cfg/redlink_cfgs/MIMXRT1062xxxxA_part.xml @@ -0,0 +1,2 @@ + + MIMXRT1062xxxxA MIMXRT1060 NXP Cortex-M7 Cortex-M diff --git a/tools/cmake/upload_methods/UploadMethodJLINK.cmake b/tools/cmake/upload_methods/UploadMethodJLINK.cmake index 198487f..4caf9f3 100644 --- a/tools/cmake/upload_methods/UploadMethodJLINK.cmake +++ b/tools/cmake/upload_methods/UploadMethodJLINK.cmake @@ -37,7 +37,8 @@ -JTAGConf -1,-1 -AutoConnect 1 -ExitOnError - -CommandFile ${COMMAND_FILE_PATH}) + -CommandFile ${COMMAND_FILE_PATH} + VERBATIM) add_dependencies(flash-${TARGET_NAME} ${TARGET_NAME}) @@ -58,4 +59,5 @@ -LocalhostOnly -noIR -port ${GDB_PORT} - USES_TERMINAL) + USES_TERMINAL + VERBATIM)