diff --git a/targets/TARGET_STM/TARGET_STM32F3/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/PeripheralNames.h new file mode 100644 index 0000000..8063fcd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/PeripheralNames.h @@ -0,0 +1,125 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, +#if defined ADC3_BASE + ADC_3 = (int)ADC3_BASE, +#endif +#if defined ADC4_BASE + ADC_4 = (int)ADC4_BASE +#endif +} ADCName; + +typedef enum { + DAC_1 = (int)DAC1_BASE, +#if defined DAC2_BASE + DAC_2 = (int)DAC2_BASE +#endif +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, +#if defined UART4_BASE + UART_4 = (int)UART4_BASE, +#endif +#if defined UART5_BASE + UART_5 = (int)UART5_BASE +#endif +} UARTName; + +#define DEVICE_SPI_COUNT 4 +typedef enum { + SPI_1 = (int)SPI1_BASE, +#if defined SPI2_BASE + SPI_2 = (int)SPI2_BASE, +#endif +#if defined SPI3_BASE + SPI_3 = (int)SPI3_BASE, +#endif +#if defined SPI4_BASE + SPI_4 = (int)SPI4_BASE +#endif +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, +#if defined I2C2_BASE + I2C_2 = (int)I2C2_BASE, +#endif +#if defined I2C3_BASE + I2C_3 = (int)I2C3_BASE +#endif +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, +#if defined TIM4_BASE + PWM_4 = (int)TIM4_BASE, +#endif +#if defined TIM8_BASE + PWM_8 = (int)TIM8_BASE, +#endif + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE, +#if defined TIM20_BASE + PWM_20 = (int)TIM20_BASE +#endif +} PWMName; + +typedef enum { + CAN_1 = (int)CAN_BASE +} CANName; + +#if defined USB_BASE +typedef enum { + USB_FS = (int)USB_BASE, +} USBName; +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f303xe.h b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f303xe.h index 2a0fcc0..61fa696 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f303xe.h +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f303xe.h @@ -66,8 +66,8 @@ #define __NVIC_PRIO_BITS 4U /*!< STM32F303xE devices use 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #ifndef __FPU_PRESENT -#define __FPU_PRESENT 1U /*!< STM32F303xE devices provide an FPU */ -#endif +#define __FPU_PRESENT 1U /*!< STM32F303x8 devices provide an FPU */ +#endif /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h index fae06eb..f0d0ed1 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/stm32f3xx.h @@ -96,7 +96,7 @@ /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC, STM32F373R8, STM32F373RB, STM32F373RC, STM32F373V8, STM32F373VB and STM32F373VC Devices */ -#define STM32F334x8 /*!< STM32F334K4, STM32F334K6, STM32F334K8, + /* #define STM32F334x8 */ /*!< STM32F334K4, STM32F334K6, STM32F334K8, STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */ /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */ @@ -115,7 +115,7 @@ In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ -#define USE_HAL_DRIVER + /*#define USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/system_stm32f3xx.h b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/system_stm32f3xx.h index da033e5..6e63952 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/system_stm32f3xx.h +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/CMSIS/system_stm32f3xx.h @@ -102,8 +102,6 @@ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); -extern void SetSysClock(void); - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_def.h index b061f99..0bafe98 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/STM32F3xx_HAL_Driver/stm32f3xx_hal_def.h @@ -45,7 +45,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f3xx.h" #if defined USE_LEGACY -#include "stm32_hal_legacy.h" // MBED patch +#include "Legacy/stm32_hal_legacy.h" #endif #include diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/stm32f3xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/stm32f3xx_hal_conf.h index f8bfcad..3c9e4f8 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/stm32f3xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/stm32f3xx_hal_conf.h @@ -312,19 +312,7 @@ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - //#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - //void assert_failed(char* file, uint32_t line); -// MBED patch. All targets use same stm32_assert.h -#include "stm32_assert.h" +#include "stm32_assert.h" // MBED patch #else #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/system_stm32f3xx.c b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/system_stm32f3xx.c index 45853d1..b10e04c 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/system_stm32f3xx.c +++ b/targets/TARGET_STM/TARGET_STM32F3/STM32Cube_FW/system_stm32f3xx.c @@ -159,10 +159,6 @@ * @{ */ -/*+ MBED */ -#if 0 -/*- MBED */ - /** * @brief Setup the microcontroller system * Initialize the FPU setting, vector table location and the PLL configuration is reset. @@ -204,14 +200,11 @@ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#include "nvic_addr.h" // MBED + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED #endif } -/*+ MBED */ -#endif -/*- MBED */ - /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/startup_stm32f302x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/startup_stm32f302x8.S index 848f7c0..9a38698 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/startup_stm32f302x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/startup_stm32f302x8.S @@ -1,4 +1,4 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f302x8.s ;* Author : MCD Application Team ;* Description : STM32F302x6/x8 devices vector table for MDK-ARM toolchain. @@ -46,9 +46,9 @@ EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -320,4 +320,11 @@ ENDP ALIGN - END + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/stm32f302x8.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/stm32f302x8.sct index ec6a59a..3313512 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/stm32f302x8.sct +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_ARM/stm32f302x8.sct @@ -1,58 +1,57 @@ #! armcc -E ; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START #endif -#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif -; STM32F302R8: 64KB FLASH + 16KB SRAM -LR_IROM1 0x08000000 0x10000 { ; load region size_region +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif - ER_IROM1 0x08000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) } - ; 98 vectors (16 core + 82 peripheral) * 4 bytes = 392 bytes to reserve (0x188) - RW_IRAM1 (0x20000000+0x188) (0x4000-0x188-Stack_Size) { ; RW data - .ANY (+RW +ZI) + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) } - ARM_LIB_STACK (0x20000000+0x4000) EMPTY -Stack_Size { ; stack + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down } } - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/STM32F302X8.ld b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/STM32F302X8.ld index 74381b8..5f47993 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/STM32F302X8.ld +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/STM32F302X8.ld @@ -1,22 +1,51 @@ /* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START #endif -STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K - RAM (xrw) : ORIGIN = 0x20000188, LENGTH = 16K - 0x188 +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end @@ -70,7 +99,7 @@ KEEP(*(.eh_frame*)) } > FLASH - .ARM.extab : + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -84,7 +113,7 @@ __etext = .; _sidata = .; - + .data : AT (__etext) { __data_start__ = .; @@ -105,7 +134,6 @@ KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); @@ -121,6 +149,19 @@ } > RAM + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + .bss : { . = ALIGN(8); @@ -132,13 +173,13 @@ __bss_end__ = .; _ebss = .; } > RAM - + .heap (COPY): { __end__ = .; - end = __end__; + PROVIDE(end = .); *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; __HeapLimit = .; } > RAM @@ -154,10 +195,9 @@ * size of stack_dummy section */ __StackTop = ORIGIN(RAM) + LENGTH(RAM); _estack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; PROVIDE(__stack = __StackTop); - + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.S index c6f594a..1fb8141 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.S @@ -13,7 +13,7 @@ * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** - * + * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, @@ -105,17 +105,8 @@ /* Call the clock system intitialization function.*/ bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main -/** - * Calling the crt0 'cold-start' entry point. There __libc_init_array is called - * and when existing hardware_init_hook() and software_init_hook() before - * starting main(). software_init_hook() is available and has to be called due - * to initializsation when using rtos. -*/ - bl _start + bl _start + bx lr LoopForever: b LoopForever diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/startup_stm32f302x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/startup_stm32f302x8.S index 2da7dc0..2e4e5af 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/startup_stm32f302x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/startup_stm32f302x8.S @@ -1,4 +1,4 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f302x8.s ;* Author : MCD Application Team ;* Description : STM32F302x6/STM32F302x8 devices vector table for EWARM toolchain. diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/stm32f302x8.icf b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/stm32f302x8.icf index 9520263..8754259 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/stm32f302x8.icf +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/TOOLCHAIN_IAR/stm32f302x8.icf @@ -1,33 +1,59 @@ -/* [ROM = 64kb = 0x10000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0800FFFF; +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ -/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000187; /*aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x20000188; -define symbol __region_RAM_end__ = 0x20003FFF; +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -/* Memory regions */ -define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; +define symbol VECTORS = 98; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; -/* Stack and Heap */ +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } -define symbol __size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; -define symbol __size_heap__ = 0x1000; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; -initialize by copy with packing = zeros { readwrite }; +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__intvec_start__ { readonly section .intvec }; +place at address mem: MBED_APP_START { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/cmsis_nvic.h index 37e0080..78d4dd0 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/cmsis_nvic.h @@ -1,41 +1,39 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

* - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ + ****************************************************************************** +*/ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -// STM32F302R8 -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187 -// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x10000 // 64 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x4000 // 16 KB +#endif + #define NVIC_NUM_VECTORS 98 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h deleted file mode 100644 index d0f3565..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/us_ticker_data.h deleted file mode 100644 index 043950a..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/us_ticker_data.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32f3xx.h" -#include "stm32f3xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM2 -#define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() - -#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h deleted file mode 100644 index 07f8807..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralNames.h +++ /dev/null @@ -1,81 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC1_BASE, - DAC_2 = (int)DAC2_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 1 -typedef enum { - SPI_1 = (int)SPI1_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_15 = (int)TIM15_BASE, - PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN_BASE -} CANName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c deleted file mode 100644 index cf58c1c..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/system_clock.c +++ /dev/null @@ -1,225 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC | 3- USE_PLL_HSI - * | (external 8 MHz clock) | (internal 8 MHz) - * | 2- USE_PLL_HSE_XTAL | - * | (external 8 MHz xtal) | - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * AHBCLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * APB1CLK (MHz) | 36 | 32 - *----------------------------------------------------------------------------- - * APB2CLK (MHz) | 72 | 64 - *----------------------------------------------------------------------------- - * USB capable | NO | NO - *----------------------------------------------------------------------------- - */ - - -#include "stm32f3xx.h" -#include "mbed_error.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and the PLL configuration is reset. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= 0x00000001U; - - /* Reset CFGR register */ - RCC->CFGR &= 0xF87FC00CU; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= 0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ - RCC->CFGR &= 0xFF80FFFFU; - - /* Reset PREDIV1[3:0] bits */ - RCC->CFGR2 &= 0xFFFFFFF0U; - - /* Reset USARTSW[1:0], I2CSW and TIMs bits */ - RCC->CFGR3 &= 0xFF00FCCCU; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000U; - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal - //else - // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/startup_stm32f303x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/startup_stm32f303x8.S index 9a3b3d4..4b5ebb4 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/startup_stm32f303x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/startup_stm32f303x8.S @@ -1,4 +1,4 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f303x8.s ;* Author : MCD Application Team ;* Description : STM32F303x6/x8 devices vector table for MDK-ARM toolchain. @@ -46,9 +46,9 @@ EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -307,6 +307,10 @@ ALIGN +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/stm32f303x8.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/stm32f303x8.sct index a279523..3313512 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/stm32f303x8.sct +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_ARM/stm32f303x8.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S index 9c204f4..77cd9f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S @@ -13,7 +13,7 @@ * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** - * + * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, @@ -105,17 +105,8 @@ /* Call the clock system intitialization function.*/ bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main -/** - * Calling the crt0 'cold-start' entry point. There __libc_init_array is called - * and when existing hardware_init_hook() and software_init_hook() before - * starting main(). software_init_hook() is available and has to be called due - * to initializsation when using rtos. -*/ - bl _start + bl _start + bx lr LoopForever: b LoopForever diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/startup_stm32f303x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/startup_stm32f303x8.S index 85be167..b9301cb 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/startup_stm32f303x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/startup_stm32f303x8.S @@ -1,4 +1,4 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f303x8.s ;* Author : MCD Application Team ;* Description : STM32F303x6/STM32F303x8 devices vector table for EWARM toolchain. diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/stm32f303x8.icf b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/stm32f303x8.icf index ed9368a..8754259 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/stm32f303x8.icf +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TOOLCHAIN_IAR/stm32f303x8.icf @@ -32,7 +32,7 @@ } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h deleted file mode 100644 index d0f3565..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/system_clock.c new file mode 100644 index 0000000..6d51e49 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/system_clock.c @@ -0,0 +1,173 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC | 3- USE_PLL_HSI + * | (external 8 MHz clock) | (internal 8 MHz) + * | 2- USE_PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 36 | 32 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 72 | 64 + *----------------------------------------------------------------------------- + * USB capable | NO | NO + *----------------------------------------------------------------------------- + */ + + +#include "stm32f3xx.h" +#include "mbed_error.h" + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + { + error("SetSysClock failed\n"); + } + } + } + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/us_ticker_data.h deleted file mode 100644 index 043950a..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/us_ticker_data.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32f3xx.h" -#include "stm32f3xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM2 -#define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() - -#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h deleted file mode 100644 index d0f3565..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/us_ticker_data.h deleted file mode 100644 index 043950a..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/us_ticker_data.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32f3xx.h" -#include "stm32f3xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM2 -#define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() - -#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h deleted file mode 100644 index 58f7521..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h +++ /dev/null @@ -1,96 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE, - ADC_4 = (int)ADC4_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 4 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_15 = (int)TIM15_BASE, - PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE, - PWM_20 = (int)TIM20_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN_BASE -} CANName; - -typedef enum { - USB_FS = (int)USB_BASE, -} USBName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c deleted file mode 100644 index 16aecba..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/system_clock.c +++ /dev/null @@ -1,222 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) - * | 3- USE_PLL_HSI (internal 8 MHz) - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 72 - * AHBCLK (MHz) | 72 - * APB1CLK (MHz) | 36 - * APB2CLK (MHz) | 72 - * USB capable | YES - *----------------------------------------------------------------------------- - */ - - -#include "stm32f3xx.h" -#include "mbed_error.h" - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and the PLL configuration is reset. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= 0x00000001U; - - /* Reset CFGR register */ - RCC->CFGR &= 0xF87FC00CU; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= 0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ - RCC->CFGR &= 0xFF80FFFFU; - - /* Reset PREDIV1[3:0] bits */ - RCC->CFGR2 &= 0xFFFFFFF0U; - - /* Reset USARTSW[1:0], I2CSW and TIMs bits */ - RCC->CFGR3 &= 0xFF00FCCCU; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000U; -} - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - - /* Output clock on MCO2 pin(PC9) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal - //else - // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h deleted file mode 100644 index 58f7521..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h +++ /dev/null @@ -1,96 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE, - ADC_3 = (int)ADC3_BASE, - ADC_4 = (int)ADC4_BASE -} ADCName; - -typedef enum { - DAC_1 = (int)DAC_BASE -} DACName; - -typedef enum { - UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, - UART_3 = (int)USART3_BASE, - UART_4 = (int)UART4_BASE, - UART_5 = (int)UART5_BASE -} UARTName; - -#define DEVICE_SPI_COUNT 4 -typedef enum { - SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE, - SPI_3 = (int)SPI3_BASE, - SPI_4 = (int)SPI4_BASE -} SPIName; - -typedef enum { - I2C_1 = (int)I2C1_BASE, - I2C_2 = (int)I2C2_BASE, - I2C_3 = (int)I2C3_BASE -} I2CName; - -typedef enum { - PWM_1 = (int)TIM1_BASE, - PWM_2 = (int)TIM2_BASE, - PWM_3 = (int)TIM3_BASE, - PWM_4 = (int)TIM4_BASE, - PWM_8 = (int)TIM8_BASE, - PWM_15 = (int)TIM15_BASE, - PWM_16 = (int)TIM16_BASE, - PWM_17 = (int)TIM17_BASE, - PWM_20 = (int)TIM20_BASE -} PWMName; - -typedef enum { - CAN_1 = (int)CAN_BASE -} CANName; - -typedef enum { - USB_FS = (int)USB_BASE, -} USBName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c deleted file mode 100644 index a3e00a5..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/system_clock.c +++ /dev/null @@ -1,235 +0,0 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -/** - * This file configures the system clock as follows: - *----------------------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) - * | 3- USE_PLL_HSI (internal 8 MHz) - *----------------------------------------------------------------------------- - * SYSCLK(MHz) | 72 - * AHBCLK (MHz) | 72 - * APB1CLK (MHz) | 36 - * APB2CLK (MHz) | 72 - * USB capable | YES - *----------------------------------------------------------------------------- - */ - - -#include "stm32f3xx.h" -#include "mbed_error.h" - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - -// clock source is selected with CLOCK_SOURCE in json config -#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) -#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) -#define USE_PLL_HSI 0x2 // Use HSI internal clock - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -uint8_t SetSysClock_PLL_HSE(uint8_t bypass); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -uint8_t SetSysClock_PLL_HSI(void); -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and the PLL configuration is reset. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ -#endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= 0x00000001U; - - /* Reset CFGR register */ - RCC->CFGR &= 0xF87FC00CU; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= 0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */ - RCC->CFGR &= 0xFF80FFFFU; - - /* Reset PREDIV1[3:0] bits */ - RCC->CFGR2 &= 0xFFFFFFF0U; - - /* Reset USARTSW[1:0], I2CSW and TIMs bits */ - RCC->CFGR3 &= 0xFF00FCCCU; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000U; - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ - -void SetSysClock(void) -{ -#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) - /* 1- Try to start with HSE and external clock */ - if (SetSysClock_PLL_HSE(1) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) - /* 2- If fail try to start with HSE and external xtal */ - if (SetSysClock_PLL_HSE(0) == 0) -#endif - { -#if ((CLOCK_SOURCE) & USE_PLL_HSI) - /* 3- If fail start with HSI clock */ - if (SetSysClock_PLL_HSI() == 0) -#endif - { - { - error("SetSysClock failed\n"); - } - } - } - } - - /* Output clock on MCO2 pin(PC9) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); -} - -#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSE(uint8_t bypass) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; - - /* Enable HSE oscillator and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ - } else { - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ - } - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal - //else - // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ - -#if ((CLOCK_SOURCE) & USE_PLL_HSI) -/******************************************************************************/ -/* PLL (clocked by HSI) used as System clock source */ -/******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) -{ - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; - - /* Enable HSI oscillator and activate PLL with HSI as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSEState = RCC_HSE_OFF; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9) - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - - /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ - RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz - - return 1; // OK -} -#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/startup_stm32f303xe.S index f38b1ae..61653d7 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/startup_stm32f303xe.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/startup_stm32f303xe.S @@ -1,4 +1,4 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f303xe.s ;* Author : MCD Application Team ;* Description : STM32F303xE devices vector table for MDK-ARM toolchain. @@ -46,9 +46,9 @@ EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -372,6 +372,10 @@ ALIGN - END +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/stm32f303xe.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/stm32f303xe.sct index 92b6e75..3313512 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/stm32f303xe.sct +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_ARM/stm32f303xe.sct @@ -25,13 +25,13 @@ #define MBED_APP_SIZE MBED_ROM_SIZE #endif -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif #endif /* Round up VECTORS_SIZE to 8 bytes */ @@ -55,4 +55,3 @@ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down } } - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S index 1790b28..0d6304b 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S @@ -13,7 +13,7 @@ * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** - * + * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, @@ -105,17 +105,8 @@ /* Call the clock system intitialization function.*/ bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main -/** - * Calling the crt0 'cold-start' entry point. There __libc_init_array is called - * and when existing hardware_init_hook() and software_init_hook() before - * starting main(). software_init_hook() is available and has to be called due - * to initializsation when using rtos. -*/ - bl _start + bl _start + bx lr LoopForever: b LoopForever diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/startup_stm32f303xe.S index 38166c2..bd339fe 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/startup_stm32f303xe.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/startup_stm32f303xe.S @@ -1,4 +1,4 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f303xe.s ;* Author : MCD Application Team ;* Description : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/stm32f303xe.icf b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/stm32f303xe.icf index 4d5c7d7..cc624d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/stm32f303xe.icf +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TOOLCHAIN_IAR/stm32f303xe.icf @@ -32,7 +32,7 @@ } if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools + /* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h deleted file mode 100644 index d0f3565..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/system_clock.c new file mode 100644 index 0000000..0587357 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/system_clock.c @@ -0,0 +1,183 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 8 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 72 + * AHBCLK (MHz) | 72 + * APB1CLK (MHz) | 36 + * APB2CLK (MHz) | 72 + * USB capable | YES + *----------------------------------------------------------------------------- + */ + + +#include "stm32f3xx.h" +#include "mbed_error.h" + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + { + error("SetSysClock failed\n"); + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz/1 * 9) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/us_ticker_data.h deleted file mode 100644 index 043950a..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/us_ticker_data.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32f3xx.h" -#include "stm32f3xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM2 -#define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() - -#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/startup_stm32f334x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/startup_stm32f334x8.S index ba5a68d..8193226 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/startup_stm32f334x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/startup_stm32f334x8.S @@ -1,4 +1,4 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f334x8.s ;* Author : MCD Application Team ;* Description : STM32F334x4/x6/x8 devices vector table for MDK-ARM toolchain. @@ -46,9 +46,9 @@ EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler @@ -320,6 +320,11 @@ ENDP ALIGN - END + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + + END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/stm32f334x8.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/stm32f334x8.sct index 89bbb6f..3313512 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/stm32f334x8.sct +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_ARM/stm32f334x8.sct @@ -1,58 +1,57 @@ #! armcc -E ; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2014, STMicroelectronics -; All rights reserved. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) -# if defined(MBED_BOOT_STACK_SIZE) -# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE -# else -# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 -# endif +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START #endif -#define Stack_Size MBED_CONF_TARGET_BOOT_STACK_SIZE +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif -; STM32F334x8: 64KB FLASH (0x10000) + 12KB SRAM (0x3000) -LR_IROM1 0x08000000 0x10000 { ; load region size_region +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ +#if defined(MBED_BOOT_STACK_SIZE) +#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE +#else +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif +#endif - ER_IROM1 0x08000000 0x10000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) } - ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM - RW_IRAM1 (0x20000000+0x188) (0x3000-0x188-Stack_Size) { ; RW data - .ANY (+RW +ZI) + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) } - ARM_LIB_STACK (0x20000000+0x3000) EMPTY -Stack_Size { ; stack + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down } } - diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/STM32F334X8.ld b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/STM32F334X8.ld index c1c63b8..5f47993 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/STM32F334X8.ld +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/STM32F334X8.ld @@ -1,23 +1,51 @@ /* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ -#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) - #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START #endif -STACK_SIZE = MBED_CONF_TARGET_BOOT_STACK_SIZE; +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64K - CCMRAM (rw) : ORIGIN = 0x10000000, LENGTH = 4K - RAM (xrw) : ORIGIN = 0x20000188, LENGTH = 12K - 0x0188 +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE } /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end @@ -48,6 +76,7 @@ { KEEP(*(.isr_vector)) *(.text*) + KEEP(*(.init)) KEEP(*(.fini)) @@ -84,7 +113,7 @@ __etext = .; _sidata = .; - + .data : AT (__etext) { __data_start__ = .; @@ -105,7 +134,6 @@ KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); @@ -121,6 +149,19 @@ } > RAM + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + .bss : { . = ALIGN(8); @@ -136,9 +177,9 @@ .heap (COPY): { __end__ = .; - end = __end__; + PROVIDE(end = .); *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE; __HeapLimit = .; } > RAM @@ -154,7 +195,7 @@ * size of stack_dummy section */ __StackTop = ORIGIN(RAM) + LENGTH(RAM); _estack = __StackTop; - __StackLimit = __StackTop - STACK_SIZE; + __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE; PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S index 25fdefe..3f1aa84 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S @@ -13,7 +13,7 @@ * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** - * + * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, @@ -105,17 +105,8 @@ /* Call the clock system intitialization function.*/ bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main -/** - * Calling the crt0 'cold-start' entry point. There __libc_init_array is called - * and when existing hardware_init_hook() and software_init_hook() before - * starting main(). software_init_hook() is available and has to be called due - * to initializsation when using rtos. -*/ - bl _start + bl _start + bx lr LoopForever: b LoopForever diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/startup_stm32f334x8.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/startup_stm32f334x8.S index 863aba8..9e5a202 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/startup_stm32f334x8.S +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/startup_stm32f334x8.S @@ -1,4 +1,4 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** ;* File Name : startup_stm32f334x8.s ;* Author : MCD Application Team ;* Description : STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for EWARM toolchain. diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/stm32f334x8.icf b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/stm32f334x8.icf index e07b3ce..8754259 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/stm32f334x8.icf +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/TOOLCHAIN_IAR/stm32f334x8.icf @@ -1,36 +1,59 @@ -/* [ROM = 64kb = 0x10000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0800FFFF; +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ -/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ -define symbol __NVIC_start__ = 0x20000000; -define symbol __NVIC_end__ = 0x20000187; /*aligned on 8 bytes */ -define symbol __region_RAM_start__ = 0x20000188; -define symbol __region_RAM_end__ = 0x20002FFF; -define symbol __region_CCMRAM_start__ = 0x10000000; -define symbol __region_CCMRAM_end__ = 0x10000FFF; +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ -/* Memory regions */ -define memory mem with size = 4G; -define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; -define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; -define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__]; +define symbol VECTORS = 98; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; -/* Stack and Heap */ +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; } -define symbol __size_cstack__ = MBED_CONF_TARGET_BOOT_STACK_SIZE; -define symbol __size_heap__ = 0xC00; -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block STACKHEAP with fixed order { block HEAP, block CSTACK }; -initialize by copy with packing = zeros { readwrite }; +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; do not initialize { section .noinit }; -place at address mem:__intvec_start__ { readonly section .intvec }; +place at address mem: MBED_APP_START { readonly section .intvec }; place in ROM_region { readonly }; -place in RAM_region { readwrite, block STACKHEAP }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/cmsis_nvic.h index 796f87c..78d4dd0 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/cmsis_nvic.h @@ -1,41 +1,39 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

* - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ + ****************************************************************************** +*/ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -// STM32F334R8 -// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F -// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187 -// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x10000 // 64 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x4000 // 16 KB +#endif + #define NVIC_NUM_VECTORS 98 -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h deleted file mode 100644 index d0f3565..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/objects.h +++ /dev/null @@ -1,63 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - IRQn_Type irq_n; - uint32_t irq_index; - uint32_t event; - PinName pin; -}; - -struct port_s { - PortName port; - uint32_t mask; - PinDirection direction; - __IO uint32_t *reg_in; - __IO uint32_t *reg_out; -}; - -#include "common_objects.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/us_ticker_data.h deleted file mode 100644 index 043950a..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/us_ticker_data.h +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef __US_TICKER_DATA_H -#define __US_TICKER_DATA_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "stm32f3xx.h" -#include "stm32f3xx_ll_tim.h" -#include "cmsis_nvic.h" - -#define TIM_MST TIM2 -#define TIM_MST_IRQ TIM2_IRQn -#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() -#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() - -#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() -#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() - -#define TIM_MST_BIT_WIDTH 32 // 16 or 32 - -#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) - - -#ifdef __cplusplus -} -#endif - -#endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h b/targets/TARGET_STM/TARGET_STM32F3/common_objects.h deleted file mode 100644 index 6f960dd..0000000 --- a/targets/TARGET_STM/TARGET_STM32F3/common_objects.h +++ /dev/null @@ -1,155 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_COMMON_OBJECTS_H -#define MBED_COMMON_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" -#include "stm32f3xx_ll_usart.h" -#include "stm32f3xx_ll_tim.h" -#include "stm32f3xx_ll_pwr.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct pwmout_s { - PWMName pwm; - PinName pin; - uint32_t prescaler; - uint32_t period; - uint32_t pulse; - uint8_t channel; - uint8_t inverted; -}; - -struct spi_s { - SPI_HandleTypeDef handle; - IRQn_Type spiIRQ; - SPIName spi; - PinName pin_miso; - PinName pin_mosi; - PinName pin_sclk; - PinName pin_ssel; -#if DEVICE_SPI_ASYNCH - uint32_t event; - uint8_t transfer_type; -#endif -}; - -struct serial_s { - UARTName uart; - int index; // Used by irq - uint32_t baudrate; - uint32_t databits; - uint32_t stopbits; - uint32_t parity; - PinName pin_tx; - PinName pin_rx; -#if DEVICE_SERIAL_ASYNCH - uint32_t events; -#endif -#if DEVICE_SERIAL_FC - uint32_t hw_flow_ctl; - PinName pin_rts; - PinName pin_cts; -#endif -}; - -struct i2c_s { - /* The 1st 2 members I2CName i2c - * and I2C_HandleTypeDef handle should - * be kept as the first members of this struct - * to ensure i2c_get_obj to work as expected - */ - I2CName i2c; - I2C_HandleTypeDef handle; - uint8_t index; - int hz; - PinName sda; - PinName scl; - int sda_func; - int scl_func; - IRQn_Type event_i2cIRQ; - IRQn_Type error_i2cIRQ; - uint32_t XferOperation; - volatile uint8_t event; - volatile int pending_start; -#if DEVICE_I2CSLAVE - uint8_t slave; - volatile uint8_t pending_slave_tx_master_rx; - volatile uint8_t pending_slave_rx_maxter_tx; -#endif -#if DEVICE_I2C_ASYNCH - uint32_t address; - uint8_t stop; - uint8_t available_events; -#endif -}; - -struct dac_s { - DACName dac; - PinName pin; - uint32_t channel; - DAC_HandleTypeDef handle; -}; - -struct analogin_s { - ADC_HandleTypeDef handle; - PinName pin; - uint8_t channel; -}; - -#if DEVICE_CAN -struct can_s { - CAN_HandleTypeDef CanHandle; - int index; - int hz; -}; -#endif - -#if DEVICE_FLASH -struct flash_s { - /* nothing to be stored for now */ - uint32_t dummy; -}; -#endif - -#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 7 || (width) == 8 || (width) == 16 || (width) == 32) - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/objects.h b/targets/TARGET_STM/TARGET_STM32F3/objects.h new file mode 100644 index 0000000..e066260 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/objects.h @@ -0,0 +1,171 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" + +#include "stm32f3xx_ll_usart.h" +#include "stm32f3xx_ll_tim.h" +#include "stm32f3xx_ll_pwr.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t prescaler; + uint32_t period; + uint32_t pulse; + uint8_t channel; + uint8_t inverted; +}; + +struct spi_s { + SPI_HandleTypeDef handle; + IRQn_Type spiIRQ; + SPIName spi; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; +#if DEVICE_SPI_ASYNCH + uint32_t event; + uint8_t transfer_type; +#endif +}; + +struct serial_s { + UARTName uart; + int index; // Used by irq + uint32_t baudrate; + uint32_t databits; + uint32_t stopbits; + uint32_t parity; + PinName pin_tx; + PinName pin_rx; +#if DEVICE_SERIAL_ASYNCH + uint32_t events; +#endif +#if DEVICE_SERIAL_FC + uint32_t hw_flow_ctl; + PinName pin_rts; + PinName pin_cts; +#endif +}; + +struct i2c_s { + /* The 1st 2 members I2CName i2c + * and I2C_HandleTypeDef handle should + * be kept as the first members of this struct + * to ensure i2c_get_obj to work as expected + */ + I2CName i2c; + I2C_HandleTypeDef handle; + uint8_t index; + int hz; + PinName sda; + PinName scl; + int sda_func; + int scl_func; + IRQn_Type event_i2cIRQ; + IRQn_Type error_i2cIRQ; + uint32_t XferOperation; + volatile uint8_t event; + volatile int pending_start; +#if DEVICE_I2CSLAVE + uint8_t slave; + volatile uint8_t pending_slave_tx_master_rx; + volatile uint8_t pending_slave_rx_maxter_tx; +#endif +#if DEVICE_I2C_ASYNCH + uint32_t address; + uint8_t stop; + uint8_t available_events; +#endif +}; + +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; + DAC_HandleTypeDef handle; +}; + +struct analogin_s { + ADC_HandleTypeDef handle; + PinName pin; + uint8_t channel; +}; + +#if DEVICE_CAN +struct can_s { + CAN_HandleTypeDef CanHandle; + int index; + int hz; +}; +#endif + +#if DEVICE_FLASH +struct flash_s { + /* nothing to be stored for now */ + uint32_t dummy; +}; +#endif + +#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 7 || (width) == 8 || (width) == 16 || (width) == 32) + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h new file mode 100644 index 0000000..043950a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h @@ -0,0 +1,46 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __US_TICKER_DATA_H +#define __US_TICKER_DATA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32f3xx.h" +#include "stm32f3xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() + +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() + +#define TIM_MST_BIT_WIDTH 32 // 16 or 32 + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + + +#ifdef __cplusplus +} +#endif + +#endif // __US_TICKER_DATA_H + diff --git a/targets/targets.json b/targets/targets.json index 2bb0dee..e57331d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1418,14 +1418,22 @@ "LPTICKER" ] }, - "NUCLEO_F303K8": { + "MCU_STM32F303x8": { "inherits": [ "MCU_STM32F3" ], + "public": false, "c_lib": "small", "extra_labels_add": [ - "STM32F303x8", - "STM32F303K8" + "STM32F303x8" + ], + "macros_add": [ + "STM32F303x8" + ] + }, + "NUCLEO_F303K8": { + "inherits": [ + "MCU_STM32F303x8" ], "overrides": { "clock_source": "USE_PLL_HSI", @@ -1436,51 +1444,50 @@ ], "device_name": "STM32F303K8" }, - "NUCLEO_F303RE": { + "MCU_STM32F303xE": { "inherits": [ "MCU_STM32F3" ], - "c_lib": "small", - "supported_form_factors": [ - "ARDUINO", - "MORPHO" - ], + "public": false, "extra_labels_add": [ - "STM32F303xE", - "STM32F303RE" + "STM32F303xE" + ], + "macros_add": [ + "STM32F303xE" ], "components_add": [ "FLASHIAP" ], - "detect_code": [ - "0745" - ], "device_has_add": [ "SERIAL_ASYNCH", "FLASH", "MPU" - ], - "device_name": "STM32F303RE" + ] }, - "NUCLEO_F303ZE": { + "NUCLEO_F303RE": { "inherits": [ - "MCU_STM32F3" + "MCU_STM32F303xE" ], "supported_form_factors": [ "ARDUINO", "MORPHO" ], - "extra_labels_add": [ - "STM32F303xE", - "STM32F303ZE" + "detect_code": [ + "0745" + ], + "device_name": "STM32F303RE" + }, + "NUCLEO_F303ZE": { + "inherits": [ + "MCU_STM32F303xE" + ], + "supported_form_factors": [ + "ARDUINO", + "MORPHO" ], "detect_code": [ "0747" ], - "device_has_add": [ - "FLASH", - "MPU" - ], "device_name": "STM32F303ZE" }, "MCU_STM32F4": {