diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt index 2b43027..45f860e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/CMakeLists.txt @@ -28,10 +28,10 @@ sleep.c trng_api.c us_ticker.c - fsl_clock_config.c + clock_config.c PeripheralPins.c pinmap.c - specific.c + mimxrt_clock_adjustment.c lpm.c mbed_overrides.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralPins.c index 6c867355..0712820 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/PeripheralPins.c @@ -17,6 +17,39 @@ #include "PeripheralPins.h" +// Note on MIMXRT pin functions: +// The MIMXRT's pin function system is pretty dang complicated, and Mbed's pin function data for this chip +// (the 3rd element in each pinmap entry) has to be pretty complicated to match. +// It's a 32-bit bitfield with the following format: +// __________________________________________________________________________________________________ +// | | | | | +// | Daisy Reg Value (bits 19:16) | Daisy Register (bits 15:4) | SION (bit 3) | Mux Mode (bits 2:0) | +// |_______________________________|____________________________|______________|_____________________| +// +// Mux mode: +// This value gets written to the IOMUXC_SW_MUX_CTL_PAD_xxx.MUX_MODE bitfield for the given pin. +// It's a number from 0 to 7 that selects the possible mux mode. +// See Table 10-1 in the datasheet for the possible muxing options +// +// SION: +// This is a somewhat unusual setting used to "force the pin mode to input regardless of MUX_MODE +// functionality". It's a setting needed for certain peripherals to work that use pins in input mode. +// I'm not quite sure of the logic for when to use it... +// +// Daisy Register: +// If nonzero, this field specifies the offset for a "daisy chain register" to use when setting up the pin +// function. "Daisy chain" is actually kinda a misnomer, this register is used to select which of multiple +// pin options a peripheral is connected to, it doesn't daisy chain pins together. It would be better to +// call it "top-level mux register" or something. +// +// The daisy register is specified as an offset relative to the IOMUXC peripheral base. For example, for the +// LPI2C3 peripheral, the daisy chain register for SCL is IOMUXC_LPI2C3_SDA_SELECT_INPUT. So, since the address +// of that register is IOMUXC + 0x4E0, I'd put 0x4E0 as the daisy register. +// +// Daisy Reg Value: +// Numeric option to select in the above daisy register, if the address is given. +// + /************RTC***************/ const PinMap PinMap_RTC[] = { {NC, OSC32KCLK, 0}, @@ -62,15 +95,15 @@ /************UART***************/ const PinMap PinMap_UART_TX[] = { {GPIO_AD_B0_12, UART_1, 2}, - {GPIO_AD_B1_06, UART_3, 2}, - {GPIO_AD_B0_02, UART_6, 2}, + {GPIO_AD_B1_06, UART_3, ((0 << DAISY_REG_VALUE_SHIFT) | (0x53C << DAISY_REG_SHIFT) | 2)}, + {GPIO_AD_B0_02, UART_6, ((1 << DAISY_REG_VALUE_SHIFT) | (0x554 << DAISY_REG_SHIFT) | 2)}, {NC , NC , 0} }; const PinMap PinMap_UART_RX[] = { {GPIO_AD_B0_13, UART_1, 2}, - {GPIO_AD_B1_07, UART_3, 2}, - {GPIO_AD_B0_03, UART_6, 2}, + {GPIO_AD_B1_07, UART_3, ((0 << DAISY_REG_VALUE_SHIFT) | (0x538 << DAISY_REG_SHIFT) | 2)}, + {GPIO_AD_B0_03, UART_6, ((1 << DAISY_REG_VALUE_SHIFT) | (0x550 << DAISY_REG_SHIFT) | 2)}, {NC , NC , 0} }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c index a2c0267..e4643b7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/TARGET_1050_EVK/xip/evkbimxrt1050_sdram_ini_dcd.c @@ -238,9 +238,9 @@ 0x40, 0x1F, 0x82, 0xA8, 0x00, 0x01, 0x10, 0xF9, /* #1.95, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, - /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x30524, size: 4 */ + /* #1.96, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, - /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x6030524, size: 4 */ + /* #1.97, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, /* #1.98, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/bootdata.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/bootdata.c index 237a715..3c0b2ed 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/bootdata.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_TEENSY_4X/bootdata.c @@ -1,15 +1,18 @@ + // This file is adapted from bootdata.c in the Teensy4 Arduino core. // https://github.com/PaulStoffregen/cores/blob/a2368ad57e9470608a234d942c55a2278c6cd72b/teensy4/bootdata.c // The only changes made were: // - Section names had to be modified to match what is expected by Mbed's linker script. // - #define names had to be modified to match Mbed -// - _flashimagelen replaced with __USED_FLASH_END +// - _flashimagelen replaced with __USED_FLASH_SIZE // - ResetHandler replaced with Reset_Handler /* Teensyduino Core Library * http://www.pjrc.com/teensy/ * Copyright (c) 2017 PJRC.COM, LLC. * + * SPDX-License-Identifier: MIT + * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including @@ -40,14 +43,14 @@ extern void Reset_Handler(void); extern unsigned long _estack; -extern unsigned long __USED_FLASH_END; +extern unsigned long __USED_FLASH_SIZE; __attribute__ ((section(".boot_hdr.boot_data"), used)) const uint32_t BootData[3] = { 0x60000000, - (uint32_t)&__USED_FLASH_END, + (uint32_t)&__USED_FLASH_SIZE, 0 }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/clock_config.c new file mode 100644 index 0000000..59bc5eb --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/clock_config.c @@ -0,0 +1,1254 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 13.0.1 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ +} + +/******************************************************************************* + ********************* Configuration BOARD_ClockFullSpeed ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_ClockFullSpeed +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 528 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 132 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.056 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '44', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_ClockFullSpeed configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_ClockFullSpeed = + { + .loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_ClockFullSpeed = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_ClockFullSpeed = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_ClockFullSpeed configuration + ******************************************************************************/ +void BOARD_ClockFullSpeed(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_ClockFullSpeed); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_ClockFullSpeed); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_ClockFullSpeed); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_CLOCKFULLSPEED_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_ClockOverdrive ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_ClockOverdrive +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_ClockOverdrive configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_ClockOverdrive = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_ClockOverdrive = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_ClockOverdrive = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_ClockOverdrive configuration + ******************************************************************************/ +void BOARD_ClockOverdrive(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 1); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_ClockOverdrive); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_ClockOverdrive); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_ClockOverdrive); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_CLOCKOVERDRIVE_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_ClockLowPower *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_ClockLowPower +description: Clocks the MIMRT using the lowest possible power settings (core runs at 24MHz) +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 2 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 12 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 12 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 12 MHz} +- {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz} +- {id: LVDS1_CLK.outFreq, value: 24 MHz} +- {id: MQS_MCLK.outFreq, value: 3 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 12 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI1_MCLK1.outFreq, value: 3 MHz} +- {id: SAI1_MCLK2.outFreq, value: 3 MHz} +- {id: SAI1_MCLK3.outFreq, value: 1.5 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI2_MCLK1.outFreq, value: 3 MHz} +- {id: SAI2_MCLK3.outFreq, value: 1.5 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 3 MHz} +- {id: SAI3_MCLK1.outFreq, value: 3 MHz} +- {id: SAI3_MCLK3.outFreq, value: 1.5 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 4 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz} +settings: +- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true} +- {id: CCM.IPG_PODF.scale, value: '2', locked: true} +- {id: CCM.PERIPH_CLK2_SEL.sel, value: XTALOSC24M.OSC_CLK} +- {id: CCM.PERIPH_CLK_SEL.sel, value: CCM.PERIPH_CLK2_PODF} +- {id: CCM.SEMC_PODF.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1'} +- {id: CCM_ANALOG.PLL2.num, value: '0'} +- {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_SYS_POWERDOWN_CFG, value: 'Yes'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_ClockLowPower configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_ClockLowPower configuration + ******************************************************************************/ +void BOARD_ClockLowPower(void) +{ + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 1); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 0); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 0); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 0); +#endif + /* Disable CSI clock gate. */ + CLOCK_DisableClock(kCLOCK_Csi); + /* Set CSI_PODF. */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 1); + /* Set Csi clock source. */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 3); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable LCDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_LcdPixel); + /* Set LCDIF_PRED. */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); + /* Set LCDIF_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); + /* Set Lcdif pre clock source. */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* DeInit ARM PLL. */ + CLOCK_DeinitArmPll(); + /* Bypass ARM PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllArm, 1); + /* Enable ARM PLL output. */ + CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_ENABLE_MASK; + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* DeInit System PLL. */ + CLOCK_DeinitSysPll(); + /* Bypass System PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllSys, 1); + /* Enable System PLL output. */ + CCM_ANALOG->PLL_SYS |= CCM_ANALOG_PLL_SYS_ENABLE_MASK; +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* DeInit Usb1 PLL. */ + CLOCK_DeinitUsb1Pll(); + /* Bypass Usb1 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb1, 1); + /* Enable Usb1 PLL output. */ + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_ENABLE_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source to other clock source before change periph clock2 source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ +#if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK; +#elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) + /* Backward compatibility for original bitfield name */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; +#else +#error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined." +#endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */ + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_CLOCKLOWPOWER_CORE_CLOCK; +} + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/clock_config.h new file mode 100644 index 0000000..57cbd76 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/clock_config.h @@ -0,0 +1,278 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_ClockFullSpeed ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_ClockFullSpeed configuration + ******************************************************************************/ +#define BOARD_CLOCKFULLSPEED_CORE_CLOCK 528000000U /*!< Core clock frequency: 528000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_CLOCKFULLSPEED_AHB_CLK_ROOT 528000000UL +#define BOARD_CLOCKFULLSPEED_CAN_CLK_ROOT 40000000UL +#define BOARD_CLOCKFULLSPEED_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_CLOCKFULLSPEED_CLKO1_CLK 0UL +#define BOARD_CLOCKFULLSPEED_CLKO2_CLK 0UL +#define BOARD_CLOCKFULLSPEED_CLK_1M 1000000UL +#define BOARD_CLOCKFULLSPEED_CLK_24M 24000000UL +#define BOARD_CLOCKFULLSPEED_CSI_CLK_ROOT 12000000UL +#define BOARD_CLOCKFULLSPEED_ENET_125M_CLK 2400000UL +#define BOARD_CLOCKFULLSPEED_ENET_25M_REF_CLK 1200000UL +#define BOARD_CLOCKFULLSPEED_ENET_REF_CLK 0UL +#define BOARD_CLOCKFULLSPEED_ENET_TX_CLK 0UL +#define BOARD_CLOCKFULLSPEED_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_CLOCKFULLSPEED_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_CLOCKFULLSPEED_FLEXSPI_CLK_ROOT 160000000UL +#define BOARD_CLOCKFULLSPEED_GPT1_IPG_CLK_HIGHFREQ 66000000UL +#define BOARD_CLOCKFULLSPEED_GPT2_IPG_CLK_HIGHFREQ 66000000UL +#define BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT 132000000UL +#define BOARD_CLOCKFULLSPEED_LCDIF_CLK_ROOT 67500000UL +#define BOARD_CLOCKFULLSPEED_LPI2C_CLK_ROOT 60000000UL +#define BOARD_CLOCKFULLSPEED_LPSPI_CLK_ROOT 105600000UL +#define BOARD_CLOCKFULLSPEED_LVDS1_CLK 1056000000UL +#define BOARD_CLOCKFULLSPEED_MQS_MCLK 63529411UL +#define BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT 66000000UL +#define BOARD_CLOCKFULLSPEED_PLL7_MAIN_CLK 24000000UL +#define BOARD_CLOCKFULLSPEED_SAI1_CLK_ROOT 63529411UL +#define BOARD_CLOCKFULLSPEED_SAI1_MCLK1 63529411UL +#define BOARD_CLOCKFULLSPEED_SAI1_MCLK2 63529411UL +#define BOARD_CLOCKFULLSPEED_SAI1_MCLK3 30000000UL +#define BOARD_CLOCKFULLSPEED_SAI2_CLK_ROOT 63529411UL +#define BOARD_CLOCKFULLSPEED_SAI2_MCLK1 63529411UL +#define BOARD_CLOCKFULLSPEED_SAI2_MCLK2 0UL +#define BOARD_CLOCKFULLSPEED_SAI2_MCLK3 30000000UL +#define BOARD_CLOCKFULLSPEED_SAI3_CLK_ROOT 63529411UL +#define BOARD_CLOCKFULLSPEED_SAI3_MCLK1 63529411UL +#define BOARD_CLOCKFULLSPEED_SAI3_MCLK2 0UL +#define BOARD_CLOCKFULLSPEED_SAI3_MCLK3 30000000UL +#define BOARD_CLOCKFULLSPEED_SEMC_CLK_ROOT 66000000UL +#define BOARD_CLOCKFULLSPEED_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_CLOCKFULLSPEED_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_CLOCKFULLSPEED_TRACE_CLK_ROOT 117333333UL +#define BOARD_CLOCKFULLSPEED_UART_CLK_ROOT 80000000UL +#define BOARD_CLOCKFULLSPEED_USBPHY1_CLK 0UL +#define BOARD_CLOCKFULLSPEED_USBPHY2_CLK 0UL +#define BOARD_CLOCKFULLSPEED_USDHC1_CLK_ROOT 198000000UL +#define BOARD_CLOCKFULLSPEED_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_ClockFullSpeed configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_ClockFullSpeed; +/*! @brief Usb1 PLL set for BOARD_ClockFullSpeed configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_ClockFullSpeed; +/*! @brief Sys PLL for BOARD_ClockFullSpeed configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_ClockFullSpeed; + +/******************************************************************************* + * API for BOARD_ClockFullSpeed configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_ClockFullSpeed(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_ClockOverdrive ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_ClockOverdrive configuration + ******************************************************************************/ +#define BOARD_CLOCKOVERDRIVE_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_CLOCKOVERDRIVE_AHB_CLK_ROOT 600000000UL +#define BOARD_CLOCKOVERDRIVE_CAN_CLK_ROOT 40000000UL +#define BOARD_CLOCKOVERDRIVE_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_CLOCKOVERDRIVE_CLKO1_CLK 0UL +#define BOARD_CLOCKOVERDRIVE_CLKO2_CLK 0UL +#define BOARD_CLOCKOVERDRIVE_CLK_1M 1000000UL +#define BOARD_CLOCKOVERDRIVE_CLK_24M 24000000UL +#define BOARD_CLOCKOVERDRIVE_CSI_CLK_ROOT 12000000UL +#define BOARD_CLOCKOVERDRIVE_ENET_125M_CLK 2400000UL +#define BOARD_CLOCKOVERDRIVE_ENET_25M_REF_CLK 1200000UL +#define BOARD_CLOCKOVERDRIVE_ENET_REF_CLK 0UL +#define BOARD_CLOCKOVERDRIVE_ENET_TX_CLK 0UL +#define BOARD_CLOCKOVERDRIVE_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_CLOCKOVERDRIVE_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_CLOCKOVERDRIVE_FLEXSPI_CLK_ROOT 160000000UL +#define BOARD_CLOCKOVERDRIVE_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_CLOCKOVERDRIVE_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_CLOCKOVERDRIVE_IPG_CLK_ROOT 150000000UL +#define BOARD_CLOCKOVERDRIVE_LCDIF_CLK_ROOT 67500000UL +#define BOARD_CLOCKOVERDRIVE_LPI2C_CLK_ROOT 60000000UL +#define BOARD_CLOCKOVERDRIVE_LPSPI_CLK_ROOT 105600000UL +#define BOARD_CLOCKOVERDRIVE_LVDS1_CLK 1200000000UL +#define BOARD_CLOCKOVERDRIVE_MQS_MCLK 63529411UL +#define BOARD_CLOCKOVERDRIVE_PERCLK_CLK_ROOT 75000000UL +#define BOARD_CLOCKOVERDRIVE_PLL7_MAIN_CLK 24000000UL +#define BOARD_CLOCKOVERDRIVE_SAI1_CLK_ROOT 63529411UL +#define BOARD_CLOCKOVERDRIVE_SAI1_MCLK1 63529411UL +#define BOARD_CLOCKOVERDRIVE_SAI1_MCLK2 63529411UL +#define BOARD_CLOCKOVERDRIVE_SAI1_MCLK3 30000000UL +#define BOARD_CLOCKOVERDRIVE_SAI2_CLK_ROOT 63529411UL +#define BOARD_CLOCKOVERDRIVE_SAI2_MCLK1 63529411UL +#define BOARD_CLOCKOVERDRIVE_SAI2_MCLK2 0UL +#define BOARD_CLOCKOVERDRIVE_SAI2_MCLK3 30000000UL +#define BOARD_CLOCKOVERDRIVE_SAI3_CLK_ROOT 63529411UL +#define BOARD_CLOCKOVERDRIVE_SAI3_MCLK1 63529411UL +#define BOARD_CLOCKOVERDRIVE_SAI3_MCLK2 0UL +#define BOARD_CLOCKOVERDRIVE_SAI3_MCLK3 30000000UL +#define BOARD_CLOCKOVERDRIVE_SEMC_CLK_ROOT 75000000UL +#define BOARD_CLOCKOVERDRIVE_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_CLOCKOVERDRIVE_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_CLOCKOVERDRIVE_TRACE_CLK_ROOT 117333333UL +#define BOARD_CLOCKOVERDRIVE_UART_CLK_ROOT 80000000UL +#define BOARD_CLOCKOVERDRIVE_USBPHY1_CLK 0UL +#define BOARD_CLOCKOVERDRIVE_USBPHY2_CLK 0UL +#define BOARD_CLOCKOVERDRIVE_USDHC1_CLK_ROOT 198000000UL +#define BOARD_CLOCKOVERDRIVE_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_ClockOverdrive configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_ClockOverdrive; +/*! @brief Usb1 PLL set for BOARD_ClockOverdrive configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_ClockOverdrive; +/*! @brief Sys PLL for BOARD_ClockOverdrive configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_ClockOverdrive; + +/******************************************************************************* + * API for BOARD_ClockOverdrive configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_ClockOverdrive(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_ClockLowPower *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_ClockLowPower configuration + ******************************************************************************/ +#define BOARD_CLOCKLOWPOWER_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_CLOCKLOWPOWER_AHB_CLK_ROOT 24000000UL +#define BOARD_CLOCKLOWPOWER_CAN_CLK_ROOT 2000000UL +#define BOARD_CLOCKLOWPOWER_CKIL_SYNC_CLK_ROOT 0UL +#define BOARD_CLOCKLOWPOWER_CLKO1_CLK 0UL +#define BOARD_CLOCKLOWPOWER_CLKO2_CLK 0UL +#define BOARD_CLOCKLOWPOWER_CLK_1M 1000000UL +#define BOARD_CLOCKLOWPOWER_CLK_24M 24000000UL +#define BOARD_CLOCKLOWPOWER_CSI_CLK_ROOT 12000000UL +#define BOARD_CLOCKLOWPOWER_ENET_125M_CLK 2400000UL +#define BOARD_CLOCKLOWPOWER_ENET_25M_REF_CLK 1200000UL +#define BOARD_CLOCKLOWPOWER_ENET_REF_CLK 0UL +#define BOARD_CLOCKLOWPOWER_ENET_TX_CLK 0UL +#define BOARD_CLOCKLOWPOWER_FLEXIO1_CLK_ROOT 1500000UL +#define BOARD_CLOCKLOWPOWER_FLEXIO2_CLK_ROOT 1500000UL +#define BOARD_CLOCKLOWPOWER_FLEXSPI_CLK_ROOT 24000000UL +#define BOARD_CLOCKLOWPOWER_GPT1_IPG_CLK_HIGHFREQ 12000000UL +#define BOARD_CLOCKLOWPOWER_GPT2_IPG_CLK_HIGHFREQ 12000000UL +#define BOARD_CLOCKLOWPOWER_IPG_CLK_ROOT 12000000UL +#define BOARD_CLOCKLOWPOWER_LCDIF_CLK_ROOT 3000000UL +#define BOARD_CLOCKLOWPOWER_LPI2C_CLK_ROOT 3000000UL +#define BOARD_CLOCKLOWPOWER_LPSPI_CLK_ROOT 6000000UL +#define BOARD_CLOCKLOWPOWER_LVDS1_CLK 24000000UL +#define BOARD_CLOCKLOWPOWER_MQS_MCLK 3000000UL +#define BOARD_CLOCKLOWPOWER_PERCLK_CLK_ROOT 12000000UL +#define BOARD_CLOCKLOWPOWER_PLL7_MAIN_CLK 24000000UL +#define BOARD_CLOCKLOWPOWER_SAI1_CLK_ROOT 3000000UL +#define BOARD_CLOCKLOWPOWER_SAI1_MCLK1 3000000UL +#define BOARD_CLOCKLOWPOWER_SAI1_MCLK2 3000000UL +#define BOARD_CLOCKLOWPOWER_SAI1_MCLK3 1500000UL +#define BOARD_CLOCKLOWPOWER_SAI2_CLK_ROOT 3000000UL +#define BOARD_CLOCKLOWPOWER_SAI2_MCLK1 3000000UL +#define BOARD_CLOCKLOWPOWER_SAI2_MCLK2 0UL +#define BOARD_CLOCKLOWPOWER_SAI2_MCLK3 1500000UL +#define BOARD_CLOCKLOWPOWER_SAI3_CLK_ROOT 3000000UL +#define BOARD_CLOCKLOWPOWER_SAI3_MCLK1 3000000UL +#define BOARD_CLOCKLOWPOWER_SAI3_MCLK2 0UL +#define BOARD_CLOCKLOWPOWER_SAI3_MCLK3 1500000UL +#define BOARD_CLOCKLOWPOWER_SEMC_CLK_ROOT 24000000UL +#define BOARD_CLOCKLOWPOWER_SPDIF0_CLK_ROOT 1500000UL +#define BOARD_CLOCKLOWPOWER_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_CLOCKLOWPOWER_TRACE_CLK_ROOT 6000000UL +#define BOARD_CLOCKLOWPOWER_UART_CLK_ROOT 4000000UL +#define BOARD_CLOCKLOWPOWER_USBPHY1_CLK 0UL +#define BOARD_CLOCKLOWPOWER_USBPHY2_CLK 0UL +#define BOARD_CLOCKLOWPOWER_USDHC1_CLK_ROOT 12000000UL +#define BOARD_CLOCKLOWPOWER_USDHC2_CLK_ROOT 12000000UL + + +/******************************************************************************* + * API for BOARD_ClockLowPower configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_ClockLowPower(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld index 0684eb4..f9444af 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld @@ -69,7 +69,6 @@ #endif m_itcm (RX) : ORIGIN = 0x00000000, LENGTH = 0x00020000 - m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 m_dtcm (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 } @@ -85,7 +84,7 @@ . = ALIGN(8); } > m_flash_config - ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); .ivt : { @@ -241,14 +240,14 @@ *(NonCacheable.init) . = ALIGN(8); __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ - } > m_ncache AT> m_text + } > m_data AT> m_text . = __noncachedata_init_end__; .ncache : { *(NonCacheable) . = ALIGN(8); __noncachedata_end__ = .; /* define a global symbol at ncache data end */ - } > m_ncache + } > m_data __TEXT_CSF_ROM = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); @@ -260,7 +259,14 @@ __text_csf_end = .; } > m_text - __USED_FLASH_END = __TEXT_CSF_ROM + SIZEOF(.csf); + + /* __USED_FLASH_END gives the end of all data written to the flash memory, including code and data + initializers. */ + PROVIDE(__USED_FLASH_END = __TEXT_CSF_ROM + SIZEOF(.csf)); + + /* __USED_FLASH_SIZE gives the size of all data written to the flash memory, including code and data + initializers. */ + PROVIDE(__USED_FLASH_SIZE = __USED_FLASH_END - ORIGIN(m_text)); text_end = ORIGIN(m_text) + LENGTH(m_text); ASSERT(__USED_FLASH_END <= text_end, "Code and data initializers exceed flash size!") @@ -305,6 +311,14 @@ .ARM.attributes 0 : { *(.ARM.attributes) } + /* Teensy model identifier symbol (used by Teensy Loader) */ + /* See here https://forum.pjrc.com/threads/72107-Testers-Needed-Mbed-OS-Port-for-Teensy-4-0?p=320414&viewfull=1#post320414 */ +#if defined(TARGET_TEENSY_40) + _teensy_model_identifier = 0x24; +#elif defined(TARGET_TEENSY_41) + _teensy_model_identifier = 0x25; +#endif + ASSERT(__StackLimit >= __HeapLimit, "Stack, heap, and globals exceed main RAM size!") } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.c deleted file mode 100644 index d9a1fb3..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to setup clock using clock driver functions: - * - * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. - * - * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. - * - * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. - * - * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. - * - * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. - * - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v5.0 -processor: MIMXRT1052xxxxB -package_id: MIMXRT1052DVL6B -mcu_data: ksdk2_0 -processor_version: 0.0.0 -board: IMXRT1050-EVKB - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "fsl_clock_config.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} -- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} -- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} -- {id: CLK_1M.outFreq, value: 1 MHz} -- {id: CLK_24M.outFreq, value: 24 MHz} -- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} -- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} -- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} -- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} -- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz} -- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} -- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} -- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} -- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} -- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} -- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} -- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} -- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} -- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} -- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} -- {id: SAI1_MCLK3.outFreq, value: 30 MHz} -- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI2_MCLK3.outFreq, value: 30 MHz} -- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} -- {id: SAI3_MCLK3.outFreq, value: 30 MHz} -- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} -- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} -- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} -- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} -- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} -- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} -settings: -- {id: CCM.AHB_PODF.scale, value: '1', locked: true} -- {id: CCM.ARM_PODF.scale, value: '2', locked: true} -- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true} -- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL} -- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} -- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} -- {id: CCM.SEMC_PODF.scale, value: '8'} -- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} -- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} -- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} -- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} -- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} -- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} -- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} -- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} -- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} -- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} -- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} -- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} -- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} -- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} -- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} -- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} -- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} -- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} -- {id: CCM_ANALOG.PLL4.denom, value: '50'} -- {id: CCM_ANALOG.PLL4.div, value: '47'} -- {id: CCM_ANALOG.PLL5.denom, value: '1'} -- {id: CCM_ANALOG.PLL5.div, value: '40'} -- {id: CCM_ANALOG.PLL5.num, value: '0'} -- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} -- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} -sources: -- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true} -- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = { - .loopDivider = 88, /* PLL loop divider, Fout = Fin * 44 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /* Init RTC OSC clock frequency. */ - CLOCK_SetRtcXtalFreq(32768U); - /* Enable 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; - /* Use free 1MHz clock output. */ - XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; - /* Set XTAL 24MHz clock frequency. */ - CLOCK_SetXtalFreq(24000000U); - /* Enable XTAL 24MHz clock source. */ - CLOCK_InitExternalClk(0); - /* Enable internal RC. */ - CLOCK_InitRcOsc24M(); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); - /* Set Oscillator ready counter value. */ - CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); - /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) - { - } - /* Set AHB_PODF. */ - CLOCK_SetDiv(kCLOCK_AhbDiv, 0); - /* Disable IPG clock gate. */ - CLOCK_DisableClock(kCLOCK_Adc1); - CLOCK_DisableClock(kCLOCK_Adc2); - CLOCK_DisableClock(kCLOCK_Xbar1); - CLOCK_DisableClock(kCLOCK_Xbar2); - CLOCK_DisableClock(kCLOCK_Xbar3); - /* Set IPG_PODF. */ - CLOCK_SetDiv(kCLOCK_IpgDiv, 3); - /* Set ARM_PODF. */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - /* Set PERIPH_CLK2_PODF. */ - CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); - /* Disable PERCLK clock gate. */ - CLOCK_DisableClock(kCLOCK_Gpt1); - CLOCK_DisableClock(kCLOCK_Gpt1S); - CLOCK_DisableClock(kCLOCK_Gpt2); - CLOCK_DisableClock(kCLOCK_Gpt2S); - CLOCK_DisableClock(kCLOCK_Pit); - /* Set PERCLK_PODF. */ - CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); - /* Disable USDHC1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc1); - /* Set USDHC1_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); - /* Set Usdhc1 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); - /* Disable USDHC2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Usdhc2); - /* Set USDHC2_PODF. */ - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); - /* Set Usdhc2 clock source. */ - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); -/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. - * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Disable Semc clock gate. */ - CLOCK_DisableClock(kCLOCK_Semc); - /* Set SEMC_PODF. */ - CLOCK_SetDiv(kCLOCK_SemcDiv, 7); - /* Set Semc alt clock source. */ - CLOCK_SetMux(kCLOCK_SemcAltMux, 0); - /* Set Semc clock source. */ - CLOCK_SetMux(kCLOCK_SemcMux, 0); -#endif -/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. - * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Disable Flexspi clock gate. */ - CLOCK_DisableClock(kCLOCK_FlexSpi); - /* Set FLEXSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2); - /* Set Flexspi clock source. */ - CLOCK_SetMux(kCLOCK_FlexspiMux, 1); -#endif - /* Disable CSI clock gate. */ - CLOCK_DisableClock(kCLOCK_Csi); - /* Set CSI_PODF. */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 1); - /* Set Csi clock source. */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); - /* Disable LPSPI clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpspi1); - CLOCK_DisableClock(kCLOCK_Lpspi2); - CLOCK_DisableClock(kCLOCK_Lpspi3); - CLOCK_DisableClock(kCLOCK_Lpspi4); - /* Set LPSPI_PODF. */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); - /* Set Lpspi clock source. */ - CLOCK_SetMux(kCLOCK_LpspiMux, 2); - /* Disable TRACE clock gate. */ - CLOCK_DisableClock(kCLOCK_Trace); - /* Set TRACE_PODF. */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 2); - /* Set Trace clock source. */ - CLOCK_SetMux(kCLOCK_TraceMux, 2); - /* Disable SAI1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai1); - /* Set SAI1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); - /* Set SAI1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai1Div, 1); - /* Set Sai1 clock source. */ - CLOCK_SetMux(kCLOCK_Sai1Mux, 0); - /* Disable SAI2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai2); - /* Set SAI2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); - /* Set SAI2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai2Div, 1); - /* Set Sai2 clock source. */ - CLOCK_SetMux(kCLOCK_Sai2Mux, 0); - /* Disable SAI3 clock gate. */ - CLOCK_DisableClock(kCLOCK_Sai3); - /* Set SAI3_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); - /* Set SAI3_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Sai3Div, 1); - /* Set Sai3 clock source. */ - CLOCK_SetMux(kCLOCK_Sai3Mux, 0); - /* Disable Lpi2c clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpi2c1); - CLOCK_DisableClock(kCLOCK_Lpi2c2); - CLOCK_DisableClock(kCLOCK_Lpi2c3); - /* Set LPI2C_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); - /* Set Lpi2c clock source. */ - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); - /* Disable CAN clock gate. */ - CLOCK_DisableClock(kCLOCK_Can1); - CLOCK_DisableClock(kCLOCK_Can2); - CLOCK_DisableClock(kCLOCK_Can1S); - CLOCK_DisableClock(kCLOCK_Can2S); - /* Set CAN_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_CanDiv, 1); - /* Set Can clock source. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); - /* Disable UART clock gate. */ - CLOCK_DisableClock(kCLOCK_Lpuart1); - CLOCK_DisableClock(kCLOCK_Lpuart2); - CLOCK_DisableClock(kCLOCK_Lpuart3); - CLOCK_DisableClock(kCLOCK_Lpuart4); - CLOCK_DisableClock(kCLOCK_Lpuart5); - CLOCK_DisableClock(kCLOCK_Lpuart6); - CLOCK_DisableClock(kCLOCK_Lpuart7); - CLOCK_DisableClock(kCLOCK_Lpuart8); - /* Set UART_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); - /* Set Uart clock source. */ - CLOCK_SetMux(kCLOCK_UartMux, 0); - /* Disable LCDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_LcdPixel); - /* Set LCDIF_PRED. */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); - /* Set LCDIF_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); - /* Set Lcdif pre clock source. */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); - /* Disable SPDIF clock gate. */ - CLOCK_DisableClock(kCLOCK_Spdif); - /* Set SPDIF0_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); - /* Set SPDIF0_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); - /* Set Spdif clock source. */ - CLOCK_SetMux(kCLOCK_SpdifMux, 3); - /* Disable Flexio1 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio1); - /* Set FLEXIO1_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); - /* Set FLEXIO1_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); - /* Set Flexio1 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); - /* Disable Flexio2 clock gate. */ - CLOCK_DisableClock(kCLOCK_Flexio2); - /* Set FLEXIO2_CLK_PRED. */ - CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); - /* Set FLEXIO2_CLK_PODF. */ - CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); - /* Set Flexio2 clock source. */ - CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); - /* Set Pll3 sw clock source. */ - CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); - /* Init ARM PLL. */ - CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); - /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. - * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left - * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as - * well.*/ -#ifndef SKIP_SYSCLK_INIT - /* Init System PLL. */ - CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - /* Disable pfd offset. */ - CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK; -#endif - /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. - * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left - * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as - * well.*/ -#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Init Usb1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; -#endif - /* DeInit Audio PLL. */ - CLOCK_DeinitAudioPll(); - /* Bypass Audio PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); - /* Set divider for Audio PLL. */ - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; - CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; - /* Enable Audio PLL output. */ - CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - /* DeInit Video PLL. */ - CLOCK_DeinitVideoPll(); - /* Bypass Video PLL. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - /* Set divider for Video PLL. */ - CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); - /* Enable Video PLL output. */ - CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - /* DeInit Enet PLL. */ - CLOCK_DeinitEnetPll(); - /* Bypass Enet PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); - /* Set Enet output divider. */ - CCM_ANALOG->PLL_ENET = - (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); - /* Enable Enet output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; - /* Enable Enet25M output. */ - CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - /* DeInit Usb2 PLL. */ - CLOCK_DeinitUsb2Pll(); - /* Bypass Usb2 PLL. */ - CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); - /* Enable Usb2 PLL output. */ - CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; - /* Set preperiph clock source. */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); - /* Set periph clock source. */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0); - /* Set periph clock2 clock source. */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); - /* Set per clock source. */ - CLOCK_SetMux(kCLOCK_PerclkMux, 0); - /* Set lvds1 clock source. */ - CCM_ANALOG->MISC1 = - (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); - /* Set clock out1 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); - /* Set clock out1 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); - /* Set clock out2 divider. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); - /* Set clock out2 source. */ - CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); - /* Set clock out1 drives clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; - /* Disable clock out1. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; - /* Disable clock out2. */ - CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; - /* Set SAI1 MCLK1 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); - /* Set SAI1 MCLK2 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); - /* Set SAI1 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); - /* Set SAI2 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); - /* Set SAI3 MCLK3 clock source. */ - IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); - /* Set MQS configuration. */ - IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); - /* Set ENET Tx clock source. */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); - /* Set GPT1 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; - /* Set GPT2 High frequency reference clock source. */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; - /* Set SystemCoreClock variable. */ - SystemCoreClock = CLOCK_GetCpuClkFreq(); -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.h index f213ac7..be880da 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/fsl_clock_config.h @@ -1,119 +1,11 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause +/* mbed Microcontroller Library + * Copyright (c) 2023 ARM Limited + * SPDX-License-Identifier: Apache-2.0 */ -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ +// +// "clock_config.h" is the name needed by MCUXpresso Config Tools to load the file, +// but "fsl_clock_config.h" is expected by some Mbed headers. +// -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ - -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ - -/* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL - -/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; -/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. - */ -extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; -/*! @brief Sys PLL for BOARD_BootClockRUN configuration. - */ -extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ +#include "clock_config.h" \ No newline at end of file diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.c index 420f15d..e36526d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2020 NXP * All rights reserved. * * @@ -9,11 +9,7 @@ #include "lpm.h" #include "fsl_gpc.h" #include "fsl_dcdc.h" -#include "fsl_gpt.h" -#include "fsl_clock_config.h" -#include "mbed_critical.h" -#include "cmsis.h" -#include "specific.h" +#include "mimxrt_clock_adjustment.h" /******************************************************************************* * Definitions @@ -23,10 +19,7 @@ /******************************************************************************* * Variables ******************************************************************************/ - -uint32_t g_savedPrimask; -GPT_Type *vPortGetGptBase(void); -IRQn_Type vPortGetGptIrqn(void); +static uint32_t g_savedPrimask; /******************************************************************************* * Code @@ -92,15 +85,15 @@ CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); - //assert(busyShift <= CCM_NO_BUSY_WAIT); + assert(busyShift <= CCM_NO_BUSY_WAIT); /* Clock switch need Handshake? */ if (CCM_NO_BUSY_WAIT != busyShift) { /* Wait until CCM internal handshake finish. */ while (CCM->CDHIPR & (1U << busyShift)) - { - } + { + } } } @@ -118,7 +111,7 @@ CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); - //assert(busyShift <= CCM_NO_BUSY_WAIT); + assert(busyShift <= CCM_NO_BUSY_WAIT); /* Clock switch need Handshake? */ if (CCM_NO_BUSY_WAIT != busyShift) @@ -132,321 +125,33 @@ void ClockSelectXtalOsc(void) { + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Wait for XTAL stable */ + SDK_DelayAtLeastUs(200); /* Switch clock source to external OSC. */ CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* + * Some board will failed to wake up from suspend mode if rcosc is powered down when clock source switch from rcosc + * to external osc. Root cause is not found. Workaround: keep rcosc on. + */ +#ifndef KEEP_RCOSC_ON + /* Power Down internal RC. */ + CLOCK_DeinitRcOsc24M(); +#endif } void ClockSelectRcOsc(void) { + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); /* Switch clock source to internal RC. */ - XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; + CLOCK_SwitchOsc(kCLOCK_RcOsc); + /* Disable XTAL 24MHz clock source. */ + CLOCK_DeinitExternalClk(); } -void LPM_SetRunModeConfig(void) -{ - CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); -} - -void LPM_SetWaitModeConfig(void) -{ - uint32_t clpcr; - - /* - * ERR007265: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending - * by setting IOMUXC_GPR_GPR1_GINT. - * 2) Software should then unmask IRQ #41 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #41 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); - clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); - CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeWait) | CCM_CLPCR_MASK_SCU_IDLE_MASK | CCM_CLPCR_MASK_L2CC_IDLE_MASK | - CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK | - CCM_CLPCR_BYPASS_LPM_HS1_MASK; - GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); -} - -void LPM_SetStopModeConfig(void) -{ - uint32_t clpcr; - - /* - * ERR007265: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending - * by setting IOMUXC_GPR_GPR1_GINT. - * 2) Software should then unmask IRQ #41 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #41 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); - clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); - CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeStop) | CCM_CLPCR_MASK_L2CC_IDLE_MASK | CCM_CLPCR_MASK_SCU_IDLE_MASK | - CCM_CLPCR_VSTBY_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_SBYOS_MASK | - CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK; - GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); -} - -void LPM_OverDriveRun(void) -{ - /* CCM Mode */ - DCDC_BootIntoCCM(DCDC); - /* Connect internal the load resistor */ - DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; - /* Adjust SOC voltage to 1.275V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - - /* Disable FET ODRIVE */ - PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - BandgapOn(); - EnableRegularLDO(); - DisableWeakLDO(); - - ClockSetToOverDriveRun(); - SetRestoreClockGate(); -} - -void LPM_FullSpeedRun(void) -{ - /* CCM Mode */ - DCDC_BootIntoCCM(DCDC); - /* Connect internal the load resistor */ - DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; - /* Adjust SOC voltage to 1.275V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - - /* Disable FET ODRIVE */ - PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - BandgapOn(); - EnableRegularLDO(); - DisableWeakLDO(); - - ClockSetToFullSpeedRun(); - - /* Adjust SOC voltage to 1.15V */ - DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); -} - -void LPM_LowSpeedRun(void) -{ - /* CCM Mode */ - DCDC_BootIntoCCM(DCDC); - /* Connect internal the load resistor */ - DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; - /* Adjust SOC voltage to 1.275V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - - /* Disable FET ODRIVE */ - PMU->REG_CORE_CLR = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - BandgapOn(); - EnableRegularLDO(); - DisableWeakLDO(); - - ClockSetToLowSpeedRun(); - - /* Adjust SOC voltage to 1.15V */ - DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); -} - -void LPM_LowPowerRun(void) -{ - ClockSetToLowPowerRun(); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* Adjust SOC voltage to 0.95V */ - DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); - /* DCM Mode */ - DCDC_BootIntoDCM(DCDC); - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - /* Power Down output range comparator */ - DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - EnableWeakLDO(); - DisableRegularLDO(); - BandgapOff(); -} - -void LPM_EnterSystemIdle(void) -{ - LPM_SetWaitModeConfig(); - SetLowPowerClockGate(); - - ClockSetToSystemIdle(); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* DCDC to 1.15V */ - DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); - /* DCM Mode */ - DCDC_BootIntoDCM(DCDC); - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - /* Power Down output range comparator */ - DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - EnableRegularLDO(); - DisableWeakLDO(); - BandgapOn(); - - PeripheralEnterDozeMode(); -} - -void LPM_ExitSystemIdle(void) -{ - PeripheralExitDozeMode(); - LPM_SetRunModeConfig(); -} - -void LPM_EnterLowPowerIdle(void) -{ - LPM_SetWaitModeConfig(); - SetLowPowerClockGate(); - - ClockSetToLowPowerIdle(); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* Adjust SOC voltage to 0.95V */ - DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); - /* DCM Mode */ - DCDC_BootIntoDCM(DCDC); - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - /* Power Down output range comparator */ - DCDC->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - - EnableWeakLDO(); - DisableRegularLDO(); - BandgapOff(); - - PeripheralEnterDozeMode(); -} - -void LPM_ExitLowPowerIdle(void) -{ - PeripheralExitDozeMode(); - LPM_SetRunModeConfig(); -} - -void LPM_EnterSuspend(void) -{ - uint32_t i; - uint32_t gpcIMR[LPM_GPC_IMR_NUM]; - - LPM_SetStopModeConfig(); - SetLowPowerClockGate(); - - /* Disconnect internal the load resistor */ - DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; - - /* Turn off FlexRAM0 */ - GPC->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; - /* Turn off FlexRAM1 */ - PGC->MEGA_CTRL |= PGC_MEGA_CTRL_PCR_MASK; - - /* Clean and disable data cache to make sure context is saved into RAM */ - SCB_CleanDCache(); - SCB_DisableDCache(); - - /* Adjust LP voltage to 0.925V */ - DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); - /* Switch DCDC to use DCDC internal OSC */ - DCDC_SetClockSource(DCDC, kDCDC_ClockInternalOsc); - - /* Power down USBPHY */ - PowerDownUSBPHY(); - - /* Power down CPU when requested */ - PGC->CPU_CTRL = PGC_CPU_CTRL_PCR_MASK; - - /* Enable FET ODRIVE */ - PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; - /* Connect vdd_high_in and connect vdd_snvs_in */ - PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; - /* STOP_MODE config, turn off all analog except RTC in stop mode */ - PMU->MISC0_CLR = PMU_MISC0_STOP_MODE_CONFIG_MASK; - - /* Mask all GPC interrupts before enabling the RBC counters to - * avoid the counter starting too early if an interupt is already - * pending. - */ - for (i = 0; i < LPM_GPC_IMR_NUM; i++) - { - gpcIMR[i] = GPC->IMR[i]; - GPC->IMR[i] = 0xFFFFFFFFU; - } - - /* - * ERR006223: CCM: Failure to resuem from wait/stop mode with power gating - * Configure REG_BYPASS_COUNTER to 2 - * Enable the RBC bypass counter here to hold off the interrupts. RBC counter - * needs to be no less than 2. - */ - CCM->CCR = (CCM->CCR & ~CCM_CCR_REG_BYPASS_COUNT_MASK) | CCM_CCR_REG_BYPASS_COUNT(2); - CCM->CCR |= (CCM_CCR_OSCNT(0xAF) | CCM_CCR_COSC_EN_MASK | CCM_CCR_RBC_EN_MASK); - - /* Now delay for a short while (3usec) at this point - * so a short loop should be enough. This delay is required to ensure that - * the RBC counter can start counting in case an interrupt is already pending - * or in case an interrupt arrives just as ARM is about to assert DSM_request. - */ - SDK_DelayAtLeastUs(3); - - /* Recover all the GPC interrupts. */ - for (i = 0; i < LPM_GPC_IMR_NUM; i++) - { - GPC->IMR[i] = gpcIMR[i]; - } - - PeripheralEnterStopMode(); -} - -void LPM_EnterSNVS(void) -{ - SNVS->LPCR |= SNVS_LPCR_TOP_MASK; - while (1) /* Shutdown */ - { - } -} - -bool LPM_Init(void) +void LPM_Init(void) { uint32_t i; uint32_t tmp_reg = 0; @@ -475,10 +180,10 @@ tmp_reg |= XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(0x2d7); XTALOSC24M->OSC_CONFIG2 = tmp_reg; /* Hardware requires to read OSC_CONFIG0 or OSC_CONFIG1 to make OSC_CONFIG2 write work */ - tmp_reg = XTALOSC24M->OSC_CONFIG1; + tmp_reg = XTALOSC24M->OSC_CONFIG1; XTALOSC24M->OSC_CONFIG1 = tmp_reg; - /* ERR007265 */ + /* ERR050143 */ IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK; /* Initialize GPC to mask all IRQs */ @@ -486,14 +191,19 @@ { GPC->IMR[i] = 0xFFFFFFFFU; } + GPC->IMR5 = 0xFFFFFFFFU; - return true; -} + /* DCM Mode */ + DCDC_BootIntoDCM(DCDC); + /* Adjust SOC voltage to 1.275V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + /* Disconnect internal the load resistor */ + DCDC->REG1 &= ~DCDC_REG1_REG_RLOAD_SW_MASK; -void LPM_Deinit(void) -{ - /* ERR007265 */ - IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_GINT_MASK; + /* Enable FET ODRIVE */ + PMU->REG_CORE_SET = PMU_REG_CORE_FET_ODRIVE_MASK; + /* Connect vdd_high_in and connect vdd_snvs_in */ + PMU->MISC0_CLR = PMU_MISC0_DISCON_HIGH_SNVS_MASK; } void LPM_EnableWakeupSource(uint32_t irq) @@ -506,29 +216,282 @@ GPC_DisableIRQ(GPC, irq); } -GPT_Type *vPortGetGptBase(void) +void LPM_EnterSleepMode(clock_mode_t mode) { - return GPT2; + assert(mode != kCLOCK_ModeRun); + + g_savedPrimask = DisableGlobalIRQ(); + __DSB(); + __ISB(); + + if (mode == kCLOCK_ModeWait) + { + /* Clear the SLEEPDEEP bit to go into sleep mode (WAIT) */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + } + else + { + /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + } + /* WFI instruction will start entry into WAIT/STOP mode */ + __WFI(); + + EnableGlobalIRQ(g_savedPrimask); + __DSB(); + __ISB(); } -IRQn_Type vPortGetGptIrqn(void) +void LPM_SetRunModeConfig(void) { - return GPT2_IRQn; + CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); } -void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode) +void LPM_SetWaitModeConfig(void) { - LPM_EnableWakeupSource(vPortGetGptIrqn()); + uint32_t clpcr; - LPM_EnterLowPowerIdle(); + /* + * ERR050143: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending + * by setting IOMUXC_GPR_GPR1_GINT. + * 2) Software should then unmask IRQ #41 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #41 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); + clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); + CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeWait) | CCM_CLPCR_MASK_SCU_IDLE_MASK | CCM_CLPCR_MASK_L2CC_IDLE_MASK | + CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_BYPASS_LPM_HS_BITS; + GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); } -void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode) +void LPM_SetStopModeConfig(void) { - LPM_ExitLowPowerIdle(); + uint32_t clpcr; - LPM_OverDriveRun(); - - LPM_DisableWakeupSource(vPortGetGptIrqn()); + /* + * ERR050143: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending + * by setting IOMUXC_GPR_GPR1_GINT. + * 2) Software should then unmask IRQ #41 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #41 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); + clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); + CCM->CLPCR = clpcr | CCM_CLPCR_LPM(kCLOCK_ModeStop) | CCM_CLPCR_MASK_L2CC_IDLE_MASK | CCM_CLPCR_MASK_SCU_IDLE_MASK | + CCM_CLPCR_VSTBY_MASK | CCM_CLPCR_STBY_COUNT_MASK | CCM_CLPCR_SBYOS_MASK | + CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK | CCM_CLPCR_BYPASS_LPM_HS_BITS; + GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); } +/* Adjust system settings according to current run mode and target mode */ +void LPM_AdjustSystemSettings(lpm_power_mode_t curRunMode, lpm_power_mode_t targetMode) +{ + if (curRunMode == targetMode) + return; + + switch (curRunMode) + { + case LPM_PowerModeOverRun: + if (targetMode == LPM_PowerModeLowPowerRun) + { + ClockSelectRcOsc(); + /* Adjust SOC voltage to 0.95V */ + DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); + EnableWeakLDO(); + DisableRegularLDO(); + BandgapOff(); + } + else + { + /* Adjust SOC voltage to 1.15V */ + DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); + } + break; + case LPM_PowerModeFullRun: + if (targetMode == LPM_PowerModeOverRun) + { + /* Adjust SOC voltage to 1.275V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + } + else if (targetMode == LPM_PowerModeLowPowerRun) + { + ClockSelectRcOsc(); + /* Adjust SOC voltage to 0.95V */ + DCDC_AdjustTargetVoltage(DCDC, 0x6, 0x1); + EnableWeakLDO(); + DisableRegularLDO(); + BandgapOff(); + } + break; + case LPM_PowerModeLowPowerRun: + if (targetMode == LPM_PowerModeOverRun) + { + /* Adjust SOC voltage to 1.275V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + } + else + { + /* Adjust SOC voltage to 1.15V */ + DCDC_AdjustTargetVoltage(DCDC, 0xe, 0x1); + } + BandgapOn(); + EnableRegularLDO(); + DisableWeakLDO(); + ClockSelectXtalOsc(); + break; + default: + assert(false); + break; + } +} + +void LPM_OverDriveRun(lpm_power_mode_t curRunMode) +{ + /* Increase power supply before increasing core frequency */ + LPM_AdjustSystemSettings(curRunMode, LPM_PowerModeOverRun); + ClockSetToOverDriveRun(); +} + +void LPM_FullSpeedRun(lpm_power_mode_t curRunMode) +{ + if (curRunMode == LPM_PowerModeOverRun) + { + /* Decrease core frequency before decreasing power supply */ + ClockSetToFullSpeedRun(); + LPM_AdjustSystemSettings(curRunMode, LPM_PowerModeFullRun); + } + else + { + /* Increase power supply before increasing core frequency */ + LPM_AdjustSystemSettings(curRunMode, LPM_PowerModeFullRun); + ClockSetToFullSpeedRun(); + } +} + + +void LPM_LowPowerRun(lpm_power_mode_t curRunMode) +{ + /* Decrease core frequency before decreasing power supply */ + ClockSetToLowPowerRun(); + LPM_AdjustSystemSettings(curRunMode, LPM_PowerModeLowPowerRun); +} + +void LPM_EnterLowPowerIdle(lpm_power_mode_t curRunMode) +{ + /* LowPowerIdle is the idle state of LowPowerRun. Enter LowPowerRun mode first, then enter idle state. */ + if (curRunMode != LPM_PowerModeLowPowerRun) + { + LPM_LowPowerRun(curRunMode); + } + LPM_SetWaitModeConfig(); + PeripheralEnterDozeMode(); +} + +void LPM_ExitLowPowerIdle(lpm_power_mode_t curRunMode) +{ + PeripheralExitDozeMode(); + LPM_SetRunModeConfig(); + + if (curRunMode != LPM_PowerModeLowPowerRun) + { + /* Recover to previous run mode from LowPowerRun mode */ + switch (curRunMode) + { + case LPM_PowerModeOverRun: + LPM_OverDriveRun(LPM_PowerModeLowPowerRun); + break; + case LPM_PowerModeFullRun: + LPM_FullSpeedRun(LPM_PowerModeLowPowerRun); + break; + default: + break; + } + } +} + +void LPM_EnterSuspend(void) +{ + uint32_t i; + uint32_t gpcIMR[LPM_GPC_IMR_NUM]; + uint32_t gpcIMR5; + + LPM_SetStopModeConfig(); + + /* Connect internal the load resistor */ + DCDC->REG1 |= DCDC_REG1_REG_RLOAD_SW_MASK; + + /* Turn off FlexRAM0 */ + GPC->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; + /* Turn off FlexRAM1 */ + PGC->MEGA_CTRL |= PGC_MEGA_CTRL_PCR_MASK; + + /* Clean data cache to make sure context is saved into RAM */ + SCB_CleanDCache(); + + /* Adjust LP voltage to 0.925V */ + DCDC_AdjustTargetVoltage(DCDC, 0x13, 0x1); + /* Switch DCDC to use DCDC internal OSC */ + DCDC_SetClockSource(DCDC, kDCDC_ClockInternalOsc); + + /* Power down CPU when requested */ + PGC->CPU_CTRL = PGC_CPU_CTRL_PCR_MASK; + + /* STOP_MODE config, turn off all analog except RTC in stop mode */ + PMU->MISC0_CLR = PMU_MISC0_STOP_MODE_CONFIG_MASK; + + /* Mask all GPC interrupts before enabling the RBC counters to + * avoid the counter starting too early if an interupt is already + * pending. + */ + for (i = 0; i < LPM_GPC_IMR_NUM; i++) + { + gpcIMR[i] = GPC->IMR[i]; + GPC->IMR[i] = 0xFFFFFFFFU; + } + gpcIMR5 = GPC->IMR5; + GPC->IMR5 = 0xFFFFFFFFU; + + /* + * ERR006223: CCM: Failure to resuem from wait/stop mode with power gating + * Configure REG_BYPASS_COUNTER to 2 + * Enable the RBC bypass counter here to hold off the interrupts. RBC counter + * needs to be no less than 2. + */ + CCM->CCR = (CCM->CCR & ~CCM_CCR_REG_BYPASS_COUNT_MASK) | CCM_CCR_REG_BYPASS_COUNT(2); + CCM->CCR |= (CCM_CCR_OSCNT(0xAF) | CCM_CCR_COSC_EN_MASK | CCM_CCR_RBC_EN_MASK); + + /* Now delay for a short while (3usec) at this point + * so a short loop should be enough. This delay is required to ensure that + * the RBC counter can start counting in case an interrupt is already pending + * or in case an interrupt arrives just as ARM is about to assert DSM_request. + */ + SDK_DelayAtLeastUs(3); + + /* Recover all the GPC interrupts. */ + for (i = 0; i < LPM_GPC_IMR_NUM; i++) + { + GPC->IMR[i] = gpcIMR[i]; + } + GPC->IMR5 = gpcIMR5; + + PeripheralEnterStopMode(); +} + +void LPM_EnterSNVS(void) +{ + SNVS->LPCR |= SNVS_LPCR_TOP_MASK; + while (1) /* Shutdown */ + { + } +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.h index ea20400..867aaa0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/lpm.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2020 NXP * All rights reserved. * * @@ -9,53 +9,18 @@ #ifndef _LPM_H_ #define _LPM_H_ -#include "fsl_clock.h" #include +#include "fsl_clock.h" /******************************************************************************* * Definitions ******************************************************************************/ -extern void vPortGPTIsr(void); -extern uint32_t g_savedPrimask; -#define vPortGptIsr GPT1_IRQHandler - -#define CLOCK_CCM_HANDSHAKE_WAIT() \ - \ - do \ - { \ - while (CCM->CDHIPR != 0) \ - { \ - } \ - \ - } while (0) - -#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) -#define LPM_EnterCritical() \ - \ - do \ - { \ - g_savedPrimask = DisableGlobalIRQ(); \ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; \ - \ - } while (0) - -#define LPM_ExitCritical() \ - \ - do \ - { \ - EnableGlobalIRQ(g_savedPrimask); \ - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; \ - \ - } while (0) - -#else #define LPM_EnterCritical() #define LPM_ExitCritical() -#endif -/* Power mode definition of low power management. - * Waken up duration Off > Dsm > Idle > Wait > Run. +/* + * Power mode definition of low power management. */ typedef enum _lpm_power_mode { @@ -63,16 +28,9 @@ LPM_PowerModeFullRun, /* Full RUN mode, CPU won't stop running */ - LPM_PowerModeLowSpeedRun, - LPM_PowerModeLowPowerRun, LPM_PowerModeRunEnd = LPM_PowerModeLowPowerRun, - /* In system wait mode, cpu clock is gated. - * All peripheral can remain active, clock gating decided by CCGR setting. - * DRAM enters auto-refresh mode when there is no access. - */ - LPM_PowerModeSysIdle, /* System WAIT mode, also system low speed idle */ /* In low power idle mode, all PLL/PFD is off, cpu power is off. * Analog modules running in low power mode. @@ -106,35 +64,18 @@ AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_MUX(clock_mux_t mux, uint32_t value)); AT_QUICKACCESS_SECTION_CODE(void CLOCK_SET_DIV(clock_div_t divider, uint32_t value)); - -/* Initialize the Low Power Management */ -bool LPM_Init(void); - -/* Deinitialize the Low Power Management */ -void LPM_Deinit(void); - -/* Enable wakeup source in low power mode */ -void LPM_EnableWakeupSource(uint32_t irq); - -/* Disable wakeup source in low power mode */ -void LPM_DisableWakeupSource(uint32_t irq); - -void ClockSelectXtalOsc(void); -void ClockSelectRcOsc(void); +AT_QUICKACCESS_SECTION_CODE(void LPM_EnterSleepMode(clock_mode_t mode)); +void LPM_Init(void); void LPM_EnableWakeupSource(uint32_t irq); void LPM_DisableWakeupSource(uint32_t irq); -void LPM_PreEnterWaitMode(void); -void LPM_PostExitWaitMode(void); -void LPM_PreEnterStopMode(void); -void LPM_PostExitStopMode(void); -void LPM_OverDriveRun(void); -void LPM_FullSpeedRun(void); -void LPM_LowSpeedRun(void); -void LPM_LowPowerRun(void); -void LPM_EnterSystemIdle(void); -void LPM_ExitSystemIdle(void); -void LPM_EnterLowPowerIdle(void); -void LPM_ExitLowPowerIdle(void); +void LPM_OverDriveRun(lpm_power_mode_t curRunMode); +void LPM_FullSpeedRun(lpm_power_mode_t curRunMode); +void LPM_LowSpeedRun(lpm_power_mode_t curRunMode); +void LPM_LowPowerRun(lpm_power_mode_t curRunMode); +void LPM_EnterSystemIdle(lpm_power_mode_t curRunMode); +void LPM_ExitSystemIdle(lpm_power_mode_t curRunMode); +void LPM_EnterLowPowerIdle(lpm_power_mode_t curRunMode); +void LPM_ExitLowPowerIdle(lpm_power_mode_t curRunMode); void LPM_EnterSuspend(void); void LPM_EnterSNVS(void); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mbed_overrides.c index fbe9eb1..1e27ce2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mbed_overrides.c @@ -15,7 +15,7 @@ * limitations under the License. */ #include "pinmap.h" -#include "fsl_clock_config.h" +#include "clock_config.h" #include "fsl_clock.h" #include "fsl_xbara.h" #include "fsl_iomuxc.h" @@ -163,7 +163,13 @@ void mbed_sdk_init() { BOARD_ConfigMPU(); - BOARD_BootClockRUN(); + +#if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE + BOARD_ClockOverdrive(); +#else + BOARD_ClockFullSpeed(); +#endif + #if TARGET_EVK /* Since SNVS_PMIC_STBY_REQ_GPIO5_IO02 will output a high-level signal under Stop Mode(Suspend Mode) and this pin is @@ -347,3 +353,21 @@ return irqNumber; } +#if MBED_CONF_TARGET_ENABLE_OVERDRIVE_MODE +#define LPM_POWER_MODE LPM_PowerModeOverRun +#else +#define LPM_POWER_MODE LPM_PowerModeFullRun +#endif + +void vPortPRE_SLEEP_PROCESSING(clock_mode_t powermode) +{ + LPM_EnableWakeupSource(GPT2_IRQn); + LPM_EnterLowPowerIdle(LPM_POWER_MODE); +} + +void vPortPOST_SLEEP_PROCESSING(clock_mode_t powermode) +{ + LPM_ExitLowPowerIdle(LPM_POWER_MODE); + LPM_DisableWakeupSource(GPT2_IRQn); +} + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mimxrt_clock_adjustment.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mimxrt_clock_adjustment.c new file mode 100644 index 0000000..e5cdcef --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mimxrt_clock_adjustment.c @@ -0,0 +1,295 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Mbed: This file was imported from "specific.c" in the "power_mode_switch_bm" SDK example. + * It's responsible for switching around the clocks for low-power/full-speed/overdrive running. + * We modified it a bit to make it pull clock info from clock_config.h, so you don't have to enter + * clock configurations in two places. + * + * Not every clock configuration can be deduced, but it can at least pull in the dividers for + * IPG_CLK_ROOT, SEMC_CLK_ROOT, and PERCLK_CLK_ROOT. + * + * We also removed parts of the file that control the FlexSPI clock source, because we could + * not determine, based on available info, whether this might perturb the code flash (FlexSPI) + * clock timing. + * + * Note: This file has to be used instead of just calling the clock init functions in + * clock_config.c, because those functions turn off clocks for all the peripherals, + * which makes things like the UART and timers die (or even crash the entire chip if + * code tries to use them while they're unclocked). + */ + +#include "mimxrt_clock_adjustment.h" +#include "fsl_common.h" +#include "fsl_clock.h" +#include "lpm.h" +#include "fsl_iomuxc.h" +#include "clock_config.h" + +#include +#include + +/******************************************************************************* + * Code + ******************************************************************************/ + +AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode)); + +void SwitchSystemClocks(lpm_power_mode_t power_mode) +{ +#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + LPM_EnterCritical(); + while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) + { + } + FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; + + /* Disable clock gate of flexspi. */ + CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK); +#endif + + switch (power_mode) + { + case LPM_PowerModeOverRun: + CLOCK_SET_DIV(kCLOCK_SemcDiv, BOARD_CLOCKOVERDRIVE_AHB_CLK_ROOT / BOARD_CLOCKOVERDRIVE_SEMC_CLK_ROOT - 1); // Deduce SEMC divider from clock_config.h defines + /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */ + CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT / BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider + CLOCK_SET_DIV(kCLOCK_IpgDiv, BOARD_CLOCKOVERDRIVE_AHB_CLK_ROOT / BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT - 1); + CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); + CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK + CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL + CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK + + CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0, matches setting used by ROM bootloader + break; + case LPM_PowerModeFullRun: + CLOCK_SET_DIV(kCLOCK_SemcDiv, BOARD_CLOCKFULLSPEED_AHB_CLK_ROOT / BOARD_CLOCKFULLSPEED_SEMC_CLK_ROOT - 1); // Deduce SEMC divider from clock_config.h defines + /* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */ + CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT / BOARD_CLOCKFULLSPEED_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider + CLOCK_SET_DIV(kCLOCK_IpgDiv, BOARD_CLOCKFULLSPEED_AHB_CLK_ROOT / BOARD_CLOCKFULLSPEED_IPG_CLK_ROOT - 1); + CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); + CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK + CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL + CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK + + CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0, matches setting used by ROM bootloader + break; + case LPM_PowerModeLowPowerRun: + case LPM_PowerModeLPIdle: + CLOCK_SET_DIV(kCLOCK_PeriphClk2Div, 0); + CLOCK_SET_MUX(kCLOCK_PeriphClk2Mux, 1); // PERIPH_CLK2 mux to OSC + CLOCK_SET_MUX(kCLOCK_PeriphMux, 1); // PERIPH_CLK mux to PERIPH_CLK2 + CLOCK_SET_DIV(kCLOCK_SemcDiv, BOARD_CLOCKLOWPOWER_AHB_CLK_ROOT / BOARD_CLOCKLOWPOWER_SEMC_CLK_ROOT - 1); // Deduce SEMC divider from clock_config.h defines + CLOCK_SET_MUX(kCLOCK_SemcMux, 0); // SEMC mux to PERIPH_CLK + CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre + /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */ + CLOCK_SET_DIV(kCLOCK_PerclkDiv, BOARD_CLOCKLOWPOWER_IPG_CLK_ROOT / BOARD_CLOCKLOWPOWER_PERCLK_CLK_ROOT - 1); // Deduce PERCLK divider + CLOCK_SET_DIV(kCLOCK_IpgDiv, BOARD_CLOCKLOWPOWER_AHB_CLK_ROOT / BOARD_CLOCKLOWPOWER_IPG_CLK_ROOT - 1); + CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); + CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK + break; + default: + break; + } + +#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Enable clock gate of flexspi. */ + CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK); + + FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) + { + } + while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) + { + } + LPM_ExitCritical(); +#endif +} + +void ClockSetToOverDriveRun(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + + /* Init ARM PLL */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + CLOCK_InitArmPll(&armPllConfig_BOARD_ClockOverdrive); + + /* Init SYS PLL*/ + CLOCK_InitSysPll(&sysPllConfig_BOARD_ClockOverdrive); + + /* Init USB1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_ClockOverdrive); + + SwitchSystemClocks(LPM_PowerModeOverRun); +} + +void ClockSetToFullSpeedRun(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + + /* Init ARM PLL */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + CLOCK_InitArmPll(&armPllConfig_BOARD_ClockFullSpeed); + + /* Init SYS PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_ClockFullSpeed); + + /* Init USB1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_ClockFullSpeed); + + SwitchSystemClocks(LPM_PowerModeFullRun); +} + +void ClockSetToLowPowerRun(void) +{ + // CORE CLK mux to 24M before reconfigure PLLs + SwitchSystemClocks(LPM_PowerModeLowPowerRun); + + /* Deinit ARM PLL */ + CLOCK_DeinitArmPll(); + + /* Deinit SYS PLL */ + CLOCK_DeinitSysPll(); + + /* Power Down USB1 PLL */ + CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK; + CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK; + CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK; + + /* Deinit USB2 PLL */ + CLOCK_DeinitUsb2Pll(); + + /* Deinit AUDIO PLL */ + CLOCK_DeinitAudioPll(); + + /* Deinit VIDEO PLL */ + CLOCK_DeinitVideoPll(); + + /* Deinit ENET PLL */ + CLOCK_DeinitEnetPll(); +} + +#define GPR4_STOP_REQ_BITS \ + (IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) + +#define GPR4_STOP_ACK_BITS \ + (IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) + +#define GPR7_STOP_REQ_BITS \ + (IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK | \ + IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) + +#define GPR7_STOP_ACK_BITS \ + (IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK | \ + IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) + +#define GPR8_DOZE_BITS \ + (IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK | \ + IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) + +#define GPR8_STOP_MODE_BITS \ + (IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK | \ + IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) + +#define GPR12_DOZE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) + +#define GPR12_STOP_MODE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) + +void PeripheralEnterDozeMode(void) +{ + IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS; + IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS; +} + +void PeripheralExitDozeMode(void) +{ + IOMUXC_GPR->GPR8 = 0x00000000; + IOMUXC_GPR->GPR12 = 0x00000000; +} + +void PeripheralEnterStopMode(void) +{ + IOMUXC_GPR->GPR4 = IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK; + while ((IOMUXC_GPR->GPR4 & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) != IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) + { + } + IOMUXC_GPR->GPR4 = GPR4_STOP_REQ_BITS; + IOMUXC_GPR->GPR7 = GPR7_STOP_REQ_BITS; + IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS | GPR8_STOP_MODE_BITS; + IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS | GPR12_STOP_MODE_BITS; + while ((IOMUXC_GPR->GPR4 & GPR4_STOP_ACK_BITS) != GPR4_STOP_ACK_BITS) + { + } + while ((IOMUXC_GPR->GPR7 & GPR7_STOP_ACK_BITS) != GPR7_STOP_ACK_BITS) + { + } +} + +void APP_PrintRunFrequency(int32_t run_freq_only) +{ + printf("\r\n"); + printf("***********************************************************\r\n"); + printf("CPU: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_CpuClk)); + printf("AHB: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_AhbClk)); + printf("SEMC: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_SemcClk)); + printf("IPG: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_IpgClk)); + printf("PER: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_PerClk)); + printf("OSC: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_OscClk)); + printf("RTC: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_RtcClk)); + if (!run_freq_only) + { + printf("ARMPLL: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_ArmPllClk)); + printf("USB1PLL: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllClk)); + printf("USB1PLLPFD0: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk)); + printf("USB1PLLPFD1: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk)); + printf("USB1PLLPFD2: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd2Clk)); + printf("USB1PLLPFD3: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb1PllPfd3Clk)); + printf("USB2PLL: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_Usb2PllClk)); + printf("SYSPLL: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllClk)); + printf("SYSPLLPFD0: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd0Clk)); + printf("SYSPLLPFD1: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd1Clk)); + printf("SYSPLLPFD2: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk)); + printf("SYSPLLPFD3: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_SysPllPfd3Clk)); + printf("ENETPLL0: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_EnetPll0Clk)); + printf("ENETPLL1: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_EnetPll1Clk)); + printf("AUDIOPLL: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_AudioPllClk)); + printf("VIDEOPLL: %" PRIu32 " Hz\r\n", CLOCK_GetFreq(kCLOCK_VideoPllClk)); + } + printf("***********************************************************\r\n"); + printf("\r\n"); +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mimxrt_clock_adjustment.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mimxrt_clock_adjustment.h new file mode 100644 index 0000000..32b32e9 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/mimxrt_clock_adjustment.h @@ -0,0 +1,44 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _SPECIFIC_H_ +#define _SPECIFIC_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FLEXSPI_INST FLEXSPI +#define HAS_WAKEUP_PIN (1) +#define CCM_CLPCR_BYPASS_LPM_HS_BITS (CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK) + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void ClockSetToOverDriveRun(void); +void ClockSetToFullSpeedRun(void); +void ClockSetToLowSpeedRun(void); +void ClockSetToLowPowerRun(void); +void ClockSetToSystemIdle(void); +void ClockSetToLowPowerIdle(void); +void PeripheralEnterDozeMode(void); +void PeripheralExitDozeMode(void); +void PeripheralEnterStopMode(void); +void APP_PrintRunFrequency(int32_t run_freq_only); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _SPECIFIC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/serial_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/serial_api.c index 0af83e9..aada942 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/serial_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/serial_api.c @@ -28,7 +28,7 @@ #include "pinmap.h" #include "fsl_lpuart.h" #include "PeripheralPins.h" -#include "fsl_clock_config.h" +#include "clock_config.h" /* LPUART starts from index 1 */ static uint32_t serial_irq_ids[FSL_FEATURE_SOC_LPUART_COUNT + 1] = {0}; @@ -164,6 +164,30 @@ uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 4); } +void uart5_irq() +{ + uint32_t status_flags = LPUART5->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 5); +} + +void uart6_irq() +{ + uint32_t status_flags = LPUART6->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 6); +} + +void uart7_irq() +{ + uint32_t status_flags = LPUART7->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 7); +} + +void uart8_irq() +{ + uint32_t status_flags = LPUART8->STAT; + uart_irq((status_flags & kLPUART_TxDataRegEmptyFlag), (status_flags & kLPUART_RxDataRegFullFlag), 8); +} + void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -188,8 +212,20 @@ case 4: vector = (uint32_t)&uart4_irq; break; - default: + case 5: + vector = (uint32_t)&uart5_irq; break; + case 6: + vector = (uint32_t)&uart6_irq; + break; + case 7: + vector = (uint32_t)&uart7_irq; + break; + case 8: + vector = (uint32_t)&uart8_irq; + break; + default: + MBED_ASSERT(false); } if (enable) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.c deleted file mode 100644 index 5abd97c..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.c +++ /dev/null @@ -1,615 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "specific.h" -#include "fsl_common.h" -#include "fsl_clock.h" -#include "lpm.h" -#include "fsl_iomuxc.h" - -/******************************************************************************* - * Code - ******************************************************************************/ - -const clock_arm_pll_config_t armPllConfig_PowerMode = { - .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_sys_pll_config_t sysPllConfig_PowerMode = { - .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ - .numerator = 0, /* 30 bit numerator of fractional loop divider */ - .denominator = 1, /* 30 bit denominator of fractional loop divider */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; -const clock_usb_pll_config_t usb1PllConfig_PowerMode = { - .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ - .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ -}; - -AT_QUICKACCESS_SECTION_CODE(void SwitchSystemClocks(lpm_power_mode_t power_mode)); - -#define NUMBER_OF_CCM_GATE_REGS 7 -static uint32_t clock_gate_values[NUMBER_OF_CCM_GATE_REGS]; - -void SwitchSystemClocks(lpm_power_mode_t power_mode) -{ -#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) - { - } - FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; - - /* Disable clock gate of flexspi. */ - CCM->CCGR6 &= (~CCM_CCGR6_CG5_MASK); -#endif - switch (power_mode) - { - case LPM_PowerModeOverRun: - CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0 - /* CORE CLK to 600MHz, AHB, IPG to 150MHz, PERCLK to 75MHz */ - //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); - //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 3); // PRE_PERIPH_CLK mux to ARM PLL - CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK - break; - case LPM_PowerModeFullRun: - CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 3); // FLEXSPI mux to PLL3 PFD0 - /* CORE CLK to 528MHz, AHB, IPG to 132MHz, PERCLK to 66MHz */ - CLOCK_SET_DIV(kCLOCK_PerclkDiv, 1); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); - CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // PRE_PERIPH_CLK mux to SYS PLL - CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // PERIPH_CLK mux to PRE_PERIPH_CLK - break; - case LPM_PowerModeLowSpeedRun: - case LPM_PowerModeSysIdle: - CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz -#ifdef HYPERFLASH_BOOT - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode -#else - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 3); // FLEXSPI in SDR mode -#endif - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2 - /* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */ - CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 3); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 3); - CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - CLOCK_SET_MUX(kCLOCK_PrePeriphMux, 0); // Switch PRE_PERIPH_CLK to SYS PLL - CLOCK_SET_MUX(kCLOCK_PeriphMux, 0); // Switch PERIPH_CLK to PRE_PERIPH_CLK - break; - case LPM_PowerModeLowPowerRun: - case LPM_PowerModeLPIdle: - CLOCK_SET_DIV(kCLOCK_PeriphClk2Div, 0); - CLOCK_SET_MUX(kCLOCK_PeriphClk2Mux, 1); // PERIPH_CLK2 mux to OSC - CLOCK_SET_MUX(kCLOCK_PeriphMux, 1); // PERIPH_CLK mux to PERIPH_CLK2 - CLOCK_SET_DIV(kCLOCK_SemcDiv, 0); - CLOCK_SET_MUX(kCLOCK_SemcMux, 0); // SEMC mux to PERIPH_CLK - CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 0); // FLEXSPI in DDR mode - CLOCK_SET_MUX(kCLOCK_FlexspiMux, 0); // FLEXSPI mux to semc_clk_root_pre - /* CORE CLK to 24MHz and AHB, IPG, PERCLK to 12MHz */ - //CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0); - CLOCK_SET_DIV(kCLOCK_IpgDiv, 1); - CLOCK_SET_DIV(kCLOCK_AhbDiv, 0); - //CLOCK_SET_MUX(kCLOCK_PerclkMux, 0); // PERCLK mux to IPG CLK - break; - default: - break; - } - -#if (defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) - /* Enable clock gate of flexspi. */ - CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK); - -#ifdef HYPERFLASH_BOOT - if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode)) - { - FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19); - } - else - { - FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15); - } -#endif - - FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; - FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; - while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) - { - } - while (!((FLEXSPI_INST->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI_INST->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) - { - } -#endif -} - -void ClockSetToOverDriveRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - //ClockSelectXtalOsc(); - - /* Init ARM PLL */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - CLOCK_InitArmPll(&armPllConfig_PowerMode); - - /* Init SYS PLL*/ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - - /* Init USB1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; - - /* Init USB2 PLL*/ - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK; - while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - - /* Init AUDIO PLL */ - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - - /* Init VIDEO PLL */ - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - - /* Init ENET PLL */ - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeOverRun); - LPM_ExitCritical(); -} - -void ClockSetToFullSpeedRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectXtalOsc(); - - /* Init ARM PLL */ - CLOCK_SetDiv(kCLOCK_ArmDiv, 1); - CLOCK_InitArmPll(&armPllConfig_PowerMode); - - /* Init SYS PLL. */ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - /* Init System pfd0. */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); - /* Init System pfd1. */ - CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - /* Init System pfd3. */ - CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); - - /* Init USB1 PLL. */ - CLOCK_InitUsb1Pll(&usb1PllConfig_PowerMode); - /* Init Usb1 pfd0. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); - /* Init Usb1 pfd1. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); - /* Init Usb1 pfd2. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); - /* Init Usb1 pfd3. */ - CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); - /* Disable Usb1 PLL output for USBPHY1. */ - CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; - - /* Init USB2 PLL*/ - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_ENABLE_MASK; - CCM_ANALOG->PLL_USB2_SET = CCM_ANALOG_PLL_USB2_POWER_MASK; - while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_USB2_CLR = CCM_ANALOG_PLL_USB2_BYPASS_MASK; - - /* Init AUDIO PLL */ - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; - CCM_ANALOG->PLL_AUDIO_SET = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_AUDIO_CLR = CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; - - /* Init VIDEO PLL */ - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; - CCM_ANALOG->PLL_VIDEO_SET = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; - while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_VIDEO_CLR = CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; - - /* Init ENET PLL */ - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE_MASK; - CCM_ANALOG->PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; - while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) - { - } - CCM_ANALOG->PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS_MASK; - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeFullRun); - LPM_ExitCritical(); -} - -void ClockSetToLowSpeedRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectXtalOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Init SYS PLL */ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - - /* Deinit SYS PLL PFD 0 1 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Deinit USB1 PLL */ - CLOCK_DeinitUsb1Pll(); - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowSpeedRun); - LPM_ExitCritical(); -} - -void ClockSetToLowPowerRun(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectRcOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Deinit SYS PLL */ - CLOCK_DeinitSysPll(); - - /* Deinit SYS PLL PFD 0 1 2 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - CLOCK_DeinitSysPfd(kCLOCK_Pfd2); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Power Down USB1 PLL */ - CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_BYPASS_MASK; - CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_POWER_MASK; - CCM_ANALOG->PLL_USB1_CLR = CCM_ANALOG_PLL_USB1_ENABLE_MASK; - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); -} - -void ClockSetToSystemIdle(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - ClockSelectXtalOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Init SYS PLL */ - CLOCK_InitSysPll(&sysPllConfig_PowerMode); - - /* Deinit SYS PLL PFD 0 1 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - /* Init System pfd2. */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 18); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Deinit USB1 PLL */ - CLOCK_DeinitUsb1Pll(); - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeSysIdle); - LPM_ExitCritical(); -} - -void ClockSetToLowPowerIdle(void) -{ - // CORE CLK mux to 24M before reconfigure PLLs - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLowPowerRun); - LPM_ExitCritical(); - //ClockSelectRcOsc(); - - /* Deinit ARM PLL */ - CLOCK_DeinitArmPll(); - - /* Deinit SYS PLL */ - CLOCK_DeinitSysPll(); - - /* Deinit SYS PLL PFD 0 1 2 3 */ - CLOCK_DeinitSysPfd(kCLOCK_Pfd0); - CLOCK_DeinitSysPfd(kCLOCK_Pfd1); - CLOCK_DeinitSysPfd(kCLOCK_Pfd2); - CLOCK_DeinitSysPfd(kCLOCK_Pfd3); - - /* Deinit USB1 PLL */ - CLOCK_DeinitUsb1Pll(); - - /* Deinit USB1 PLL PFD 0 1 2 3 */ - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd0); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd1); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd2); - CLOCK_DeinitUsb1Pfd(kCLOCK_Pfd3); - - /* Deinit USB2 PLL */ - CLOCK_DeinitUsb2Pll(); - - /* Deinit AUDIO PLL */ - CLOCK_DeinitAudioPll(); - - /* Deinit VIDEO PLL */ - CLOCK_DeinitVideoPll(); - - /* Deinit ENET PLL */ - CLOCK_DeinitEnetPll(); - - LPM_EnterCritical(); - SwitchSystemClocks(LPM_PowerModeLPIdle); - LPM_ExitCritical(); -} - -void SetLowPowerClockGate(void) -{ - /* Save of the clock gate registers */ - clock_gate_values[0] = CCM->CCGR0; - clock_gate_values[1] = CCM->CCGR1; - clock_gate_values[2] = CCM->CCGR2; - clock_gate_values[3] = CCM->CCGR3; - clock_gate_values[4] = CCM->CCGR4; - clock_gate_values[5] = CCM->CCGR5; - clock_gate_values[6] = CCM->CCGR6; - - /* Set low power gate values */ - CCM->CCGR0 = CCM_CCGR0_CG0(1) | CCM_CCGR0_CG1(1) | CCM_CCGR0_CG3(3) | CCM_CCGR0_CG11(1) | CCM_CCGR0_CG12(1); - CCM->CCGR1 = CCM_CCGR1_CG9(3) | CCM_CCGR1_CG10(1) | CCM_CCGR1_CG13(1) | CCM_CCGR1_CG14(1) | CCM_CCGR1_CG15(1); - CCM->CCGR2 = CCM_CCGR2_CG2(1) | CCM_CCGR2_CG8(1) | CCM_CCGR2_CG9(1) | CCM_CCGR2_CG10(1); - CCM->CCGR3 = CCM_CCGR3_CG2(1) | CCM_CCGR3_CG4(1) | CCM_CCGR3_CG9(1) | CCM_CCGR3_CG14(3) | CCM_CCGR3_CG15(1); - CCM->CCGR4 = - CCM_CCGR4_CG1(1) | CCM_CCGR4_CG2(1) | CCM_CCGR4_CG4(1) | CCM_CCGR4_CG5(1) | CCM_CCGR4_CG6(1) | CCM_CCGR4_CG7(1); - CCM->CCGR5 = CCM_CCGR5_CG0(1) | CCM_CCGR5_CG1(1) | CCM_CCGR5_CG4(1) | CCM_CCGR5_CG6(1) | CCM_CCGR5_CG12(1) | - CCM_CCGR5_CG14(1) | CCM_CCGR5_CG15(1); - /* We can enable DCDC when need to config it and close it after configuration */ - CCM->CCGR6 = CCM_CCGR6_CG3(1) | CCM_CCGR6_CG4(1) | CCM_CCGR6_CG5(1) | CCM_CCGR6_CG9(1) | CCM_CCGR6_CG10(1) | - CCM_CCGR6_CG11(1); -} - -void SetRestoreClockGate(void) -{ - CCM->CCGR0 = clock_gate_values[0]; - CCM->CCGR1 = clock_gate_values[1]; - CCM->CCGR2 = clock_gate_values[2]; - CCM->CCGR3 = clock_gate_values[3]; - CCM->CCGR4 = clock_gate_values[4]; - CCM->CCGR5 = clock_gate_values[5]; - CCM->CCGR6 = clock_gate_values[6]; -} - -void PowerDownUSBPHY(void) -{ - USBPHY1->CTRL = 0xFFFFFFFF; - USBPHY2->CTRL = 0xFFFFFFFF; -} - -void ConfigUartRxPinToGpio(void) -{ - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, 0); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_GPIO1_IO13, - IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2) | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK); -} - -void ReConfigUartRxPin(void) -{ - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, IOMUXC_SW_PAD_CTL_PAD_SPEED(2)); -} - -#define GPR4_STOP_REQ_BITS \ - (IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK | IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) - -#define GPR4_STOP_ACK_BITS \ - (IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK | IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK | IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK | IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) - -#define GPR7_STOP_REQ_BITS \ - (IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK | \ - IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) - -#define GPR7_STOP_ACK_BITS \ - (IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK | \ - IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK | IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) - -#define GPR8_DOZE_BITS \ - (IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK | \ - IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK | IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) - -#define GPR8_STOP_MODE_BITS \ - (IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK | \ - IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) - -#define GPR12_DOZE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) - -#define GPR12_STOP_MODE_BITS (IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK | IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) - -void PeripheralEnterDozeMode(void) -{ - IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS; - IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS; -} - -void PeripheralExitDozeMode(void) -{ - IOMUXC_GPR->GPR8 = 0x00000000; - IOMUXC_GPR->GPR12 = 0x00000000; -} - -void PeripheralEnterStopMode(void) -{ - IOMUXC_GPR->GPR4 = IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK; - while ((IOMUXC_GPR->GPR4 & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) != IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) - { - } - IOMUXC_GPR->GPR4 = GPR4_STOP_REQ_BITS; - IOMUXC_GPR->GPR7 = GPR7_STOP_REQ_BITS; - IOMUXC_GPR->GPR8 = GPR8_DOZE_BITS | GPR8_STOP_MODE_BITS; - IOMUXC_GPR->GPR12 = GPR12_DOZE_BITS | GPR12_STOP_MODE_BITS; - while ((IOMUXC_GPR->GPR4 & GPR4_STOP_ACK_BITS) != GPR4_STOP_ACK_BITS) - { - } - while ((IOMUXC_GPR->GPR7 & GPR7_STOP_ACK_BITS) != GPR7_STOP_ACK_BITS) - { - } -} - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.h deleted file mode 100644 index cc384b4..0000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/specific.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _SPECIFIC_H_ -#define _SPECIFIC_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#define FLEXSPI_INST FLEXSPI -#define HAS_WAKEUP_PIN (1) - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -void ClockSetToOverDriveRun(void); -void ClockSetToFullSpeedRun(void); -void ClockSetToLowSpeedRun(void); -void ClockSetToLowPowerRun(void); -void ClockSetToSystemIdle(void); -void ClockSetToLowPowerIdle(void); - -void SetLowPowerClockGate(void); -void SetRestoreClockGate(void); -void PowerDownUSBPHY(void); -void ConfigUartRxPinToGpio(void); -void ReConfigUartRxPin(void); -void PeripheralEnterDozeMode(void); -void PeripheralExitDozeMode(void); -void PeripheralEnterStopMode(void); -void APP_PrintRunFrequency(int32_t run_freq_only); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _SPECIFIC_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker.c index 87c0dcc..57897e9 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/us_ticker.c @@ -18,7 +18,7 @@ #include "us_ticker_api.h" #include "us_ticker_defines.h" #include "fsl_pit.h" -#include "fsl_clock_config.h" +#include "clock_config.h" const ticker_info_t* us_ticker_get_info() { diff --git a/targets/targets.json b/targets/targets.json index 0a9c9c5..99d3dd9 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5085,7 +5085,8 @@ "STDIO_MESSAGES", "TRNG", "WATCHDOG", - "USBDEVICE" + "USBDEVICE", + "LPTICKER" ], "features": [ "LWIP" @@ -5093,8 +5094,14 @@ "device_name": "MIMXRT1052", "overrides": { "deep-sleep-latency": 10 - } - }, + }, + "config": { + "enable-overdrive-mode": { + "help": "Enable 'overdrive mode' and raise core clock from 528MHz to 600MHz. Only allowed on MIMXRT10xxD parts, not MIMXRT10xxC", + "value": 1 + } + } + }, "MIMXRT1050_EVK": { "inherits": [ "MIMXRT105X" @@ -5110,10 +5117,9 @@ "XIP_BOOT_HEADER_DCD_ENABLE=1", "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE", "MIMXRT105X_BOARD_HAS_EXTERNAL_RAM=1", - "MIMXRT105X_EXTERNAL_RAM_SIZE=0x01E00000" + "MIMXRT105X_EXTERNAL_RAM_SIZE=0x02000000" ], "device_has_add": [ - "LPTICKER", "FLASH" ], "detect_code": [ diff --git a/tools/cmake/profiles/release.cmake b/tools/cmake/profiles/release.cmake index 877dd18..feec05f 100644 --- a/tools/cmake/profiles/release.cmake +++ b/tools/cmake/profiles/release.cmake @@ -7,7 +7,6 @@ if(${mbed_toolchain} STREQUAL "GCC_ARM") list(APPEND profile_c_compile_options - "-c" "-Os" ) target_compile_options(${target} @@ -16,7 +15,6 @@ ) list(APPEND profile_cxx_compile_options - "-c" "-fno-rtti" "-Wvla" "-Os" @@ -27,7 +25,6 @@ ) list(APPEND profile_asm_compile_options - "-c" "-x" "assembler-with-cpp" ) target_compile_options(${target}