diff --git a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.S b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.S new file mode 100644 index 0000000..99fbbf3 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.S @@ -0,0 +1,268 @@ +;/* +; * BEETLE CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +; +; This file is derivative of CMSIS V5.00 startup_ARMCM3.s +; +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_Handler ; UART 0 RX and TX Handler + DCD Spare_IRQ_Handler ; Undefined + DCD UART1_Handler ; UART 1 RX and TX Handler + DCD I2C0_Handler ; I2C 0 Handler + DCD I2C1_Handler ; I2C 1 Handler + DCD RTC_Handler ; RTC Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI0_Handler ; SPI 0 Handler + DCD UARTOVF_Handler ; UART 0,1 Overflow Handler + DCD SPI1_Handler ; SPI 1 Handler + DCD QSPI_Handler ; QSPI Handler + DCD DMA_Handler ; DMA handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD SysError_Handler ; System Error (Flash Cache) + DCD EFLASH_Handler ; Embedded Flash + DCD LLCC_TXCMD_EMPTY_Handler ; LLCC_TXCMDIRQ + DCD LLCC_TXEVT_EMPTY_Handler ; LLCC_TXEVTIRQ + DCD LLCC_TXDMAH_DONE_Handler ; LLCC_TXDMA0IRQ + DCD LLCC_TXDMAL_DONE_Handler ; LLCC_TXDMA1IRQ + DCD LLCC_RXCMD_VALID_Handler ; LLCC_RXCMDIRQ + DCD LLCC_RXEVT_VALID_Handler ; LLCC_RXEVTIRQ + DCD LLCC_RXDMAH_DONE_Handler ; LLCC_RXDMA0IRQ + DCD LLCC_RXDMAL_DONE_Handler ; LLCC_RXDMA1IRQ + DCD PORT2_COMB_Handler ; GPIO 2 + DCD PORT3_COMB_Handler ; GPIO 3 + DCD TRNG_Handler ; TRNG +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UART0_Handler [WEAK] + EXPORT Spare_IRQ_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI0_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT SPI1_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + EXPORT SysError_Handler [WEAK] + EXPORT EFLASH_Handler [WEAK] + EXPORT LLCC_TXEVT_EMPTY_Handler [WEAK] + EXPORT LLCC_TXCMD_EMPTY_Handler [WEAK] + EXPORT LLCC_RXEVT_VALID_Handler [WEAK] + EXPORT LLCC_RXCMD_VALID_Handler [WEAK] + EXPORT LLCC_TXDMAL_DONE_Handler [WEAK] + EXPORT LLCC_RXDMAL_DONE_Handler [WEAK] + EXPORT LLCC_TXDMAH_DONE_Handler [WEAK] + EXPORT LLCC_RXDMAH_DONE_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + +UART0_Handler +Spare_IRQ_Handler +UART1_Handler +I2C0_Handler +I2C1_Handler +RTC_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI0_Handler +UARTOVF_Handler +SPI1_Handler +QSPI_Handler +DMA_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler +SysError_Handler +EFLASH_Handler +LLCC_TXEVT_EMPTY_Handler +LLCC_TXCMD_EMPTY_Handler +LLCC_RXEVT_VALID_Handler +LLCC_RXCMD_VALID_Handler +LLCC_TXDMAL_DONE_Handler +LLCC_RXDMAL_DONE_Handler +LLCC_TXDMAH_DONE_Handler +LLCC_RXDMAH_DONE_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +TRNG_Handler + B . + + ENDP + + + ALIGN + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.s b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.s deleted file mode 100644 index 99fbbf3..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.s +++ /dev/null @@ -1,268 +0,0 @@ -;/* -; * BEETLE CMSIS Library -; */ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of CMSIS V5.00 startup_ARMCM3.s -; -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -__initial_sp EQU 0x20020000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UART0_Handler ; UART 0 RX and TX Handler - DCD Spare_IRQ_Handler ; Undefined - DCD UART1_Handler ; UART 1 RX and TX Handler - DCD I2C0_Handler ; I2C 0 Handler - DCD I2C1_Handler ; I2C 1 Handler - DCD RTC_Handler ; RTC Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI0_Handler ; SPI 0 Handler - DCD UARTOVF_Handler ; UART 0,1 Overflow Handler - DCD SPI1_Handler ; SPI 1 Handler - DCD QSPI_Handler ; QSPI Handler - DCD DMA_Handler ; DMA handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler - DCD SysError_Handler ; System Error (Flash Cache) - DCD EFLASH_Handler ; Embedded Flash - DCD LLCC_TXCMD_EMPTY_Handler ; LLCC_TXCMDIRQ - DCD LLCC_TXEVT_EMPTY_Handler ; LLCC_TXEVTIRQ - DCD LLCC_TXDMAH_DONE_Handler ; LLCC_TXDMA0IRQ - DCD LLCC_TXDMAL_DONE_Handler ; LLCC_TXDMA1IRQ - DCD LLCC_RXCMD_VALID_Handler ; LLCC_RXCMDIRQ - DCD LLCC_RXEVT_VALID_Handler ; LLCC_RXEVTIRQ - DCD LLCC_RXDMAH_DONE_Handler ; LLCC_RXDMA0IRQ - DCD LLCC_RXDMAL_DONE_Handler ; LLCC_RXDMA1IRQ - DCD PORT2_COMB_Handler ; GPIO 2 - DCD PORT3_COMB_Handler ; GPIO 3 - DCD TRNG_Handler ; TRNG -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UART0_Handler [WEAK] - EXPORT Spare_IRQ_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI0_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT SPI1_Handler [WEAK] - EXPORT QSPI_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] - EXPORT SysError_Handler [WEAK] - EXPORT EFLASH_Handler [WEAK] - EXPORT LLCC_TXEVT_EMPTY_Handler [WEAK] - EXPORT LLCC_TXCMD_EMPTY_Handler [WEAK] - EXPORT LLCC_RXEVT_VALID_Handler [WEAK] - EXPORT LLCC_RXCMD_VALID_Handler [WEAK] - EXPORT LLCC_TXDMAL_DONE_Handler [WEAK] - EXPORT LLCC_RXDMAL_DONE_Handler [WEAK] - EXPORT LLCC_TXDMAH_DONE_Handler [WEAK] - EXPORT LLCC_RXDMAH_DONE_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - -UART0_Handler -Spare_IRQ_Handler -UART1_Handler -I2C0_Handler -I2C1_Handler -RTC_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI0_Handler -UARTOVF_Handler -SPI1_Handler -QSPI_Handler -DMA_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler -SysError_Handler -EFLASH_Handler -LLCC_TXEVT_EMPTY_Handler -LLCC_TXCMD_EMPTY_Handler -LLCC_RXEVT_VALID_Handler -LLCC_RXCMD_VALID_Handler -LLCC_TXDMAL_DONE_Handler -LLCC_RXDMAL_DONE_Handler -LLCC_TXDMAH_DONE_Handler -LLCC_RXDMAH_DONE_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -TRNG_Handler - B . - - ENDP - - - ALIGN - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.S b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.S new file mode 100644 index 0000000..9fcf1e6 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.S @@ -0,0 +1,421 @@ +;/* +; * BEETLE CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UART0_Handler ; 0: UART 0 RX and TX Handler + DCD Spare_IRQ_Handler ; 1: Undefined + DCD UART1_Handler ; 2: UART 1 RX and TX Handler + DCD I2C0_Handler ; 3: I2C 0 Handler + DCD I2C1_Handler ; 4: I2C 1 Handler + DCD RTC_Handler ; 5: RTC Handler + DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; 8: TIMER 0 handler + DCD TIMER1_Handler ; 9: TIMER 1 handler + DCD DUALTIMER_HANDLER ; 10: Dual timer handler + DCD SPI0_Handler ; 11: SPI 0 Handler + DCD UARTOVF_Handler ; 12: UART 0,1 Overflow Handler + DCD SPI1_Handler ; 13: SPI 1 Handler + DCD QSPI_Handler ; 14: QSPI Handler + DCD DMA_Handler ; 15: DMA handler + DCD PORT0_0_Handler ; 16: GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; 17: GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; 18: GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; 19: GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; 20: GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; 21: GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; 22: GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; 23: GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; 24: GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; 25: GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; 26: GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; 27: GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; 28: GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; 29: GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; 30: GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; 31: GPIO Port 0 pin 15 Handler + DCD SysError_Handler ; 32: System Error (Flash Cache) + DCD EFLASH_Handler ; 33: Embedded Flash + DCD LLCC_TXCMD_EMPTY_Handler ; 34: LLCC_TXCMDIRQ + DCD LLCC_TXEVT_EMPTY_Handler ; 35: LLCC_TXEVTIRQ + DCD LLCC_TXDMAH_DONE_Handler ; 36: LLCC_TXDMA0IRQ + DCD LLCC_TXDMAL_DONE_Handler ; 37: LLCC_TXDMA1IRQ + DCD LLCC_RXCMD_VALID_Handler ; 38: LLCC_RXCMDIRQ + DCD LLCC_RXEVT_VALID_Handler ; 39: LLCC_RXEVTIRQ + DCD LLCC_RXDMAH_DONE_Handler ; 40: LLCC_RXDMA0IRQ + DCD LLCC_RXDMAL_DONE_Handler ; 41: LLCC_RXDMA1IRQ + DCD PORT2_COMB_Handler ; 42: GPIO 2 + DCD PORT3_COMB_Handler ; 43: GPIO 3 + DCD TRNG_Handler ; 44: TRNG +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B SecureFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK Spare_IRQ_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +Spare_IRQ_Handler + B Spare_IRQ_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK PORT0_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_COMB_Handler + B PORT0_COMB_Handler + + PUBWEAK PORT1_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_COMB_Handler + B PORT1_COMB_Handler + + PUBWEAK TIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_Handler + B TIMER0_Handler + + PUBWEAK TIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_Handler + B TIMER1_Handler + + PUBWEAK DUALTIMER_HANDLER + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_HANDLER + B DUALTIMER_HANDLER + + PUBWEAK SPI0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_Handler + B SPI0_Handler + + PUBWEAK UARTOVF_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_Handler + B UARTOVF_Handler + + PUBWEAK SPI1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_Handler + B SPI1_Handler + + PUBWEAK QSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +QSPI_Handler + B QSPI_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK PORT0_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_Handler + B PORT0_0_Handler + + PUBWEAK PORT0_1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_Handler + B PORT0_1_Handler + + PUBWEAK PORT0_2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_Handler + B PORT0_2_Handler + + PUBWEAK PORT0_3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_Handler + B PORT0_3_Handler + + PUBWEAK PORT0_4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_Handler + B PORT0_4_Handler + + PUBWEAK PORT0_5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_Handler + B PORT0_5_Handler + + PUBWEAK PORT0_6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_Handler + B PORT0_6_Handler + + PUBWEAK PORT0_7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_Handler + B PORT0_7_Handler + + PUBWEAK PORT0_8_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_8_Handler + B PORT0_8_Handler + + PUBWEAK PORT0_9_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_9_Handler + B PORT0_9_Handler + + PUBWEAK PORT0_10_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_10_Handler + B PORT0_10_Handler + + PUBWEAK PORT0_11_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_11_Handler + B PORT0_11_Handler + + PUBWEAK PORT0_12_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_12_Handler + B PORT0_12_Handler + + PUBWEAK PORT0_13_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_13_Handler + B PORT0_13_Handler + + PUBWEAK PORT0_14_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_14_Handler + B PORT0_14_Handler + + PUBWEAK PORT0_15_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_15_Handler + B PORT0_15_Handler + + PUBWEAK SysError_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysError_Handler + B SysError_Handler + + PUBWEAK EFLASH_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EFLASH_Handler + B EFLASH_Handler + + PUBWEAK LLCC_TXCMD_EMPTY_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXCMD_EMPTY_Handler + B LLCC_TXCMD_EMPTY_Handler + + PUBWEAK LLCC_TXEVT_EMPTY_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXEVT_EMPTY_Handler + B LLCC_TXEVT_EMPTY_Handler + + PUBWEAK LLCC_TXDMAH_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXDMAH_DONE_Handler + B LLCC_TXDMAH_DONE_Handler + + PUBWEAK LLCC_TXDMAL_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXDMAL_DONE_Handler + B LLCC_TXDMAL_DONE_Handler + + PUBWEAK LLCC_RXCMD_VALID_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXCMD_VALID_Handler + B LLCC_RXCMD_VALID_Handler + + PUBWEAK LLCC_RXEVT_VALID_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXEVT_VALID_Handler + B LLCC_RXEVT_VALID_Handler + + PUBWEAK LLCC_RXDMAH_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXDMAH_DONE_Handler + B LLCC_RXDMAH_DONE_Handler + + PUBWEAK LLCC_RXDMAL_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXDMAL_DONE_Handler + B LLCC_RXDMAL_DONE_Handler + + PUBWEAK PORT2_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_COMB_Handler + B PORT2_COMB_Handler + + PUBWEAK PORT3_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_COMB_Handler + B PORT3_COMB_Handler + + PUBWEAK TRNG_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG_Handler + B TRNG_Handler + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.s b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.s deleted file mode 100644 index 9fcf1e6..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.s +++ /dev/null @@ -1,421 +0,0 @@ -;/* -; * BEETLE CMSIS Library -; */ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -;/* -; * This file is derivative of CMSIS V5.00 startup_Device.s -; */ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD UART0_Handler ; 0: UART 0 RX and TX Handler - DCD Spare_IRQ_Handler ; 1: Undefined - DCD UART1_Handler ; 2: UART 1 RX and TX Handler - DCD I2C0_Handler ; 3: I2C 0 Handler - DCD I2C1_Handler ; 4: I2C 1 Handler - DCD RTC_Handler ; 5: RTC Handler - DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; 8: TIMER 0 handler - DCD TIMER1_Handler ; 9: TIMER 1 handler - DCD DUALTIMER_HANDLER ; 10: Dual timer handler - DCD SPI0_Handler ; 11: SPI 0 Handler - DCD UARTOVF_Handler ; 12: UART 0,1 Overflow Handler - DCD SPI1_Handler ; 13: SPI 1 Handler - DCD QSPI_Handler ; 14: QSPI Handler - DCD DMA_Handler ; 15: DMA handler - DCD PORT0_0_Handler ; 16: GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; 17: GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; 18: GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; 19: GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; 20: GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; 21: GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; 22: GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; 23: GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; 24: GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; 25: GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; 26: GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; 27: GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; 28: GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; 29: GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; 30: GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; 31: GPIO Port 0 pin 15 Handler - DCD SysError_Handler ; 32: System Error (Flash Cache) - DCD EFLASH_Handler ; 33: Embedded Flash - DCD LLCC_TXCMD_EMPTY_Handler ; 34: LLCC_TXCMDIRQ - DCD LLCC_TXEVT_EMPTY_Handler ; 35: LLCC_TXEVTIRQ - DCD LLCC_TXDMAH_DONE_Handler ; 36: LLCC_TXDMA0IRQ - DCD LLCC_TXDMAL_DONE_Handler ; 37: LLCC_TXDMA1IRQ - DCD LLCC_RXCMD_VALID_Handler ; 38: LLCC_RXCMDIRQ - DCD LLCC_RXEVT_VALID_Handler ; 39: LLCC_RXEVTIRQ - DCD LLCC_RXDMAH_DONE_Handler ; 40: LLCC_RXDMA0IRQ - DCD LLCC_RXDMAL_DONE_Handler ; 41: LLCC_RXDMA1IRQ - DCD PORT2_COMB_Handler ; 42: GPIO 2 - DCD PORT3_COMB_Handler ; 43: GPIO 3 - DCD TRNG_Handler ; 44: TRNG -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B SecureFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK Spare_IRQ_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -Spare_IRQ_Handler - B Spare_IRQ_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK PORT0_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_COMB_Handler - B PORT0_COMB_Handler - - PUBWEAK PORT1_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_COMB_Handler - B PORT1_COMB_Handler - - PUBWEAK TIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_Handler - B TIMER0_Handler - - PUBWEAK TIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_Handler - B TIMER1_Handler - - PUBWEAK DUALTIMER_HANDLER - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER_HANDLER - B DUALTIMER_HANDLER - - PUBWEAK SPI0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI0_Handler - B SPI0_Handler - - PUBWEAK UARTOVF_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UARTOVF_Handler - B UARTOVF_Handler - - PUBWEAK SPI1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_Handler - B SPI1_Handler - - PUBWEAK QSPI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -QSPI_Handler - B QSPI_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK PORT0_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_0_Handler - B PORT0_0_Handler - - PUBWEAK PORT0_1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_1_Handler - B PORT0_1_Handler - - PUBWEAK PORT0_2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_2_Handler - B PORT0_2_Handler - - PUBWEAK PORT0_3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_3_Handler - B PORT0_3_Handler - - PUBWEAK PORT0_4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_4_Handler - B PORT0_4_Handler - - PUBWEAK PORT0_5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_5_Handler - B PORT0_5_Handler - - PUBWEAK PORT0_6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_6_Handler - B PORT0_6_Handler - - PUBWEAK PORT0_7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_7_Handler - B PORT0_7_Handler - - PUBWEAK PORT0_8_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_8_Handler - B PORT0_8_Handler - - PUBWEAK PORT0_9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_9_Handler - B PORT0_9_Handler - - PUBWEAK PORT0_10_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_10_Handler - B PORT0_10_Handler - - PUBWEAK PORT0_11_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_11_Handler - B PORT0_11_Handler - - PUBWEAK PORT0_12_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_12_Handler - B PORT0_12_Handler - - PUBWEAK PORT0_13_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_13_Handler - B PORT0_13_Handler - - PUBWEAK PORT0_14_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_14_Handler - B PORT0_14_Handler - - PUBWEAK PORT0_15_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_15_Handler - B PORT0_15_Handler - - PUBWEAK SysError_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysError_Handler - B SysError_Handler - - PUBWEAK EFLASH_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EFLASH_Handler - B EFLASH_Handler - - PUBWEAK LLCC_TXCMD_EMPTY_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXCMD_EMPTY_Handler - B LLCC_TXCMD_EMPTY_Handler - - PUBWEAK LLCC_TXEVT_EMPTY_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXEVT_EMPTY_Handler - B LLCC_TXEVT_EMPTY_Handler - - PUBWEAK LLCC_TXDMAH_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXDMAH_DONE_Handler - B LLCC_TXDMAH_DONE_Handler - - PUBWEAK LLCC_TXDMAL_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXDMAL_DONE_Handler - B LLCC_TXDMAL_DONE_Handler - - PUBWEAK LLCC_RXCMD_VALID_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXCMD_VALID_Handler - B LLCC_RXCMD_VALID_Handler - - PUBWEAK LLCC_RXEVT_VALID_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXEVT_VALID_Handler - B LLCC_RXEVT_VALID_Handler - - PUBWEAK LLCC_RXDMAH_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXDMAH_DONE_Handler - B LLCC_RXDMAH_DONE_Handler - - PUBWEAK LLCC_RXDMAL_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXDMAL_DONE_Handler - B LLCC_RXDMAL_DONE_Handler - - PUBWEAK PORT2_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_COMB_Handler - B PORT2_COMB_Handler - - PUBWEAK PORT3_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_COMB_Handler - B PORT3_COMB_Handler - - PUBWEAK TRNG_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -TRNG_Handler - B TRNG_Handler - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S new file mode 100644 index 0000000..93c14e2 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S @@ -0,0 +1,308 @@ +/* + * MPS2 CMSIS Library + * + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * This file is derivative of CMSIS V5.00 startup_ARMCM3.s + * +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + */ + + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt + DCD Spare_IRQHandler ; 1:Undefined + DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt + DCD APB_Slave0_IRQHandler ; 3:Reserved for APB Slave + DCD APB_Slave1_IRQHandler ; 4:Reserved for APB Slave + DCD RTC_IRQHandler ; 5:RTC Interrupt + DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt + DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt + DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt + DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt + DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt + DCD APB_Slave2_IRQHandler ; 11:Reserved for APB Slave + DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt + DCD APB_Slave3_IRQHandler ; 13:Reserved for APB Slave + DCD RESERVED0_IRQHandler ; 14:Reserved + DCD TSC_IRQHandler ; 15:Touch Screen Interrupt + DCD PORT0_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler + DCD PORT0_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler + DCD PORT0_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler + DCD PORT0_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler + DCD PORT0_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler + DCD PORT0_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler + DCD PORT0_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler + DCD PORT0_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler + DCD PORT0_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler + DCD PORT0_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler + DCD PORT0_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler + DCD PORT0_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler + DCD PORT0_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler + DCD PORT0_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler + DCD PORT0_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler + DCD PORT0_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler + DCD FLASH0_IRQHandler ; 32:Reserved for Flash + DCD FLASH1_IRQHandler ; 33:Reserved for Flash + DCD RESERVED1_IRQHandler ; 34:Reserved + DCD RESERVED2_IRQHandler ; 35:Reserved + DCD RESERVED3_IRQHandler ; 36:Reserved + DCD RESERVED4_IRQHandler ; 37:Reserved + DCD RESERVED5_IRQHandler ; 38:Reserved + DCD RESERVED6_IRQHandler ; 39:Reserved + DCD RESERVED7_IRQHandler ; 40:Reserved + DCD RESERVED8_IRQHandler ; 41:Reserved + DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt + DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt + DCD TRNG_IRQHandler ; 44:Random number generator Interrupt + DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt + DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt + DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. + DCD I2S_IRQHandler ; 48:I2S Interrupt + DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) + DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) + DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) + DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) + DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) + DCD PORT4_ALL_IRQHandler ; 54:GPIO Port 4 combined Interrupt + DCD PORT5_ALL_IRQHandler ; 55:GPIO Port 5 combined Interrupt + DCD UART4_IRQHandler ; 56:UART 4 RX and TX Combined Interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt + EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined + EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt + EXPORT APB_Slave0_IRQHandler [WEAK] ; 3:Reserved for APB Slave + EXPORT APB_Slave1_IRQHandler [WEAK] ; 4:Reserved for APB Slave + EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt + EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt + EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt + EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt + EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt + EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt + EXPORT APB_Slave2_IRQHandler [WEAK] ; 11:Reserved for APB Slave + EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt + EXPORT APB_Slave3_IRQHandler [WEAK] ; 13:Reserved for APB Slave + EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved + EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt + EXPORT PORT0_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler + EXPORT PORT0_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler + EXPORT PORT0_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler + EXPORT PORT0_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler + EXPORT PORT0_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler + EXPORT PORT0_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler + EXPORT PORT0_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler + EXPORT PORT0_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler + EXPORT PORT0_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler + EXPORT PORT0_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler + EXPORT PORT0_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler + EXPORT PORT0_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler + EXPORT PORT0_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler + EXPORT PORT0_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler + EXPORT PORT0_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler + EXPORT PORT0_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler + EXPORT FLASH0_IRQHandler [WEAK] ; 32:Reserved for Flash + EXPORT FLASH1_IRQHandler [WEAK] ; 33:Reserved for Flash + EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved + EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved + EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved + EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved + EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved + EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved + EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved + EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved + EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt + EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt + EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt + EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt + EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt + EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a. + EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt + EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header) + EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd) + EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement) + EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement) + EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1) + EXPORT PORT4_ALL_IRQHandler [WEAK] ; 54:GPIO Port 4 combined Interrupt + EXPORT PORT5_ALL_IRQHandler [WEAK] ; 55:GPIO Port 5 combined Interrupt + EXPORT UART4_IRQHandler [WEAK] ; 56:UART 4 RX and TX Combined Interrupt + +UART0_IRQHandler +Spare_IRQHandler +UART1_IRQHandler +APB_Slave0_IRQHandler +APB_Slave1_IRQHandler +RTC_IRQHandler +PORT0_IRQHandler +PORT1_ALL_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +DUALTIMER_IRQHandler +APB_Slave2_IRQHandler +UARTOVF_IRQHandler +APB_Slave3_IRQHandler +RESERVED0_IRQHandler +TSC_IRQHandler +PORT0_0_IRQHandler +PORT0_1_IRQHandler +PORT0_2_IRQHandler +PORT0_3_IRQHandler +PORT0_4_IRQHandler +PORT0_5_IRQHandler +PORT0_6_IRQHandler +PORT0_7_IRQHandler +PORT0_8_IRQHandler +PORT0_9_IRQHandler +PORT0_10_IRQHandler +PORT0_11_IRQHandler +PORT0_12_IRQHandler +PORT0_13_IRQHandler +PORT0_14_IRQHandler +PORT0_15_IRQHandler +FLASH0_IRQHandler +FLASH1_IRQHandler +RESERVED1_IRQHandler +RESERVED2_IRQHandler +RESERVED3_IRQHandler +RESERVED4_IRQHandler +RESERVED5_IRQHandler +RESERVED6_IRQHandler +RESERVED7_IRQHandler +RESERVED8_IRQHandler +PORT2_ALL_IRQHandler +PORT3_ALL_IRQHandler +TRNG_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +ETHERNET_IRQHandler +I2S_IRQHandler +MPS2_SPI0_IRQHandler +MPS2_SPI1_IRQHandler +MPS2_SPI2_IRQHandler +MPS2_SPI3_IRQHandler +MPS2_SPI4_IRQHandler +PORT4_ALL_IRQHandler +PORT5_ALL_IRQHandler +UART4_IRQHandler + + B . + + ENDP + + + ALIGN + + + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.s b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.s deleted file mode 100644 index 93c14e2..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ /dev/null @@ -1,308 +0,0 @@ -/* - * MPS2 CMSIS Library - * - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * - * This file is derivative of CMSIS V5.00 startup_ARMCM3.s - * -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ - */ - - -__initial_sp EQU 0x20020000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt - DCD Spare_IRQHandler ; 1:Undefined - DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt - DCD APB_Slave0_IRQHandler ; 3:Reserved for APB Slave - DCD APB_Slave1_IRQHandler ; 4:Reserved for APB Slave - DCD RTC_IRQHandler ; 5:RTC Interrupt - DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt - DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt - DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt - DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt - DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt - DCD APB_Slave2_IRQHandler ; 11:Reserved for APB Slave - DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt - DCD APB_Slave3_IRQHandler ; 13:Reserved for APB Slave - DCD RESERVED0_IRQHandler ; 14:Reserved - DCD TSC_IRQHandler ; 15:Touch Screen Interrupt - DCD PORT0_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler - DCD PORT0_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler - DCD PORT0_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler - DCD PORT0_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler - DCD PORT0_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler - DCD PORT0_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler - DCD PORT0_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler - DCD PORT0_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler - DCD PORT0_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler - DCD PORT0_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler - DCD PORT0_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler - DCD PORT0_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler - DCD PORT0_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler - DCD PORT0_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler - DCD PORT0_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler - DCD PORT0_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler - DCD FLASH0_IRQHandler ; 32:Reserved for Flash - DCD FLASH1_IRQHandler ; 33:Reserved for Flash - DCD RESERVED1_IRQHandler ; 34:Reserved - DCD RESERVED2_IRQHandler ; 35:Reserved - DCD RESERVED3_IRQHandler ; 36:Reserved - DCD RESERVED4_IRQHandler ; 37:Reserved - DCD RESERVED5_IRQHandler ; 38:Reserved - DCD RESERVED6_IRQHandler ; 39:Reserved - DCD RESERVED7_IRQHandler ; 40:Reserved - DCD RESERVED8_IRQHandler ; 41:Reserved - DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt - DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt - DCD TRNG_IRQHandler ; 44:Random number generator Interrupt - DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt - DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt - DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. - DCD I2S_IRQHandler ; 48:I2S Interrupt - DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) - DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) - DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) - DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) - DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) - DCD PORT4_ALL_IRQHandler ; 54:GPIO Port 4 combined Interrupt - DCD PORT5_ALL_IRQHandler ; 55:GPIO Port 5 combined Interrupt - DCD UART4_IRQHandler ; 56:UART 4 RX and TX Combined Interrupt - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt - EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined - EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt - EXPORT APB_Slave0_IRQHandler [WEAK] ; 3:Reserved for APB Slave - EXPORT APB_Slave1_IRQHandler [WEAK] ; 4:Reserved for APB Slave - EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt - EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt - EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt - EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt - EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt - EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt - EXPORT APB_Slave2_IRQHandler [WEAK] ; 11:Reserved for APB Slave - EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt - EXPORT APB_Slave3_IRQHandler [WEAK] ; 13:Reserved for APB Slave - EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved - EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt - EXPORT PORT0_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler - EXPORT PORT0_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler - EXPORT PORT0_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler - EXPORT PORT0_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler - EXPORT PORT0_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler - EXPORT PORT0_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler - EXPORT PORT0_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler - EXPORT PORT0_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler - EXPORT PORT0_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler - EXPORT PORT0_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler - EXPORT PORT0_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler - EXPORT PORT0_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler - EXPORT PORT0_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler - EXPORT PORT0_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler - EXPORT PORT0_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler - EXPORT PORT0_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler - EXPORT FLASH0_IRQHandler [WEAK] ; 32:Reserved for Flash - EXPORT FLASH1_IRQHandler [WEAK] ; 33:Reserved for Flash - EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved - EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved - EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved - EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved - EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved - EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved - EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved - EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved - EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt - EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt - EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt - EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt - EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt - EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a. - EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt - EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header) - EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd) - EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement) - EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement) - EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1) - EXPORT PORT4_ALL_IRQHandler [WEAK] ; 54:GPIO Port 4 combined Interrupt - EXPORT PORT5_ALL_IRQHandler [WEAK] ; 55:GPIO Port 5 combined Interrupt - EXPORT UART4_IRQHandler [WEAK] ; 56:UART 4 RX and TX Combined Interrupt - -UART0_IRQHandler -Spare_IRQHandler -UART1_IRQHandler -APB_Slave0_IRQHandler -APB_Slave1_IRQHandler -RTC_IRQHandler -PORT0_IRQHandler -PORT1_ALL_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -DUALTIMER_IRQHandler -APB_Slave2_IRQHandler -UARTOVF_IRQHandler -APB_Slave3_IRQHandler -RESERVED0_IRQHandler -TSC_IRQHandler -PORT0_0_IRQHandler -PORT0_1_IRQHandler -PORT0_2_IRQHandler -PORT0_3_IRQHandler -PORT0_4_IRQHandler -PORT0_5_IRQHandler -PORT0_6_IRQHandler -PORT0_7_IRQHandler -PORT0_8_IRQHandler -PORT0_9_IRQHandler -PORT0_10_IRQHandler -PORT0_11_IRQHandler -PORT0_12_IRQHandler -PORT0_13_IRQHandler -PORT0_14_IRQHandler -PORT0_15_IRQHandler -FLASH0_IRQHandler -FLASH1_IRQHandler -RESERVED1_IRQHandler -RESERVED2_IRQHandler -RESERVED3_IRQHandler -RESERVED4_IRQHandler -RESERVED5_IRQHandler -RESERVED6_IRQHandler -RESERVED7_IRQHandler -RESERVED8_IRQHandler -PORT2_ALL_IRQHandler -PORT3_ALL_IRQHandler -TRNG_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -ETHERNET_IRQHandler -I2S_IRQHandler -MPS2_SPI0_IRQHandler -MPS2_SPI1_IRQHandler -MPS2_SPI2_IRQHandler -MPS2_SPI3_IRQHandler -MPS2_SPI4_IRQHandler -PORT4_ALL_IRQHandler -PORT5_ALL_IRQHandler -UART4_IRQHandler - - B . - - ENDP - - - ALIGN - - - - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/startup_MPS2.S new file mode 100644 index 0000000..46e4eba --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/startup_MPS2.S @@ -0,0 +1,490 @@ +;/* +; * MPS2 CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt + DCD Spare_IRQHandler ; 1:Undefined + DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt + DCD APB_Slave0_IRQHandler ; 3:Reserved for APB Slave + DCD APB_Slave1_IRQHandler ; 4:Reserved for APB Slave + DCD RTC_IRQHandler ; 5:RTC Interrupt + DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt + DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt + DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt + DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt + DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt + DCD APB_Slave2_IRQHandler ; 11:Reserved for APB Slave + DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt + DCD APB_Slave3_IRQHandler ; 13:Reserved for APB Slave + DCD RESERVED0_IRQHandler ; 14:Reserved + DCD TSC_IRQHandler ; 15:Touch Screen Interrupt + DCD PORT0_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler + DCD PORT0_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler + DCD PORT0_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler + DCD PORT0_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler + DCD PORT0_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler + DCD PORT0_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler + DCD PORT0_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler + DCD PORT0_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler + DCD PORT0_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler + DCD PORT0_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler + DCD PORT0_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler + DCD PORT0_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler + DCD PORT0_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler + DCD PORT0_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler + DCD PORT0_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler + DCD PORT0_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler + DCD FLASH0_IRQHandler ; 32:Reserved for Flash + DCD FLASH1_IRQHandler ; 33:Reserved for Flash + DCD RESERVED1_IRQHandler ; 34:Reserved + DCD RESERVED2_IRQHandler ; 35:Reserved + DCD RESERVED3_IRQHandler ; 36:Reserved + DCD RESERVED4_IRQHandler ; 37:Reserved + DCD RESERVED5_IRQHandler ; 38:Reserved + DCD RESERVED6_IRQHandler ; 39:Reserved + DCD RESERVED7_IRQHandler ; 40:Reserved + DCD RESERVED8_IRQHandler ; 41:Reserved + DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt + DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt + DCD TRNG_IRQHandler ; 44:Random number generator Interrupt + DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt + DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt + DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. + DCD I2S_IRQHandler ; 48:I2S Interrupt + DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) + DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) + DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) + DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) + DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) + DCD PORT4_ALL_IRQHandler ; 54:GPIO Port 4 combined Interrupt + DCD PORT5_ALL_IRQHandler ; 55:GPIO Port 5 combined Interrupt + DCD UART4_IRQHandler ; 56:UART 4 RX and TX Combined Interrupt + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_IRQHandler + B UART0_IRQHandler + + PUBWEAK Spare_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Spare_IRQHandler + B Spare_IRQHandler + + PUBWEAK UART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_IRQHandler + B UART1_IRQHandler + + PUBWEAK APB_Slave0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +APB_Slave0_IRQHandler + B APB_Slave0_IRQHandler + + PUBWEAK APB_Slave1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +APB_Slave1_IRQHandler + B APB_Slave1_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK PORT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_IRQHandler + B PORT0_IRQHandler + + PUBWEAK PORT1_ALL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_ALL_IRQHandler + B PORT1_ALL_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK DUALTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_IRQHandler + B DUALTIMER_IRQHandler + + PUBWEAK APB_Slave2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +APB_Slave2_IRQHandler + B APB_Slave2_IRQHandler + + PUBWEAK UARTOVF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_IRQHandler + B UARTOVF_IRQHandler + + PUBWEAK APB_Slave3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +APB_Slave3_IRQHandler + B APB_Slave3_IRQHandler + + PUBWEAK RESERVED0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED0_IRQHandler + B RESERVED0_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK PORT0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_IRQHandler + B PORT0_0_IRQHandler + + PUBWEAK PORT0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_IRQHandler + B PORT0_1_IRQHandler + + PUBWEAK PORT0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_IRQHandler + B PORT0_2_IRQHandler + + PUBWEAK PORT0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_IRQHandler + B PORT0_3_IRQHandler + + PUBWEAK PORT0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_IRQHandler + B PORT0_4_IRQHandler + + PUBWEAK PORT0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_IRQHandler + B PORT0_5_IRQHandler + + PUBWEAK PORT0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_IRQHandler + B PORT0_6_IRQHandler + + PUBWEAK PORT0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_IRQHandler + B PORT0_7_IRQHandler + + PUBWEAK PORT0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_8_IRQHandler + B PORT0_8_IRQHandler + + PUBWEAK PORT0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_9_IRQHandler + B PORT0_9_IRQHandler + + PUBWEAK PORT0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_10_IRQHandler + B PORT0_10_IRQHandler + + PUBWEAK PORT0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_11_IRQHandler + B PORT0_11_IRQHandler + + PUBWEAK PORT0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_12_IRQHandler + B PORT0_12_IRQHandler + + PUBWEAK PORT0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_13_IRQHandler + B PORT0_13_IRQHandler + + PUBWEAK PORT0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_14_IRQHandler + B PORT0_14_IRQHandler + + PUBWEAK PORT0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_15_IRQHandler + B PORT0_15_IRQHandler + + PUBWEAK FLASH0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH0_IRQHandler + B FLASH0_IRQHandler + + PUBWEAK FLASH1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH1_IRQHandler + B FLASH1_IRQHandler + + PUBWEAK RESERVED1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED1_IRQHandler + B RESERVED1_IRQHandler + + PUBWEAK RESERVED2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED2_IRQHandler + B RESERVED2_IRQHandler + + PUBWEAK RESERVED3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED3_IRQHandler + B RESERVED3_IRQHandler + + PUBWEAK RESERVED4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED4_IRQHandler + B RESERVED4_IRQHandler + + PUBWEAK RESERVED5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED5_IRQHandler + B RESERVED5_IRQHandler + + PUBWEAK RESERVED6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED6_IRQHandler + B RESERVED6_IRQHandler + + PUBWEAK RESERVED7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED7_IRQHandler + B RESERVED7_IRQHandler + + PUBWEAK RESERVED8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RESERVED8_IRQHandler + B RESERVED8_IRQHandler + + PUBWEAK PORT2_ALL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_ALL_IRQHandler + B PORT2_ALL_IRQHandler + + PUBWEAK PORT3_ALL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_ALL_IRQHandler + B PORT3_ALL_IRQHandler + + PUBWEAK TRNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG_IRQHandler + B TRNG_IRQHandler + + PUBWEAK UART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_IRQHandler + B UART2_IRQHandler + + PUBWEAK UART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART3_IRQHandler + B UART3_IRQHandler + + PUBWEAK ETHERNET_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETHERNET_IRQHandler + B ETHERNET_IRQHandler + + PUBWEAK I2S_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2S_IRQHandler + B I2S_IRQHandler + + PUBWEAK MPS2_SPI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MPS2_SPI0_IRQHandler + B MPS2_SPI0_IRQHandler + + PUBWEAK MPS2_SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MPS2_SPI1_IRQHandler + B MPS2_SPI1_IRQHandler + + PUBWEAK MPS2_SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MPS2_SPI2_IRQHandler + B MPS2_SPI2_IRQHandler + + PUBWEAK MPS2_SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MPS2_SPI3_IRQHandler + B MPS2_SPI3_IRQHandler + + PUBWEAK MPS2_SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MPS2_SPI4_IRQHandler + B MPS2_SPI4_IRQHandler + + PUBWEAK PORT4_ALL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT4_ALL_IRQHandler + B PORT4_ALL_IRQHandler + + PUBWEAK PORT5_ALL_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT5_ALL_IRQHandler + B PORT5_ALL_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/startup_MPS2.s b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/startup_MPS2.s deleted file mode 100644 index 46e4eba..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/startup_MPS2.s +++ /dev/null @@ -1,490 +0,0 @@ -;/* -; * MPS2 CMSIS Library -; */ -;/* -; * Copyright (c) 2009-2017 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -;/* -; * This file is derivative of CMSIS V5.00 startup_Device.s -; */ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt - DCD Spare_IRQHandler ; 1:Undefined - DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt - DCD APB_Slave0_IRQHandler ; 3:Reserved for APB Slave - DCD APB_Slave1_IRQHandler ; 4:Reserved for APB Slave - DCD RTC_IRQHandler ; 5:RTC Interrupt - DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt - DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt - DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt - DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt - DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt - DCD APB_Slave2_IRQHandler ; 11:Reserved for APB Slave - DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt - DCD APB_Slave3_IRQHandler ; 13:Reserved for APB Slave - DCD RESERVED0_IRQHandler ; 14:Reserved - DCD TSC_IRQHandler ; 15:Touch Screen Interrupt - DCD PORT0_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler - DCD PORT0_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler - DCD PORT0_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler - DCD PORT0_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler - DCD PORT0_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler - DCD PORT0_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler - DCD PORT0_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler - DCD PORT0_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler - DCD PORT0_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler - DCD PORT0_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler - DCD PORT0_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler - DCD PORT0_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler - DCD PORT0_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler - DCD PORT0_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler - DCD PORT0_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler - DCD PORT0_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler - DCD FLASH0_IRQHandler ; 32:Reserved for Flash - DCD FLASH1_IRQHandler ; 33:Reserved for Flash - DCD RESERVED1_IRQHandler ; 34:Reserved - DCD RESERVED2_IRQHandler ; 35:Reserved - DCD RESERVED3_IRQHandler ; 36:Reserved - DCD RESERVED4_IRQHandler ; 37:Reserved - DCD RESERVED5_IRQHandler ; 38:Reserved - DCD RESERVED6_IRQHandler ; 39:Reserved - DCD RESERVED7_IRQHandler ; 40:Reserved - DCD RESERVED8_IRQHandler ; 41:Reserved - DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt - DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt - DCD TRNG_IRQHandler ; 44:Random number generator Interrupt - DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt - DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt - DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. - DCD I2S_IRQHandler ; 48:I2S Interrupt - DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) - DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) - DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) - DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) - DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) - DCD PORT4_ALL_IRQHandler ; 54:GPIO Port 4 combined Interrupt - DCD PORT5_ALL_IRQHandler ; 55:GPIO Port 5 combined Interrupt - DCD UART4_IRQHandler ; 56:UART 4 RX and TX Combined Interrupt - -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_IRQHandler - B UART0_IRQHandler - - PUBWEAK Spare_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -Spare_IRQHandler - B Spare_IRQHandler - - PUBWEAK UART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_IRQHandler - B UART1_IRQHandler - - PUBWEAK APB_Slave0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -APB_Slave0_IRQHandler - B APB_Slave0_IRQHandler - - PUBWEAK APB_Slave1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -APB_Slave1_IRQHandler - B APB_Slave1_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK PORT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_IRQHandler - B PORT0_IRQHandler - - PUBWEAK PORT1_ALL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_ALL_IRQHandler - B PORT1_ALL_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK DUALTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER_IRQHandler - B DUALTIMER_IRQHandler - - PUBWEAK APB_Slave2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -APB_Slave2_IRQHandler - B APB_Slave2_IRQHandler - - PUBWEAK UARTOVF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UARTOVF_IRQHandler - B UARTOVF_IRQHandler - - PUBWEAK APB_Slave3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -APB_Slave3_IRQHandler - B APB_Slave3_IRQHandler - - PUBWEAK RESERVED0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED0_IRQHandler - B RESERVED0_IRQHandler - - PUBWEAK TSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TSC_IRQHandler - B TSC_IRQHandler - - PUBWEAK PORT0_0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_0_IRQHandler - B PORT0_0_IRQHandler - - PUBWEAK PORT0_1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_1_IRQHandler - B PORT0_1_IRQHandler - - PUBWEAK PORT0_2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_2_IRQHandler - B PORT0_2_IRQHandler - - PUBWEAK PORT0_3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_3_IRQHandler - B PORT0_3_IRQHandler - - PUBWEAK PORT0_4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_4_IRQHandler - B PORT0_4_IRQHandler - - PUBWEAK PORT0_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_5_IRQHandler - B PORT0_5_IRQHandler - - PUBWEAK PORT0_6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_6_IRQHandler - B PORT0_6_IRQHandler - - PUBWEAK PORT0_7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_7_IRQHandler - B PORT0_7_IRQHandler - - PUBWEAK PORT0_8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_8_IRQHandler - B PORT0_8_IRQHandler - - PUBWEAK PORT0_9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_9_IRQHandler - B PORT0_9_IRQHandler - - PUBWEAK PORT0_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_10_IRQHandler - B PORT0_10_IRQHandler - - PUBWEAK PORT0_11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_11_IRQHandler - B PORT0_11_IRQHandler - - PUBWEAK PORT0_12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_12_IRQHandler - B PORT0_12_IRQHandler - - PUBWEAK PORT0_13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_13_IRQHandler - B PORT0_13_IRQHandler - - PUBWEAK PORT0_14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_14_IRQHandler - B PORT0_14_IRQHandler - - PUBWEAK PORT0_15_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_15_IRQHandler - B PORT0_15_IRQHandler - - PUBWEAK FLASH0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH0_IRQHandler - B FLASH0_IRQHandler - - PUBWEAK FLASH1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH1_IRQHandler - B FLASH1_IRQHandler - - PUBWEAK RESERVED1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED1_IRQHandler - B RESERVED1_IRQHandler - - PUBWEAK RESERVED2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED2_IRQHandler - B RESERVED2_IRQHandler - - PUBWEAK RESERVED3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED3_IRQHandler - B RESERVED3_IRQHandler - - PUBWEAK RESERVED4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED4_IRQHandler - B RESERVED4_IRQHandler - - PUBWEAK RESERVED5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED5_IRQHandler - B RESERVED5_IRQHandler - - PUBWEAK RESERVED6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED6_IRQHandler - B RESERVED6_IRQHandler - - PUBWEAK RESERVED7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED7_IRQHandler - B RESERVED7_IRQHandler - - PUBWEAK RESERVED8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RESERVED8_IRQHandler - B RESERVED8_IRQHandler - - PUBWEAK PORT2_ALL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_ALL_IRQHandler - B PORT2_ALL_IRQHandler - - PUBWEAK PORT3_ALL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_ALL_IRQHandler - B PORT3_ALL_IRQHandler - - PUBWEAK TRNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TRNG_IRQHandler - B TRNG_IRQHandler - - PUBWEAK UART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_IRQHandler - B UART2_IRQHandler - - PUBWEAK UART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART3_IRQHandler - B UART3_IRQHandler - - PUBWEAK ETHERNET_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETHERNET_IRQHandler - B ETHERNET_IRQHandler - - PUBWEAK I2S_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2S_IRQHandler - B I2S_IRQHandler - - PUBWEAK MPS2_SPI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MPS2_SPI0_IRQHandler - B MPS2_SPI0_IRQHandler - - PUBWEAK MPS2_SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MPS2_SPI1_IRQHandler - B MPS2_SPI1_IRQHandler - - PUBWEAK MPS2_SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MPS2_SPI2_IRQHandler - B MPS2_SPI2_IRQHandler - - PUBWEAK MPS2_SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MPS2_SPI3_IRQHandler - B MPS2_SPI3_IRQHandler - - PUBWEAK MPS2_SPI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MPS2_SPI4_IRQHandler - B MPS2_SPI4_IRQHandler - - PUBWEAK PORT4_ALL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT4_ALL_IRQHandler - B PORT4_ALL_IRQHandler - - PUBWEAK PORT5_ALL_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT5_ALL_IRQHandler - B PORT5_ALL_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.S new file mode 100644 index 0000000..8ff44c3 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.S @@ -0,0 +1,358 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_BEID.s +; @brief CMSIS Core Device Startup File for +; CMSDK_BEID Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt + DCD Spare_IRQHandler ; 1:Undefined + DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt + DCD I2C0_IRQHandler ; 3:I2C 0 Interrupt + DCD I2C1_IRQHandler ; 4:I2C 1 Interrupt + DCD RTC_IRQHandler ; 5:RTC Interrupt + DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt + DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt + DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt + DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt + DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt + DCD SPI0_IRQHandler ; 11:SPI 0 Interrupt + DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt + DCD SPI1_IRQHandler ; 13:SPI 1 Interrupt + DCD RESERVED0_IRQHandler ; 14:Reserved + DCD TSC_IRQHandler ; 15:Touch Screen Interrupt + DCD PORT01_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler + DCD PORT01_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler + DCD PORT01_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler + DCD PORT01_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler + DCD PORT01_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler + DCD PORT01_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler + DCD PORT01_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler + DCD PORT01_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler + DCD PORT01_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler + DCD PORT01_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler + DCD PORT01_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler + DCD PORT01_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler + DCD PORT01_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler + DCD PORT01_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler + DCD PORT01_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler + DCD PORT01_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler + DCD SYSERROR_IRQHandler ; 32:System Error Interrupt + DCD EFLASH_IRQHandler ; 33:Embedded Flash Interrupt + DCD RESERVED1_IRQHandler ; 34:Reserved + DCD RESERVED2_IRQHandler ; 35:Reserved + DCD RESERVED3_IRQHandler ; 36:Reserved + DCD RESERVED4_IRQHandler ; 37:Reserved + DCD RESERVED5_IRQHandler ; 38:Reserved + DCD RESERVED6_IRQHandler ; 39:Reserved + DCD RESERVED7_IRQHandler ; 40:Reserved + DCD RESERVED8_IRQHandler ; 41:Reserved + DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt + DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt + DCD TRNG_IRQHandler ; 44:Random number generator Interrupt + DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt + DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt + DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. + DCD I2S_IRQHandler ; 48:I2S Interrupt + DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) + DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) + DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) + DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) + DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt + EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined + EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt + EXPORT I2C0_IRQHandler [WEAK] ; 3:I2C 0 Interrupt + EXPORT I2C1_IRQHandler [WEAK] ; 4:I2C 1 Interrupt + EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt + EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt + EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt + EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt + EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt + EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt + EXPORT SPI0_IRQHandler [WEAK] ; 11:SPI 0 Interrupt + EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt + EXPORT SPI1_IRQHandler [WEAK] ; 13:SPI 1 Interrupt + EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved + EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt + EXPORT PORT01_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler + EXPORT PORT01_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler + EXPORT PORT01_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler + EXPORT PORT01_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler + EXPORT PORT01_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler + EXPORT PORT01_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler + EXPORT PORT01_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler + EXPORT PORT01_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler + EXPORT PORT01_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler + EXPORT PORT01_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler + EXPORT PORT01_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler + EXPORT PORT01_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler + EXPORT PORT01_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler + EXPORT PORT01_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler + EXPORT PORT01_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler + EXPORT PORT01_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler + EXPORT SYSERROR_IRQHandler [WEAK] ; 32:System Error Interrupt + EXPORT EFLASH_IRQHandler [WEAK] ; 33:Embedded Flash Interrupt + EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved + EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved + EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved + EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved + EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved + EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved + EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved + EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved + EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt + EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt + EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt + EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt + EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt + EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a. + EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt + EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header) + EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd) + EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement) + EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement) + EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1) + +UART0_IRQHandler +Spare_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +RTC_IRQHandler +PORT0_IRQHandler +PORT1_ALL_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +DUALTIMER_IRQHandler +SPI0_IRQHandler +UARTOVF_IRQHandler +SPI1_IRQHandler +RESERVED0_IRQHandler +TSC_IRQHandler +PORT01_0_IRQHandler +PORT01_1_IRQHandler +PORT01_2_IRQHandler +PORT01_3_IRQHandler +PORT01_4_IRQHandler +PORT01_5_IRQHandler +PORT01_6_IRQHandler +PORT01_7_IRQHandler +PORT01_8_IRQHandler +PORT01_9_IRQHandler +PORT01_10_IRQHandler +PORT01_11_IRQHandler +PORT01_12_IRQHandler +PORT01_13_IRQHandler +PORT01_14_IRQHandler +PORT01_15_IRQHandler +SYSERROR_IRQHandler +EFLASH_IRQHandler +RESERVED1_IRQHandler +RESERVED2_IRQHandler +RESERVED3_IRQHandler +RESERVED4_IRQHandler +RESERVED5_IRQHandler +RESERVED6_IRQHandler +RESERVED7_IRQHandler +RESERVED8_IRQHandler +PORT2_ALL_IRQHandler +PORT3_ALL_IRQHandler +TRNG_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +ETHERNET_IRQHandler +I2S_IRQHandler +MPS2_SPI0_IRQHandler +MPS2_SPI1_IRQHandler +MPS2_SPI2_IRQHandler +MPS2_SPI3_IRQHandler +MPS2_SPI4_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.s b/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.s deleted file mode 100644 index 8ff44c3..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ /dev/null @@ -1,358 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_BEID.s -; @brief CMSIS Core Device Startup File for -; CMSDK_BEID Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt - DCD Spare_IRQHandler ; 1:Undefined - DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt - DCD I2C0_IRQHandler ; 3:I2C 0 Interrupt - DCD I2C1_IRQHandler ; 4:I2C 1 Interrupt - DCD RTC_IRQHandler ; 5:RTC Interrupt - DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt - DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt - DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt - DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt - DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt - DCD SPI0_IRQHandler ; 11:SPI 0 Interrupt - DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt - DCD SPI1_IRQHandler ; 13:SPI 1 Interrupt - DCD RESERVED0_IRQHandler ; 14:Reserved - DCD TSC_IRQHandler ; 15:Touch Screen Interrupt - DCD PORT01_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler - DCD PORT01_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler - DCD PORT01_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler - DCD PORT01_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler - DCD PORT01_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler - DCD PORT01_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler - DCD PORT01_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler - DCD PORT01_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler - DCD PORT01_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler - DCD PORT01_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler - DCD PORT01_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler - DCD PORT01_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler - DCD PORT01_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler - DCD PORT01_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler - DCD PORT01_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler - DCD PORT01_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler - DCD SYSERROR_IRQHandler ; 32:System Error Interrupt - DCD EFLASH_IRQHandler ; 33:Embedded Flash Interrupt - DCD RESERVED1_IRQHandler ; 34:Reserved - DCD RESERVED2_IRQHandler ; 35:Reserved - DCD RESERVED3_IRQHandler ; 36:Reserved - DCD RESERVED4_IRQHandler ; 37:Reserved - DCD RESERVED5_IRQHandler ; 38:Reserved - DCD RESERVED6_IRQHandler ; 39:Reserved - DCD RESERVED7_IRQHandler ; 40:Reserved - DCD RESERVED8_IRQHandler ; 41:Reserved - DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt - DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt - DCD TRNG_IRQHandler ; 44:Random number generator Interrupt - DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt - DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt - DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. - DCD I2S_IRQHandler ; 48:I2S Interrupt - DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) - DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) - DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) - DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) - DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt - EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined - EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt - EXPORT I2C0_IRQHandler [WEAK] ; 3:I2C 0 Interrupt - EXPORT I2C1_IRQHandler [WEAK] ; 4:I2C 1 Interrupt - EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt - EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt - EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt - EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt - EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt - EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt - EXPORT SPI0_IRQHandler [WEAK] ; 11:SPI 0 Interrupt - EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt - EXPORT SPI1_IRQHandler [WEAK] ; 13:SPI 1 Interrupt - EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved - EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt - EXPORT PORT01_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler - EXPORT PORT01_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler - EXPORT PORT01_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler - EXPORT PORT01_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler - EXPORT PORT01_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler - EXPORT PORT01_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler - EXPORT PORT01_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler - EXPORT PORT01_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler - EXPORT PORT01_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler - EXPORT PORT01_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler - EXPORT PORT01_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler - EXPORT PORT01_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler - EXPORT PORT01_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler - EXPORT PORT01_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler - EXPORT PORT01_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler - EXPORT PORT01_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler - EXPORT SYSERROR_IRQHandler [WEAK] ; 32:System Error Interrupt - EXPORT EFLASH_IRQHandler [WEAK] ; 33:Embedded Flash Interrupt - EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved - EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved - EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved - EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved - EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved - EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved - EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved - EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved - EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt - EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt - EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt - EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt - EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt - EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a. - EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt - EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header) - EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd) - EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement) - EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement) - EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1) - -UART0_IRQHandler -Spare_IRQHandler -UART1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -RTC_IRQHandler -PORT0_IRQHandler -PORT1_ALL_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -DUALTIMER_IRQHandler -SPI0_IRQHandler -UARTOVF_IRQHandler -SPI1_IRQHandler -RESERVED0_IRQHandler -TSC_IRQHandler -PORT01_0_IRQHandler -PORT01_1_IRQHandler -PORT01_2_IRQHandler -PORT01_3_IRQHandler -PORT01_4_IRQHandler -PORT01_5_IRQHandler -PORT01_6_IRQHandler -PORT01_7_IRQHandler -PORT01_8_IRQHandler -PORT01_9_IRQHandler -PORT01_10_IRQHandler -PORT01_11_IRQHandler -PORT01_12_IRQHandler -PORT01_13_IRQHandler -PORT01_14_IRQHandler -PORT01_15_IRQHandler -SYSERROR_IRQHandler -EFLASH_IRQHandler -RESERVED1_IRQHandler -RESERVED2_IRQHandler -RESERVED3_IRQHandler -RESERVED4_IRQHandler -RESERVED5_IRQHandler -RESERVED6_IRQHandler -RESERVED7_IRQHandler -RESERVED8_IRQHandler -PORT2_ALL_IRQHandler -PORT3_ALL_IRQHandler -TRNG_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -ETHERNET_IRQHandler -I2S_IRQHandler -MPS2_SPI0_IRQHandler -MPS2_SPI1_IRQHandler -MPS2_SPI2_IRQHandler -MPS2_SPI3_IRQHandler -MPS2_SPI4_IRQHandler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.S new file mode 100644 index 0000000..71dff7d --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.S @@ -0,0 +1,270 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM0.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM0 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.s b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.s deleted file mode 100644 index 71dff7d..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ /dev/null @@ -1,270 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM0.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM0 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S new file mode 100644 index 0000000..df56e01 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S @@ -0,0 +1,270 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM0P.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM0P Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.s b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.s deleted file mode 100644 index df56e01..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ /dev/null @@ -1,270 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM0P.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM0P Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.S new file mode 100644 index 0000000..282a082 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.S @@ -0,0 +1,290 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM3.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM3 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.s b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.s deleted file mode 100644 index 282a082..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ /dev/null @@ -1,290 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM3.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM3 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.S new file mode 100644 index 0000000..29a1f32 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.S @@ -0,0 +1,290 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM4.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM4 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.s b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.s deleted file mode 100644 index 29a1f32..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.s +++ /dev/null @@ -1,290 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM4.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM4 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S new file mode 100644 index 0000000..d119289 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S @@ -0,0 +1,290 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM7.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM7 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s deleted file mode 100644 index d119289..0000000 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s +++ /dev/null @@ -1,290 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM7.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM7 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S new file mode 100644 index 0000000..1b8b9ba --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s deleted file mode 100644 index 1b8b9ba..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S new file mode 100644 index 0000000..1b8b9ba --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s deleted file mode 100644 index 1b8b9ba..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S new file mode 100644 index 0000000..1b8b9ba --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s deleted file mode 100644 index 1b8b9ba..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S new file mode 100644 index 0000000..1b8b9ba --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s deleted file mode 100644 index 1b8b9ba..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s +++ /dev/null @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S new file mode 100644 index 0000000..ee5d737 --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S @@ -0,0 +1,194 @@ +;/**************************************************************************//** +; * @file startup_SAML21.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAML21 Device Series +; * @version V1.00 +; * @date 10. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ;Top of RAM + + PRESERVE8 + THUMB + + +;Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ;Top of Stack + DCD Reset_Handler ;Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator + DCD WDT_Handler ;1 Watchdog Timer + DCD RTC_Handler ;2 Real-Time Counter + DCD EIC_Handler ;3 External Interrupt Controller + DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller + DCD DMAC_Handler ;5 Direct Memory Access Controller + DCD USB_Handler ;6 Universal Serial Bus + DCD EVSYS_Handler ;7 Event System Interface + DCD SERCOM0_Handler ;8 Serial Communication Interface 0 + DCD SERCOM1_Handler ;9 Serial Communication Interface 1 + DCD SERCOM2_Handler ;10 Serial Communication Interface 2 + DCD SERCOM3_Handler ;11 Serial Communication Interface 3 + DCD SERCOM4_Handler ;12 Serial Communication Interface 4 + DCD SERCOM5_Handler ;13 Serial Communication Interface 5 + DCD TCC0_Handler ;14 Timer Counter Control 0 + DCD TCC1_Handler ;15 Timer Counter Control 1 + DCD TCC2_Handler ;16 Timer Counter Control 2 + DCD TC0_Handler ;17 Basic Timer Counter 0 + DCD TC1_Handler ;18 Basic Timer Counter 1 + DCD TC2_Handler ;19 Basic Timer Counter 2 + DCD TC3_Handler ;20 Basic Timer Counter 3 + DCD TC4_Handler ;21 Basic Timer Counter 4 + DCD ADC_Handler ;22 Analog Digital Converter + DCD AC_Handler ;23 Analog Comparators + DCD DAC_Handler ;24 Digital-to-Analog Converter + DCD PTC_Handler ;25 Peripheral Touch Controller + DCD AES_Handler ;26 Advanced Encryption Standard + DCD TRNG_Handler ;27 True Random Generator + DCD PICOP_Handler ;28 PicoProcessor +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +;Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +;Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SYSTEM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT PICOP_Handler [WEAK] + +SYSTEM_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +AES_Handler +TRNG_Handler +PICOP_Handler + B . + ENDP + + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.s deleted file mode 100644 index ee5d737..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.s +++ /dev/null @@ -1,194 +0,0 @@ -;/**************************************************************************//** -; * @file startup_SAML21.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Atmel SAML21 Device Series -; * @version V1.00 -; * @date 10. February 2015 -; * -; * @note -; * Copyright (C) 2015 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ;Top of RAM - - PRESERVE8 - THUMB - - -;Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ;Top of Stack - DCD Reset_Handler ;Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator - DCD WDT_Handler ;1 Watchdog Timer - DCD RTC_Handler ;2 Real-Time Counter - DCD EIC_Handler ;3 External Interrupt Controller - DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller - DCD DMAC_Handler ;5 Direct Memory Access Controller - DCD USB_Handler ;6 Universal Serial Bus - DCD EVSYS_Handler ;7 Event System Interface - DCD SERCOM0_Handler ;8 Serial Communication Interface 0 - DCD SERCOM1_Handler ;9 Serial Communication Interface 1 - DCD SERCOM2_Handler ;10 Serial Communication Interface 2 - DCD SERCOM3_Handler ;11 Serial Communication Interface 3 - DCD SERCOM4_Handler ;12 Serial Communication Interface 4 - DCD SERCOM5_Handler ;13 Serial Communication Interface 5 - DCD TCC0_Handler ;14 Timer Counter Control 0 - DCD TCC1_Handler ;15 Timer Counter Control 1 - DCD TCC2_Handler ;16 Timer Counter Control 2 - DCD TC0_Handler ;17 Basic Timer Counter 0 - DCD TC1_Handler ;18 Basic Timer Counter 1 - DCD TC2_Handler ;19 Basic Timer Counter 2 - DCD TC3_Handler ;20 Basic Timer Counter 3 - DCD TC4_Handler ;21 Basic Timer Counter 4 - DCD ADC_Handler ;22 Analog Digital Converter - DCD AC_Handler ;23 Analog Comparators - DCD DAC_Handler ;24 Digital-to-Analog Converter - DCD PTC_Handler ;25 Peripheral Touch Controller - DCD AES_Handler ;26 Advanced Encryption Standard - DCD TRNG_Handler ;27 True Random Generator - DCD PICOP_Handler ;28 PicoProcessor -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -;Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -;Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT SYSTEM_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC0_Handler [WEAK] - EXPORT TC1_Handler [WEAK] - EXPORT TC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT AES_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - EXPORT PICOP_Handler [WEAK] - -SYSTEM_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC0_Handler -TC1_Handler -TC2_Handler -TC3_Handler -TC4_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -AES_Handler -TRNG_Handler -PICOP_Handler - B . - ENDP - - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S new file mode 100644 index 0000000..ee5d737 --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S @@ -0,0 +1,194 @@ +;/**************************************************************************//** +; * @file startup_SAML21.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAML21 Device Series +; * @version V1.00 +; * @date 10. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ;Top of RAM + + PRESERVE8 + THUMB + + +;Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ;Top of Stack + DCD Reset_Handler ;Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator + DCD WDT_Handler ;1 Watchdog Timer + DCD RTC_Handler ;2 Real-Time Counter + DCD EIC_Handler ;3 External Interrupt Controller + DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller + DCD DMAC_Handler ;5 Direct Memory Access Controller + DCD USB_Handler ;6 Universal Serial Bus + DCD EVSYS_Handler ;7 Event System Interface + DCD SERCOM0_Handler ;8 Serial Communication Interface 0 + DCD SERCOM1_Handler ;9 Serial Communication Interface 1 + DCD SERCOM2_Handler ;10 Serial Communication Interface 2 + DCD SERCOM3_Handler ;11 Serial Communication Interface 3 + DCD SERCOM4_Handler ;12 Serial Communication Interface 4 + DCD SERCOM5_Handler ;13 Serial Communication Interface 5 + DCD TCC0_Handler ;14 Timer Counter Control 0 + DCD TCC1_Handler ;15 Timer Counter Control 1 + DCD TCC2_Handler ;16 Timer Counter Control 2 + DCD TC0_Handler ;17 Basic Timer Counter 0 + DCD TC1_Handler ;18 Basic Timer Counter 1 + DCD TC2_Handler ;19 Basic Timer Counter 2 + DCD TC3_Handler ;20 Basic Timer Counter 3 + DCD TC4_Handler ;21 Basic Timer Counter 4 + DCD ADC_Handler ;22 Analog Digital Converter + DCD AC_Handler ;23 Analog Comparators + DCD DAC_Handler ;24 Digital-to-Analog Converter + DCD PTC_Handler ;25 Peripheral Touch Controller + DCD AES_Handler ;26 Advanced Encryption Standard + DCD TRNG_Handler ;27 True Random Generator + DCD PICOP_Handler ;28 PicoProcessor +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +;Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +;Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SYSTEM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT PICOP_Handler [WEAK] + +SYSTEM_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +AES_Handler +TRNG_Handler +PICOP_Handler + B . + ENDP + + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.s deleted file mode 100644 index ee5d737..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.s +++ /dev/null @@ -1,194 +0,0 @@ -;/**************************************************************************//** -; * @file startup_SAML21.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Atmel SAML21 Device Series -; * @version V1.00 -; * @date 10. February 2015 -; * -; * @note -; * Copyright (C) 2015 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ;Top of RAM - - PRESERVE8 - THUMB - - -;Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ;Top of Stack - DCD Reset_Handler ;Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator - DCD WDT_Handler ;1 Watchdog Timer - DCD RTC_Handler ;2 Real-Time Counter - DCD EIC_Handler ;3 External Interrupt Controller - DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller - DCD DMAC_Handler ;5 Direct Memory Access Controller - DCD USB_Handler ;6 Universal Serial Bus - DCD EVSYS_Handler ;7 Event System Interface - DCD SERCOM0_Handler ;8 Serial Communication Interface 0 - DCD SERCOM1_Handler ;9 Serial Communication Interface 1 - DCD SERCOM2_Handler ;10 Serial Communication Interface 2 - DCD SERCOM3_Handler ;11 Serial Communication Interface 3 - DCD SERCOM4_Handler ;12 Serial Communication Interface 4 - DCD SERCOM5_Handler ;13 Serial Communication Interface 5 - DCD TCC0_Handler ;14 Timer Counter Control 0 - DCD TCC1_Handler ;15 Timer Counter Control 1 - DCD TCC2_Handler ;16 Timer Counter Control 2 - DCD TC0_Handler ;17 Basic Timer Counter 0 - DCD TC1_Handler ;18 Basic Timer Counter 1 - DCD TC2_Handler ;19 Basic Timer Counter 2 - DCD TC3_Handler ;20 Basic Timer Counter 3 - DCD TC4_Handler ;21 Basic Timer Counter 4 - DCD ADC_Handler ;22 Analog Digital Converter - DCD AC_Handler ;23 Analog Comparators - DCD DAC_Handler ;24 Digital-to-Analog Converter - DCD PTC_Handler ;25 Peripheral Touch Controller - DCD AES_Handler ;26 Advanced Encryption Standard - DCD TRNG_Handler ;27 True Random Generator - DCD PICOP_Handler ;28 PicoProcessor -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -;Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -;Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT SYSTEM_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC0_Handler [WEAK] - EXPORT TC1_Handler [WEAK] - EXPORT TC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT AES_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - EXPORT PICOP_Handler [WEAK] - -SYSTEM_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC0_Handler -TC1_Handler -TC2_Handler -TC3_Handler -TC4_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -AES_Handler -TRNG_Handler -PICOP_Handler - B . - ENDP - - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S new file mode 100644 index 0000000..f1ffe2f --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S @@ -0,0 +1,189 @@ +;/***************************************************************************** +; * @file startup_SAMR21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMR21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s deleted file mode 100644 index f1ffe2f..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s +++ /dev/null @@ -1,189 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMR21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMR21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S new file mode 100644 index 0000000..f1ffe2f --- /dev/null +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S @@ -0,0 +1,189 @@ +;/***************************************************************************** +; * @file startup_SAMR21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMR21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.s b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.s deleted file mode 100644 index f1ffe2f..0000000 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.s +++ /dev/null @@ -1,189 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMR21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMR21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.S b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.S new file mode 100644 index 0000000..4396825 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.S @@ -0,0 +1,365 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MKL26Z4.s +; * @purpose: CMSIS Cortex-M0P Core Device Startup File +; * MKL26Z4 +; * @version: 1.7 +; * @date: 2015-2-18 +; * @build: b150218 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;FTFA command complete and read collision + DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD UART0_IRQHandler ;UART0 status and error + DCD UART1_IRQHandler ;UART1 status and error + DCD UART2_IRQHandler ;UART2 status and error + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT_IRQHandler ;PIT single interrupt vector for all channels + DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources + DCD USB0_IRQHandler ;USB0 OTG + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD TSI0_IRQHandler ;TSI0 interrupt + DCD MCG_IRQHandler ;MCG interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD Reserved45_IRQHandler ;Reserved interrupt + DCD PORTA_IRQHandler ;PORTA pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT0 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. +; NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; RESET_PIN_CFG +; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function +; <1=> RESET_b pin is dedicated +; LPBOOT1 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. +; FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +FOPT EQU 0xFF +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT init_data_bss + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + LDR R0, =FlashConfig ; dummy read, workaround for flashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =init_data_bss + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT Reserved20_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT Reserved45_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTC_PORTD_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_IRQHandler +USB0_IRQHandler +DAC0_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +Reserved45_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.s b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.s deleted file mode 100644 index 4396825..0000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.s +++ /dev/null @@ -1,365 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MKL26Z4.s -; * @purpose: CMSIS Cortex-M0P Core Device Startup File -; * MKL26Z4 -; * @version: 1.7 -; * @date: 2015-2-18 -; * @build: b150218 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;FTFA command complete and read collision - DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD UART0_IRQHandler ;UART0 status and error - DCD UART1_IRQHandler ;UART1 status and error - DCD UART2_IRQHandler ;UART2 status and error - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT_IRQHandler ;PIT single interrupt vector for all channels - DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources - DCD USB0_IRQHandler ;USB0 OTG - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD TSI0_IRQHandler ;TSI0 interrupt - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD Reserved45_IRQHandler ;Reserved interrupt - DCD PORTA_IRQHandler ;PORTA pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict access to the FTFL module. -; Backdoor Comparison Key -; Backdoor Comparison Key 0. <0x0-0xFF:2> -; Backdoor Comparison Key 1. <0x0-0xFF:2> -; Backdoor Comparison Key 2. <0x0-0xFF:2> -; Backdoor Comparison Key 3. <0x0-0xFF:2> -; Backdoor Comparison Key 4. <0x0-0xFF:2> -; Backdoor Comparison Key 5. <0x0-0xFF:2> -; Backdoor Comparison Key 6. <0x0-0xFF:2> -; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT0 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. -; NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; RESET_PIN_CFG -; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function -; <1=> RESET_b pin is dedicated -; LPBOOT1 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. -; FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -FOPT EQU 0xFF -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor Key Security Enable -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT init_data_bss - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - LDR R0, =FlashConfig ; dummy read, workaround for flashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =init_data_bss - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT Reserved20_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT TSI0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT Reserved45_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTC_PORTD_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_IRQHandler -USB0_IRQHandler -DAC0_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -Reserved45_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.S b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.S new file mode 100644 index 0000000..a0a7478 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.S @@ -0,0 +1,251 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKL26Z4.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKL26Z4 +; @version: 1.7 +; @date: 2015-2-18 +; @build: b150218 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN init_data_bss + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;FTFA command complete and read collision + DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD UART0_IRQHandler ;UART0 status and error + DCD UART1_IRQHandler ;UART1 status and error + DCD UART2_IRQHandler ;UART2 status and error + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT_IRQHandler ;PIT single interrupt vector for all channels + DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources + DCD USB0_IRQHandler ;USB0 OTG + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD TSI0_IRQHandler ;TSI0 interrupt + DCD MCG_IRQHandler ;MCG interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD Reserved45_IRQHandler ;Reserved interrupt + DCD PORTA_IRQHandler ;PORTA pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =init_data_bss + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK TSI0_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK Reserved45_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTC_PORTD_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_IRQHandler +USB0_IRQHandler +DAC0_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +Reserved45_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END diff --git a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.s b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.s deleted file mode 100644 index a0a7478..0000000 --- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.s +++ /dev/null @@ -1,251 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKL26Z4.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKL26Z4 -; @version: 1.7 -; @date: 2015-2-18 -; @build: b150218 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN init_data_bss - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;FTFA command complete and read collision - DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD UART0_IRQHandler ;UART0 status and error - DCD UART1_IRQHandler ;UART1 status and error - DCD UART2_IRQHandler ;UART2 status and error - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT_IRQHandler ;PIT single interrupt vector for all channels - DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources - DCD USB0_IRQHandler ;USB0 OTG - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD TSI0_IRQHandler ;TSI0 interrupt - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD Reserved45_IRQHandler ;Reserved interrupt - DCD PORTA_IRQHandler ;PORTA pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =init_data_bss - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA3_IRQHandler - PUBWEAK Reserved20_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK LVD_LVW_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK I2S0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK TSI0_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK Reserved45_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTC_PORTD_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_IRQHandler -USB0_IRQHandler -DAC0_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -Reserved45_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.S new file mode 100644 index 0000000..0715690 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.S @@ -0,0 +1,456 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MKL43Z4.s +; * @purpose: CMSIS Cortex-M0P Core Device Startup File +; * MKL43Z4 +; * @version: 1.8 +; * @date: 2016-6-24 +; * @build: b160627 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20006000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD I2S0_IRQHandler ;I2S0 interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD Reserved42_IRQHandler ;Reserved interrupt + DCD Reserved43_IRQHandler ;Reserved interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT0 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. +; BOOTPIN_OPT +; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin +; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits +; NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; RESET_PIN_CFG +; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function +; <1=> RESET_b pin is dedicated +; LPBOOT1 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. +; FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +; BOOTSRC_SEL +; <0=> Boot from Flash +; <2=> Boot from ROM +; <3=> Boot from ROM +; Boot source selection +FOPT EQU 0x3F +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +LPUART0_IRQHandler\ + PROC + EXPORT LPUART0_IRQHandler [WEAK] + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + ENDP + +LPUART1_IRQHandler\ + PROC + EXPORT LPUART1_IRQHandler [WEAK] + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + ENDP + +UART2_FLEXIO_IRQHandler\ + PROC + EXPORT UART2_FLEXIO_IRQHandler [WEAK] + LDR R0, =UART2_FLEXIO_DriverIRQHandler + BX R0 + ENDP + +I2S0_IRQHandler\ + PROC + EXPORT I2S0_IRQHandler [WEAK] + LDR R0, =I2S0_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT Reserved20_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT LPUART0_DriverIRQHandler [WEAK] + EXPORT LPUART1_DriverIRQHandler [WEAK] + EXPORT UART2_FLEXIO_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT I2S0_DriverIRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT Reserved42_IRQHandler [WEAK] + EXPORT Reserved43_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTC_PORTD_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +UART2_FLEXIO_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_DriverIRQHandler +USB0_IRQHandler +DAC0_IRQHandler +Reserved42_IRQHandler +Reserved43_IRQHandler +LPTMR0_IRQHandler +LCD_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s deleted file mode 100644 index 0715690..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s +++ /dev/null @@ -1,456 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MKL43Z4.s -; * @purpose: CMSIS Cortex-M0P Core Device Startup File -; * MKL43Z4 -; * @version: 1.8 -; * @date: 2016-6-24 -; * @build: b160627 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - -__initial_sp EQU 0x20006000 ; Top of RAM - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;Command complete and read collision - DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD PIT_IRQHandler ;PIT interrupt - DCD I2S0_IRQHandler ;I2S0 interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD Reserved42_IRQHandler ;Reserved interrupt - DCD Reserved43_IRQHandler ;Reserved interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD LCD_IRQHandler ;LCD interrupt - DCD PORTA_IRQHandler ;PORTA Pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict access to the FTFL module. -; Backdoor Comparison Key -; Backdoor Comparison Key 0. <0x0-0xFF:2> -; Backdoor Comparison Key 1. <0x0-0xFF:2> -; Backdoor Comparison Key 2. <0x0-0xFF:2> -; Backdoor Comparison Key 3. <0x0-0xFF:2> -; Backdoor Comparison Key 4. <0x0-0xFF:2> -; Backdoor Comparison Key 5. <0x0-0xFF:2> -; Backdoor Comparison Key 6. <0x0-0xFF:2> -; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT0 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. -; BOOTPIN_OPT -; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin -; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits -; NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; RESET_PIN_CFG -; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function -; <1=> RESET_b pin is dedicated -; LPBOOT1 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. -; FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -; BOOTSRC_SEL -; <0=> Boot from Flash -; <2=> Boot from ROM -; <3=> Boot from ROM -; Boot source selection -FOPT EQU 0x3F -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor Key Security Enable -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - REQUIRE FlashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -DMA2_IRQHandler\ - PROC - EXPORT DMA2_IRQHandler [WEAK] - LDR R0, =DMA2_DriverIRQHandler - BX R0 - ENDP - -DMA3_IRQHandler\ - PROC - EXPORT DMA3_IRQHandler [WEAK] - LDR R0, =DMA3_DriverIRQHandler - BX R0 - ENDP - -I2C0_IRQHandler\ - PROC - EXPORT I2C0_IRQHandler [WEAK] - LDR R0, =I2C0_DriverIRQHandler - BX R0 - ENDP - -I2C1_IRQHandler\ - PROC - EXPORT I2C1_IRQHandler [WEAK] - LDR R0, =I2C1_DriverIRQHandler - BX R0 - ENDP - -SPI0_IRQHandler\ - PROC - EXPORT SPI0_IRQHandler [WEAK] - LDR R0, =SPI0_DriverIRQHandler - BX R0 - ENDP - -SPI1_IRQHandler\ - PROC - EXPORT SPI1_IRQHandler [WEAK] - LDR R0, =SPI1_DriverIRQHandler - BX R0 - ENDP - -LPUART0_IRQHandler\ - PROC - EXPORT LPUART0_IRQHandler [WEAK] - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - ENDP - -LPUART1_IRQHandler\ - PROC - EXPORT LPUART1_IRQHandler [WEAK] - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - ENDP - -UART2_FLEXIO_IRQHandler\ - PROC - EXPORT UART2_FLEXIO_IRQHandler [WEAK] - LDR R0, =UART2_FLEXIO_DriverIRQHandler - BX R0 - ENDP - -I2S0_IRQHandler\ - PROC - EXPORT I2S0_IRQHandler [WEAK] - LDR R0, =I2S0_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT DMA2_DriverIRQHandler [WEAK] - EXPORT DMA3_DriverIRQHandler [WEAK] - EXPORT Reserved20_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT PMC_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT I2C0_DriverIRQHandler [WEAK] - EXPORT I2C1_DriverIRQHandler [WEAK] - EXPORT SPI0_DriverIRQHandler [WEAK] - EXPORT SPI1_DriverIRQHandler [WEAK] - EXPORT LPUART0_DriverIRQHandler [WEAK] - EXPORT LPUART1_DriverIRQHandler [WEAK] - EXPORT UART2_FLEXIO_DriverIRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT_IRQHandler [WEAK] - EXPORT I2S0_DriverIRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT Reserved42_IRQHandler [WEAK] - EXPORT Reserved43_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTC_PORTD_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -UART2_FLEXIO_DriverIRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_DriverIRQHandler -USB0_IRQHandler -DAC0_IRQHandler -Reserved42_IRQHandler -Reserved43_IRQHandler -LPTMR0_IRQHandler -LCD_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.S new file mode 100644 index 0000000..efcb4d3 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.S @@ -0,0 +1,323 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKL43Z4.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKL43Z4 +; @version: 1.8 +; @date: 2016-6-24 +; @build: b160627 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD I2S0_IRQHandler ;I2S0 interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD Reserved42_IRQHandler ;Reserved interrupt + DCD Reserved43_IRQHandler ;Reserved interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFF3FFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK PMC_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK UART2_FLEXIO_IRQHandler + PUBWEAK UART2_FLEXIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_FLEXIO_IRQHandler + LDR R0, =UART2_FLEXIO_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK I2S0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_IRQHandler + LDR R0, =I2S0_DriverIRQHandler + BX R0 + + PUBWEAK USB0_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK Reserved42_IRQHandler + PUBWEAK Reserved43_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK LCD_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTC_PORTD_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +UART2_FLEXIO_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_DriverIRQHandler +USB0_IRQHandler +DAC0_IRQHandler +Reserved42_IRQHandler +Reserved43_IRQHandler +LPTMR0_IRQHandler +LCD_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.s deleted file mode 100644 index efcb4d3..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.s +++ /dev/null @@ -1,323 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKL43Z4.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKL43Z4 -; @version: 1.8 -; @date: 2016-6-24 -; @build: b160627 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;Command complete and read collision - DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD PIT_IRQHandler ;PIT interrupt - DCD I2S0_IRQHandler ;I2S0 interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD Reserved42_IRQHandler ;Reserved interrupt - DCD Reserved43_IRQHandler ;Reserved interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD LCD_IRQHandler ;LCD interrupt - DCD PORTA_IRQHandler ;PORTA Pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFF3FFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_IRQHandler - LDR R0, =DMA2_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_IRQHandler - LDR R0, =DMA3_DriverIRQHandler - BX R0 - - PUBWEAK Reserved20_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK PMC_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK LPUART0_IRQHandler - PUBWEAK LPUART0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART0_IRQHandler - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - - PUBWEAK LPUART1_IRQHandler - PUBWEAK LPUART1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART1_IRQHandler - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - - PUBWEAK UART2_FLEXIO_IRQHandler - PUBWEAK UART2_FLEXIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_FLEXIO_IRQHandler - LDR R0, =UART2_FLEXIO_DriverIRQHandler - BX R0 - - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK I2S0_IRQHandler - PUBWEAK I2S0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_IRQHandler - LDR R0, =I2S0_DriverIRQHandler - BX R0 - - PUBWEAK USB0_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved43_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK LCD_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTC_PORTD_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -UART2_FLEXIO_DriverIRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_DriverIRQHandler -USB0_IRQHandler -DAC0_IRQHandler -Reserved42_IRQHandler -Reserved43_IRQHandler -LPTMR0_IRQHandler -LCD_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.S new file mode 100644 index 0000000..aa7fdb1 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.S @@ -0,0 +1,616 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MKL82Z7.s +; * @purpose: CMSIS Cortex-M0P Core Device Startup File +; * MKL82Z7 +; * @version: 1.5 +; * @date: 2015-9-24 +; * @build: b151217 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20012000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete + DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete + DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete + DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete + DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error + DCD FLEXIO0_IRQHandler ;Flexible IO + DCD TPM0_IRQHandler ;Timer/PWM module 0 + DCD TPM1_IRQHandler ;Timer/PWM module 1 + DCD TPM2_IRQHandler ;Timer/PWM module 2 + DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 + DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 + DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 + DCD QSPI0_IRQHandler ;QuadSPI0 interrupt + DCD Reserved32_IRQHandler ;DryIce tamper detect + DCD PORTA_IRQHandler ;Pin detect Port A + DCD PORTB_IRQHandler ;Pin detect Port B + DCD PORTC_IRQHandler ;Pin detect Port C + DCD PORTD_IRQHandler ;Pin detect Port D + DCD PORTE_IRQHandler ;Pin detect Port E + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD LTC0_IRQHandler ;Low power trusted cryptographic + DCD USB0_IRQHandler ;USB OTG interrupt + DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 + DCD LPTMR0_IRQHandler ;Low-Power Timer 0 + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 + DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 + DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 + DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 + DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) + DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) + DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) + DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) + DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) + DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) + DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) + DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) + DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) + DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) + DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) + DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) + DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) + DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) + DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) + DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) + DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) + DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) + DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) + DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) + DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) + DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) + DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) + DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) + DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) + DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) + DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; BOOTPIN_OPT +; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin +; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits +; NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +; BOOTSRC_SEL +; <0=> Boot from Flash +; <2=> Boot from ROM, configure QSPI0, and enter boot loader mode. +; <3=> Boot from ROM and enter boot loader mode. +; Boot source selection +FOPT EQU 0x3D +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_DMA4_IRQHandler\ + PROC + EXPORT DMA0_DMA4_IRQHandler [WEAK] + LDR R0, =DMA0_DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA1_DMA5_IRQHandler\ + PROC + EXPORT DMA1_DMA5_IRQHandler [WEAK] + LDR R0, =DMA1_DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA2_DMA6_IRQHandler\ + PROC + EXPORT DMA2_DMA6_IRQHandler [WEAK] + LDR R0, =DMA2_DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA3_DMA7_IRQHandler\ + PROC + EXPORT DMA3_DMA7_IRQHandler [WEAK] + LDR R0, =DMA3_DMA7_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +FLEXIO0_IRQHandler\ + PROC + EXPORT FLEXIO0_IRQHandler [WEAK] + LDR R0, =FLEXIO0_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +LPUART0_IRQHandler\ + PROC + EXPORT LPUART0_IRQHandler [WEAK] + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + ENDP + +LPUART1_IRQHandler\ + PROC + EXPORT LPUART1_IRQHandler [WEAK] + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +QSPI0_IRQHandler\ + PROC + EXPORT QSPI0_IRQHandler [WEAK] + LDR R0, =QSPI0_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_0_IRQHandler\ + PROC + EXPORT INTMUX0_0_IRQHandler [WEAK] + LDR R0, =INTMUX0_0_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_1_IRQHandler\ + PROC + EXPORT INTMUX0_1_IRQHandler [WEAK] + LDR R0, =INTMUX0_1_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_2_IRQHandler\ + PROC + EXPORT INTMUX0_2_IRQHandler [WEAK] + LDR R0, =INTMUX0_2_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_3_IRQHandler\ + PROC + EXPORT INTMUX0_3_IRQHandler [WEAK] + LDR R0, =INTMUX0_3_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +LPUART2_IRQHandler\ + PROC + EXPORT LPUART2_IRQHandler [WEAK] + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +DMA4_IRQHandler\ + PROC + EXPORT DMA4_IRQHandler [WEAK] + LDR R0, =DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA5_IRQHandler\ + PROC + EXPORT DMA5_IRQHandler [WEAK] + LDR R0, =DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA6_IRQHandler\ + PROC + EXPORT DMA6_IRQHandler [WEAK] + LDR R0, =DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA7_IRQHandler\ + PROC + EXPORT DMA7_IRQHandler [WEAK] + LDR R0, =DMA7_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DMA4_DriverIRQHandler [WEAK] + EXPORT DMA1_DMA5_DriverIRQHandler [WEAK] + EXPORT DMA2_DMA6_DriverIRQHandler [WEAK] + EXPORT DMA3_DMA7_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT FLEXIO0_DriverIRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT EMVSIM0_IRQHandler [WEAK] + EXPORT LPUART0_DriverIRQHandler [WEAK] + EXPORT LPUART1_DriverIRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT QSPI0_DriverIRQHandler [WEAK] + EXPORT Reserved32_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT LTC0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT INTMUX0_0_DriverIRQHandler [WEAK] + EXPORT INTMUX0_1_DriverIRQHandler [WEAK] + EXPORT INTMUX0_2_DriverIRQHandler [WEAK] + EXPORT INTMUX0_3_DriverIRQHandler [WEAK] + EXPORT LPTMR1_IRQHandler [WEAK] + EXPORT Reserved49_IRQHandler [WEAK] + EXPORT Reserved50_IRQHandler [WEAK] + EXPORT Reserved51_IRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT LPUART2_DriverIRQHandler [WEAK] + EXPORT EMVSIM1_IRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + EXPORT Reserved63_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT Reserved65_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT Reserved67_IRQHandler [WEAK] + EXPORT Reserved68_IRQHandler [WEAK] + EXPORT Reserved69_IRQHandler [WEAK] + EXPORT Reserved70_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DMA4_DriverIRQHandler [WEAK] + EXPORT DMA5_DriverIRQHandler [WEAK] + EXPORT DMA6_DriverIRQHandler [WEAK] + EXPORT DMA7_DriverIRQHandler [WEAK] + EXPORT Reserved76_IRQHandler [WEAK] + EXPORT Reserved77_IRQHandler [WEAK] + EXPORT Reserved78_IRQHandler [WEAK] + EXPORT Reserved79_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DMA4_DriverIRQHandler +DMA1_DMA5_DriverIRQHandler +DMA2_DMA6_DriverIRQHandler +DMA3_DMA7_DriverIRQHandler +DMA_Error_DriverIRQHandler +FLEXIO0_DriverIRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +PIT0_IRQHandler +SPI0_DriverIRQHandler +EMVSIM0_IRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +I2C0_DriverIRQHandler +QSPI0_DriverIRQHandler +Reserved32_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +LLWU_IRQHandler +LTC0_IRQHandler +USB0_IRQHandler +ADC0_IRQHandler +LPTMR0_IRQHandler +RTC_Seconds_IRQHandler +INTMUX0_0_DriverIRQHandler +INTMUX0_1_DriverIRQHandler +INTMUX0_2_DriverIRQHandler +INTMUX0_3_DriverIRQHandler +LPTMR1_IRQHandler +Reserved49_IRQHandler +Reserved50_IRQHandler +Reserved51_IRQHandler +SPI1_DriverIRQHandler +LPUART2_DriverIRQHandler +EMVSIM1_IRQHandler +I2C1_DriverIRQHandler +TSI0_IRQHandler +PMC_IRQHandler +FTFA_IRQHandler +MCG_IRQHandler +WDOG_EWM_IRQHandler +DAC0_IRQHandler +TRNG0_IRQHandler +Reserved63_IRQHandler +CMP0_IRQHandler +Reserved65_IRQHandler +RTC_Alarm_IRQHandler +Reserved67_IRQHandler +Reserved68_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +Reserved76_IRQHandler +Reserved77_IRQHandler +Reserved78_IRQHandler +Reserved79_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s deleted file mode 100644 index aa7fdb1..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s +++ /dev/null @@ -1,616 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MKL82Z7.s -; * @purpose: CMSIS Cortex-M0P Core Device Startup File -; * MKL82Z7 -; * @version: 1.5 -; * @date: 2015-9-24 -; * @build: b151217 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - -__initial_sp EQU 0x20012000 ; Top of RAM - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete - DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete - DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete - DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error - DCD FLEXIO0_IRQHandler ;Flexible IO - DCD TPM0_IRQHandler ;Timer/PWM module 0 - DCD TPM1_IRQHandler ;Timer/PWM module 1 - DCD TPM2_IRQHandler ;Timer/PWM module 2 - DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 - DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 - DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 - DCD QSPI0_IRQHandler ;QuadSPI0 interrupt - DCD Reserved32_IRQHandler ;DryIce tamper detect - DCD PORTA_IRQHandler ;Pin detect Port A - DCD PORTB_IRQHandler ;Pin detect Port B - DCD PORTC_IRQHandler ;Pin detect Port C - DCD PORTD_IRQHandler ;Pin detect Port D - DCD PORTE_IRQHandler ;Pin detect Port E - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD LTC0_IRQHandler ;Low power trusted cryptographic - DCD USB0_IRQHandler ;USB OTG interrupt - DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 - DCD LPTMR0_IRQHandler ;Low-Power Timer 0 - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 - DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 - DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 - DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 - DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) - DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) - DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) - DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) - DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) - DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) - DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) - DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) - DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) - DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) - DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) - DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) - DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) - DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) - DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) - DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) - DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) - DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) - DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) - DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) - DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) - DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) - DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) - DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) - DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) - DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict access to the FTFL module. -; Backdoor Comparison Key -; Backdoor Comparison Key 0. <0x0-0xFF:2> -; Backdoor Comparison Key 1. <0x0-0xFF:2> -; Backdoor Comparison Key 2. <0x0-0xFF:2> -; Backdoor Comparison Key 3. <0x0-0xFF:2> -; Backdoor Comparison Key 4. <0x0-0xFF:2> -; Backdoor Comparison Key 5. <0x0-0xFF:2> -; Backdoor Comparison Key 6. <0x0-0xFF:2> -; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT -; <0=> Low-power boot -; <1=> Normal boot -; BOOTPIN_OPT -; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin -; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits -; NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -; BOOTSRC_SEL -; <0=> Boot from Flash -; <2=> Boot from ROM, configure QSPI0, and enter boot loader mode. -; <3=> Boot from ROM and enter boot loader mode. -; Boot source selection -FOPT EQU 0x3D -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor Key Security Enable -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - REQUIRE FlashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_DMA4_IRQHandler\ - PROC - EXPORT DMA0_DMA4_IRQHandler [WEAK] - LDR R0, =DMA0_DMA4_DriverIRQHandler - BX R0 - ENDP - -DMA1_DMA5_IRQHandler\ - PROC - EXPORT DMA1_DMA5_IRQHandler [WEAK] - LDR R0, =DMA1_DMA5_DriverIRQHandler - BX R0 - ENDP - -DMA2_DMA6_IRQHandler\ - PROC - EXPORT DMA2_DMA6_IRQHandler [WEAK] - LDR R0, =DMA2_DMA6_DriverIRQHandler - BX R0 - ENDP - -DMA3_DMA7_IRQHandler\ - PROC - EXPORT DMA3_DMA7_IRQHandler [WEAK] - LDR R0, =DMA3_DMA7_DriverIRQHandler - BX R0 - ENDP - -DMA_Error_IRQHandler\ - PROC - EXPORT DMA_Error_IRQHandler [WEAK] - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - ENDP - -FLEXIO0_IRQHandler\ - PROC - EXPORT FLEXIO0_IRQHandler [WEAK] - LDR R0, =FLEXIO0_DriverIRQHandler - BX R0 - ENDP - -SPI0_IRQHandler\ - PROC - EXPORT SPI0_IRQHandler [WEAK] - LDR R0, =SPI0_DriverIRQHandler - BX R0 - ENDP - -LPUART0_IRQHandler\ - PROC - EXPORT LPUART0_IRQHandler [WEAK] - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - ENDP - -LPUART1_IRQHandler\ - PROC - EXPORT LPUART1_IRQHandler [WEAK] - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - ENDP - -I2C0_IRQHandler\ - PROC - EXPORT I2C0_IRQHandler [WEAK] - LDR R0, =I2C0_DriverIRQHandler - BX R0 - ENDP - -QSPI0_IRQHandler\ - PROC - EXPORT QSPI0_IRQHandler [WEAK] - LDR R0, =QSPI0_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_0_IRQHandler\ - PROC - EXPORT INTMUX0_0_IRQHandler [WEAK] - LDR R0, =INTMUX0_0_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_1_IRQHandler\ - PROC - EXPORT INTMUX0_1_IRQHandler [WEAK] - LDR R0, =INTMUX0_1_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_2_IRQHandler\ - PROC - EXPORT INTMUX0_2_IRQHandler [WEAK] - LDR R0, =INTMUX0_2_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_3_IRQHandler\ - PROC - EXPORT INTMUX0_3_IRQHandler [WEAK] - LDR R0, =INTMUX0_3_DriverIRQHandler - BX R0 - ENDP - -SPI1_IRQHandler\ - PROC - EXPORT SPI1_IRQHandler [WEAK] - LDR R0, =SPI1_DriverIRQHandler - BX R0 - ENDP - -LPUART2_IRQHandler\ - PROC - EXPORT LPUART2_IRQHandler [WEAK] - LDR R0, =LPUART2_DriverIRQHandler - BX R0 - ENDP - -I2C1_IRQHandler\ - PROC - EXPORT I2C1_IRQHandler [WEAK] - LDR R0, =I2C1_DriverIRQHandler - BX R0 - ENDP - -DMA4_IRQHandler\ - PROC - EXPORT DMA4_IRQHandler [WEAK] - LDR R0, =DMA4_DriverIRQHandler - BX R0 - ENDP - -DMA5_IRQHandler\ - PROC - EXPORT DMA5_IRQHandler [WEAK] - LDR R0, =DMA5_DriverIRQHandler - BX R0 - ENDP - -DMA6_IRQHandler\ - PROC - EXPORT DMA6_IRQHandler [WEAK] - LDR R0, =DMA6_DriverIRQHandler - BX R0 - ENDP - -DMA7_IRQHandler\ - PROC - EXPORT DMA7_IRQHandler [WEAK] - LDR R0, =DMA7_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DMA4_DriverIRQHandler [WEAK] - EXPORT DMA1_DMA5_DriverIRQHandler [WEAK] - EXPORT DMA2_DMA6_DriverIRQHandler [WEAK] - EXPORT DMA3_DMA7_DriverIRQHandler [WEAK] - EXPORT DMA_Error_DriverIRQHandler [WEAK] - EXPORT FLEXIO0_DriverIRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT SPI0_DriverIRQHandler [WEAK] - EXPORT EMVSIM0_IRQHandler [WEAK] - EXPORT LPUART0_DriverIRQHandler [WEAK] - EXPORT LPUART1_DriverIRQHandler [WEAK] - EXPORT I2C0_DriverIRQHandler [WEAK] - EXPORT QSPI0_DriverIRQHandler [WEAK] - EXPORT Reserved32_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT LTC0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT INTMUX0_0_DriverIRQHandler [WEAK] - EXPORT INTMUX0_1_DriverIRQHandler [WEAK] - EXPORT INTMUX0_2_DriverIRQHandler [WEAK] - EXPORT INTMUX0_3_DriverIRQHandler [WEAK] - EXPORT LPTMR1_IRQHandler [WEAK] - EXPORT Reserved49_IRQHandler [WEAK] - EXPORT Reserved50_IRQHandler [WEAK] - EXPORT Reserved51_IRQHandler [WEAK] - EXPORT SPI1_DriverIRQHandler [WEAK] - EXPORT LPUART2_DriverIRQHandler [WEAK] - EXPORT EMVSIM1_IRQHandler [WEAK] - EXPORT I2C1_DriverIRQHandler [WEAK] - EXPORT TSI0_IRQHandler [WEAK] - EXPORT PMC_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT WDOG_EWM_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT TRNG0_IRQHandler [WEAK] - EXPORT Reserved63_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT Reserved65_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT Reserved67_IRQHandler [WEAK] - EXPORT Reserved68_IRQHandler [WEAK] - EXPORT Reserved69_IRQHandler [WEAK] - EXPORT Reserved70_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT DMA4_DriverIRQHandler [WEAK] - EXPORT DMA5_DriverIRQHandler [WEAK] - EXPORT DMA6_DriverIRQHandler [WEAK] - EXPORT DMA7_DriverIRQHandler [WEAK] - EXPORT Reserved76_IRQHandler [WEAK] - EXPORT Reserved77_IRQHandler [WEAK] - EXPORT Reserved78_IRQHandler [WEAK] - EXPORT Reserved79_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DMA4_DriverIRQHandler -DMA1_DMA5_DriverIRQHandler -DMA2_DMA6_DriverIRQHandler -DMA3_DMA7_DriverIRQHandler -DMA_Error_DriverIRQHandler -FLEXIO0_DriverIRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -PIT0_IRQHandler -SPI0_DriverIRQHandler -EMVSIM0_IRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -I2C0_DriverIRQHandler -QSPI0_DriverIRQHandler -Reserved32_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -LLWU_IRQHandler -LTC0_IRQHandler -USB0_IRQHandler -ADC0_IRQHandler -LPTMR0_IRQHandler -RTC_Seconds_IRQHandler -INTMUX0_0_DriverIRQHandler -INTMUX0_1_DriverIRQHandler -INTMUX0_2_DriverIRQHandler -INTMUX0_3_DriverIRQHandler -LPTMR1_IRQHandler -Reserved49_IRQHandler -Reserved50_IRQHandler -Reserved51_IRQHandler -SPI1_DriverIRQHandler -LPUART2_DriverIRQHandler -EMVSIM1_IRQHandler -I2C1_DriverIRQHandler -TSI0_IRQHandler -PMC_IRQHandler -FTFA_IRQHandler -MCG_IRQHandler -WDOG_EWM_IRQHandler -DAC0_IRQHandler -TRNG0_IRQHandler -Reserved63_IRQHandler -CMP0_IRQHandler -Reserved65_IRQHandler -RTC_Alarm_IRQHandler -Reserved67_IRQHandler -Reserved68_IRQHandler -Reserved69_IRQHandler -Reserved70_IRQHandler -Reserved71_IRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -Reserved76_IRQHandler -Reserved77_IRQHandler -Reserved78_IRQHandler -Reserved79_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.S new file mode 100644 index 0000000..8e9c43d --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.S @@ -0,0 +1,479 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKL82Z7.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKL82Z7 +; @version: 1.5 +; @date: 2015-9-24 +; @build: b151217 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete + DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete + DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete + DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete + DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error + DCD FLEXIO0_IRQHandler ;Flexible IO + DCD TPM0_IRQHandler ;Timer/PWM module 0 + DCD TPM1_IRQHandler ;Timer/PWM module 1 + DCD TPM2_IRQHandler ;Timer/PWM module 2 + DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 + DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 + DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 + DCD QSPI0_IRQHandler ;QuadSPI0 interrupt + DCD Reserved32_IRQHandler ;DryIce tamper detect + DCD PORTA_IRQHandler ;Pin detect Port A + DCD PORTB_IRQHandler ;Pin detect Port B + DCD PORTC_IRQHandler ;Pin detect Port C + DCD PORTD_IRQHandler ;Pin detect Port D + DCD PORTE_IRQHandler ;Pin detect Port E + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD LTC0_IRQHandler ;Low power trusted cryptographic + DCD USB0_IRQHandler ;USB OTG interrupt + DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 + DCD LPTMR0_IRQHandler ;Low-Power Timer 0 + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 + DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 + DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 + DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 + DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) + DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) + DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) + DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) + DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) + DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) + DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) + DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) + DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) + DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) + DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) + DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) + DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) + DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) + DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) + DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) + DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) + DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) + DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) + DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) + DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) + DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) + DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) + DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) + DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) + DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) + DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFF3DFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_DMA4_IRQHandler + PUBWEAK DMA0_DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DMA4_IRQHandler + LDR R0, =DMA0_DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_DMA5_IRQHandler + PUBWEAK DMA1_DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_DMA5_IRQHandler + LDR R0, =DMA1_DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_DMA6_IRQHandler + PUBWEAK DMA2_DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_DMA6_IRQHandler + LDR R0, =DMA2_DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_DMA7_IRQHandler + PUBWEAK DMA3_DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_DMA7_IRQHandler + LDR R0, =DMA3_DMA7_DriverIRQHandler + BX R0 + + PUBWEAK DMA_Error_IRQHandler + PUBWEAK DMA_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_Error_IRQHandler + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + + PUBWEAK FLEXIO0_IRQHandler + PUBWEAK FLEXIO0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO0_IRQHandler + LDR R0, =FLEXIO0_DriverIRQHandler + BX R0 + + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK EMVSIM0_IRQHandler + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK QSPI0_IRQHandler + PUBWEAK QSPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QSPI0_IRQHandler + LDR R0, =QSPI0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved32_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK LTC0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK INTMUX0_0_IRQHandler + PUBWEAK INTMUX0_0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_0_IRQHandler + LDR R0, =INTMUX0_0_DriverIRQHandler + BX R0 + + PUBWEAK INTMUX0_1_IRQHandler + PUBWEAK INTMUX0_1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_1_IRQHandler + LDR R0, =INTMUX0_1_DriverIRQHandler + BX R0 + + PUBWEAK INTMUX0_2_IRQHandler + PUBWEAK INTMUX0_2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_2_IRQHandler + LDR R0, =INTMUX0_2_DriverIRQHandler + BX R0 + + PUBWEAK INTMUX0_3_IRQHandler + PUBWEAK INTMUX0_3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_3_IRQHandler + LDR R0, =INTMUX0_3_DriverIRQHandler + BX R0 + + PUBWEAK LPTMR1_IRQHandler + PUBWEAK Reserved49_IRQHandler + PUBWEAK Reserved50_IRQHandler + PUBWEAK Reserved51_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART2_IRQHandler + PUBWEAK LPUART2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART2_IRQHandler + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + + PUBWEAK EMVSIM1_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK TSI0_IRQHandler + PUBWEAK PMC_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK TRNG0_IRQHandler + PUBWEAK Reserved63_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK Reserved65_IRQHandler + PUBWEAK RTC_Alarm_IRQHandler + PUBWEAK Reserved67_IRQHandler + PUBWEAK Reserved68_IRQHandler + PUBWEAK Reserved69_IRQHandler + PUBWEAK Reserved70_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_IRQHandler + LDR R0, =DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_IRQHandler + LDR R0, =DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_IRQHandler + LDR R0, =DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_IRQHandler + LDR R0, =DMA7_DriverIRQHandler + BX R0 + + PUBWEAK Reserved76_IRQHandler + PUBWEAK Reserved77_IRQHandler + PUBWEAK Reserved78_IRQHandler + PUBWEAK Reserved79_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DMA4_DriverIRQHandler +DMA1_DMA5_DriverIRQHandler +DMA2_DMA6_DriverIRQHandler +DMA3_DMA7_DriverIRQHandler +DMA_Error_DriverIRQHandler +FLEXIO0_DriverIRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +PIT0_IRQHandler +SPI0_DriverIRQHandler +EMVSIM0_IRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +I2C0_DriverIRQHandler +QSPI0_DriverIRQHandler +Reserved32_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +LLWU_IRQHandler +LTC0_IRQHandler +USB0_IRQHandler +ADC0_IRQHandler +LPTMR0_IRQHandler +RTC_Seconds_IRQHandler +INTMUX0_0_DriverIRQHandler +INTMUX0_1_DriverIRQHandler +INTMUX0_2_DriverIRQHandler +INTMUX0_3_DriverIRQHandler +LPTMR1_IRQHandler +Reserved49_IRQHandler +Reserved50_IRQHandler +Reserved51_IRQHandler +SPI1_DriverIRQHandler +LPUART2_DriverIRQHandler +EMVSIM1_IRQHandler +I2C1_DriverIRQHandler +TSI0_IRQHandler +PMC_IRQHandler +FTFA_IRQHandler +MCG_IRQHandler +WDOG_EWM_IRQHandler +DAC0_IRQHandler +TRNG0_IRQHandler +Reserved63_IRQHandler +CMP0_IRQHandler +Reserved65_IRQHandler +RTC_Alarm_IRQHandler +Reserved67_IRQHandler +Reserved68_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +Reserved76_IRQHandler +Reserved77_IRQHandler +Reserved78_IRQHandler +Reserved79_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s deleted file mode 100644 index 8e9c43d..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s +++ /dev/null @@ -1,479 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKL82Z7.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKL82Z7 -; @version: 1.5 -; @date: 2015-9-24 -; @build: b151217 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete - DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete - DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete - DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error - DCD FLEXIO0_IRQHandler ;Flexible IO - DCD TPM0_IRQHandler ;Timer/PWM module 0 - DCD TPM1_IRQHandler ;Timer/PWM module 1 - DCD TPM2_IRQHandler ;Timer/PWM module 2 - DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 - DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 - DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 - DCD QSPI0_IRQHandler ;QuadSPI0 interrupt - DCD Reserved32_IRQHandler ;DryIce tamper detect - DCD PORTA_IRQHandler ;Pin detect Port A - DCD PORTB_IRQHandler ;Pin detect Port B - DCD PORTC_IRQHandler ;Pin detect Port C - DCD PORTD_IRQHandler ;Pin detect Port D - DCD PORTE_IRQHandler ;Pin detect Port E - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD LTC0_IRQHandler ;Low power trusted cryptographic - DCD USB0_IRQHandler ;USB OTG interrupt - DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 - DCD LPTMR0_IRQHandler ;Low-Power Timer 0 - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 - DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 - DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 - DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 - DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) - DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) - DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) - DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) - DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) - DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) - DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) - DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) - DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) - DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) - DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) - DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) - DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) - DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) - DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) - DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) - DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) - DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) - DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) - DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) - DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) - DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) - DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) - DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) - DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) - DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFF3DFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_DMA4_IRQHandler - PUBWEAK DMA0_DMA4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DMA4_IRQHandler - LDR R0, =DMA0_DMA4_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_DMA5_IRQHandler - PUBWEAK DMA1_DMA5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_DMA5_IRQHandler - LDR R0, =DMA1_DMA5_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_DMA6_IRQHandler - PUBWEAK DMA2_DMA6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_DMA6_IRQHandler - LDR R0, =DMA2_DMA6_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_DMA7_IRQHandler - PUBWEAK DMA3_DMA7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_DMA7_IRQHandler - LDR R0, =DMA3_DMA7_DriverIRQHandler - BX R0 - - PUBWEAK DMA_Error_IRQHandler - PUBWEAK DMA_Error_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA_Error_IRQHandler - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - - PUBWEAK FLEXIO0_IRQHandler - PUBWEAK FLEXIO0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXIO0_IRQHandler - LDR R0, =FLEXIO0_DriverIRQHandler - BX R0 - - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK EMVSIM0_IRQHandler - PUBWEAK LPUART0_IRQHandler - PUBWEAK LPUART0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART0_IRQHandler - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - - PUBWEAK LPUART1_IRQHandler - PUBWEAK LPUART1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART1_IRQHandler - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK QSPI0_IRQHandler - PUBWEAK QSPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -QSPI0_IRQHandler - LDR R0, =QSPI0_DriverIRQHandler - BX R0 - - PUBWEAK Reserved32_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK LTC0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK INTMUX0_0_IRQHandler - PUBWEAK INTMUX0_0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_0_IRQHandler - LDR R0, =INTMUX0_0_DriverIRQHandler - BX R0 - - PUBWEAK INTMUX0_1_IRQHandler - PUBWEAK INTMUX0_1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_1_IRQHandler - LDR R0, =INTMUX0_1_DriverIRQHandler - BX R0 - - PUBWEAK INTMUX0_2_IRQHandler - PUBWEAK INTMUX0_2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_2_IRQHandler - LDR R0, =INTMUX0_2_DriverIRQHandler - BX R0 - - PUBWEAK INTMUX0_3_IRQHandler - PUBWEAK INTMUX0_3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_3_IRQHandler - LDR R0, =INTMUX0_3_DriverIRQHandler - BX R0 - - PUBWEAK LPTMR1_IRQHandler - PUBWEAK Reserved49_IRQHandler - PUBWEAK Reserved50_IRQHandler - PUBWEAK Reserved51_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK LPUART2_IRQHandler - PUBWEAK LPUART2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART2_IRQHandler - LDR R0, =LPUART2_DriverIRQHandler - BX R0 - - PUBWEAK EMVSIM1_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK TSI0_IRQHandler - PUBWEAK PMC_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK WDOG_EWM_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK TRNG0_IRQHandler - PUBWEAK Reserved63_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK Reserved65_IRQHandler - PUBWEAK RTC_Alarm_IRQHandler - PUBWEAK Reserved67_IRQHandler - PUBWEAK Reserved68_IRQHandler - PUBWEAK Reserved69_IRQHandler - PUBWEAK Reserved70_IRQHandler - PUBWEAK Reserved71_IRQHandler - PUBWEAK DMA4_IRQHandler - PUBWEAK DMA4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA4_IRQHandler - LDR R0, =DMA4_DriverIRQHandler - BX R0 - - PUBWEAK DMA5_IRQHandler - PUBWEAK DMA5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA5_IRQHandler - LDR R0, =DMA5_DriverIRQHandler - BX R0 - - PUBWEAK DMA6_IRQHandler - PUBWEAK DMA6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA6_IRQHandler - LDR R0, =DMA6_DriverIRQHandler - BX R0 - - PUBWEAK DMA7_IRQHandler - PUBWEAK DMA7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA7_IRQHandler - LDR R0, =DMA7_DriverIRQHandler - BX R0 - - PUBWEAK Reserved76_IRQHandler - PUBWEAK Reserved77_IRQHandler - PUBWEAK Reserved78_IRQHandler - PUBWEAK Reserved79_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DMA4_DriverIRQHandler -DMA1_DMA5_DriverIRQHandler -DMA2_DMA6_DriverIRQHandler -DMA3_DMA7_DriverIRQHandler -DMA_Error_DriverIRQHandler -FLEXIO0_DriverIRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -PIT0_IRQHandler -SPI0_DriverIRQHandler -EMVSIM0_IRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -I2C0_DriverIRQHandler -QSPI0_DriverIRQHandler -Reserved32_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -LLWU_IRQHandler -LTC0_IRQHandler -USB0_IRQHandler -ADC0_IRQHandler -LPTMR0_IRQHandler -RTC_Seconds_IRQHandler -INTMUX0_0_DriverIRQHandler -INTMUX0_1_DriverIRQHandler -INTMUX0_2_DriverIRQHandler -INTMUX0_3_DriverIRQHandler -LPTMR1_IRQHandler -Reserved49_IRQHandler -Reserved50_IRQHandler -Reserved51_IRQHandler -SPI1_DriverIRQHandler -LPUART2_DriverIRQHandler -EMVSIM1_IRQHandler -I2C1_DriverIRQHandler -TSI0_IRQHandler -PMC_IRQHandler -FTFA_IRQHandler -MCG_IRQHandler -WDOG_EWM_IRQHandler -DAC0_IRQHandler -TRNG0_IRQHandler -Reserved63_IRQHandler -CMP0_IRQHandler -Reserved65_IRQHandler -RTC_Alarm_IRQHandler -Reserved67_IRQHandler -Reserved68_IRQHandler -Reserved69_IRQHandler -Reserved70_IRQHandler -Reserved71_IRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -Reserved76_IRQHandler -Reserved77_IRQHandler -Reserved78_IRQHandler -Reserved79_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.S new file mode 100644 index 0000000..1363c29 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.S @@ -0,0 +1,718 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKW24D5.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; MKW24D5 +; @version: 2.0 +; @date: 2014-11-26 +; @build: b160512 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete + DCD DMA8_IRQHandler ;DMA channel 8 transfer complete + DCD DMA9_IRQHandler ;DMA channel 9 transfer complete + DCD DMA10_IRQHandler ;DMA channel 10 transfer complete + DCD DMA11_IRQHandler ;DMA channel 11 transfer complete + DCD DMA12_IRQHandler ;DMA channel 12 transfer complete + DCD DMA13_IRQHandler ;DMA channel 13 transfer complete + DCD DMA14_IRQHandler ;DMA channel 14 transfer complete + DCD DMA15_IRQHandler ;DMA channel 15 transfer complete + DCD DMA_Error_IRQHandler ;DMA channel 0 - 15 error + DCD MCM_IRQHandler ;MCM normal interrupt + DCD FTFL_IRQHandler ;FTFL command complete + DCD FTFL_Collision_IRQHandler ;FTFL read collision + DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM + DCD RNG_IRQHandler ;Randon number generator + DCD I2C0_IRQHandler ;Inter-integrated circuit 0 + DCD I2C1_IRQHandler ;Inter-integrated circuit 1 + DCD SPI0_IRQHandler ;Serial peripheral Interface 0 + DCD SPI1_IRQHandler ;Serial peripheral Interface 1 + DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt + DCD Reserved46_IRQHandler ;Reserved interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 receive/transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 receive/transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 receive/transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 error interrupt + DCD Reserved53_IRQHandler ;Reserved interrupt + DCD Reserved54_IRQHandler ;Reserved interrupt + DCD ADC0_IRQHandler ;Analog-to-digital converter 0 + DCD CMP0_IRQHandler ;Comparator 0 + DCD CMP1_IRQHandler ;Comparator 1 + DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;Carrier modulator transmitter + DCD RTC_IRQHandler ;Real time clock + DCD RTC_Seconds_IRQHandler ;Real time clock seconds + DCD PIT0_IRQHandler ;Periodic interrupt timer channel 0 + DCD PIT1_IRQHandler ;Periodic interrupt timer channel 1 + DCD PIT2_IRQHandler ;Periodic interrupt timer channel 2 + DCD PIT3_IRQHandler ;Periodic interrupt timer channel 3 + DCD PDB0_IRQHandler ;Programmable delay block + DCD USB0_IRQHandler ;USB OTG interrupt + DCD USBDCD_IRQHandler ;USB charger detect + DCD Reserved71_IRQHandler ;Reserved interrupt + DCD Reserved72_IRQHandler ;Reserved interrupt + DCD MCG_IRQHandler ;Multipurpose clock generator + DCD LPTMR0_IRQHandler ;Low power timer interrupt + DCD PORTA_IRQHandler ;Port A pin detect interrupt + DCD PORTB_IRQHandler ;Port B pin detect interrupt + DCD PORTC_IRQHandler ;Port C pin detect interrupt + DCD PORTD_IRQHandler ;Port D pin detect interrupt + DCD PORTE_IRQHandler ;Port E pin detect interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD DefaultISR ;81 + DCD DefaultISR ;82 + DCD DefaultISR ;83 + DCD DefaultISR ;84 + DCD DefaultISR ;85 + DCD DefaultISR ;86 + DCD DefaultISR ;87 + DCD DefaultISR ;88 + DCD DefaultISR ;89 + DCD DefaultISR ;90 + DCD DefaultISR ;91 + DCD DefaultISR ;92 + DCD DefaultISR ;93 + DCD DefaultISR ;94 + DCD DefaultISR ;95 + DCD DefaultISR ;96 + DCD DefaultISR ;97 + DCD DefaultISR ;98 + DCD DefaultISR ;99 + DCD DefaultISR ;100 + DCD DefaultISR ;101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_IRQHandler + LDR R0, =DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_IRQHandler + LDR R0, =DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_IRQHandler + LDR R0, =DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_IRQHandler + LDR R0, =DMA7_DriverIRQHandler + BX R0 + + PUBWEAK DMA8_IRQHandler + PUBWEAK DMA8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA8_IRQHandler + LDR R0, =DMA8_DriverIRQHandler + BX R0 + + PUBWEAK DMA9_IRQHandler + PUBWEAK DMA9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA9_IRQHandler + LDR R0, =DMA9_DriverIRQHandler + BX R0 + + PUBWEAK DMA10_IRQHandler + PUBWEAK DMA10_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA10_IRQHandler + LDR R0, =DMA10_DriverIRQHandler + BX R0 + + PUBWEAK DMA11_IRQHandler + PUBWEAK DMA11_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA11_IRQHandler + LDR R0, =DMA11_DriverIRQHandler + BX R0 + + PUBWEAK DMA12_IRQHandler + PUBWEAK DMA12_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA12_IRQHandler + LDR R0, =DMA12_DriverIRQHandler + BX R0 + + PUBWEAK DMA13_IRQHandler + PUBWEAK DMA13_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA13_IRQHandler + LDR R0, =DMA13_DriverIRQHandler + BX R0 + + PUBWEAK DMA14_IRQHandler + PUBWEAK DMA14_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA14_IRQHandler + LDR R0, =DMA14_DriverIRQHandler + BX R0 + + PUBWEAK DMA15_IRQHandler + PUBWEAK DMA15_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA15_IRQHandler + LDR R0, =DMA15_DriverIRQHandler + BX R0 + + PUBWEAK DMA_Error_IRQHandler + PUBWEAK DMA_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_Error_IRQHandler + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + + PUBWEAK MCM_IRQHandler + PUBWEAK FTFL_IRQHandler + PUBWEAK FTFL_Collision_IRQHandler + PUBWEAK PMC_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK RNG_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Tx_IRQHandler + PUBWEAK I2S0_Tx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Tx_IRQHandler + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Rx_IRQHandler + PUBWEAK I2S0_Rx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Rx_IRQHandler + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + + PUBWEAK Reserved46_IRQHandler + PUBWEAK UART0_RX_TX_IRQHandler + PUBWEAK UART0_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_RX_TX_IRQHandler + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART0_ERR_IRQHandler + PUBWEAK UART0_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_ERR_IRQHandler + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART1_RX_TX_IRQHandler + PUBWEAK UART1_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_RX_TX_IRQHandler + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART1_ERR_IRQHandler + PUBWEAK UART1_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_ERR_IRQHandler + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART2_RX_TX_IRQHandler + PUBWEAK UART2_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_RX_TX_IRQHandler + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART2_ERR_IRQHandler + PUBWEAK UART2_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_ERR_IRQHandler + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + + PUBWEAK Reserved53_IRQHandler + PUBWEAK Reserved54_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK FTM0_IRQHandler + PUBWEAK FTM1_IRQHandler + PUBWEAK FTM2_IRQHandler + PUBWEAK CMT_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK PIT1_IRQHandler + PUBWEAK PIT2_IRQHandler + PUBWEAK PIT3_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK USBDCD_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK Reserved72_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SWI_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFL_IRQHandler +FTFL_Collision_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +Reserved46_IRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +Reserved72_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.s deleted file mode 100644 index 1363c29..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.s +++ /dev/null @@ -1,718 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKW24D5.s -; @purpose: CMSIS Cortex-M4 Core Device Startup File -; MKW24D5 -; @version: 2.0 -; @date: 2014-11-26 -; @build: b160512 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete - DCD DMA8_IRQHandler ;DMA channel 8 transfer complete - DCD DMA9_IRQHandler ;DMA channel 9 transfer complete - DCD DMA10_IRQHandler ;DMA channel 10 transfer complete - DCD DMA11_IRQHandler ;DMA channel 11 transfer complete - DCD DMA12_IRQHandler ;DMA channel 12 transfer complete - DCD DMA13_IRQHandler ;DMA channel 13 transfer complete - DCD DMA14_IRQHandler ;DMA channel 14 transfer complete - DCD DMA15_IRQHandler ;DMA channel 15 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 15 error - DCD MCM_IRQHandler ;MCM normal interrupt - DCD FTFL_IRQHandler ;FTFL command complete - DCD FTFL_Collision_IRQHandler ;FTFL read collision - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM - DCD RNG_IRQHandler ;Randon number generator - DCD I2C0_IRQHandler ;Inter-integrated circuit 0 - DCD I2C1_IRQHandler ;Inter-integrated circuit 1 - DCD SPI0_IRQHandler ;Serial peripheral Interface 0 - DCD SPI1_IRQHandler ;Serial peripheral Interface 1 - DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt - DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt - DCD Reserved46_IRQHandler ;Reserved interrupt - DCD UART0_RX_TX_IRQHandler ;UART0 receive/transmit interrupt - DCD UART0_ERR_IRQHandler ;UART0 error interrupt - DCD UART1_RX_TX_IRQHandler ;UART1 receive/transmit interrupt - DCD UART1_ERR_IRQHandler ;UART1 error interrupt - DCD UART2_RX_TX_IRQHandler ;UART2 receive/transmit interrupt - DCD UART2_ERR_IRQHandler ;UART2 error interrupt - DCD Reserved53_IRQHandler ;Reserved interrupt - DCD Reserved54_IRQHandler ;Reserved interrupt - DCD ADC0_IRQHandler ;Analog-to-digital converter 0 - DCD CMP0_IRQHandler ;Comparator 0 - DCD CMP1_IRQHandler ;Comparator 1 - DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ;Carrier modulator transmitter - DCD RTC_IRQHandler ;Real time clock - DCD RTC_Seconds_IRQHandler ;Real time clock seconds - DCD PIT0_IRQHandler ;Periodic interrupt timer channel 0 - DCD PIT1_IRQHandler ;Periodic interrupt timer channel 1 - DCD PIT2_IRQHandler ;Periodic interrupt timer channel 2 - DCD PIT3_IRQHandler ;Periodic interrupt timer channel 3 - DCD PDB0_IRQHandler ;Programmable delay block - DCD USB0_IRQHandler ;USB OTG interrupt - DCD USBDCD_IRQHandler ;USB charger detect - DCD Reserved71_IRQHandler ;Reserved interrupt - DCD Reserved72_IRQHandler ;Reserved interrupt - DCD MCG_IRQHandler ;Multipurpose clock generator - DCD LPTMR0_IRQHandler ;Low power timer interrupt - DCD PORTA_IRQHandler ;Port A pin detect interrupt - DCD PORTB_IRQHandler ;Port B pin detect interrupt - DCD PORTC_IRQHandler ;Port C pin detect interrupt - DCD PORTD_IRQHandler ;Port D pin detect interrupt - DCD PORTE_IRQHandler ;Port E pin detect interrupt - DCD SWI_IRQHandler ;Software interrupt - DCD DefaultISR ;81 - DCD DefaultISR ;82 - DCD DefaultISR ;83 - DCD DefaultISR ;84 - DCD DefaultISR ;85 - DCD DefaultISR ;86 - DCD DefaultISR ;87 - DCD DefaultISR ;88 - DCD DefaultISR ;89 - DCD DefaultISR ;90 - DCD DefaultISR ;91 - DCD DefaultISR ;92 - DCD DefaultISR ;93 - DCD DefaultISR ;94 - DCD DefaultISR ;95 - DCD DefaultISR ;96 - DCD DefaultISR ;97 - DCD DefaultISR ;98 - DCD DefaultISR ;99 - DCD DefaultISR ;100 - DCD DefaultISR ;101 - DCD DefaultISR ;102 - DCD DefaultISR ;103 - DCD DefaultISR ;104 - DCD DefaultISR ;105 - DCD DefaultISR ;106 - DCD DefaultISR ;107 - DCD DefaultISR ;108 - DCD DefaultISR ;109 - DCD DefaultISR ;110 - DCD DefaultISR ;111 - DCD DefaultISR ;112 - DCD DefaultISR ;113 - DCD DefaultISR ;114 - DCD DefaultISR ;115 - DCD DefaultISR ;116 - DCD DefaultISR ;117 - DCD DefaultISR ;118 - DCD DefaultISR ;119 - DCD DefaultISR ;120 - DCD DefaultISR ;121 - DCD DefaultISR ;122 - DCD DefaultISR ;123 - DCD DefaultISR ;124 - DCD DefaultISR ;125 - DCD DefaultISR ;126 - DCD DefaultISR ;127 - DCD DefaultISR ;128 - DCD DefaultISR ;129 - DCD DefaultISR ;130 - DCD DefaultISR ;131 - DCD DefaultISR ;132 - DCD DefaultISR ;133 - DCD DefaultISR ;134 - DCD DefaultISR ;135 - DCD DefaultISR ;136 - DCD DefaultISR ;137 - DCD DefaultISR ;138 - DCD DefaultISR ;139 - DCD DefaultISR ;140 - DCD DefaultISR ;141 - DCD DefaultISR ;142 - DCD DefaultISR ;143 - DCD DefaultISR ;144 - DCD DefaultISR ;145 - DCD DefaultISR ;146 - DCD DefaultISR ;147 - DCD DefaultISR ;148 - DCD DefaultISR ;149 - DCD DefaultISR ;150 - DCD DefaultISR ;151 - DCD DefaultISR ;152 - DCD DefaultISR ;153 - DCD DefaultISR ;154 - DCD DefaultISR ;155 - DCD DefaultISR ;156 - DCD DefaultISR ;157 - DCD DefaultISR ;158 - DCD DefaultISR ;159 - DCD DefaultISR ;160 - DCD DefaultISR ;161 - DCD DefaultISR ;162 - DCD DefaultISR ;163 - DCD DefaultISR ;164 - DCD DefaultISR ;165 - DCD DefaultISR ;166 - DCD DefaultISR ;167 - DCD DefaultISR ;168 - DCD DefaultISR ;169 - DCD DefaultISR ;170 - DCD DefaultISR ;171 - DCD DefaultISR ;172 - DCD DefaultISR ;173 - DCD DefaultISR ;174 - DCD DefaultISR ;175 - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_IRQHandler - LDR R0, =DMA2_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_IRQHandler - LDR R0, =DMA3_DriverIRQHandler - BX R0 - - PUBWEAK DMA4_IRQHandler - PUBWEAK DMA4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA4_IRQHandler - LDR R0, =DMA4_DriverIRQHandler - BX R0 - - PUBWEAK DMA5_IRQHandler - PUBWEAK DMA5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA5_IRQHandler - LDR R0, =DMA5_DriverIRQHandler - BX R0 - - PUBWEAK DMA6_IRQHandler - PUBWEAK DMA6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA6_IRQHandler - LDR R0, =DMA6_DriverIRQHandler - BX R0 - - PUBWEAK DMA7_IRQHandler - PUBWEAK DMA7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA7_IRQHandler - LDR R0, =DMA7_DriverIRQHandler - BX R0 - - PUBWEAK DMA8_IRQHandler - PUBWEAK DMA8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA8_IRQHandler - LDR R0, =DMA8_DriverIRQHandler - BX R0 - - PUBWEAK DMA9_IRQHandler - PUBWEAK DMA9_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA9_IRQHandler - LDR R0, =DMA9_DriverIRQHandler - BX R0 - - PUBWEAK DMA10_IRQHandler - PUBWEAK DMA10_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA10_IRQHandler - LDR R0, =DMA10_DriverIRQHandler - BX R0 - - PUBWEAK DMA11_IRQHandler - PUBWEAK DMA11_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA11_IRQHandler - LDR R0, =DMA11_DriverIRQHandler - BX R0 - - PUBWEAK DMA12_IRQHandler - PUBWEAK DMA12_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA12_IRQHandler - LDR R0, =DMA12_DriverIRQHandler - BX R0 - - PUBWEAK DMA13_IRQHandler - PUBWEAK DMA13_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA13_IRQHandler - LDR R0, =DMA13_DriverIRQHandler - BX R0 - - PUBWEAK DMA14_IRQHandler - PUBWEAK DMA14_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA14_IRQHandler - LDR R0, =DMA14_DriverIRQHandler - BX R0 - - PUBWEAK DMA15_IRQHandler - PUBWEAK DMA15_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA15_IRQHandler - LDR R0, =DMA15_DriverIRQHandler - BX R0 - - PUBWEAK DMA_Error_IRQHandler - PUBWEAK DMA_Error_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA_Error_IRQHandler - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - - PUBWEAK MCM_IRQHandler - PUBWEAK FTFL_IRQHandler - PUBWEAK FTFL_Collision_IRQHandler - PUBWEAK PMC_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK WDOG_EWM_IRQHandler - PUBWEAK RNG_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK I2S0_Tx_IRQHandler - PUBWEAK I2S0_Tx_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_Tx_IRQHandler - LDR R0, =I2S0_Tx_DriverIRQHandler - BX R0 - - PUBWEAK I2S0_Rx_IRQHandler - PUBWEAK I2S0_Rx_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_Rx_IRQHandler - LDR R0, =I2S0_Rx_DriverIRQHandler - BX R0 - - PUBWEAK Reserved46_IRQHandler - PUBWEAK UART0_RX_TX_IRQHandler - PUBWEAK UART0_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART0_RX_TX_IRQHandler - LDR R0, =UART0_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART0_ERR_IRQHandler - PUBWEAK UART0_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART0_ERR_IRQHandler - LDR R0, =UART0_ERR_DriverIRQHandler - BX R0 - - PUBWEAK UART1_RX_TX_IRQHandler - PUBWEAK UART1_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART1_RX_TX_IRQHandler - LDR R0, =UART1_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART1_ERR_IRQHandler - PUBWEAK UART1_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART1_ERR_IRQHandler - LDR R0, =UART1_ERR_DriverIRQHandler - BX R0 - - PUBWEAK UART2_RX_TX_IRQHandler - PUBWEAK UART2_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_RX_TX_IRQHandler - LDR R0, =UART2_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART2_ERR_IRQHandler - PUBWEAK UART2_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_ERR_IRQHandler - LDR R0, =UART2_ERR_DriverIRQHandler - BX R0 - - PUBWEAK Reserved53_IRQHandler - PUBWEAK Reserved54_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK CMP1_IRQHandler - PUBWEAK FTM0_IRQHandler - PUBWEAK FTM1_IRQHandler - PUBWEAK FTM2_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK PIT1_IRQHandler - PUBWEAK PIT2_IRQHandler - PUBWEAK PIT3_IRQHandler - PUBWEAK PDB0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK USBDCD_IRQHandler - PUBWEAK Reserved71_IRQHandler - PUBWEAK Reserved72_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK SWI_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(1) -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -DMA8_DriverIRQHandler -DMA9_DriverIRQHandler -DMA10_DriverIRQHandler -DMA11_DriverIRQHandler -DMA12_DriverIRQHandler -DMA13_DriverIRQHandler -DMA14_DriverIRQHandler -DMA15_DriverIRQHandler -DMA_Error_DriverIRQHandler -MCM_IRQHandler -FTFL_IRQHandler -FTFL_Collision_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -WDOG_EWM_IRQHandler -RNG_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -I2S0_Tx_DriverIRQHandler -I2S0_Rx_DriverIRQHandler -Reserved46_IRQHandler -UART0_RX_TX_DriverIRQHandler -UART0_ERR_DriverIRQHandler -UART1_RX_TX_DriverIRQHandler -UART1_ERR_DriverIRQHandler -UART2_RX_TX_DriverIRQHandler -UART2_ERR_DriverIRQHandler -Reserved53_IRQHandler -Reserved54_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -Reserved72_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -DefaultISR - B DefaultISR - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.S new file mode 100644 index 0000000..33f583e --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.S @@ -0,0 +1,305 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKW41Z4.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKW41Z4 +; @version: 1.0 +; @date: 2015-9-23 +; @build: b160720 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD LVD_LVW_DCDC_IRQHandler ;Low-voltage detect, low-voltage warning, DCDC + DCD LLWU_IRQHandler ;Low leakage wakeup Unit + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD TSI0_IRQHandler ;TSI0 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD TRNG0_IRQHandler ;TRNG0 interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD LTC0_IRQHandler ;LTC0 interrupt + DCD Radio_0_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 0 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD Radio_1_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 1 + DCD MCG_IRQHandler ;MCG interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTB_PORTC_IRQHandler ;PORTB and PORTC Pin detect +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK LVD_LVW_DCDC_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK TSI0_IRQHandler + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK TRNG0_IRQHandler + PUBWEAK CMT_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK LTC0_IRQHandler + PUBWEAK Radio_0_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK Radio_1_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_PORTC_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_DCDC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +TSI0_IRQHandler +LPUART0_DriverIRQHandler +TRNG0_IRQHandler +CMT_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +LTC0_IRQHandler +Radio_0_IRQHandler +DAC0_IRQHandler +Radio_1_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +SPI1_DriverIRQHandler +PORTA_IRQHandler +PORTB_PORTC_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.s deleted file mode 100644 index 33f583e..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.s +++ /dev/null @@ -1,305 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKW41Z4.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKW41Z4 -; @version: 1.0 -; @date: 2015-9-23 -; @build: b160720 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;Command complete and read collision - DCD LVD_LVW_DCDC_IRQHandler ;Low-voltage detect, low-voltage warning, DCDC - DCD LLWU_IRQHandler ;Low leakage wakeup Unit - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD TSI0_IRQHandler ;TSI0 single interrupt vector for all sources - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD TRNG0_IRQHandler ;TRNG0 interrupt - DCD CMT_IRQHandler ;CMT interrupt - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD PIT_IRQHandler ;PIT interrupt - DCD LTC0_IRQHandler ;LTC0 interrupt - DCD Radio_0_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 0 - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD Radio_1_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 1 - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD PORTA_IRQHandler ;PORTA Pin detect - DCD PORTB_PORTC_IRQHandler ;PORTB and PORTC Pin detect -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_IRQHandler - LDR R0, =DMA2_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_IRQHandler - LDR R0, =DMA3_DriverIRQHandler - BX R0 - - PUBWEAK Reserved20_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK LVD_LVW_DCDC_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK TSI0_IRQHandler - PUBWEAK LPUART0_IRQHandler - PUBWEAK LPUART0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART0_IRQHandler - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - - PUBWEAK TRNG0_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK LTC0_IRQHandler - PUBWEAK Radio_0_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK Radio_1_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_PORTC_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_DCDC_IRQHandler -LLWU_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -TSI0_IRQHandler -LPUART0_DriverIRQHandler -TRNG0_IRQHandler -CMT_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -LTC0_IRQHandler -Radio_0_IRQHandler -DAC0_IRQHandler -Radio_1_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -SPI1_DriverIRQHandler -PORTA_IRQHandler -PORTB_PORTC_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.S new file mode 100644 index 0000000..ddfb954 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.S @@ -0,0 +1,1023 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MK24F12.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * MK24F12 +; * @version: 2.8 +; * @date: 2016-3-21 +; * @build: b160321 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20030000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTFE_IRQHandler ;FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD UART0_LON_IRQHandler ;UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ;UART3 Error interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD USBDCD_IRQHandler ;USBDCD Interrupt + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD SPI2_IRQHandler ;SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ;UART4 Error interrupt + DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt + DCD UART5_ERR_IRQHandler ;UART5 Error interrupt + DCD CMP2_IRQHandler ;CMP2 interrupt + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD I2C2_IRQHandler ;I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ;CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt + DCD SDHC_IRQHandler ;SDHC interrupt + DCD Reserved98_IRQHandler ;Reserved interrupt 98 + DCD Reserved99_IRQHandler ;Reserved interrupt 99 + DCD Reserved100_IRQHandler ;Reserved interrupt 100 + DCD Reserved101_IRQHandler ;Reserved interrupt 101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Data flash protection byte (FDPROT) +; Each bit protects a 1/8 region of the data flash memory. +; (Program flash only devices: Reserved) +; FDPROT.0 +; FDPROT.1 +; FDPROT.2 +; FDPROT.3 +; FDPROT.4 +; FDPROT.5 +; FDPROT.6 +; FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; +; EEPROM protection byte (FEPROT) +; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; (Program flash only devices: Reserved) +; FEPROT.0 +; FEPROT.1 +; FEPROT.2 +; FEPROT.3 +; FEPROT.4 +; FEPROT.5 +; FEPROT.6 +; FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; EZPORT_DIS +; <0=> EzPort operation is disabled +; <1=> EzPort operation is enabled +FOPT EQU 0xFF +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , FEPROT , FDPROT + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +DMA4_IRQHandler\ + PROC + EXPORT DMA4_IRQHandler [WEAK] + LDR R0, =DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA5_IRQHandler\ + PROC + EXPORT DMA5_IRQHandler [WEAK] + LDR R0, =DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA6_IRQHandler\ + PROC + EXPORT DMA6_IRQHandler [WEAK] + LDR R0, =DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA7_IRQHandler\ + PROC + EXPORT DMA7_IRQHandler [WEAK] + LDR R0, =DMA7_DriverIRQHandler + BX R0 + ENDP + +DMA8_IRQHandler\ + PROC + EXPORT DMA8_IRQHandler [WEAK] + LDR R0, =DMA8_DriverIRQHandler + BX R0 + ENDP + +DMA9_IRQHandler\ + PROC + EXPORT DMA9_IRQHandler [WEAK] + LDR R0, =DMA9_DriverIRQHandler + BX R0 + ENDP + +DMA10_IRQHandler\ + PROC + EXPORT DMA10_IRQHandler [WEAK] + LDR R0, =DMA10_DriverIRQHandler + BX R0 + ENDP + +DMA11_IRQHandler\ + PROC + EXPORT DMA11_IRQHandler [WEAK] + LDR R0, =DMA11_DriverIRQHandler + BX R0 + ENDP + +DMA12_IRQHandler\ + PROC + EXPORT DMA12_IRQHandler [WEAK] + LDR R0, =DMA12_DriverIRQHandler + BX R0 + ENDP + +DMA13_IRQHandler\ + PROC + EXPORT DMA13_IRQHandler [WEAK] + LDR R0, =DMA13_DriverIRQHandler + BX R0 + ENDP + +DMA14_IRQHandler\ + PROC + EXPORT DMA14_IRQHandler [WEAK] + LDR R0, =DMA14_DriverIRQHandler + BX R0 + ENDP + +DMA15_IRQHandler\ + PROC + EXPORT DMA15_IRQHandler [WEAK] + LDR R0, =DMA15_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +I2S0_Tx_IRQHandler\ + PROC + EXPORT I2S0_Tx_IRQHandler [WEAK] + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + ENDP + +I2S0_Rx_IRQHandler\ + PROC + EXPORT I2S0_Rx_IRQHandler [WEAK] + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + ENDP + +UART0_LON_IRQHandler\ + PROC + EXPORT UART0_LON_IRQHandler [WEAK] + LDR R0, =UART0_LON_DriverIRQHandler + BX R0 + ENDP + +UART0_RX_TX_IRQHandler\ + PROC + EXPORT UART0_RX_TX_IRQHandler [WEAK] + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART0_ERR_IRQHandler\ + PROC + EXPORT UART0_ERR_IRQHandler [WEAK] + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + ENDP + +UART1_RX_TX_IRQHandler\ + PROC + EXPORT UART1_RX_TX_IRQHandler [WEAK] + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART1_ERR_IRQHandler\ + PROC + EXPORT UART1_ERR_IRQHandler [WEAK] + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + ENDP + +UART2_RX_TX_IRQHandler\ + PROC + EXPORT UART2_RX_TX_IRQHandler [WEAK] + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART2_ERR_IRQHandler\ + PROC + EXPORT UART2_ERR_IRQHandler [WEAK] + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + ENDP + +UART3_RX_TX_IRQHandler\ + PROC + EXPORT UART3_RX_TX_IRQHandler [WEAK] + LDR R0, =UART3_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART3_ERR_IRQHandler\ + PROC + EXPORT UART3_ERR_IRQHandler [WEAK] + LDR R0, =UART3_ERR_DriverIRQHandler + BX R0 + ENDP + +SPI2_IRQHandler\ + PROC + EXPORT SPI2_IRQHandler [WEAK] + LDR R0, =SPI2_DriverIRQHandler + BX R0 + ENDP + +UART4_RX_TX_IRQHandler\ + PROC + EXPORT UART4_RX_TX_IRQHandler [WEAK] + LDR R0, =UART4_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART4_ERR_IRQHandler\ + PROC + EXPORT UART4_ERR_IRQHandler [WEAK] + LDR R0, =UART4_ERR_DriverIRQHandler + BX R0 + ENDP + +UART5_RX_TX_IRQHandler\ + PROC + EXPORT UART5_RX_TX_IRQHandler [WEAK] + LDR R0, =UART5_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART5_ERR_IRQHandler\ + PROC + EXPORT UART5_ERR_IRQHandler [WEAK] + LDR R0, =UART5_ERR_DriverIRQHandler + BX R0 + ENDP + +I2C2_IRQHandler\ + PROC + EXPORT I2C2_IRQHandler [WEAK] + LDR R0, =I2C2_DriverIRQHandler + BX R0 + ENDP + +CAN0_ORed_Message_buffer_IRQHandler\ + PROC + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Bus_Off_IRQHandler\ + PROC + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Error_IRQHandler\ + PROC + EXPORT CAN0_Error_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Tx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Rx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Wake_Up_IRQHandler\ + PROC + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +SDHC_IRQHandler\ + PROC + EXPORT SDHC_IRQHandler [WEAK] + LDR R0, =SDHC_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT DMA4_DriverIRQHandler [WEAK] + EXPORT DMA5_DriverIRQHandler [WEAK] + EXPORT DMA6_DriverIRQHandler [WEAK] + EXPORT DMA7_DriverIRQHandler [WEAK] + EXPORT DMA8_DriverIRQHandler [WEAK] + EXPORT DMA9_DriverIRQHandler [WEAK] + EXPORT DMA10_DriverIRQHandler [WEAK] + EXPORT DMA11_DriverIRQHandler [WEAK] + EXPORT DMA12_DriverIRQHandler [WEAK] + EXPORT DMA13_DriverIRQHandler [WEAK] + EXPORT DMA14_DriverIRQHandler [WEAK] + EXPORT DMA15_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT MCM_IRQHandler [WEAK] + EXPORT FTFE_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT I2S0_Tx_DriverIRQHandler [WEAK] + EXPORT I2S0_Rx_DriverIRQHandler [WEAK] + EXPORT UART0_LON_DriverIRQHandler [WEAK] + EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART0_ERR_DriverIRQHandler [WEAK] + EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART1_ERR_DriverIRQHandler [WEAK] + EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART2_ERR_DriverIRQHandler [WEAK] + EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART3_ERR_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT SPI2_DriverIRQHandler [WEAK] + EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART4_ERR_DriverIRQHandler [WEAK] + EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART5_ERR_DriverIRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT I2C2_DriverIRQHandler [WEAK] + EXPORT CAN0_DriverIRQHandler [WEAK] + EXPORT SDHC_DriverIRQHandler [WEAK] + EXPORT Reserved98_IRQHandler [WEAK] + EXPORT Reserved99_IRQHandler [WEAK] + EXPORT Reserved100_IRQHandler [WEAK] + EXPORT Reserved101_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +UART0_LON_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +UART3_RX_TX_DriverIRQHandler +UART3_ERR_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_DriverIRQHandler +UART4_RX_TX_DriverIRQHandler +UART4_ERR_DriverIRQHandler +UART5_RX_TX_DriverIRQHandler +UART5_ERR_DriverIRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_DriverIRQHandler +CAN0_DriverIRQHandler +SDHC_DriverIRQHandler +Reserved98_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +Reserved101_IRQHandler +DefaultISR + B DefaultISR + ENDP + ALIGN + + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.s deleted file mode 100644 index ddfb954..0000000 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.s +++ /dev/null @@ -1,1023 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MK24F12.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * MK24F12 -; * @version: 2.8 -; * @date: 2016-3-21 -; * @build: b160321 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - -__initial_sp EQU 0x20030000 ; Top of RAM - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete - DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete - DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete - DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete - DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete - DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete - DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete - DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete - DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete - DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete - DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete - DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete - DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete - DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete - DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete - DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete - DCD DMA_Error_IRQHandler ;DMA Error Interrupt - DCD MCM_IRQHandler ;Normal Interrupt - DCD FTFE_IRQHandler ;FTFE Command complete interrupt - DCD Read_Collision_IRQHandler ;Read Collision Interrupt - DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit - DCD WDOG_EWM_IRQHandler ;WDOG Interrupt - DCD RNG_IRQHandler ;RNG Interrupt - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 Interrupt - DCD SPI1_IRQHandler ;SPI1 Interrupt - DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt - DCD UART0_LON_IRQHandler ;UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt - DCD UART0_ERR_IRQHandler ;UART0 Error interrupt - DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt - DCD UART1_ERR_IRQHandler ;UART1 Error interrupt - DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt - DCD UART2_ERR_IRQHandler ;UART2 Error interrupt - DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt - DCD UART3_ERR_IRQHandler ;UART3 Error interrupt - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD CMP1_IRQHandler ;CMP1 interrupt - DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ;CMT interrupt - DCD RTC_IRQHandler ;RTC interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ;PDB0 Interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD USBDCD_IRQHandler ;USBDCD Interrupt - DCD Reserved71_IRQHandler ;Reserved interrupt 71 - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD MCG_IRQHandler ;MCG Interrupt - DCD LPTMR0_IRQHandler ;LPTimer interrupt - DCD PORTA_IRQHandler ;Port A interrupt - DCD PORTB_IRQHandler ;Port B interrupt - DCD PORTC_IRQHandler ;Port C interrupt - DCD PORTD_IRQHandler ;Port D interrupt - DCD PORTE_IRQHandler ;Port E interrupt - DCD SWI_IRQHandler ;Software interrupt - DCD SPI2_IRQHandler ;SPI2 Interrupt - DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt - DCD UART4_ERR_IRQHandler ;UART4 Error interrupt - DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt - DCD UART5_ERR_IRQHandler ;UART5 Error interrupt - DCD CMP2_IRQHandler ;CMP2 interrupt - DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt - DCD DAC1_IRQHandler ;DAC1 interrupt - DCD ADC1_IRQHandler ;ADC1 interrupt - DCD I2C2_IRQHandler ;I2C2 interrupt - DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt - DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt - DCD CAN0_Error_IRQHandler ;CAN0 error interrupt - DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt - DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt - DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt - DCD SDHC_IRQHandler ;SDHC interrupt - DCD Reserved98_IRQHandler ;Reserved interrupt 98 - DCD Reserved99_IRQHandler ;Reserved interrupt 99 - DCD Reserved100_IRQHandler ;Reserved interrupt 100 - DCD Reserved101_IRQHandler ;Reserved interrupt 101 - DCD DefaultISR ;102 - DCD DefaultISR ;103 - DCD DefaultISR ;104 - DCD DefaultISR ;105 - DCD DefaultISR ;106 - DCD DefaultISR ;107 - DCD DefaultISR ;108 - DCD DefaultISR ;109 - DCD DefaultISR ;110 - DCD DefaultISR ;111 - DCD DefaultISR ;112 - DCD DefaultISR ;113 - DCD DefaultISR ;114 - DCD DefaultISR ;115 - DCD DefaultISR ;116 - DCD DefaultISR ;117 - DCD DefaultISR ;118 - DCD DefaultISR ;119 - DCD DefaultISR ;120 - DCD DefaultISR ;121 - DCD DefaultISR ;122 - DCD DefaultISR ;123 - DCD DefaultISR ;124 - DCD DefaultISR ;125 - DCD DefaultISR ;126 - DCD DefaultISR ;127 - DCD DefaultISR ;128 - DCD DefaultISR ;129 - DCD DefaultISR ;130 - DCD DefaultISR ;131 - DCD DefaultISR ;132 - DCD DefaultISR ;133 - DCD DefaultISR ;134 - DCD DefaultISR ;135 - DCD DefaultISR ;136 - DCD DefaultISR ;137 - DCD DefaultISR ;138 - DCD DefaultISR ;139 - DCD DefaultISR ;140 - DCD DefaultISR ;141 - DCD DefaultISR ;142 - DCD DefaultISR ;143 - DCD DefaultISR ;144 - DCD DefaultISR ;145 - DCD DefaultISR ;146 - DCD DefaultISR ;147 - DCD DefaultISR ;148 - DCD DefaultISR ;149 - DCD DefaultISR ;150 - DCD DefaultISR ;151 - DCD DefaultISR ;152 - DCD DefaultISR ;153 - DCD DefaultISR ;154 - DCD DefaultISR ;155 - DCD DefaultISR ;156 - DCD DefaultISR ;157 - DCD DefaultISR ;158 - DCD DefaultISR ;159 - DCD DefaultISR ;160 - DCD DefaultISR ;161 - DCD DefaultISR ;162 - DCD DefaultISR ;163 - DCD DefaultISR ;164 - DCD DefaultISR ;165 - DCD DefaultISR ;166 - DCD DefaultISR ;167 - DCD DefaultISR ;168 - DCD DefaultISR ;169 - DCD DefaultISR ;170 - DCD DefaultISR ;171 - DCD DefaultISR ;172 - DCD DefaultISR ;173 - DCD DefaultISR ;174 - DCD DefaultISR ;175 - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; Flash Configuration -; 16-byte flash configuration field that stores default protection settings (loaded on reset) -; and security information that allows the MCU to restrict access to the FTFL module. -; Backdoor Comparison Key -; Backdoor Comparison Key 0. <0x0-0xFF:2> -; Backdoor Comparison Key 1. <0x0-0xFF:2> -; Backdoor Comparison Key 2. <0x0-0xFF:2> -; Backdoor Comparison Key 3. <0x0-0xFF:2> -; Backdoor Comparison Key 4. <0x0-0xFF:2> -; Backdoor Comparison Key 5. <0x0-0xFF:2> -; Backdoor Comparison Key 6. <0x0-0xFF:2> -; Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; -; Program flash protection bytes (FPROT) -; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; Each bit protects a 1/32 region of the program flash memory. -; FPROT0 -; Program Flash Region Protect Register 0 -; 1/32 - 8/32 region -; FPROT0.0 -; FPROT0.1 -; FPROT0.2 -; FPROT0.3 -; FPROT0.4 -; FPROT0.5 -; FPROT0.6 -; FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; -; FPROT1 -; Program Flash Region Protect Register 1 -; 9/32 - 16/32 region -; FPROT1.0 -; FPROT1.1 -; FPROT1.2 -; FPROT1.3 -; FPROT1.4 -; FPROT1.5 -; FPROT1.6 -; FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; -; FPROT2 -; Program Flash Region Protect Register 2 -; 17/32 - 24/32 region -; FPROT2.0 -; FPROT2.1 -; FPROT2.2 -; FPROT2.3 -; FPROT2.4 -; FPROT2.5 -; FPROT2.6 -; FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; -; FPROT3 -; Program Flash Region Protect Register 3 -; 25/32 - 32/32 region -; FPROT3.0 -; FPROT3.1 -; FPROT3.2 -; FPROT3.3 -; FPROT3.4 -; FPROT3.5 -; FPROT3.6 -; FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; -; -; Data flash protection byte (FDPROT) -; Each bit protects a 1/8 region of the data flash memory. -; (Program flash only devices: Reserved) -; FDPROT.0 -; FDPROT.1 -; FDPROT.2 -; FDPROT.3 -; FDPROT.4 -; FDPROT.5 -; FDPROT.6 -; FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; -; EEPROM protection byte (FEPROT) -; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; (Program flash only devices: Reserved) -; FEPROT.0 -; FEPROT.1 -; FEPROT.2 -; FEPROT.3 -; FEPROT.4 -; FEPROT.5 -; FEPROT.6 -; FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; -; Flash nonvolatile option byte (FOPT) -; Allows the user to customize the operation of the MCU at boot time. -; LPBOOT -; <0=> Low-power boot -; <1=> Normal boot -; EZPORT_DIS -; <0=> EzPort operation is disabled -; <1=> EzPort operation is enabled -FOPT EQU 0xFF -; -; Flash security byte (FSEC) -; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; Flash Security -; FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; Freescale Failure Analysis Access Code -; MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; Backdoor Key Security Enable -FSEC EQU 0xFE -; -; - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , FEPROT , FDPROT - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - REQUIRE FlashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -DMA2_IRQHandler\ - PROC - EXPORT DMA2_IRQHandler [WEAK] - LDR R0, =DMA2_DriverIRQHandler - BX R0 - ENDP - -DMA3_IRQHandler\ - PROC - EXPORT DMA3_IRQHandler [WEAK] - LDR R0, =DMA3_DriverIRQHandler - BX R0 - ENDP - -DMA4_IRQHandler\ - PROC - EXPORT DMA4_IRQHandler [WEAK] - LDR R0, =DMA4_DriverIRQHandler - BX R0 - ENDP - -DMA5_IRQHandler\ - PROC - EXPORT DMA5_IRQHandler [WEAK] - LDR R0, =DMA5_DriverIRQHandler - BX R0 - ENDP - -DMA6_IRQHandler\ - PROC - EXPORT DMA6_IRQHandler [WEAK] - LDR R0, =DMA6_DriverIRQHandler - BX R0 - ENDP - -DMA7_IRQHandler\ - PROC - EXPORT DMA7_IRQHandler [WEAK] - LDR R0, =DMA7_DriverIRQHandler - BX R0 - ENDP - -DMA8_IRQHandler\ - PROC - EXPORT DMA8_IRQHandler [WEAK] - LDR R0, =DMA8_DriverIRQHandler - BX R0 - ENDP - -DMA9_IRQHandler\ - PROC - EXPORT DMA9_IRQHandler [WEAK] - LDR R0, =DMA9_DriverIRQHandler - BX R0 - ENDP - -DMA10_IRQHandler\ - PROC - EXPORT DMA10_IRQHandler [WEAK] - LDR R0, =DMA10_DriverIRQHandler - BX R0 - ENDP - -DMA11_IRQHandler\ - PROC - EXPORT DMA11_IRQHandler [WEAK] - LDR R0, =DMA11_DriverIRQHandler - BX R0 - ENDP - -DMA12_IRQHandler\ - PROC - EXPORT DMA12_IRQHandler [WEAK] - LDR R0, =DMA12_DriverIRQHandler - BX R0 - ENDP - -DMA13_IRQHandler\ - PROC - EXPORT DMA13_IRQHandler [WEAK] - LDR R0, =DMA13_DriverIRQHandler - BX R0 - ENDP - -DMA14_IRQHandler\ - PROC - EXPORT DMA14_IRQHandler [WEAK] - LDR R0, =DMA14_DriverIRQHandler - BX R0 - ENDP - -DMA15_IRQHandler\ - PROC - EXPORT DMA15_IRQHandler [WEAK] - LDR R0, =DMA15_DriverIRQHandler - BX R0 - ENDP - -DMA_Error_IRQHandler\ - PROC - EXPORT DMA_Error_IRQHandler [WEAK] - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - ENDP - -I2C0_IRQHandler\ - PROC - EXPORT I2C0_IRQHandler [WEAK] - LDR R0, =I2C0_DriverIRQHandler - BX R0 - ENDP - -I2C1_IRQHandler\ - PROC - EXPORT I2C1_IRQHandler [WEAK] - LDR R0, =I2C1_DriverIRQHandler - BX R0 - ENDP - -SPI0_IRQHandler\ - PROC - EXPORT SPI0_IRQHandler [WEAK] - LDR R0, =SPI0_DriverIRQHandler - BX R0 - ENDP - -SPI1_IRQHandler\ - PROC - EXPORT SPI1_IRQHandler [WEAK] - LDR R0, =SPI1_DriverIRQHandler - BX R0 - ENDP - -I2S0_Tx_IRQHandler\ - PROC - EXPORT I2S0_Tx_IRQHandler [WEAK] - LDR R0, =I2S0_Tx_DriverIRQHandler - BX R0 - ENDP - -I2S0_Rx_IRQHandler\ - PROC - EXPORT I2S0_Rx_IRQHandler [WEAK] - LDR R0, =I2S0_Rx_DriverIRQHandler - BX R0 - ENDP - -UART0_LON_IRQHandler\ - PROC - EXPORT UART0_LON_IRQHandler [WEAK] - LDR R0, =UART0_LON_DriverIRQHandler - BX R0 - ENDP - -UART0_RX_TX_IRQHandler\ - PROC - EXPORT UART0_RX_TX_IRQHandler [WEAK] - LDR R0, =UART0_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART0_ERR_IRQHandler\ - PROC - EXPORT UART0_ERR_IRQHandler [WEAK] - LDR R0, =UART0_ERR_DriverIRQHandler - BX R0 - ENDP - -UART1_RX_TX_IRQHandler\ - PROC - EXPORT UART1_RX_TX_IRQHandler [WEAK] - LDR R0, =UART1_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART1_ERR_IRQHandler\ - PROC - EXPORT UART1_ERR_IRQHandler [WEAK] - LDR R0, =UART1_ERR_DriverIRQHandler - BX R0 - ENDP - -UART2_RX_TX_IRQHandler\ - PROC - EXPORT UART2_RX_TX_IRQHandler [WEAK] - LDR R0, =UART2_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART2_ERR_IRQHandler\ - PROC - EXPORT UART2_ERR_IRQHandler [WEAK] - LDR R0, =UART2_ERR_DriverIRQHandler - BX R0 - ENDP - -UART3_RX_TX_IRQHandler\ - PROC - EXPORT UART3_RX_TX_IRQHandler [WEAK] - LDR R0, =UART3_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART3_ERR_IRQHandler\ - PROC - EXPORT UART3_ERR_IRQHandler [WEAK] - LDR R0, =UART3_ERR_DriverIRQHandler - BX R0 - ENDP - -SPI2_IRQHandler\ - PROC - EXPORT SPI2_IRQHandler [WEAK] - LDR R0, =SPI2_DriverIRQHandler - BX R0 - ENDP - -UART4_RX_TX_IRQHandler\ - PROC - EXPORT UART4_RX_TX_IRQHandler [WEAK] - LDR R0, =UART4_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART4_ERR_IRQHandler\ - PROC - EXPORT UART4_ERR_IRQHandler [WEAK] - LDR R0, =UART4_ERR_DriverIRQHandler - BX R0 - ENDP - -UART5_RX_TX_IRQHandler\ - PROC - EXPORT UART5_RX_TX_IRQHandler [WEAK] - LDR R0, =UART5_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART5_ERR_IRQHandler\ - PROC - EXPORT UART5_ERR_IRQHandler [WEAK] - LDR R0, =UART5_ERR_DriverIRQHandler - BX R0 - ENDP - -I2C2_IRQHandler\ - PROC - EXPORT I2C2_IRQHandler [WEAK] - LDR R0, =I2C2_DriverIRQHandler - BX R0 - ENDP - -CAN0_ORed_Message_buffer_IRQHandler\ - PROC - EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Bus_Off_IRQHandler\ - PROC - EXPORT CAN0_Bus_Off_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Error_IRQHandler\ - PROC - EXPORT CAN0_Error_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Tx_Warning_IRQHandler\ - PROC - EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Rx_Warning_IRQHandler\ - PROC - EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Wake_Up_IRQHandler\ - PROC - EXPORT CAN0_Wake_Up_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -SDHC_IRQHandler\ - PROC - EXPORT SDHC_IRQHandler [WEAK] - LDR R0, =SDHC_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT DMA2_DriverIRQHandler [WEAK] - EXPORT DMA3_DriverIRQHandler [WEAK] - EXPORT DMA4_DriverIRQHandler [WEAK] - EXPORT DMA5_DriverIRQHandler [WEAK] - EXPORT DMA6_DriverIRQHandler [WEAK] - EXPORT DMA7_DriverIRQHandler [WEAK] - EXPORT DMA8_DriverIRQHandler [WEAK] - EXPORT DMA9_DriverIRQHandler [WEAK] - EXPORT DMA10_DriverIRQHandler [WEAK] - EXPORT DMA11_DriverIRQHandler [WEAK] - EXPORT DMA12_DriverIRQHandler [WEAK] - EXPORT DMA13_DriverIRQHandler [WEAK] - EXPORT DMA14_DriverIRQHandler [WEAK] - EXPORT DMA15_DriverIRQHandler [WEAK] - EXPORT DMA_Error_DriverIRQHandler [WEAK] - EXPORT MCM_IRQHandler [WEAK] - EXPORT FTFE_IRQHandler [WEAK] - EXPORT Read_Collision_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT WDOG_EWM_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT I2C0_DriverIRQHandler [WEAK] - EXPORT I2C1_DriverIRQHandler [WEAK] - EXPORT SPI0_DriverIRQHandler [WEAK] - EXPORT SPI1_DriverIRQHandler [WEAK] - EXPORT I2S0_Tx_DriverIRQHandler [WEAK] - EXPORT I2S0_Rx_DriverIRQHandler [WEAK] - EXPORT UART0_LON_DriverIRQHandler [WEAK] - EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART0_ERR_DriverIRQHandler [WEAK] - EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART1_ERR_DriverIRQHandler [WEAK] - EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART2_ERR_DriverIRQHandler [WEAK] - EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART3_ERR_DriverIRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT FTM2_IRQHandler [WEAK] - EXPORT CMT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USBDCD_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT SPI2_DriverIRQHandler [WEAK] - EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART4_ERR_DriverIRQHandler [WEAK] - EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART5_ERR_DriverIRQHandler [WEAK] - EXPORT CMP2_IRQHandler [WEAK] - EXPORT FTM3_IRQHandler [WEAK] - EXPORT DAC1_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT I2C2_DriverIRQHandler [WEAK] - EXPORT CAN0_DriverIRQHandler [WEAK] - EXPORT SDHC_DriverIRQHandler [WEAK] - EXPORT Reserved98_IRQHandler [WEAK] - EXPORT Reserved99_IRQHandler [WEAK] - EXPORT Reserved100_IRQHandler [WEAK] - EXPORT Reserved101_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -DMA8_DriverIRQHandler -DMA9_DriverIRQHandler -DMA10_DriverIRQHandler -DMA11_DriverIRQHandler -DMA12_DriverIRQHandler -DMA13_DriverIRQHandler -DMA14_DriverIRQHandler -DMA15_DriverIRQHandler -DMA_Error_DriverIRQHandler -MCM_IRQHandler -FTFE_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -WDOG_EWM_IRQHandler -RNG_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -I2S0_Tx_DriverIRQHandler -I2S0_Rx_DriverIRQHandler -UART0_LON_DriverIRQHandler -UART0_RX_TX_DriverIRQHandler -UART0_ERR_DriverIRQHandler -UART1_RX_TX_DriverIRQHandler -UART1_ERR_DriverIRQHandler -UART2_RX_TX_DriverIRQHandler -UART2_ERR_DriverIRQHandler -UART3_RX_TX_DriverIRQHandler -UART3_ERR_DriverIRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -DAC0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -SPI2_DriverIRQHandler -UART4_RX_TX_DriverIRQHandler -UART4_ERR_DriverIRQHandler -UART5_RX_TX_DriverIRQHandler -UART5_ERR_DriverIRQHandler -CMP2_IRQHandler -FTM3_IRQHandler -DAC1_IRQHandler -ADC1_IRQHandler -I2C2_DriverIRQHandler -CAN0_DriverIRQHandler -SDHC_DriverIRQHandler -Reserved98_IRQHandler -Reserved99_IRQHandler -Reserved100_IRQHandler -Reserved101_IRQHandler -DefaultISR - B DefaultISR - ENDP - ALIGN - - - END diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S new file mode 100644 index 0000000..aac3e2c --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S @@ -0,0 +1,245 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + +__initial_sp EQU 0x20010000 + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IMPORT nrf_reloc_vector_table + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMonitor_Handler\ + PROC + EXPORT DebugMonitor_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT POWER_CLOCK_IRQHandler [WEAK] + EXPORT RADIO_IRQHandler [WEAK] + EXPORT UARTE0_UART0_IRQHandler_v [WEAK] + EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] + EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] + EXPORT NFCT_IRQHandler_v [WEAK] + EXPORT GPIOTE_IRQHandler_v [WEAK] + EXPORT SAADC_IRQHandler_v [WEAK] + EXPORT TIMER0_IRQHandler_v [WEAK] + EXPORT TIMER1_IRQHandler_v [WEAK] + EXPORT TIMER2_IRQHandler_v [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler_v [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ECB_IRQHandler [WEAK] + EXPORT CCM_AAR_IRQHandler [WEAK] + EXPORT WDT_IRQHandler_v [WEAK] + EXPORT RTC1_IRQHandler_v [WEAK] + EXPORT QDEC_IRQHandler_v [WEAK] + EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] + EXPORT SWI0_EGU0_IRQHandler_v [WEAK] + EXPORT SWI1_EGU1_IRQHandler_v [WEAK] + EXPORT SWI2_EGU2_IRQHandler_v [WEAK] + EXPORT SWI3_EGU3_IRQHandler_v [WEAK] + EXPORT SWI4_EGU4_IRQHandler [WEAK] + EXPORT SWI5_EGU5_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler_v [WEAK] + EXPORT TIMER4_IRQHandler_v [WEAK] + EXPORT PWM0_IRQHandler_v [WEAK] + EXPORT PDM_IRQHandler_v [WEAK] + EXPORT MWU_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler_v [WEAK] + EXPORT PWM2_IRQHandler_v [WEAK] + EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] + EXPORT RTC2_IRQHandler_v [WEAK] + EXPORT I2S_IRQHandler_v [WEAK] + EXPORT FPU_IRQHandler_v [WEAK] +POWER_CLOCK_IRQHandler +RADIO_IRQHandler +UARTE0_UART0_IRQHandler_v +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v +NFCT_IRQHandler_v +GPIOTE_IRQHandler_v +SAADC_IRQHandler_v +TIMER0_IRQHandler_v +TIMER1_IRQHandler_v +TIMER2_IRQHandler_v +RTC0_IRQHandler +TEMP_IRQHandler_v +RNG_IRQHandler +ECB_IRQHandler +CCM_AAR_IRQHandler +WDT_IRQHandler_v +RTC1_IRQHandler_v +QDEC_IRQHandler_v +COMP_LPCOMP_IRQHandler_v +SWI0_EGU0_IRQHandler_v +SWI1_EGU1_IRQHandler_v +SWI2_EGU2_IRQHandler_v +SWI3_EGU3_IRQHandler_v +SWI4_EGU4_IRQHandler +SWI5_EGU5_IRQHandler +TIMER3_IRQHandler_v +TIMER4_IRQHandler_v +PWM0_IRQHandler_v +PDM_IRQHandler_v +MWU_IRQHandler +PWM1_IRQHandler_v +PWM2_IRQHandler_v +SPIM2_SPIS2_SPI2_IRQHandler_v +RTC2_IRQHandler_v +I2S_IRQHandler_v +FPU_IRQHandler_v + B . + ENDP + ALIGN + END diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s deleted file mode 100644 index aac3e2c..0000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s +++ /dev/null @@ -1,245 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - -__initial_sp EQU 0x20010000 - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT nrf_reloc_vector_table - - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemoryManagement_Handler\ - PROC - EXPORT MemoryManagement_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMonitor_Handler\ - PROC - EXPORT DebugMonitor_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UARTE0_UART0_IRQHandler_v [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] - EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] - EXPORT NFCT_IRQHandler_v [WEAK] - EXPORT GPIOTE_IRQHandler_v [WEAK] - EXPORT SAADC_IRQHandler_v [WEAK] - EXPORT TIMER0_IRQHandler_v [WEAK] - EXPORT TIMER1_IRQHandler_v [WEAK] - EXPORT TIMER2_IRQHandler_v [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler_v [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler_v [WEAK] - EXPORT RTC1_IRQHandler_v [WEAK] - EXPORT QDEC_IRQHandler_v [WEAK] - EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] - EXPORT SWI0_EGU0_IRQHandler_v [WEAK] - EXPORT SWI1_EGU1_IRQHandler_v [WEAK] - EXPORT SWI2_EGU2_IRQHandler_v [WEAK] - EXPORT SWI3_EGU3_IRQHandler_v [WEAK] - EXPORT SWI4_EGU4_IRQHandler [WEAK] - EXPORT SWI5_EGU5_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler_v [WEAK] - EXPORT TIMER4_IRQHandler_v [WEAK] - EXPORT PWM0_IRQHandler_v [WEAK] - EXPORT PDM_IRQHandler_v [WEAK] - EXPORT MWU_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler_v [WEAK] - EXPORT PWM2_IRQHandler_v [WEAK] - EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] - EXPORT RTC2_IRQHandler_v [WEAK] - EXPORT I2S_IRQHandler_v [WEAK] - EXPORT FPU_IRQHandler_v [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UARTE0_UART0_IRQHandler_v -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v -NFCT_IRQHandler_v -GPIOTE_IRQHandler_v -SAADC_IRQHandler_v -TIMER0_IRQHandler_v -TIMER1_IRQHandler_v -TIMER2_IRQHandler_v -RTC0_IRQHandler -TEMP_IRQHandler_v -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler_v -RTC1_IRQHandler_v -QDEC_IRQHandler_v -COMP_LPCOMP_IRQHandler_v -SWI0_EGU0_IRQHandler_v -SWI1_EGU1_IRQHandler_v -SWI2_EGU2_IRQHandler_v -SWI3_EGU3_IRQHandler_v -SWI4_EGU4_IRQHandler -SWI5_EGU5_IRQHandler -TIMER3_IRQHandler_v -TIMER4_IRQHandler_v -PWM0_IRQHandler_v -PDM_IRQHandler_v -MWU_IRQHandler -PWM1_IRQHandler_v -PWM2_IRQHandler_v -SPIM2_SPIS2_SPI2_IRQHandler_v -RTC2_IRQHandler_v -I2S_IRQHandler_v -FPU_IRQHandler_v - B . - ENDP - ALIGN - END diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S new file mode 100644 index 0000000..b27d189 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S @@ -0,0 +1,381 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + + + MODULE ?cstartup + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN nrf_reloc_vector_table + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMonitor_Handler + SECTION .text:CODE:NOROOT(1) +DebugMonitor_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:NOROOT(1) +RADIO_IRQHandler + B . + + PUBWEAK UARTE0_UART0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +UARTE0_UART0_IRQHandler_v + B . + + PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + B . + + PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + B . + + PUBWEAK NFCT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +NFCT_IRQHandler_v + B . + + PUBWEAK GPIOTE_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +GPIOTE_IRQHandler_v + B . + + PUBWEAK SAADC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SAADC_IRQHandler_v + B . + + PUBWEAK TIMER0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER0_IRQHandler_v + B . + + PUBWEAK TIMER1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER1_IRQHandler_v + B . + + PUBWEAK TIMER2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER2_IRQHandler_v + B . + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:NOROOT(1) +RTC0_IRQHandler + B . + + PUBWEAK TEMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TEMP_IRQHandler_v + B . + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT(1) +RNG_IRQHandler + B . + + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:NOROOT(1) +ECB_IRQHandler + B . + + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:NOROOT(1) +CCM_AAR_IRQHandler + B . + + PUBWEAK WDT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +WDT_IRQHandler_v + B . + + PUBWEAK RTC1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC1_IRQHandler_v + B . + + PUBWEAK QDEC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +QDEC_IRQHandler_v + B . + + PUBWEAK COMP_LPCOMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +COMP_LPCOMP_IRQHandler_v + B . + + PUBWEAK SWI0_EGU0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI0_EGU0_IRQHandler_v + B . + + PUBWEAK SWI1_EGU1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI1_EGU1_IRQHandler_v + B . + + PUBWEAK SWI2_EGU2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI2_EGU2_IRQHandler_v + B . + + PUBWEAK SWI3_EGU3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI3_EGU3_IRQHandler_v + B . + + PUBWEAK SWI4_EGU4_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI4_EGU4_IRQHandler + B . + + PUBWEAK SWI5_EGU5_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI5_EGU5_IRQHandler + B . + + PUBWEAK TIMER3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER3_IRQHandler_v + B . + + PUBWEAK TIMER4_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER4_IRQHandler_v + B . + + PUBWEAK PWM0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM0_IRQHandler_v + B . + + PUBWEAK PDM_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PDM_IRQHandler_v + B . + + PUBWEAK MWU_IRQHandler + SECTION .text:CODE:NOROOT(1) +MWU_IRQHandler + B . + + PUBWEAK PWM1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM1_IRQHandler_v + B . + + PUBWEAK PWM2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM2_IRQHandler_v + B . + + PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM2_SPIS2_SPI2_IRQHandler_v + B . + + PUBWEAK RTC2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC2_IRQHandler_v + B . + + PUBWEAK I2S_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +I2S_IRQHandler_v + B . + + PUBWEAK FPU_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +FPU_IRQHandler_v + B . + + + END + + diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s deleted file mode 100644 index b27d189..0000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s +++ /dev/null @@ -1,381 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. - - - - MODULE ?cstartup - - ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. - ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN nrf_reloc_vector_table - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemoryManagement_Handler - SECTION .text:CODE:NOROOT(1) -MemoryManagement_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMonitor_Handler - SECTION .text:CODE:NOROOT(1) -DebugMonitor_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT(1) -SysTick_Handler - B . - - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:NOROOT(1) -RADIO_IRQHandler - B . - - PUBWEAK UARTE0_UART0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -UARTE0_UART0_IRQHandler_v - B . - - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - B . - - PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - B . - - PUBWEAK NFCT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -NFCT_IRQHandler_v - B . - - PUBWEAK GPIOTE_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -GPIOTE_IRQHandler_v - B . - - PUBWEAK SAADC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SAADC_IRQHandler_v - B . - - PUBWEAK TIMER0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER0_IRQHandler_v - B . - - PUBWEAK TIMER1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER1_IRQHandler_v - B . - - PUBWEAK TIMER2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER2_IRQHandler_v - B . - - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:NOROOT(1) -RTC0_IRQHandler - B . - - PUBWEAK TEMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TEMP_IRQHandler_v - B . - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT(1) -RNG_IRQHandler - B . - - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:NOROOT(1) -ECB_IRQHandler - B . - - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:NOROOT(1) -CCM_AAR_IRQHandler - B . - - PUBWEAK WDT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -WDT_IRQHandler_v - B . - - PUBWEAK RTC1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC1_IRQHandler_v - B . - - PUBWEAK QDEC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -QDEC_IRQHandler_v - B . - - PUBWEAK COMP_LPCOMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -COMP_LPCOMP_IRQHandler_v - B . - - PUBWEAK SWI0_EGU0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI0_EGU0_IRQHandler_v - B . - - PUBWEAK SWI1_EGU1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI1_EGU1_IRQHandler_v - B . - - PUBWEAK SWI2_EGU2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI2_EGU2_IRQHandler_v - B . - - PUBWEAK SWI3_EGU3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI3_EGU3_IRQHandler_v - B . - - PUBWEAK SWI4_EGU4_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI4_EGU4_IRQHandler - B . - - PUBWEAK SWI5_EGU5_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI5_EGU5_IRQHandler - B . - - PUBWEAK TIMER3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER3_IRQHandler_v - B . - - PUBWEAK TIMER4_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER4_IRQHandler_v - B . - - PUBWEAK PWM0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM0_IRQHandler_v - B . - - PUBWEAK PDM_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PDM_IRQHandler_v - B . - - PUBWEAK MWU_IRQHandler - SECTION .text:CODE:NOROOT(1) -MWU_IRQHandler - B . - - PUBWEAK PWM1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM1_IRQHandler_v - B . - - PUBWEAK PWM2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM2_IRQHandler_v - B . - - PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM2_SPIS2_SPI2_IRQHandler_v - B . - - PUBWEAK RTC2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC2_IRQHandler_v - B . - - PUBWEAK I2S_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -I2S_IRQHandler_v - B . - - PUBWEAK FPU_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -FPU_IRQHandler_v - B . - - - END - - diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S new file mode 100644 index 0000000..253746c --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S @@ -0,0 +1,269 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + +__initial_sp EQU 0x20040000 + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + DCD USBD_IRQHandler_v + DCD UARTE1_IRQHandler_v + DCD QSPI_IRQHandler_v + DCD CRYPTOCELL_IRQHandler_v + DCD SPIM3_IRQHandler_v + DCD 0 ; Reserved + DCD PWM3_IRQHandler_v + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IMPORT nrf_reloc_vector_table + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMonitor_Handler\ + PROC + EXPORT DebugMonitor_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT POWER_CLOCK_IRQHandler [WEAK] + EXPORT RADIO_IRQHandler [WEAK] + EXPORT UARTE0_UART0_IRQHandler_v [WEAK] + EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] + EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] + EXPORT NFCT_IRQHandler_v [WEAK] + EXPORT GPIOTE_IRQHandler_v [WEAK] + EXPORT SAADC_IRQHandler_v [WEAK] + EXPORT TIMER0_IRQHandler_v [WEAK] + EXPORT TIMER1_IRQHandler_v [WEAK] + EXPORT TIMER2_IRQHandler_v [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler_v [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ECB_IRQHandler [WEAK] + EXPORT CCM_AAR_IRQHandler [WEAK] + EXPORT WDT_IRQHandler_v [WEAK] + EXPORT RTC1_IRQHandler_v [WEAK] + EXPORT QDEC_IRQHandler_v [WEAK] + EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] + EXPORT SWI0_EGU0_IRQHandler_v [WEAK] + EXPORT SWI1_EGU1_IRQHandler_v [WEAK] + EXPORT SWI2_EGU2_IRQHandler_v [WEAK] + EXPORT SWI3_EGU3_IRQHandler_v [WEAK] + EXPORT SWI4_EGU4_IRQHandler [WEAK] + EXPORT SWI5_EGU5_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler_v [WEAK] + EXPORT TIMER4_IRQHandler_v [WEAK] + EXPORT PWM0_IRQHandler_v [WEAK] + EXPORT PDM_IRQHandler_v [WEAK] + EXPORT MWU_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler_v [WEAK] + EXPORT PWM2_IRQHandler_v [WEAK] + EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] + EXPORT RTC2_IRQHandler_v [WEAK] + EXPORT I2S_IRQHandler_v [WEAK] + EXPORT FPU_IRQHandler_v [WEAK] + EXPORT USBD_IRQHandler_v [WEAK] + EXPORT UARTE1_IRQHandler_v [WEAK] + EXPORT QSPI_IRQHandler_v [WEAK] + EXPORT CRYPTOCELL_IRQHandler_v [WEAK] + EXPORT SPIM3_IRQHandler_v [WEAK] + EXPORT PWM3_IRQHandler_v [WEAK] + + + + +POWER_CLOCK_IRQHandler +RADIO_IRQHandler +UARTE0_UART0_IRQHandler_v +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v +NFCT_IRQHandler_v +GPIOTE_IRQHandler_v +SAADC_IRQHandler_v +TIMER0_IRQHandler_v +TIMER1_IRQHandler_v +TIMER2_IRQHandler_v +RTC0_IRQHandler +TEMP_IRQHandler_v +RNG_IRQHandler +ECB_IRQHandler +CCM_AAR_IRQHandler +WDT_IRQHandler_v +RTC1_IRQHandler_v +QDEC_IRQHandler_v +COMP_LPCOMP_IRQHandler_v +SWI0_EGU0_IRQHandler_v +SWI1_EGU1_IRQHandler_v +SWI2_EGU2_IRQHandler_v +SWI3_EGU3_IRQHandler_v +SWI4_EGU4_IRQHandler +SWI5_EGU5_IRQHandler +TIMER3_IRQHandler_v +TIMER4_IRQHandler_v +PWM0_IRQHandler_v +PDM_IRQHandler_v +MWU_IRQHandler +PWM1_IRQHandler_v +PWM2_IRQHandler_v +SPIM2_SPIS2_SPI2_IRQHandler_v +RTC2_IRQHandler_v +I2S_IRQHandler_v +FPU_IRQHandler_v +USBD_IRQHandler_v +UARTE1_IRQHandler_v +QSPI_IRQHandler_v +CRYPTOCELL_IRQHandler_v +SPIM3_IRQHandler_v +PWM3_IRQHandler_v + + B . + ENDP + ALIGN + END diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s deleted file mode 100644 index 253746c..0000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s +++ /dev/null @@ -1,269 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - -__initial_sp EQU 0x20040000 - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - DCD USBD_IRQHandler_v - DCD UARTE1_IRQHandler_v - DCD QSPI_IRQHandler_v - DCD CRYPTOCELL_IRQHandler_v - DCD SPIM3_IRQHandler_v - DCD 0 ; Reserved - DCD PWM3_IRQHandler_v - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT nrf_reloc_vector_table - - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemoryManagement_Handler\ - PROC - EXPORT MemoryManagement_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMonitor_Handler\ - PROC - EXPORT DebugMonitor_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UARTE0_UART0_IRQHandler_v [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] - EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] - EXPORT NFCT_IRQHandler_v [WEAK] - EXPORT GPIOTE_IRQHandler_v [WEAK] - EXPORT SAADC_IRQHandler_v [WEAK] - EXPORT TIMER0_IRQHandler_v [WEAK] - EXPORT TIMER1_IRQHandler_v [WEAK] - EXPORT TIMER2_IRQHandler_v [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler_v [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler_v [WEAK] - EXPORT RTC1_IRQHandler_v [WEAK] - EXPORT QDEC_IRQHandler_v [WEAK] - EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] - EXPORT SWI0_EGU0_IRQHandler_v [WEAK] - EXPORT SWI1_EGU1_IRQHandler_v [WEAK] - EXPORT SWI2_EGU2_IRQHandler_v [WEAK] - EXPORT SWI3_EGU3_IRQHandler_v [WEAK] - EXPORT SWI4_EGU4_IRQHandler [WEAK] - EXPORT SWI5_EGU5_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler_v [WEAK] - EXPORT TIMER4_IRQHandler_v [WEAK] - EXPORT PWM0_IRQHandler_v [WEAK] - EXPORT PDM_IRQHandler_v [WEAK] - EXPORT MWU_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler_v [WEAK] - EXPORT PWM2_IRQHandler_v [WEAK] - EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] - EXPORT RTC2_IRQHandler_v [WEAK] - EXPORT I2S_IRQHandler_v [WEAK] - EXPORT FPU_IRQHandler_v [WEAK] - EXPORT USBD_IRQHandler_v [WEAK] - EXPORT UARTE1_IRQHandler_v [WEAK] - EXPORT QSPI_IRQHandler_v [WEAK] - EXPORT CRYPTOCELL_IRQHandler_v [WEAK] - EXPORT SPIM3_IRQHandler_v [WEAK] - EXPORT PWM3_IRQHandler_v [WEAK] - - - - -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UARTE0_UART0_IRQHandler_v -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v -NFCT_IRQHandler_v -GPIOTE_IRQHandler_v -SAADC_IRQHandler_v -TIMER0_IRQHandler_v -TIMER1_IRQHandler_v -TIMER2_IRQHandler_v -RTC0_IRQHandler -TEMP_IRQHandler_v -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler_v -RTC1_IRQHandler_v -QDEC_IRQHandler_v -COMP_LPCOMP_IRQHandler_v -SWI0_EGU0_IRQHandler_v -SWI1_EGU1_IRQHandler_v -SWI2_EGU2_IRQHandler_v -SWI3_EGU3_IRQHandler_v -SWI4_EGU4_IRQHandler -SWI5_EGU5_IRQHandler -TIMER3_IRQHandler_v -TIMER4_IRQHandler_v -PWM0_IRQHandler_v -PDM_IRQHandler_v -MWU_IRQHandler -PWM1_IRQHandler_v -PWM2_IRQHandler_v -SPIM2_SPIS2_SPI2_IRQHandler_v -RTC2_IRQHandler_v -I2S_IRQHandler_v -FPU_IRQHandler_v -USBD_IRQHandler_v -UARTE1_IRQHandler_v -QSPI_IRQHandler_v -CRYPTOCELL_IRQHandler_v -SPIM3_IRQHandler_v -PWM3_IRQHandler_v - - B . - ENDP - ALIGN - END diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S new file mode 100644 index 0000000..26ba439 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S @@ -0,0 +1,417 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + + + MODULE ?cstartup + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN nrf_reloc_vector_table + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + DCD USBD_IRQHandler_v + DCD UARTE1_IRQHandler_v + DCD QSPI_IRQHandler_v + DCD CRYPTOCELL_IRQHandler_v + DCD SPIM3_IRQHandler_v + DCD 0 /*Reserved */ + DCD PWM3_IRQHandler_v + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMonitor_Handler + SECTION .text:CODE:NOROOT(1) +DebugMonitor_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:NOROOT(1) +RADIO_IRQHandler + B . + + PUBWEAK UARTE0_UART0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +UARTE0_UART0_IRQHandler_v + B . + + PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + B . + + PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + B . + + PUBWEAK NFCT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +NFCT_IRQHandler_v + B . + + PUBWEAK GPIOTE_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +GPIOTE_IRQHandler_v + B . + + PUBWEAK SAADC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SAADC_IRQHandler_v + B . + + PUBWEAK TIMER0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER0_IRQHandler_v + B . + + PUBWEAK TIMER1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER1_IRQHandler_v + B . + + PUBWEAK TIMER2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER2_IRQHandler_v + B . + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:NOROOT(1) +RTC0_IRQHandler + B . + + PUBWEAK TEMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TEMP_IRQHandler_v + B . + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT(1) +RNG_IRQHandler + B . + + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:NOROOT(1) +ECB_IRQHandler + B . + + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:NOROOT(1) +CCM_AAR_IRQHandler + B . + + PUBWEAK WDT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +WDT_IRQHandler_v + B . + + PUBWEAK RTC1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC1_IRQHandler_v + B . + + PUBWEAK QDEC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +QDEC_IRQHandler_v + B . + + PUBWEAK COMP_LPCOMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +COMP_LPCOMP_IRQHandler_v + B . + + PUBWEAK SWI0_EGU0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI0_EGU0_IRQHandler_v + B . + + PUBWEAK SWI1_EGU1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI1_EGU1_IRQHandler_v + B . + + PUBWEAK SWI2_EGU2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI2_EGU2_IRQHandler_v + B . + + PUBWEAK SWI3_EGU3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI3_EGU3_IRQHandler_v + B . + + PUBWEAK SWI4_EGU4_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI4_EGU4_IRQHandler + B . + + PUBWEAK SWI5_EGU5_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI5_EGU5_IRQHandler + B . + + PUBWEAK TIMER3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER3_IRQHandler_v + B . + + PUBWEAK TIMER4_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER4_IRQHandler_v + B . + + PUBWEAK PWM0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM0_IRQHandler_v + B . + + PUBWEAK PDM_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PDM_IRQHandler_v + B . + + PUBWEAK MWU_IRQHandler + SECTION .text:CODE:NOROOT(1) +MWU_IRQHandler + B . + + PUBWEAK PWM1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM1_IRQHandler_v + B . + + PUBWEAK PWM2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM2_IRQHandler_v + B . + + PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM2_SPIS2_SPI2_IRQHandler_v + B . + + PUBWEAK RTC2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC2_IRQHandler_v + B . + + PUBWEAK I2S_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +I2S_IRQHandler_v + B . + + PUBWEAK FPU_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +FPU_IRQHandler_v + B . + + PUBWEAK USBD_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +USBD_IRQHandler_v + B . + + PUBWEAK UARTE1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +UARTE1_IRQHandler_v + B . + + PUBWEAK QSPI_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +QSPI_IRQHandler_v + B . + + PUBWEAK CRYPTOCELL_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +CRYPTOCELL_IRQHandler_v + B . + + PUBWEAK SPIM3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM3_IRQHandler_v + B . + + PUBWEAK PWM3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM3_IRQHandler_v + B . + + + END + + diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s deleted file mode 100644 index 26ba439..0000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s +++ /dev/null @@ -1,417 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. - - - - MODULE ?cstartup - - ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. - ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN nrf_reloc_vector_table - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - DCD USBD_IRQHandler_v - DCD UARTE1_IRQHandler_v - DCD QSPI_IRQHandler_v - DCD CRYPTOCELL_IRQHandler_v - DCD SPIM3_IRQHandler_v - DCD 0 /*Reserved */ - DCD PWM3_IRQHandler_v - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemoryManagement_Handler - SECTION .text:CODE:NOROOT(1) -MemoryManagement_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMonitor_Handler - SECTION .text:CODE:NOROOT(1) -DebugMonitor_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT(1) -SysTick_Handler - B . - - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:NOROOT(1) -RADIO_IRQHandler - B . - - PUBWEAK UARTE0_UART0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -UARTE0_UART0_IRQHandler_v - B . - - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - B . - - PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - B . - - PUBWEAK NFCT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -NFCT_IRQHandler_v - B . - - PUBWEAK GPIOTE_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -GPIOTE_IRQHandler_v - B . - - PUBWEAK SAADC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SAADC_IRQHandler_v - B . - - PUBWEAK TIMER0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER0_IRQHandler_v - B . - - PUBWEAK TIMER1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER1_IRQHandler_v - B . - - PUBWEAK TIMER2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER2_IRQHandler_v - B . - - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:NOROOT(1) -RTC0_IRQHandler - B . - - PUBWEAK TEMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TEMP_IRQHandler_v - B . - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT(1) -RNG_IRQHandler - B . - - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:NOROOT(1) -ECB_IRQHandler - B . - - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:NOROOT(1) -CCM_AAR_IRQHandler - B . - - PUBWEAK WDT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -WDT_IRQHandler_v - B . - - PUBWEAK RTC1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC1_IRQHandler_v - B . - - PUBWEAK QDEC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -QDEC_IRQHandler_v - B . - - PUBWEAK COMP_LPCOMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -COMP_LPCOMP_IRQHandler_v - B . - - PUBWEAK SWI0_EGU0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI0_EGU0_IRQHandler_v - B . - - PUBWEAK SWI1_EGU1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI1_EGU1_IRQHandler_v - B . - - PUBWEAK SWI2_EGU2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI2_EGU2_IRQHandler_v - B . - - PUBWEAK SWI3_EGU3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI3_EGU3_IRQHandler_v - B . - - PUBWEAK SWI4_EGU4_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI4_EGU4_IRQHandler - B . - - PUBWEAK SWI5_EGU5_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI5_EGU5_IRQHandler - B . - - PUBWEAK TIMER3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER3_IRQHandler_v - B . - - PUBWEAK TIMER4_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER4_IRQHandler_v - B . - - PUBWEAK PWM0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM0_IRQHandler_v - B . - - PUBWEAK PDM_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PDM_IRQHandler_v - B . - - PUBWEAK MWU_IRQHandler - SECTION .text:CODE:NOROOT(1) -MWU_IRQHandler - B . - - PUBWEAK PWM1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM1_IRQHandler_v - B . - - PUBWEAK PWM2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM2_IRQHandler_v - B . - - PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM2_SPIS2_SPI2_IRQHandler_v - B . - - PUBWEAK RTC2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC2_IRQHandler_v - B . - - PUBWEAK I2S_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -I2S_IRQHandler_v - B . - - PUBWEAK FPU_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -FPU_IRQHandler_v - B . - - PUBWEAK USBD_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -USBD_IRQHandler_v - B . - - PUBWEAK UARTE1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -UARTE1_IRQHandler_v - B . - - PUBWEAK QSPI_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -QSPI_IRQHandler_v - B . - - PUBWEAK CRYPTOCELL_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -CRYPTOCELL_IRQHandler_v - B . - - PUBWEAK SPIM3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM3_IRQHandler_v - B . - - PUBWEAK PWM3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM3_IRQHandler_v - B . - - - END - - diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S new file mode 100644 index 0000000..c711ca5 --- /dev/null +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S @@ -0,0 +1,208 @@ +;/* File: startup_ncs36510.s +; * Purpose: startup file for Cortex-M3 devices. Should use with +; * ARMGCC for ARM Embedded Processors +; * Version: V2.00 +; * Date: 25 Feb 2016 +; * +; */ +;/* Copyright (c) 2011 - 2014 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0x3000 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_HEAP$$ZI$$Limit| ; Top of RAM + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD fIrqTim0Handler + DCD fIrqTim1Handler + DCD fIrqTim2Handler + DCD fIrqUart1Handler + DCD fIrqSpiHandler + DCD fIrqI2CHandler + DCD fIrqGpioHandler + DCD fIrqRtcHandler + DCD fIrqFlashHandler + DCD fIrqMacHwHandler + DCD fIrqAesHandler + DCD fIrqAdcHandler + DCD fIrqClockCalHandler + DCD fIrqUart2Handler + DCD fIrqUviHandler + DCD fIrqDmaHandler + DCD fIrqDbgPwrUpHandler + DCD fIrqSpi2Handler + DCD fIrqI2C2Handler + DCD fIrqFVDDHCompHandler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT fIrqTim0Handler [WEAK] + EXPORT fIrqTim1Handler [WEAK] + EXPORT fIrqTim2Handler [WEAK] + EXPORT fIrqUart1Handler [WEAK] + EXPORT fIrqSpiHandler [WEAK] + EXPORT fIrqI2CHandler [WEAK] + EXPORT fIrqGpioHandler [WEAK] + EXPORT fIrqRtcHandler [WEAK] + EXPORT fIrqFlashHandler [WEAK] + EXPORT fIrqMacHwHandler [WEAK] + EXPORT fIrqAesHandler [WEAK] + EXPORT fIrqAdcHandler [WEAK] + EXPORT fIrqClockCalHandler [WEAK] + EXPORT fIrqUart2Handler [WEAK] + EXPORT fIrqUviHandler [WEAK] + EXPORT fIrqDmaHandler [WEAK] + EXPORT fIrqDbgPwrUpHandler [WEAK] + EXPORT fIrqSpi2Handler [WEAK] + EXPORT fIrqI2C2Handler [WEAK] + EXPORT fIrqFVDDHCompHandler [WEAK] + +fIrqTim0Handler +fIrqTim1Handler +fIrqTim2Handler +fIrqUart1Handler +fIrqSpiHandler +fIrqI2CHandler +fIrqGpioHandler +fIrqRtcHandler +fIrqFlashHandler +fIrqMacHwHandler +fIrqAesHandler +fIrqAdcHandler +fIrqClockCalHandler +fIrqUart2Handler +fIrqUviHandler +fIrqDmaHandler +fIrqDbgPwrUpHandler +fIrqSpi2Handler +fIrqI2C2Handler +fIrqFVDDHCompHandler +DefaultISR + + B . + + ENDP + + EXPORT __user_initial_stackheap + IMPORT |Image$$ARM_LIB_HEAP$$Base| + IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| + +__user_initial_stackheap PROC + LDR R0, = |Image$$ARM_LIB_HEAP$$Base| + LDR R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit| + BX LR + ENDP + + ALIGN + END diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s deleted file mode 100644 index c711ca5..0000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s +++ /dev/null @@ -1,208 +0,0 @@ -;/* File: startup_ncs36510.s -; * Purpose: startup file for Cortex-M3 devices. Should use with -; * ARMGCC for ARM Embedded Processors -; * Version: V2.00 -; * Date: 25 Feb 2016 -; * -; */ -;/* Copyright (c) 2011 - 2014 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0x3000 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_HEAP$$ZI$$Limit| ; Top of RAM - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD fIrqTim0Handler - DCD fIrqTim1Handler - DCD fIrqTim2Handler - DCD fIrqUart1Handler - DCD fIrqSpiHandler - DCD fIrqI2CHandler - DCD fIrqGpioHandler - DCD fIrqRtcHandler - DCD fIrqFlashHandler - DCD fIrqMacHwHandler - DCD fIrqAesHandler - DCD fIrqAdcHandler - DCD fIrqClockCalHandler - DCD fIrqUart2Handler - DCD fIrqUviHandler - DCD fIrqDmaHandler - DCD fIrqDbgPwrUpHandler - DCD fIrqSpi2Handler - DCD fIrqI2C2Handler - DCD fIrqFVDDHCompHandler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT fIrqTim0Handler [WEAK] - EXPORT fIrqTim1Handler [WEAK] - EXPORT fIrqTim2Handler [WEAK] - EXPORT fIrqUart1Handler [WEAK] - EXPORT fIrqSpiHandler [WEAK] - EXPORT fIrqI2CHandler [WEAK] - EXPORT fIrqGpioHandler [WEAK] - EXPORT fIrqRtcHandler [WEAK] - EXPORT fIrqFlashHandler [WEAK] - EXPORT fIrqMacHwHandler [WEAK] - EXPORT fIrqAesHandler [WEAK] - EXPORT fIrqAdcHandler [WEAK] - EXPORT fIrqClockCalHandler [WEAK] - EXPORT fIrqUart2Handler [WEAK] - EXPORT fIrqUviHandler [WEAK] - EXPORT fIrqDmaHandler [WEAK] - EXPORT fIrqDbgPwrUpHandler [WEAK] - EXPORT fIrqSpi2Handler [WEAK] - EXPORT fIrqI2C2Handler [WEAK] - EXPORT fIrqFVDDHCompHandler [WEAK] - -fIrqTim0Handler -fIrqTim1Handler -fIrqTim2Handler -fIrqUart1Handler -fIrqSpiHandler -fIrqI2CHandler -fIrqGpioHandler -fIrqRtcHandler -fIrqFlashHandler -fIrqMacHwHandler -fIrqAesHandler -fIrqAdcHandler -fIrqClockCalHandler -fIrqUart2Handler -fIrqUviHandler -fIrqDmaHandler -fIrqDbgPwrUpHandler -fIrqSpi2Handler -fIrqI2C2Handler -fIrqFVDDHCompHandler -DefaultISR - - B . - - ENDP - - EXPORT __user_initial_stackheap - IMPORT |Image$$ARM_LIB_HEAP$$Base| - IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| - -__user_initial_stackheap PROC - LDR R0, = |Image$$ARM_LIB_HEAP$$Base| - LDR R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit| - BX LR - ENDP - - ALIGN - END diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S new file mode 100644 index 0000000..4ecaeb5 --- /dev/null +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S @@ -0,0 +1,214 @@ +/* File: startup_ncs36510.S + * Purpose: startup file for Cortex-M3 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.00 + * Date: 15 Jan 2016 + * + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0x400 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.space Heap_Size +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + +.section .vector_table,"a",%progbits +.align 2 +.globl __Vectors +__Vectors: +.long __StackTop /* Top of Stack */ +.long Reset_Handler /* Reset Handler */ +.long NMI_Handler /* NMI Handler */ +.long HardFault_Handler /* Hard Fault Handler */ +.long MemManage_Handler /* MPU Fault Handler */ +.long BusFault_Handler /* Bus Fault Handler */ +.long UsageFault_Handler /* Usage Fault Handler */ +.long 0 /* Reserved */ +.long 0 /* Reserved */ +.long 0 /* Reserved */ +.long 0 /* Reserved */ +.long SVC_Handler /* SVCall Handler */ +.long DebugMon_Handler /* Debug Monitor Handler */ +.long 0 /* Reserved */ +.long PendSV_Handler /* PendSV Handler */ +.long SysTick_Handler /* SysTick Handler */ + +/* External Interrupts */ +.long fIrqTim0Handler +.long fIrqTim1Handler +.long fIrqTim2Handler +.long fIrqUart1Handler +.long fIrqSpiHandler +.long fIrqI2CHandler +.long fIrqGpioHandler +.long fIrqRtcHandler +.long fIrqFlashHandler +.long fIrqMacHwHandler +.long fIrqAesHandler +.long fIrqAdcHandler +.long fIrqClockCalHandler +.long fIrqUart2Handler +.long fIrqUviHandler +.long fIrqDmaHandler +.long fIrqDbgPwrUpHandler +.long fIrqSpi2Handler +.long fIrqI2C2Handler +.long fIrqFVDDHCompHandler + +.size __Vectors, . - __Vectors + +.section .text.Reset_Handler +.thumb +.thumb_func +.align 2 +.globl Reset_Handler +.type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges +* of copy from/to are specified by following symbols evaluated in +* linker script. +* __etext: End of code section, i.e., begin of data sections to copy from. +* __data_start__/__data_end__: RAM address range that data should be +* copied to. Both must be aligned to 4 bytes boundary. */ + +disable_watchdog: +/*MPL - Need to implement?! */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 +/* TODO - Uncomment when uvisor support is added */ +/* + ldr r0, =uvisor_init + blx r0 +*/ + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler +* will be weak symbol and just dead loops. They can be +* overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + +/* IRQ Handlers */ + def_irq_default_handler fIrqTim0Handler + def_irq_default_handler fIrqTim1Handler + def_irq_default_handler fIrqTim2Handler + def_irq_default_handler fIrqUart1Handler + def_irq_default_handler fIrqSpiHandler + def_irq_default_handler fIrqI2CHandler + def_irq_default_handler fIrqGpioHandler + def_irq_default_handler fIrqRtcHandler + def_irq_default_handler fIrqFlashHandler + def_irq_default_handler fIrqMacHwHandler + def_irq_default_handler fIrqAesHandler + def_irq_default_handler fIrqAdcHandler + def_irq_default_handler fIrqClockCalHandler + def_irq_default_handler fIrqUart2Handler + def_irq_default_handler fIrqUviHandler + def_irq_default_handler fIrqDmaHandler + def_irq_default_handler fIrqDbgPwrUpHandler + def_irq_default_handler fIrqSpi2Handler + def_irq_default_handler fIrqI2C2Handler + def_irq_default_handler fIrqFVDDHCompHandler + def_irq_default_handler DefaultISR + + .end diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s deleted file mode 100644 index 4ecaeb5..0000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s +++ /dev/null @@ -1,214 +0,0 @@ -/* File: startup_ncs36510.S - * Purpose: startup file for Cortex-M3 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V2.00 - * Date: 15 Jan 2016 - * - */ -/* Copyright (c) 2011 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0x400 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.space Heap_Size -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - -.section .vector_table,"a",%progbits -.align 2 -.globl __Vectors -__Vectors: -.long __StackTop /* Top of Stack */ -.long Reset_Handler /* Reset Handler */ -.long NMI_Handler /* NMI Handler */ -.long HardFault_Handler /* Hard Fault Handler */ -.long MemManage_Handler /* MPU Fault Handler */ -.long BusFault_Handler /* Bus Fault Handler */ -.long UsageFault_Handler /* Usage Fault Handler */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long SVC_Handler /* SVCall Handler */ -.long DebugMon_Handler /* Debug Monitor Handler */ -.long 0 /* Reserved */ -.long PendSV_Handler /* PendSV Handler */ -.long SysTick_Handler /* SysTick Handler */ - -/* External Interrupts */ -.long fIrqTim0Handler -.long fIrqTim1Handler -.long fIrqTim2Handler -.long fIrqUart1Handler -.long fIrqSpiHandler -.long fIrqI2CHandler -.long fIrqGpioHandler -.long fIrqRtcHandler -.long fIrqFlashHandler -.long fIrqMacHwHandler -.long fIrqAesHandler -.long fIrqAdcHandler -.long fIrqClockCalHandler -.long fIrqUart2Handler -.long fIrqUviHandler -.long fIrqDmaHandler -.long fIrqDbgPwrUpHandler -.long fIrqSpi2Handler -.long fIrqI2C2Handler -.long fIrqFVDDHCompHandler - -.size __Vectors, . - __Vectors - -.section .text.Reset_Handler -.thumb -.thumb_func -.align 2 -.globl Reset_Handler -.type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges -* of copy from/to are specified by following symbols evaluated in -* linker script. -* __etext: End of code section, i.e., begin of data sections to copy from. -* __data_start__/__data_end__: RAM address range that data should be -* copied to. Both must be aligned to 4 bytes boundary. */ - -disable_watchdog: -/*MPL - Need to implement?! */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 -/* TODO - Uncomment when uvisor support is added */ -/* - ldr r0, =uvisor_init - blx r0 -*/ - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler -* will be weak symbol and just dead loops. They can be -* overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - -/* IRQ Handlers */ - def_irq_default_handler fIrqTim0Handler - def_irq_default_handler fIrqTim1Handler - def_irq_default_handler fIrqTim2Handler - def_irq_default_handler fIrqUart1Handler - def_irq_default_handler fIrqSpiHandler - def_irq_default_handler fIrqI2CHandler - def_irq_default_handler fIrqGpioHandler - def_irq_default_handler fIrqRtcHandler - def_irq_default_handler fIrqFlashHandler - def_irq_default_handler fIrqMacHwHandler - def_irq_default_handler fIrqAesHandler - def_irq_default_handler fIrqAdcHandler - def_irq_default_handler fIrqClockCalHandler - def_irq_default_handler fIrqUart2Handler - def_irq_default_handler fIrqUviHandler - def_irq_default_handler fIrqDmaHandler - def_irq_default_handler fIrqDbgPwrUpHandler - def_irq_default_handler fIrqSpi2Handler - def_irq_default_handler fIrqI2C2Handler - def_irq_default_handler fIrqFVDDHCompHandler - def_irq_default_handler DefaultISR - - .end diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S new file mode 100644 index 0000000..e3a7ab0 --- /dev/null +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S @@ -0,0 +1,310 @@ +;/****************************************************************************** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM3 Device Series +; * @version V1.05 +; * @date 25. July 2011 +; * +; * @note +; * Copyright (C) 2010-2011 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN fInitSource + EXTERN HardFault_Handler + EXTERN SVC_Handler + EXTERN PendSV_Handler + EXTERN SysTick_Handler + EXTERN fIrqTim0Handler + EXTERN fIrqTim1Handler + EXTERN fIrqTim2Handler + EXTERN fIrqGpioHandler + EXTERN fIrqSpiHandler + EXTERN fIrqUart1Handler + EXTERN fIrqUart2Handler + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler +#ifndef RAM_VECTOR_TABLE + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +#endif +__vector_table_0x1c +#ifndef RAM_VECTOR_TABLE + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD fIrqTim0Handler + DCD fIrqTim1Handler + DCD fIrqTim2Handler + DCD fIrqUart1Handler + DCD fIrqSpiHandler + DCD fIrqI2CHandler + DCD fIrqGpioHandler + DCD fIrqRtcHandler + DCD fIrqFlashHandler + DCD fIrqMacHwHandler + DCD fIrqAesHandler + DCD fIrqAdcHandler + DCD fIrqClockCalHandler + DCD fIrqUart2Handler + DCD fIrqUviHandler + DCD fIrqDmaHandler + DCD fIrqDbgPwrUpHandler + /* REV C/D interrupts */ + DCD fIrqSpi2Handler + DCD fIrqI2c2Handler + DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */ +#endif +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +opt: DC32 0x2082353F /* Full featured device */ +opt_reg: DC32 0x4001E000 +enable: DC32 0x00000000 +per_en: DC32 0x4001B010 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + +;; Taken from article http://netstorage.iar.com/SuppDB/Public/UPDINFO/007040/arm/doc/infocenter/ilinkarm.ENU.html +;; If this line is removed, veneers for functions copied into RAM are flasely also placed in RAM, but are NOT +;; copied into it by __iar_copy_init3 +__iar_init$$done + + PUBLIC Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0,= enable ;; load R0 with address of enable + LDR R0,[R0] ;; load R0 with what address R0 points to + LDR R1,= per_en ;; load R1 with address of per_en + LDR R1,[R1] ;; load R1 with what address R1 points to + STR R0,[R1] ;; store R0 into address pointed to by R1 /* Disable all peripherals */ + + LDR R0,= opt ;; load R0 with address of opt + LDR R0,[R0] ;; load R0 with what address R0 points to + LDR R1,= opt_reg ;; load R1 with address of opt_reg + LDR R1,[R1] ;; load R1 with what address R1 points to + STR R0, [R1] ;; store R0 into address pointed to by R1 /* Device option: Full featured device */ + + LDR R0,= sfe(CSTACK) + MOV SP,R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + +; PUBWEAK HardFault_Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;HardFault_Handler +; B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + +; PUBWEAK vPortSVCHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;vPortSVCHandler +; B vPortSVCHandler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + +; PUBWEAK xPortPendSVHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;xPortPendSVHandler +; B xPortPendSVHandler + +; PUBWEAK SysTick_Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;SysTick_Handler +; B SysTick_Handler + + +; PUBWEAK fIrqTim0Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqTim0Handler +; B fIrqTim0Handler + +; PUBWEAK fIrqTim1Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqTim1Handler +; B fIrqTim1Handler + +; PUBWEAK fIrqTim2Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqTim2Handler +; B fIrqTim2Handler + +; PUBWEAK fIrqUart1Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqUart1Handler +; B fIrqUart1Handler + +; PUBWEAK fIrqSpiHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqSpiHandler +; B fIrqSpiHandler + + PUBWEAK fIrqI2CHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqI2CHandler + B fIrqI2CHandler + +; PUBWEAK fIrqGpioHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqGpioHandler +; B fIrqGpioHandler + + PUBWEAK fIrqRtcHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqRtcHandler + B fIrqRtcHandler + + PUBWEAK fIrqFlashHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqFlashHandler + B fIrqFlashHandler + + PUBWEAK fIrqMacHwHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqMacHwHandler + B fIrqMacHwHandler + + PUBWEAK fIrqAesHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqAesHandler + B fIrqAesHandler + + PUBWEAK fIrqAdcHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqAdcHandler + B fIrqAdcHandler + + PUBWEAK fIrqClockCalHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqClockCalHandler + B fIrqClockCalHandler + +; PUBWEAK fIrqUart2Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqUart2Handler +; B fIrqUart2Handler + + PUBWEAK fIrqDbgPwrUpHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqDbgPwrUpHandler + B fIrqDbgPwrUpHandler + + PUBWEAK fIrqDmaHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqDmaHandler + B fIrqDmaHandler + + PUBWEAK fIrqUviHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqUviHandler + B fIrqUviHandler + + PUBWEAK fIrqSpi2Handler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqSpi2Handler + B fIrqSpi2Handler + + PUBWEAK fIrqI2c2Handler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqI2c2Handler + B fIrqI2c2Handler + + PUBWEAK FIrqFVDDHCompHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FIrqFVDDHCompHandler + B FIrqFVDDHCompHandler + + PUBWEAK DEF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DEF_IRQHandler + B DEF_IRQHandler + + END diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s deleted file mode 100644 index e3a7ab0..0000000 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s +++ /dev/null @@ -1,310 +0,0 @@ -;/****************************************************************************** -; * @file startup_ARMCM3.s -; * @brief CMSIS Cortex-M4 Core Device Startup File -; * for CM3 Device Series -; * @version V1.05 -; * @date 25. July 2011 -; * -; * @note -; * Copyright (C) 2010-2011 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN fInitSource - EXTERN HardFault_Handler - EXTERN SVC_Handler - EXTERN PendSV_Handler - EXTERN SysTick_Handler - EXTERN fIrqTim0Handler - EXTERN fIrqTim1Handler - EXTERN fIrqTim2Handler - EXTERN fIrqGpioHandler - EXTERN fIrqSpiHandler - EXTERN fIrqUart1Handler - EXTERN fIrqUart2Handler - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler -#ifndef RAM_VECTOR_TABLE - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -#endif -__vector_table_0x1c -#ifndef RAM_VECTOR_TABLE - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD fIrqTim0Handler - DCD fIrqTim1Handler - DCD fIrqTim2Handler - DCD fIrqUart1Handler - DCD fIrqSpiHandler - DCD fIrqI2CHandler - DCD fIrqGpioHandler - DCD fIrqRtcHandler - DCD fIrqFlashHandler - DCD fIrqMacHwHandler - DCD fIrqAesHandler - DCD fIrqAdcHandler - DCD fIrqClockCalHandler - DCD fIrqUart2Handler - DCD fIrqUviHandler - DCD fIrqDmaHandler - DCD fIrqDbgPwrUpHandler - /* REV C/D interrupts */ - DCD fIrqSpi2Handler - DCD fIrqI2c2Handler - DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */ -#endif -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -opt: DC32 0x2082353F /* Full featured device */ -opt_reg: DC32 0x4001E000 -enable: DC32 0x00000000 -per_en: DC32 0x4001B010 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - -;; Taken from article http://netstorage.iar.com/SuppDB/Public/UPDINFO/007040/arm/doc/infocenter/ilinkarm.ENU.html -;; If this line is removed, veneers for functions copied into RAM are flasely also placed in RAM, but are NOT -;; copied into it by __iar_copy_init3 -__iar_init$$done - - PUBLIC Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0,= enable ;; load R0 with address of enable - LDR R0,[R0] ;; load R0 with what address R0 points to - LDR R1,= per_en ;; load R1 with address of per_en - LDR R1,[R1] ;; load R1 with what address R1 points to - STR R0,[R1] ;; store R0 into address pointed to by R1 /* Disable all peripherals */ - - LDR R0,= opt ;; load R0 with address of opt - LDR R0,[R0] ;; load R0 with what address R0 points to - LDR R1,= opt_reg ;; load R1 with address of opt_reg - LDR R1,[R1] ;; load R1 with what address R1 points to - STR R0, [R1] ;; store R0 into address pointed to by R1 /* Device option: Full featured device */ - - LDR R0,= sfe(CSTACK) - MOV SP,R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - -; PUBWEAK HardFault_Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;HardFault_Handler -; B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - -; PUBWEAK vPortSVCHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;vPortSVCHandler -; B vPortSVCHandler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - -; PUBWEAK xPortPendSVHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;xPortPendSVHandler -; B xPortPendSVHandler - -; PUBWEAK SysTick_Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;SysTick_Handler -; B SysTick_Handler - - -; PUBWEAK fIrqTim0Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim0Handler -; B fIrqTim0Handler - -; PUBWEAK fIrqTim1Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim1Handler -; B fIrqTim1Handler - -; PUBWEAK fIrqTim2Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim2Handler -; B fIrqTim2Handler - -; PUBWEAK fIrqUart1Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqUart1Handler -; B fIrqUart1Handler - -; PUBWEAK fIrqSpiHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqSpiHandler -; B fIrqSpiHandler - - PUBWEAK fIrqI2CHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqI2CHandler - B fIrqI2CHandler - -; PUBWEAK fIrqGpioHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqGpioHandler -; B fIrqGpioHandler - - PUBWEAK fIrqRtcHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqRtcHandler - B fIrqRtcHandler - - PUBWEAK fIrqFlashHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqFlashHandler - B fIrqFlashHandler - - PUBWEAK fIrqMacHwHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqMacHwHandler - B fIrqMacHwHandler - - PUBWEAK fIrqAesHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqAesHandler - B fIrqAesHandler - - PUBWEAK fIrqAdcHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqAdcHandler - B fIrqAdcHandler - - PUBWEAK fIrqClockCalHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqClockCalHandler - B fIrqClockCalHandler - -; PUBWEAK fIrqUart2Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqUart2Handler -; B fIrqUart2Handler - - PUBWEAK fIrqDbgPwrUpHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqDbgPwrUpHandler - B fIrqDbgPwrUpHandler - - PUBWEAK fIrqDmaHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqDmaHandler - B fIrqDmaHandler - - PUBWEAK fIrqUviHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqUviHandler - B fIrqUviHandler - - PUBWEAK fIrqSpi2Handler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqSpi2Handler - B fIrqSpi2Handler - - PUBWEAK fIrqI2c2Handler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqI2c2Handler - B fIrqI2c2Handler - - PUBWEAK FIrqFVDDHCompHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FIrqFVDDHCompHandler - B FIrqFVDDHCompHandler - - PUBWEAK DEF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DEF_IRQHandler - B DEF_IRQHandler - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S new file mode 100644 index 0000000..fb769e5 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.S @@ -0,0 +1,505 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 49919 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector_core_a9 + PUBLIC __RST_Handler + PUBLIC Undefined_Handler + EXTERN SWI_Handler + PUBLIC Prefetch_Handler + PUBLIC Abort_Handler + PUBLIC IRQ_Handler + PUBLIC FIQ_Handler + EXTERN VbarInit + EXTERN SetLowVectors + EXTERN init_TTB + EXTERN enable_mmu + EXTERN Peripheral_BasicInit + EXTERN initsct + EXTERN PowerON_Reset + PUBLIC FPUEnable + + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_core_a9: ; Make this a DATA label, so that stack usage + ; analysis doesn't consider it an uncalled fun + + ARM + + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + + DATA + +Reset_Addr: DCD __RST_Handler +Undefined_Addr: DCD Undefined_Handler +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD Prefetch_Handler +Abort_Addr: DCD Abort_Handler +IRQ_Addr: DCD IRQ_Handler +FIQ_Addr: DCD FIQ_Handler + + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reset execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + EXTERN RZ_A1_SetSramWriteEnable + EXTERN create_translation_table + EXTERN SystemInit + EXTERN InitMemorySubsystem + EXTERN __iar_program_start + REQUIRE __vector_core_a9 + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + + + ARM + +__RST_Handler: +?cstartup: + + +;;; @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR + ands r0, r0, #3 + +goToSleep: + wfine + bne goToSleep + + +//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +//@ Enables Full Access i.e. in both privileged and non privileged modes + mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) + orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 + mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) + isb + + +;; Switch on the VFP and NEON hardware + mov r0, #0x40000000 + vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set + + mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register + isb + + +;; Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__vector_core_a9 + mcr p15, 0, r0, c12, c0, 0 + + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR + +#define USR_MODE 0x10 ; User mode +#define FIQ_MODE 0x11 ; Fast Interrupt Request mode +#define IRQ_MODE 0x12 ; Interrupt Request mode +#define SVC_MODE 0x13 ; Supervisor mode +#define ABT_MODE 0x17 ; Abort mode +#define UND_MODE 0x1B ; Undefined Instruction mode +#define SYS_MODE 0x1F ; System mode + +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define GICI_BASE 0xe8202000 +#define ICCIAR_OFFSET 0x0000000C +#define ICCEOIR_OFFSET 0x00000010 +#define ICCHPIR_OFFSET 0x00000018 +#define GICD_BASE 0xe8201000 +#define GIC_ERRATA_CHECK_1 0x000003FE +#define GIC_ERRATA_CHECK_2 0x000003FF +#define ICDABR0_OFFSET 0x00000300 +#define ICDIPR0_OFFSET 0x00000400 +#define T_Bit 0x20 ; when T bit is set, core is in Thumb state + + MRS r0, cpsr ; Original PSR value + + ;; Set up the SVC stack pointer. + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the ABT stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #ABT_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the UDF stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #UND_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + +;;; + + isb + ldr r0, =RZ_A1_SetSramWriteEnable + blx r0 + + bl create_translation_table + +; USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + ldr r0, =InitMemorySubsystem + blx r0 + +; fp_init + mov r0, #0x3000000 + vmsr fpscr, r0 + + + +;;; Continue to __cmain for C-level initialization. + + FUNCALL __RST_Handler, __iar_program_start + B __iar_program_start + + + ldr r0, sf_boot ;@ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + DC32 0x00000001 + +Undefined_Handler: + EXTERN CUndefHandler + SRSDB SP!, #Mode_UND + PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ + + MRS R0, SPSR + TST R0, #T_Bit /* Check mode */ + MOVEQ R1, #4 /* R1 = 4 ARM mode */ + MOVNE R1, #2 /* R1 = 2 Thumb mode */ + SUB R0, LR, R1 + LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ + BEQ undef_cont + + /* Thumb instruction */ + /* Determine if it is a 32-bit Thumb instruction */ + LDRH R0, [R0] + MOV R2, #0x1c + CMP R2, R0, LSR #11 + BHS undef_cont /* 16-bit Thumb instruction */ + + /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +undef_cont: + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + /* R0 Offending instruction */ + /* R1 =2 (Thumb) or =4 (ARM) */ + BL CUndefHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ + SUB LR, LR, R0 + LDR R0, [SP, #28] /* Restore stacked SPSR */ + MSR SPSR_cxsf, R0 + POP {R0-R4, R12} /* Restore stacked APCS registers */ + ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ + MOVS PC, LR + +Prefetch_Handler: + EXTERN CPAbtHandler + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + MRC p15, 0, R0, c5, c0, 1 /* IFSR */ + MRC p15, 0, R1, c6, c0, 2 /* IFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CPAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stack APCS registers */ + RFEFD SP! /* Return from exception */ + +Abort_Handler: + EXTERN CDAbtHandler + SUB LR, LR, #8 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + CLREX /* State of exclusive monitors unknown after taken data abort */ + MRC p15, 0, R0, c5, c0, 0 /* DFSR */ + MRC p15, 0, R1, c6, c0, 0 /* DFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CDAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ + +FIQ_Handler: + /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, + * so if a real FIQ Handler is implemented, this will be needed before returning: + */ + /* LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + */ + B . + + EXTERN SVC_Handler /* refer RTX function */ + +IRQ_Handler: + EXTERN IRQCount + EXTERN IRQTable + EXTERN IRQNestLevel + + /* prologue */ + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ + CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ + PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ + +/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R1, R3, #4 + SUB SP, SP, R1 /* Adjust stack */ + PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + ADD R1, R1, #1 /* Increment nesting counter */ + STR R1, [R0] + + /* identify and acknowledge interrupt */ + LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ + LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ + DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ + + /* Workaround GIC 390 errata 733075 + * If the ID is not 0, then service the interrupt as normal. + * If the ID is 0 and active, then service interrupt ID 0 as normal. + * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it + * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. + */ + LDR R2, =GICD_BASE + LDR R3, =GIC_ERRATA_CHECK_1 + CMP R0, R3 + BEQ unlock_cpu + LDR R3, =GIC_ERRATA_CHECK_2 + CMP R0, R3 + BEQ unlock_cpu + CMP R0, #0 + BNE int_active /* If the ID is not 0, then service the interrupt */ + LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ + TST R3, #1 + BNE int_active /* If active, then service the interrupt */ +unlock_cpu: + LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ + STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ + DSB /* Ensure the write completes before continuing */ + B ret_irq /* Do not service the spurious interrupt */ + /* End workaround */ + +int_active: + LDR R2, =IRQCount /* Read number of IRQs */ + LDR R2, [R2] + CMP R0, R2 /* Clean up and return if no handler */ + BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ + LDR R2, =IRQTable /* Get address of handler */ + LDR R2, [R2, R0, LSL #2] + CMP R2, #0 /* Clean up and return if handler address is 0 */ + BEQ ret_irq + PUSH {R0,R1} + + CPSIE i /* Now safe to re-enable interrupts */ + BLX R2 /* Call handler. R0 will be IRQ number */ + CPSID i /* Disable interrupts again */ + + /* write EOIR (GIC CPU Interface register) */ + POP {R0,R1} + DSB /* Ensure that interrupt source is cleared before we write the EOIR */ +ret_irq: + /* epilogue */ + STR R0, [R1, #ICCEOIR_OFFSET] + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + SUB R1, R1, #1 /* Decrement nesting counter */ + STR R1, [R0] + + POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ + ADD SP, SP, R1 /* Unadjust stack */ + + POP {R0-R3,R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ +;;; +;;; Add more initialization here +;;; +FPUEnable: + ARM + + //Permit access to VFP registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Enable VFP + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP registers to 0 + MOV R2,#0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + //Initialise FPSCR to a known state + VMRS R2,FPSCR + LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R2,R2,R3 + VMSR FPSCR,R2 + + BX LR + + END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.s b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.s deleted file mode 100644 index fb769e5..0000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_IAR/startup_RZA1H.s +++ /dev/null @@ -1,505 +0,0 @@ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Part one of the system initialization code, -;; contains low-level -;; initialization. -;; -;; Copyright 2007 IAR Systems. All rights reserved. -;; -;; $Revision: 49919 $ -;; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION CSTACK:DATA:NOROOT(3) - -; -; The module in this file are included in the libraries, and may be -; replaced by any user-defined modules that define the PUBLIC symbol -; __iar_program_start or a user defined start symbol. -; -; To override the cstartup defined in the library, simply add your -; modified version to the workbench project. - - SECTION .intvec:CODE:NOROOT(2) - - PUBLIC __vector_core_a9 - PUBLIC __RST_Handler - PUBLIC Undefined_Handler - EXTERN SWI_Handler - PUBLIC Prefetch_Handler - PUBLIC Abort_Handler - PUBLIC IRQ_Handler - PUBLIC FIQ_Handler - EXTERN VbarInit - EXTERN SetLowVectors - EXTERN init_TTB - EXTERN enable_mmu - EXTERN Peripheral_BasicInit - EXTERN initsct - EXTERN PowerON_Reset - PUBLIC FPUEnable - - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_core_a9: ; Make this a DATA label, so that stack usage - ; analysis doesn't consider it an uncalled fun - - ARM - - ; All default exception handlers (except reset) are - ; defined as weak symbol definitions. - ; If a handler is defined by the application it will take precedence. - LDR PC,Reset_Addr ; Reset - LDR PC,Undefined_Addr ; Undefined instructions - LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) - LDR PC,Prefetch_Addr ; Prefetch abort - LDR PC,Abort_Addr ; Data abort - DCD 0 ; RESERVED - LDR PC,IRQ_Addr ; IRQ - LDR PC,FIQ_Addr ; FIQ - - DATA - -Reset_Addr: DCD __RST_Handler -Undefined_Addr: DCD Undefined_Handler -SWI_Addr: DCD SWI_Handler -Prefetch_Addr: DCD Prefetch_Handler -Abort_Addr: DCD Abort_Handler -IRQ_Addr: DCD IRQ_Handler -FIQ_Addr: DCD FIQ_Handler - - -; -------------------------------------------------- -; ?cstartup -- low-level system initialization code. -; -; After a reset execution starts here, the mode is ARM, supervisor -; with interrupts disabled. -; - - - - SECTION .text:CODE:NOROOT(2) - EXTERN RZ_A1_SetSramWriteEnable - EXTERN create_translation_table - EXTERN SystemInit - EXTERN InitMemorySubsystem - EXTERN __iar_program_start - REQUIRE __vector_core_a9 - EXTWEAK __iar_init_core - EXTWEAK __iar_init_vfp - - - ARM - -__RST_Handler: -?cstartup: - - -;;; @ Put any cores other than 0 to sleep - mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR - ands r0, r0, #3 - -goToSleep: - wfine - bne goToSleep - - -//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -//@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) - isb - - -;; Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set - - mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register - bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache - bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache - bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU - bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction - bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs - mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register - isb - - -;; Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__vector_core_a9 - mcr p15, 0, r0, c12, c0, 0 - - -; -; Add initialization needed before setup of stackpointers here. -; - -; -; Initialize the stack pointers. -; The pattern below can be used for any of the exception stacks: -; FIQ, IRQ, SVC, ABT, UND, SYS. -; The USR mode uses the same stack as SYS. -; The stack segments must be defined in the linker command file, -; and be declared above. -; - - -; -------------------- -; Mode, correspords to bits 0-5 in CPSR - -#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR - -#define USR_MODE 0x10 ; User mode -#define FIQ_MODE 0x11 ; Fast Interrupt Request mode -#define IRQ_MODE 0x12 ; Interrupt Request mode -#define SVC_MODE 0x13 ; Supervisor mode -#define ABT_MODE 0x17 ; Abort mode -#define UND_MODE 0x1B ; Undefined Instruction mode -#define SYS_MODE 0x1F ; System mode - -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define GICI_BASE 0xe8202000 -#define ICCIAR_OFFSET 0x0000000C -#define ICCEOIR_OFFSET 0x00000010 -#define ICCHPIR_OFFSET 0x00000018 -#define GICD_BASE 0xe8201000 -#define GIC_ERRATA_CHECK_1 0x000003FE -#define GIC_ERRATA_CHECK_2 0x000003FF -#define ICDABR0_OFFSET 0x00000300 -#define ICDIPR0_OFFSET 0x00000400 -#define T_Bit 0x20 ; when T bit is set, core is in Thumb state - - MRS r0, cpsr ; Original PSR value - - ;; Set up the SVC stack pointer. - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #SVC_MODE ; Set SVC mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the fast interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #FIQ_MODE ; Set FIR mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the ABT stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #ABT_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(ABT_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the UDF stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #UND_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(UND_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the normal stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #SYS_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(CSTACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - -;;; - - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - bl create_translation_table - -; USR/SYS stack pointer will be set during kernel init - ldr r0, =SystemInit - blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -; fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 - - - -;;; Continue to __cmain for C-level initialization. - - FUNCALL __RST_Handler, __iar_program_start - B __iar_program_start - - - ldr r0, sf_boot ;@ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - DC32 0x00000001 - -Undefined_Handler: - EXTERN CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - -Prefetch_Handler: - EXTERN CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - -Abort_Handler: - EXTERN CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - -FIQ_Handler: - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ - B . - - EXTERN SVC_Handler /* refer RTX function */ - -IRQ_Handler: - EXTERN IRQCount - EXTERN IRQTable - EXTERN IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ -;;; -;;; Add more initialization here -;;; -FPUEnable: - ARM - - //Permit access to VFP registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Enable VFP - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP registers to 0 - MOV R2,#0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR - - END diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S new file mode 100644 index 0000000..94f605c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S @@ -0,0 +1,505 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2007 IAR Systems. All rights reserved. +;; +;; $Revision: 49919 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector_core_a9 + PUBWEAK __iar_program_start + PUBLIC Undefined_Handler + EXTERN SWI_Handler + PUBLIC Prefetch_Handler + PUBLIC Abort_Handler + PUBLIC IRQ_Handler + PUBLIC FIQ_Handler + EXTERN VbarInit + EXTERN SetLowVectors + EXTERN init_TTB + EXTERN enable_mmu + EXTERN Peripheral_BasicInit + EXTERN initsct + EXTERN PowerON_Reset + PUBLIC FPUEnable + + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_core_a9: ; Make this a DATA label, so that stack usage + ; analysis doesn't consider it an uncalled fun + + ARM + + ; All default exception handlers (except reset) are + ; defined as weak symbol definitions. + ; If a handler is defined by the application it will take precedence. + LDR PC,Reset_Addr ; Reset + LDR PC,Undefined_Addr ; Undefined instructions + LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) + LDR PC,Prefetch_Addr ; Prefetch abort + LDR PC,Abort_Addr ; Data abort + DCD 0 ; RESERVED + LDR PC,IRQ_Addr ; IRQ + LDR PC,FIQ_Addr ; FIQ + + DATA + +Reset_Addr: DCD __iar_program_start +Undefined_Addr: DCD Undefined_Handler +SWI_Addr: DCD SWI_Handler +Prefetch_Addr: DCD Prefetch_Handler +Abort_Addr: DCD Abort_Handler +IRQ_Addr: DCD IRQ_Handler +FIQ_Addr: DCD FIQ_Handler + + +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reset execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + EXTERN RZ_A1_SetSramWriteEnable + EXTERN create_translation_table + EXTERN SystemInit + EXTERN InitMemorySubsystem + EXTERN __cmain + REQUIRE __vector_core_a9 + EXTWEAK __iar_init_core + EXTWEAK __iar_init_vfp + + + ARM + +__iar_program_start: +?cstartup: + + +;;; @ Put any cores other than 0 to sleep + mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR + ands r0, r0, #3 + +goToSleep: + wfine + bne goToSleep + + +//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +//@ Enables Full Access i.e. in both privileged and non privileged modes + mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) + orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 + mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) + isb + + +;; Switch on the VFP and NEON hardware + mov r0, #0x40000000 + vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set + + mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register + bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU + bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction + bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs + mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register + isb + + +;; Set Vector Base Address Register (VBAR) to point to this application's vector table + ldr r0, =__vector_core_a9 + mcr p15, 0, r0, c12, c0, 0 + + +; +; Add initialization needed before setup of stackpointers here. +; + +; +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; + + +; -------------------- +; Mode, correspords to bits 0-5 in CPSR + +#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR + +#define USR_MODE 0x10 ; User mode +#define FIQ_MODE 0x11 ; Fast Interrupt Request mode +#define IRQ_MODE 0x12 ; Interrupt Request mode +#define SVC_MODE 0x13 ; Supervisor mode +#define ABT_MODE 0x17 ; Abort mode +#define UND_MODE 0x1B ; Undefined Instruction mode +#define SYS_MODE 0x1F ; System mode + +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define GICI_BASE 0xe8202000 +#define ICCIAR_OFFSET 0x0000000C +#define ICCEOIR_OFFSET 0x00000010 +#define ICCHPIR_OFFSET 0x00000018 +#define GICD_BASE 0xe8201000 +#define GIC_ERRATA_CHECK_1 0x000003FE +#define GIC_ERRATA_CHECK_2 0x000003FF +#define ICDABR0_OFFSET 0x00000300 +#define ICDIPR0_OFFSET 0x00000400 +#define T_Bit 0x20 ; when T bit is set, core is in Thumb state + + MRS r0, cpsr ; Original PSR value + + ;; Set up the SVC stack pointer. + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the fast interrupt stack pointer. + + BIC r0, r0, #MODE_MSK ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIR mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the ABT stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #ABT_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + + ;; Set up the UDF stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #UND_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + + ;; Set up the normal stack pointer. + + BIC r0 ,r0, #MODE_MSK ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + BIC sp,sp,#0x7 ; Make sure SP is 8 aligned + +;;; + + isb + ldr r0, =RZ_A1_SetSramWriteEnable + blx r0 + + bl create_translation_table + +; USR/SYS stack pointer will be set during kernel init + ldr r0, =SystemInit + blx r0 + ldr r0, =InitMemorySubsystem + blx r0 + +; fp_init + mov r0, #0x3000000 + vmsr fpscr, r0 + + + +;;; Continue to __cmain for C-level initialization. + + FUNCALL __iar_program_start, __cmain + B __cmain + + + ldr r0, sf_boot ;@ dummy to keep boot loader area +loop_here: + b loop_here + +sf_boot: + DC32 0x00000001 + +Undefined_Handler: + EXTERN CUndefHandler + SRSDB SP!, #Mode_UND + PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ + + MRS R0, SPSR + TST R0, #T_Bit /* Check mode */ + MOVEQ R1, #4 /* R1 = 4 ARM mode */ + MOVNE R1, #2 /* R1 = 2 Thumb mode */ + SUB R0, LR, R1 + LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ + BEQ undef_cont + + /* Thumb instruction */ + /* Determine if it is a 32-bit Thumb instruction */ + LDRH R0, [R0] + MOV R2, #0x1c + CMP R2, R0, LSR #11 + BHS undef_cont /* 16-bit Thumb instruction */ + + /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +undef_cont: + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + /* R0 Offending instruction */ + /* R1 =2 (Thumb) or =4 (ARM) */ + BL CUndefHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ + SUB LR, LR, R0 + LDR R0, [SP, #28] /* Restore stacked SPSR */ + MSR SPSR_cxsf, R0 + POP {R0-R4, R12} /* Restore stacked APCS registers */ + ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ + MOVS PC, LR + +Prefetch_Handler: + EXTERN CPAbtHandler + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + MRC p15, 0, R0, c5, c0, 1 /* IFSR */ + MRC p15, 0, R1, c6, c0, 2 /* IFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CPAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stack APCS registers */ + RFEFD SP! /* Return from exception */ + +Abort_Handler: + EXTERN CDAbtHandler + SUB LR, LR, #8 /* Pre-adjust LR */ + SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ + PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ + CLREX /* State of exclusive monitors unknown after taken data abort */ + MRC p15, 0, R0, c5, c0, 0 /* DFSR */ + MRC p15, 0, R1, c6, c0, 0 /* DFAR */ + + MOV R2, LR /* Set LR to third argument */ + +/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R12, R3, #4 + SUB SP, SP, R12 /* Adjust stack */ + PUSH {R12, LR} /* Store stack adjustment and dummy LR */ + + BL CDAbtHandler + + POP {R12, LR} /* Get stack adjustment & discard dummy LR */ + ADD SP, SP, R12 /* Unadjust stack */ + + POP {R0-R4, R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ + +FIQ_Handler: + /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, + * so if a real FIQ Handler is implemented, this will be needed before returning: + */ + /* LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + */ + B . + + EXTERN SVC_Handler /* refer RTX function */ + +IRQ_Handler: + EXTERN IRQCount + EXTERN IRQTable + EXTERN IRQNestLevel + + /* prologue */ + SUB LR, LR, #4 /* Pre-adjust LR */ + SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ + CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ + PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ + +/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ + MOV R3, SP /* Ensure stack is 8-byte aligned */ + AND R1, R3, #4 + SUB SP, SP, R1 /* Adjust stack */ + PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + ADD R1, R1, #1 /* Increment nesting counter */ + STR R1, [R0] + + /* identify and acknowledge interrupt */ + LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ + LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ + DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ + + /* Workaround GIC 390 errata 733075 + * If the ID is not 0, then service the interrupt as normal. + * If the ID is 0 and active, then service interrupt ID 0 as normal. + * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it + * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. + */ + LDR R2, =GICD_BASE + LDR R3, =GIC_ERRATA_CHECK_1 + CMP R0, R3 + BEQ unlock_cpu + LDR R3, =GIC_ERRATA_CHECK_2 + CMP R0, R3 + BEQ unlock_cpu + CMP R0, #0 + BNE int_active /* If the ID is not 0, then service the interrupt */ + LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ + TST R3, #1 + BNE int_active /* If active, then service the interrupt */ +unlock_cpu: + LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ + STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ + DSB /* Ensure the write completes before continuing */ + B ret_irq /* Do not service the spurious interrupt */ + /* End workaround */ + +int_active: + LDR R2, =IRQCount /* Read number of IRQs */ + LDR R2, [R2] + CMP R0, R2 /* Clean up and return if no handler */ + BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ + LDR R2, =IRQTable /* Get address of handler */ + LDR R2, [R2, R0, LSL #2] + CMP R2, #0 /* Clean up and return if handler address is 0 */ + BEQ ret_irq + PUSH {R0,R1} + + CPSIE i /* Now safe to re-enable interrupts */ + BLX R2 /* Call handler. R0 will be IRQ number */ + CPSID i /* Disable interrupts again */ + + /* write EOIR (GIC CPU Interface register) */ + POP {R0,R1} + DSB /* Ensure that interrupt source is cleared before we write the EOIR */ +ret_irq: + /* epilogue */ + STR R0, [R1, #ICCEOIR_OFFSET] + + LDR R0, =IRQNestLevel /* Get address of nesting counter */ + LDR R1, [R0] + SUB R1, R1, #1 /* Decrement nesting counter */ + STR R1, [R0] + + POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ + ADD SP, SP, R1 /* Unadjust stack */ + + POP {R0-R3,R12} /* Restore stacked APCS registers */ + RFEFD SP! /* Return from exception */ +;;; +;;; Add more initialization here +;;; +FPUEnable: + ARM + + //Permit access to VFP registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Enable VFP + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP registers to 0 + MOV R2,#0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + //Initialise FPSCR to a known state + VMRS R2,FPSCR + LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R2,R2,R3 + VMSR FPSCR,R2 + + BX LR + + END diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.s b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.s deleted file mode 100644 index 94f605c..0000000 --- a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.s +++ /dev/null @@ -1,505 +0,0 @@ -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Part one of the system initialization code, -;; contains low-level -;; initialization. -;; -;; Copyright 2007 IAR Systems. All rights reserved. -;; -;; $Revision: 49919 $ -;; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION CSTACK:DATA:NOROOT(3) - -; -; The module in this file are included in the libraries, and may be -; replaced by any user-defined modules that define the PUBLIC symbol -; __iar_program_start or a user defined start symbol. -; -; To override the cstartup defined in the library, simply add your -; modified version to the workbench project. - - SECTION .intvec:CODE:NOROOT(2) - - PUBLIC __vector_core_a9 - PUBWEAK __iar_program_start - PUBLIC Undefined_Handler - EXTERN SWI_Handler - PUBLIC Prefetch_Handler - PUBLIC Abort_Handler - PUBLIC IRQ_Handler - PUBLIC FIQ_Handler - EXTERN VbarInit - EXTERN SetLowVectors - EXTERN init_TTB - EXTERN enable_mmu - EXTERN Peripheral_BasicInit - EXTERN initsct - EXTERN PowerON_Reset - PUBLIC FPUEnable - - - DATA - -__iar_init$$done: ; The vector table is not needed - ; until after copy initialization is done - -__vector_core_a9: ; Make this a DATA label, so that stack usage - ; analysis doesn't consider it an uncalled fun - - ARM - - ; All default exception handlers (except reset) are - ; defined as weak symbol definitions. - ; If a handler is defined by the application it will take precedence. - LDR PC,Reset_Addr ; Reset - LDR PC,Undefined_Addr ; Undefined instructions - LDR PC,SWI_Addr ; Software interrupt (SWI/SVC) - LDR PC,Prefetch_Addr ; Prefetch abort - LDR PC,Abort_Addr ; Data abort - DCD 0 ; RESERVED - LDR PC,IRQ_Addr ; IRQ - LDR PC,FIQ_Addr ; FIQ - - DATA - -Reset_Addr: DCD __iar_program_start -Undefined_Addr: DCD Undefined_Handler -SWI_Addr: DCD SWI_Handler -Prefetch_Addr: DCD Prefetch_Handler -Abort_Addr: DCD Abort_Handler -IRQ_Addr: DCD IRQ_Handler -FIQ_Addr: DCD FIQ_Handler - - -; -------------------------------------------------- -; ?cstartup -- low-level system initialization code. -; -; After a reset execution starts here, the mode is ARM, supervisor -; with interrupts disabled. -; - - - - SECTION .text:CODE:NOROOT(2) - EXTERN RZ_A1_SetSramWriteEnable - EXTERN create_translation_table - EXTERN SystemInit - EXTERN InitMemorySubsystem - EXTERN __cmain - REQUIRE __vector_core_a9 - EXTWEAK __iar_init_core - EXTWEAK __iar_init_vfp - - - ARM - -__iar_program_start: -?cstartup: - - -;;; @ Put any cores other than 0 to sleep - mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR - ands r0, r0, #3 - -goToSleep: - wfine - bne goToSleep - - -//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -//@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) - isb - - -;; Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set - - mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register - bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache - bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache - bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU - bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction - bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs - mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register - isb - - -;; Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__vector_core_a9 - mcr p15, 0, r0, c12, c0, 0 - - -; -; Add initialization needed before setup of stackpointers here. -; - -; -; Initialize the stack pointers. -; The pattern below can be used for any of the exception stacks: -; FIQ, IRQ, SVC, ABT, UND, SYS. -; The USR mode uses the same stack as SYS. -; The stack segments must be defined in the linker command file, -; and be declared above. -; - - -; -------------------- -; Mode, correspords to bits 0-5 in CPSR - -#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR - -#define USR_MODE 0x10 ; User mode -#define FIQ_MODE 0x11 ; Fast Interrupt Request mode -#define IRQ_MODE 0x12 ; Interrupt Request mode -#define SVC_MODE 0x13 ; Supervisor mode -#define ABT_MODE 0x17 ; Abort mode -#define UND_MODE 0x1B ; Undefined Instruction mode -#define SYS_MODE 0x1F ; System mode - -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define GICI_BASE 0xe8202000 -#define ICCIAR_OFFSET 0x0000000C -#define ICCEOIR_OFFSET 0x00000010 -#define ICCHPIR_OFFSET 0x00000018 -#define GICD_BASE 0xe8201000 -#define GIC_ERRATA_CHECK_1 0x000003FE -#define GIC_ERRATA_CHECK_2 0x000003FF -#define ICDABR0_OFFSET 0x00000300 -#define ICDIPR0_OFFSET 0x00000400 -#define T_Bit 0x20 ; when T bit is set, core is in Thumb state - - MRS r0, cpsr ; Original PSR value - - ;; Set up the SVC stack pointer. - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #SVC_MODE ; Set SVC mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the fast interrupt stack pointer. - - BIC r0, r0, #MODE_MSK ; Clear the mode bits - ORR r0, r0, #FIQ_MODE ; Set FIR mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the ABT stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #ABT_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(ABT_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - - ;; Set up the UDF stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #UND_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(UND_STACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - - ;; Set up the normal stack pointer. - - BIC r0 ,r0, #MODE_MSK ; Clear the mode bits - ORR r0 ,r0, #SYS_MODE ; Set System mode bits - MSR cpsr_c, r0 ; Change the mode - LDR sp, =SFE(CSTACK) ; End of CSTACK - BIC sp,sp,#0x7 ; Make sure SP is 8 aligned - -;;; - - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - bl create_translation_table - -; USR/SYS stack pointer will be set during kernel init - ldr r0, =SystemInit - blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -; fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 - - - -;;; Continue to __cmain for C-level initialization. - - FUNCALL __iar_program_start, __cmain - B __cmain - - - ldr r0, sf_boot ;@ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - DC32 0x00000001 - -Undefined_Handler: - EXTERN CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - -Prefetch_Handler: - EXTERN CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - -Abort_Handler: - EXTERN CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - -FIQ_Handler: - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ - B . - - EXTERN SVC_Handler /* refer RTX function */ - -IRQ_Handler: - EXTERN IRQCount - EXTERN IRQTable - EXTERN IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ -;;; -;;; Add more initialization here -;;; -FPUEnable: - ARM - - //Permit access to VFP registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Enable VFP - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP registers to 0 - MOV R2,#0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR - - END diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S new file mode 100644 index 0000000..6630f36 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S @@ -0,0 +1,242 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f051x8.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.s deleted file mode 100644 index 6630f36..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.s +++ /dev/null @@ -1,242 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f051x8.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_IRQHandler ; CEC - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_COMP_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_COMP_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM6_DAC_IRQHandler -TIM14_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S new file mode 100644 index 0000000..71932f4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S @@ -0,0 +1,217 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f051x8.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + + +__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.s deleted file mode 100644 index 71932f4..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.s +++ /dev/null @@ -1,217 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f051x8.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - - -__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_IRQHandler ; CEC - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_COMP_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_COMP_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM6_DAC_IRQHandler -TIM14_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S new file mode 100644 index 0000000..a6eea51 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S @@ -0,0 +1,226 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20001000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s deleted file mode 100644 index a6eea51..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s +++ /dev/null @@ -1,226 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f031x6.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20001000 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -USART1_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S new file mode 100644 index 0000000..757a90d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S @@ -0,0 +1,199 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20001000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s deleted file mode 100644 index 757a90d..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s +++ /dev/null @@ -1,199 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f031x6.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20001000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -USART1_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S new file mode 100644 index 0000000..2d50570 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S @@ -0,0 +1,261 @@ +/** + ****************************************************************************** + * @file startup_stm32f031x6.s + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ +// bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word 0 /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s deleted file mode 100644 index 2d50570..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s +++ /dev/null @@ -1,261 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f031x6.s - * @author MCD Application Team - * @version V2.2.2 - * @date 26-June-2015 - * @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/* Call the application's entry point.*/ -// bl main - bl _start - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detect */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* Reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* Reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word 0 /* Reserved */ - .word SPI1_IRQHandler /* SPI1 */ - .word 0 /* Reserved */ - .word USART1_IRQHandler /* USART1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S new file mode 100644 index 0000000..c02773e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S @@ -0,0 +1,272 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;*

© COPYRIGHT(c) 2015 STMicroelectronics

+;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.s deleted file mode 100644 index c02773e..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.s +++ /dev/null @@ -1,272 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f031x6.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address, -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* -;*

© COPYRIGHT(c) 2015 STMicroelectronics

-;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - PUBWEAK DMA1_Channel4_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_IRQHandler - B DMA1_Channel4_5_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_UP_TRG_COM_IRQHandler - B TIM1_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler - B TIM16_IRQHandler - - PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler - B TIM17_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S new file mode 100644 index 0000000..25c8f93 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S @@ -0,0 +1,267 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20001800 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + + + LDR R0, =__initial_sp ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + +;; SYSCFG clock enable + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s deleted file mode 100644 index 25c8f93..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s +++ /dev/null @@ -1,267 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f042x6.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20001800 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_CAN_IRQHandler ; CEC and CAN - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - - - LDR R0, =__initial_sp ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart - -;; SYSCFG clock enable - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_VDDIO2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_CRS_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_CAN_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_VDDIO2_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_CRS_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_CAN_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S new file mode 100644 index 0000000..0144877 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S @@ -0,0 +1,240 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20001800 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + + + LDR R0, =__initial_sp ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + +;; SYSCFG clock enable + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s deleted file mode 100644 index 0144877..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s +++ /dev/null @@ -1,240 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f042x6.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20001800 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_CAN_IRQHandler ; CEC and CAN - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - - - LDR R0, =__initial_sp ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart - -;; SYSCFG clock enable - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_VDDIO2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_CRS_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_CAN_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_VDDIO2_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_CRS_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_CAN_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S new file mode 100644 index 0000000..a751fe5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S @@ -0,0 +1,308 @@ +/** + ****************************************************************************** + * @file startup_stm32f042x6.s + * @author MCD Application Team + * @version V2.2.2 + * @date 26-June-2015 + * @brief STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/*Check if boot space corresponds to test memory*/ + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + MOVS R1, #0 + MOVS R2, #1 + CMP R1, R2 + BNE ApplicationStart + + /*SYSCFG clock enable*/ + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ +// bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC and CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word TSC_IRQHandler /* TSC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word CEC_CAN_IRQHandler /* CEC and CAN */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s deleted file mode 100644 index a751fe5..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s +++ /dev/null @@ -1,308 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f042x6.s - * @author MCD Application Team - * @version V2.2.2 - * @date 26-June-2015 - * @brief STM32F042x4/STM32F042x6 devices vector table for Atollic TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/*Check if boot space corresponds to test memory*/ - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - MOVS R1, #0 - MOVS R2, #1 - CMP R1, R2 - BNE ApplicationStart - - /*SYSCFG clock enable*/ - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -/*Set CFGR1 register with flash memory remap at address 0*/ - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] - -ApplicationStart: -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/* Call the application's entry point.*/ -// bl main - bl _start - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_CRS_IRQHandler /* RCC and CRS */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word TSC_IRQHandler /* TSC */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* Reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word 0 /* Reserved */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word CEC_CAN_IRQHandler /* CEC and CAN */ - .word USB_IRQHandler /* USB */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_VDDIO2_IRQHandler - .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_CRS_IRQHandler - .thumb_set RCC_CRS_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak TSC_IRQHandler - .thumb_set TSC_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak CEC_CAN_IRQHandler - .thumb_set CEC_CAN_IRQHandler,Default_Handler - - .weak USB_IRQHandler - .thumb_set USB_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S new file mode 100644 index 0000000..8cde736 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S @@ -0,0 +1,323 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Version : V2.2.2 +;* Date : 26-June-2015 +;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;*

© COPYRIGHT(c) 2015 STMicroelectronics

+;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart +;; SYSCFG clock enable + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK CEC_CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_CAN_IRQHandler + B CEC_CAN_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.s b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.s deleted file mode 100644 index 8cde736..0000000 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.s +++ /dev/null @@ -1,323 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f042x6.s -;* Author : MCD Application Team -;* Version : V2.2.2 -;* Date : 26-June-2015 -;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address, -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* -;*

© COPYRIGHT(c) 2015 STMicroelectronics

-;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TSC - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_CAN_IRQHandler ; CEC and CAN - DCD USB_IRQHandler ; USB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - - LDR R0, =sfe(CSTACK) ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart -;; SYSCFG clock enable - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_VDDIO2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_VDDIO2_IRQHandler - B PVD_VDDIO2_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_CRS_IRQHandler - B RCC_CRS_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK TSC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TSC_IRQHandler - B TSC_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - PUBWEAK DMA1_Channel4_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_IRQHandler - B DMA1_Channel4_5_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_UP_TRG_COM_IRQHandler - B TIM1_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler - B TIM16_IRQHandler - - PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler - B TIM17_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK CEC_CAN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_CAN_IRQHandler - B CEC_CAN_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.S b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.S new file mode 100644 index 0000000..2d470b3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.S @@ -0,0 +1,415 @@ +******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f207xx.s +;* Author : MCD Application Team +;* Version : V2.1.1 +;* Date : 20-November-2015 +;* Description : STM32F207xx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.s b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.s deleted file mode 100644 index 2d470b3..0000000 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.s +++ /dev/null @@ -1,415 +0,0 @@ -******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f207xx.s -;* Author : MCD Application Team -;* Version : V2.1.1 -;* Date : 20-November-2015 -;* Description : STM32F207xx devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.S b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.S new file mode 100644 index 0000000..d5fa1d6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.S @@ -0,0 +1,436 @@ +******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f207xx.s +;* Author : MCD Application Team +;* Version : V2.1.1 +;* Date : 20-November-2015 +;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.s b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.s deleted file mode 100644 index d5fa1d6..0000000 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.s +++ /dev/null @@ -1,436 +0,0 @@ -******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f207xx.s -;* Author : MCD Application Team -;* Version : V2.1.1 -;* Date : 20-November-2015 -;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.S b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.S new file mode 100644 index 0000000..d9d1225 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.S @@ -0,0 +1,508 @@ +/** + ****************************************************************************** + * @file startup_stm32f207xx.s + * @author MCD Application Team + * @version V2.1.1 + * @date 20-November-2015 + * @brief STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.s b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.s deleted file mode 100644 index d9d1225..0000000 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.s +++ /dev/null @@ -1,508 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f207xx.s - * @author MCD Application Team - * @version V2.1.1 - * @date 20-November-2015 - * @brief STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.S b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.S new file mode 100644 index 0000000..a5a13fe --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.S @@ -0,0 +1,633 @@ +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f207xx.s +;* Author : MCD Application Team +;* Version : V2.1.1 +;* Date : 20-November-2015 +;* Description : STM32F20x/21x devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and RNG + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.s b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.s deleted file mode 100644 index a5a13fe..0000000 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.s +++ /dev/null @@ -1,633 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f207xx.s -;* Author : MCD Application Team -;* Version : V2.1.1 -;* Date : 20-November-2015 -;* Description : STM32F20x/21x devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and RNG - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK FSMC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FSMC_IRQHandler - B FSMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK ETH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_IRQHandler - B ETH_IRQHandler - - PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_WKUP_IRQHandler - B ETH_WKUP_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_OUT_IRQHandler - B OTG_HS_EP1_OUT_IRQHandler - - PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_IN_IRQHandler - B OTG_HS_EP1_IN_IRQHandler - - PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_WKUP_IRQHandler - B OTG_HS_WKUP_IRQHandler - - PUBWEAK OTG_HS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler - - PUBWEAK DCMI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DCMI_IRQHandler - B DCMI_IRQHandler - - PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -HASH_RNG_IRQHandler - B HASH_RNG_IRQHandler - - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410xx.S new file mode 100644 index 0000000..5a1c1b1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410xx.S @@ -0,0 +1,439 @@ +/** + ****************************************************************************** + * @file startup_stm32f410rx.s + * @author MCD Application Team + * @version V2.4.1 + * @date 09-October-2015 + * @brief STM32F410Rx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM5_IRQHandler /* TIM5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410xx.s deleted file mode 100644 index 5a1c1b1..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410xx.s +++ /dev/null @@ -1,439 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f410rx.s - * @author MCD Application Team - * @version V2.4.1 - * @date 09-October-2015 - * @brief STM32F410Rx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_IRQHandler /* TIM1 Update */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM5_IRQHandler /* TIM5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ - .word 0 /* Reserved */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI5_IRQHandler /* SPI5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ - .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ - .word LPTIM1_IRQHandler /* LP TIM1 */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak FMPI2C1_EV_IRQHandler - .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler - - .weak FMPI2C1_ER_IRQHandler - .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410xx.S new file mode 100644 index 0000000..3dff77f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410xx.S @@ -0,0 +1,510 @@ +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f410rx.s +;* Author : MCD Application Team +;* Version : V2.4.1 +;* Date : 09-October-2015 +;* Description : STM32F410Rx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LP TIM1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK FMPI2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_EV_IRQHandler + B FMPI2C1_EV_IRQHandler + + PUBWEAK FMPI2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_ER_IRQHandler + B FMPI2C1_ER_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410xx.s deleted file mode 100644 index 3dff77f..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410xx.s +++ /dev/null @@ -1,510 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f410rx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F410Rx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI5_IRQHandler ; SPI5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error - DCD LPTIM1_IRQHandler ; LP TIM1 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_IRQHandler - B TIM1_UP_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B RNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI5_IRQHandler - B SPI5_IRQHandler - - PUBWEAK FMPI2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_EV_IRQHandler - B FMPI2C1_EV_IRQHandler - - PUBWEAK FMPI2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_ER_IRQHandler - B FMPI2C1_ER_IRQHandler - - PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412xx.S new file mode 100644 index 0000000..10aad67 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412xx.S @@ -0,0 +1,531 @@ +/** + ****************************************************************************** + * @file startup_stm32f412zx.s + * @author MCD Application Team + * @version V2.5.1 + * @date 28-June-2016 + * @brief STM32F412Zx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QUADSPI_IRQHandler /* QuadSPI */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412xx.s deleted file mode 100644 index 10aad67..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412xx.s +++ /dev/null @@ -1,531 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f412zx.s - * @author MCD Application Team - * @version V2.5.1 - * @date 28-June-2016 - * @brief STM32F412Zx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM6_IRQHandler /* TIM6 */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word QUADSPI_IRQHandler /* QuadSPI */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ - .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak FMPI2C1_EV_IRQHandler - .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler - - .weak FMPI2C1_ER_IRQHandler - .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.S new file mode 100644 index 0000000..98fa2eb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.S @@ -0,0 +1,449 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Version : V2.4.0 +;* Date : 14-August-2015 +;* Description : STM32F429x devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInitPre + IMPORT HAL_InitPre + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInitPre + BLX R0 + LDR R0, =HAL_InitPre + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s deleted file mode 100644 index 98fa2eb..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s +++ /dev/null @@ -1,449 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f429xx.s -;* Author : MCD Application Team -;* Version : V2.4.0 -;* Date : 14-August-2015 -;* Description : STM32F429x devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInitPre - IMPORT HAL_InitPre - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInitPre - BLX R0 - LDR R0, =HAL_InitPre - BLX R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S new file mode 100644 index 0000000..2acea79 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S @@ -0,0 +1,422 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Version : V2.4.0 +;* Date : 14-August-2015 +;* Description : STM32F429x devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20030000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInitPre + IMPORT HAL_InitPre + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInitPre + BLX R0 + LDR R0, =HAL_InitPre + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s deleted file mode 100644 index 2acea79..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s +++ /dev/null @@ -1,422 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f429xx.s -;* Author : MCD Application Team -;* Version : V2.4.0 -;* Date : 14-August-2015 -;* Description : STM32F429x devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20030000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInitPre - IMPORT HAL_InitPre - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInitPre - BLX R0 - LDR R0, =HAL_InitPre - BLX R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.S new file mode 100644 index 0000000..73a6ee2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.S @@ -0,0 +1,554 @@ +/** + ****************************************************************************** + * @file startup_stm32f437xx.s + * @author MCD Application Team + * @version V2.6.0 + * @date 04-November-2016 + * @brief STM32F437xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.s deleted file mode 100644 index 73a6ee2..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.s +++ /dev/null @@ -1,554 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f437xx.s - * @author MCD Application Team - * @version V2.6.0 - * @date 04-November-2016 - * @brief STM32F437xx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2D_IRQHandler /* DMA2D */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S new file mode 100644 index 0000000..7293fb9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S @@ -0,0 +1,445 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.6.0 +;* Date : 04-November-2016 +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20030000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s deleted file mode 100644 index 7293fb9..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s +++ /dev/null @@ -1,445 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f439xx.s -;* Author : MCD Application Team -;* Version : V2.6.0 -;* Date : 04-November-2016 -;* Description : STM32F439x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20030000 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYPTO - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S new file mode 100644 index 0000000..46cd696 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S @@ -0,0 +1,418 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Version : V2.6.0 +;* Date : 04-November-2016 +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20030000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s deleted file mode 100644 index 46cd696..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s +++ /dev/null @@ -1,418 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f439xx.s -;* Author : MCD Application Team -;* Version : V2.6.0 -;* Date : 04-November-2016 -;* Description : STM32F439x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20030000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYPTO - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.S new file mode 100644 index 0000000..84bed04 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.S @@ -0,0 +1,440 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Version : V2.3.2 +;* Date : 26-June-2015 +;* Description : STM32F446x devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QuadSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD I2C4_Event_IRQHandler ; I2C 4 Event + DCD I2C4_Error_IRQHandler ; I2C 4 Error +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QuadSPI_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT I2C4_Event_IRQHandler [WEAK] + EXPORT I2C4_Error_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +QuadSPI_IRQHandler +CEC_IRQHandler +SPDIF_RX_IRQHandler +I2C4_Event_IRQHandler +I2C4_Error_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.s deleted file mode 100644 index 84bed04..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.s +++ /dev/null @@ -1,440 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f446xx.s -;* Author : MCD Application Team -;* Version : V2.3.2 -;* Date : 26-June-2015 -;* Description : STM32F446x devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI1_IRQHandler ; SAI1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI2_IRQHandler ; SAI2 - DCD QuadSPI_IRQHandler ; QuadSPI - DCD CEC_IRQHandler ; CEC - DCD SPDIF_RX_IRQHandler ; SPDIF RX - DCD I2C4_Event_IRQHandler ; I2C 4 Event - DCD I2C4_Error_IRQHandler ; I2C 4 Error -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT QuadSPI_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT SPDIF_RX_IRQHandler [WEAK] - EXPORT I2C4_Event_IRQHandler [WEAK] - EXPORT I2C4_Error_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SAI1_IRQHandler -SAI2_IRQHandler -QuadSPI_IRQHandler -CEC_IRQHandler -SPDIF_RX_IRQHandler -I2C4_Event_IRQHandler -I2C4_Error_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.S new file mode 100644 index 0000000..96f3fed --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.S @@ -0,0 +1,413 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Version : V2.3.2 +;* Date : 26-June-2015 +;* Description : STM32F446x devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QuadSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD I2C4_Event_IRQHandler ; I2C 4 Event + DCD I2C4_Error_IRQHandler ; I2C 4 Error +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QuadSPI_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT I2C4_Event_IRQHandler [WEAK] + EXPORT I2C4_Error_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +QuadSPI_IRQHandler +CEC_IRQHandler +SPDIF_RX_IRQHandler +I2C4_Event_IRQHandler +I2C4_Error_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.s deleted file mode 100644 index 96f3fed..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.s +++ /dev/null @@ -1,413 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f446xx.s -;* Author : MCD Application Team -;* Version : V2.3.2 -;* Date : 26-June-2015 -;* Description : STM32F446x devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20020000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI1_IRQHandler ; SAI1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI2_IRQHandler ; SAI2 - DCD QuadSPI_IRQHandler ; QuadSPI - DCD CEC_IRQHandler ; CEC - DCD SPDIF_RX_IRQHandler ; SPDIF RX - DCD I2C4_Event_IRQHandler ; I2C 4 Event - DCD I2C4_Error_IRQHandler ; I2C 4 Error -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT QuadSPI_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT SPDIF_RX_IRQHandler [WEAK] - EXPORT I2C4_Event_IRQHandler [WEAK] - EXPORT I2C4_Error_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SAI1_IRQHandler -SAI2_IRQHandler -QuadSPI_IRQHandler -CEC_IRQHandler -SPDIF_RX_IRQHandler -I2C4_Event_IRQHandler -I2C4_Error_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.S new file mode 100644 index 0000000..dd394f8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.S @@ -0,0 +1,678 @@ +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Version : V2.3.2 +;* Date : 26-June-2015 +;* Description : STM32F446xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QuadSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD FMPI2C1_Event_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_Error_IRQHandler ; FMPI2C1 Error + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QuadSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QuadSPI_IRQHandler + B QuadSPI_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK FMPI2C1_Event_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_Event_IRQHandler + B FMPI2C1_Event_IRQHandler + + PUBWEAK FMPI2C1_Error_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_Error_IRQHandler + B FMPI2C1_Error_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.s deleted file mode 100644 index dd394f8..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.s +++ /dev/null @@ -1,678 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f446xx.s -;* Author : MCD Application Team -;* Version : V2.3.2 -;* Date : 26-June-2015 -;* Description : STM32F446xx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI1_IRQHandler ; SAI1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI2_IRQHandler ; SAI2 - DCD QuadSPI_IRQHandler ; QuadSPI - DCD CEC_IRQHandler ; CEC - DCD SPDIF_RX_IRQHandler ; SPDIF RX - DCD FMPI2C1_Event_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_Error_IRQHandler ; FMPI2C1 Error - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_OUT_IRQHandler - B OTG_HS_EP1_OUT_IRQHandler - - PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_IN_IRQHandler - B OTG_HS_EP1_IN_IRQHandler - - PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_WKUP_IRQHandler - B OTG_HS_WKUP_IRQHandler - - PUBWEAK OTG_HS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler - - PUBWEAK DCMI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DCMI_IRQHandler - B DCMI_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI4_IRQHandler - B SPI4_IRQHandler - - PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAI1_IRQHandler - B SAI1_IRQHandler - - PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAI2_IRQHandler - B SAI2_IRQHandler - - PUBWEAK QuadSPI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QuadSPI_IRQHandler - B QuadSPI_IRQHandler - - PUBWEAK CEC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CEC_IRQHandler - B CEC_IRQHandler - - PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler - - PUBWEAK FMPI2C1_Event_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_Event_IRQHandler - B FMPI2C1_Event_IRQHandler - - PUBWEAK FMPI2C1_Error_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_Error_IRQHandler - B FMPI2C1_Error_IRQHandler - - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.S new file mode 100644 index 0000000..196df1b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.S @@ -0,0 +1,449 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Version : V2.4.1 +;* Date : 09-October-2015 +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20050000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.s deleted file mode 100644 index 196df1b..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.s +++ /dev/null @@ -1,449 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f469xx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F469x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20050000 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD QUADSPI_IRQHandler ; QUADSPI - DCD DSI_IRQHandler ; DSI - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT DSI_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler -QUADSPI_IRQHandler -DSI_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.S new file mode 100644 index 0000000..01f2bbc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.S @@ -0,0 +1,422 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Version : V2.4.1 +;* Date : 09-October-2015 +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20050000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.s deleted file mode 100644 index 01f2bbc..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.s +++ /dev/null @@ -1,422 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f469xx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F469x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20050000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD QUADSPI_IRQHandler ; QUADSPI - DCD DSI_IRQHandler ; DSI - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT DSI_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler -QUADSPI_IRQHandler -DSI_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.S new file mode 100644 index 0000000..44e20f3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.S @@ -0,0 +1,564 @@ +/** + ****************************************************************************** + * @file startup_stm32f469xx.s + * @author MCD Application Team + * @version V2.4.1 + * @date 09-October-2015 + * @brief STM32F469xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word DSI_IRQHandler /* DSI */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + + + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.s deleted file mode 100644 index 44e20f3..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.s +++ /dev/null @@ -1,564 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f469xx.s - * @author MCD Application Team - * @version V2.4.1 - * @date 09-October-2015 - * @brief STM32F469xx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* Reserved */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word DSI_IRQHandler /* DSI */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak DSI_IRQHandler - .thumb_set DSI_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - - - - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.S new file mode 100644 index 0000000..f0fc3e3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.S @@ -0,0 +1,704 @@ +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Version : V2.4.1 +;* Date : 09-October-2015 +;* Description : STM32F469xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI Controller + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.s deleted file mode 100644 index f0fc3e3..0000000 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.s +++ /dev/null @@ -1,704 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f469xx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F469xx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD QUADSPI_IRQHandler ; QUADSPI - DCD DSI_IRQHandler ; DSI Controller - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK ETH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_IRQHandler - B ETH_IRQHandler - - PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_WKUP_IRQHandler - B ETH_WKUP_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_OUT_IRQHandler - B OTG_HS_EP1_OUT_IRQHandler - - PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_IN_IRQHandler - B OTG_HS_EP1_IN_IRQHandler - - PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_WKUP_IRQHandler - B OTG_HS_WKUP_IRQHandler - - PUBWEAK OTG_HS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler - - PUBWEAK DCMI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DCMI_IRQHandler - B DCMI_IRQHandler - - PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -HASH_RNG_IRQHandler - B HASH_RNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK UART7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART7_IRQHandler - B UART7_IRQHandler - - PUBWEAK UART8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART8_IRQHandler - B UART8_IRQHandler - - PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI4_IRQHandler - B SPI4_IRQHandler - - PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI5_IRQHandler - B SPI5_IRQHandler - - PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI6_IRQHandler - B SPI6_IRQHandler - - PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAI1_IRQHandler - B SAI1_IRQHandler - - PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LTDC_IRQHandler - B LTDC_IRQHandler - - PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler - - PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler - - PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - - PUBWEAK DSI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DSI_IRQHandler - B DSI_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.S new file mode 100644 index 0000000..1c591e6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.S @@ -0,0 +1,500 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f769xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 22-April-2016 +;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20080000 ; Top of RAM + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD DSI_IRQHandler ; DSI + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DSI_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SDMMC2_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +JPEG_IRQHandler +MDIOS_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s deleted file mode 100644 index 1c591e6..0000000 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f769xx.s +++ /dev/null @@ -1,500 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f769xx.s -;* Author : MCD Application Team -;* Version : V1.1.0 -;* Date : 22-April-2016 -;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM7 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20080000 ; Top of RAM - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD RNG_IRQHandler ; Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD SAI2_IRQHandler ; SAI2 - DCD QUADSPI_IRQHandler ; QUADSPI - DCD LPTIM1_IRQHandler ; LPTIM1 - DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error - DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD DSI_IRQHandler ; DSI - DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt - DCD SDMMC2_IRQHandler ; SDMMC2 - DCD CAN3_TX_IRQHandler ; CAN3 TX - DCD CAN3_RX0_IRQHandler ; CAN3 RX0 - DCD CAN3_RX1_IRQHandler ; CAN3 RX1 - DCD CAN3_SCE_IRQHandler ; CAN3 SCE - DCD JPEG_IRQHandler ; JPEG - DCD MDIOS_IRQHandler ; MDIOS -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDMMC1_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT I2C4_EV_IRQHandler [WEAK] - EXPORT I2C4_ER_IRQHandler [WEAK] - EXPORT SPDIF_RX_IRQHandler [WEAK] - EXPORT DSI_IRQHandler [WEAK] - EXPORT DFSDM1_FLT0_IRQHandler [WEAK] - EXPORT DFSDM1_FLT1_IRQHandler [WEAK] - EXPORT DFSDM1_FLT2_IRQHandler [WEAK] - EXPORT DFSDM1_FLT3_IRQHandler [WEAK] - EXPORT SDMMC2_IRQHandler [WEAK] - EXPORT CAN3_TX_IRQHandler [WEAK] - EXPORT CAN3_RX0_IRQHandler [WEAK] - EXPORT CAN3_RX1_IRQHandler [WEAK] - EXPORT CAN3_SCE_IRQHandler [WEAK] - EXPORT JPEG_IRQHandler [WEAK] - EXPORT MDIOS_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDMMC1_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler -SAI2_IRQHandler -QUADSPI_IRQHandler -LPTIM1_IRQHandler -CEC_IRQHandler -I2C4_EV_IRQHandler -I2C4_ER_IRQHandler -SPDIF_RX_IRQHandler -DSI_IRQHandler -DFSDM1_FLT0_IRQHandler -DFSDM1_FLT1_IRQHandler -DFSDM1_FLT2_IRQHandler -DFSDM1_FLT3_IRQHandler -SDMMC2_IRQHandler -CAN3_TX_IRQHandler -CAN3_RX0_IRQHandler -CAN3_RX1_IRQHandler -CAN3_SCE_IRQHandler -JPEG_IRQHandler -MDIOS_IRQHandler - B . - - ENDP - - ALIGN - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/startup_stm32f769xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/startup_stm32f769xx.S new file mode 100644 index 0000000..8521c8b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/startup_stm32f769xx.S @@ -0,0 +1,479 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f769xx.s +;* Author : MCD Application Team +;* Version : V1.1.0 +;* Date : 22-April-2016 +;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +__initial_sp EQU 0x20080000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD DSI_IRQHandler ; DSI + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 + DCD CAN3_TX_IRQHandler ; CAN3 TX + DCD CAN3_RX0_IRQHandler ; CAN3 RX0 + DCD CAN3_RX1_IRQHandler ; CAN3 RX1 + DCD CAN3_SCE_IRQHandler ; CAN3 SCE + DCD JPEG_IRQHandler ; JPEG + DCD MDIOS_IRQHandler ; MDIOS +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT CAN3_TX_IRQHandler [WEAK] + EXPORT CAN3_RX0_IRQHandler [WEAK] + EXPORT CAN3_RX1_IRQHandler [WEAK] + EXPORT CAN3_SCE_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +DSI_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SDMMC2_IRQHandler +CAN3_TX_IRQHandler +CAN3_RX0_IRQHandler +CAN3_RX1_IRQHandler +CAN3_SCE_IRQHandler +JPEG_IRQHandler +MDIOS_IRQHandler + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/startup_stm32f769xx.s b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/startup_stm32f769xx.s deleted file mode 100644 index 8521c8b..0000000 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_ARM_STD/startup_stm32f769xx.s +++ /dev/null @@ -1,479 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f769xx.s -;* Author : MCD Application Team -;* Version : V1.1.0 -;* Date : 22-April-2016 -;* Description : STM32F769xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM7 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -__initial_sp EQU 0x20080000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDMMC1_IRQHandler ; SDMMC1 - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD RNG_IRQHandler ; Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD SAI2_IRQHandler ; SAI2 - DCD QUADSPI_IRQHandler ; QUADSPI - DCD LPTIM1_IRQHandler ; LPTIM1 - DCD CEC_IRQHandler ; HDMI_CEC - DCD I2C4_EV_IRQHandler ; I2C4 Event - DCD I2C4_ER_IRQHandler ; I2C4 Error - DCD SPDIF_RX_IRQHandler ; SPDIF_RX - DCD DSI_IRQHandler ; DSI - DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt - DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt - DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt - DCD SDMMC2_IRQHandler ; SDMMC2 - DCD CAN3_TX_IRQHandler ; CAN3 TX - DCD CAN3_RX0_IRQHandler ; CAN3 RX0 - DCD CAN3_RX1_IRQHandler ; CAN3 RX1 - DCD CAN3_SCE_IRQHandler ; CAN3 SCE - DCD JPEG_IRQHandler ; JPEG - DCD MDIOS_IRQHandler ; MDIOS -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDMMC1_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT I2C4_EV_IRQHandler [WEAK] - EXPORT I2C4_ER_IRQHandler [WEAK] - EXPORT SPDIF_RX_IRQHandler [WEAK] - EXPORT DSI_IRQHandler [WEAK] - EXPORT DFSDM1_FLT0_IRQHandler [WEAK] - EXPORT DFSDM1_FLT1_IRQHandler [WEAK] - EXPORT DFSDM1_FLT2_IRQHandler [WEAK] - EXPORT DFSDM1_FLT3_IRQHandler [WEAK] - EXPORT SDMMC2_IRQHandler [WEAK] - EXPORT CAN3_TX_IRQHandler [WEAK] - EXPORT CAN3_RX0_IRQHandler [WEAK] - EXPORT CAN3_RX1_IRQHandler [WEAK] - EXPORT CAN3_SCE_IRQHandler [WEAK] - EXPORT JPEG_IRQHandler [WEAK] - EXPORT MDIOS_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDMMC1_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler -SAI2_IRQHandler -QUADSPI_IRQHandler -LPTIM1_IRQHandler -CEC_IRQHandler -I2C4_EV_IRQHandler -I2C4_ER_IRQHandler -SPDIF_RX_IRQHandler -DSI_IRQHandler -DFSDM1_FLT0_IRQHandler -DFSDM1_FLT1_IRQHandler -DFSDM1_FLT2_IRQHandler -DFSDM1_FLT3_IRQHandler -SDMMC2_IRQHandler -CAN3_TX_IRQHandler -CAN3_RX0_IRQHandler -CAN3_RX1_IRQHandler -CAN3_SCE_IRQHandler -JPEG_IRQHandler -MDIOS_IRQHandler - B . - - ENDP - - ALIGN - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.S b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.S new file mode 100644 index 0000000..72833bf --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.S @@ -0,0 +1,629 @@ +/** + ****************************************************************************** + * @file startup_stm32f769xx.s + * @author MCD Application Team + * @version V1.1.0 + * @date 22-April-2016 + * @brief STM32F769xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word DSI_IRQHandler /* DSI */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 */ + .word CAN3_TX_IRQHandler /* CAN3 TX */ + .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ + .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ + .word CAN3_SCE_IRQHandler /* CAN3 SCE */ + .word JPEG_IRQHandler /* JPEG */ + .word MDIOS_IRQHandler /* MDIOS */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak CAN3_TX_IRQHandler + .thumb_set CAN3_TX_IRQHandler,Default_Handler + + .weak CAN3_RX0_IRQHandler + .thumb_set CAN3_RX0_IRQHandler,Default_Handler + + .weak CAN3_RX1_IRQHandler + .thumb_set CAN3_RX1_IRQHandler,Default_Handler + + .weak CAN3_SCE_IRQHandler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s deleted file mode 100644 index 72833bf..0000000 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f769xx.s +++ /dev/null @@ -1,629 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f769xx.s - * @author MCD Application Team - * @version V1.1.0 - * @date 22-April-2016 - * @brief STM32F769xx Devices vector table for GCC based toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M7 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m7 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M7. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDMMC1_IRQHandler /* SDMMC1 */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word SAI2_IRQHandler /* SAI2 */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word CEC_IRQHandler /* HDMI_CEC */ - .word I2C4_EV_IRQHandler /* I2C4 Event */ - .word I2C4_ER_IRQHandler /* I2C4 Error */ - .word SPDIF_RX_IRQHandler /* SPDIF_RX */ - .word DSI_IRQHandler /* DSI */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter 0 global Interrupt */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter 1 global Interrupt */ - .word DFSDM1_FLT2_IRQHandler /* DFSDM1 Filter 2 global Interrupt */ - .word DFSDM1_FLT3_IRQHandler /* DFSDM1 Filter 3 global Interrupt */ - .word SDMMC2_IRQHandler /* SDMMC2 */ - .word CAN3_TX_IRQHandler /* CAN3 TX */ - .word CAN3_RX0_IRQHandler /* CAN3 RX0 */ - .word CAN3_RX1_IRQHandler /* CAN3 RX1 */ - .word CAN3_SCE_IRQHandler /* CAN3 SCE */ - .word JPEG_IRQHandler /* JPEG */ - .word MDIOS_IRQHandler /* MDIOS */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak I2C4_EV_IRQHandler - .thumb_set I2C4_EV_IRQHandler,Default_Handler - - .weak I2C4_ER_IRQHandler - .thumb_set I2C4_ER_IRQHandler,Default_Handler - - .weak SPDIF_RX_IRQHandler - .thumb_set SPDIF_RX_IRQHandler,Default_Handler - - .weak DSI_IRQHandler - .thumb_set DSI_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak DFSDM1_FLT2_IRQHandler - .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler - - .weak DFSDM1_FLT3_IRQHandler - .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler - - .weak SDMMC2_IRQHandler - .thumb_set SDMMC2_IRQHandler,Default_Handler - - .weak CAN3_TX_IRQHandler - .thumb_set CAN3_TX_IRQHandler,Default_Handler - - .weak CAN3_RX0_IRQHandler - .thumb_set CAN3_RX0_IRQHandler,Default_Handler - - .weak CAN3_RX1_IRQHandler - .thumb_set CAN3_RX1_IRQHandler,Default_Handler - - .weak CAN3_SCE_IRQHandler - .thumb_set CAN3_SCE_IRQHandler,Default_Handler - - .weak JPEG_IRQHandler - .thumb_set JPEG_IRQHandler,Default_Handler - - .weak MDIOS_IRQHandler - .thumb_set MDIOS_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.S new file mode 100644 index 0000000..be5c8a7 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.S @@ -0,0 +1,257 @@ +;/**************************************************************************//** +; * @file startup_efm32hg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32HG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 4: ADC0 Interrupt + DCD I2C0_IRQHandler ; 5: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt + DCD RTC_IRQHandler ; 12: RTC Interrupt + DCD CMU_IRQHandler ; 13: CMU Interrupt + DCD VCMP_IRQHandler ; 14: VCMP Interrupt + DCD MSC_IRQHandler ; 15: MSC Interrupt + DCD AES_IRQHandler ; 16: AES Interrupt + DCD USART0_RX_IRQHandler ; 17: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 18: USART0_TX Interrupt + DCD USB_IRQHandler ; 19: USB Interrupt + DCD TIMER2_IRQHandler ; 20: TIMER2 Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.s deleted file mode 100644 index be5c8a7..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.s +++ /dev/null @@ -1,257 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32hg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32HG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 4: ADC0 Interrupt - DCD I2C0_IRQHandler ; 5: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt - DCD RTC_IRQHandler ; 12: RTC Interrupt - DCD CMU_IRQHandler ; 13: CMU Interrupt - DCD VCMP_IRQHandler ; 14: VCMP Interrupt - DCD MSC_IRQHandler ; 15: MSC Interrupt - DCD AES_IRQHandler ; 16: AES Interrupt - DCD USART0_RX_IRQHandler ; 17: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 18: USART0_TX Interrupt - DCD USB_IRQHandler ; 19: USB Interrupt - DCD TIMER2_IRQHandler ; 20: TIMER2 Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - - END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.S new file mode 100644 index 0000000..3bcdab4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.S @@ -0,0 +1,386 @@ +;/**************************************************************************//** +; * @file startup_efm32lg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32LG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD USB_IRQHandler ; 5: USB Interrupt + DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 7: ADC0 Interrupt + DCD DAC0_IRQHandler ; 8: DAC0 Interrupt + DCD I2C0_IRQHandler ; 9: I2C0 Interrupt + DCD I2C1_IRQHandler ; 10: I2C1 Interrupt + DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt + DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt + DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt + DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt + DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt + DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt + DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt + DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt + DCD RTC_IRQHandler ; 30: RTC Interrupt + DCD BURTC_IRQHandler ; 31: BURTC Interrupt + DCD CMU_IRQHandler ; 32: CMU Interrupt + DCD VCMP_IRQHandler ; 33: VCMP Interrupt + DCD LCD_IRQHandler ; 34: LCD Interrupt + DCD MSC_IRQHandler ; 35: MSC Interrupt + DCD AES_IRQHandler ; 36: AES Interrupt + DCD EBI_IRQHandler ; 37: EBI Interrupt + DCD EMU_IRQHandler ; 38: EMU Interrupt + DCD 0 ; 39: Reserved Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK UART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_RX_IRQHandler + B UART1_RX_IRQHandler + + PUBWEAK UART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_TX_IRQHandler + B UART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK BURTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BURTC_IRQHandler + B BURTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK EBI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EBI_IRQHandler + B EBI_IRQHandler + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.s deleted file mode 100644 index 3bcdab4..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.s +++ /dev/null @@ -1,386 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32lg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32LG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt - DCD USB_IRQHandler ; 5: USB Interrupt - DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 7: ADC0 Interrupt - DCD DAC0_IRQHandler ; 8: DAC0 Interrupt - DCD I2C0_IRQHandler ; 9: I2C0 Interrupt - DCD I2C1_IRQHandler ; 10: I2C1 Interrupt - DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt - DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt - DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt - DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt - DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt - DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt - DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt - DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt - DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt - DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt - DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt - DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt - DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt - DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt - DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt - DCD RTC_IRQHandler ; 30: RTC Interrupt - DCD BURTC_IRQHandler ; 31: BURTC Interrupt - DCD CMU_IRQHandler ; 32: CMU Interrupt - DCD VCMP_IRQHandler ; 33: VCMP Interrupt - DCD LCD_IRQHandler ; 34: LCD Interrupt - DCD MSC_IRQHandler ; 35: MSC Interrupt - DCD AES_IRQHandler ; 36: AES Interrupt - DCD EBI_IRQHandler ; 37: EBI Interrupt - DCD EMU_IRQHandler ; 38: EMU Interrupt - DCD 0 ; 39: Reserved Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK DAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC0_IRQHandler - B DAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK UART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_RX_IRQHandler - B UART0_RX_IRQHandler - - PUBWEAK UART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_TX_IRQHandler - B UART0_TX_IRQHandler - - PUBWEAK UART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_RX_IRQHandler - B UART1_RX_IRQHandler - - PUBWEAK UART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_TX_IRQHandler - B UART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK LEUART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART1_IRQHandler - B LEUART1_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK BURTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BURTC_IRQHandler - B BURTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - PUBWEAK EBI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EBI_IRQHandler - B EBI_IRQHandler - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - - END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.S new file mode 100644 index 0000000..5405f7c --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.S @@ -0,0 +1,306 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File for +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00004000 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY, ALIGN=8 + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved + DCD 0 ; 5: Reserved + DCD 0 ; 6: Reserved + DCD 0 ; 7: Reserved + DCD 0 ; 8: Reserved + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved + DCD 0 ; 29: Reserved + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT EMU_IRQHandler [WEAK] + EXPORT WDOG0_IRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT LDMA_IRQHandler [WEAK] + EXPORT GPIO_EVEN_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT USART0_RX_IRQHandler [WEAK] + EXPORT USART0_TX_IRQHandler [WEAK] + EXPORT ACMP0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT IDAC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT GPIO_ODD_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT USART1_RX_IRQHandler [WEAK] + EXPORT USART1_TX_IRQHandler [WEAK] + EXPORT LEUART0_IRQHandler [WEAK] + EXPORT PCNT0_IRQHandler [WEAK] + EXPORT CMU_IRQHandler [WEAK] + EXPORT MSC_IRQHandler [WEAK] + EXPORT CRYPTO0_IRQHandler [WEAK] + EXPORT LETIMER0_IRQHandler [WEAK] + EXPORT RTCC_IRQHandler [WEAK] + EXPORT CRYOTIMER_IRQHandler [WEAK] + EXPORT FPUEH_IRQHandler [WEAK] + EXPORT SMU_IRQHandler [WEAK] + EXPORT WTIMER0_IRQHandler [WEAK] + EXPORT WTIMER1_IRQHandler [WEAK] + EXPORT PCNT1_IRQHandler [WEAK] + EXPORT PCNT2_IRQHandler [WEAK] + EXPORT USART2_RX_IRQHandler [WEAK] + EXPORT USART2_TX_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART3_RX_IRQHandler [WEAK] + EXPORT USART3_TX_IRQHandler [WEAK] + EXPORT VDAC0_IRQHandler [WEAK] + EXPORT CSEN_IRQHandler [WEAK] + EXPORT LESENSE_IRQHandler [WEAK] + EXPORT CRYPTO1_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + + +EMU_IRQHandler +WDOG0_IRQHandler +WDOG1_IRQHandler +LDMA_IRQHandler +GPIO_EVEN_IRQHandler +TIMER0_IRQHandler +USART0_RX_IRQHandler +USART0_TX_IRQHandler +ACMP0_IRQHandler +ADC0_IRQHandler +IDAC0_IRQHandler +I2C0_IRQHandler +GPIO_ODD_IRQHandler +TIMER1_IRQHandler +USART1_RX_IRQHandler +USART1_TX_IRQHandler +LEUART0_IRQHandler +PCNT0_IRQHandler +CMU_IRQHandler +MSC_IRQHandler +CRYPTO0_IRQHandler +LETIMER0_IRQHandler +RTCC_IRQHandler +CRYOTIMER_IRQHandler +FPUEH_IRQHandler +SMU_IRQHandler +WTIMER0_IRQHandler +WTIMER1_IRQHandler +PCNT1_IRQHandler +PCNT2_IRQHandler +USART2_RX_IRQHandler +USART2_TX_IRQHandler +I2C1_IRQHandler +USART3_RX_IRQHandler +USART3_TX_IRQHandler +VDAC0_IRQHandler +CSEN_IRQHandler +LESENSE_IRQHandler +CRYPTO1_IRQHandler +TRNG0_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s deleted file mode 100644 index 5405f7c..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s +++ /dev/null @@ -1,306 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32pg12b.s -; * @brief CMSIS Core Device Startup File for -; * Silicon Labs EFM32PG12B Device Series -; * @version 5.1.2 -; * @date 03. February 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF: __STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00001000 - ENDIF - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - IF :DEF: __HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00004000 - ENDIF - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY, ALIGN=8 - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD 0 ; 1: Reserved - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt - DCD 0 ; 4: Reserved - DCD 0 ; 5: Reserved - DCD 0 ; 6: Reserved - DCD 0 ; 7: Reserved - DCD 0 ; 8: Reserved - DCD LDMA_IRQHandler ; 9: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 15: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 17: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt - DCD CMU_IRQHandler ; 24: CMU Interrupt - DCD MSC_IRQHandler ; 25: MSC Interrupt - DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt - DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt - DCD 0 ; 28: Reserved - DCD 0 ; 29: Reserved - DCD RTCC_IRQHandler ; 30: RTCC Interrupt - DCD 0 ; 31: Reserved - DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt - DCD 0 ; 33: Reserved - DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt - DCD SMU_IRQHandler ; 35: SMU Interrupt - DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt - DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt - DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt - DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt - DCD I2C1_IRQHandler ; 42: I2C1 Interrupt - DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt - DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt - DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt - DCD CSEN_IRQHandler ; 46: CSEN Interrupt - DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt - DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt - DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt - DCD 0 ; 50: Reserved - -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT EMU_IRQHandler [WEAK] - EXPORT WDOG0_IRQHandler [WEAK] - EXPORT WDOG1_IRQHandler [WEAK] - EXPORT LDMA_IRQHandler [WEAK] - EXPORT GPIO_EVEN_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT USART0_RX_IRQHandler [WEAK] - EXPORT USART0_TX_IRQHandler [WEAK] - EXPORT ACMP0_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT IDAC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT GPIO_ODD_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT USART1_RX_IRQHandler [WEAK] - EXPORT USART1_TX_IRQHandler [WEAK] - EXPORT LEUART0_IRQHandler [WEAK] - EXPORT PCNT0_IRQHandler [WEAK] - EXPORT CMU_IRQHandler [WEAK] - EXPORT MSC_IRQHandler [WEAK] - EXPORT CRYPTO0_IRQHandler [WEAK] - EXPORT LETIMER0_IRQHandler [WEAK] - EXPORT RTCC_IRQHandler [WEAK] - EXPORT CRYOTIMER_IRQHandler [WEAK] - EXPORT FPUEH_IRQHandler [WEAK] - EXPORT SMU_IRQHandler [WEAK] - EXPORT WTIMER0_IRQHandler [WEAK] - EXPORT WTIMER1_IRQHandler [WEAK] - EXPORT PCNT1_IRQHandler [WEAK] - EXPORT PCNT2_IRQHandler [WEAK] - EXPORT USART2_RX_IRQHandler [WEAK] - EXPORT USART2_TX_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT USART3_RX_IRQHandler [WEAK] - EXPORT USART3_TX_IRQHandler [WEAK] - EXPORT VDAC0_IRQHandler [WEAK] - EXPORT CSEN_IRQHandler [WEAK] - EXPORT LESENSE_IRQHandler [WEAK] - EXPORT CRYPTO1_IRQHandler [WEAK] - EXPORT TRNG0_IRQHandler [WEAK] - - -EMU_IRQHandler -WDOG0_IRQHandler -WDOG1_IRQHandler -LDMA_IRQHandler -GPIO_EVEN_IRQHandler -TIMER0_IRQHandler -USART0_RX_IRQHandler -USART0_TX_IRQHandler -ACMP0_IRQHandler -ADC0_IRQHandler -IDAC0_IRQHandler -I2C0_IRQHandler -GPIO_ODD_IRQHandler -TIMER1_IRQHandler -USART1_RX_IRQHandler -USART1_TX_IRQHandler -LEUART0_IRQHandler -PCNT0_IRQHandler -CMU_IRQHandler -MSC_IRQHandler -CRYPTO0_IRQHandler -LETIMER0_IRQHandler -RTCC_IRQHandler -CRYOTIMER_IRQHandler -FPUEH_IRQHandler -SMU_IRQHandler -WTIMER0_IRQHandler -WTIMER1_IRQHandler -PCNT1_IRQHandler -PCNT2_IRQHandler -USART2_RX_IRQHandler -USART2_TX_IRQHandler -I2C1_IRQHandler -USART3_RX_IRQHandler -USART3_TX_IRQHandler -VDAC0_IRQHandler -CSEN_IRQHandler -LESENSE_IRQHandler -CRYPTO1_IRQHandler -TRNG0_IRQHandler - B . - ENDP - - ALIGN - -; User Initial Stack & Heap - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.S new file mode 100644 index 0000000..7a10da7 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.S @@ -0,0 +1,401 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved Interrupt + DCD 0 ; 5: Reserved Interrupt + DCD 0 ; 6: Reserved Interrupt + DCD 0 ; 7: Reserved Interrupt + DCD 0 ; 8: Reserved Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved Interrupt + DCD 0 ; 29: Reserved Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s deleted file mode 100644 index 7a10da7..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s +++ /dev/null @@ -1,401 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32pg12b.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32PG12B Device Series -; * @version 5.1.2 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD 0 ; 1: Reserved Interrupt - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt - DCD 0 ; 4: Reserved Interrupt - DCD 0 ; 5: Reserved Interrupt - DCD 0 ; 6: Reserved Interrupt - DCD 0 ; 7: Reserved Interrupt - DCD 0 ; 8: Reserved Interrupt - DCD LDMA_IRQHandler ; 9: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 15: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 17: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt - DCD CMU_IRQHandler ; 24: CMU Interrupt - DCD MSC_IRQHandler ; 25: MSC Interrupt - DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt - DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt - DCD 0 ; 28: Reserved Interrupt - DCD 0 ; 29: Reserved Interrupt - DCD RTCC_IRQHandler ; 30: RTCC Interrupt - DCD 0 ; 31: Reserved Interrupt - DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt - DCD 0 ; 33: Reserved Interrupt - DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt - DCD SMU_IRQHandler ; 35: SMU Interrupt - DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt - DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt - DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt - DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt - DCD I2C1_IRQHandler ; 42: I2C1 Interrupt - DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt - DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt - DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt - DCD CSEN_IRQHandler ; 46: CSEN Interrupt - DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt - DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt - DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt - DCD 0 ; 50: Reserved Interrupt - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK WDOG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG0_IRQHandler - B WDOG0_IRQHandler - - PUBWEAK WDOG1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG1_IRQHandler - B WDOG1_IRQHandler - - PUBWEAK LDMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LDMA_IRQHandler - B LDMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK IDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -IDAC0_IRQHandler - B IDAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK CRYPTO0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO0_IRQHandler - B CRYPTO0_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK RTCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTCC_IRQHandler - B RTCC_IRQHandler - - PUBWEAK CRYOTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYOTIMER_IRQHandler - B CRYOTIMER_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - PUBWEAK SMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SMU_IRQHandler - B SMU_IRQHandler - - PUBWEAK WTIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER0_IRQHandler - B WTIMER0_IRQHandler - - PUBWEAK WTIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER1_IRQHandler - B WTIMER1_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK USART3_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_RX_IRQHandler - B USART3_RX_IRQHandler - - PUBWEAK USART3_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_TX_IRQHandler - B USART3_TX_IRQHandler - - PUBWEAK VDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VDAC0_IRQHandler - B VDAC0_IRQHandler - - PUBWEAK CSEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CSEN_IRQHandler - B CSEN_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK CRYPTO1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO1_IRQHandler - B CRYPTO1_IRQHandler - - PUBWEAK TRNG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TRNG0_IRQHandler - B TRNG0_IRQHandler - - - END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.S new file mode 100644 index 0000000..c451cb4 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.S @@ -0,0 +1,391 @@ +;/**************************************************************************//** +; * @file startup_efm32wg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32WG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD USB_IRQHandler ; 5: USB Interrupt + DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 7: ADC0 Interrupt + DCD DAC0_IRQHandler ; 8: DAC0 Interrupt + DCD I2C0_IRQHandler ; 9: I2C0 Interrupt + DCD I2C1_IRQHandler ; 10: I2C1 Interrupt + DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt + DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt + DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt + DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt + DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt + DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt + DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt + DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt + DCD RTC_IRQHandler ; 30: RTC Interrupt + DCD BURTC_IRQHandler ; 31: BURTC Interrupt + DCD CMU_IRQHandler ; 32: CMU Interrupt + DCD VCMP_IRQHandler ; 33: VCMP Interrupt + DCD LCD_IRQHandler ; 34: LCD Interrupt + DCD MSC_IRQHandler ; 35: MSC Interrupt + DCD AES_IRQHandler ; 36: AES Interrupt + DCD EBI_IRQHandler ; 37: EBI Interrupt + DCD EMU_IRQHandler ; 38: EMU Interrupt + DCD FPUEH_IRQHandler ; 39: FPUEH Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK UART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_RX_IRQHandler + B UART1_RX_IRQHandler + + PUBWEAK UART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_TX_IRQHandler + B UART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK BURTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BURTC_IRQHandler + B BURTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK EBI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EBI_IRQHandler + B EBI_IRQHandler + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.s deleted file mode 100644 index c451cb4..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.s +++ /dev/null @@ -1,391 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32wg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32WG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt - DCD USB_IRQHandler ; 5: USB Interrupt - DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 7: ADC0 Interrupt - DCD DAC0_IRQHandler ; 8: DAC0 Interrupt - DCD I2C0_IRQHandler ; 9: I2C0 Interrupt - DCD I2C1_IRQHandler ; 10: I2C1 Interrupt - DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt - DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt - DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt - DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt - DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt - DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt - DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt - DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt - DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt - DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt - DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt - DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt - DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt - DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt - DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt - DCD RTC_IRQHandler ; 30: RTC Interrupt - DCD BURTC_IRQHandler ; 31: BURTC Interrupt - DCD CMU_IRQHandler ; 32: CMU Interrupt - DCD VCMP_IRQHandler ; 33: VCMP Interrupt - DCD LCD_IRQHandler ; 34: LCD Interrupt - DCD MSC_IRQHandler ; 35: MSC Interrupt - DCD AES_IRQHandler ; 36: AES Interrupt - DCD EBI_IRQHandler ; 37: EBI Interrupt - DCD EMU_IRQHandler ; 38: EMU Interrupt - DCD FPUEH_IRQHandler ; 39: FPUEH Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK DAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC0_IRQHandler - B DAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK UART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_RX_IRQHandler - B UART0_RX_IRQHandler - - PUBWEAK UART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_TX_IRQHandler - B UART0_TX_IRQHandler - - PUBWEAK UART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_RX_IRQHandler - B UART1_RX_IRQHandler - - PUBWEAK UART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_TX_IRQHandler - B UART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK LEUART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART1_IRQHandler - B LEUART1_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK BURTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BURTC_IRQHandler - B BURTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - PUBWEAK EBI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EBI_IRQHandler - B EBI_IRQHandler - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - - END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.S new file mode 100644 index 0000000..19098da --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.S @@ -0,0 +1,235 @@ +;/**************************************************************************//** +; * @file startup_efm32zg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32ZG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 4: ADC0 Interrupt + DCD I2C0_IRQHandler ; 5: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt + DCD RTC_IRQHandler ; 12: RTC Interrupt + DCD CMU_IRQHandler ; 13: CMU Interrupt + DCD VCMP_IRQHandler ; 14: VCMP Interrupt + DCD MSC_IRQHandler ; 15: MSC Interrupt + DCD AES_IRQHandler ; 16: AES Interrupt + DCD 0 ; 17: Reserved Interrupt + DCD 0 ; 18: Reserved Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.s deleted file mode 100644 index 19098da..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.s +++ /dev/null @@ -1,235 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32zg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32ZG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 4: ADC0 Interrupt - DCD I2C0_IRQHandler ; 5: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt - DCD RTC_IRQHandler ; 12: RTC Interrupt - DCD CMU_IRQHandler ; 13: CMU Interrupt - DCD VCMP_IRQHandler ; 14: VCMP Interrupt - DCD MSC_IRQHandler ; 15: MSC Interrupt - DCD AES_IRQHandler ; 16: AES Interrupt - DCD 0 ; 17: Reserved Interrupt - DCD 0 ; 18: Reserved Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - - END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.S new file mode 100644 index 0000000..aca5a91 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.S @@ -0,0 +1,354 @@ +;/**************************************************************************//** +; * @file startup_efr32mg1p.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFR32MG1P Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD FRC_IRQHandler ; 3: FRC Interrupt + DCD MODEM_IRQHandler ; 4: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 7: BUFC Interrupt + DCD LDMA_IRQHandler ; 8: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 14: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 16: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt + DCD CMU_IRQHandler ; 23: CMU Interrupt + DCD MSC_IRQHandler ; 24: MSC Interrupt + DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 27: AGC Interrupt + DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 29: RTCC Interrupt + DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FRC_PRI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_PRI_IRQHandler + B FRC_PRI_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK FRC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_IRQHandler + B FRC_IRQHandler + + PUBWEAK MODEM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MODEM_IRQHandler + B MODEM_IRQHandler + + PUBWEAK RAC_SEQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_SEQ_IRQHandler + B RAC_SEQ_IRQHandler + + PUBWEAK RAC_RSM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_RSM_IRQHandler + B RAC_RSM_IRQHandler + + PUBWEAK BUFC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BUFC_IRQHandler + B BUFC_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO_IRQHandler + B CRYPTO_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK AGC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AGC_IRQHandler + B AGC_IRQHandler + + PUBWEAK PROTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PROTIMER_IRQHandler + B PROTIMER_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK SYNTH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SYNTH_IRQHandler + B SYNTH_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK RFSENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RFSENSE_IRQHandler + B RFSENSE_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.s deleted file mode 100644 index aca5a91..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.s +++ /dev/null @@ -1,354 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efr32mg1p.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFR32MG1P Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD FRC_IRQHandler ; 3: FRC Interrupt - DCD MODEM_IRQHandler ; 4: MODEM Interrupt - DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt - DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt - DCD BUFC_IRQHandler ; 7: BUFC Interrupt - DCD LDMA_IRQHandler ; 8: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 14: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 16: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt - DCD CMU_IRQHandler ; 23: CMU Interrupt - DCD MSC_IRQHandler ; 24: MSC Interrupt - DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt - DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt - DCD AGC_IRQHandler ; 27: AGC Interrupt - DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt - DCD RTCC_IRQHandler ; 29: RTCC Interrupt - DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt - DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt - DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt - DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK FRC_PRI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_PRI_IRQHandler - B FRC_PRI_IRQHandler - - PUBWEAK WDOG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG0_IRQHandler - B WDOG0_IRQHandler - - PUBWEAK FRC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_IRQHandler - B FRC_IRQHandler - - PUBWEAK MODEM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MODEM_IRQHandler - B MODEM_IRQHandler - - PUBWEAK RAC_SEQ_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_SEQ_IRQHandler - B RAC_SEQ_IRQHandler - - PUBWEAK RAC_RSM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_RSM_IRQHandler - B RAC_RSM_IRQHandler - - PUBWEAK BUFC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BUFC_IRQHandler - B BUFC_IRQHandler - - PUBWEAK LDMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LDMA_IRQHandler - B LDMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK IDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -IDAC0_IRQHandler - B IDAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK CRYPTO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO_IRQHandler - B CRYPTO_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK AGC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AGC_IRQHandler - B AGC_IRQHandler - - PUBWEAK PROTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PROTIMER_IRQHandler - B PROTIMER_IRQHandler - - PUBWEAK RTCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTCC_IRQHandler - B RTCC_IRQHandler - - PUBWEAK SYNTH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SYNTH_IRQHandler - B SYNTH_IRQHandler - - PUBWEAK CRYOTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYOTIMER_IRQHandler - B CRYOTIMER_IRQHandler - - PUBWEAK RFSENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RFSENSE_IRQHandler - B RFSENSE_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - - END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.S b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.S new file mode 100644 index 0000000..2cb7255 --- /dev/null +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.S @@ -0,0 +1,451 @@ +;/**************************************************************************//** +; * @file startup_efr32mg12p.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFR32MG12P Device Series +; * @version 5.1.2 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD FRC_IRQHandler ; 4: FRC Interrupt + DCD MODEM_IRQHandler ; 5: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 8: BUFC Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 28: AGC Interrupt + DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FRC_PRI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_PRI_IRQHandler + B FRC_PRI_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + + PUBWEAK FRC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_IRQHandler + B FRC_IRQHandler + + PUBWEAK MODEM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MODEM_IRQHandler + B MODEM_IRQHandler + + PUBWEAK RAC_SEQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_SEQ_IRQHandler + B RAC_SEQ_IRQHandler + + PUBWEAK RAC_RSM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_RSM_IRQHandler + B RAC_RSM_IRQHandler + + PUBWEAK BUFC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BUFC_IRQHandler + B BUFC_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK AGC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AGC_IRQHandler + B AGC_IRQHandler + + PUBWEAK PROTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PROTIMER_IRQHandler + B PROTIMER_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK SYNTH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SYNTH_IRQHandler + B SYNTH_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK RFSENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RFSENSE_IRQHandler + B RFSENSE_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + + + END diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s deleted file mode 100644 index 2cb7255..0000000 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s +++ /dev/null @@ -1,451 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efr32mg12p.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFR32MG12P Device Series -; * @version 5.1.2 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt - DCD FRC_IRQHandler ; 4: FRC Interrupt - DCD MODEM_IRQHandler ; 5: MODEM Interrupt - DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt - DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt - DCD BUFC_IRQHandler ; 8: BUFC Interrupt - DCD LDMA_IRQHandler ; 9: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 15: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 17: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt - DCD CMU_IRQHandler ; 24: CMU Interrupt - DCD MSC_IRQHandler ; 25: MSC Interrupt - DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt - DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt - DCD AGC_IRQHandler ; 28: AGC Interrupt - DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt - DCD RTCC_IRQHandler ; 30: RTCC Interrupt - DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt - DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt - DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt - DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt - DCD SMU_IRQHandler ; 35: SMU Interrupt - DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt - DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt - DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt - DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt - DCD I2C1_IRQHandler ; 42: I2C1 Interrupt - DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt - DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt - DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt - DCD CSEN_IRQHandler ; 46: CSEN Interrupt - DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt - DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt - DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt - DCD 0 ; 50: Reserved Interrupt - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK FRC_PRI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_PRI_IRQHandler - B FRC_PRI_IRQHandler - - PUBWEAK WDOG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG0_IRQHandler - B WDOG0_IRQHandler - - PUBWEAK WDOG1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG1_IRQHandler - B WDOG1_IRQHandler - - PUBWEAK FRC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_IRQHandler - B FRC_IRQHandler - - PUBWEAK MODEM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MODEM_IRQHandler - B MODEM_IRQHandler - - PUBWEAK RAC_SEQ_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_SEQ_IRQHandler - B RAC_SEQ_IRQHandler - - PUBWEAK RAC_RSM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_RSM_IRQHandler - B RAC_RSM_IRQHandler - - PUBWEAK BUFC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BUFC_IRQHandler - B BUFC_IRQHandler - - PUBWEAK LDMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LDMA_IRQHandler - B LDMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK IDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -IDAC0_IRQHandler - B IDAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK CRYPTO0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO0_IRQHandler - B CRYPTO0_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK AGC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AGC_IRQHandler - B AGC_IRQHandler - - PUBWEAK PROTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PROTIMER_IRQHandler - B PROTIMER_IRQHandler - - PUBWEAK RTCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTCC_IRQHandler - B RTCC_IRQHandler - - PUBWEAK SYNTH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SYNTH_IRQHandler - B SYNTH_IRQHandler - - PUBWEAK CRYOTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYOTIMER_IRQHandler - B CRYOTIMER_IRQHandler - - PUBWEAK RFSENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RFSENSE_IRQHandler - B RFSENSE_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - PUBWEAK SMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SMU_IRQHandler - B SMU_IRQHandler - - PUBWEAK WTIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER0_IRQHandler - B WTIMER0_IRQHandler - - PUBWEAK WTIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER1_IRQHandler - B WTIMER1_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK USART3_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_RX_IRQHandler - B USART3_RX_IRQHandler - - PUBWEAK USART3_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_TX_IRQHandler - B USART3_TX_IRQHandler - - PUBWEAK VDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VDAC0_IRQHandler - B VDAC0_IRQHandler - - PUBWEAK CSEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CSEN_IRQHandler - B CSEN_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK CRYPTO1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO1_IRQHandler - B CRYPTO1_IRQHandler - - PUBWEAK TRNG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TRNG0_IRQHandler - B TRNG0_IRQHandler - - - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.S new file mode 100644 index 0000000..1b28c47 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.S @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright �� 2016 +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s deleted file mode 100644 index 1b28c47..0000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s +++ /dev/null @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright �� 2016 -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.S new file mode 100644 index 0000000..1b28c47 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.S @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright �� 2016 +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s deleted file mode 100644 index 1b28c47..0000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s +++ /dev/null @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright �� 2016 -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.S new file mode 100644 index 0000000..1b28c47 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.S @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright �� 2016 +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s deleted file mode 100644 index 1b28c47..0000000 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s +++ /dev/null @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright �� 2016 -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ��Software��), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ��AS IS��, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END diff --git a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.S b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.S new file mode 100644 index 0000000..2bc9ff7 --- /dev/null +++ b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.S @@ -0,0 +1,163 @@ +; mbed Microcontroller Library +; Copyright (c) 2016 u-blox. +;Licensed under the Apache License, Version 2.0 (the "License"); +;you may not use this file except in compliance with the License. +;You may obtain a copy of the License at +;http://www.apache.org/licenses/LICENSE-2.0 +;Unless required by applicable law or agreed to in writing, software +;distributed under the License is distributed on an "AS IS" BASIS, +;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;See the License for the specific language governing permissions and +;limitations under the License. + +; Description message + +__initial_sp EQU (0x01000000 + 0x5000 - 256) + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; External Interrupts + DCD IRQ0_RTC_Handler + DCD IRQ1_TMR0_Handler + DCD IRQ2_SECURITY_Handler + DCD IRQ3_PROTOCOL_Handler + DCD IRQ4_APPS_Handler + DCD IRQ5_GPIO_Handler + DCD IRQ6_DMA_Handler + DCD IRQ7_UART0_Handler + DCD IRQ8_UART1_Handler + DCD IRQ9_SSP0_Handler + DCD IRQ10_SSP1_Handler + DCD IRQ11_PWM0IN_Handler + DCD IRQ12_PWM0OUT_Handler + DCD IRQ13_PWM1IN_Handler + DCD IRQ14_PWM1OUT_Handler + DCD IRQ15_I2C_Handler + DCD IRQ16_LPUART_Handler + DCD IRQ17_CAP_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT IRQ0_RTC_Handler [WEAK] + EXPORT IRQ1_TMR0_Handler [WEAK] + EXPORT IRQ2_SECURITY_Handler [WEAK] + EXPORT IRQ3_PROTOCOL_Handler [WEAK] + EXPORT IRQ4_APPS_Handler [WEAK] + EXPORT IRQ5_GPIO_Handler [WEAK] + EXPORT IRQ6_DMA_Handler [WEAK] + EXPORT IRQ7_UART0_Handler [WEAK] + EXPORT IRQ8_UART1_Handler [WEAK] + EXPORT IRQ9_SSP0_Handler [WEAK] + EXPORT IRQ10_SSP1_Handler [WEAK] + EXPORT IRQ11_PWM0IN_Handler [WEAK] + EXPORT IRQ12_PWM0OUT_Handler [WEAK] + EXPORT IRQ13_PWM1IN_Handler [WEAK] + EXPORT IRQ14_PWM1OUT_Handler [WEAK] + EXPORT IRQ15_I2C_Handler [WEAK] + EXPORT IRQ16_LPUART_Handler [WEAK] + EXPORT IRQ17_CAP_Handler [WEAK] +IRQ0_RTC_Handler +IRQ1_TMR0_Handler +IRQ2_SECURITY_Handler +IRQ3_PROTOCOL_Handler +IRQ4_APPS_Handler +IRQ5_GPIO_Handler +IRQ6_DMA_Handler +IRQ7_UART0_Handler +IRQ8_UART1_Handler +IRQ9_SSP0_Handler +IRQ10_SSP1_Handler +IRQ11_PWM0IN_Handler +IRQ12_PWM0OUT_Handler +IRQ13_PWM1IN_Handler +IRQ14_PWM1OUT_Handler +IRQ15_I2C_Handler +IRQ16_LPUART_Handler +IRQ17_CAP_Handler + + B . + ENDP + ALIGN + END diff --git a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.s b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.s deleted file mode 100644 index 2bc9ff7..0000000 --- a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.s +++ /dev/null @@ -1,163 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2016 u-blox. -;Licensed under the Apache License, Version 2.0 (the "License"); -;you may not use this file except in compliance with the License. -;You may obtain a copy of the License at -;http://www.apache.org/licenses/LICENSE-2.0 -;Unless required by applicable law or agreed to in writing, software -;distributed under the License is distributed on an "AS IS" BASIS, -;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;See the License for the specific language governing permissions and -;limitations under the License. - -; Description message - -__initial_sp EQU (0x01000000 + 0x5000 - 256) - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; External Interrupts - DCD IRQ0_RTC_Handler - DCD IRQ1_TMR0_Handler - DCD IRQ2_SECURITY_Handler - DCD IRQ3_PROTOCOL_Handler - DCD IRQ4_APPS_Handler - DCD IRQ5_GPIO_Handler - DCD IRQ6_DMA_Handler - DCD IRQ7_UART0_Handler - DCD IRQ8_UART1_Handler - DCD IRQ9_SSP0_Handler - DCD IRQ10_SSP1_Handler - DCD IRQ11_PWM0IN_Handler - DCD IRQ12_PWM0OUT_Handler - DCD IRQ13_PWM1IN_Handler - DCD IRQ14_PWM1OUT_Handler - DCD IRQ15_I2C_Handler - DCD IRQ16_LPUART_Handler - DCD IRQ17_CAP_Handler - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT IRQ0_RTC_Handler [WEAK] - EXPORT IRQ1_TMR0_Handler [WEAK] - EXPORT IRQ2_SECURITY_Handler [WEAK] - EXPORT IRQ3_PROTOCOL_Handler [WEAK] - EXPORT IRQ4_APPS_Handler [WEAK] - EXPORT IRQ5_GPIO_Handler [WEAK] - EXPORT IRQ6_DMA_Handler [WEAK] - EXPORT IRQ7_UART0_Handler [WEAK] - EXPORT IRQ8_UART1_Handler [WEAK] - EXPORT IRQ9_SSP0_Handler [WEAK] - EXPORT IRQ10_SSP1_Handler [WEAK] - EXPORT IRQ11_PWM0IN_Handler [WEAK] - EXPORT IRQ12_PWM0OUT_Handler [WEAK] - EXPORT IRQ13_PWM1IN_Handler [WEAK] - EXPORT IRQ14_PWM1OUT_Handler [WEAK] - EXPORT IRQ15_I2C_Handler [WEAK] - EXPORT IRQ16_LPUART_Handler [WEAK] - EXPORT IRQ17_CAP_Handler [WEAK] -IRQ0_RTC_Handler -IRQ1_TMR0_Handler -IRQ2_SECURITY_Handler -IRQ3_PROTOCOL_Handler -IRQ4_APPS_Handler -IRQ5_GPIO_Handler -IRQ6_DMA_Handler -IRQ7_UART0_Handler -IRQ8_UART1_Handler -IRQ9_SSP0_Handler -IRQ10_SSP1_Handler -IRQ11_PWM0IN_Handler -IRQ12_PWM0OUT_Handler -IRQ13_PWM1IN_Handler -IRQ14_PWM1OUT_Handler -IRQ15_I2C_Handler -IRQ16_LPUART_Handler -IRQ17_CAP_Handler - - B . - ENDP - ALIGN - END diff --git a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.S b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.S new file mode 100644 index 0000000..0c69cc0 --- /dev/null +++ b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.S @@ -0,0 +1,202 @@ +; mbed Microcontroller Library +; Copyright (c) 2016 u-blox. +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; http://www.apache.org/licenses/LICENSE-2.0 +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; Description message + + MODULE ?cstartup + + ; Stack size default : 1024 + ; Heap size default : 2048 + + ; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + +; External Interrupts + DCD IRQ0_RTC_Handler + DCD IRQ1_TMR0_Handler + DCD IRQ2_SECURITY_Handler + DCD IRQ3_PROTOCOL_Handler + DCD IRQ4_APPS_Handler + DCD IRQ5_GPIO_Handler + DCD IRQ6_DMA_Handler + DCD IRQ7_UART0_Handler + DCD IRQ8_UART1_Handler + DCD IRQ9_SSP0_Handler + DCD IRQ10_SSP1_Handler + DCD IRQ11_PWM0IN_Handler + DCD IRQ12_PWM0OUT_Handler + DCD IRQ13_PWM1IN_Handler + DCD IRQ14_PWM1OUT_Handler + DCD IRQ15_I2C_Handler + DCD IRQ16_LPUART_Handler + DCD IRQ17_CAP_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + ; Dummy interrupt handlers + + PUBWEAK IRQ0_RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ0_RTC_Handler + B . + PUBWEAK IRQ1_TMR0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ1_TMR0_Handler + B . + PUBWEAK IRQ2_SECURITY_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ2_SECURITY_Handler + B . + PUBWEAK IRQ3_PROTOCOL_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ3_PROTOCOL_Handler + B . + PUBWEAK IRQ4_APPS_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ4_APPS_Handler + B . + PUBWEAK IRQ5_GPIO_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ5_GPIO_Handler + B . + PUBWEAK IRQ6_DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ6_DMA_Handler + B . + PUBWEAK IRQ7_UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ7_UART0_Handler + B . + PUBWEAK IRQ8_UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ8_UART1_Handler + B . + PUBWEAK IRQ9_SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ9_SSP0_Handler + B . + PUBWEAK IRQ10_SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ10_SSP1_Handler + B . + PUBWEAK IRQ11_PWM0IN_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ11_PWM0IN_Handler + B . + PUBWEAK IRQ12_PWM0OUT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ12_PWM0OUT_Handler + B . + PUBWEAK IRQ13_PWM1IN_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ13_PWM1IN_Handler + B . + PUBWEAK IRQ14_PWM1OUT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ14_PWM1OUT_Handler + B . + PUBWEAK IRQ15_I2C_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ15_I2C_Handler + B . + PUBWEAK IRQ16_LPUART_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ16_LPUART_Handler + B . + PUBWEAK IRQ17_CAP_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ17_CAP_Handler + + END diff --git a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.s b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.s deleted file mode 100644 index 0c69cc0..0000000 --- a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.s +++ /dev/null @@ -1,202 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2016 u-blox. -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; http://www.apache.org/licenses/LICENSE-2.0 -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - -; Description message - - MODULE ?cstartup - - ; Stack size default : 1024 - ; Heap size default : 2048 - - ; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - -; External Interrupts - DCD IRQ0_RTC_Handler - DCD IRQ1_TMR0_Handler - DCD IRQ2_SECURITY_Handler - DCD IRQ3_PROTOCOL_Handler - DCD IRQ4_APPS_Handler - DCD IRQ5_GPIO_Handler - DCD IRQ6_DMA_Handler - DCD IRQ7_UART0_Handler - DCD IRQ8_UART1_Handler - DCD IRQ9_SSP0_Handler - DCD IRQ10_SSP1_Handler - DCD IRQ11_PWM0IN_Handler - DCD IRQ12_PWM0OUT_Handler - DCD IRQ13_PWM1IN_Handler - DCD IRQ14_PWM1OUT_Handler - DCD IRQ15_I2C_Handler - DCD IRQ16_LPUART_Handler - DCD IRQ17_CAP_Handler - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - ; Dummy interrupt handlers - - PUBWEAK IRQ0_RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ0_RTC_Handler - B . - PUBWEAK IRQ1_TMR0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ1_TMR0_Handler - B . - PUBWEAK IRQ2_SECURITY_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ2_SECURITY_Handler - B . - PUBWEAK IRQ3_PROTOCOL_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ3_PROTOCOL_Handler - B . - PUBWEAK IRQ4_APPS_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ4_APPS_Handler - B . - PUBWEAK IRQ5_GPIO_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ5_GPIO_Handler - B . - PUBWEAK IRQ6_DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ6_DMA_Handler - B . - PUBWEAK IRQ7_UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ7_UART0_Handler - B . - PUBWEAK IRQ8_UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ8_UART1_Handler - B . - PUBWEAK IRQ9_SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ9_SSP0_Handler - B . - PUBWEAK IRQ10_SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ10_SSP1_Handler - B . - PUBWEAK IRQ11_PWM0IN_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ11_PWM0IN_Handler - B . - PUBWEAK IRQ12_PWM0OUT_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ12_PWM0OUT_Handler - B . - PUBWEAK IRQ13_PWM1IN_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ13_PWM1IN_Handler - B . - PUBWEAK IRQ14_PWM1OUT_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ14_PWM1OUT_Handler - B . - PUBWEAK IRQ15_I2C_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ15_I2C_Handler - B . - PUBWEAK IRQ16_LPUART_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ16_LPUART_Handler - B . - PUBWEAK IRQ17_CAP_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ17_CAP_Handler - - END