diff --git a/hal/tests/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h b/hal/tests/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h
index 3ecff9e..8ff82c2 100644
--- a/hal/tests/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h
+++ b/hal/tests/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h
@@ -46,6 +46,9 @@
 #undef QSPI_CMD_WRITE_DPI
 #undef QSPI_CMD_WRITE_QPI
 
+#elif defined(TARGET_MTS_DRAGONFLY_L496VG)
+#include "MT25Q_config.h"
+
 #elif defined(TARGET_NRF52840)
 #if TARGET_EP_AGORA
 #include "NORDIC/EP_AGORA/flash_config.h"
diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json
index 73ae742..6b03c00 100644
--- a/platform/mbed_lib.json
+++ b/platform/mbed_lib.json
@@ -164,7 +164,7 @@
         },
         "UNO_91H": {
             "stdio-baud-rate": 115200
-        }, 
+        },
         "DISCO_L475VG_IOT01A": {
             "crash-capture-enabled": true,
             "fatal-error-auto-reboot-enabled": true
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/CMakeLists.txt
index 2e1e4b7..4889083 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/CMakeLists.txt
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/CMakeLists.txt
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 add_subdirectory(TARGET_DISCO_L496AG EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_MTS_DRAGONFLY_L496VG EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_NUCLEO_L496ZG EXCLUDE_FROM_ALL)
 
 if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/CMakeLists.txt
new file mode 100644
index 0000000..1b0d6f3
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/CMakeLists.txt
@@ -0,0 +1,18 @@
+# Copyright (c) 2021 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+add_library(mbed-mts-dragonfly-l496vg INTERFACE)
+
+target_sources(mbed-mts-dragonfly-l496vg
+    INTERFACE
+        ONBOARD_QUECTEL_EG25.cpp
+        PeripheralPins.c
+        TargetInit.c
+)
+
+target_include_directories(mbed-mts-dragonfly-l496vg
+    INTERFACE
+        .
+)
+
+target_link_libraries(mbed-mts-dragonfly-l496vg INTERFACE mbed-stm32l496xg)
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.cpp b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.cpp
new file mode 100644
index 0000000..2f34b34
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.cpp
@@ -0,0 +1,222 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if MBED_CONF_NSAPI_PRESENT
+
+#include "QUECTEL_EC2X.h"
+#include "ONBOARD_QUECTEL_EG25.h"
+#include "gpio_api.h"
+#include "platform/mbed_thread.h"
+#include "PinNames.h"
+#include "drivers/BufferedSerial.h"
+#include "CellularLog.h"
+#include "mbed_wait_api.h"
+
+using namespace mbed;
+
+ONBOARD_QUECTEL_EG25::ONBOARD_QUECTEL_EG25(FileHandle *fh, PinName pwr, bool active_high, PinName rst) : QUECTEL_EC2X(fh, pwr, active_high, rst)
+{
+    initialized = 0;
+    ls = new DigitalOut(LS_LED);
+    net_status = new InterruptIn(NET_STATUS);
+}
+
+nsapi_error_t ONBOARD_QUECTEL_EG25::hard_power_on()
+{
+    onboard_modem_init();
+    return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t ONBOARD_QUECTEL_EG25::hard_power_off()
+{
+    onboard_modem_deinit();
+    return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t ONBOARD_QUECTEL_EG25::soft_power_on()
+{
+    // See base function description. This function is for power on but reset too.
+    onboard_modem_power_down();
+    onboard_modem_power_up();
+    return NSAPI_ERROR_OK;
+}
+
+nsapi_error_t ONBOARD_QUECTEL_EG25::soft_power_off()
+{
+    onboard_modem_power_down();
+    return NSAPI_ERROR_OK;
+}
+
+CellularDevice *CellularDevice::get_target_default_instance()
+{
+    static BufferedSerial serial(MDMTXD, MDMRXD, 115200);
+#if DEVICE_SERIAL_FC
+    if (MDMRTS != NC && MDMCTS != NC) {
+        tr_debug("Modem flow control: RTS %d CTS %d", MDMRTS, MDMCTS);
+        serial.set_flow_control(SerialBase::RTSCTS, MDMRTS, MDMCTS);
+    }
+#endif
+    static ONBOARD_QUECTEL_EG25 device(&serial, MDMPWRON, 0, MDMRST);
+    return &device;
+}
+
+void ONBOARD_QUECTEL_EG25::press_power_button(int time_us)
+{
+    gpio_t gpio;
+    gpio_init_inout(&gpio, MDMPWRON, PIN_OUTPUT, OpenDrainNoPull, 0);
+    wait_us(time_us);
+    gpio_init_inout(&gpio, MDMPWRON, PIN_INPUT, PullNone, 1);
+}
+
+void ONBOARD_QUECTEL_EG25::onboard_modem_init()
+{
+    // PWRKEY/RADIO_ONOFF = output open drain
+    // RADIO_PWR = Enables the regulator. High = on. Has pulldown on board.
+    // RADIO_RESET/MDMRST = Reset the radio. Open drain or float.
+    // RADIO_STATUS/STATUS = input with pull up. Gets driven low when radio is on.
+
+    gpio_t gpio;
+    // Enable radio power regulator and buffer, configure RESET_N and PWR_ON.
+    gpio_init_inout(&gpio, RADIO_PWR, PIN_OUTPUT, PushPullNoPull, 1);
+    gpio_init_inout(&gpio, BUF_EN, PIN_OUTPUT, OpenDrainNoPull, 0);
+    // MDMRST and MDMPWRON get driven low via open drain.
+    gpio_init_inout(&gpio, MDMRST, PIN_INPUT, PullNone, 1);
+    gpio_init_inout(&gpio, MDMPWRON, PIN_INPUT, PullNone, 1);
+    gpio_init_in_ex(&gpio, RADIO_STATUS, PullUp);
+    // Quectel hardware design guide recommends >= 30ms from powered until
+    //  PWRKEY(MDMPWRON) is pulled low.
+    wait_us(40000);
+    initialized = 1;
+}
+
+void ONBOARD_QUECTEL_EG25::onboard_modem_deinit()
+{
+    // Make sure to power down before removing power!
+    onboard_modem_power_down();
+    gpio_t gpio;
+
+    // Set all to inputs no pull. Let pull resistors do their thing. Allows
+    // for lowest power draw. Disable radio power regulator and buffer.
+    gpio_init_inout(&gpio, MDMRST, PIN_INPUT, PullNone, 1);
+    gpio_init_inout(&gpio, MDMPWRON, PIN_INPUT, PullNone, 1);
+    gpio_init_inout(&gpio, BUF_EN, PIN_INPUT, PullNone, 1);
+    gpio_init_inout(&gpio, RADIO_PWR, PIN_INPUT, PullNone, 0);
+    initialized = 0;
+}
+
+void ONBOARD_QUECTEL_EG25::link_status()
+{
+    ls->write(net_status->read());
+}
+
+void ONBOARD_QUECTEL_EG25::onboard_modem_power_up()
+{
+    // NET_STATUS = input. InterruptIn make LS LED follow.
+    // LS_LED = output. Follow NET_STATUS.
+    net_status->rise(callback(this,&ONBOARD_QUECTEL_EG25::link_status));
+    net_status->fall(callback(this,&ONBOARD_QUECTEL_EG25::link_status));
+
+    // Make sure the radio is initialized so it can be powered on.
+    if (!initialized){
+        onboard_modem_init();
+    }
+
+    gpio_t status;
+    gpio_init_in_ex(&status, RADIO_STATUS, PullUp);
+
+    int radio_off = gpio_read(&status);
+    // If radio is on, do nothing.
+    if (!radio_off) {
+        return;
+    }
+
+    // Activate PWRKEY at least 500ms to turn on.
+    press_power_button(550000);
+
+    // Wait 10s for status to go low before retrying.
+    uint8_t timeout = 10;
+    do {
+        thread_sleep_for(1000);
+        radio_off = gpio_read(&status);
+        if(!timeout--){
+            press_power_button(550000);
+            timeout = 10;
+        }
+    } while (radio_off);
+
+    _at.lock();
+
+    _at.set_at_timeout(15000);
+    _at.resp_start();
+    _at.set_stop_tag("RDY");
+    bool rdy = _at.consume_to_stop_tag();
+    _at.set_stop_tag(OK);
+
+    _at.unlock();
+    if (rdy) {
+        tr_debug("Radio outputted RDY");
+    } else {
+        tr_debug("Radio did not output RDY within 15s.");
+    }
+}
+
+void ONBOARD_QUECTEL_EG25::onboard_modem_power_down()
+{
+    gpio_t status;
+    gpio_init_in_ex(&status, RADIO_STATUS, PullUp);
+    // Need volatile so status check is not optimized out.
+    volatile int radio_off = gpio_read(&status);
+    // Do nothing if it's already off.
+    if (radio_off) {
+        return;
+    }
+
+    // Make sure the I/O are properly initialized.
+    if (!initialized){
+        onboard_modem_init();
+    }
+
+    do {
+        // Activate PWRKEY for at least 650ms to turn off.
+        press_power_button(680000);
+        // Wait 40s for status to go high before resetting.
+        uint8_t timeout = 40;
+        do {
+            thread_sleep_for(1000);
+            radio_off = gpio_read(&status);
+        } while (!radio_off && timeout);
+
+        if (radio_off) {
+            break;
+        }
+        else {
+            onboard_modem_reset();
+        }
+    }
+    while (!radio_off);
+}
+
+void ONBOARD_QUECTEL_EG25::onboard_modem_reset()
+{
+    gpio_t gpio;
+    gpio_init_inout(&gpio, MDMRST, PIN_OUTPUT, OpenDrainNoPull, 0);
+    thread_sleep_for(500);
+    gpio_init_inout(&gpio, MDMRST, PIN_INPUT, PullNone, 1);
+    thread_sleep_for(100);
+}
+
+#endif // MBED_CONF_NSAPI_PRESENT
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.h
new file mode 100644
index 0000000..7084bb9
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/ONBOARD_QUECTEL_EG25.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ONBOARD_QUECTEL_EG25_H
+#define ONBOARD_QUECTEL_EG25_H
+
+#include "QUECTEL_EC2X.h"
+
+namespace mbed {
+
+class ONBOARD_QUECTEL_EG25 : public QUECTEL_EC2X {
+public:
+    ONBOARD_QUECTEL_EG25(FileHandle *fh, PinName pwr, bool active_high, PinName rst);
+
+    virtual nsapi_error_t hard_power_on();
+    virtual nsapi_error_t hard_power_off();
+    virtual nsapi_error_t soft_power_on();
+    virtual nsapi_error_t soft_power_off();
+
+private:
+    uint8_t initialized;
+    DigitalOut* ls;
+    InterruptIn* net_status;
+    void link_status();
+    void press_power_button(int time_ms);
+    void onboard_modem_init();
+    void onboard_modem_deinit();
+    void onboard_modem_power_up();
+    void onboard_modem_power_down();
+    void onboard_modem_reset();
+};
+
+} // namespace mbed
+
+#endif // ONBOARD_QUECTEL_EG25_H
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PeripheralPins.c
new file mode 100644
index 0000000..a11e1b8
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PeripheralPins.c
@@ -0,0 +1,350 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
+//   See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+    {PA_0,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_0_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+    {PA_1,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+    {PA_1_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6
+    {PA_2,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+    {PA_2_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7
+    {PA_3,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PA_3_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
+    {PA_4,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PA_4_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+    {PA_5,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PA_5_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10
+    {PA_6,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {PA_6_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+    {PA_7,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+    {PA_7_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to QSPI_BK1_IO2 [MX25R6435FM2IL0_SIO2]
+    {PB_0,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {PB_0_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+    {PB_1,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+    {PB_1_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16
+    {PC_0,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+    {PC_0_ALT1,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1
+    {PC_1,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+    {PC_1_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2
+    {PC_1_ALT1,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2
+    {PC_2,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PC_2_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+    {PC_2_ALT1,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+    {PC_3,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+    {PC_3_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4
+    {PC_3_ALT1,  ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4
+    {PC_4,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+    {PC_4_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13
+    {PC_5,       ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+    {PC_5_ALT0,  ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VREF,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_VBAT,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+    {PA_4,       DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+    {PA_5,       DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2
+    {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+    {PB_4,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_7,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_7_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
+    {PB_9,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_14,      I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PC_1_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)},
+    {PC_9,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+    {PA_7,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_6,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_6_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
+    {PB_8,       I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10,      I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_10_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+    {PB_13,      I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_0,       I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PC_0_ALT0,  I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)},
+    {NC, NC, 0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker
+MBED_WEAK const PinMap PinMap_PWM[] = {
+    {PA_0,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+//  {PA_0,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
+    {PA_1,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+    {PA_1_ALT0,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+//  {PA_1,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
+    {PA_2,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+//  {PA_2,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
+    {PA_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+    {PA_3_ALT0,  PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+//  {PA_3,       PWM_5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
+    {PA_5,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+    {PA_5_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+    {PA_6,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+    {PA_6_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+    {PA_7,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PA_7_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+    {PA_7_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+    {PA_7_ALT2,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+    {PA_8,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+    {PA_9,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+    {PA_15,      PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+    {PB_0,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+    {PB_0_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+    {PB_0_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+    {PB_1,       PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {PB_1_ALT0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+    {PB_1_ALT1,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+    {PB_3,       PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+    {PB_4,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+    {PB_5,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+    {PB_6,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+    {PB_6_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
+    {PB_7,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+    {PB_7_ALT0,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N
+    {PB_8,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+    {PB_8_ALT0,  PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+    {PB_9,       PWM_4,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+    {PB_9_ALT0,  PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+    {PB_13,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+    {PB_15,      PWM_1,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {PB_15_ALT0, PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+    {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+    {PC_8,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+    {PC_8_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+    {PC_9,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+    {PC_9_ALT0,  PWM_8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+    {PE_6,       PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+    {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+    {PA_0,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_2_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_9,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PC_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_4,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_8,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+    {PA_1,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_3,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_15,      UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)},
+    {PB_7,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PC_0,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PD_9,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+    {PA_1,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_15,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_15_ALT0, UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PB_1,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_1_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_3,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PB_12,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PD_12,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+    {PA_0,       UART_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6,       UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_6_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_4,       UART_1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_5,       UART_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PB_7,       UART_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PB_13,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PD_11,      UART_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PB_5,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PB_5_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_15,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PC_1,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)},
+    {PD_4,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PB_4,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PB_4_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PC_2,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+    {PA_1,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PA_5,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PA_9,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)},
+    {PB_3,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PB_3_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_13,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PD_1,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PA_4_ALT0,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PA_15,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+    {PB_0,       SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+    {PB_9,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PB_12,      SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {PD_0,       SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+    {PB_5,       CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_CAN2)},
+    {PB_8,       CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_12,      CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)},
+    {PD_0,       CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+    {PB_6,       CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN2)},
+    {PB_9,       CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_13,      CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)},
+    {PD_1,       CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {NC, NC, 0}
+};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
+    {PB_1,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO0
+    {PE_12,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO0
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
+    {PB_0,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO1
+    {PE_13,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO1
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
+    {PA_7,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO2
+    {PE_14,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO2
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
+    {PA_6,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO3
+    {PE_15,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_IO3
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+    {PA_3,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_CLK
+    {PE_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_CLK
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+    {PA_2,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_NCS
+    {PE_11,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},  // QUADSPI_BK1_NCS
+    {NC, NC, 0}
+};
+
+//*** USBDEVICE ***
+
+MBED_WEAK const PinMap PinMap_USB_FS[] = {
+//  {PA_8,      USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
+    {PA_9,      USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS
+//  {PA_13,     USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE
+//  {PA_14,     USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
+//  {PC_9,      USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_NOE
+    {NC, NC, 0}
+};
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PinNames.h
new file mode 100644
index 0000000..521eae6
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/PinNames.h
@@ -0,0 +1,368 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+/* MBED TARGET LIST: MTS_DRAGONFLY_L471QG */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+} ALTx;
+
+typedef enum {
+    PA_0       = 0x00,
+    PA_0_ALT0  = PA_0  | ALT0, // same pin used for alternate HW
+    PA_1       = 0x01,
+    PA_1_ALT0  = PA_1  | ALT0, // same pin used for alternate HW
+    PA_2       = 0x02,
+    PA_2_ALT0  = PA_2  | ALT0, // same pin used for alternate HW
+    PA_3       = 0x03,
+    PA_3_ALT0  = PA_3  | ALT0, // same pin used for alternate HW
+    PA_4       = 0x04,
+    PA_4_ALT0  = PA_4  | ALT0, // same pin used for alternate HW
+    PA_5       = 0x05,
+    PA_5_ALT0  = PA_5  | ALT0, // same pin used for alternate HW
+    PA_6       = 0x06,
+    PA_6_ALT0  = PA_6  | ALT0, // same pin used for alternate HW
+    PA_7       = 0x07,
+    PA_7_ALT0  = PA_7  | ALT0, // same pin used for alternate HW
+    PA_7_ALT1  = PA_7  | ALT1, // same pin used for alternate HW
+    PA_7_ALT2  = PA_7  | ALT2, // same pin used for alternate HW
+    PA_8       = 0x08,
+    PA_9       = 0x09,
+    PA_10      = 0x0A,
+    PA_11      = 0x0B,
+    PA_12      = 0x0C,
+    PA_13      = 0x0D,
+    PA_14      = 0x0E,
+    PA_15      = 0x0F,
+    PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW
+
+    PB_0       = 0x10,
+    PB_0_ALT0  = PB_0  | ALT0, // same pin used for alternate HW
+    PB_0_ALT1  = PB_0  | ALT1, // same pin used for alternate HW
+    PB_1       = 0x11,
+    PB_1_ALT0  = PB_1  | ALT0, // same pin used for alternate HW
+    PB_1_ALT1  = PB_1  | ALT1, // same pin used for alternate HW
+    PB_2       = 0x12,
+    PB_3       = 0x13,
+    PB_3_ALT0  = PB_3  | ALT0, // same pin used for alternate HW
+    PB_4       = 0x14,
+    PB_4_ALT0  = PB_4  | ALT0, // same pin used for alternate HW
+    PB_5       = 0x15,
+    PB_5_ALT0  = PB_5  | ALT0, // same pin used for alternate HW
+    PB_6       = 0x16,
+    PB_6_ALT0  = PB_6  | ALT0, // same pin used for alternate HW
+    PB_7       = 0x17,
+    PB_7_ALT0  = PB_7  | ALT0, // same pin used for alternate HW
+    PB_8       = 0x18,
+    PB_8_ALT0  = PB_8  | ALT0, // same pin used for alternate HW
+    PB_9       = 0x19,
+    PB_9_ALT0  = PB_9  | ALT0, // same pin used for alternate HW
+    PB_10      = 0x1A,
+    PB_10_ALT0 = PB_10 | ALT0, // same pin used for alternate HW
+    PB_11      = 0x1B,
+    PB_11_ALT0 = PB_11 | ALT0, // same pin used for alternate HW
+    PB_12      = 0x1C,
+    PB_13      = 0x1D,
+    PB_13_ALT0 = PB_13 | ALT0, // same pin used for alternate HW
+    PB_14      = 0x1E,
+    PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW
+    PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW
+    PB_15      = 0x1F,
+    PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW
+    PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW
+
+    PC_0       = 0x20,
+    PC_0_ALT0  = PC_0  | ALT0, // same pin used for alternate HW
+    PC_0_ALT1  = PC_0  | ALT1, // same pin used for alternate HW
+    PC_1       = 0x21,
+    PC_1_ALT0  = PC_1  | ALT0, // same pin used for alternate HW
+    PC_1_ALT1  = PC_1  | ALT1, // same pin used for alternate HW
+    PC_2       = 0x22,
+    PC_2_ALT0  = PC_2  | ALT0, // same pin used for alternate HW
+    PC_2_ALT1  = PC_2  | ALT1, // same pin used for alternate HW
+    PC_3       = 0x23,
+    PC_3_ALT0  = PC_3  | ALT0, // same pin used for alternate HW
+    PC_3_ALT1  = PC_3  | ALT1, // same pin used for alternate HW
+    PC_4       = 0x24,
+    PC_4_ALT0  = PC_4  | ALT0, // same pin used for alternate HW
+    PC_5       = 0x25,
+    PC_5_ALT0  = PC_5  | ALT0, // same pin used for alternate HW
+    PC_6       = 0x26,
+    PC_6_ALT0  = PC_6  | ALT0, // same pin used for alternate HW
+    PC_7       = 0x27,
+    PC_7_ALT0  = PC_7  | ALT0, // same pin used for alternate HW
+    PC_8       = 0x28,
+    PC_8_ALT0  = PC_8  | ALT0, // same pin used for alternate HW
+    PC_9       = 0x29,
+    PC_9_ALT0  = PC_9  | ALT0, // same pin used for alternate HW
+    PC_10      = 0x2A,
+    PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW
+    PC_11      = 0x2B,
+    PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_0 = 0x30,
+    PD_1 = 0x31,
+    PD_2 = 0x32,
+    PD_3 = 0x33,
+    PD_4 = 0x34,
+    PD_5 = 0x35,
+    PD_6 = 0x36,
+    PD_7 = 0x37,
+    PD_8 = 0x38,
+    PD_9 = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0 = 0x40,
+    PE_1 = 0x41,
+    PE_2 = 0x42,
+    PE_3 = 0x43,
+    PE_4 = 0x44,
+    PE_5 = 0x45,
+    PE_6 = 0x46,
+    PE_7 = 0x47,
+    PE_8 = 0x48,
+    PE_9 = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,
+
+    PH_0 = 0x70,
+    PH_1 = 0x71,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+#ifdef TARGET_FF_ARDUINO_UNO
+    ARDUINO_UNO_A0  = PC_2,
+    ARDUINO_UNO_A1  = PC_0,
+    ARDUINO_UNO_A2  = PC_4,
+    ARDUINO_UNO_A3  = PB_0,
+    ARDUINO_UNO_A4  = PC_1,
+    ARDUINO_UNO_A5  = PC_9,
+    ARDUINO_UNO_D0  = PA_3,
+    ARDUINO_UNO_D1  = PA_2,
+    ARDUINO_UNO_D2  = PB_15,
+    ARDUINO_UNO_D3  = PA_0,
+    ARDUINO_UNO_D4  = PA_7,
+    ARDUINO_UNO_D5  = PA_9,
+    ARDUINO_UNO_D6  = PA_1,
+    ARDUINO_UNO_D7  = PA_8,
+    ARDUINO_UNO_D8  = PB_1,
+    ARDUINO_UNO_D9  = PB_13,
+    ARDUINO_UNO_D10 = PC_8,
+    ARDUINO_UNO_D11 = PB_5,
+    ARDUINO_UNO_D12 = PA_6,
+    ARDUINO_UNO_D13 = PA_5,
+    ARDUINO_UNO_D14 = PB_9,
+    ARDUINO_UNO_D15 = PB_8,
+#endif
+
+    // 40 pin
+    IO_00 = ARDUINO_UNO_D1,
+    IO_01 = ARDUINO_UNO_D4,
+    IO_02 = ARDUINO_UNO_D8,
+    IO_03 = ARDUINO_UNO_D6,
+    IO_04 = ARDUINO_UNO_D11,
+    IO_05 = ARDUINO_UNO_D13,
+    IO_06 = ARDUINO_UNO_D15,
+    IO_07 = ARDUINO_UNO_D2,
+    IO_08 = ARDUINO_UNO_A0,
+    IO_09 = ARDUINO_UNO_A3,
+    IO_10 = ARDUINO_UNO_A1,
+    IO_11 = ARDUINO_UNO_A4,
+    IO_12 = ARDUINO_UNO_A2,
+    IO_13 = ARDUINO_UNO_D9,
+    IO_14 = ARDUINO_UNO_A5,
+    IO_15 = ARDUINO_UNO_D14,
+    IO_16 = ARDUINO_UNO_D12,
+    IO_17 = ARDUINO_UNO_D10,
+    IO_18 = ARDUINO_UNO_D3,
+    IO_19 = ARDUINO_UNO_D5,
+    IO_20 = ARDUINO_UNO_D7,
+    IO_21 = ARDUINO_UNO_D0,
+
+    // 40 pin USB debug port
+    CONSOLE_TX = PB_6,
+    CONSOLE_RX = PB_7,
+
+    // UARTS to external I/O
+    UART2_TX = ARDUINO_UNO_D1,
+    UART2_RX = ARDUINO_UNO_D0,
+    UART2_RTS = ARDUINO_UNO_D6,
+    UART2_CTS = ARDUINO_UNO_D3,
+    UART2_DSR = ARDUINO_UNO_D5,
+    UART2_DTR = ARDUINO_UNO_D7,
+    UART2_DCD = ARDUINO_UNO_D4,
+    UART2_RI = ARDUINO_UNO_D8,
+
+    UART1_TX = PB_6,
+    UART1_RX = PB_7,
+    UART1_RTS = PB_3,
+    UART1_CTS = PB_4,
+
+    // 40 pin JTAG/SWD
+    J_TCK = PA_14,	// a.k.a. SWCLK
+    J_TDI = PA_15,
+    J_RST = PB_4,
+    J_TDO = PB_3,	// a.k.a. SWO
+    J_TMS = PA_13,	// a.k.a. SWDIO
+
+    // Exteranl serial port
+    SERIAL_TX  = ARDUINO_UNO_D1,
+    SERIAL_RX  = ARDUINO_UNO_D0,
+    SERIAL_RTS = ARDUINO_UNO_D6,
+    SERIAL_CTS = ARDUINO_UNO_D3,
+    SERIAL_DCD = ARDUINO_UNO_D4,
+    SERIAL_DSR = ARDUINO_UNO_D5,
+    SERIAL_DTR = ARDUINO_UNO_D7,
+    SERIAL_RI  = ARDUINO_UNO_D8,
+
+    // SPI1 and SPI2 are available on Arduino pins
+    SPI1_MOSI = ARDUINO_UNO_D11,
+    SPI1_MISO = ARDUINO_UNO_D12,
+    SPI1_SCK  = ARDUINO_UNO_D13,
+    SPI2_MOSI = ARDUINO_UNO_D2,
+    SPI2_MISO = ARDUINO_UNO_A0,
+    SPI2_SCK  = ARDUINO_UNO_D9,
+
+    // QuadSPI connects to flash part
+    QSPI_FLASH1_SCK = PE_10,
+    QSPI_FLASH1_CSN = PE_11,
+    QSPI_FLASH1_IO0 = PE_12,
+    QSPI_FLASH1_IO1 = PE_13,
+    QSPI_FLASH1_IO2 = PE_14,
+    QSPI_FLASH1_IO3 = PE_15,
+
+    // I2C1 and I2C3 are available on Arduino pins
+    I2C1_SCL = ARDUINO_UNO_D15,
+    I2C1_SDA = ARDUINO_UNO_D14,
+    I2C2_SCL = PB_10,
+    I2C2_SDA = PB_14,
+    I2C3_SCL = ARDUINO_UNO_A1,
+    I2C3_SDA = ARDUINO_UNO_A4,
+
+    // Cellular radio (note: no DSR signal)
+    RADIO_PWR   = PE_0,
+    RADIO_RESET = PE_1,
+    RADIO_TX    = PD_8,
+    RADIO_RX    = PD_9,
+    RADIO_RI    = PD_10,
+    RADIO_CTS   = PD_11,
+    RADIO_RTS   = PD_12,
+    RADIO_DTR   = PD_13,
+    RADIO_DCD   = PD_14,
+    RADIO_ONOFF = PE_2,
+    RADIO_STATUS = PE_3,
+    AP_READY    = PE_4,
+    RADIO_WAKEUP = PE_5,
+    NET_MODE    = PD_3,
+    NET_STATUS  = PD_2,
+    VRAD_ALERT  = PB_2,
+    MON_1V8     = PC_5,
+    RADIO_VDD_EXT = MON_1V8,
+
+    MDMPWRON = RADIO_ONOFF, // 3G_ONOFF DragonFly Design Guide, Page No. 16
+    MDMRST = RADIO_RESET,
+    MDMTXD   = RADIO_TX, // Transmit Data
+    MDMRXD   = RADIO_RX, // Receive Data
+    MDMRTS   = RADIO_RTS, // Request to Send
+    MDMCTS   = RADIO_CTS, // Clear to Send
+    MDMDCD   = RADIO_DCD, // Data Carrier Detect
+    MDMDTR   = RADIO_DTR, // Data Terminal Ready
+    MDMRI    = RADIO_RI, // Ring Indicator
+
+    // Power control for level shifter and SPI flash. Low powers on.
+    BUF_EN	= PD_15,
+    VMEM_EN	= PE_7,
+
+    // Voltage measuring
+    VCC_IN_MEAS_EN = PE_8,
+    VCC_IN_MEAS = PC_3,
+
+    INPUT_POWER = PC_7,
+
+    // GNSS/GPS
+    GPS_ANT_PWR_EN = PE_9,
+
+    // Wake up from Standby/Shutdown options are PA0 & PA2.
+    WAKEUP  = ARDUINO_UNO_D3,
+    // Wake up build Options
+    STM_WKUP = PC_13,
+
+    // CAN
+    CAN_TX = ARDUINO_UNO_D14,
+    CAN_RX = ARDUINO_UNO_D15,
+    // build option
+    CAN1_TX = PD_1,
+    CAN1_RX = PD_0,
+    CAN2_RX = PB_12,
+    CAN2_TX = ARDUINO_UNO_D9,
+
+    LS_LED = PE_6,
+
+    // Not connected
+    NC = (int) 0xFFFFFFFF
+} PinName;
+
+// Standardized LED and button names
+#define LED1  PA_0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/TargetInit.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/TargetInit.c
new file mode 100644
index 0000000..73ed3d3
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_MTS_DRAGONFLY_L496VG/TargetInit.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ *
+ * Copyright (c) 2015-2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include "stm32l4xx.h"
+
+void TargetBSP_Init(void)
+{
+    /* Enable the flash memory so greentea tests for QuadSPI work. */
+    /* The application can set it high to disable and save power. */
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    GPIO_InitTypeDef  GPIO_InitStruct;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+    GPIO_InitStruct.Pin = GPIO_PIN_7;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+    HAL_GPIO_WritePin(GPIOE, GPIO_PIN_7, GPIO_PIN_RESET);
+}
diff --git a/targets/targets.json b/targets/targets.json
index f45b0de..d26e94f 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -3955,6 +3955,25 @@
             "0828"
         ]
     },
+    "MTS_DRAGONFLY_L496VG": {
+        "inherits": [
+            "MCU_STM32L496xG"
+        ],
+        "supported_form_factors": [
+            "ARDUINO_UNO"
+        ],
+        "components_add": [
+            "QSPIF"
+        ],
+        "device_has_add": [
+            "USBDEVICE",
+            "QSPI"
+        ],
+        "detect_code": [
+            "0313"
+        ],
+        "device_name": "STM32L496VGTx"
+    },
     "MCU_STM32L4R5xI": {
         "inherits": [
             "MCU_STM32L4"