diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h
index e367c19..9d46287 100644
--- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h
+++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h
@@ -112,6 +112,18 @@
sub r0, r0, #32
bx lr
}
+#elif (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
+__STATIC_INLINE __attribute__((naked)) uint32_t __get_PSP (void) {
+ __ASM volatile (
+ ".syntax unified\n\t"
+ ".arm\n\t"
+ "sub sp,sp,#4\n\t"
+ "stm sp,{sp}^\n\t"
+ "pop {r0}\n\t"
+ "sub r0,r0,#32\n\t"
+ "bx lr\n\t"
+ );
+}
#else
#ifdef __ICCARM__
__arm
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h
deleted file mode 100644
index d10ed67..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/mem_RZ_A1LU.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**************************************************************************//**
- * @file mem_RZ_A1LU.h
- * @brief Memory base and size definitions (used in scatter file)
- * @version V1.00
- * @date 10 Mar 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __MEM_RZ_A1LU_H
-#define __MEM_RZ_A1LU_H
-
-/*----------------------------------------------------------------------------
- User Stack & Heap size definition
- *----------------------------------------------------------------------------*/
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- ROM Configuration ------------------------------------
-//
-// ROM Configuration
-// ROM Base Address <0x0-0xFFFFFFFF:8>
-// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
-//
- *----------------------------------------------------------------------------*/
-
-/*--------------------- RAM Configuration -----------------------------------
- *----------------------------------------------------------------------------*/
-#define __RAM_BASE 0x20000000
-#define __RAM_SIZE 0x00300000
-#define __NC_RAM_SIZE 0x00100000
-#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
-#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
-
-#define __UND_STACK_SIZE 0x00000100
-#define __SVC_STACK_SIZE 0x00008000
-#define __ABT_STACK_SIZE 0x00000100
-#define __FIQ_STACK_SIZE 0x00000100
-#define __IRQ_STACK_SIZE 0x0000F000
-#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
-
-/*----------------------------------------------------------------------------*/
-
-/*--------------------- TTB Configuration ------------------------------------
-//
-// TTB Configuration
-// TTB Base Address <0x0-0xFFFFFFFF:8>
-// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
-//
- *----------------------------------------------------------------------------*/
-#define __TTB_BASE 0x20000000
-#define __TTB_SIZE 0x00004000
-
-#endif /* __MEM_RZ_A1H_H */
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.S
new file mode 100644
index 0000000..b12d54d
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.S
@@ -0,0 +1,151 @@
+;/******************************************************************************
+; * @file startup_RZ_A1H.S
+; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+__UND_STACK_SIZE EQU 0x00000100
+__SVC_STACK_SIZE EQU 0x00008000
+__ABT_STACK_SIZE EQU 0x00000100
+__FIQ_STACK_SIZE EQU 0x00000100
+__IRQ_STACK_SIZE EQU 0x0000F000
+
+USR_MODE EQU 0x10 ; User mode
+FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode
+IRQ_MODE EQU 0x12 ; Interrupt Request mode
+SVC_MODE EQU 0x13 ; Supervisor mode
+ABT_MODE EQU 0x17 ; Abort mode
+UND_MODE EQU 0x1B ; Undefined Instruction mode
+SYS_MODE EQU 0x1F ; System mode
+
+
+ PRESERVE8
+ ARM
+
+ AREA RESET, CODE, READONLY
+
+Vectors PROC
+ EXPORT Vectors
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+ ENDP
+
+
+
+ AREA |.text|, CODE, READONLY
+
+Reset_Handler PROC
+ EXPORT Reset_Handler
+ IMPORT SystemInit
+ IMPORT __main
+
+
+ ; Mask interrupts
+ CPSID if
+
+ ; Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ ; Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register
+ ISB
+
+ ; Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register
+
+ ; Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ ; Setup Stack for each exceptional mode
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ ;Enter Undefined Instruction Mode and set its Stack Pointer
+ CPS #UND_MODE
+ MOV SP, R0
+ SUB R0, R0, #__UND_STACK_SIZE
+
+ ; Enter Abort Mode and set its Stack Pointer
+ CPS #ABT_MODE
+ MOV SP, R0
+ SUB R0, R0, #__ABT_STACK_SIZE
+
+ ; Enter FIQ Mode and set its Stack Pointer
+ CPS #FIQ_MODE
+ MOV SP, R0
+ SUB R0, R0, #__FIQ_STACK_SIZE
+
+ ; Enter IRQ Mode and set its Stack Pointer
+ CPS #IRQ_MODE
+ MOV SP, R0
+ SUB R0, R0, #__IRQ_STACK_SIZE
+
+ ; Enter Supervisor Mode and set its Stack Pointer
+ CPS #SVC_MODE
+ MOV SP, R0
+ SUB R0, R0, #__SVC_STACK_SIZE
+
+ ; Enter System Mode to complete initialization and enter kernel
+ CPS #SYS_MODE
+ MOV SP, R0
+
+ ; Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ ; Unmask interrupts
+ CPSIE if
+
+ ; Call __main
+ IMPORT __main
+ BL __main
+
+ ENDP
+
+ END
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c
deleted file mode 100644
index 0d8f589..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/startup_RZ_A1LU.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
- * @file startup_RZ_A1LU.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
- * @version V1.00
- * @date 10 Mar 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "MBRZA1LU.h"
-#include "mem_RZ_A1LU.h"
-
-/*----------------------------------------------------------------------------
- Definitions
- *----------------------------------------------------------------------------*/
-#define USR_MODE 0x10 // User mode
-#define FIQ_MODE 0x11 // Fast Interrupt Request mode
-#define IRQ_MODE 0x12 // Interrupt Request mode
-#define SVC_MODE 0x13 // Supervisor mode
-#define ABT_MODE 0x17 // Abort mode
-#define UND_MODE 0x1B // Undefined Instruction mode
-#define SYS_MODE 0x1F // System mode
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Vectors (void) __attribute__ ((section("RESET")));
-void Reset_Handler(void);
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector Table
- *----------------------------------------------------------------------------*/
-__ASM void Vectors(void) {
- IMPORT Undef_Handler
- IMPORT SVC_Handler
- IMPORT PAbt_Handler
- IMPORT DAbt_Handler
- IMPORT IRQ_Handler
- IMPORT FIQ_Handler
- LDR PC, =Reset_Handler
- LDR PC, =Undef_Handler
- LDR PC, =SVC_Handler
- LDR PC, =PAbt_Handler
- LDR PC, =DAbt_Handler
- NOP
- LDR PC, =IRQ_Handler
- LDR PC, =FIQ_Handler
-}
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-__ASM void Reset_Handler(void) {
-
- // Mask interrupts
- CPSID if
-
- // Put any cores other than 0 to sleep
- MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
- ANDS R0, R0, #3
-goToSleep
- WFINE
- BNE goToSleep
-
- // Reset SCTLR Settings
- MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
- BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
- BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
- BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
- BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
- BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
- MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
- ISB
-
- // Configure ACTLR
- MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
- ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
- MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
-
- // Set Vector Base Address Register (VBAR) to point to this application's vector table
- LDR R0, =Vectors
- MCR p15, 0, R0, c12, c0, 0
-
- // Setup Stack for each exceptional mode
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
- LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
-
- //Enter Undefined Instruction Mode and set its Stack Pointer
- CPS #UND_MODE
- MOV SP, R0
- SUB R0, R0, #__UND_STACK_SIZE
-
- // Enter Abort Mode and set its Stack Pointer
- CPS #ABT_MODE
- MOV SP, R0
- SUB R0, R0, #__ABT_STACK_SIZE
-
- // Enter FIQ Mode and set its Stack Pointer
- CPS #FIQ_MODE
- MOV SP, R0
- SUB R0, R0, #__FIQ_STACK_SIZE
-
- // Enter IRQ Mode and set its Stack Pointer
- CPS #IRQ_MODE
- MOV SP, R0
- SUB R0, R0, #__IRQ_STACK_SIZE
-
- // Enter Supervisor Mode and set its Stack Pointer
- CPS #SVC_MODE
- MOV SP, R0
- SUB R0, R0, #__SVC_STACK_SIZE
-
- // Enter System Mode to complete initialization and enter kernel
- CPS #SYS_MODE
- MOV SP, R0
-
- // Call SystemInit
- IMPORT SystemInit
- BL SystemInit
-
- // Unmask interrupts
- CPSIE if
-
- // Call __main
- IMPORT __main
- BL __main
-}
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.S
new file mode 100644
index 0000000..7bfaa35
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.S
@@ -0,0 +1,91 @@
+;/*
+; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project: CMSIS-RTOS RTX
+; * Title: Cortex-A Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+MODE_SVC EQU 0x13
+
+ PRESERVE8
+ THUMB
+
+ AREA |.text|, CODE, READONLY
+
+IRQ_Handler PROC
+ EXPORT IRQ_Handler [WEAK]
+
+ IMPORT IRQ_GetActiveIRQ
+ IMPORT IRQ_GetHandler
+ IMPORT IRQ_EndOfInterrupt
+
+ SUB LR, LR, #4 ; Pre-adjust LR
+ SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
+ CPS #MODE_SVC ; Change to SVC mode
+ PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
+
+ MOV R3, SP ; Move SP into R3
+ AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
+ SUB SP, SP, R3 ; Adjust stack
+ PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
+
+ BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
+ MOV R4, R0 ; Move interrupt ID to R4
+
+ BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
+ CMP R0, #0 ; Check if handler address is 0
+ BEQ IRQ_End ; If 0, end interrupt and return
+
+ CPSIE i ; Re-enable interrupts
+ BLX R0 ; Call IRQ handler
+ CPSID i ; Disable interrupts
+
+IRQ_End
+ MOV R0, R4 ; Move interrupt ID to R0
+ BLX IRQ_EndOfInterrupt ; Signal end of interrupt
+
+ POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
+ ADD SP, SP, R3 ; Unadjust stack
+
+ POP {R0-R3, R12, LR} ; Restore stacked APCS registers
+ RFEFD SP! ; Return from IRQ handler
+
+ ENDP
+
+
+Default_Handler PROC
+ EXPORT Undef_Handler [WEAK]
+ EXPORT SVC_Handler [WEAK]
+ EXPORT PAbt_Handler [WEAK]
+ EXPORT DAbt_Handler [WEAK]
+ EXPORT FIQ_Handler [WEAK]
+
+Undef_Handler
+SVC_Handler
+PAbt_Handler
+DAbt_Handler
+FIQ_Handler
+
+ B .
+
+ ENDP
+
+ END
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.c
deleted file mode 100644
index 5557af1..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/TOOLCHAIN_ARM_STD/weak_handler.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * Project: CMSIS-RTOS RTX
- * Title: Cortex-A Exception handlers
- *
- * -----------------------------------------------------------------------------
- */
-
-#include "core_ca.h"
-
-#define MODE_SVC 0x13
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/*----------------------------------------------------------------------------
- Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
- while(1);
-}
-
-/*----------------------------------------------------------------------------
- Default IRQ Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-__WEAK __ASM void IRQ_Handler(void) {
- IMPORT IRQ_GetActiveIRQ
- IMPORT IRQ_GetHandler
- IMPORT IRQ_EndOfInterrupt
-
- SUB LR, LR, #4 // Pre-adjust LR
- SRSFD SP!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack
- CPS #MODE_SVC // Change to SVC mode
- PUSH {R0-R3, R12, LR} // Save APCS corruptible registers
-
- MOV R3, SP // Move SP into R3
- AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment
- SUB SP, SP, R3 // Adjust stack
- PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4)
-
- BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0
- MOV R4, R0 // Move interrupt ID to R4
-
- BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID
- CMP R0, #0 // Check if handler address is 0
- BEQ IRQ_End // If 0, end interrupt and return
-
- CPSIE i // Re-enable interrupts
- BLX R0 // Call IRQ handler
- CPSID i // Disable interrupts
-
-IRQ_End
- MOV R0, R4 // Move interrupt ID to R0
- BLX IRQ_EndOfInterrupt // Signal end of interrupt
-
- POP {R3, R4} // Restore stack adjustment(R3) and user data(R4)
- ADD SP, SP, R3 // Unadjust stack
-
- POP {R0-R3, R12, LR} // Restore stacked APCS registers
- RFEFD SP! // Return from IRQ handler
-}
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c
index 6d25278..94f2c51 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mbed_sf_boot.c
@@ -38,12 +38,12 @@
#if defined (__CC_ARM)
#pragma arm section rodata = "BOOT_LOADER"
const char boot_loader[] __attribute__((used)) =
-
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+const char boot_loader[] __attribute__ ((section("BOOT_LOADER"), used)) =
#elif defined (__ICCARM__)
__root const char boot_loader[] @ 0x18000000 =
#else
const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) =
-
#endif
{
0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c
index 6c3cd9f..93aa695 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/mmu_RZ_A1LU.c
@@ -116,7 +116,7 @@
extern uint32_t Image$$TTB$$ZI$$Base;
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#elif defined( __ICCARM__ )
#else
extern uint32_t Image$$RW_DATA_NC$$Base;
@@ -127,7 +127,7 @@
extern uint32_t Image$$RO_DATA$$Limit;
extern uint32_t Image$$RW_DATA$$Limit;
extern uint32_t Image$$RW_IRAM1$$Limit;
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#else
extern uint32_t Image$$RW_DATA_NC$$Limit;
extern uint32_t Image$$ZI_DATA_NC$$Limit;
@@ -145,7 +145,7 @@
#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#else
#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
@@ -250,7 +250,7 @@
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#elif defined ( __ICCARM__ )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h
deleted file mode 100644
index e7ddd4f..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_RZ_A1H.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**************************************************************************//**
- * @file mem_RZ_A1H.h
- * @brief Memory base and size definitions (used in scatter file)
- * @version V1.00
- * @date 10 Mar 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __MEM_RZ_A1H_H
-#define __MEM_RZ_A1H_H
-
-/*----------------------------------------------------------------------------
- User Stack & Heap size definition
- *----------------------------------------------------------------------------*/
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- ROM Configuration ------------------------------------
-//
-// ROM Configuration
-// ROM Base Address <0x0-0xFFFFFFFF:8>
-// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
-//
- *----------------------------------------------------------------------------*/
-
-/*--------------------- RAM Configuration -----------------------------------
- *----------------------------------------------------------------------------*/
-#define __RAM_BASE 0x20000000
-#define __RAM_SIZE 0x00A00000
-#define __NC_RAM_SIZE 0x00100000
-#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
-#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
-
-#define __UND_STACK_SIZE 0x00000100
-#define __SVC_STACK_SIZE 0x00008000
-#define __ABT_STACK_SIZE 0x00000100
-#define __FIQ_STACK_SIZE 0x00000100
-#define __IRQ_STACK_SIZE 0x0000F000
-#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
-
-/*----------------------------------------------------------------------------*/
-
-/*--------------------- TTB Configuration ------------------------------------
-//
-// TTB Configuration
-// TTB Base Address <0x0-0xFFFFFFFF:8>
-// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
-//
- *----------------------------------------------------------------------------*/
-#define __TTB_BASE 0x20000000
-#define __TTB_SIZE 0x00004000
-
-#endif /* __MEM_RZ_A1H_H */
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.S
new file mode 100644
index 0000000..b12d54d
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.S
@@ -0,0 +1,151 @@
+;/******************************************************************************
+; * @file startup_RZ_A1H.S
+; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+__UND_STACK_SIZE EQU 0x00000100
+__SVC_STACK_SIZE EQU 0x00008000
+__ABT_STACK_SIZE EQU 0x00000100
+__FIQ_STACK_SIZE EQU 0x00000100
+__IRQ_STACK_SIZE EQU 0x0000F000
+
+USR_MODE EQU 0x10 ; User mode
+FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode
+IRQ_MODE EQU 0x12 ; Interrupt Request mode
+SVC_MODE EQU 0x13 ; Supervisor mode
+ABT_MODE EQU 0x17 ; Abort mode
+UND_MODE EQU 0x1B ; Undefined Instruction mode
+SYS_MODE EQU 0x1F ; System mode
+
+
+ PRESERVE8
+ ARM
+
+ AREA RESET, CODE, READONLY
+
+Vectors PROC
+ EXPORT Vectors
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+ ENDP
+
+
+
+ AREA |.text|, CODE, READONLY
+
+Reset_Handler PROC
+ EXPORT Reset_Handler
+ IMPORT SystemInit
+ IMPORT __main
+
+
+ ; Mask interrupts
+ CPSID if
+
+ ; Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ ; Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register
+ ISB
+
+ ; Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register
+
+ ; Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ ; Setup Stack for each exceptional mode
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ ;Enter Undefined Instruction Mode and set its Stack Pointer
+ CPS #UND_MODE
+ MOV SP, R0
+ SUB R0, R0, #__UND_STACK_SIZE
+
+ ; Enter Abort Mode and set its Stack Pointer
+ CPS #ABT_MODE
+ MOV SP, R0
+ SUB R0, R0, #__ABT_STACK_SIZE
+
+ ; Enter FIQ Mode and set its Stack Pointer
+ CPS #FIQ_MODE
+ MOV SP, R0
+ SUB R0, R0, #__FIQ_STACK_SIZE
+
+ ; Enter IRQ Mode and set its Stack Pointer
+ CPS #IRQ_MODE
+ MOV SP, R0
+ SUB R0, R0, #__IRQ_STACK_SIZE
+
+ ; Enter Supervisor Mode and set its Stack Pointer
+ CPS #SVC_MODE
+ MOV SP, R0
+ SUB R0, R0, #__SVC_STACK_SIZE
+
+ ; Enter System Mode to complete initialization and enter kernel
+ CPS #SYS_MODE
+ MOV SP, R0
+
+ ; Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ ; Unmask interrupts
+ CPSIE if
+
+ ; Call __main
+ IMPORT __main
+ BL __main
+
+ ENDP
+
+ END
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c
deleted file mode 100644
index 6e522d8..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_RZ_A1H.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
- * @file startup_RZ_A1H_H.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
- * @version V1.00
- * @date 10 Mar 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "MBRZA1H.h"
-#include "mem_RZ_A1H.h"
-
-/*----------------------------------------------------------------------------
- Definitions
- *----------------------------------------------------------------------------*/
-#define USR_MODE 0x10 // User mode
-#define FIQ_MODE 0x11 // Fast Interrupt Request mode
-#define IRQ_MODE 0x12 // Interrupt Request mode
-#define SVC_MODE 0x13 // Supervisor mode
-#define ABT_MODE 0x17 // Abort mode
-#define UND_MODE 0x1B // Undefined Instruction mode
-#define SYS_MODE 0x1F // System mode
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Vectors (void) __attribute__ ((section("RESET")));
-void Reset_Handler(void);
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector Table
- *----------------------------------------------------------------------------*/
-__ASM void Vectors(void) {
- IMPORT Undef_Handler
- IMPORT SVC_Handler
- IMPORT PAbt_Handler
- IMPORT DAbt_Handler
- IMPORT IRQ_Handler
- IMPORT FIQ_Handler
- LDR PC, =Reset_Handler
- LDR PC, =Undef_Handler
- LDR PC, =SVC_Handler
- LDR PC, =PAbt_Handler
- LDR PC, =DAbt_Handler
- NOP
- LDR PC, =IRQ_Handler
- LDR PC, =FIQ_Handler
-}
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-__ASM void Reset_Handler(void) {
-
- // Mask interrupts
- CPSID if
-
- // Put any cores other than 0 to sleep
- MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
- ANDS R0, R0, #3
-goToSleep
- WFINE
- BNE goToSleep
-
- // Reset SCTLR Settings
- MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
- BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
- BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
- BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
- BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
- BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
- MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
- ISB
-
- // Configure ACTLR
- MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
- ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
- MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
-
- // Set Vector Base Address Register (VBAR) to point to this application's vector table
- LDR R0, =Vectors
- MCR p15, 0, R0, c12, c0, 0
-
- // Setup Stack for each exceptional mode
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
- LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
-
- //Enter Undefined Instruction Mode and set its Stack Pointer
- CPS #UND_MODE
- MOV SP, R0
- SUB R0, R0, #__UND_STACK_SIZE
-
- // Enter Abort Mode and set its Stack Pointer
- CPS #ABT_MODE
- MOV SP, R0
- SUB R0, R0, #__ABT_STACK_SIZE
-
- // Enter FIQ Mode and set its Stack Pointer
- CPS #FIQ_MODE
- MOV SP, R0
- SUB R0, R0, #__FIQ_STACK_SIZE
-
- // Enter IRQ Mode and set its Stack Pointer
- CPS #IRQ_MODE
- MOV SP, R0
- SUB R0, R0, #__IRQ_STACK_SIZE
-
- // Enter Supervisor Mode and set its Stack Pointer
- CPS #SVC_MODE
- MOV SP, R0
- SUB R0, R0, #__SVC_STACK_SIZE
-
- // Enter System Mode to complete initialization and enter kernel
- CPS #SYS_MODE
- MOV SP, R0
-
- // Call SystemInit
- IMPORT SystemInit
- BL SystemInit
-
- // Unmask interrupts
- CPSIE if
-
- // Call __main
- IMPORT __main
- BL __main
-}
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S
new file mode 100644
index 0000000..7bfaa35
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S
@@ -0,0 +1,91 @@
+;/*
+; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project: CMSIS-RTOS RTX
+; * Title: Cortex-A Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+MODE_SVC EQU 0x13
+
+ PRESERVE8
+ THUMB
+
+ AREA |.text|, CODE, READONLY
+
+IRQ_Handler PROC
+ EXPORT IRQ_Handler [WEAK]
+
+ IMPORT IRQ_GetActiveIRQ
+ IMPORT IRQ_GetHandler
+ IMPORT IRQ_EndOfInterrupt
+
+ SUB LR, LR, #4 ; Pre-adjust LR
+ SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
+ CPS #MODE_SVC ; Change to SVC mode
+ PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
+
+ MOV R3, SP ; Move SP into R3
+ AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
+ SUB SP, SP, R3 ; Adjust stack
+ PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
+
+ BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
+ MOV R4, R0 ; Move interrupt ID to R4
+
+ BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
+ CMP R0, #0 ; Check if handler address is 0
+ BEQ IRQ_End ; If 0, end interrupt and return
+
+ CPSIE i ; Re-enable interrupts
+ BLX R0 ; Call IRQ handler
+ CPSID i ; Disable interrupts
+
+IRQ_End
+ MOV R0, R4 ; Move interrupt ID to R0
+ BLX IRQ_EndOfInterrupt ; Signal end of interrupt
+
+ POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
+ ADD SP, SP, R3 ; Unadjust stack
+
+ POP {R0-R3, R12, LR} ; Restore stacked APCS registers
+ RFEFD SP! ; Return from IRQ handler
+
+ ENDP
+
+
+Default_Handler PROC
+ EXPORT Undef_Handler [WEAK]
+ EXPORT SVC_Handler [WEAK]
+ EXPORT PAbt_Handler [WEAK]
+ EXPORT DAbt_Handler [WEAK]
+ EXPORT FIQ_Handler [WEAK]
+
+Undef_Handler
+SVC_Handler
+PAbt_Handler
+DAbt_Handler
+FIQ_Handler
+
+ B .
+
+ ENDP
+
+ END
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.c
deleted file mode 100644
index 5557af1..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * -----------------------------------------------------------------------------
- *
- * Project: CMSIS-RTOS RTX
- * Title: Cortex-A Exception handlers
- *
- * -----------------------------------------------------------------------------
- */
-
-#include "core_ca.h"
-
-#define MODE_SVC 0x13
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/*----------------------------------------------------------------------------
- Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
- while(1);
-}
-
-/*----------------------------------------------------------------------------
- Default IRQ Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-__WEAK __ASM void IRQ_Handler(void) {
- IMPORT IRQ_GetActiveIRQ
- IMPORT IRQ_GetHandler
- IMPORT IRQ_EndOfInterrupt
-
- SUB LR, LR, #4 // Pre-adjust LR
- SRSFD SP!, #MODE_SVC // Save LR_irq and SPSR_irq on to the SVC stack
- CPS #MODE_SVC // Change to SVC mode
- PUSH {R0-R3, R12, LR} // Save APCS corruptible registers
-
- MOV R3, SP // Move SP into R3
- AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment
- SUB SP, SP, R3 // Adjust stack
- PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4)
-
- BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0
- MOV R4, R0 // Move interrupt ID to R4
-
- BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID
- CMP R0, #0 // Check if handler address is 0
- BEQ IRQ_End // If 0, end interrupt and return
-
- CPSIE i // Re-enable interrupts
- BLX R0 // Call IRQ handler
- CPSID i // Disable interrupts
-
-IRQ_End
- MOV R0, R4 // Move interrupt ID to R0
- BLX IRQ_EndOfInterrupt // Signal end of interrupt
-
- POP {R3, R4} // Restore stack adjustment(R3) and user data(R4)
- ADD SP, SP, R3 // Unadjust stack
-
- POP {R0-R3, R12, LR} // Restore stacked APCS registers
- RFEFD SP! // Return from IRQ handler
-}
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c
index bc50ddf..a020644 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mbed_sf_boot.c
@@ -38,12 +38,12 @@
#if defined (__CC_ARM)
#pragma arm section rodata = "BOOT_LOADER"
const char boot_loader[] __attribute__((used)) =
-
+#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+const char boot_loader[] __attribute__ ((section("BOOT_LOADER"), used)) =
#elif defined (__ICCARM__)
__root const char boot_loader[] @ 0x18000000 =
#else
const char boot_loader[] __attribute__ ((section(".boot_loader"), used)) =
-
#endif
{
0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c
index b1a5825..46f7217 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/mmu_RZ_A1H.c
@@ -116,7 +116,7 @@
extern uint32_t Image$$TTB$$ZI$$Base;
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#elif defined( __ICCARM__ )
#else
extern uint32_t Image$$RW_DATA_NC$$Base;
@@ -127,7 +127,7 @@
extern uint32_t Image$$RO_DATA$$Limit;
extern uint32_t Image$$RW_DATA$$Limit;
extern uint32_t Image$$RW_IRAM1$$Limit;
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#else
extern uint32_t Image$$RW_DATA_NC$$Limit;
extern uint32_t Image$$ZI_DATA_NC$$Limit;
@@ -145,7 +145,7 @@
#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
#endif
-#if defined( __CC_ARM )
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
#else
#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
@@ -251,7 +251,7 @@
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#elif defined ( __ICCARM__ )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h
deleted file mode 100644
index 63feb75..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**************************************************************************//**
- * @file mem_VK_RZ_A1H.h
- * @brief Memory base and size definitions (used in scatter file)
- * @version V1.00
- * @date 10 Mar 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __MEM_VK_RZ_A1H_H
-#define __MEM_VK_RZ_A1H_H
-
-/*----------------------------------------------------------------------------
- User Stack & Heap size definition
- *----------------------------------------------------------------------------*/
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- ROM Configuration ------------------------------------
-//
-// ROM Configuration
-// ROM Base Address <0x0-0xFFFFFFFF:8>
-// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
-//
- *----------------------------------------------------------------------------*/
-#ifdef RUN_FROM_SDRAM
- #define __ROM_BASE 0x08000000
- #define __ROM_SIZE 0x02000000
- #define __VECTOR_BASE 0x08000000
- #define __DATA_BASE +0 ALIGN 0x100000
-#elif defined (RUN_FROM_SRAM)
- #define __ROM_BASE 0x200A0000
- #define __ROM_SIZE 0x00960000
- #define __VECTOR_BASE 0x200A0000
- #define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS
-#else
- #define __ROM_BASE 0x18020000
- #define __ROM_SIZE 0x01FE0000
- #define __VECTOR_BASE 0x18020000
- #define __DATA_BASE 0x20020000
-#endif
-
-/*--------------------- RAM Configuration -----------------------------------
- *----------------------------------------------------------------------------*/
-#ifdef RUN_FROM_SDRAM
-#define __RAM_BASE 0x08000000
-#define __RAM_SIZE 0x02000000
-#define __NC_RAM_SIZE 0x00200000
-#else
-#define __RAM_BASE 0x20000000
-#define __RAM_SIZE 0x00A00000
-#define __NC_RAM_SIZE 0x00100000
-#endif
-#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
-#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
-
-#define __UND_STACK_SIZE 0x00000100
-#define __SVC_STACK_SIZE 0x00008000
-#define __ABT_STACK_SIZE 0x00000100
-#define __FIQ_STACK_SIZE 0x00000100
-#define __IRQ_STACK_SIZE 0x0000F000
-#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
-
-/*----------------------------------------------------------------------------*/
-
-/*--------------------- TTB Configuration ------------------------------------
-//
-// TTB Configuration
-// TTB Base Address <0x0-0xFFFFFFFF:8>
-// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
-//
- *----------------------------------------------------------------------------*/
-#define __TTB_BASE 0x20000000
-#define __TTB_SIZE 0x00004000
-
-#endif /* __MEM_VK_RZ_A1H_H */
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S
new file mode 100644
index 0000000..b12d54d
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S
@@ -0,0 +1,151 @@
+;/******************************************************************************
+; * @file startup_RZ_A1H.S
+; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+__UND_STACK_SIZE EQU 0x00000100
+__SVC_STACK_SIZE EQU 0x00008000
+__ABT_STACK_SIZE EQU 0x00000100
+__FIQ_STACK_SIZE EQU 0x00000100
+__IRQ_STACK_SIZE EQU 0x0000F000
+
+USR_MODE EQU 0x10 ; User mode
+FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode
+IRQ_MODE EQU 0x12 ; Interrupt Request mode
+SVC_MODE EQU 0x13 ; Supervisor mode
+ABT_MODE EQU 0x17 ; Abort mode
+UND_MODE EQU 0x1B ; Undefined Instruction mode
+SYS_MODE EQU 0x1F ; System mode
+
+
+ PRESERVE8
+ ARM
+
+ AREA RESET, CODE, READONLY
+
+Vectors PROC
+ EXPORT Vectors
+ IMPORT Undef_Handler
+ IMPORT SVC_Handler
+ IMPORT PAbt_Handler
+ IMPORT DAbt_Handler
+ IMPORT IRQ_Handler
+ IMPORT FIQ_Handler
+
+ LDR PC, =Reset_Handler
+ LDR PC, =Undef_Handler
+ LDR PC, =SVC_Handler
+ LDR PC, =PAbt_Handler
+ LDR PC, =DAbt_Handler
+ NOP
+ LDR PC, =IRQ_Handler
+ LDR PC, =FIQ_Handler
+
+ ENDP
+
+
+
+ AREA |.text|, CODE, READONLY
+
+Reset_Handler PROC
+ EXPORT Reset_Handler
+ IMPORT SystemInit
+ IMPORT __main
+
+
+ ; Mask interrupts
+ CPSID if
+
+ ; Put any cores other than 0 to sleep
+ MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR
+ ANDS R0, R0, #3
+goToSleep
+ WFINE
+ BNE goToSleep
+
+ ; Reset SCTLR Settings
+ MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register
+ BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache
+ BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache
+ BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU
+ BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction
+ BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs
+ MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register
+ ISB
+
+ ; Configure ACTLR
+ MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register
+ ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1)
+ MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register
+
+ ; Set Vector Base Address Register (VBAR) to point to this application's vector table
+ LDR R0, =Vectors
+ MCR p15, 0, R0, c12, c0, 0
+
+ ; Setup Stack for each exceptional mode
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ ;Enter Undefined Instruction Mode and set its Stack Pointer
+ CPS #UND_MODE
+ MOV SP, R0
+ SUB R0, R0, #__UND_STACK_SIZE
+
+ ; Enter Abort Mode and set its Stack Pointer
+ CPS #ABT_MODE
+ MOV SP, R0
+ SUB R0, R0, #__ABT_STACK_SIZE
+
+ ; Enter FIQ Mode and set its Stack Pointer
+ CPS #FIQ_MODE
+ MOV SP, R0
+ SUB R0, R0, #__FIQ_STACK_SIZE
+
+ ; Enter IRQ Mode and set its Stack Pointer
+ CPS #IRQ_MODE
+ MOV SP, R0
+ SUB R0, R0, #__IRQ_STACK_SIZE
+
+ ; Enter Supervisor Mode and set its Stack Pointer
+ CPS #SVC_MODE
+ MOV SP, R0
+ SUB R0, R0, #__SVC_STACK_SIZE
+
+ ; Enter System Mode to complete initialization and enter kernel
+ CPS #SYS_MODE
+ MOV SP, R0
+
+ ; Call SystemInit
+ IMPORT SystemInit
+ BL SystemInit
+
+ ; Unmask interrupts
+ CPSIE if
+
+ ; Call __main
+ IMPORT __main
+ BL __main
+
+ ENDP
+
+ END
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c
deleted file mode 100644
index a83d7a2..0000000
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/******************************************************************************
- * @file startup_RZ_A1H_H.c
- * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
- * @version V1.00
- * @date 10 Mar 2017
- *
- * @note
- *
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "VKRZA1H.h"
-#include "mem_VK_RZ_A1H.h"
-
-/*----------------------------------------------------------------------------
- Definitions
- *----------------------------------------------------------------------------*/
-#define USR_MODE 0x10 // User mode
-#define FIQ_MODE 0x11 // Fast Interrupt Request mode
-#define IRQ_MODE 0x12 // Interrupt Request mode
-#define SVC_MODE 0x13 // Supervisor mode
-#define ABT_MODE 0x17 // Abort mode
-#define UND_MODE 0x1B // Undefined Instruction mode
-#define SYS_MODE 0x1F // System mode
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Vectors (void) __attribute__ ((section("RESET")));
-void Reset_Handler(void);
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector Table
- *----------------------------------------------------------------------------*/
-__ASM void Vectors(void) {
- IMPORT Undef_Handler
- IMPORT SVC_Handler
- IMPORT PAbt_Handler
- IMPORT DAbt_Handler
- IMPORT IRQ_Handler
- IMPORT FIQ_Handler
- LDR PC, =Reset_Handler
- LDR PC, =Undef_Handler
- LDR PC, =SVC_Handler
- LDR PC, =PAbt_Handler
- LDR PC, =DAbt_Handler
- NOP
- LDR PC, =IRQ_Handler
- LDR PC, =FIQ_Handler
-}
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-__ASM void Reset_Handler(void) {
-
- // Mask interrupts
- CPSID if
-
- // Put any cores other than 0 to sleep
- MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
- ANDS R0, R0, #3
-goToSleep
- WFINE
- BNE goToSleep
-
- // Reset SCTLR Settings
- MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
- BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
- BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
- BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
- BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
- BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
- MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
- ISB
-
- // Configure ACTLR
- MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
- ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
- MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
-
- // Set Vector Base Address Register (VBAR) to point to this application's vector table
- LDR R0, =Vectors
- MCR p15, 0, R0, c12, c0, 0
-
- // Setup Stack for each exceptional mode
- IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
- LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
-
- //Enter Undefined Instruction Mode and set its Stack Pointer
- CPS #UND_MODE
- MOV SP, R0
- SUB R0, R0, #__UND_STACK_SIZE
-
- // Enter Abort Mode and set its Stack Pointer
- CPS #ABT_MODE
- MOV SP, R0
- SUB R0, R0, #__ABT_STACK_SIZE
-
- // Enter FIQ Mode and set its Stack Pointer
- CPS #FIQ_MODE
- MOV SP, R0
- SUB R0, R0, #__FIQ_STACK_SIZE
-
- // Enter IRQ Mode and set its Stack Pointer
- CPS #IRQ_MODE
- MOV SP, R0
- SUB R0, R0, #__IRQ_STACK_SIZE
-
- // Enter Supervisor Mode and set its Stack Pointer
- CPS #SVC_MODE
- MOV SP, R0
- SUB R0, R0, #__SVC_STACK_SIZE
-
- // Enter System Mode to complete initialization and enter kernel
- CPS #SYS_MODE
- MOV SP, R0
-
- // Call SystemInit
- IMPORT SystemInit
- BL SystemInit
-
- // Unmask interrupts
- CPSIE if
-
- // Call __main
- IMPORT __main
- BL __main
-}
-
-/*----------------------------------------------------------------------------
- Default Handler for Exceptions / Interrupts
- *----------------------------------------------------------------------------*/
-void Default_Handler(void) {
- while(1);
-}
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S
new file mode 100644
index 0000000..7bfaa35
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S
@@ -0,0 +1,91 @@
+;/*
+; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project: CMSIS-RTOS RTX
+; * Title: Cortex-A Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+MODE_SVC EQU 0x13
+
+ PRESERVE8
+ THUMB
+
+ AREA |.text|, CODE, READONLY
+
+IRQ_Handler PROC
+ EXPORT IRQ_Handler [WEAK]
+
+ IMPORT IRQ_GetActiveIRQ
+ IMPORT IRQ_GetHandler
+ IMPORT IRQ_EndOfInterrupt
+
+ SUB LR, LR, #4 ; Pre-adjust LR
+ SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
+ CPS #MODE_SVC ; Change to SVC mode
+ PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
+
+ MOV R3, SP ; Move SP into R3
+ AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
+ SUB SP, SP, R3 ; Adjust stack
+ PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
+
+ BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
+ MOV R4, R0 ; Move interrupt ID to R4
+
+ BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
+ CMP R0, #0 ; Check if handler address is 0
+ BEQ IRQ_End ; If 0, end interrupt and return
+
+ CPSIE i ; Re-enable interrupts
+ BLX R0 ; Call IRQ handler
+ CPSID i ; Disable interrupts
+
+IRQ_End
+ MOV R0, R4 ; Move interrupt ID to R0
+ BLX IRQ_EndOfInterrupt ; Signal end of interrupt
+
+ POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
+ ADD SP, SP, R3 ; Unadjust stack
+
+ POP {R0-R3, R12, LR} ; Restore stacked APCS registers
+ RFEFD SP! ; Return from IRQ handler
+
+ ENDP
+
+
+Default_Handler PROC
+ EXPORT Undef_Handler [WEAK]
+ EXPORT SVC_Handler [WEAK]
+ EXPORT PAbt_Handler [WEAK]
+ EXPORT DAbt_Handler [WEAK]
+ EXPORT FIQ_Handler [WEAK]
+
+Undef_Handler
+SVC_Handler
+PAbt_Handler
+DAbt_Handler
+FIQ_Handler
+
+ B .
+
+ ENDP
+
+ END
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c
index f97edff..37877ad 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c
@@ -116,7 +116,7 @@
extern uint32_t Image$$TTB$$ZI$$Base;
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#elif defined( __ICCARM__ )
#else
extern uint32_t Image$$RW_DATA_NC$$Base;
@@ -127,7 +127,7 @@
extern uint32_t Image$$RO_DATA$$Limit;
extern uint32_t Image$$RW_DATA$$Limit;
extern uint32_t Image$$RW_IRAM1$$Limit;
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#else
extern uint32_t Image$$RW_DATA_NC$$Limit;
extern uint32_t Image$$ZI_DATA_NC$$Limit;
@@ -145,7 +145,7 @@
#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#else
#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
@@ -251,7 +251,7 @@
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#endif
-#if defined( __CC_ARM )
+#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#elif defined ( __ICCARM__ )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c
index ba24d29..6cca0ef 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/flash_api.c
@@ -40,7 +40,7 @@
#define STREG_BUSY_BIT (0x01u) /* SR.[0]BUSY Erase/Write In Progress (RO) */
/* Definition of the base address for the MMU translation table */
-#if defined(__CC_ARM) || defined(__GNUC__)
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
extern uint32_t Image$$TTB$$ZI$$Base;
#define TTB ((uint32_t)&Image$$TTB$$ZI$$Base) /* using linker symbol */
#elif defined(__ICCARM__)
diff --git a/targets/TARGET_RENESAS/mbed_rtx.h b/targets/TARGET_RENESAS/mbed_rtx.h
index 08336e2..203b1b1 100644
--- a/targets/TARGET_RENESAS/mbed_rtx.h
+++ b/targets/TARGET_RENESAS/mbed_rtx.h
@@ -18,7 +18,7 @@
#include
-#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE)
+#if defined(TARGET_RENESAS)
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$ARM_LIB_STACK$$Base[];
@@ -34,6 +34,7 @@
#else
#error "no toolchain defined"
#endif
+
#endif
#endif // MBED_MBED_RTX_H