diff --git a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt
index 1ad0fa7..e2e2278 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt
+++ b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt
@@ -1,13 +1,23 @@
 # Copyright (c) 2020 ARM Limited. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
+add_subdirectory(TARGET_STM32WL54xC EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32WL55xC EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32WLE4x8 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32WLE4xB EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32WLE4xC EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32WLE5x8 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_STM32WLE5xB EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_STM32WLE5xC EXCLUDE_FROM_ALL)
-
 add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL)
 
 add_library(mbed-stm32wl INTERFACE)
 
+target_include_directories(mbed-stm32wl
+    INTERFACE
+        .
+)
+
 target_sources(mbed-stm32wl
     INTERFACE
         analogin_device.c
@@ -21,9 +31,5 @@
         system_clock.c
 )
 
-target_include_directories(mbed-stm32wl
-    INTERFACE
-        .
-)
 
 target_link_libraries(mbed-stm32wl INTERFACE mbed-stm mbed-stm32wlcube-fw)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/License.md b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/License.md
new file mode 100644
index 0000000..c6b7c8b
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/License.md
@@ -0,0 +1,3 @@
+# Copyright (c) 2020 STMicroelectronics
+
+This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
\ No newline at end of file
diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h
index 82170f1..d10d8aa 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/stm32wlxx_hal_conf.h
@@ -69,25 +69,63 @@
 /**
   * @brief This is the list of modules where register callback can be used
   */
+#if !defined  (USE_HAL_ADC_REGISTER_CALLBACKS)
 #define USE_HAL_ADC_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_COMP_REGISTER_CALLBACKS)
 #define USE_HAL_COMP_REGISTER_CALLBACKS        0u
+#endif
+#if !defined  (USE_HAL_CRYP_REGISTER_CALLBACKS)
 #define USE_HAL_CRYP_REGISTER_CALLBACKS        0u
+#endif
+#if !defined  (USE_HAL_DAC_REGISTER_CALLBACKS)
 #define USE_HAL_DAC_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_I2C_REGISTER_CALLBACKS)
 #define USE_HAL_I2C_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_I2S_REGISTER_CALLBACKS)
 #define USE_HAL_I2S_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_IRDA_REGISTER_CALLBACKS)
 #define USE_HAL_IRDA_REGISTER_CALLBACKS        0u
+#endif
+#if !defined  (USE_HAL_LPTIM_REGISTER_CALLBACKS)
 #define USE_HAL_LPTIM_REGISTER_CALLBACKS       0u
+#endif
+#if !defined  (USE_HAL_PKA_REGISTER_CALLBACKS)
 #define USE_HAL_PKA_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_RNG_REGISTER_CALLBACKS)
 #define USE_HAL_RNG_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_RTC_REGISTER_CALLBACKS)
 #define USE_HAL_RTC_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_SMARTCARD_REGISTER_CALLBACKS)
 #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0u
+#endif
+#if !defined  (USE_HAL_SMBUS_REGISTER_CALLBACKS)
 #define USE_HAL_SMBUS_REGISTER_CALLBACKS       0u
+#endif
+#if !defined  (USE_HAL_SPI_REGISTER_CALLBACKS)
 #define USE_HAL_SPI_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_SUBGHZ_REGISTER_CALLBACKS)
 #define USE_HAL_SUBGHZ_REGISTER_CALLBACKS      0u
+#endif
+#if !defined  (USE_HAL_TIM_REGISTER_CALLBACKS)
 #define USE_HAL_TIM_REGISTER_CALLBACKS         0u
+#endif
+#if !defined  (USE_HAL_UART_REGISTER_CALLBACKS)
 #define USE_HAL_UART_REGISTER_CALLBACKS        0u
+#endif
+#if !defined  (USE_HAL_USART_REGISTER_CALLBACKS)
 #define USE_HAL_USART_REGISTER_CALLBACKS       0u
+#endif
+#if !defined  (USE_HAL_WWDG_REGISTER_CALLBACKS)
 #define USE_HAL_WWDG_REGISTER_CALLBACKS        0u
+#endif
 
 /* ########################## Oscillator Values adaptation ####################*/
 /**
@@ -183,7 +221,9 @@
 
 /* ################## CRYP peripheral configuration ########################## */
 
+#if !defined  (USE_HAL_CRYP_SUSPEND_RESUME)
 #define USE_HAL_CRYP_SUSPEND_RESUME         1U
+#endif
 
 
 /* Includes ------------------------------------------------------------------*/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c
index 0613417..5cf561e 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c
+++ b/targets/TARGET_STM/TARGET_STM32WL/STM32Cube_FW/system_stm32wlxx.c
@@ -138,8 +138,7 @@
 #define VECT_TAB_OFFSET         0x00008000U     /*!< Vector Table base offset field.
                                                      This value must be a multiple of 0x100. */
 #else
-#include "nvic_addr.h"                   // MBED
-  SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
                                                      This value must be a multiple of 0x100. */
 #define VECT_TAB_OFFSET         0x00020000U        /*!< Vector Table base offset field.
                                                      This value must be a multiple of 0x100. */
@@ -154,8 +153,7 @@
 #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
                                                      This value must be a multiple of 0x200. */
 #else
-#include "nvic_addr.h"                   // MBED
-  SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED
+#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
                                                      This value must be a multiple of 0x200. */
 #define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
                                                      This value must be a multiple of 0x200. */
@@ -211,11 +209,12 @@
   * @param  None
   * @retval None
   */
-void SystemInit(void)
+__WEAK void SystemInit(void)
 {
+#include "nvic_addr.h"                   // MBED
+  SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED
 #if defined(USER_VECT_TAB_ADDRESS)
   /* Configure the Vector Table location add offset address ------------------*/
-  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
 #endif
 
   /* FPU settings ------------------------------------------------------------*/
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/CMakeLists.txt
new file mode 100644
index 0000000..2afb1eb
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wl54xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wl54xc.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wl54xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32wl54xc.sct)
+endif()
+
+add_library(mbed-stm32wl54xc INTERFACE)
+
+target_include_directories(mbed-stm32wl54xc
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32wl54xc
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32wl54xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32wl54xc INTERFACE mbed-stm32wl)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/TOOLCHAIN_ARM/stm32wl54xc.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h
index a18342e..dd7de71 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL54xC/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x0  // 0 B
+#define MBED_ROM_SIZE  0x40000  // 256 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x0  // 0 B
+#define MBED_RAM_SIZE  0x10000  // 64 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TOOLCHAIN_ARM/stm32wl55xc.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h
index c5ec327..dd7de71 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x40000
+#define MBED_ROM_SIZE  0x40000  // 256 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x10000
+#define MBED_RAM_SIZE  0x10000  // 64 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/CMakeLists.txt
new file mode 100644
index 0000000..31a63cf
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle4x8.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle4xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32wle4x8.sct)
+endif()
+
+add_library(mbed-stm32wle4x8 INTERFACE)
+
+target_include_directories(mbed-stm32wle4x8
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32wle4x8
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32wle4x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32wle4x8 INTERFACE mbed-stm32wl)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/TOOLCHAIN_ARM/stm32wle4x8.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h
index a18342e..9407c41 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4x8/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x0  // 0 B
+#define MBED_ROM_SIZE  0x10000  // 64 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x0  // 0 B
+#define MBED_RAM_SIZE  0x5000  // 20 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/CMakeLists.txt
new file mode 100644
index 0000000..dd127f4
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle4xb.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle4xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32wle4xb.sct)
+endif()
+
+add_library(mbed-stm32wle4xb INTERFACE)
+
+target_include_directories(mbed-stm32wle4xb
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32wle4xb
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32wle4xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32wle4xb INTERFACE mbed-stm32wl)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/TOOLCHAIN_ARM/stm32wle4xb.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h
index a18342e..7f3b390 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xB/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x0  // 0 B
+#define MBED_ROM_SIZE  0x20000  // 128 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x0  // 0 B
+#define MBED_RAM_SIZE  0xC000  // 48 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/CMakeLists.txt
new file mode 100644
index 0000000..1388309
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle4xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle4xc.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle4xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32wle4xc.sct)
+endif()
+
+add_library(mbed-stm32wle4xc INTERFACE)
+
+target_include_directories(mbed-stm32wle4xc
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32wle4xc
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32wle4xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32wle4xc INTERFACE mbed-stm32wl)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/TOOLCHAIN_ARM/stm32wle4xc.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h
index a18342e..dd7de71 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE4xC/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x0  // 0 B
+#define MBED_ROM_SIZE  0x40000  // 256 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x0  // 0 B
+#define MBED_RAM_SIZE  0x10000  // 64 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/CMakeLists.txt
new file mode 100644
index 0000000..b3aafa5
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle5x8.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle5xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32wle5x8.sct)
+endif()
+
+add_library(mbed-stm32wle5x8 INTERFACE)
+
+target_include_directories(mbed-stm32wle5x8
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32wle5x8
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32wle5x8 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32wle5x8 INTERFACE mbed-stm32wl)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/TOOLCHAIN_ARM/stm32wle5x8.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h
index a18342e..9407c41 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5x8/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x0  // 0 B
+#define MBED_ROM_SIZE  0x10000  // 64 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x0  // 0 B
+#define MBED_RAM_SIZE  0x5000  // 20 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/CMakeLists.txt
new file mode 100644
index 0000000..4009192
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2020 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wle5xx.S)
+    set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wle5xb.ld)
+elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
+    set(STARTUP_FILE TOOLCHAIN_ARM/startup_stm32wle5xx.S)
+    set(LINKER_FILE TOOLCHAIN_ARM/stm32wle5xb.sct)
+endif()
+
+add_library(mbed-stm32wle5xb INTERFACE)
+
+target_include_directories(mbed-stm32wle5xb
+    INTERFACE
+        .
+)
+
+target_sources(mbed-stm32wle5xb
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
+mbed_set_linker_script(mbed-stm32wle5xb ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
+
+target_link_libraries(mbed-stm32wle5xb INTERFACE mbed-stm32wl)
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/TOOLCHAIN_ARM/stm32wle5xb.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h
index a18342e..7f3b390 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xB/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x0  // 0 B
+#define MBED_ROM_SIZE  0x20000  // 128 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x0  // 0 B
+#define MBED_RAM_SIZE  0xC000  // 48 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt
index e080aaf..2faf76b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/CMakeLists.txt
@@ -11,16 +11,16 @@
 
 add_library(mbed-stm32wle5xc INTERFACE)
 
-target_sources(mbed-stm32wle5xc
-    INTERFACE
-        ${STARTUP_FILE}
-)
-
 target_include_directories(mbed-stm32wle5xc
     INTERFACE
         .
 )
 
+target_sources(mbed-stm32wle5xc
+    INTERFACE
+        ${STARTUP_FILE}
+)
+
 mbed_set_linker_script(mbed-stm32wle5xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})
 
 target_link_libraries(mbed-stm32wle5xc INTERFACE mbed-stm32wl)
\ No newline at end of file
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct
index 9258e6a..7aff08b 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/TOOLCHAIN_ARM/stm32wle5xc.sct
@@ -1,4 +1,4 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-M4
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
 ; Scatter-Loading Description File
 ;
 ; SPDX-License-Identifier: BSD-3-Clause
diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h
index a18342e..dd7de71 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h
+++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WLE5xC/cmsis_nvic.h
@@ -22,7 +22,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-#define MBED_ROM_SIZE  0x0  // 0 B
+#define MBED_ROM_SIZE  0x40000  // 256 KB
 #endif
 
 #if !defined(MBED_RAM_START)
@@ -30,7 +30,7 @@
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-#define MBED_RAM_SIZE  0x0  // 0 B
+#define MBED_RAM_SIZE  0x10000  // 64 KB
 #endif
 
 #define NVIC_NUM_VECTORS        78